arch/x86/kernel/process.c

   1 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   2
   3 #include <linux/errno.h>
   4 #include <linux/kernel.h>
   5 #include <linux/mm.h>
   6 #include <linux/smp.h>
   7 #include <linux/prctl.h>
   8 #include <linux/slab.h>
   9 #include <linux/sched.h>
  10 #include <linux/module.h>
  11 #include <linux/pm.h>
  12 #include <linux/clockchips.h>
  13 #include <linux/random.h>
  14 #include <linux/user-return-notifier.h>
  15 #include <linux/dmi.h>
  16 #include <linux/utsname.h>
  17 #include <linux/stackprotector.h>
  18 #include <linux/tick.h>
  19 #include <linux/cpuidle.h>
  20 #include <trace/events/power.h>
  21 #include <linux/hw_breakpoint.h>
  22 #include <asm/cpu.h>
  23 #include <asm/apic.h>
  24 #include <asm/syscalls.h>
  25 #include <asm/idle.h>
  26 #include <asm/uaccess.h>
  27 #include <asm/i387.h>
  28 #include <asm/fpu-internal.h>
  29 #include <asm/debugreg.h>
  30 #include <asm/nmi.h>
  31
  32 /*
  33  * per-CPU TSS segments. Threads are completely 'soft' on Linux,
  34  * no more per-task TSS's. The TSS size is kept cacheline-aligned
  35  * so they are allowed to end up in the .data..cacheline_aligned
  36  * section. Since TSS's are completely CPU-local, we want them
  37  * on exact cacheline boundaries, to eliminate cacheline ping-pong.
  38  */
  39 DEFINE_PER_CPU_SHARED_ALIGNED(struct tss_struct, init_tss) = INIT_TSS;
  40
  41 #ifdef CONFIG_X86_64
  42 static DEFINE_PER_CPU(unsigned char, is_idle);
  43 static ATOMIC_NOTIFIER_HEAD(idle_notifier);
  44
  45 void idle_notifier_register(struct notifier_block *n)
  46 {
  47         atomic_notifier_chain_register(&idle_notifier, n);
  48 }
  49 EXPORT_SYMBOL_GPL(idle_notifier_register);
  50
  51 void idle_notifier_unregister(struct notifier_block *n)
  52 {
  53         atomic_notifier_chain_unregister(&idle_notifier, n);
  54 }
  55 EXPORT_SYMBOL_GPL(idle_notifier_unregister);
  56 #endif
  57
  58 struct kmem_cache *task_xstate_cachep;
  59 EXPORT_SYMBOL_GPL(task_xstate_cachep);
  60
  61 /*
  62  * this gets called so that we can store lazy state into memory and copy the
  63  * current task into the new thread.
  64  */
  65 int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src)
  66 {
  67         int ret;
  68
  69         *dst = *src;
  70         if (fpu_allocated(&src->thread.fpu)) {
  71                 memset(&dst->thread.fpu, 0, sizeof(dst->thread.fpu));
  72                 ret = fpu_alloc(&dst->thread.fpu);
  73                 if (ret)
  74                         return ret;
  75                 fpu_copy(dst, src);
  76         }
  77         return 0;
  78 }
  79
  80 void free_thread_xstate(struct task_struct *tsk)
  81 {
  82         fpu_free(&tsk->thread.fpu);
  83 }
  84
  85 void arch_release_task_struct(struct task_struct *tsk)
  86 {
  87         free_thread_xstate(tsk);
  88 }
  89
  90 void arch_task_cache_init(void)
  91 {
  92         task_xstate_cachep =
  93                 kmem_cache_create("task_xstate", xstate_size,
  94                                   __alignof__(union thread_xstate),
  95                                   SLAB_PANIC | SLAB_NOTRACK, NULL);
  96 }
  97
  98 /*
  99  * Free current thread data structures etc..
 100  */
 101 void exit_thread(void)
 102 {
 103         struct task_struct *me = current;
 104         struct thread_struct *t = &me->thread;
 105         unsigned long *bp = t->io_bitmap_ptr;
 106
 107         if (bp) {
 108                 struct tss_struct *tss = &per_cpu(init_tss, get_cpu());
 109
 110                 t->io_bitmap_ptr = NULL;
 111                 clear_thread_flag(TIF_IO_BITMAP);
 112                 /*
 113                  * Careful, clear this in the TSS too:
 114                  */
 115                 memset(tss->io_bitmap, 0xff, t->io_bitmap_max);
 116                 t->io_bitmap_max = 0;
 117                 put_cpu();
 118                 kfree(bp);
 119         }
 120
 121         drop_fpu(me);
 122 }
 123
 124 void show_regs_common(void)
 125 {
 126         const char *vendor, *product, *board;
 127
 128         vendor = dmi_get_system_info(DMI_SYS_VENDOR);
 129         if (!vendor)
 130                 vendor = "";
 131         product = dmi_get_system_info(DMI_PRODUCT_NAME);
 132         if (!product)
 133                 product = "";
 134
 135         /* Board Name is optional */
 136         board = dmi_get_system_info(DMI_BOARD_NAME);
 137
 138         printk(KERN_DEFAULT "Pid: %d, comm: %.20s %s %s %.*s %s %s%s%s\n",
 139                current->pid, current->comm, print_tainted(),
 140                init_utsname()->release,
 141                (int)strcspn(init_utsname()->version, " "),
 142                init_utsname()->version,
 143                vendor, product,
 144                board ? "/" : "",
 145                board ? board : "");
 146 }
 147
 148 void flush_thread(void)
 149 {
 150         struct task_struct *tsk = current;
 151
 152         flush_ptrace_hw_breakpoint(tsk);
 153         memset(tsk->thread.tls_array, 0, sizeof(tsk->thread.tls_array));
 154         drop_init_fpu(tsk);
 155         /*
 156          * Free the FPU state for non xsave platforms. They get reallocated
 157          * lazily at the first use.
 158          */
 159         if (!use_eager_fpu())
 160                 free_thread_xstate(tsk);
 161 }
 162
 163 static void hard_disable_TSC(void)
 164 {
 165         write_cr4(read_cr4() | X86_CR4_TSD);
 166 }
 167
 168 void disable_TSC(void)
 169 {
 170         preempt_disable();
 171         if (!test_and_set_thread_flag(TIF_NOTSC))
 172                 /*
 173                  * Must flip the CPU state synchronously with
 174                  * TIF_NOTSC in the current running context.
 175                  */
 176                 hard_disable_TSC();
 177         preempt_enable();
 178 }
 179
 180 static void hard_enable_TSC(void)
 181 {
 182         write_cr4(read_cr4() & ~X86_CR4_TSD);
 183 }
 184
 185 static void enable_TSC(void)
 186 {
 187         preempt_disable();
 188         if (test_and_clear_thread_flag(TIF_NOTSC))
 189                 /*
 190                  * Must flip the CPU state synchronously with
 191                  * TIF_NOTSC in the current running context.
 192                  */
 193                 hard_enable_TSC();
 194         preempt_enable();
 195 }
 196
 197 int get_tsc_mode(unsigned long adr)
 198 {
 199         unsigned int val;
 200
 201         if (test_thread_flag(TIF_NOTSC))
 202                 val = PR_TSC_SIGSEGV;
 203         else
 204                 val = PR_TSC_ENABLE;
 205
 206         return put_user(val, (unsigned int __user *)adr);
 207 }
 208
 209 int set_tsc_mode(unsigned int val)
 210 {
 211         if (val == PR_TSC_SIGSEGV)
 212                 disable_TSC();
 213         else if (val == PR_TSC_ENABLE)
 214                 enable_TSC();
 215         else
 216                 return -EINVAL;
 217
 218         return 0;
 219 }
 220
 221 void __switch_to_xtra(struct task_struct *prev_p, struct task_struct *next_p,
 222                       struct tss_struct *tss)
 223 {
 224         struct thread_struct *prev, *next;
 225
 226         prev = &prev_p->thread;
 227         next = &next_p->thread;
 228
 229         if (test_tsk_thread_flag(prev_p, TIF_BLOCKSTEP) ^
 230             test_tsk_thread_flag(next_p, TIF_BLOCKSTEP)) {
 231                 unsigned long debugctl = get_debugctlmsr();
 232
 233                 debugctl &= ~DEBUGCTLMSR_BTF;
 234                 if (test_tsk_thread_flag(next_p, TIF_BLOCKSTEP))
 235                         debugctl |= DEBUGCTLMSR_BTF;
 236
 237                 update_debugctlmsr(debugctl);
 238         }
 239
 240         if (test_tsk_thread_flag(prev_p, TIF_NOTSC) ^
 241             test_tsk_thread_flag(next_p, TIF_NOTSC)) {
 242                 /* prev and next are different */
 243                 if (test_tsk_thread_flag(next_p, TIF_NOTSC))
 244                         hard_disable_TSC();
 245                 else
 246                         hard_enable_TSC();
 247         }
 248
 249         if (test_tsk_thread_flag(next_p, TIF_IO_BITMAP)) {
 250                 /*
 251                  * Copy the relevant range of the IO bitmap.
 252                  * Normally this is 128 bytes or less:
 253                  */
 254                 memcpy(tss->io_bitmap, next->io_bitmap_ptr,
 255                        max(prev->io_bitmap_max, next->io_bitmap_max));
 256         } else if (test_tsk_thread_flag(prev_p, TIF_IO_BITMAP)) {
 257                 /*
 258                  * Clear any possible leftover bits:
 259                  */
 260                 memset(tss->io_bitmap, 0xff, prev->io_bitmap_max);
 261         }
 262         propagate_user_return_notify(prev_p, next_p);
 263 }
 264
 265 /*
 266  * Idle related variables and functions
 267  */
 268 unsigned long boot_option_idle_override = IDLE_NO_OVERRIDE;
 269 EXPORT_SYMBOL(boot_option_idle_override);
 270
 271 static void (*x86_idle)(void);
 272
 273 #ifndef CONFIG_SMP
 274 static inline void play_dead(void)
 275 {
 276         BUG();
 277 }
 278 #endif
 279
 280 #ifdef CONFIG_X86_64
 281 void enter_idle(void)
 282 {
 283         this_cpu_write(is_idle, 1);
 284         atomic_notifier_call_chain(&idle_notifier, IDLE_START, NULL);
 285 }
 286
 287 static void __exit_idle(void)
 288 {
 289         if (x86_test_and_clear_bit_percpu(0, is_idle) == 0)
 290                 return;
 291         atomic_notifier_call_chain(&idle_notifier, IDLE_END, NULL);
 292 }
 293
 294 /* Called from interrupts to signify idle end */
 295 void exit_idle(void)
 296 {
 297         /* idle loop has pid 0 */
 298         if (current->pid)
 299                 return;
 300         __exit_idle();
 301 }
 302 #endif
 303
 304 void arch_cpu_idle_prepare(void)
 305 {
 306         /*
 307          * If we're the non-boot CPU, nothing set the stack canary up
 308          * for us.  CPU0 already has it initialized but no harm in
 309          * doing it again.  This is a good place for updating it, as
 310          * we wont ever return from this function (so the invalid
 311          * canaries already on the stack wont ever trigger).
 312          */
 313         boot_init_stack_canary();
 314 }
 315
 316 void arch_cpu_idle_enter(void)
 317 {
 318         local_touch_nmi();
 319         enter_idle();
 320 }
 321
 322 void arch_cpu_idle_exit(void)
 323 {
 324         __exit_idle();
 325 }
 326
 327 void arch_cpu_idle_dead(void)
 328 {
 329         play_dead();
 330 }
 331
 332 /*
 333  * Called from the generic idle code.
 334  */
 335 void arch_cpu_idle(void)
 336 {
 337         if (cpuidle_idle_call())
 338                 x86_idle();
 339 }
 340
 341 /*
 342  * We use this if we don't have any better idle routine..
 343  */
 344 void default_idle(void)
 345 {
 346         trace_cpu_idle_rcuidle(1, smp_processor_id());
 347         safe_halt();
 348         trace_cpu_idle_rcuidle(PWR_EVENT_EXIT, smp_processor_id());
 349 }
 350 #ifdef CONFIG_APM_MODULE
 351 EXPORT_SYMBOL(default_idle);
 352 #endif
 353
 354 #ifdef CONFIG_XEN
 355 bool xen_set_default_idle(void)
 356 {
 357         bool ret = !!x86_idle;
 358
 359         x86_idle = default_idle;
 360
 361         return ret;
 362 }
 363 #endif
 364 void stop_this_cpu(void *dummy)
 365 {
 366         local_irq_disable();
 367         /*
 368          * Remove this CPU:
 369          */
 370         set_cpu_online(smp_processor_id(), false);
 371         disable_local_APIC();
 372
 373         for (;;)
 374                 halt();
 375 }
 376
 377 bool amd_e400_c1e_detected;
 378 EXPORT_SYMBOL(amd_e400_c1e_detected);
 379
 380 static cpumask_var_t amd_e400_c1e_mask;
 381
 382 void amd_e400_remove_cpu(int cpu)
 383 {
 384         if (amd_e400_c1e_mask != NULL)
 385                 cpumask_clear_cpu(cpu, amd_e400_c1e_mask);
 386 }
 387
 388 /*
 389  * AMD Erratum 400 aware idle routine. We check for C1E active in the interrupt
 390  * pending message MSR. If we detect C1E, then we handle it the same
 391  * way as C3 power states (local apic timer and TSC stop)
 392  */
 393 static void amd_e400_idle(void)
 394 {
 395         if (need_resched())
 396                 return;
 397
 398         if (!amd_e400_c1e_detected) {
 399                 u32 lo, hi;
 400
 401                 rdmsr(MSR_K8_INT_PENDING_MSG, lo, hi);
 402
 403                 if (lo & K8_INTP_C1E_ACTIVE_MASK) {
 404                         amd_e400_c1e_detected = true;
 405                         if (!boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
 406                                 mark_tsc_unstable("TSC halt in AMD C1E");
 407                         pr_info("System has AMD C1E enabled\n");
 408                 }
 409         }
 410
 411         if (amd_e400_c1e_detected) {
 412                 int cpu = smp_processor_id();
 413
 414                 if (!cpumask_test_cpu(cpu, amd_e400_c1e_mask)) {
 415                         cpumask_set_cpu(cpu, amd_e400_c1e_mask);
 416                         /*
 417                          * Force broadcast so ACPI can not interfere.
 418                          */
 419                         clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_FORCE,
 420                                            &cpu);
 421                         pr_info("Switch to broadcast mode on CPU%d\n", cpu);
 422                 }
 423                 clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_ENTER, &cpu);
 424
 425                 default_idle();
 426
 427                 /*
 428                  * The switch back from broadcast mode needs to be
 429                  * called with interrupts disabled.
 430                  */
 431                  local_irq_disable();
 432                  clockevents_notify(CLOCK_EVT_NOTIFY_BROADCAST_EXIT, &cpu);
 433                  local_irq_enable();
 434         } else
 435                 default_idle();
 436 }
 437
 438 void __cpuinit select_idle_routine(const struct cpuinfo_x86 *c)
 439 {
 440 #ifdef CONFIG_SMP
 441         if (boot_option_idle_override == IDLE_POLL && smp_num_siblings > 1)
 442                 pr_warn_once("WARNING: polling idle and HT enabled, performance may degrade\n");
 443 #endif
 444         if (x86_idle || boot_option_idle_override == IDLE_POLL)
 445                 return;
 446
 447         if (cpu_has_amd_erratum(amd_erratum_400)) {
 448                 /* E400: APIC timer interrupt does not wake up CPU from C1e */
 449                 pr_info("using AMD E400 aware idle routine\n");
 450                 x86_idle = amd_e400_idle;
 451         } else
 452                 x86_idle = default_idle;
 453 }
 454
 455 void __init init_amd_e400_c1e_mask(void)
 456 {
 457         /* If we're using amd_e400_idle, we need to allocate amd_e400_c1e_mask. */
 458         if (x86_idle == amd_e400_idle)
 459                 zalloc_cpumask_var(&amd_e400_c1e_mask, GFP_KERNEL);
 460 }
 461
 462 static int __init idle_setup(char *str)
 463 {
 464         if (!str)
 465                 return -EINVAL;
 466
 467         if (!strcmp(str, "poll")) {
 468                 pr_info("using polling idle threads\n");
 469                 boot_option_idle_override = IDLE_POLL;
 470                 cpu_idle_poll_ctrl(true);
 471         } else if (!strcmp(str, "halt")) {
 472                 /*
 473                  * When the boot option of idle=halt is added, halt is
 474                  * forced to be used for CPU idle. In such case CPU C2/C3
 475                  * won't be used again.
 476                  * To continue to load the CPU idle driver, don't touch
 477                  * the boot_option_idle_override.
 478                  */
 479                 x86_idle = default_idle;
 480                 boot_option_idle_override = IDLE_HALT;
 481         } else if (!strcmp(str, "nomwait")) {
 482                 /*
 483                  * If the boot option of "idle=nomwait" is added,
 484                  * it means that mwait will be disabled for CPU C2/C3
 485                  * states. In such case it won't touch the variable
 486                  * of boot_option_idle_override.
 487                  */
 488                 boot_option_idle_override = IDLE_NOMWAIT;
 489         } else
 490                 return -1;
 491
 492         return 0;
 493 }
 494 early_param("idle", idle_setup);
 495
 496 unsigned long arch_align_stack(unsigned long sp)
 497 {
 498         if (!(current->personality & ADDR_NO_RANDOMIZE) && randomize_va_space)
 499                 sp -= get_random_int() % 8192;
 500         return sp & ~0xf;
 501 }
 502
 503 unsigned long arch_randomize_brk(struct mm_struct *mm)
 504 {
 505         unsigned long range_end = mm->brk + 0x02000000;
 506         return randomize_range(mm->brk, range_end, 0) ? : mm->brk;
 507 }
 508