2 * Copyright © 2012 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
28 #include <linux/cpufreq.h>
30 #include "intel_drv.h"
31 #include "../../../platform/x86/intel_ips.h"
32 #include <linux/module.h>
33 #include <linux/vgaarb.h>
34 #include <drm/i915_powerwell.h>
35 #include <linux/pm_runtime.h>
38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
54 #define INTEL_RC6_ENABLE (1<<0)
55 #define INTEL_RC6p_ENABLE (1<<1)
56 #define INTEL_RC6pp_ENABLE (1<<2)
58 /* FBC, or Frame Buffer Compression, is a technique employed to compress the
59 * framebuffer contents in-memory, aiming at reducing the required bandwidth
60 * during in-memory transfers and, therefore, reduce the power packet.
62 * The benefits of FBC are mostly visible with solid backgrounds and
63 * variation-less patterns.
65 * FBC-related functionality can be enabled by the means of the
66 * i915.i915_enable_fbc parameter
69 static void i8xx_disable_fbc(struct drm_device
*dev
)
71 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
74 /* Disable compression */
75 fbc_ctl
= I915_READ(FBC_CONTROL
);
76 if ((fbc_ctl
& FBC_CTL_EN
) == 0)
79 fbc_ctl
&= ~FBC_CTL_EN
;
80 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
82 /* Wait for compressing bit to clear */
83 if (wait_for((I915_READ(FBC_STATUS
) & FBC_STAT_COMPRESSING
) == 0, 10)) {
84 DRM_DEBUG_KMS("FBC idle timed out\n");
88 DRM_DEBUG_KMS("disabled FBC\n");
91 static void i8xx_enable_fbc(struct drm_crtc
*crtc
)
93 struct drm_device
*dev
= crtc
->dev
;
94 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
95 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
96 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
97 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
98 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
103 cfb_pitch
= dev_priv
->fbc
.size
/ FBC_LL_SIZE
;
104 if (fb
->pitches
[0] < cfb_pitch
)
105 cfb_pitch
= fb
->pitches
[0];
107 /* FBC_CTL wants 32B or 64B units */
109 cfb_pitch
= (cfb_pitch
/ 32) - 1;
111 cfb_pitch
= (cfb_pitch
/ 64) - 1;
114 for (i
= 0; i
< (FBC_LL_SIZE
/ 32) + 1; i
++)
115 I915_WRITE(FBC_TAG
+ (i
* 4), 0);
121 fbc_ctl2
= FBC_CTL_FENCE_DBL
| FBC_CTL_IDLE_IMM
| FBC_CTL_CPU_FENCE
;
122 fbc_ctl2
|= FBC_CTL_PLANE(intel_crtc
->plane
);
123 I915_WRITE(FBC_CONTROL2
, fbc_ctl2
);
124 I915_WRITE(FBC_FENCE_OFF
, crtc
->y
);
128 fbc_ctl
= I915_READ(FBC_CONTROL
);
129 fbc_ctl
&= 0x3fff << FBC_CTL_INTERVAL_SHIFT
;
130 fbc_ctl
|= FBC_CTL_EN
| FBC_CTL_PERIODIC
;
132 fbc_ctl
|= FBC_CTL_C3_IDLE
; /* 945 needs special SR handling */
133 fbc_ctl
|= (cfb_pitch
& 0xff) << FBC_CTL_STRIDE_SHIFT
;
134 fbc_ctl
|= obj
->fence_reg
;
135 I915_WRITE(FBC_CONTROL
, fbc_ctl
);
137 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n",
138 cfb_pitch
, crtc
->y
, plane_name(intel_crtc
->plane
));
141 static bool i8xx_fbc_enabled(struct drm_device
*dev
)
143 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
145 return I915_READ(FBC_CONTROL
) & FBC_CTL_EN
;
148 static void g4x_enable_fbc(struct drm_crtc
*crtc
)
150 struct drm_device
*dev
= crtc
->dev
;
151 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
152 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
153 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
154 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
155 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
158 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
) | DPFC_SR_EN
;
159 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
160 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
162 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
163 dpfc_ctl
|= DPFC_CTL_FENCE_EN
| obj
->fence_reg
;
165 I915_WRITE(DPFC_FENCE_YOFF
, crtc
->y
);
168 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
170 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
173 static void g4x_disable_fbc(struct drm_device
*dev
)
175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
178 /* Disable compression */
179 dpfc_ctl
= I915_READ(DPFC_CONTROL
);
180 if (dpfc_ctl
& DPFC_CTL_EN
) {
181 dpfc_ctl
&= ~DPFC_CTL_EN
;
182 I915_WRITE(DPFC_CONTROL
, dpfc_ctl
);
184 DRM_DEBUG_KMS("disabled FBC\n");
188 static bool g4x_fbc_enabled(struct drm_device
*dev
)
190 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
192 return I915_READ(DPFC_CONTROL
) & DPFC_CTL_EN
;
195 static void sandybridge_blit_fbc_update(struct drm_device
*dev
)
197 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
200 /* Make sure blitter notifies FBC of writes */
202 /* Blitter is part of Media powerwell on VLV. No impact of
203 * his param in other platforms for now */
204 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_MEDIA
);
206 blt_ecoskpd
= I915_READ(GEN6_BLITTER_ECOSKPD
);
207 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
<<
208 GEN6_BLITTER_LOCK_SHIFT
;
209 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
210 blt_ecoskpd
|= GEN6_BLITTER_FBC_NOTIFY
;
211 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
212 blt_ecoskpd
&= ~(GEN6_BLITTER_FBC_NOTIFY
<<
213 GEN6_BLITTER_LOCK_SHIFT
);
214 I915_WRITE(GEN6_BLITTER_ECOSKPD
, blt_ecoskpd
);
215 POSTING_READ(GEN6_BLITTER_ECOSKPD
);
217 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_MEDIA
);
220 static void ironlake_enable_fbc(struct drm_crtc
*crtc
)
222 struct drm_device
*dev
= crtc
->dev
;
223 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
224 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
225 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
226 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
227 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
230 dpfc_ctl
= DPFC_CTL_PLANE(intel_crtc
->plane
);
231 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
232 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
234 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
235 dpfc_ctl
|= DPFC_CTL_FENCE_EN
;
237 dpfc_ctl
|= obj
->fence_reg
;
239 I915_WRITE(ILK_DPFC_FENCE_YOFF
, crtc
->y
);
240 I915_WRITE(ILK_FBC_RT_BASE
, i915_gem_obj_ggtt_offset(obj
) | ILK_FBC_RT_VALID
);
242 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
245 I915_WRITE(SNB_DPFC_CTL_SA
,
246 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
247 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
248 sandybridge_blit_fbc_update(dev
);
251 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
254 static void ironlake_disable_fbc(struct drm_device
*dev
)
256 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
259 /* Disable compression */
260 dpfc_ctl
= I915_READ(ILK_DPFC_CONTROL
);
261 if (dpfc_ctl
& DPFC_CTL_EN
) {
262 dpfc_ctl
&= ~DPFC_CTL_EN
;
263 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
);
265 DRM_DEBUG_KMS("disabled FBC\n");
269 static bool ironlake_fbc_enabled(struct drm_device
*dev
)
271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
273 return I915_READ(ILK_DPFC_CONTROL
) & DPFC_CTL_EN
;
276 static void gen7_enable_fbc(struct drm_crtc
*crtc
)
278 struct drm_device
*dev
= crtc
->dev
;
279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
280 struct drm_framebuffer
*fb
= crtc
->primary
->fb
;
281 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
282 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
283 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
286 dpfc_ctl
= IVB_DPFC_CTL_PLANE(intel_crtc
->plane
);
287 if (drm_format_plane_cpp(fb
->pixel_format
, 0) == 2)
288 dpfc_ctl
|= DPFC_CTL_LIMIT_2X
;
290 dpfc_ctl
|= DPFC_CTL_LIMIT_1X
;
291 dpfc_ctl
|= IVB_DPFC_CTL_FENCE_EN
;
293 I915_WRITE(ILK_DPFC_CONTROL
, dpfc_ctl
| DPFC_CTL_EN
);
295 if (IS_IVYBRIDGE(dev
)) {
296 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
297 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
298 I915_READ(ILK_DISPLAY_CHICKEN1
) |
301 /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */
302 I915_WRITE(CHICKEN_PIPESL_1(intel_crtc
->pipe
),
303 I915_READ(CHICKEN_PIPESL_1(intel_crtc
->pipe
)) |
307 I915_WRITE(SNB_DPFC_CTL_SA
,
308 SNB_CPU_FENCE_ENABLE
| obj
->fence_reg
);
309 I915_WRITE(DPFC_CPU_FENCE_OFFSET
, crtc
->y
);
311 sandybridge_blit_fbc_update(dev
);
313 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc
->plane
));
316 bool intel_fbc_enabled(struct drm_device
*dev
)
318 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
320 if (!dev_priv
->display
.fbc_enabled
)
323 return dev_priv
->display
.fbc_enabled(dev
);
326 static void intel_fbc_work_fn(struct work_struct
*__work
)
328 struct intel_fbc_work
*work
=
329 container_of(to_delayed_work(__work
),
330 struct intel_fbc_work
, work
);
331 struct drm_device
*dev
= work
->crtc
->dev
;
332 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
334 mutex_lock(&dev
->struct_mutex
);
335 if (work
== dev_priv
->fbc
.fbc_work
) {
336 /* Double check that we haven't switched fb without cancelling
339 if (work
->crtc
->primary
->fb
== work
->fb
) {
340 dev_priv
->display
.enable_fbc(work
->crtc
);
342 dev_priv
->fbc
.plane
= to_intel_crtc(work
->crtc
)->plane
;
343 dev_priv
->fbc
.fb_id
= work
->crtc
->primary
->fb
->base
.id
;
344 dev_priv
->fbc
.y
= work
->crtc
->y
;
347 dev_priv
->fbc
.fbc_work
= NULL
;
349 mutex_unlock(&dev
->struct_mutex
);
354 static void intel_cancel_fbc_work(struct drm_i915_private
*dev_priv
)
356 if (dev_priv
->fbc
.fbc_work
== NULL
)
359 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
361 /* Synchronisation is provided by struct_mutex and checking of
362 * dev_priv->fbc.fbc_work, so we can perform the cancellation
363 * entirely asynchronously.
365 if (cancel_delayed_work(&dev_priv
->fbc
.fbc_work
->work
))
366 /* tasklet was killed before being run, clean up */
367 kfree(dev_priv
->fbc
.fbc_work
);
369 /* Mark the work as no longer wanted so that if it does
370 * wake-up (because the work was already running and waiting
371 * for our mutex), it will discover that is no longer
374 dev_priv
->fbc
.fbc_work
= NULL
;
377 static void intel_enable_fbc(struct drm_crtc
*crtc
)
379 struct intel_fbc_work
*work
;
380 struct drm_device
*dev
= crtc
->dev
;
381 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
383 if (!dev_priv
->display
.enable_fbc
)
386 intel_cancel_fbc_work(dev_priv
);
388 work
= kzalloc(sizeof(*work
), GFP_KERNEL
);
390 DRM_ERROR("Failed to allocate FBC work structure\n");
391 dev_priv
->display
.enable_fbc(crtc
);
396 work
->fb
= crtc
->primary
->fb
;
397 INIT_DELAYED_WORK(&work
->work
, intel_fbc_work_fn
);
399 dev_priv
->fbc
.fbc_work
= work
;
401 /* Delay the actual enabling to let pageflipping cease and the
402 * display to settle before starting the compression. Note that
403 * this delay also serves a second purpose: it allows for a
404 * vblank to pass after disabling the FBC before we attempt
405 * to modify the control registers.
407 * A more complicated solution would involve tracking vblanks
408 * following the termination of the page-flipping sequence
409 * and indeed performing the enable as a co-routine and not
410 * waiting synchronously upon the vblank.
412 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
414 schedule_delayed_work(&work
->work
, msecs_to_jiffies(50));
417 void intel_disable_fbc(struct drm_device
*dev
)
419 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
421 intel_cancel_fbc_work(dev_priv
);
423 if (!dev_priv
->display
.disable_fbc
)
426 dev_priv
->display
.disable_fbc(dev
);
427 dev_priv
->fbc
.plane
= -1;
430 static bool set_no_fbc_reason(struct drm_i915_private
*dev_priv
,
431 enum no_fbc_reason reason
)
433 if (dev_priv
->fbc
.no_fbc_reason
== reason
)
436 dev_priv
->fbc
.no_fbc_reason
= reason
;
441 * intel_update_fbc - enable/disable FBC as needed
442 * @dev: the drm_device
444 * Set up the framebuffer compression hardware at mode set time. We
445 * enable it if possible:
446 * - plane A only (on pre-965)
447 * - no pixel mulitply/line duplication
448 * - no alpha buffer discard
450 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
452 * We can't assume that any compression will take place (worst case),
453 * so the compressed buffer has to be the same size as the uncompressed
454 * one. It also must reside (along with the line length buffer) in
457 * We need to enable/disable FBC on a global basis.
459 void intel_update_fbc(struct drm_device
*dev
)
461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
462 struct drm_crtc
*crtc
= NULL
, *tmp_crtc
;
463 struct intel_crtc
*intel_crtc
;
464 struct drm_framebuffer
*fb
;
465 struct intel_framebuffer
*intel_fb
;
466 struct drm_i915_gem_object
*obj
;
467 const struct drm_display_mode
*adjusted_mode
;
468 unsigned int max_width
, max_height
;
471 set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED
);
475 if (!i915
.powersave
) {
476 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
477 DRM_DEBUG_KMS("fbc disabled per module param\n");
482 * If FBC is already on, we just have to verify that we can
483 * keep it that way...
484 * Need to disable if:
485 * - more than one pipe is active
486 * - changing FBC params (stride, fence, mode)
487 * - new fb is too large to fit in compressed buffer
488 * - going to an unsupported config (interlace, pixel multiply, etc.)
490 for_each_crtc(dev
, tmp_crtc
) {
491 if (intel_crtc_active(tmp_crtc
) &&
492 to_intel_crtc(tmp_crtc
)->primary_enabled
) {
494 if (set_no_fbc_reason(dev_priv
, FBC_MULTIPLE_PIPES
))
495 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
502 if (!crtc
|| crtc
->primary
->fb
== NULL
) {
503 if (set_no_fbc_reason(dev_priv
, FBC_NO_OUTPUT
))
504 DRM_DEBUG_KMS("no output, disabling\n");
508 intel_crtc
= to_intel_crtc(crtc
);
509 fb
= crtc
->primary
->fb
;
510 intel_fb
= to_intel_framebuffer(fb
);
512 adjusted_mode
= &intel_crtc
->config
.adjusted_mode
;
514 if (i915
.enable_fbc
< 0 &&
515 INTEL_INFO(dev
)->gen
<= 7 && !IS_HASWELL(dev
)) {
516 if (set_no_fbc_reason(dev_priv
, FBC_CHIP_DEFAULT
))
517 DRM_DEBUG_KMS("disabled per chip default\n");
520 if (!i915
.enable_fbc
) {
521 if (set_no_fbc_reason(dev_priv
, FBC_MODULE_PARAM
))
522 DRM_DEBUG_KMS("fbc disabled per module param\n");
525 if ((adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) ||
526 (adjusted_mode
->flags
& DRM_MODE_FLAG_DBLSCAN
)) {
527 if (set_no_fbc_reason(dev_priv
, FBC_UNSUPPORTED_MODE
))
528 DRM_DEBUG_KMS("mode incompatible with compression, "
533 if (IS_G4X(dev
) || INTEL_INFO(dev
)->gen
>= 5) {
540 if (intel_crtc
->config
.pipe_src_w
> max_width
||
541 intel_crtc
->config
.pipe_src_h
> max_height
) {
542 if (set_no_fbc_reason(dev_priv
, FBC_MODE_TOO_LARGE
))
543 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
546 if ((INTEL_INFO(dev
)->gen
< 4 || HAS_DDI(dev
)) &&
547 intel_crtc
->plane
!= PLANE_A
) {
548 if (set_no_fbc_reason(dev_priv
, FBC_BAD_PLANE
))
549 DRM_DEBUG_KMS("plane not A, disabling compression\n");
553 /* The use of a CPU fence is mandatory in order to detect writes
554 * by the CPU to the scanout and trigger updates to the FBC.
556 if (obj
->tiling_mode
!= I915_TILING_X
||
557 obj
->fence_reg
== I915_FENCE_REG_NONE
) {
558 if (set_no_fbc_reason(dev_priv
, FBC_NOT_TILED
))
559 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
563 /* If the kernel debugger is active, always disable compression */
567 if (i915_gem_stolen_setup_compression(dev
, intel_fb
->obj
->base
.size
)) {
568 if (set_no_fbc_reason(dev_priv
, FBC_STOLEN_TOO_SMALL
))
569 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
573 /* If the scanout has not changed, don't modify the FBC settings.
574 * Note that we make the fundamental assumption that the fb->obj
575 * cannot be unpinned (and have its GTT offset and fence revoked)
576 * without first being decoupled from the scanout and FBC disabled.
578 if (dev_priv
->fbc
.plane
== intel_crtc
->plane
&&
579 dev_priv
->fbc
.fb_id
== fb
->base
.id
&&
580 dev_priv
->fbc
.y
== crtc
->y
)
583 if (intel_fbc_enabled(dev
)) {
584 /* We update FBC along two paths, after changing fb/crtc
585 * configuration (modeswitching) and after page-flipping
586 * finishes. For the latter, we know that not only did
587 * we disable the FBC at the start of the page-flip
588 * sequence, but also more than one vblank has passed.
590 * For the former case of modeswitching, it is possible
591 * to switch between two FBC valid configurations
592 * instantaneously so we do need to disable the FBC
593 * before we can modify its control registers. We also
594 * have to wait for the next vblank for that to take
595 * effect. However, since we delay enabling FBC we can
596 * assume that a vblank has passed since disabling and
597 * that we can safely alter the registers in the deferred
600 * In the scenario that we go from a valid to invalid
601 * and then back to valid FBC configuration we have
602 * no strict enforcement that a vblank occurred since
603 * disabling the FBC. However, along all current pipe
604 * disabling paths we do need to wait for a vblank at
605 * some point. And we wait before enabling FBC anyway.
607 DRM_DEBUG_KMS("disabling active FBC for update\n");
608 intel_disable_fbc(dev
);
611 intel_enable_fbc(crtc
);
612 dev_priv
->fbc
.no_fbc_reason
= FBC_OK
;
616 /* Multiple disables should be harmless */
617 if (intel_fbc_enabled(dev
)) {
618 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
619 intel_disable_fbc(dev
);
621 i915_gem_stolen_cleanup_compression(dev
);
624 static void i915_pineview_get_mem_freq(struct drm_device
*dev
)
626 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
629 tmp
= I915_READ(CLKCFG
);
631 switch (tmp
& CLKCFG_FSB_MASK
) {
633 dev_priv
->fsb_freq
= 533; /* 133*4 */
636 dev_priv
->fsb_freq
= 800; /* 200*4 */
639 dev_priv
->fsb_freq
= 667; /* 167*4 */
642 dev_priv
->fsb_freq
= 400; /* 100*4 */
646 switch (tmp
& CLKCFG_MEM_MASK
) {
648 dev_priv
->mem_freq
= 533;
651 dev_priv
->mem_freq
= 667;
654 dev_priv
->mem_freq
= 800;
658 /* detect pineview DDR3 setting */
659 tmp
= I915_READ(CSHRDDR3CTL
);
660 dev_priv
->is_ddr3
= (tmp
& CSHRDDR3CTL_DDR3
) ? 1 : 0;
663 static void i915_ironlake_get_mem_freq(struct drm_device
*dev
)
665 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
668 ddrpll
= I915_READ16(DDRMPLL1
);
669 csipll
= I915_READ16(CSIPLL0
);
671 switch (ddrpll
& 0xff) {
673 dev_priv
->mem_freq
= 800;
676 dev_priv
->mem_freq
= 1066;
679 dev_priv
->mem_freq
= 1333;
682 dev_priv
->mem_freq
= 1600;
685 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
687 dev_priv
->mem_freq
= 0;
691 dev_priv
->ips
.r_t
= dev_priv
->mem_freq
;
693 switch (csipll
& 0x3ff) {
695 dev_priv
->fsb_freq
= 3200;
698 dev_priv
->fsb_freq
= 3733;
701 dev_priv
->fsb_freq
= 4266;
704 dev_priv
->fsb_freq
= 4800;
707 dev_priv
->fsb_freq
= 5333;
710 dev_priv
->fsb_freq
= 5866;
713 dev_priv
->fsb_freq
= 6400;
716 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
718 dev_priv
->fsb_freq
= 0;
722 if (dev_priv
->fsb_freq
== 3200) {
723 dev_priv
->ips
.c_m
= 0;
724 } else if (dev_priv
->fsb_freq
> 3200 && dev_priv
->fsb_freq
<= 4800) {
725 dev_priv
->ips
.c_m
= 1;
727 dev_priv
->ips
.c_m
= 2;
731 static const struct cxsr_latency cxsr_latency_table
[] = {
732 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
733 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
734 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
735 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
736 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
738 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
739 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
740 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
741 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
742 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
744 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
745 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
746 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
747 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
748 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
750 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
751 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
752 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
753 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
754 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
756 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
757 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
758 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
759 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
760 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
762 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
763 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
764 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
765 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
766 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
769 static const struct cxsr_latency
*intel_get_cxsr_latency(int is_desktop
,
774 const struct cxsr_latency
*latency
;
777 if (fsb
== 0 || mem
== 0)
780 for (i
= 0; i
< ARRAY_SIZE(cxsr_latency_table
); i
++) {
781 latency
= &cxsr_latency_table
[i
];
782 if (is_desktop
== latency
->is_desktop
&&
783 is_ddr3
== latency
->is_ddr3
&&
784 fsb
== latency
->fsb_freq
&& mem
== latency
->mem_freq
)
788 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
793 static void pineview_disable_cxsr(struct drm_device
*dev
)
795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
797 /* deactivate cxsr */
798 I915_WRITE(DSPFW3
, I915_READ(DSPFW3
) & ~PINEVIEW_SELF_REFRESH_EN
);
802 * Latency for FIFO fetches is dependent on several factors:
803 * - memory configuration (speed, channels)
805 * - current MCH state
806 * It can be fairly high in some situations, so here we assume a fairly
807 * pessimal value. It's a tradeoff between extra memory fetches (if we
808 * set this value too high, the FIFO will fetch frequently to stay full)
809 * and power consumption (set it too low to save power and we might see
810 * FIFO underruns and display "flicker").
812 * A value of 5us seems to be a good balance; safe for very low end
813 * platforms but not overly aggressive on lower latency configs.
815 static const int latency_ns
= 5000;
817 static int i9xx_get_fifo_size(struct drm_device
*dev
, int plane
)
819 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
820 uint32_t dsparb
= I915_READ(DSPARB
);
823 size
= dsparb
& 0x7f;
825 size
= ((dsparb
>> DSPARB_CSTART_SHIFT
) & 0x7f) - size
;
827 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
828 plane
? "B" : "A", size
);
833 static int i830_get_fifo_size(struct drm_device
*dev
, int plane
)
835 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
836 uint32_t dsparb
= I915_READ(DSPARB
);
839 size
= dsparb
& 0x1ff;
841 size
= ((dsparb
>> DSPARB_BEND_SHIFT
) & 0x1ff) - size
;
842 size
>>= 1; /* Convert to cachelines */
844 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
845 plane
? "B" : "A", size
);
850 static int i845_get_fifo_size(struct drm_device
*dev
, int plane
)
852 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
853 uint32_t dsparb
= I915_READ(DSPARB
);
856 size
= dsparb
& 0x7f;
857 size
>>= 2; /* Convert to cachelines */
859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb
,
866 /* Pineview has different values for various configs */
867 static const struct intel_watermark_params pineview_display_wm
= {
868 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
869 .max_wm
= PINEVIEW_MAX_WM
,
870 .default_wm
= PINEVIEW_DFT_WM
,
871 .guard_size
= PINEVIEW_GUARD_WM
,
872 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
874 static const struct intel_watermark_params pineview_display_hplloff_wm
= {
875 .fifo_size
= PINEVIEW_DISPLAY_FIFO
,
876 .max_wm
= PINEVIEW_MAX_WM
,
877 .default_wm
= PINEVIEW_DFT_HPLLOFF_WM
,
878 .guard_size
= PINEVIEW_GUARD_WM
,
879 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
881 static const struct intel_watermark_params pineview_cursor_wm
= {
882 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
883 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
884 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
885 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
886 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
888 static const struct intel_watermark_params pineview_cursor_hplloff_wm
= {
889 .fifo_size
= PINEVIEW_CURSOR_FIFO
,
890 .max_wm
= PINEVIEW_CURSOR_MAX_WM
,
891 .default_wm
= PINEVIEW_CURSOR_DFT_WM
,
892 .guard_size
= PINEVIEW_CURSOR_GUARD_WM
,
893 .cacheline_size
= PINEVIEW_FIFO_LINE_SIZE
,
895 static const struct intel_watermark_params g4x_wm_info
= {
896 .fifo_size
= G4X_FIFO_SIZE
,
897 .max_wm
= G4X_MAX_WM
,
898 .default_wm
= G4X_MAX_WM
,
900 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
902 static const struct intel_watermark_params g4x_cursor_wm_info
= {
903 .fifo_size
= I965_CURSOR_FIFO
,
904 .max_wm
= I965_CURSOR_MAX_WM
,
905 .default_wm
= I965_CURSOR_DFT_WM
,
907 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
909 static const struct intel_watermark_params valleyview_wm_info
= {
910 .fifo_size
= VALLEYVIEW_FIFO_SIZE
,
911 .max_wm
= VALLEYVIEW_MAX_WM
,
912 .default_wm
= VALLEYVIEW_MAX_WM
,
914 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
916 static const struct intel_watermark_params valleyview_cursor_wm_info
= {
917 .fifo_size
= I965_CURSOR_FIFO
,
918 .max_wm
= VALLEYVIEW_CURSOR_MAX_WM
,
919 .default_wm
= I965_CURSOR_DFT_WM
,
921 .cacheline_size
= G4X_FIFO_LINE_SIZE
,
923 static const struct intel_watermark_params i965_cursor_wm_info
= {
924 .fifo_size
= I965_CURSOR_FIFO
,
925 .max_wm
= I965_CURSOR_MAX_WM
,
926 .default_wm
= I965_CURSOR_DFT_WM
,
928 .cacheline_size
= I915_FIFO_LINE_SIZE
,
930 static const struct intel_watermark_params i945_wm_info
= {
931 .fifo_size
= I945_FIFO_SIZE
,
932 .max_wm
= I915_MAX_WM
,
935 .cacheline_size
= I915_FIFO_LINE_SIZE
,
937 static const struct intel_watermark_params i915_wm_info
= {
938 .fifo_size
= I915_FIFO_SIZE
,
939 .max_wm
= I915_MAX_WM
,
942 .cacheline_size
= I915_FIFO_LINE_SIZE
,
944 static const struct intel_watermark_params i830_wm_info
= {
945 .fifo_size
= I855GM_FIFO_SIZE
,
946 .max_wm
= I915_MAX_WM
,
949 .cacheline_size
= I830_FIFO_LINE_SIZE
,
951 static const struct intel_watermark_params i845_wm_info
= {
952 .fifo_size
= I830_FIFO_SIZE
,
953 .max_wm
= I915_MAX_WM
,
956 .cacheline_size
= I830_FIFO_LINE_SIZE
,
960 * intel_calculate_wm - calculate watermark level
961 * @clock_in_khz: pixel clock
962 * @wm: chip FIFO params
963 * @pixel_size: display pixel size
964 * @latency_ns: memory latency for the platform
966 * Calculate the watermark level (the level at which the display plane will
967 * start fetching from memory again). Each chip has a different display
968 * FIFO size and allocation, so the caller needs to figure that out and pass
969 * in the correct intel_watermark_params structure.
971 * As the pixel clock runs, the FIFO will be drained at a rate that depends
972 * on the pixel size. When it reaches the watermark level, it'll start
973 * fetching FIFO line sized based chunks from memory until the FIFO fills
974 * past the watermark point. If the FIFO drains completely, a FIFO underrun
975 * will occur, and a display engine hang could result.
977 static unsigned long intel_calculate_wm(unsigned long clock_in_khz
,
978 const struct intel_watermark_params
*wm
,
981 unsigned long latency_ns
)
983 long entries_required
, wm_size
;
986 * Note: we need to make sure we don't overflow for various clock &
988 * clocks go from a few thousand to several hundred thousand.
989 * latency is usually a few thousand
991 entries_required
= ((clock_in_khz
/ 1000) * pixel_size
* latency_ns
) /
993 entries_required
= DIV_ROUND_UP(entries_required
, wm
->cacheline_size
);
995 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required
);
997 wm_size
= fifo_size
- (entries_required
+ wm
->guard_size
);
999 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size
);
1001 /* Don't promote wm_size to unsigned... */
1002 if (wm_size
> (long)wm
->max_wm
)
1003 wm_size
= wm
->max_wm
;
1005 wm_size
= wm
->default_wm
;
1009 static struct drm_crtc
*single_enabled_crtc(struct drm_device
*dev
)
1011 struct drm_crtc
*crtc
, *enabled
= NULL
;
1013 for_each_crtc(dev
, crtc
) {
1014 if (intel_crtc_active(crtc
)) {
1024 static void pineview_update_wm(struct drm_crtc
*unused_crtc
)
1026 struct drm_device
*dev
= unused_crtc
->dev
;
1027 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1028 struct drm_crtc
*crtc
;
1029 const struct cxsr_latency
*latency
;
1033 latency
= intel_get_cxsr_latency(IS_PINEVIEW_G(dev
), dev_priv
->is_ddr3
,
1034 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
1036 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1037 pineview_disable_cxsr(dev
);
1041 crtc
= single_enabled_crtc(dev
);
1043 const struct drm_display_mode
*adjusted_mode
;
1044 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1047 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1048 clock
= adjusted_mode
->crtc_clock
;
1051 wm
= intel_calculate_wm(clock
, &pineview_display_wm
,
1052 pineview_display_wm
.fifo_size
,
1053 pixel_size
, latency
->display_sr
);
1054 reg
= I915_READ(DSPFW1
);
1055 reg
&= ~DSPFW_SR_MASK
;
1056 reg
|= wm
<< DSPFW_SR_SHIFT
;
1057 I915_WRITE(DSPFW1
, reg
);
1058 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg
);
1061 wm
= intel_calculate_wm(clock
, &pineview_cursor_wm
,
1062 pineview_display_wm
.fifo_size
,
1063 pixel_size
, latency
->cursor_sr
);
1064 reg
= I915_READ(DSPFW3
);
1065 reg
&= ~DSPFW_CURSOR_SR_MASK
;
1066 reg
|= (wm
& 0x3f) << DSPFW_CURSOR_SR_SHIFT
;
1067 I915_WRITE(DSPFW3
, reg
);
1069 /* Display HPLL off SR */
1070 wm
= intel_calculate_wm(clock
, &pineview_display_hplloff_wm
,
1071 pineview_display_hplloff_wm
.fifo_size
,
1072 pixel_size
, latency
->display_hpll_disable
);
1073 reg
= I915_READ(DSPFW3
);
1074 reg
&= ~DSPFW_HPLL_SR_MASK
;
1075 reg
|= wm
& DSPFW_HPLL_SR_MASK
;
1076 I915_WRITE(DSPFW3
, reg
);
1078 /* cursor HPLL off SR */
1079 wm
= intel_calculate_wm(clock
, &pineview_cursor_hplloff_wm
,
1080 pineview_display_hplloff_wm
.fifo_size
,
1081 pixel_size
, latency
->cursor_hpll_disable
);
1082 reg
= I915_READ(DSPFW3
);
1083 reg
&= ~DSPFW_HPLL_CURSOR_MASK
;
1084 reg
|= (wm
& 0x3f) << DSPFW_HPLL_CURSOR_SHIFT
;
1085 I915_WRITE(DSPFW3
, reg
);
1086 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg
);
1090 I915_READ(DSPFW3
) | PINEVIEW_SELF_REFRESH_EN
);
1091 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1093 pineview_disable_cxsr(dev
);
1094 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1098 static bool g4x_compute_wm0(struct drm_device
*dev
,
1100 const struct intel_watermark_params
*display
,
1101 int display_latency_ns
,
1102 const struct intel_watermark_params
*cursor
,
1103 int cursor_latency_ns
,
1107 struct drm_crtc
*crtc
;
1108 const struct drm_display_mode
*adjusted_mode
;
1109 int htotal
, hdisplay
, clock
, pixel_size
;
1110 int line_time_us
, line_count
;
1111 int entries
, tlb_miss
;
1113 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1114 if (!intel_crtc_active(crtc
)) {
1115 *cursor_wm
= cursor
->guard_size
;
1116 *plane_wm
= display
->guard_size
;
1120 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1121 clock
= adjusted_mode
->crtc_clock
;
1122 htotal
= adjusted_mode
->crtc_htotal
;
1123 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1124 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1126 /* Use the small buffer method to calculate plane watermark */
1127 entries
= ((clock
* pixel_size
/ 1000) * display_latency_ns
) / 1000;
1128 tlb_miss
= display
->fifo_size
*display
->cacheline_size
- hdisplay
* 8;
1130 entries
+= tlb_miss
;
1131 entries
= DIV_ROUND_UP(entries
, display
->cacheline_size
);
1132 *plane_wm
= entries
+ display
->guard_size
;
1133 if (*plane_wm
> (int)display
->max_wm
)
1134 *plane_wm
= display
->max_wm
;
1136 /* Use the large buffer method to calculate cursor watermark */
1137 line_time_us
= max(htotal
* 1000 / clock
, 1);
1138 line_count
= (cursor_latency_ns
/ line_time_us
+ 1000) / 1000;
1139 entries
= line_count
* to_intel_crtc(crtc
)->cursor_width
* pixel_size
;
1140 tlb_miss
= cursor
->fifo_size
*cursor
->cacheline_size
- hdisplay
* 8;
1142 entries
+= tlb_miss
;
1143 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1144 *cursor_wm
= entries
+ cursor
->guard_size
;
1145 if (*cursor_wm
> (int)cursor
->max_wm
)
1146 *cursor_wm
= (int)cursor
->max_wm
;
1152 * Check the wm result.
1154 * If any calculated watermark values is larger than the maximum value that
1155 * can be programmed into the associated watermark register, that watermark
1158 static bool g4x_check_srwm(struct drm_device
*dev
,
1159 int display_wm
, int cursor_wm
,
1160 const struct intel_watermark_params
*display
,
1161 const struct intel_watermark_params
*cursor
)
1163 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1164 display_wm
, cursor_wm
);
1166 if (display_wm
> display
->max_wm
) {
1167 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1168 display_wm
, display
->max_wm
);
1172 if (cursor_wm
> cursor
->max_wm
) {
1173 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1174 cursor_wm
, cursor
->max_wm
);
1178 if (!(display_wm
|| cursor_wm
)) {
1179 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1186 static bool g4x_compute_srwm(struct drm_device
*dev
,
1189 const struct intel_watermark_params
*display
,
1190 const struct intel_watermark_params
*cursor
,
1191 int *display_wm
, int *cursor_wm
)
1193 struct drm_crtc
*crtc
;
1194 const struct drm_display_mode
*adjusted_mode
;
1195 int hdisplay
, htotal
, pixel_size
, clock
;
1196 unsigned long line_time_us
;
1197 int line_count
, line_size
;
1202 *display_wm
= *cursor_wm
= 0;
1206 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1207 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1208 clock
= adjusted_mode
->crtc_clock
;
1209 htotal
= adjusted_mode
->crtc_htotal
;
1210 hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1211 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1213 line_time_us
= max(htotal
* 1000 / clock
, 1);
1214 line_count
= (latency_ns
/ line_time_us
+ 1000) / 1000;
1215 line_size
= hdisplay
* pixel_size
;
1217 /* Use the minimum of the small and large buffer method for primary */
1218 small
= ((clock
* pixel_size
/ 1000) * latency_ns
) / 1000;
1219 large
= line_count
* line_size
;
1221 entries
= DIV_ROUND_UP(min(small
, large
), display
->cacheline_size
);
1222 *display_wm
= entries
+ display
->guard_size
;
1224 /* calculate the self-refresh watermark for display cursor */
1225 entries
= line_count
* pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1226 entries
= DIV_ROUND_UP(entries
, cursor
->cacheline_size
);
1227 *cursor_wm
= entries
+ cursor
->guard_size
;
1229 return g4x_check_srwm(dev
,
1230 *display_wm
, *cursor_wm
,
1234 static bool vlv_compute_drain_latency(struct drm_device
*dev
,
1236 int *plane_prec_mult
,
1238 int *cursor_prec_mult
,
1241 struct drm_crtc
*crtc
;
1242 int clock
, pixel_size
;
1245 crtc
= intel_get_crtc_for_plane(dev
, plane
);
1246 if (!intel_crtc_active(crtc
))
1249 clock
= to_intel_crtc(crtc
)->config
.adjusted_mode
.crtc_clock
;
1250 pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8; /* BPP */
1252 entries
= (clock
/ 1000) * pixel_size
;
1253 *plane_prec_mult
= (entries
> 256) ?
1254 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1255 *plane_dl
= (64 * (*plane_prec_mult
) * 4) / ((clock
/ 1000) *
1258 entries
= (clock
/ 1000) * 4; /* BPP is always 4 for cursor */
1259 *cursor_prec_mult
= (entries
> 256) ?
1260 DRAIN_LATENCY_PRECISION_32
: DRAIN_LATENCY_PRECISION_16
;
1261 *cursor_dl
= (64 * (*cursor_prec_mult
) * 4) / ((clock
/ 1000) * 4);
1267 * Update drain latency registers of memory arbiter
1269 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1270 * to be programmed. Each plane has a drain latency multiplier and a drain
1274 static void vlv_update_drain_latency(struct drm_device
*dev
)
1276 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1277 int planea_prec
, planea_dl
, planeb_prec
, planeb_dl
;
1278 int cursora_prec
, cursora_dl
, cursorb_prec
, cursorb_dl
;
1279 int plane_prec_mult
, cursor_prec_mult
; /* Precision multiplier is
1282 /* For plane A, Cursor A */
1283 if (vlv_compute_drain_latency(dev
, 0, &plane_prec_mult
, &planea_dl
,
1284 &cursor_prec_mult
, &cursora_dl
)) {
1285 cursora_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1286 DDL_CURSORA_PRECISION_32
: DDL_CURSORA_PRECISION_16
;
1287 planea_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1288 DDL_PLANEA_PRECISION_32
: DDL_PLANEA_PRECISION_16
;
1290 I915_WRITE(VLV_DDL1
, cursora_prec
|
1291 (cursora_dl
<< DDL_CURSORA_SHIFT
) |
1292 planea_prec
| planea_dl
);
1295 /* For plane B, Cursor B */
1296 if (vlv_compute_drain_latency(dev
, 1, &plane_prec_mult
, &planeb_dl
,
1297 &cursor_prec_mult
, &cursorb_dl
)) {
1298 cursorb_prec
= (cursor_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1299 DDL_CURSORB_PRECISION_32
: DDL_CURSORB_PRECISION_16
;
1300 planeb_prec
= (plane_prec_mult
== DRAIN_LATENCY_PRECISION_32
) ?
1301 DDL_PLANEB_PRECISION_32
: DDL_PLANEB_PRECISION_16
;
1303 I915_WRITE(VLV_DDL2
, cursorb_prec
|
1304 (cursorb_dl
<< DDL_CURSORB_SHIFT
) |
1305 planeb_prec
| planeb_dl
);
1309 #define single_plane_enabled(mask) is_power_of_2(mask)
1311 static void valleyview_update_wm(struct drm_crtc
*crtc
)
1313 struct drm_device
*dev
= crtc
->dev
;
1314 static const int sr_latency_ns
= 12000;
1315 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1316 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1317 int plane_sr
, cursor_sr
;
1318 int ignore_plane_sr
, ignore_cursor_sr
;
1319 unsigned int enabled
= 0;
1321 vlv_update_drain_latency(dev
);
1323 if (g4x_compute_wm0(dev
, PIPE_A
,
1324 &valleyview_wm_info
, latency_ns
,
1325 &valleyview_cursor_wm_info
, latency_ns
,
1326 &planea_wm
, &cursora_wm
))
1327 enabled
|= 1 << PIPE_A
;
1329 if (g4x_compute_wm0(dev
, PIPE_B
,
1330 &valleyview_wm_info
, latency_ns
,
1331 &valleyview_cursor_wm_info
, latency_ns
,
1332 &planeb_wm
, &cursorb_wm
))
1333 enabled
|= 1 << PIPE_B
;
1335 if (single_plane_enabled(enabled
) &&
1336 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1338 &valleyview_wm_info
,
1339 &valleyview_cursor_wm_info
,
1340 &plane_sr
, &ignore_cursor_sr
) &&
1341 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1343 &valleyview_wm_info
,
1344 &valleyview_cursor_wm_info
,
1345 &ignore_plane_sr
, &cursor_sr
)) {
1346 I915_WRITE(FW_BLC_SELF_VLV
, FW_CSPWRDWNEN
);
1348 I915_WRITE(FW_BLC_SELF_VLV
,
1349 I915_READ(FW_BLC_SELF_VLV
) & ~FW_CSPWRDWNEN
);
1350 plane_sr
= cursor_sr
= 0;
1353 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1354 planea_wm
, cursora_wm
,
1355 planeb_wm
, cursorb_wm
,
1356 plane_sr
, cursor_sr
);
1359 (plane_sr
<< DSPFW_SR_SHIFT
) |
1360 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1361 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1364 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1365 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1367 (I915_READ(DSPFW3
) & ~DSPFW_CURSOR_SR_MASK
) |
1368 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1371 static void g4x_update_wm(struct drm_crtc
*crtc
)
1373 struct drm_device
*dev
= crtc
->dev
;
1374 static const int sr_latency_ns
= 12000;
1375 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1376 int planea_wm
, planeb_wm
, cursora_wm
, cursorb_wm
;
1377 int plane_sr
, cursor_sr
;
1378 unsigned int enabled
= 0;
1380 if (g4x_compute_wm0(dev
, PIPE_A
,
1381 &g4x_wm_info
, latency_ns
,
1382 &g4x_cursor_wm_info
, latency_ns
,
1383 &planea_wm
, &cursora_wm
))
1384 enabled
|= 1 << PIPE_A
;
1386 if (g4x_compute_wm0(dev
, PIPE_B
,
1387 &g4x_wm_info
, latency_ns
,
1388 &g4x_cursor_wm_info
, latency_ns
,
1389 &planeb_wm
, &cursorb_wm
))
1390 enabled
|= 1 << PIPE_B
;
1392 if (single_plane_enabled(enabled
) &&
1393 g4x_compute_srwm(dev
, ffs(enabled
) - 1,
1396 &g4x_cursor_wm_info
,
1397 &plane_sr
, &cursor_sr
)) {
1398 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1400 I915_WRITE(FW_BLC_SELF
,
1401 I915_READ(FW_BLC_SELF
) & ~FW_BLC_SELF_EN
);
1402 plane_sr
= cursor_sr
= 0;
1405 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1406 planea_wm
, cursora_wm
,
1407 planeb_wm
, cursorb_wm
,
1408 plane_sr
, cursor_sr
);
1411 (plane_sr
<< DSPFW_SR_SHIFT
) |
1412 (cursorb_wm
<< DSPFW_CURSORB_SHIFT
) |
1413 (planeb_wm
<< DSPFW_PLANEB_SHIFT
) |
1416 (I915_READ(DSPFW2
) & ~DSPFW_CURSORA_MASK
) |
1417 (cursora_wm
<< DSPFW_CURSORA_SHIFT
));
1418 /* HPLL off in SR has some issues on G4x... disable it */
1420 (I915_READ(DSPFW3
) & ~(DSPFW_HPLL_SR_EN
| DSPFW_CURSOR_SR_MASK
)) |
1421 (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1424 static void i965_update_wm(struct drm_crtc
*unused_crtc
)
1426 struct drm_device
*dev
= unused_crtc
->dev
;
1427 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1428 struct drm_crtc
*crtc
;
1432 /* Calc sr entries for one plane configs */
1433 crtc
= single_enabled_crtc(dev
);
1435 /* self-refresh has much higher latency */
1436 static const int sr_latency_ns
= 12000;
1437 const struct drm_display_mode
*adjusted_mode
=
1438 &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1439 int clock
= adjusted_mode
->crtc_clock
;
1440 int htotal
= adjusted_mode
->crtc_htotal
;
1441 int hdisplay
= to_intel_crtc(crtc
)->config
.pipe_src_w
;
1442 int pixel_size
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1443 unsigned long line_time_us
;
1446 line_time_us
= max(htotal
* 1000 / clock
, 1);
1448 /* Use ns/us then divide to preserve precision */
1449 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1450 pixel_size
* hdisplay
;
1451 entries
= DIV_ROUND_UP(entries
, I915_FIFO_LINE_SIZE
);
1452 srwm
= I965_FIFO_SIZE
- entries
;
1456 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1459 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1460 pixel_size
* to_intel_crtc(crtc
)->cursor_width
;
1461 entries
= DIV_ROUND_UP(entries
,
1462 i965_cursor_wm_info
.cacheline_size
);
1463 cursor_sr
= i965_cursor_wm_info
.fifo_size
-
1464 (entries
+ i965_cursor_wm_info
.guard_size
);
1466 if (cursor_sr
> i965_cursor_wm_info
.max_wm
)
1467 cursor_sr
= i965_cursor_wm_info
.max_wm
;
1469 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1470 "cursor %d\n", srwm
, cursor_sr
);
1472 if (IS_CRESTLINE(dev
))
1473 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN
);
1475 /* Turn off self refresh if both pipes are enabled */
1476 if (IS_CRESTLINE(dev
))
1477 I915_WRITE(FW_BLC_SELF
, I915_READ(FW_BLC_SELF
)
1481 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1484 /* 965 has limitations... */
1485 I915_WRITE(DSPFW1
, (srwm
<< DSPFW_SR_SHIFT
) |
1486 (8 << 16) | (8 << 8) | (8 << 0));
1487 I915_WRITE(DSPFW2
, (8 << 8) | (8 << 0));
1488 /* update cursor SR watermark */
1489 I915_WRITE(DSPFW3
, (cursor_sr
<< DSPFW_CURSOR_SR_SHIFT
));
1492 static void i9xx_update_wm(struct drm_crtc
*unused_crtc
)
1494 struct drm_device
*dev
= unused_crtc
->dev
;
1495 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1496 const struct intel_watermark_params
*wm_info
;
1501 int planea_wm
, planeb_wm
;
1502 struct drm_crtc
*crtc
, *enabled
= NULL
;
1505 wm_info
= &i945_wm_info
;
1506 else if (!IS_GEN2(dev
))
1507 wm_info
= &i915_wm_info
;
1509 wm_info
= &i830_wm_info
;
1511 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 0);
1512 crtc
= intel_get_crtc_for_plane(dev
, 0);
1513 if (intel_crtc_active(crtc
)) {
1514 const struct drm_display_mode
*adjusted_mode
;
1515 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1519 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1520 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1521 wm_info
, fifo_size
, cpp
,
1525 planea_wm
= fifo_size
- wm_info
->guard_size
;
1527 fifo_size
= dev_priv
->display
.get_fifo_size(dev
, 1);
1528 crtc
= intel_get_crtc_for_plane(dev
, 1);
1529 if (intel_crtc_active(crtc
)) {
1530 const struct drm_display_mode
*adjusted_mode
;
1531 int cpp
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
1535 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1536 planeb_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1537 wm_info
, fifo_size
, cpp
,
1539 if (enabled
== NULL
)
1544 planeb_wm
= fifo_size
- wm_info
->guard_size
;
1546 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm
, planeb_wm
);
1548 if (IS_I915GM(dev
) && enabled
) {
1549 struct intel_framebuffer
*fb
;
1551 fb
= to_intel_framebuffer(enabled
->primary
->fb
);
1553 /* self-refresh seems busted with untiled */
1554 if (fb
->obj
->tiling_mode
== I915_TILING_NONE
)
1559 * Overlay gets an aggressive default since video jitter is bad.
1563 /* Play safe and disable self-refresh before adjusting watermarks. */
1564 if (IS_I945G(dev
) || IS_I945GM(dev
))
1565 I915_WRITE(FW_BLC_SELF
, FW_BLC_SELF_EN_MASK
| 0);
1566 else if (IS_I915GM(dev
))
1567 I915_WRITE(INSTPM
, _MASKED_BIT_DISABLE(INSTPM_SELF_EN
));
1569 /* Calc sr entries for one plane configs */
1570 if (HAS_FW_BLC(dev
) && enabled
) {
1571 /* self-refresh has much higher latency */
1572 static const int sr_latency_ns
= 6000;
1573 const struct drm_display_mode
*adjusted_mode
=
1574 &to_intel_crtc(enabled
)->config
.adjusted_mode
;
1575 int clock
= adjusted_mode
->crtc_clock
;
1576 int htotal
= adjusted_mode
->crtc_htotal
;
1577 int hdisplay
= to_intel_crtc(enabled
)->config
.pipe_src_w
;
1578 int pixel_size
= enabled
->primary
->fb
->bits_per_pixel
/ 8;
1579 unsigned long line_time_us
;
1582 line_time_us
= max(htotal
* 1000 / clock
, 1);
1584 /* Use ns/us then divide to preserve precision */
1585 entries
= (((sr_latency_ns
/ line_time_us
) + 1000) / 1000) *
1586 pixel_size
* hdisplay
;
1587 entries
= DIV_ROUND_UP(entries
, wm_info
->cacheline_size
);
1588 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries
);
1589 srwm
= wm_info
->fifo_size
- entries
;
1593 if (IS_I945G(dev
) || IS_I945GM(dev
))
1594 I915_WRITE(FW_BLC_SELF
,
1595 FW_BLC_SELF_FIFO_MASK
| (srwm
& 0xff));
1596 else if (IS_I915GM(dev
))
1597 I915_WRITE(FW_BLC_SELF
, srwm
& 0x3f);
1600 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1601 planea_wm
, planeb_wm
, cwm
, srwm
);
1603 fwater_lo
= ((planeb_wm
& 0x3f) << 16) | (planea_wm
& 0x3f);
1604 fwater_hi
= (cwm
& 0x1f);
1606 /* Set request length to 8 cachelines per fetch */
1607 fwater_lo
= fwater_lo
| (1 << 24) | (1 << 8);
1608 fwater_hi
= fwater_hi
| (1 << 8);
1610 I915_WRITE(FW_BLC
, fwater_lo
);
1611 I915_WRITE(FW_BLC2
, fwater_hi
);
1613 if (HAS_FW_BLC(dev
)) {
1615 if (IS_I945G(dev
) || IS_I945GM(dev
))
1616 I915_WRITE(FW_BLC_SELF
,
1617 FW_BLC_SELF_EN_MASK
| FW_BLC_SELF_EN
);
1618 else if (IS_I915GM(dev
))
1619 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_SELF_EN
));
1620 DRM_DEBUG_KMS("memory self refresh enabled\n");
1622 DRM_DEBUG_KMS("memory self refresh disabled\n");
1626 static void i845_update_wm(struct drm_crtc
*unused_crtc
)
1628 struct drm_device
*dev
= unused_crtc
->dev
;
1629 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1630 struct drm_crtc
*crtc
;
1631 const struct drm_display_mode
*adjusted_mode
;
1635 crtc
= single_enabled_crtc(dev
);
1639 adjusted_mode
= &to_intel_crtc(crtc
)->config
.adjusted_mode
;
1640 planea_wm
= intel_calculate_wm(adjusted_mode
->crtc_clock
,
1642 dev_priv
->display
.get_fifo_size(dev
, 0),
1644 fwater_lo
= I915_READ(FW_BLC
) & ~0xfff;
1645 fwater_lo
|= (3<<8) | planea_wm
;
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm
);
1649 I915_WRITE(FW_BLC
, fwater_lo
);
1652 static uint32_t ilk_pipe_pixel_rate(struct drm_device
*dev
,
1653 struct drm_crtc
*crtc
)
1655 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1656 uint32_t pixel_rate
;
1658 pixel_rate
= intel_crtc
->config
.adjusted_mode
.crtc_clock
;
1660 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1661 * adjust the pixel_rate here. */
1663 if (intel_crtc
->config
.pch_pfit
.enabled
) {
1664 uint64_t pipe_w
, pipe_h
, pfit_w
, pfit_h
;
1665 uint32_t pfit_size
= intel_crtc
->config
.pch_pfit
.size
;
1667 pipe_w
= intel_crtc
->config
.pipe_src_w
;
1668 pipe_h
= intel_crtc
->config
.pipe_src_h
;
1669 pfit_w
= (pfit_size
>> 16) & 0xFFFF;
1670 pfit_h
= pfit_size
& 0xFFFF;
1671 if (pipe_w
< pfit_w
)
1673 if (pipe_h
< pfit_h
)
1676 pixel_rate
= div_u64((uint64_t) pixel_rate
* pipe_w
* pipe_h
,
1683 /* latency must be in 0.1us units. */
1684 static uint32_t ilk_wm_method1(uint32_t pixel_rate
, uint8_t bytes_per_pixel
,
1689 if (WARN(latency
== 0, "Latency value missing\n"))
1692 ret
= (uint64_t) pixel_rate
* bytes_per_pixel
* latency
;
1693 ret
= DIV_ROUND_UP_ULL(ret
, 64 * 10000) + 2;
1698 /* latency must be in 0.1us units. */
1699 static uint32_t ilk_wm_method2(uint32_t pixel_rate
, uint32_t pipe_htotal
,
1700 uint32_t horiz_pixels
, uint8_t bytes_per_pixel
,
1705 if (WARN(latency
== 0, "Latency value missing\n"))
1708 ret
= (latency
* pixel_rate
) / (pipe_htotal
* 10000);
1709 ret
= (ret
+ 1) * horiz_pixels
* bytes_per_pixel
;
1710 ret
= DIV_ROUND_UP(ret
, 64) + 2;
1714 static uint32_t ilk_wm_fbc(uint32_t pri_val
, uint32_t horiz_pixels
,
1715 uint8_t bytes_per_pixel
)
1717 return DIV_ROUND_UP(pri_val
* 64, horiz_pixels
* bytes_per_pixel
) + 2;
1720 struct ilk_pipe_wm_parameters
{
1722 uint32_t pipe_htotal
;
1723 uint32_t pixel_rate
;
1724 struct intel_plane_wm_parameters pri
;
1725 struct intel_plane_wm_parameters spr
;
1726 struct intel_plane_wm_parameters cur
;
1729 struct ilk_wm_maximums
{
1736 /* used in computing the new watermarks state */
1737 struct intel_wm_config
{
1738 unsigned int num_pipes_active
;
1739 bool sprites_enabled
;
1740 bool sprites_scaled
;
1744 * For both WM_PIPE and WM_LP.
1745 * mem_value must be in 0.1us units.
1747 static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters
*params
,
1751 uint32_t method1
, method2
;
1753 if (!params
->active
|| !params
->pri
.enabled
)
1756 method1
= ilk_wm_method1(params
->pixel_rate
,
1757 params
->pri
.bytes_per_pixel
,
1763 method2
= ilk_wm_method2(params
->pixel_rate
,
1764 params
->pipe_htotal
,
1765 params
->pri
.horiz_pixels
,
1766 params
->pri
.bytes_per_pixel
,
1769 return min(method1
, method2
);
1773 * For both WM_PIPE and WM_LP.
1774 * mem_value must be in 0.1us units.
1776 static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters
*params
,
1779 uint32_t method1
, method2
;
1781 if (!params
->active
|| !params
->spr
.enabled
)
1784 method1
= ilk_wm_method1(params
->pixel_rate
,
1785 params
->spr
.bytes_per_pixel
,
1787 method2
= ilk_wm_method2(params
->pixel_rate
,
1788 params
->pipe_htotal
,
1789 params
->spr
.horiz_pixels
,
1790 params
->spr
.bytes_per_pixel
,
1792 return min(method1
, method2
);
1796 * For both WM_PIPE and WM_LP.
1797 * mem_value must be in 0.1us units.
1799 static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters
*params
,
1802 if (!params
->active
|| !params
->cur
.enabled
)
1805 return ilk_wm_method2(params
->pixel_rate
,
1806 params
->pipe_htotal
,
1807 params
->cur
.horiz_pixels
,
1808 params
->cur
.bytes_per_pixel
,
1812 /* Only for WM_LP. */
1813 static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters
*params
,
1816 if (!params
->active
|| !params
->pri
.enabled
)
1819 return ilk_wm_fbc(pri_val
,
1820 params
->pri
.horiz_pixels
,
1821 params
->pri
.bytes_per_pixel
);
1824 static unsigned int ilk_display_fifo_size(const struct drm_device
*dev
)
1826 if (INTEL_INFO(dev
)->gen
>= 8)
1828 else if (INTEL_INFO(dev
)->gen
>= 7)
1834 static unsigned int ilk_plane_wm_reg_max(const struct drm_device
*dev
,
1835 int level
, bool is_sprite
)
1837 if (INTEL_INFO(dev
)->gen
>= 8)
1838 /* BDW primary/sprite plane watermarks */
1839 return level
== 0 ? 255 : 2047;
1840 else if (INTEL_INFO(dev
)->gen
>= 7)
1841 /* IVB/HSW primary/sprite plane watermarks */
1842 return level
== 0 ? 127 : 1023;
1843 else if (!is_sprite
)
1844 /* ILK/SNB primary plane watermarks */
1845 return level
== 0 ? 127 : 511;
1847 /* ILK/SNB sprite plane watermarks */
1848 return level
== 0 ? 63 : 255;
1851 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device
*dev
,
1854 if (INTEL_INFO(dev
)->gen
>= 7)
1855 return level
== 0 ? 63 : 255;
1857 return level
== 0 ? 31 : 63;
1860 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device
*dev
)
1862 if (INTEL_INFO(dev
)->gen
>= 8)
1868 /* Calculate the maximum primary/sprite plane watermark */
1869 static unsigned int ilk_plane_wm_max(const struct drm_device
*dev
,
1871 const struct intel_wm_config
*config
,
1872 enum intel_ddb_partitioning ddb_partitioning
,
1875 unsigned int fifo_size
= ilk_display_fifo_size(dev
);
1877 /* if sprites aren't enabled, sprites get nothing */
1878 if (is_sprite
&& !config
->sprites_enabled
)
1881 /* HSW allows LP1+ watermarks even with multiple pipes */
1882 if (level
== 0 || config
->num_pipes_active
> 1) {
1883 fifo_size
/= INTEL_INFO(dev
)->num_pipes
;
1886 * For some reason the non self refresh
1887 * FIFO size is only half of the self
1888 * refresh FIFO size on ILK/SNB.
1890 if (INTEL_INFO(dev
)->gen
<= 6)
1894 if (config
->sprites_enabled
) {
1895 /* level 0 is always calculated with 1:1 split */
1896 if (level
> 0 && ddb_partitioning
== INTEL_DDB_PART_5_6
) {
1905 /* clamp to max that the registers can hold */
1906 return min(fifo_size
, ilk_plane_wm_reg_max(dev
, level
, is_sprite
));
1909 /* Calculate the maximum cursor plane watermark */
1910 static unsigned int ilk_cursor_wm_max(const struct drm_device
*dev
,
1912 const struct intel_wm_config
*config
)
1914 /* HSW LP1+ watermarks w/ multiple pipes */
1915 if (level
> 0 && config
->num_pipes_active
> 1)
1918 /* otherwise just report max that registers can hold */
1919 return ilk_cursor_wm_reg_max(dev
, level
);
1922 static void ilk_compute_wm_maximums(const struct drm_device
*dev
,
1924 const struct intel_wm_config
*config
,
1925 enum intel_ddb_partitioning ddb_partitioning
,
1926 struct ilk_wm_maximums
*max
)
1928 max
->pri
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, false);
1929 max
->spr
= ilk_plane_wm_max(dev
, level
, config
, ddb_partitioning
, true);
1930 max
->cur
= ilk_cursor_wm_max(dev
, level
, config
);
1931 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1934 static void ilk_compute_wm_reg_maximums(struct drm_device
*dev
,
1936 struct ilk_wm_maximums
*max
)
1938 max
->pri
= ilk_plane_wm_reg_max(dev
, level
, false);
1939 max
->spr
= ilk_plane_wm_reg_max(dev
, level
, true);
1940 max
->cur
= ilk_cursor_wm_reg_max(dev
, level
);
1941 max
->fbc
= ilk_fbc_wm_reg_max(dev
);
1944 static bool ilk_validate_wm_level(int level
,
1945 const struct ilk_wm_maximums
*max
,
1946 struct intel_wm_level
*result
)
1950 /* already determined to be invalid? */
1951 if (!result
->enable
)
1954 result
->enable
= result
->pri_val
<= max
->pri
&&
1955 result
->spr_val
<= max
->spr
&&
1956 result
->cur_val
<= max
->cur
;
1958 ret
= result
->enable
;
1961 * HACK until we can pre-compute everything,
1962 * and thus fail gracefully if LP0 watermarks
1965 if (level
== 0 && !result
->enable
) {
1966 if (result
->pri_val
> max
->pri
)
1967 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1968 level
, result
->pri_val
, max
->pri
);
1969 if (result
->spr_val
> max
->spr
)
1970 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1971 level
, result
->spr_val
, max
->spr
);
1972 if (result
->cur_val
> max
->cur
)
1973 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1974 level
, result
->cur_val
, max
->cur
);
1976 result
->pri_val
= min_t(uint32_t, result
->pri_val
, max
->pri
);
1977 result
->spr_val
= min_t(uint32_t, result
->spr_val
, max
->spr
);
1978 result
->cur_val
= min_t(uint32_t, result
->cur_val
, max
->cur
);
1979 result
->enable
= true;
1985 static void ilk_compute_wm_level(const struct drm_i915_private
*dev_priv
,
1987 const struct ilk_pipe_wm_parameters
*p
,
1988 struct intel_wm_level
*result
)
1990 uint16_t pri_latency
= dev_priv
->wm
.pri_latency
[level
];
1991 uint16_t spr_latency
= dev_priv
->wm
.spr_latency
[level
];
1992 uint16_t cur_latency
= dev_priv
->wm
.cur_latency
[level
];
1994 /* WM1+ latency values stored in 0.5us units */
2001 result
->pri_val
= ilk_compute_pri_wm(p
, pri_latency
, level
);
2002 result
->spr_val
= ilk_compute_spr_wm(p
, spr_latency
);
2003 result
->cur_val
= ilk_compute_cur_wm(p
, cur_latency
);
2004 result
->fbc_val
= ilk_compute_fbc_wm(p
, result
->pri_val
);
2005 result
->enable
= true;
2009 hsw_compute_linetime_wm(struct drm_device
*dev
, struct drm_crtc
*crtc
)
2011 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2012 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2013 struct drm_display_mode
*mode
= &intel_crtc
->config
.adjusted_mode
;
2014 u32 linetime
, ips_linetime
;
2016 if (!intel_crtc_active(crtc
))
2019 /* The WM are computed with base on how long it takes to fill a single
2020 * row at the given clock rate, multiplied by 8.
2022 linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2024 ips_linetime
= DIV_ROUND_CLOSEST(mode
->crtc_htotal
* 1000 * 8,
2025 intel_ddi_get_cdclk_freq(dev_priv
));
2027 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime
) |
2028 PIPE_WM_LINETIME_TIME(linetime
);
2031 static void intel_read_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2035 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2036 uint64_t sskpd
= I915_READ64(MCH_SSKPD
);
2038 wm
[0] = (sskpd
>> 56) & 0xFF;
2040 wm
[0] = sskpd
& 0xF;
2041 wm
[1] = (sskpd
>> 4) & 0xFF;
2042 wm
[2] = (sskpd
>> 12) & 0xFF;
2043 wm
[3] = (sskpd
>> 20) & 0x1FF;
2044 wm
[4] = (sskpd
>> 32) & 0x1FF;
2045 } else if (INTEL_INFO(dev
)->gen
>= 6) {
2046 uint32_t sskpd
= I915_READ(MCH_SSKPD
);
2048 wm
[0] = (sskpd
>> SSKPD_WM0_SHIFT
) & SSKPD_WM_MASK
;
2049 wm
[1] = (sskpd
>> SSKPD_WM1_SHIFT
) & SSKPD_WM_MASK
;
2050 wm
[2] = (sskpd
>> SSKPD_WM2_SHIFT
) & SSKPD_WM_MASK
;
2051 wm
[3] = (sskpd
>> SSKPD_WM3_SHIFT
) & SSKPD_WM_MASK
;
2052 } else if (INTEL_INFO(dev
)->gen
>= 5) {
2053 uint32_t mltr
= I915_READ(MLTR_ILK
);
2055 /* ILK primary LP0 latency is 700 ns */
2057 wm
[1] = (mltr
>> MLTR_WM1_SHIFT
) & ILK_SRLT_MASK
;
2058 wm
[2] = (mltr
>> MLTR_WM2_SHIFT
) & ILK_SRLT_MASK
;
2062 static void intel_fixup_spr_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2064 /* ILK sprite LP0 latency is 1300 ns */
2065 if (INTEL_INFO(dev
)->gen
== 5)
2069 static void intel_fixup_cur_wm_latency(struct drm_device
*dev
, uint16_t wm
[5])
2071 /* ILK cursor LP0 latency is 1300 ns */
2072 if (INTEL_INFO(dev
)->gen
== 5)
2075 /* WaDoubleCursorLP3Latency:ivb */
2076 if (IS_IVYBRIDGE(dev
))
2080 int ilk_wm_max_level(const struct drm_device
*dev
)
2082 /* how many WM levels are we expecting */
2083 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2085 else if (INTEL_INFO(dev
)->gen
>= 6)
2091 static void intel_print_wm_latency(struct drm_device
*dev
,
2093 const uint16_t wm
[5])
2095 int level
, max_level
= ilk_wm_max_level(dev
);
2097 for (level
= 0; level
<= max_level
; level
++) {
2098 unsigned int latency
= wm
[level
];
2101 DRM_ERROR("%s WM%d latency not provided\n",
2106 /* WM1+ latency values in 0.5us units */
2110 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2111 name
, level
, wm
[level
],
2112 latency
/ 10, latency
% 10);
2116 static bool ilk_increase_wm_latency(struct drm_i915_private
*dev_priv
,
2117 uint16_t wm
[5], uint16_t min
)
2119 int level
, max_level
= ilk_wm_max_level(dev_priv
->dev
);
2124 wm
[0] = max(wm
[0], min
);
2125 for (level
= 1; level
<= max_level
; level
++)
2126 wm
[level
] = max_t(uint16_t, wm
[level
], DIV_ROUND_UP(min
, 5));
2131 static void snb_wm_latency_quirk(struct drm_device
*dev
)
2133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2137 * The BIOS provided WM memory latency values are often
2138 * inadequate for high resolution displays. Adjust them.
2140 changed
= ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.pri_latency
, 12) |
2141 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.spr_latency
, 12) |
2142 ilk_increase_wm_latency(dev_priv
, dev_priv
->wm
.cur_latency
, 12);
2147 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2148 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2149 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2150 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2153 static void ilk_setup_wm_latency(struct drm_device
*dev
)
2155 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2157 intel_read_wm_latency(dev
, dev_priv
->wm
.pri_latency
);
2159 memcpy(dev_priv
->wm
.spr_latency
, dev_priv
->wm
.pri_latency
,
2160 sizeof(dev_priv
->wm
.pri_latency
));
2161 memcpy(dev_priv
->wm
.cur_latency
, dev_priv
->wm
.pri_latency
,
2162 sizeof(dev_priv
->wm
.pri_latency
));
2164 intel_fixup_spr_wm_latency(dev
, dev_priv
->wm
.spr_latency
);
2165 intel_fixup_cur_wm_latency(dev
, dev_priv
->wm
.cur_latency
);
2167 intel_print_wm_latency(dev
, "Primary", dev_priv
->wm
.pri_latency
);
2168 intel_print_wm_latency(dev
, "Sprite", dev_priv
->wm
.spr_latency
);
2169 intel_print_wm_latency(dev
, "Cursor", dev_priv
->wm
.cur_latency
);
2172 snb_wm_latency_quirk(dev
);
2175 static void ilk_compute_wm_parameters(struct drm_crtc
*crtc
,
2176 struct ilk_pipe_wm_parameters
*p
)
2178 struct drm_device
*dev
= crtc
->dev
;
2179 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2180 enum pipe pipe
= intel_crtc
->pipe
;
2181 struct drm_plane
*plane
;
2183 if (!intel_crtc_active(crtc
))
2187 p
->pipe_htotal
= intel_crtc
->config
.adjusted_mode
.crtc_htotal
;
2188 p
->pixel_rate
= ilk_pipe_pixel_rate(dev
, crtc
);
2189 p
->pri
.bytes_per_pixel
= crtc
->primary
->fb
->bits_per_pixel
/ 8;
2190 p
->cur
.bytes_per_pixel
= 4;
2191 p
->pri
.horiz_pixels
= intel_crtc
->config
.pipe_src_w
;
2192 p
->cur
.horiz_pixels
= intel_crtc
->cursor_width
;
2193 /* TODO: for now, assume primary and cursor planes are always enabled. */
2194 p
->pri
.enabled
= true;
2195 p
->cur
.enabled
= true;
2197 drm_for_each_legacy_plane(plane
, &dev
->mode_config
.plane_list
) {
2198 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2200 if (intel_plane
->pipe
== pipe
) {
2201 p
->spr
= intel_plane
->wm
;
2207 static void ilk_compute_wm_config(struct drm_device
*dev
,
2208 struct intel_wm_config
*config
)
2210 struct intel_crtc
*intel_crtc
;
2212 /* Compute the currently _active_ config */
2213 for_each_intel_crtc(dev
, intel_crtc
) {
2214 const struct intel_pipe_wm
*wm
= &intel_crtc
->wm
.active
;
2216 if (!wm
->pipe_enabled
)
2219 config
->sprites_enabled
|= wm
->sprites_enabled
;
2220 config
->sprites_scaled
|= wm
->sprites_scaled
;
2221 config
->num_pipes_active
++;
2225 /* Compute new watermarks for the pipe */
2226 static bool intel_compute_pipe_wm(struct drm_crtc
*crtc
,
2227 const struct ilk_pipe_wm_parameters
*params
,
2228 struct intel_pipe_wm
*pipe_wm
)
2230 struct drm_device
*dev
= crtc
->dev
;
2231 const struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2232 int level
, max_level
= ilk_wm_max_level(dev
);
2233 /* LP0 watermark maximums depend on this pipe alone */
2234 struct intel_wm_config config
= {
2235 .num_pipes_active
= 1,
2236 .sprites_enabled
= params
->spr
.enabled
,
2237 .sprites_scaled
= params
->spr
.scaled
,
2239 struct ilk_wm_maximums max
;
2241 pipe_wm
->pipe_enabled
= params
->active
;
2242 pipe_wm
->sprites_enabled
= params
->spr
.enabled
;
2243 pipe_wm
->sprites_scaled
= params
->spr
.scaled
;
2245 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2246 if (INTEL_INFO(dev
)->gen
<= 6 && params
->spr
.enabled
)
2249 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2250 if (params
->spr
.scaled
)
2253 ilk_compute_wm_level(dev_priv
, 0, params
, &pipe_wm
->wm
[0]);
2255 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2256 pipe_wm
->linetime
= hsw_compute_linetime_wm(dev
, crtc
);
2258 /* LP0 watermarks always use 1/2 DDB partitioning */
2259 ilk_compute_wm_maximums(dev
, 0, &config
, INTEL_DDB_PART_1_2
, &max
);
2261 /* At least LP0 must be valid */
2262 if (!ilk_validate_wm_level(0, &max
, &pipe_wm
->wm
[0]))
2265 ilk_compute_wm_reg_maximums(dev
, 1, &max
);
2267 for (level
= 1; level
<= max_level
; level
++) {
2268 struct intel_wm_level wm
= {};
2270 ilk_compute_wm_level(dev_priv
, level
, params
, &wm
);
2273 * Disable any watermark level that exceeds the
2274 * register maximums since such watermarks are
2277 if (!ilk_validate_wm_level(level
, &max
, &wm
))
2280 pipe_wm
->wm
[level
] = wm
;
2287 * Merge the watermarks from all active pipes for a specific level.
2289 static void ilk_merge_wm_level(struct drm_device
*dev
,
2291 struct intel_wm_level
*ret_wm
)
2293 const struct intel_crtc
*intel_crtc
;
2295 ret_wm
->enable
= true;
2297 for_each_intel_crtc(dev
, intel_crtc
) {
2298 const struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2299 const struct intel_wm_level
*wm
= &active
->wm
[level
];
2301 if (!active
->pipe_enabled
)
2305 * The watermark values may have been used in the past,
2306 * so we must maintain them in the registers for some
2307 * time even if the level is now disabled.
2310 ret_wm
->enable
= false;
2312 ret_wm
->pri_val
= max(ret_wm
->pri_val
, wm
->pri_val
);
2313 ret_wm
->spr_val
= max(ret_wm
->spr_val
, wm
->spr_val
);
2314 ret_wm
->cur_val
= max(ret_wm
->cur_val
, wm
->cur_val
);
2315 ret_wm
->fbc_val
= max(ret_wm
->fbc_val
, wm
->fbc_val
);
2320 * Merge all low power watermarks for all active pipes.
2322 static void ilk_wm_merge(struct drm_device
*dev
,
2323 const struct intel_wm_config
*config
,
2324 const struct ilk_wm_maximums
*max
,
2325 struct intel_pipe_wm
*merged
)
2327 int level
, max_level
= ilk_wm_max_level(dev
);
2328 int last_enabled_level
= max_level
;
2330 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2331 if ((INTEL_INFO(dev
)->gen
<= 6 || IS_IVYBRIDGE(dev
)) &&
2332 config
->num_pipes_active
> 1)
2335 /* ILK: FBC WM must be disabled always */
2336 merged
->fbc_wm_enabled
= INTEL_INFO(dev
)->gen
>= 6;
2338 /* merge each WM1+ level */
2339 for (level
= 1; level
<= max_level
; level
++) {
2340 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2342 ilk_merge_wm_level(dev
, level
, wm
);
2344 if (level
> last_enabled_level
)
2346 else if (!ilk_validate_wm_level(level
, max
, wm
))
2347 /* make sure all following levels get disabled */
2348 last_enabled_level
= level
- 1;
2351 * The spec says it is preferred to disable
2352 * FBC WMs instead of disabling a WM level.
2354 if (wm
->fbc_val
> max
->fbc
) {
2356 merged
->fbc_wm_enabled
= false;
2361 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2363 * FIXME this is racy. FBC might get enabled later.
2364 * What we should check here is whether FBC can be
2365 * enabled sometime later.
2367 if (IS_GEN5(dev
) && !merged
->fbc_wm_enabled
&& intel_fbc_enabled(dev
)) {
2368 for (level
= 2; level
<= max_level
; level
++) {
2369 struct intel_wm_level
*wm
= &merged
->wm
[level
];
2376 static int ilk_wm_lp_to_level(int wm_lp
, const struct intel_pipe_wm
*pipe_wm
)
2378 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2379 return wm_lp
+ (wm_lp
>= 2 && pipe_wm
->wm
[4].enable
);
2382 /* The value we need to program into the WM_LPx latency field */
2383 static unsigned int ilk_wm_lp_latency(struct drm_device
*dev
, int level
)
2385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2387 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2390 return dev_priv
->wm
.pri_latency
[level
];
2393 static void ilk_compute_wm_results(struct drm_device
*dev
,
2394 const struct intel_pipe_wm
*merged
,
2395 enum intel_ddb_partitioning partitioning
,
2396 struct ilk_wm_values
*results
)
2398 struct intel_crtc
*intel_crtc
;
2401 results
->enable_fbc_wm
= merged
->fbc_wm_enabled
;
2402 results
->partitioning
= partitioning
;
2404 /* LP1+ register values */
2405 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2406 const struct intel_wm_level
*r
;
2408 level
= ilk_wm_lp_to_level(wm_lp
, merged
);
2410 r
= &merged
->wm
[level
];
2413 * Maintain the watermark values even if the level is
2414 * disabled. Doing otherwise could cause underruns.
2416 results
->wm_lp
[wm_lp
- 1] =
2417 (ilk_wm_lp_latency(dev
, level
) << WM1_LP_LATENCY_SHIFT
) |
2418 (r
->pri_val
<< WM1_LP_SR_SHIFT
) |
2422 results
->wm_lp
[wm_lp
- 1] |= WM1_LP_SR_EN
;
2424 if (INTEL_INFO(dev
)->gen
>= 8)
2425 results
->wm_lp
[wm_lp
- 1] |=
2426 r
->fbc_val
<< WM1_LP_FBC_SHIFT_BDW
;
2428 results
->wm_lp
[wm_lp
- 1] |=
2429 r
->fbc_val
<< WM1_LP_FBC_SHIFT
;
2432 * Always set WM1S_LP_EN when spr_val != 0, even if the
2433 * level is disabled. Doing otherwise could cause underruns.
2435 if (INTEL_INFO(dev
)->gen
<= 6 && r
->spr_val
) {
2436 WARN_ON(wm_lp
!= 1);
2437 results
->wm_lp_spr
[wm_lp
- 1] = WM1S_LP_EN
| r
->spr_val
;
2439 results
->wm_lp_spr
[wm_lp
- 1] = r
->spr_val
;
2442 /* LP0 register values */
2443 for_each_intel_crtc(dev
, intel_crtc
) {
2444 enum pipe pipe
= intel_crtc
->pipe
;
2445 const struct intel_wm_level
*r
=
2446 &intel_crtc
->wm
.active
.wm
[0];
2448 if (WARN_ON(!r
->enable
))
2451 results
->wm_linetime
[pipe
] = intel_crtc
->wm
.active
.linetime
;
2453 results
->wm_pipe
[pipe
] =
2454 (r
->pri_val
<< WM0_PIPE_PLANE_SHIFT
) |
2455 (r
->spr_val
<< WM0_PIPE_SPRITE_SHIFT
) |
2460 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2461 * case both are at the same level. Prefer r1 in case they're the same. */
2462 static struct intel_pipe_wm
*ilk_find_best_result(struct drm_device
*dev
,
2463 struct intel_pipe_wm
*r1
,
2464 struct intel_pipe_wm
*r2
)
2466 int level
, max_level
= ilk_wm_max_level(dev
);
2467 int level1
= 0, level2
= 0;
2469 for (level
= 1; level
<= max_level
; level
++) {
2470 if (r1
->wm
[level
].enable
)
2472 if (r2
->wm
[level
].enable
)
2476 if (level1
== level2
) {
2477 if (r2
->fbc_wm_enabled
&& !r1
->fbc_wm_enabled
)
2481 } else if (level1
> level2
) {
2488 /* dirty bits used to track which watermarks need changes */
2489 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2490 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2491 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2492 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2493 #define WM_DIRTY_FBC (1 << 24)
2494 #define WM_DIRTY_DDB (1 << 25)
2496 static unsigned int ilk_compute_wm_dirty(struct drm_device
*dev
,
2497 const struct ilk_wm_values
*old
,
2498 const struct ilk_wm_values
*new)
2500 unsigned int dirty
= 0;
2504 for_each_pipe(pipe
) {
2505 if (old
->wm_linetime
[pipe
] != new->wm_linetime
[pipe
]) {
2506 dirty
|= WM_DIRTY_LINETIME(pipe
);
2507 /* Must disable LP1+ watermarks too */
2508 dirty
|= WM_DIRTY_LP_ALL
;
2511 if (old
->wm_pipe
[pipe
] != new->wm_pipe
[pipe
]) {
2512 dirty
|= WM_DIRTY_PIPE(pipe
);
2513 /* Must disable LP1+ watermarks too */
2514 dirty
|= WM_DIRTY_LP_ALL
;
2518 if (old
->enable_fbc_wm
!= new->enable_fbc_wm
) {
2519 dirty
|= WM_DIRTY_FBC
;
2520 /* Must disable LP1+ watermarks too */
2521 dirty
|= WM_DIRTY_LP_ALL
;
2524 if (old
->partitioning
!= new->partitioning
) {
2525 dirty
|= WM_DIRTY_DDB
;
2526 /* Must disable LP1+ watermarks too */
2527 dirty
|= WM_DIRTY_LP_ALL
;
2530 /* LP1+ watermarks already deemed dirty, no need to continue */
2531 if (dirty
& WM_DIRTY_LP_ALL
)
2534 /* Find the lowest numbered LP1+ watermark in need of an update... */
2535 for (wm_lp
= 1; wm_lp
<= 3; wm_lp
++) {
2536 if (old
->wm_lp
[wm_lp
- 1] != new->wm_lp
[wm_lp
- 1] ||
2537 old
->wm_lp_spr
[wm_lp
- 1] != new->wm_lp_spr
[wm_lp
- 1])
2541 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2542 for (; wm_lp
<= 3; wm_lp
++)
2543 dirty
|= WM_DIRTY_LP(wm_lp
);
2548 static bool _ilk_disable_lp_wm(struct drm_i915_private
*dev_priv
,
2551 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2552 bool changed
= false;
2554 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] & WM1_LP_SR_EN
) {
2555 previous
->wm_lp
[2] &= ~WM1_LP_SR_EN
;
2556 I915_WRITE(WM3_LP_ILK
, previous
->wm_lp
[2]);
2559 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] & WM1_LP_SR_EN
) {
2560 previous
->wm_lp
[1] &= ~WM1_LP_SR_EN
;
2561 I915_WRITE(WM2_LP_ILK
, previous
->wm_lp
[1]);
2564 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] & WM1_LP_SR_EN
) {
2565 previous
->wm_lp
[0] &= ~WM1_LP_SR_EN
;
2566 I915_WRITE(WM1_LP_ILK
, previous
->wm_lp
[0]);
2571 * Don't touch WM1S_LP_EN here.
2572 * Doing so could cause underruns.
2579 * The spec says we shouldn't write when we don't need, because every write
2580 * causes WMs to be re-evaluated, expending some power.
2582 static void ilk_write_wm_values(struct drm_i915_private
*dev_priv
,
2583 struct ilk_wm_values
*results
)
2585 struct drm_device
*dev
= dev_priv
->dev
;
2586 struct ilk_wm_values
*previous
= &dev_priv
->wm
.hw
;
2590 dirty
= ilk_compute_wm_dirty(dev
, previous
, results
);
2594 _ilk_disable_lp_wm(dev_priv
, dirty
);
2596 if (dirty
& WM_DIRTY_PIPE(PIPE_A
))
2597 I915_WRITE(WM0_PIPEA_ILK
, results
->wm_pipe
[0]);
2598 if (dirty
& WM_DIRTY_PIPE(PIPE_B
))
2599 I915_WRITE(WM0_PIPEB_ILK
, results
->wm_pipe
[1]);
2600 if (dirty
& WM_DIRTY_PIPE(PIPE_C
))
2601 I915_WRITE(WM0_PIPEC_IVB
, results
->wm_pipe
[2]);
2603 if (dirty
& WM_DIRTY_LINETIME(PIPE_A
))
2604 I915_WRITE(PIPE_WM_LINETIME(PIPE_A
), results
->wm_linetime
[0]);
2605 if (dirty
& WM_DIRTY_LINETIME(PIPE_B
))
2606 I915_WRITE(PIPE_WM_LINETIME(PIPE_B
), results
->wm_linetime
[1]);
2607 if (dirty
& WM_DIRTY_LINETIME(PIPE_C
))
2608 I915_WRITE(PIPE_WM_LINETIME(PIPE_C
), results
->wm_linetime
[2]);
2610 if (dirty
& WM_DIRTY_DDB
) {
2611 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
2612 val
= I915_READ(WM_MISC
);
2613 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2614 val
&= ~WM_MISC_DATA_PARTITION_5_6
;
2616 val
|= WM_MISC_DATA_PARTITION_5_6
;
2617 I915_WRITE(WM_MISC
, val
);
2619 val
= I915_READ(DISP_ARB_CTL2
);
2620 if (results
->partitioning
== INTEL_DDB_PART_1_2
)
2621 val
&= ~DISP_DATA_PARTITION_5_6
;
2623 val
|= DISP_DATA_PARTITION_5_6
;
2624 I915_WRITE(DISP_ARB_CTL2
, val
);
2628 if (dirty
& WM_DIRTY_FBC
) {
2629 val
= I915_READ(DISP_ARB_CTL
);
2630 if (results
->enable_fbc_wm
)
2631 val
&= ~DISP_FBC_WM_DIS
;
2633 val
|= DISP_FBC_WM_DIS
;
2634 I915_WRITE(DISP_ARB_CTL
, val
);
2637 if (dirty
& WM_DIRTY_LP(1) &&
2638 previous
->wm_lp_spr
[0] != results
->wm_lp_spr
[0])
2639 I915_WRITE(WM1S_LP_ILK
, results
->wm_lp_spr
[0]);
2641 if (INTEL_INFO(dev
)->gen
>= 7) {
2642 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp_spr
[1] != results
->wm_lp_spr
[1])
2643 I915_WRITE(WM2S_LP_IVB
, results
->wm_lp_spr
[1]);
2644 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp_spr
[2] != results
->wm_lp_spr
[2])
2645 I915_WRITE(WM3S_LP_IVB
, results
->wm_lp_spr
[2]);
2648 if (dirty
& WM_DIRTY_LP(1) && previous
->wm_lp
[0] != results
->wm_lp
[0])
2649 I915_WRITE(WM1_LP_ILK
, results
->wm_lp
[0]);
2650 if (dirty
& WM_DIRTY_LP(2) && previous
->wm_lp
[1] != results
->wm_lp
[1])
2651 I915_WRITE(WM2_LP_ILK
, results
->wm_lp
[1]);
2652 if (dirty
& WM_DIRTY_LP(3) && previous
->wm_lp
[2] != results
->wm_lp
[2])
2653 I915_WRITE(WM3_LP_ILK
, results
->wm_lp
[2]);
2655 dev_priv
->wm
.hw
= *results
;
2658 static bool ilk_disable_lp_wm(struct drm_device
*dev
)
2660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2662 return _ilk_disable_lp_wm(dev_priv
, WM_DIRTY_LP_ALL
);
2665 static void ilk_update_wm(struct drm_crtc
*crtc
)
2667 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2668 struct drm_device
*dev
= crtc
->dev
;
2669 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2670 struct ilk_wm_maximums max
;
2671 struct ilk_pipe_wm_parameters params
= {};
2672 struct ilk_wm_values results
= {};
2673 enum intel_ddb_partitioning partitioning
;
2674 struct intel_pipe_wm pipe_wm
= {};
2675 struct intel_pipe_wm lp_wm_1_2
= {}, lp_wm_5_6
= {}, *best_lp_wm
;
2676 struct intel_wm_config config
= {};
2678 ilk_compute_wm_parameters(crtc
, ¶ms
);
2680 intel_compute_pipe_wm(crtc
, ¶ms
, &pipe_wm
);
2682 if (!memcmp(&intel_crtc
->wm
.active
, &pipe_wm
, sizeof(pipe_wm
)))
2685 intel_crtc
->wm
.active
= pipe_wm
;
2687 ilk_compute_wm_config(dev
, &config
);
2689 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_1_2
, &max
);
2690 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_1_2
);
2692 /* 5/6 split only in single pipe config on IVB+ */
2693 if (INTEL_INFO(dev
)->gen
>= 7 &&
2694 config
.num_pipes_active
== 1 && config
.sprites_enabled
) {
2695 ilk_compute_wm_maximums(dev
, 1, &config
, INTEL_DDB_PART_5_6
, &max
);
2696 ilk_wm_merge(dev
, &config
, &max
, &lp_wm_5_6
);
2698 best_lp_wm
= ilk_find_best_result(dev
, &lp_wm_1_2
, &lp_wm_5_6
);
2700 best_lp_wm
= &lp_wm_1_2
;
2703 partitioning
= (best_lp_wm
== &lp_wm_1_2
) ?
2704 INTEL_DDB_PART_1_2
: INTEL_DDB_PART_5_6
;
2706 ilk_compute_wm_results(dev
, best_lp_wm
, partitioning
, &results
);
2708 ilk_write_wm_values(dev_priv
, &results
);
2711 static void ilk_update_sprite_wm(struct drm_plane
*plane
,
2712 struct drm_crtc
*crtc
,
2713 uint32_t sprite_width
, int pixel_size
,
2714 bool enabled
, bool scaled
)
2716 struct drm_device
*dev
= plane
->dev
;
2717 struct intel_plane
*intel_plane
= to_intel_plane(plane
);
2719 intel_plane
->wm
.enabled
= enabled
;
2720 intel_plane
->wm
.scaled
= scaled
;
2721 intel_plane
->wm
.horiz_pixels
= sprite_width
;
2722 intel_plane
->wm
.bytes_per_pixel
= pixel_size
;
2725 * IVB workaround: must disable low power watermarks for at least
2726 * one frame before enabling scaling. LP watermarks can be re-enabled
2727 * when scaling is disabled.
2729 * WaCxSRDisabledForSpriteScaling:ivb
2731 if (IS_IVYBRIDGE(dev
) && scaled
&& ilk_disable_lp_wm(dev
))
2732 intel_wait_for_vblank(dev
, intel_plane
->pipe
);
2734 ilk_update_wm(crtc
);
2737 static void ilk_pipe_wm_get_hw_state(struct drm_crtc
*crtc
)
2739 struct drm_device
*dev
= crtc
->dev
;
2740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2741 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2742 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2743 struct intel_pipe_wm
*active
= &intel_crtc
->wm
.active
;
2744 enum pipe pipe
= intel_crtc
->pipe
;
2745 static const unsigned int wm0_pipe_reg
[] = {
2746 [PIPE_A
] = WM0_PIPEA_ILK
,
2747 [PIPE_B
] = WM0_PIPEB_ILK
,
2748 [PIPE_C
] = WM0_PIPEC_IVB
,
2751 hw
->wm_pipe
[pipe
] = I915_READ(wm0_pipe_reg
[pipe
]);
2752 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2753 hw
->wm_linetime
[pipe
] = I915_READ(PIPE_WM_LINETIME(pipe
));
2755 active
->pipe_enabled
= intel_crtc_active(crtc
);
2757 if (active
->pipe_enabled
) {
2758 u32 tmp
= hw
->wm_pipe
[pipe
];
2761 * For active pipes LP0 watermark is marked as
2762 * enabled, and LP1+ watermaks as disabled since
2763 * we can't really reverse compute them in case
2764 * multiple pipes are active.
2766 active
->wm
[0].enable
= true;
2767 active
->wm
[0].pri_val
= (tmp
& WM0_PIPE_PLANE_MASK
) >> WM0_PIPE_PLANE_SHIFT
;
2768 active
->wm
[0].spr_val
= (tmp
& WM0_PIPE_SPRITE_MASK
) >> WM0_PIPE_SPRITE_SHIFT
;
2769 active
->wm
[0].cur_val
= tmp
& WM0_PIPE_CURSOR_MASK
;
2770 active
->linetime
= hw
->wm_linetime
[pipe
];
2772 int level
, max_level
= ilk_wm_max_level(dev
);
2775 * For inactive pipes, all watermark levels
2776 * should be marked as enabled but zeroed,
2777 * which is what we'd compute them to.
2779 for (level
= 0; level
<= max_level
; level
++)
2780 active
->wm
[level
].enable
= true;
2784 void ilk_wm_get_hw_state(struct drm_device
*dev
)
2786 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2787 struct ilk_wm_values
*hw
= &dev_priv
->wm
.hw
;
2788 struct drm_crtc
*crtc
;
2790 for_each_crtc(dev
, crtc
)
2791 ilk_pipe_wm_get_hw_state(crtc
);
2793 hw
->wm_lp
[0] = I915_READ(WM1_LP_ILK
);
2794 hw
->wm_lp
[1] = I915_READ(WM2_LP_ILK
);
2795 hw
->wm_lp
[2] = I915_READ(WM3_LP_ILK
);
2797 hw
->wm_lp_spr
[0] = I915_READ(WM1S_LP_ILK
);
2798 if (INTEL_INFO(dev
)->gen
>= 7) {
2799 hw
->wm_lp_spr
[1] = I915_READ(WM2S_LP_IVB
);
2800 hw
->wm_lp_spr
[2] = I915_READ(WM3S_LP_IVB
);
2803 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
2804 hw
->partitioning
= (I915_READ(WM_MISC
) & WM_MISC_DATA_PARTITION_5_6
) ?
2805 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
2806 else if (IS_IVYBRIDGE(dev
))
2807 hw
->partitioning
= (I915_READ(DISP_ARB_CTL2
) & DISP_DATA_PARTITION_5_6
) ?
2808 INTEL_DDB_PART_5_6
: INTEL_DDB_PART_1_2
;
2811 !(I915_READ(DISP_ARB_CTL
) & DISP_FBC_WM_DIS
);
2815 * intel_update_watermarks - update FIFO watermark values based on current modes
2817 * Calculate watermark values for the various WM regs based on current mode
2818 * and plane configuration.
2820 * There are several cases to deal with here:
2821 * - normal (i.e. non-self-refresh)
2822 * - self-refresh (SR) mode
2823 * - lines are large relative to FIFO size (buffer can hold up to 2)
2824 * - lines are small relative to FIFO size (buffer can hold more than 2
2825 * lines), so need to account for TLB latency
2827 * The normal calculation is:
2828 * watermark = dotclock * bytes per pixel * latency
2829 * where latency is platform & configuration dependent (we assume pessimal
2832 * The SR calculation is:
2833 * watermark = (trunc(latency/line time)+1) * surface width *
2836 * line time = htotal / dotclock
2837 * surface width = hdisplay for normal plane and 64 for cursor
2838 * and latency is assumed to be high, as above.
2840 * The final value programmed to the register should always be rounded up,
2841 * and include an extra 2 entries to account for clock crossings.
2843 * We don't use the sprite, so we can ignore that. And on Crestline we have
2844 * to set the non-SR watermarks to 8.
2846 void intel_update_watermarks(struct drm_crtc
*crtc
)
2848 struct drm_i915_private
*dev_priv
= crtc
->dev
->dev_private
;
2850 if (dev_priv
->display
.update_wm
)
2851 dev_priv
->display
.update_wm(crtc
);
2854 void intel_update_sprite_watermarks(struct drm_plane
*plane
,
2855 struct drm_crtc
*crtc
,
2856 uint32_t sprite_width
, int pixel_size
,
2857 bool enabled
, bool scaled
)
2859 struct drm_i915_private
*dev_priv
= plane
->dev
->dev_private
;
2861 if (dev_priv
->display
.update_sprite_wm
)
2862 dev_priv
->display
.update_sprite_wm(plane
, crtc
, sprite_width
,
2863 pixel_size
, enabled
, scaled
);
2866 static struct drm_i915_gem_object
*
2867 intel_alloc_context_page(struct drm_device
*dev
)
2869 struct drm_i915_gem_object
*ctx
;
2872 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
2874 ctx
= i915_gem_alloc_object(dev
, 4096);
2876 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2880 ret
= i915_gem_obj_ggtt_pin(ctx
, 4096, 0);
2882 DRM_ERROR("failed to pin power context: %d\n", ret
);
2886 ret
= i915_gem_object_set_to_gtt_domain(ctx
, 1);
2888 DRM_ERROR("failed to set-domain on power context: %d\n", ret
);
2895 i915_gem_object_ggtt_unpin(ctx
);
2897 drm_gem_object_unreference(&ctx
->base
);
2902 * Lock protecting IPS related data structures
2904 DEFINE_SPINLOCK(mchdev_lock
);
2906 /* Global for IPS driver to get at the current i915 device. Protected by
2908 static struct drm_i915_private
*i915_mch_dev
;
2910 bool ironlake_set_drps(struct drm_device
*dev
, u8 val
)
2912 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2915 assert_spin_locked(&mchdev_lock
);
2917 rgvswctl
= I915_READ16(MEMSWCTL
);
2918 if (rgvswctl
& MEMCTL_CMD_STS
) {
2919 DRM_DEBUG("gpu busy, RCS change rejected\n");
2920 return false; /* still busy with another command */
2923 rgvswctl
= (MEMCTL_CMD_CHFREQ
<< MEMCTL_CMD_SHIFT
) |
2924 (val
<< MEMCTL_FREQ_SHIFT
) | MEMCTL_SFCAVM
;
2925 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2926 POSTING_READ16(MEMSWCTL
);
2928 rgvswctl
|= MEMCTL_CMD_STS
;
2929 I915_WRITE16(MEMSWCTL
, rgvswctl
);
2934 static void ironlake_enable_drps(struct drm_device
*dev
)
2936 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2937 u32 rgvmodectl
= I915_READ(MEMMODECTL
);
2938 u8 fmax
, fmin
, fstart
, vstart
;
2940 spin_lock_irq(&mchdev_lock
);
2942 /* Enable temp reporting */
2943 I915_WRITE16(PMMISC
, I915_READ(PMMISC
) | MCPPCE_EN
);
2944 I915_WRITE16(TSC1
, I915_READ(TSC1
) | TSE
);
2946 /* 100ms RC evaluation intervals */
2947 I915_WRITE(RCUPEI
, 100000);
2948 I915_WRITE(RCDNEI
, 100000);
2950 /* Set max/min thresholds to 90ms and 80ms respectively */
2951 I915_WRITE(RCBMAXAVG
, 90000);
2952 I915_WRITE(RCBMINAVG
, 80000);
2954 I915_WRITE(MEMIHYST
, 1);
2956 /* Set up min, max, and cur for interrupt handling */
2957 fmax
= (rgvmodectl
& MEMMODE_FMAX_MASK
) >> MEMMODE_FMAX_SHIFT
;
2958 fmin
= (rgvmodectl
& MEMMODE_FMIN_MASK
);
2959 fstart
= (rgvmodectl
& MEMMODE_FSTART_MASK
) >>
2960 MEMMODE_FSTART_SHIFT
;
2962 vstart
= (I915_READ(PXVFREQ_BASE
+ (fstart
* 4)) & PXVFREQ_PX_MASK
) >>
2965 dev_priv
->ips
.fmax
= fmax
; /* IPS callback will increase this */
2966 dev_priv
->ips
.fstart
= fstart
;
2968 dev_priv
->ips
.max_delay
= fstart
;
2969 dev_priv
->ips
.min_delay
= fmin
;
2970 dev_priv
->ips
.cur_delay
= fstart
;
2972 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2973 fmax
, fmin
, fstart
);
2975 I915_WRITE(MEMINTREN
, MEMINT_CX_SUPR_EN
| MEMINT_EVAL_CHG_EN
);
2978 * Interrupts will be enabled in ironlake_irq_postinstall
2981 I915_WRITE(VIDSTART
, vstart
);
2982 POSTING_READ(VIDSTART
);
2984 rgvmodectl
|= MEMMODE_SWMODE_EN
;
2985 I915_WRITE(MEMMODECTL
, rgvmodectl
);
2987 if (wait_for_atomic((I915_READ(MEMSWCTL
) & MEMCTL_CMD_STS
) == 0, 10))
2988 DRM_ERROR("stuck trying to change perf mode\n");
2991 ironlake_set_drps(dev
, fstart
);
2993 dev_priv
->ips
.last_count1
= I915_READ(0x112e4) + I915_READ(0x112e8) +
2995 dev_priv
->ips
.last_time1
= jiffies_to_msecs(jiffies
);
2996 dev_priv
->ips
.last_count2
= I915_READ(0x112f4);
2997 getrawmonotonic(&dev_priv
->ips
.last_time2
);
2999 spin_unlock_irq(&mchdev_lock
);
3002 static void ironlake_disable_drps(struct drm_device
*dev
)
3004 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3007 spin_lock_irq(&mchdev_lock
);
3009 rgvswctl
= I915_READ16(MEMSWCTL
);
3011 /* Ack interrupts, disable EFC interrupt */
3012 I915_WRITE(MEMINTREN
, I915_READ(MEMINTREN
) & ~MEMINT_EVAL_CHG_EN
);
3013 I915_WRITE(MEMINTRSTS
, MEMINT_EVAL_CHG
);
3014 I915_WRITE(DEIER
, I915_READ(DEIER
) & ~DE_PCU_EVENT
);
3015 I915_WRITE(DEIIR
, DE_PCU_EVENT
);
3016 I915_WRITE(DEIMR
, I915_READ(DEIMR
) | DE_PCU_EVENT
);
3018 /* Go back to the starting frequency */
3019 ironlake_set_drps(dev
, dev_priv
->ips
.fstart
);
3021 rgvswctl
|= MEMCTL_CMD_STS
;
3022 I915_WRITE(MEMSWCTL
, rgvswctl
);
3025 spin_unlock_irq(&mchdev_lock
);
3028 /* There's a funny hw issue where the hw returns all 0 when reading from
3029 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3030 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3031 * all limits and the gpu stuck at whatever frequency it is at atm).
3033 static u32
gen6_rps_limits(struct drm_i915_private
*dev_priv
, u8 val
)
3037 /* Only set the down limit when we've reached the lowest level to avoid
3038 * getting more interrupts, otherwise leave this clear. This prevents a
3039 * race in the hw when coming out of rc6: There's a tiny window where
3040 * the hw runs at the minimal clock before selecting the desired
3041 * frequency, if the down threshold expires in that window we will not
3042 * receive a down interrupt. */
3043 limits
= dev_priv
->rps
.max_freq_softlimit
<< 24;
3044 if (val
<= dev_priv
->rps
.min_freq_softlimit
)
3045 limits
|= dev_priv
->rps
.min_freq_softlimit
<< 16;
3050 static void gen6_set_rps_thresholds(struct drm_i915_private
*dev_priv
, u8 val
)
3054 new_power
= dev_priv
->rps
.power
;
3055 switch (dev_priv
->rps
.power
) {
3057 if (val
> dev_priv
->rps
.efficient_freq
+ 1 && val
> dev_priv
->rps
.cur_freq
)
3058 new_power
= BETWEEN
;
3062 if (val
<= dev_priv
->rps
.efficient_freq
&& val
< dev_priv
->rps
.cur_freq
)
3063 new_power
= LOW_POWER
;
3064 else if (val
>= dev_priv
->rps
.rp0_freq
&& val
> dev_priv
->rps
.cur_freq
)
3065 new_power
= HIGH_POWER
;
3069 if (val
< (dev_priv
->rps
.rp1_freq
+ dev_priv
->rps
.rp0_freq
) >> 1 && val
< dev_priv
->rps
.cur_freq
)
3070 new_power
= BETWEEN
;
3073 /* Max/min bins are special */
3074 if (val
== dev_priv
->rps
.min_freq_softlimit
)
3075 new_power
= LOW_POWER
;
3076 if (val
== dev_priv
->rps
.max_freq_softlimit
)
3077 new_power
= HIGH_POWER
;
3078 if (new_power
== dev_priv
->rps
.power
)
3081 /* Note the units here are not exactly 1us, but 1280ns. */
3082 switch (new_power
) {
3084 /* Upclock if more than 95% busy over 16ms */
3085 I915_WRITE(GEN6_RP_UP_EI
, 12500);
3086 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 11800);
3088 /* Downclock if less than 85% busy over 32ms */
3089 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3090 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 21250);
3092 I915_WRITE(GEN6_RP_CONTROL
,
3093 GEN6_RP_MEDIA_TURBO
|
3094 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3095 GEN6_RP_MEDIA_IS_GFX
|
3097 GEN6_RP_UP_BUSY_AVG
|
3098 GEN6_RP_DOWN_IDLE_AVG
);
3102 /* Upclock if more than 90% busy over 13ms */
3103 I915_WRITE(GEN6_RP_UP_EI
, 10250);
3104 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 9225);
3106 /* Downclock if less than 75% busy over 32ms */
3107 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3108 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 18750);
3110 I915_WRITE(GEN6_RP_CONTROL
,
3111 GEN6_RP_MEDIA_TURBO
|
3112 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3113 GEN6_RP_MEDIA_IS_GFX
|
3115 GEN6_RP_UP_BUSY_AVG
|
3116 GEN6_RP_DOWN_IDLE_AVG
);
3120 /* Upclock if more than 85% busy over 10ms */
3121 I915_WRITE(GEN6_RP_UP_EI
, 8000);
3122 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 6800);
3124 /* Downclock if less than 60% busy over 32ms */
3125 I915_WRITE(GEN6_RP_DOWN_EI
, 25000);
3126 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 15000);
3128 I915_WRITE(GEN6_RP_CONTROL
,
3129 GEN6_RP_MEDIA_TURBO
|
3130 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3131 GEN6_RP_MEDIA_IS_GFX
|
3133 GEN6_RP_UP_BUSY_AVG
|
3134 GEN6_RP_DOWN_IDLE_AVG
);
3138 dev_priv
->rps
.power
= new_power
;
3139 dev_priv
->rps
.last_adj
= 0;
3142 static u32
gen6_rps_pm_mask(struct drm_i915_private
*dev_priv
, u8 val
)
3146 if (val
> dev_priv
->rps
.min_freq_softlimit
)
3147 mask
|= GEN6_PM_RP_DOWN_THRESHOLD
| GEN6_PM_RP_DOWN_TIMEOUT
;
3148 if (val
< dev_priv
->rps
.max_freq_softlimit
)
3149 mask
|= GEN6_PM_RP_UP_THRESHOLD
;
3151 /* IVB and SNB hard hangs on looping batchbuffer
3152 * if GEN6_PM_UP_EI_EXPIRED is masked.
3154 if (INTEL_INFO(dev_priv
->dev
)->gen
<= 7 && !IS_HASWELL(dev_priv
->dev
))
3155 mask
|= GEN6_PM_RP_UP_EI_EXPIRED
;
3157 if (IS_GEN8(dev_priv
->dev
))
3158 mask
|= GEN8_PMINTR_REDIRECT_TO_NON_DISP
;
3163 /* gen6_set_rps is called to update the frequency request, but should also be
3164 * called when the range (min_delay and max_delay) is modified so that we can
3165 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
3166 void gen6_set_rps(struct drm_device
*dev
, u8 val
)
3168 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3170 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3171 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3172 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3174 /* min/max delay may still have been modified so be sure to
3175 * write the limits value.
3177 if (val
!= dev_priv
->rps
.cur_freq
) {
3178 gen6_set_rps_thresholds(dev_priv
, val
);
3180 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
3181 I915_WRITE(GEN6_RPNSWREQ
,
3182 HSW_FREQUENCY(val
));
3184 I915_WRITE(GEN6_RPNSWREQ
,
3185 GEN6_FREQUENCY(val
) |
3187 GEN6_AGGRESSIVE_TURBO
);
3190 /* Make sure we continue to get interrupts
3191 * until we hit the minimum or maximum frequencies.
3193 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
, gen6_rps_limits(dev_priv
, val
));
3194 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3196 POSTING_READ(GEN6_RPNSWREQ
);
3198 dev_priv
->rps
.cur_freq
= val
;
3199 trace_intel_gpu_freq_change(val
* 50);
3202 /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down
3204 * * If Gfx is Idle, then
3205 * 1. Mask Turbo interrupts
3206 * 2. Bring up Gfx clock
3207 * 3. Change the freq to Rpn and wait till P-Unit updates freq
3208 * 4. Clear the Force GFX CLK ON bit so that Gfx can down
3209 * 5. Unmask Turbo interrupts
3211 static void vlv_set_rps_idle(struct drm_i915_private
*dev_priv
)
3214 * When we are idle. Drop to min voltage state.
3217 if (dev_priv
->rps
.cur_freq
<= dev_priv
->rps
.min_freq_softlimit
)
3220 /* Mask turbo interrupt so that they will not come in between */
3221 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3223 vlv_force_gfx_clock(dev_priv
, true);
3225 dev_priv
->rps
.cur_freq
= dev_priv
->rps
.min_freq_softlimit
;
3227 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
,
3228 dev_priv
->rps
.min_freq_softlimit
);
3230 if (wait_for(((vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
))
3231 & GENFREQSTATUS
) == 0, 5))
3232 DRM_ERROR("timed out waiting for Punit\n");
3234 vlv_force_gfx_clock(dev_priv
, false);
3236 I915_WRITE(GEN6_PMINTRMSK
,
3237 gen6_rps_pm_mask(dev_priv
, dev_priv
->rps
.cur_freq
));
3240 void gen6_rps_idle(struct drm_i915_private
*dev_priv
)
3242 struct drm_device
*dev
= dev_priv
->dev
;
3244 mutex_lock(&dev_priv
->rps
.hw_lock
);
3245 if (dev_priv
->rps
.enabled
) {
3246 if (IS_VALLEYVIEW(dev
))
3247 vlv_set_rps_idle(dev_priv
);
3249 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3250 dev_priv
->rps
.last_adj
= 0;
3252 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3255 void gen6_rps_boost(struct drm_i915_private
*dev_priv
)
3257 struct drm_device
*dev
= dev_priv
->dev
;
3259 mutex_lock(&dev_priv
->rps
.hw_lock
);
3260 if (dev_priv
->rps
.enabled
) {
3261 if (IS_VALLEYVIEW(dev
))
3262 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3264 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.max_freq_softlimit
);
3265 dev_priv
->rps
.last_adj
= 0;
3267 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3270 void valleyview_set_rps(struct drm_device
*dev
, u8 val
)
3272 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3274 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3275 WARN_ON(val
> dev_priv
->rps
.max_freq_softlimit
);
3276 WARN_ON(val
< dev_priv
->rps
.min_freq_softlimit
);
3278 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
3279 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
3280 dev_priv
->rps
.cur_freq
,
3281 vlv_gpu_freq(dev_priv
, val
), val
);
3283 if (val
!= dev_priv
->rps
.cur_freq
)
3284 vlv_punit_write(dev_priv
, PUNIT_REG_GPU_FREQ_REQ
, val
);
3286 I915_WRITE(GEN6_PMINTRMSK
, gen6_rps_pm_mask(dev_priv
, val
));
3288 dev_priv
->rps
.cur_freq
= val
;
3289 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv
, val
));
3292 static void gen8_disable_rps_interrupts(struct drm_device
*dev
)
3294 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3296 I915_WRITE(GEN6_PMINTRMSK
, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP
);
3297 I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) &
3298 ~dev_priv
->pm_rps_events
);
3299 /* Complete PM interrupt masking here doesn't race with the rps work
3300 * item again unmasking PM interrupts because that is using a different
3301 * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in
3302 * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which
3303 * gen8_enable_rps will clean up. */
3305 spin_lock_irq(&dev_priv
->irq_lock
);
3306 dev_priv
->rps
.pm_iir
= 0;
3307 spin_unlock_irq(&dev_priv
->irq_lock
);
3309 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3312 static void gen6_disable_rps_interrupts(struct drm_device
*dev
)
3314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3316 I915_WRITE(GEN6_PMINTRMSK
, 0xffffffff);
3317 I915_WRITE(GEN6_PMIER
, I915_READ(GEN6_PMIER
) &
3318 ~dev_priv
->pm_rps_events
);
3319 /* Complete PM interrupt masking here doesn't race with the rps work
3320 * item again unmasking PM interrupts because that is using a different
3321 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3322 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3324 spin_lock_irq(&dev_priv
->irq_lock
);
3325 dev_priv
->rps
.pm_iir
= 0;
3326 spin_unlock_irq(&dev_priv
->irq_lock
);
3328 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3331 static void gen6_disable_rps(struct drm_device
*dev
)
3333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3335 I915_WRITE(GEN6_RC_CONTROL
, 0);
3336 I915_WRITE(GEN6_RPNSWREQ
, 1 << 31);
3338 if (IS_BROADWELL(dev
))
3339 gen8_disable_rps_interrupts(dev
);
3341 gen6_disable_rps_interrupts(dev
);
3344 static void cherryview_disable_rps(struct drm_device
*dev
)
3346 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3348 I915_WRITE(GEN6_RC_CONTROL
, 0);
3351 static void valleyview_disable_rps(struct drm_device
*dev
)
3353 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3355 I915_WRITE(GEN6_RC_CONTROL
, 0);
3357 gen6_disable_rps_interrupts(dev
);
3360 static void intel_print_rc6_info(struct drm_device
*dev
, u32 mode
)
3362 if (IS_VALLEYVIEW(dev
)) {
3363 if (mode
& (GEN7_RC_CTL_TO_MODE
| GEN6_RC_CTL_EI_MODE(1)))
3364 mode
= GEN6_RC_CTL_RC6_ENABLE
;
3368 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3369 (mode
& GEN6_RC_CTL_RC6_ENABLE
) ? "on" : "off",
3370 (mode
& GEN6_RC_CTL_RC6p_ENABLE
) ? "on" : "off",
3371 (mode
& GEN6_RC_CTL_RC6pp_ENABLE
) ? "on" : "off");
3374 static int sanitize_rc6_option(const struct drm_device
*dev
, int enable_rc6
)
3376 /* No RC6 before Ironlake */
3377 if (INTEL_INFO(dev
)->gen
< 5)
3380 /* RC6 is only on Ironlake mobile not on desktop */
3381 if (INTEL_INFO(dev
)->gen
== 5 && !IS_IRONLAKE_M(dev
))
3384 /* Respect the kernel parameter if it is set */
3385 if (enable_rc6
>= 0) {
3388 if (INTEL_INFO(dev
)->gen
== 6 || IS_IVYBRIDGE(dev
))
3389 mask
= INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
|
3392 mask
= INTEL_RC6_ENABLE
;
3394 if ((enable_rc6
& mask
) != enable_rc6
)
3395 DRM_INFO("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
3396 enable_rc6
& mask
, enable_rc6
, mask
);
3398 return enable_rc6
& mask
;
3401 /* Disable RC6 on Ironlake */
3402 if (INTEL_INFO(dev
)->gen
== 5)
3405 if (IS_IVYBRIDGE(dev
))
3406 return (INTEL_RC6_ENABLE
| INTEL_RC6p_ENABLE
);
3408 return INTEL_RC6_ENABLE
;
3411 int intel_enable_rc6(const struct drm_device
*dev
)
3413 return i915
.enable_rc6
;
3416 static void gen8_enable_rps_interrupts(struct drm_device
*dev
)
3418 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3420 spin_lock_irq(&dev_priv
->irq_lock
);
3421 WARN_ON(dev_priv
->rps
.pm_iir
);
3422 bdw_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3423 I915_WRITE(GEN8_GT_IIR(2), dev_priv
->pm_rps_events
);
3424 spin_unlock_irq(&dev_priv
->irq_lock
);
3427 static void gen6_enable_rps_interrupts(struct drm_device
*dev
)
3429 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3431 spin_lock_irq(&dev_priv
->irq_lock
);
3432 WARN_ON(dev_priv
->rps
.pm_iir
);
3433 snb_enable_pm_irq(dev_priv
, dev_priv
->pm_rps_events
);
3434 I915_WRITE(GEN6_PMIIR
, dev_priv
->pm_rps_events
);
3435 spin_unlock_irq(&dev_priv
->irq_lock
);
3438 static void parse_rp_state_cap(struct drm_i915_private
*dev_priv
, u32 rp_state_cap
)
3440 /* All of these values are in units of 50MHz */
3441 dev_priv
->rps
.cur_freq
= 0;
3442 /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */
3443 dev_priv
->rps
.rp1_freq
= (rp_state_cap
>> 8) & 0xff;
3444 dev_priv
->rps
.rp0_freq
= (rp_state_cap
>> 0) & 0xff;
3445 dev_priv
->rps
.min_freq
= (rp_state_cap
>> 16) & 0xff;
3446 /* XXX: only BYT has a special efficient freq */
3447 dev_priv
->rps
.efficient_freq
= dev_priv
->rps
.rp1_freq
;
3448 /* hw_max = RP0 until we check for overclocking */
3449 dev_priv
->rps
.max_freq
= dev_priv
->rps
.rp0_freq
;
3451 /* Preserve min/max settings in case of re-init */
3452 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3453 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3455 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3456 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
3459 static void gen8_enable_rps(struct drm_device
*dev
)
3461 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3462 struct intel_engine_cs
*ring
;
3463 uint32_t rc6_mask
= 0, rp_state_cap
;
3466 /* 1a: Software RC state - RC0 */
3467 I915_WRITE(GEN6_RC_STATE
, 0);
3469 /* 1c & 1d: Get forcewake during program sequence. Although the driver
3470 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3471 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3473 /* 2a: Disable RC states. */
3474 I915_WRITE(GEN6_RC_CONTROL
, 0);
3476 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3477 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3479 /* 2b: Program RC6 thresholds.*/
3480 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
3481 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
3482 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
3483 for_each_ring(ring
, dev_priv
, unused
)
3484 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3485 I915_WRITE(GEN6_RC_SLEEP
, 0);
3486 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
3489 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
3490 rc6_mask
= GEN6_RC_CTL_RC6_ENABLE
;
3491 intel_print_rc6_info(dev
, rc6_mask
);
3492 I915_WRITE(GEN6_RC_CONTROL
, GEN6_RC_CTL_HW_ENABLE
|
3493 GEN6_RC_CTL_EI_MODE(1) |
3496 /* 4 Program defaults and thresholds for RPS*/
3497 I915_WRITE(GEN6_RPNSWREQ
,
3498 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3499 I915_WRITE(GEN6_RC_VIDEO_FREQ
,
3500 HSW_FREQUENCY(dev_priv
->rps
.rp1_freq
));
3501 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
3502 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 100000000 / 128); /* 1 second timeout */
3504 /* Docs recommend 900MHz, and 300 MHz respectively */
3505 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS
,
3506 dev_priv
->rps
.max_freq_softlimit
<< 24 |
3507 dev_priv
->rps
.min_freq_softlimit
<< 16);
3509 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 7600000 / 128); /* 76ms busyness per EI, 90% */
3510 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 31300000 / 128); /* 313ms busyness per EI, 70%*/
3511 I915_WRITE(GEN6_RP_UP_EI
, 66000); /* 84.48ms, XXX: random? */
3512 I915_WRITE(GEN6_RP_DOWN_EI
, 350000); /* 448ms, XXX: random? */
3514 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3517 I915_WRITE(GEN6_RP_CONTROL
,
3518 GEN6_RP_MEDIA_TURBO
|
3519 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
3520 GEN6_RP_MEDIA_IS_GFX
|
3522 GEN6_RP_UP_BUSY_AVG
|
3523 GEN6_RP_DOWN_IDLE_AVG
);
3525 /* 6: Ring frequency + overclocking (our driver does this later */
3527 gen6_set_rps(dev
, (I915_READ(GEN6_GT_PERF_STATUS
) & 0xff00) >> 8);
3529 gen8_enable_rps_interrupts(dev
);
3531 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3534 static void gen6_enable_rps(struct drm_device
*dev
)
3536 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3537 struct intel_engine_cs
*ring
;
3540 u32 rc6vids
, pcu_mbox
= 0, rc6_mask
= 0;
3545 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3547 /* Here begins a magic sequence of register writes to enable
3548 * auto-downclocking.
3550 * Perhaps there might be some value in exposing these to
3553 I915_WRITE(GEN6_RC_STATE
, 0);
3555 /* Clear the DBG now so we don't confuse earlier errors */
3556 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
3557 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg
);
3558 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3561 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3563 rp_state_cap
= I915_READ(GEN6_RP_STATE_CAP
);
3564 gt_perf_status
= I915_READ(GEN6_GT_PERF_STATUS
);
3566 parse_rp_state_cap(dev_priv
, rp_state_cap
);
3568 /* disable the counters and set deterministic thresholds */
3569 I915_WRITE(GEN6_RC_CONTROL
, 0);
3571 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT
, 1000 << 16);
3572 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16 | 30);
3573 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT
, 30);
3574 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
3575 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
3577 for_each_ring(ring
, dev_priv
, i
)
3578 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3580 I915_WRITE(GEN6_RC_SLEEP
, 0);
3581 I915_WRITE(GEN6_RC1e_THRESHOLD
, 1000);
3582 if (IS_IVYBRIDGE(dev
))
3583 I915_WRITE(GEN6_RC6_THRESHOLD
, 125000);
3585 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000);
3586 I915_WRITE(GEN6_RC6p_THRESHOLD
, 150000);
3587 I915_WRITE(GEN6_RC6pp_THRESHOLD
, 64000); /* unused */
3589 /* Check if we are enabling RC6 */
3590 rc6_mode
= intel_enable_rc6(dev_priv
->dev
);
3591 if (rc6_mode
& INTEL_RC6_ENABLE
)
3592 rc6_mask
|= GEN6_RC_CTL_RC6_ENABLE
;
3594 /* We don't use those on Haswell */
3595 if (!IS_HASWELL(dev
)) {
3596 if (rc6_mode
& INTEL_RC6p_ENABLE
)
3597 rc6_mask
|= GEN6_RC_CTL_RC6p_ENABLE
;
3599 if (rc6_mode
& INTEL_RC6pp_ENABLE
)
3600 rc6_mask
|= GEN6_RC_CTL_RC6pp_ENABLE
;
3603 intel_print_rc6_info(dev
, rc6_mask
);
3605 I915_WRITE(GEN6_RC_CONTROL
,
3607 GEN6_RC_CTL_EI_MODE(1) |
3608 GEN6_RC_CTL_HW_ENABLE
);
3610 /* Power down if completely idle for over 50ms */
3611 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
, 50000);
3612 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
3614 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_MIN_FREQ_TABLE
, 0);
3616 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
3618 ret
= sandybridge_pcode_read(dev_priv
, GEN6_READ_OC_PARAMS
, &pcu_mbox
);
3619 if (!ret
&& (pcu_mbox
& (1<<31))) { /* OC supported */
3620 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
3621 (dev_priv
->rps
.max_freq_softlimit
& 0xff) * 50,
3622 (pcu_mbox
& 0xff) * 50);
3623 dev_priv
->rps
.max_freq
= pcu_mbox
& 0xff;
3626 dev_priv
->rps
.power
= HIGH_POWER
; /* force a reset */
3627 gen6_set_rps(dev_priv
->dev
, dev_priv
->rps
.min_freq_softlimit
);
3629 gen6_enable_rps_interrupts(dev
);
3632 ret
= sandybridge_pcode_read(dev_priv
, GEN6_PCODE_READ_RC6VIDS
, &rc6vids
);
3633 if (IS_GEN6(dev
) && ret
) {
3634 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3635 } else if (IS_GEN6(dev
) && (GEN6_DECODE_RC6_VID(rc6vids
& 0xff) < 450)) {
3636 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3637 GEN6_DECODE_RC6_VID(rc6vids
& 0xff), 450);
3638 rc6vids
&= 0xffff00;
3639 rc6vids
|= GEN6_ENCODE_RC6_VID(450);
3640 ret
= sandybridge_pcode_write(dev_priv
, GEN6_PCODE_WRITE_RC6VIDS
, rc6vids
);
3642 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3645 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
3648 static void __gen6_update_ring_freq(struct drm_device
*dev
)
3650 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3652 unsigned int gpu_freq
;
3653 unsigned int max_ia_freq
, min_ring_freq
;
3654 int scaling_factor
= 180;
3655 struct cpufreq_policy
*policy
;
3657 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3659 policy
= cpufreq_cpu_get(0);
3661 max_ia_freq
= policy
->cpuinfo
.max_freq
;
3662 cpufreq_cpu_put(policy
);
3665 * Default to measured freq if none found, PCU will ensure we
3668 max_ia_freq
= tsc_khz
;
3671 /* Convert from kHz to MHz */
3672 max_ia_freq
/= 1000;
3674 min_ring_freq
= I915_READ(DCLK
) & 0xf;
3675 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3676 min_ring_freq
= mult_frac(min_ring_freq
, 8, 3);
3679 * For each potential GPU frequency, load a ring frequency we'd like
3680 * to use for memory access. We do this by specifying the IA frequency
3681 * the PCU should use as a reference to determine the ring frequency.
3683 for (gpu_freq
= dev_priv
->rps
.max_freq_softlimit
; gpu_freq
>= dev_priv
->rps
.min_freq_softlimit
;
3685 int diff
= dev_priv
->rps
.max_freq_softlimit
- gpu_freq
;
3686 unsigned int ia_freq
= 0, ring_freq
= 0;
3688 if (INTEL_INFO(dev
)->gen
>= 8) {
3689 /* max(2 * GT, DDR). NB: GT is 50MHz units */
3690 ring_freq
= max(min_ring_freq
, gpu_freq
);
3691 } else if (IS_HASWELL(dev
)) {
3692 ring_freq
= mult_frac(gpu_freq
, 5, 4);
3693 ring_freq
= max(min_ring_freq
, ring_freq
);
3694 /* leave ia_freq as the default, chosen by cpufreq */
3696 /* On older processors, there is no separate ring
3697 * clock domain, so in order to boost the bandwidth
3698 * of the ring, we need to upclock the CPU (ia_freq).
3700 * For GPU frequencies less than 750MHz,
3701 * just use the lowest ring freq.
3703 if (gpu_freq
< min_freq
)
3706 ia_freq
= max_ia_freq
- ((diff
* scaling_factor
) / 2);
3707 ia_freq
= DIV_ROUND_CLOSEST(ia_freq
, 100);
3710 sandybridge_pcode_write(dev_priv
,
3711 GEN6_PCODE_WRITE_MIN_FREQ_TABLE
,
3712 ia_freq
<< GEN6_PCODE_FREQ_IA_RATIO_SHIFT
|
3713 ring_freq
<< GEN6_PCODE_FREQ_RING_RATIO_SHIFT
|
3718 void gen6_update_ring_freq(struct drm_device
*dev
)
3720 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3722 if (INTEL_INFO(dev
)->gen
< 6 || IS_VALLEYVIEW(dev
))
3725 mutex_lock(&dev_priv
->rps
.hw_lock
);
3726 __gen6_update_ring_freq(dev
);
3727 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3730 int cherryview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3734 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
3735 rp0
= (val
>> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT
) & PUNIT_GPU_STATUS_MAX_FREQ_MASK
;
3740 static int cherryview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3744 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_DUTYCYCLE_REG
);
3745 rpe
= (val
>> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT
) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK
;
3750 int cherryview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3754 val
= vlv_punit_read(dev_priv
, PUNIT_GPU_STATUS_REG
);
3755 rpn
= (val
>> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT
) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK
;
3759 int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
)
3763 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FREQ_FUSE
);
3765 rp0
= (val
& FB_GFX_MAX_FREQ_FUSE_MASK
) >> FB_GFX_MAX_FREQ_FUSE_SHIFT
;
3767 rp0
= min_t(u32
, rp0
, 0xea);
3772 static int valleyview_rps_rpe_freq(struct drm_i915_private
*dev_priv
)
3776 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_LO
);
3777 rpe
= (val
& FB_FMAX_VMIN_FREQ_LO_MASK
) >> FB_FMAX_VMIN_FREQ_LO_SHIFT
;
3778 val
= vlv_nc_read(dev_priv
, IOSF_NC_FB_GFX_FMAX_FUSE_HI
);
3779 rpe
|= (val
& FB_FMAX_VMIN_FREQ_HI_MASK
) << 5;
3784 int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
)
3786 return vlv_punit_read(dev_priv
, PUNIT_REG_GPU_LFM
) & 0xff;
3789 /* Check that the pctx buffer wasn't move under us. */
3790 static void valleyview_check_pctx(struct drm_i915_private
*dev_priv
)
3792 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
3794 WARN_ON(pctx_addr
!= dev_priv
->mm
.stolen_base
+
3795 dev_priv
->vlv_pctx
->stolen
->start
);
3799 /* Check that the pcbr address is not empty. */
3800 static void cherryview_check_pctx(struct drm_i915_private
*dev_priv
)
3802 unsigned long pctx_addr
= I915_READ(VLV_PCBR
) & ~4095;
3804 WARN_ON((pctx_addr
>> VLV_PCBR_ADDR_SHIFT
) == 0);
3807 static void cherryview_setup_pctx(struct drm_device
*dev
)
3809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3810 unsigned long pctx_paddr
, paddr
;
3811 struct i915_gtt
*gtt
= &dev_priv
->gtt
;
3813 int pctx_size
= 32*1024;
3815 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3817 pcbr
= I915_READ(VLV_PCBR
);
3818 if ((pcbr
>> VLV_PCBR_ADDR_SHIFT
) == 0) {
3819 paddr
= (dev_priv
->mm
.stolen_base
+
3820 (gtt
->stolen_size
- pctx_size
));
3822 pctx_paddr
= (paddr
& (~4095));
3823 I915_WRITE(VLV_PCBR
, pctx_paddr
);
3827 static void valleyview_setup_pctx(struct drm_device
*dev
)
3829 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3830 struct drm_i915_gem_object
*pctx
;
3831 unsigned long pctx_paddr
;
3833 int pctx_size
= 24*1024;
3835 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
3837 pcbr
= I915_READ(VLV_PCBR
);
3839 /* BIOS set it up already, grab the pre-alloc'd space */
3842 pcbr_offset
= (pcbr
& (~4095)) - dev_priv
->mm
.stolen_base
;
3843 pctx
= i915_gem_object_create_stolen_for_preallocated(dev_priv
->dev
,
3845 I915_GTT_OFFSET_NONE
,
3851 * From the Gunit register HAS:
3852 * The Gfx driver is expected to program this register and ensure
3853 * proper allocation within Gfx stolen memory. For example, this
3854 * register should be programmed such than the PCBR range does not
3855 * overlap with other ranges, such as the frame buffer, protected
3856 * memory, or any other relevant ranges.
3858 pctx
= i915_gem_object_create_stolen(dev
, pctx_size
);
3860 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3864 pctx_paddr
= dev_priv
->mm
.stolen_base
+ pctx
->stolen
->start
;
3865 I915_WRITE(VLV_PCBR
, pctx_paddr
);
3868 dev_priv
->vlv_pctx
= pctx
;
3871 static void valleyview_cleanup_pctx(struct drm_device
*dev
)
3873 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3875 if (WARN_ON(!dev_priv
->vlv_pctx
))
3878 drm_gem_object_unreference(&dev_priv
->vlv_pctx
->base
);
3879 dev_priv
->vlv_pctx
= NULL
;
3882 static void valleyview_init_gt_powersave(struct drm_device
*dev
)
3884 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3886 valleyview_setup_pctx(dev
);
3888 mutex_lock(&dev_priv
->rps
.hw_lock
);
3890 dev_priv
->rps
.max_freq
= valleyview_rps_max_freq(dev_priv
);
3891 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
3892 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3893 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
3894 dev_priv
->rps
.max_freq
);
3896 dev_priv
->rps
.efficient_freq
= valleyview_rps_rpe_freq(dev_priv
);
3897 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3898 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
3899 dev_priv
->rps
.efficient_freq
);
3901 dev_priv
->rps
.min_freq
= valleyview_rps_min_freq(dev_priv
);
3902 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3903 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
3904 dev_priv
->rps
.min_freq
);
3906 /* Preserve min/max settings in case of re-init */
3907 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3908 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3910 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3911 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
3913 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3916 static void cherryview_init_gt_powersave(struct drm_device
*dev
)
3918 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3920 cherryview_setup_pctx(dev
);
3922 mutex_lock(&dev_priv
->rps
.hw_lock
);
3924 dev_priv
->rps
.max_freq
= cherryview_rps_max_freq(dev_priv
);
3925 dev_priv
->rps
.rp0_freq
= dev_priv
->rps
.max_freq
;
3926 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3927 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.max_freq
),
3928 dev_priv
->rps
.max_freq
);
3930 dev_priv
->rps
.efficient_freq
= cherryview_rps_rpe_freq(dev_priv
);
3931 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3932 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
3933 dev_priv
->rps
.efficient_freq
);
3935 dev_priv
->rps
.min_freq
= cherryview_rps_min_freq(dev_priv
);
3936 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3937 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.min_freq
),
3938 dev_priv
->rps
.min_freq
);
3940 /* Preserve min/max settings in case of re-init */
3941 if (dev_priv
->rps
.max_freq_softlimit
== 0)
3942 dev_priv
->rps
.max_freq_softlimit
= dev_priv
->rps
.max_freq
;
3944 if (dev_priv
->rps
.min_freq_softlimit
== 0)
3945 dev_priv
->rps
.min_freq_softlimit
= dev_priv
->rps
.min_freq
;
3947 mutex_unlock(&dev_priv
->rps
.hw_lock
);
3950 static void valleyview_cleanup_gt_powersave(struct drm_device
*dev
)
3952 valleyview_cleanup_pctx(dev
);
3955 static void cherryview_enable_rps(struct drm_device
*dev
)
3957 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3958 struct intel_engine_cs
*ring
;
3959 u32 gtfifodbg
, val
, rc6_mode
= 0, pcbr
;
3962 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
3964 gtfifodbg
= I915_READ(GTFIFODBG
);
3966 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3968 I915_WRITE(GTFIFODBG
, gtfifodbg
);
3971 cherryview_check_pctx(dev_priv
);
3973 /* 1a & 1b: Get forcewake during program sequence. Although the driver
3974 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
3975 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
3977 /* 2a: Program RC6 thresholds.*/
3978 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 40 << 16);
3979 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000); /* 12500 * 1280ns */
3980 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25); /* 25 * 1280ns */
3982 for_each_ring(ring
, dev_priv
, i
)
3983 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
3984 I915_WRITE(GEN6_RC_SLEEP
, 0);
3986 I915_WRITE(GEN6_RC6_THRESHOLD
, 50000); /* 50/125ms per EI */
3988 /* allows RC6 residency counter to work */
3989 I915_WRITE(VLV_COUNTER_CONTROL
,
3990 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
3991 VLV_MEDIA_RC6_COUNT_EN
|
3992 VLV_RENDER_RC6_COUNT_EN
));
3994 /* For now we assume BIOS is allocating and populating the PCBR */
3995 pcbr
= I915_READ(VLV_PCBR
);
3997 DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr
);
4000 if ((intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
) &&
4001 (pcbr
>> VLV_PCBR_ADDR_SHIFT
))
4002 rc6_mode
= GEN6_RC_CTL_EI_MODE(1);
4004 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4006 /* 4 Program defaults and thresholds for RPS*/
4007 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4008 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4009 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4010 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4012 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4014 /* WaDisablePwrmtrEvent:chv (pre-production hw) */
4015 I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff);
4016 I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00);
4019 I915_WRITE(GEN6_RP_CONTROL
,
4020 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4021 GEN6_RP_MEDIA_IS_GFX
| /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */
4023 GEN6_RP_UP_BUSY_AVG
|
4024 GEN6_RP_DOWN_IDLE_AVG
);
4026 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4028 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4029 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4031 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4032 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4033 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4034 dev_priv
->rps
.cur_freq
);
4036 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4037 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4038 dev_priv
->rps
.efficient_freq
);
4040 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4042 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4045 static void valleyview_enable_rps(struct drm_device
*dev
)
4047 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4048 struct intel_engine_cs
*ring
;
4049 u32 gtfifodbg
, val
, rc6_mode
= 0;
4052 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
4054 valleyview_check_pctx(dev_priv
);
4056 if ((gtfifodbg
= I915_READ(GTFIFODBG
))) {
4057 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4059 I915_WRITE(GTFIFODBG
, gtfifodbg
);
4062 /* If VLV, Forcewake all wells, else re-direct to regular path */
4063 gen6_gt_force_wake_get(dev_priv
, FORCEWAKE_ALL
);
4065 I915_WRITE(GEN6_RP_UP_THRESHOLD
, 59400);
4066 I915_WRITE(GEN6_RP_DOWN_THRESHOLD
, 245000);
4067 I915_WRITE(GEN6_RP_UP_EI
, 66000);
4068 I915_WRITE(GEN6_RP_DOWN_EI
, 350000);
4070 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS
, 10);
4072 I915_WRITE(GEN6_RP_CONTROL
,
4073 GEN6_RP_MEDIA_TURBO
|
4074 GEN6_RP_MEDIA_HW_NORMAL_MODE
|
4075 GEN6_RP_MEDIA_IS_GFX
|
4077 GEN6_RP_UP_BUSY_AVG
|
4078 GEN6_RP_DOWN_IDLE_CONT
);
4080 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT
, 0x00280000);
4081 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL
, 125000);
4082 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS
, 25);
4084 for_each_ring(ring
, dev_priv
, i
)
4085 I915_WRITE(RING_MAX_IDLE(ring
->mmio_base
), 10);
4087 I915_WRITE(GEN6_RC6_THRESHOLD
, 0x557);
4089 /* allows RC6 residency counter to work */
4090 I915_WRITE(VLV_COUNTER_CONTROL
,
4091 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH
|
4092 VLV_MEDIA_RC6_COUNT_EN
|
4093 VLV_RENDER_RC6_COUNT_EN
));
4094 if (intel_enable_rc6(dev
) & INTEL_RC6_ENABLE
)
4095 rc6_mode
= GEN7_RC_CTL_TO_MODE
| VLV_RC_CTL_CTX_RST_PARALLEL
;
4097 intel_print_rc6_info(dev
, rc6_mode
);
4099 I915_WRITE(GEN6_RC_CONTROL
, rc6_mode
);
4101 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
4103 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val
& 0x10 ? "yes" : "no");
4104 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val
);
4106 dev_priv
->rps
.cur_freq
= (val
>> 8) & 0xff;
4107 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4108 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.cur_freq
),
4109 dev_priv
->rps
.cur_freq
);
4111 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4112 vlv_gpu_freq(dev_priv
, dev_priv
->rps
.efficient_freq
),
4113 dev_priv
->rps
.efficient_freq
);
4115 valleyview_set_rps(dev_priv
->dev
, dev_priv
->rps
.efficient_freq
);
4117 gen6_enable_rps_interrupts(dev
);
4119 gen6_gt_force_wake_put(dev_priv
, FORCEWAKE_ALL
);
4122 void ironlake_teardown_rc6(struct drm_device
*dev
)
4124 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4126 if (dev_priv
->ips
.renderctx
) {
4127 i915_gem_object_ggtt_unpin(dev_priv
->ips
.renderctx
);
4128 drm_gem_object_unreference(&dev_priv
->ips
.renderctx
->base
);
4129 dev_priv
->ips
.renderctx
= NULL
;
4132 if (dev_priv
->ips
.pwrctx
) {
4133 i915_gem_object_ggtt_unpin(dev_priv
->ips
.pwrctx
);
4134 drm_gem_object_unreference(&dev_priv
->ips
.pwrctx
->base
);
4135 dev_priv
->ips
.pwrctx
= NULL
;
4139 static void ironlake_disable_rc6(struct drm_device
*dev
)
4141 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4143 if (I915_READ(PWRCTXA
)) {
4144 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4145 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) | RCX_SW_EXIT
);
4146 wait_for(((I915_READ(RSTDBYCTL
) & RSX_STATUS_MASK
) == RSX_STATUS_ON
),
4149 I915_WRITE(PWRCTXA
, 0);
4150 POSTING_READ(PWRCTXA
);
4152 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4153 POSTING_READ(RSTDBYCTL
);
4157 static int ironlake_setup_rc6(struct drm_device
*dev
)
4159 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4161 if (dev_priv
->ips
.renderctx
== NULL
)
4162 dev_priv
->ips
.renderctx
= intel_alloc_context_page(dev
);
4163 if (!dev_priv
->ips
.renderctx
)
4166 if (dev_priv
->ips
.pwrctx
== NULL
)
4167 dev_priv
->ips
.pwrctx
= intel_alloc_context_page(dev
);
4168 if (!dev_priv
->ips
.pwrctx
) {
4169 ironlake_teardown_rc6(dev
);
4176 static void ironlake_enable_rc6(struct drm_device
*dev
)
4178 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4179 struct intel_engine_cs
*ring
= &dev_priv
->ring
[RCS
];
4180 bool was_interruptible
;
4183 /* rc6 disabled by default due to repeated reports of hanging during
4186 if (!intel_enable_rc6(dev
))
4189 WARN_ON(!mutex_is_locked(&dev
->struct_mutex
));
4191 ret
= ironlake_setup_rc6(dev
);
4195 was_interruptible
= dev_priv
->mm
.interruptible
;
4196 dev_priv
->mm
.interruptible
= false;
4199 * GPU can automatically power down the render unit if given a page
4202 ret
= intel_ring_begin(ring
, 6);
4204 ironlake_teardown_rc6(dev
);
4205 dev_priv
->mm
.interruptible
= was_interruptible
;
4209 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
| MI_SUSPEND_FLUSH_EN
);
4210 intel_ring_emit(ring
, MI_SET_CONTEXT
);
4211 intel_ring_emit(ring
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.renderctx
) |
4213 MI_SAVE_EXT_STATE_EN
|
4214 MI_RESTORE_EXT_STATE_EN
|
4215 MI_RESTORE_INHIBIT
);
4216 intel_ring_emit(ring
, MI_SUSPEND_FLUSH
);
4217 intel_ring_emit(ring
, MI_NOOP
);
4218 intel_ring_emit(ring
, MI_FLUSH
);
4219 intel_ring_advance(ring
);
4222 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4223 * does an implicit flush, combined with MI_FLUSH above, it should be
4224 * safe to assume that renderctx is valid
4226 ret
= intel_ring_idle(ring
);
4227 dev_priv
->mm
.interruptible
= was_interruptible
;
4229 DRM_ERROR("failed to enable ironlake power savings\n");
4230 ironlake_teardown_rc6(dev
);
4234 I915_WRITE(PWRCTXA
, i915_gem_obj_ggtt_offset(dev_priv
->ips
.pwrctx
) | PWRCTX_EN
);
4235 I915_WRITE(RSTDBYCTL
, I915_READ(RSTDBYCTL
) & ~RCX_SW_EXIT
);
4237 intel_print_rc6_info(dev
, GEN6_RC_CTL_RC6_ENABLE
);
4240 static unsigned long intel_pxfreq(u32 vidfreq
)
4243 int div
= (vidfreq
& 0x3f0000) >> 16;
4244 int post
= (vidfreq
& 0x3000) >> 12;
4245 int pre
= (vidfreq
& 0x7);
4250 freq
= ((div
* 133333) / ((1<<post
) * pre
));
4255 static const struct cparams
{
4261 { 1, 1333, 301, 28664 },
4262 { 1, 1066, 294, 24460 },
4263 { 1, 800, 294, 25192 },
4264 { 0, 1333, 276, 27605 },
4265 { 0, 1066, 276, 27605 },
4266 { 0, 800, 231, 23784 },
4269 static unsigned long __i915_chipset_val(struct drm_i915_private
*dev_priv
)
4271 u64 total_count
, diff
, ret
;
4272 u32 count1
, count2
, count3
, m
= 0, c
= 0;
4273 unsigned long now
= jiffies_to_msecs(jiffies
), diff1
;
4276 assert_spin_locked(&mchdev_lock
);
4278 diff1
= now
- dev_priv
->ips
.last_time1
;
4280 /* Prevent division-by-zero if we are asking too fast.
4281 * Also, we don't get interesting results if we are polling
4282 * faster than once in 10ms, so just return the saved value
4286 return dev_priv
->ips
.chipset_power
;
4288 count1
= I915_READ(DMIEC
);
4289 count2
= I915_READ(DDREC
);
4290 count3
= I915_READ(CSIEC
);
4292 total_count
= count1
+ count2
+ count3
;
4294 /* FIXME: handle per-counter overflow */
4295 if (total_count
< dev_priv
->ips
.last_count1
) {
4296 diff
= ~0UL - dev_priv
->ips
.last_count1
;
4297 diff
+= total_count
;
4299 diff
= total_count
- dev_priv
->ips
.last_count1
;
4302 for (i
= 0; i
< ARRAY_SIZE(cparams
); i
++) {
4303 if (cparams
[i
].i
== dev_priv
->ips
.c_m
&&
4304 cparams
[i
].t
== dev_priv
->ips
.r_t
) {
4311 diff
= div_u64(diff
, diff1
);
4312 ret
= ((m
* diff
) + c
);
4313 ret
= div_u64(ret
, 10);
4315 dev_priv
->ips
.last_count1
= total_count
;
4316 dev_priv
->ips
.last_time1
= now
;
4318 dev_priv
->ips
.chipset_power
= ret
;
4323 unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
)
4325 struct drm_device
*dev
= dev_priv
->dev
;
4328 if (INTEL_INFO(dev
)->gen
!= 5)
4331 spin_lock_irq(&mchdev_lock
);
4333 val
= __i915_chipset_val(dev_priv
);
4335 spin_unlock_irq(&mchdev_lock
);
4340 unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
)
4342 unsigned long m
, x
, b
;
4345 tsfs
= I915_READ(TSFS
);
4347 m
= ((tsfs
& TSFS_SLOPE_MASK
) >> TSFS_SLOPE_SHIFT
);
4348 x
= I915_READ8(TR1
);
4350 b
= tsfs
& TSFS_INTR_MASK
;
4352 return ((m
* x
) / 127) - b
;
4355 static u16
pvid_to_extvid(struct drm_i915_private
*dev_priv
, u8 pxvid
)
4357 struct drm_device
*dev
= dev_priv
->dev
;
4358 static const struct v_table
{
4359 u16 vd
; /* in .1 mil */
4360 u16 vm
; /* in .1 mil */
4491 if (INTEL_INFO(dev
)->is_mobile
)
4492 return v_table
[pxvid
].vm
;
4494 return v_table
[pxvid
].vd
;
4497 static void __i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4499 struct timespec now
, diff1
;
4501 unsigned long diffms
;
4504 assert_spin_locked(&mchdev_lock
);
4506 getrawmonotonic(&now
);
4507 diff1
= timespec_sub(now
, dev_priv
->ips
.last_time2
);
4509 /* Don't divide by 0 */
4510 diffms
= diff1
.tv_sec
* 1000 + diff1
.tv_nsec
/ 1000000;
4514 count
= I915_READ(GFXEC
);
4516 if (count
< dev_priv
->ips
.last_count2
) {
4517 diff
= ~0UL - dev_priv
->ips
.last_count2
;
4520 diff
= count
- dev_priv
->ips
.last_count2
;
4523 dev_priv
->ips
.last_count2
= count
;
4524 dev_priv
->ips
.last_time2
= now
;
4526 /* More magic constants... */
4528 diff
= div_u64(diff
, diffms
* 10);
4529 dev_priv
->ips
.gfx_power
= diff
;
4532 void i915_update_gfx_val(struct drm_i915_private
*dev_priv
)
4534 struct drm_device
*dev
= dev_priv
->dev
;
4536 if (INTEL_INFO(dev
)->gen
!= 5)
4539 spin_lock_irq(&mchdev_lock
);
4541 __i915_update_gfx_val(dev_priv
);
4543 spin_unlock_irq(&mchdev_lock
);
4546 static unsigned long __i915_gfx_val(struct drm_i915_private
*dev_priv
)
4548 unsigned long t
, corr
, state1
, corr2
, state2
;
4551 assert_spin_locked(&mchdev_lock
);
4553 pxvid
= I915_READ(PXVFREQ_BASE
+ (dev_priv
->rps
.cur_freq
* 4));
4554 pxvid
= (pxvid
>> 24) & 0x7f;
4555 ext_v
= pvid_to_extvid(dev_priv
, pxvid
);
4559 t
= i915_mch_val(dev_priv
);
4561 /* Revel in the empirically derived constants */
4563 /* Correction factor in 1/100000 units */
4565 corr
= ((t
* 2349) + 135940);
4567 corr
= ((t
* 964) + 29317);
4569 corr
= ((t
* 301) + 1004);
4571 corr
= corr
* ((150142 * state1
) / 10000 - 78642);
4573 corr2
= (corr
* dev_priv
->ips
.corr
);
4575 state2
= (corr2
* state1
) / 10000;
4576 state2
/= 100; /* convert to mW */
4578 __i915_update_gfx_val(dev_priv
);
4580 return dev_priv
->ips
.gfx_power
+ state2
;
4583 unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
)
4585 struct drm_device
*dev
= dev_priv
->dev
;
4588 if (INTEL_INFO(dev
)->gen
!= 5)
4591 spin_lock_irq(&mchdev_lock
);
4593 val
= __i915_gfx_val(dev_priv
);
4595 spin_unlock_irq(&mchdev_lock
);
4601 * i915_read_mch_val - return value for IPS use
4603 * Calculate and return a value for the IPS driver to use when deciding whether
4604 * we have thermal and power headroom to increase CPU or GPU power budget.
4606 unsigned long i915_read_mch_val(void)
4608 struct drm_i915_private
*dev_priv
;
4609 unsigned long chipset_val
, graphics_val
, ret
= 0;
4611 spin_lock_irq(&mchdev_lock
);
4614 dev_priv
= i915_mch_dev
;
4616 chipset_val
= __i915_chipset_val(dev_priv
);
4617 graphics_val
= __i915_gfx_val(dev_priv
);
4619 ret
= chipset_val
+ graphics_val
;
4622 spin_unlock_irq(&mchdev_lock
);
4626 EXPORT_SYMBOL_GPL(i915_read_mch_val
);
4629 * i915_gpu_raise - raise GPU frequency limit
4631 * Raise the limit; IPS indicates we have thermal headroom.
4633 bool i915_gpu_raise(void)
4635 struct drm_i915_private
*dev_priv
;
4638 spin_lock_irq(&mchdev_lock
);
4639 if (!i915_mch_dev
) {
4643 dev_priv
= i915_mch_dev
;
4645 if (dev_priv
->ips
.max_delay
> dev_priv
->ips
.fmax
)
4646 dev_priv
->ips
.max_delay
--;
4649 spin_unlock_irq(&mchdev_lock
);
4653 EXPORT_SYMBOL_GPL(i915_gpu_raise
);
4656 * i915_gpu_lower - lower GPU frequency limit
4658 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4659 * frequency maximum.
4661 bool i915_gpu_lower(void)
4663 struct drm_i915_private
*dev_priv
;
4666 spin_lock_irq(&mchdev_lock
);
4667 if (!i915_mch_dev
) {
4671 dev_priv
= i915_mch_dev
;
4673 if (dev_priv
->ips
.max_delay
< dev_priv
->ips
.min_delay
)
4674 dev_priv
->ips
.max_delay
++;
4677 spin_unlock_irq(&mchdev_lock
);
4681 EXPORT_SYMBOL_GPL(i915_gpu_lower
);
4684 * i915_gpu_busy - indicate GPU business to IPS
4686 * Tell the IPS driver whether or not the GPU is busy.
4688 bool i915_gpu_busy(void)
4690 struct drm_i915_private
*dev_priv
;
4691 struct intel_engine_cs
*ring
;
4695 spin_lock_irq(&mchdev_lock
);
4698 dev_priv
= i915_mch_dev
;
4700 for_each_ring(ring
, dev_priv
, i
)
4701 ret
|= !list_empty(&ring
->request_list
);
4704 spin_unlock_irq(&mchdev_lock
);
4708 EXPORT_SYMBOL_GPL(i915_gpu_busy
);
4711 * i915_gpu_turbo_disable - disable graphics turbo
4713 * Disable graphics turbo by resetting the max frequency and setting the
4714 * current frequency to the default.
4716 bool i915_gpu_turbo_disable(void)
4718 struct drm_i915_private
*dev_priv
;
4721 spin_lock_irq(&mchdev_lock
);
4722 if (!i915_mch_dev
) {
4726 dev_priv
= i915_mch_dev
;
4728 dev_priv
->ips
.max_delay
= dev_priv
->ips
.fstart
;
4730 if (!ironlake_set_drps(dev_priv
->dev
, dev_priv
->ips
.fstart
))
4734 spin_unlock_irq(&mchdev_lock
);
4738 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable
);
4741 * Tells the intel_ips driver that the i915 driver is now loaded, if
4742 * IPS got loaded first.
4744 * This awkward dance is so that neither module has to depend on the
4745 * other in order for IPS to do the appropriate communication of
4746 * GPU turbo limits to i915.
4749 ips_ping_for_i915_load(void)
4753 link
= symbol_get(ips_link_to_i915_driver
);
4756 symbol_put(ips_link_to_i915_driver
);
4760 void intel_gpu_ips_init(struct drm_i915_private
*dev_priv
)
4762 /* We only register the i915 ips part with intel-ips once everything is
4763 * set up, to avoid intel-ips sneaking in and reading bogus values. */
4764 spin_lock_irq(&mchdev_lock
);
4765 i915_mch_dev
= dev_priv
;
4766 spin_unlock_irq(&mchdev_lock
);
4768 ips_ping_for_i915_load();
4771 void intel_gpu_ips_teardown(void)
4773 spin_lock_irq(&mchdev_lock
);
4774 i915_mch_dev
= NULL
;
4775 spin_unlock_irq(&mchdev_lock
);
4778 static void intel_init_emon(struct drm_device
*dev
)
4780 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4785 /* Disable to program */
4789 /* Program energy weights for various events */
4790 I915_WRITE(SDEW
, 0x15040d00);
4791 I915_WRITE(CSIEW0
, 0x007f0000);
4792 I915_WRITE(CSIEW1
, 0x1e220004);
4793 I915_WRITE(CSIEW2
, 0x04000004);
4795 for (i
= 0; i
< 5; i
++)
4796 I915_WRITE(PEW
+ (i
* 4), 0);
4797 for (i
= 0; i
< 3; i
++)
4798 I915_WRITE(DEW
+ (i
* 4), 0);
4800 /* Program P-state weights to account for frequency power adjustment */
4801 for (i
= 0; i
< 16; i
++) {
4802 u32 pxvidfreq
= I915_READ(PXVFREQ_BASE
+ (i
* 4));
4803 unsigned long freq
= intel_pxfreq(pxvidfreq
);
4804 unsigned long vid
= (pxvidfreq
& PXVFREQ_PX_MASK
) >>
4809 val
*= (freq
/ 1000);
4811 val
/= (127*127*900);
4813 DRM_ERROR("bad pxval: %ld\n", val
);
4816 /* Render standby states get 0 weight */
4820 for (i
= 0; i
< 4; i
++) {
4821 u32 val
= (pxw
[i
*4] << 24) | (pxw
[(i
*4)+1] << 16) |
4822 (pxw
[(i
*4)+2] << 8) | (pxw
[(i
*4)+3]);
4823 I915_WRITE(PXW
+ (i
* 4), val
);
4826 /* Adjust magic regs to magic values (more experimental results) */
4827 I915_WRITE(OGW0
, 0);
4828 I915_WRITE(OGW1
, 0);
4829 I915_WRITE(EG0
, 0x00007f00);
4830 I915_WRITE(EG1
, 0x0000000e);
4831 I915_WRITE(EG2
, 0x000e0000);
4832 I915_WRITE(EG3
, 0x68000300);
4833 I915_WRITE(EG4
, 0x42000000);
4834 I915_WRITE(EG5
, 0x00140031);
4838 for (i
= 0; i
< 8; i
++)
4839 I915_WRITE(PXWL
+ (i
* 4), 0);
4841 /* Enable PMON + select events */
4842 I915_WRITE(ECR
, 0x80000019);
4844 lcfuse
= I915_READ(LCFUSE02
);
4846 dev_priv
->ips
.corr
= (lcfuse
& LCFUSE_HIV_MASK
);
4849 void intel_init_gt_powersave(struct drm_device
*dev
)
4851 i915
.enable_rc6
= sanitize_rc6_option(dev
, i915
.enable_rc6
);
4853 if (IS_CHERRYVIEW(dev
))
4854 cherryview_init_gt_powersave(dev
);
4855 else if (IS_VALLEYVIEW(dev
))
4856 valleyview_init_gt_powersave(dev
);
4859 void intel_cleanup_gt_powersave(struct drm_device
*dev
)
4861 if (IS_CHERRYVIEW(dev
))
4863 else if (IS_VALLEYVIEW(dev
))
4864 valleyview_cleanup_gt_powersave(dev
);
4867 void intel_disable_gt_powersave(struct drm_device
*dev
)
4869 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4871 /* Interrupts should be disabled already to avoid re-arming. */
4872 WARN_ON(dev
->irq_enabled
);
4874 if (IS_IRONLAKE_M(dev
)) {
4875 ironlake_disable_drps(dev
);
4876 ironlake_disable_rc6(dev
);
4877 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4878 if (cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
))
4879 intel_runtime_pm_put(dev_priv
);
4881 cancel_work_sync(&dev_priv
->rps
.work
);
4882 mutex_lock(&dev_priv
->rps
.hw_lock
);
4883 if (IS_CHERRYVIEW(dev
))
4884 cherryview_disable_rps(dev
);
4885 else if (IS_VALLEYVIEW(dev
))
4886 valleyview_disable_rps(dev
);
4888 gen6_disable_rps(dev
);
4889 dev_priv
->rps
.enabled
= false;
4890 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4894 static void intel_gen6_powersave_work(struct work_struct
*work
)
4896 struct drm_i915_private
*dev_priv
=
4897 container_of(work
, struct drm_i915_private
,
4898 rps
.delayed_resume_work
.work
);
4899 struct drm_device
*dev
= dev_priv
->dev
;
4901 mutex_lock(&dev_priv
->rps
.hw_lock
);
4903 if (IS_CHERRYVIEW(dev
)) {
4904 cherryview_enable_rps(dev
);
4905 } else if (IS_VALLEYVIEW(dev
)) {
4906 valleyview_enable_rps(dev
);
4907 } else if (IS_BROADWELL(dev
)) {
4908 gen8_enable_rps(dev
);
4909 __gen6_update_ring_freq(dev
);
4911 gen6_enable_rps(dev
);
4912 __gen6_update_ring_freq(dev
);
4914 dev_priv
->rps
.enabled
= true;
4915 mutex_unlock(&dev_priv
->rps
.hw_lock
);
4917 intel_runtime_pm_put(dev_priv
);
4920 void intel_enable_gt_powersave(struct drm_device
*dev
)
4922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4924 if (IS_IRONLAKE_M(dev
)) {
4925 mutex_lock(&dev
->struct_mutex
);
4926 ironlake_enable_drps(dev
);
4927 ironlake_enable_rc6(dev
);
4928 intel_init_emon(dev
);
4929 mutex_unlock(&dev
->struct_mutex
);
4930 } else if (INTEL_INFO(dev
)->gen
>= 6) {
4932 * PCU communication is slow and this doesn't need to be
4933 * done at any specific time, so do this out of our fast path
4934 * to make resume and init faster.
4936 * We depend on the HW RC6 power context save/restore
4937 * mechanism when entering D3 through runtime PM suspend. So
4938 * disable RPM until RPS/RC6 is properly setup. We can only
4939 * get here via the driver load/system resume/runtime resume
4940 * paths, so the _noresume version is enough (and in case of
4941 * runtime resume it's necessary).
4943 if (schedule_delayed_work(&dev_priv
->rps
.delayed_resume_work
,
4944 round_jiffies_up_relative(HZ
)))
4945 intel_runtime_pm_get_noresume(dev_priv
);
4949 void intel_reset_gt_powersave(struct drm_device
*dev
)
4951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4953 dev_priv
->rps
.enabled
= false;
4954 intel_enable_gt_powersave(dev
);
4957 static void ibx_init_clock_gating(struct drm_device
*dev
)
4959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4962 * On Ibex Peak and Cougar Point, we need to disable clock
4963 * gating for the panel power sequencer or it will fail to
4964 * start up when no ports are active.
4966 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
);
4969 static void g4x_disable_trickle_feed(struct drm_device
*dev
)
4971 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4974 for_each_pipe(pipe
) {
4975 I915_WRITE(DSPCNTR(pipe
),
4976 I915_READ(DSPCNTR(pipe
)) |
4977 DISPPLANE_TRICKLE_FEED_DISABLE
);
4978 intel_flush_primary_plane(dev_priv
, pipe
);
4982 static void ilk_init_lp_watermarks(struct drm_device
*dev
)
4984 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4986 I915_WRITE(WM3_LP_ILK
, I915_READ(WM3_LP_ILK
) & ~WM1_LP_SR_EN
);
4987 I915_WRITE(WM2_LP_ILK
, I915_READ(WM2_LP_ILK
) & ~WM1_LP_SR_EN
);
4988 I915_WRITE(WM1_LP_ILK
, I915_READ(WM1_LP_ILK
) & ~WM1_LP_SR_EN
);
4991 * Don't touch WM1S_LP_EN here.
4992 * Doing so could cause underruns.
4996 static void ironlake_init_clock_gating(struct drm_device
*dev
)
4998 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4999 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5003 * WaFbcDisableDpfcClockGating:ilk
5005 dspclk_gate
|= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE
|
5006 ILK_DPFCUNIT_CLOCK_GATE_DISABLE
|
5007 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
;
5009 I915_WRITE(PCH_3DCGDIS0
,
5010 MARIUNIT_CLOCK_GATE_DISABLE
|
5011 SVSMUNIT_CLOCK_GATE_DISABLE
);
5012 I915_WRITE(PCH_3DCGDIS1
,
5013 VFMUNIT_CLOCK_GATE_DISABLE
);
5016 * According to the spec the following bits should be set in
5017 * order to enable memory self-refresh
5018 * The bit 22/21 of 0x42004
5019 * The bit 5 of 0x42020
5020 * The bit 15 of 0x45000
5022 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5023 (I915_READ(ILK_DISPLAY_CHICKEN2
) |
5024 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
));
5025 dspclk_gate
|= ILK_DPARBUNIT_CLOCK_GATE_ENABLE
;
5026 I915_WRITE(DISP_ARB_CTL
,
5027 (I915_READ(DISP_ARB_CTL
) |
5030 ilk_init_lp_watermarks(dev
);
5033 * Based on the document from hardware guys the following bits
5034 * should be set unconditionally in order to enable FBC.
5035 * The bit 22 of 0x42000
5036 * The bit 22 of 0x42004
5037 * The bit 7,8,9 of 0x42020.
5039 if (IS_IRONLAKE_M(dev
)) {
5040 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
5041 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5042 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5044 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5045 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5049 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5051 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5052 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5053 ILK_ELPIN_409_SELECT
);
5054 I915_WRITE(_3D_CHICKEN2
,
5055 _3D_CHICKEN2_WM_READ_PIPELINED
<< 16 |
5056 _3D_CHICKEN2_WM_READ_PIPELINED
);
5058 /* WaDisableRenderCachePipelinedFlush:ilk */
5059 I915_WRITE(CACHE_MODE_0
,
5060 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5062 /* WaDisable_RenderCache_OperationalFlush:ilk */
5063 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5065 g4x_disable_trickle_feed(dev
);
5067 ibx_init_clock_gating(dev
);
5070 static void cpt_init_clock_gating(struct drm_device
*dev
)
5072 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5077 * On Ibex Peak and Cougar Point, we need to disable clock
5078 * gating for the panel power sequencer or it will fail to
5079 * start up when no ports are active.
5081 I915_WRITE(SOUTH_DSPCLK_GATE_D
, PCH_DPLSUNIT_CLOCK_GATE_DISABLE
|
5082 PCH_DPLUNIT_CLOCK_GATE_DISABLE
|
5083 PCH_CPUNIT_CLOCK_GATE_DISABLE
);
5084 I915_WRITE(SOUTH_CHICKEN2
, I915_READ(SOUTH_CHICKEN2
) |
5085 DPLS_EDP_PPS_FIX_DIS
);
5086 /* The below fixes the weird display corruption, a few pixels shifted
5087 * downward, on (only) LVDS of some HP laptops with IVY.
5089 for_each_pipe(pipe
) {
5090 val
= I915_READ(TRANS_CHICKEN2(pipe
));
5091 val
|= TRANS_CHICKEN2_TIMING_OVERRIDE
;
5092 val
&= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5093 if (dev_priv
->vbt
.fdi_rx_polarity_inverted
)
5094 val
|= TRANS_CHICKEN2_FDI_POLARITY_REVERSED
;
5095 val
&= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK
;
5096 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER
;
5097 val
&= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH
;
5098 I915_WRITE(TRANS_CHICKEN2(pipe
), val
);
5100 /* WADP0ClockGatingDisable */
5101 for_each_pipe(pipe
) {
5102 I915_WRITE(TRANS_CHICKEN1(pipe
),
5103 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5107 static void gen6_check_mch_setup(struct drm_device
*dev
)
5109 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5112 tmp
= I915_READ(MCH_SSKPD
);
5113 if ((tmp
& MCH_SSKPD_WM0_MASK
) != MCH_SSKPD_WM0_VAL
) {
5114 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp
);
5115 DRM_INFO("This can cause pipe underruns and display issues.\n");
5116 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5120 static void gen6_init_clock_gating(struct drm_device
*dev
)
5122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5123 uint32_t dspclk_gate
= ILK_VRHUNIT_CLOCK_GATE_DISABLE
;
5125 I915_WRITE(ILK_DSPCLK_GATE_D
, dspclk_gate
);
5127 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5128 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5129 ILK_ELPIN_409_SELECT
);
5131 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
5132 I915_WRITE(_3D_CHICKEN
,
5133 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB
));
5135 /* WaSetupGtModeTdRowDispatch:snb */
5136 if (IS_SNB_GT1(dev
))
5137 I915_WRITE(GEN6_GT_MODE
,
5138 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE
));
5140 /* WaDisable_RenderCache_OperationalFlush:snb */
5141 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5144 * BSpec recoomends 8x4 when MSAA is used,
5145 * however in practice 16x4 seems fastest.
5147 * Note that PS/WM thread counts depend on the WIZ hashing
5148 * disable bit, which we don't touch here, but it's good
5149 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5151 I915_WRITE(GEN6_GT_MODE
,
5152 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5154 ilk_init_lp_watermarks(dev
);
5156 I915_WRITE(CACHE_MODE_0
,
5157 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB
));
5159 I915_WRITE(GEN6_UCGCTL1
,
5160 I915_READ(GEN6_UCGCTL1
) |
5161 GEN6_BLBUNIT_CLOCK_GATE_DISABLE
|
5162 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5164 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5165 * gating disable must be set. Failure to set it results in
5166 * flickering pixels due to Z write ordering failures after
5167 * some amount of runtime in the Mesa "fire" demo, and Unigine
5168 * Sanctuary and Tropics, and apparently anything else with
5169 * alpha test or pixel discard.
5171 * According to the spec, bit 11 (RCCUNIT) must also be set,
5172 * but we didn't debug actual testcases to find it out.
5174 * WaDisableRCCUnitClockGating:snb
5175 * WaDisableRCPBUnitClockGating:snb
5177 I915_WRITE(GEN6_UCGCTL2
,
5178 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE
|
5179 GEN6_RCCUNIT_CLOCK_GATE_DISABLE
);
5181 /* WaStripsFansDisableFastClipPerformanceFix:snb */
5182 I915_WRITE(_3D_CHICKEN3
,
5183 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL
));
5187 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
5188 * 3DSTATE_SF number of SF output attributes is more than 16."
5190 I915_WRITE(_3D_CHICKEN3
,
5191 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH
));
5194 * According to the spec the following bits should be
5195 * set in order to enable memory self-refresh and fbc:
5196 * The bit21 and bit22 of 0x42000
5197 * The bit21 and bit22 of 0x42004
5198 * The bit5 and bit7 of 0x42020
5199 * The bit14 of 0x70180
5200 * The bit14 of 0x71180
5202 * WaFbcAsynchFlipDisableFbcQueue:snb
5204 I915_WRITE(ILK_DISPLAY_CHICKEN1
,
5205 I915_READ(ILK_DISPLAY_CHICKEN1
) |
5206 ILK_FBCQ_DIS
| ILK_PABSTRETCH_DIS
);
5207 I915_WRITE(ILK_DISPLAY_CHICKEN2
,
5208 I915_READ(ILK_DISPLAY_CHICKEN2
) |
5209 ILK_DPARB_GATE
| ILK_VSDPFD_FULL
);
5210 I915_WRITE(ILK_DSPCLK_GATE_D
,
5211 I915_READ(ILK_DSPCLK_GATE_D
) |
5212 ILK_DPARBUNIT_CLOCK_GATE_ENABLE
|
5213 ILK_DPFDUNIT_CLOCK_GATE_ENABLE
);
5215 g4x_disable_trickle_feed(dev
);
5217 cpt_init_clock_gating(dev
);
5219 gen6_check_mch_setup(dev
);
5222 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private
*dev_priv
)
5224 uint32_t reg
= I915_READ(GEN7_FF_THREAD_MODE
);
5227 * WaVSThreadDispatchOverride:ivb,vlv
5229 * This actually overrides the dispatch
5230 * mode for all thread types.
5232 reg
&= ~GEN7_FF_SCHED_MASK
;
5233 reg
|= GEN7_FF_TS_SCHED_HW
;
5234 reg
|= GEN7_FF_VS_SCHED_HW
;
5235 reg
|= GEN7_FF_DS_SCHED_HW
;
5237 I915_WRITE(GEN7_FF_THREAD_MODE
, reg
);
5240 static void lpt_init_clock_gating(struct drm_device
*dev
)
5242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5245 * TODO: this bit should only be enabled when really needed, then
5246 * disabled when not needed anymore in order to save power.
5248 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
)
5249 I915_WRITE(SOUTH_DSPCLK_GATE_D
,
5250 I915_READ(SOUTH_DSPCLK_GATE_D
) |
5251 PCH_LP_PARTITION_LEVEL_DISABLE
);
5253 /* WADPOClockGatingDisable:hsw */
5254 I915_WRITE(_TRANSA_CHICKEN1
,
5255 I915_READ(_TRANSA_CHICKEN1
) |
5256 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE
);
5259 static void lpt_suspend_hw(struct drm_device
*dev
)
5261 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5263 if (dev_priv
->pch_id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
5264 uint32_t val
= I915_READ(SOUTH_DSPCLK_GATE_D
);
5266 val
&= ~PCH_LP_PARTITION_LEVEL_DISABLE
;
5267 I915_WRITE(SOUTH_DSPCLK_GATE_D
, val
);
5271 static void gen8_init_clock_gating(struct drm_device
*dev
)
5273 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5276 I915_WRITE(WM3_LP_ILK
, 0);
5277 I915_WRITE(WM2_LP_ILK
, 0);
5278 I915_WRITE(WM1_LP_ILK
, 0);
5280 /* FIXME(BDW): Check all the w/a, some might only apply to
5281 * pre-production hw. */
5283 /* WaDisablePartialInstShootdown:bdw */
5284 I915_WRITE(GEN8_ROW_CHICKEN
,
5285 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
));
5287 /* WaDisableThreadStallDopClockGating:bdw */
5288 /* FIXME: Unclear whether we really need this on production bdw. */
5289 I915_WRITE(GEN8_ROW_CHICKEN
,
5290 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE
));
5293 * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for
5294 * pre-production hardware
5296 I915_WRITE(HALF_SLICE_CHICKEN3
,
5297 _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS
));
5298 I915_WRITE(HALF_SLICE_CHICKEN3
,
5299 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5300 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE
));
5302 I915_WRITE(_3D_CHICKEN3
,
5303 _3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2));
5305 I915_WRITE(COMMON_SLICE_CHICKEN2
,
5306 _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE
));
5308 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5309 _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE
));
5311 /* WaDisableDopClockGating:bdw May not be needed for production */
5312 I915_WRITE(GEN7_ROW_CHICKEN2
,
5313 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5315 /* WaSwitchSolVfFArbitrationPriority:bdw */
5316 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5318 /* WaPsrDPAMaskVBlankInSRD:bdw */
5319 I915_WRITE(CHICKEN_PAR1_1
,
5320 I915_READ(CHICKEN_PAR1_1
) | DPA_MASK_VBLANK_SRD
);
5322 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
5323 for_each_pipe(pipe
) {
5324 I915_WRITE(CHICKEN_PIPESL_1(pipe
),
5325 I915_READ(CHICKEN_PIPESL_1(pipe
)) |
5326 BDW_DPRS_MASK_VBLANK_SRD
);
5329 /* Use Force Non-Coherent whenever executing a 3D context. This is a
5330 * workaround for for a possible hang in the unlikely event a TLB
5331 * invalidation occurs during a PSD flush.
5333 I915_WRITE(HDC_CHICKEN0
,
5334 I915_READ(HDC_CHICKEN0
) |
5335 _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT
));
5337 /* WaVSRefCountFullforceMissDisable:bdw */
5338 /* WaDSRefCountFullforceMissDisable:bdw */
5339 I915_WRITE(GEN7_FF_THREAD_MODE
,
5340 I915_READ(GEN7_FF_THREAD_MODE
) &
5341 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5344 * BSpec recommends 8x4 when MSAA is used,
5345 * however in practice 16x4 seems fastest.
5347 * Note that PS/WM thread counts depend on the WIZ hashing
5348 * disable bit, which we don't touch here, but it's good
5349 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5351 I915_WRITE(GEN7_GT_MODE
,
5352 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5354 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5355 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5357 /* WaDisableSDEUnitClockGating:bdw */
5358 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5359 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5361 /* Wa4x4STCOptimizationDisable:bdw */
5362 I915_WRITE(CACHE_MODE_1
,
5363 _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE
));
5366 static void haswell_init_clock_gating(struct drm_device
*dev
)
5368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5370 ilk_init_lp_watermarks(dev
);
5372 /* L3 caching of data atomics doesn't work -- disable it. */
5373 I915_WRITE(HSW_SCRATCH1
, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE
);
5374 I915_WRITE(HSW_ROW_CHICKEN3
,
5375 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE
));
5377 /* This is required by WaCatErrorRejectionIssue:hsw */
5378 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5379 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5380 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5382 /* WaVSRefCountFullforceMissDisable:hsw */
5383 I915_WRITE(GEN7_FF_THREAD_MODE
,
5384 I915_READ(GEN7_FF_THREAD_MODE
) & ~GEN7_FF_VS_REF_CNT_FFME
);
5386 /* WaDisable_RenderCache_OperationalFlush:hsw */
5387 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5389 /* enable HiZ Raw Stall Optimization */
5390 I915_WRITE(CACHE_MODE_0_GEN7
,
5391 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5393 /* WaDisable4x2SubspanOptimization:hsw */
5394 I915_WRITE(CACHE_MODE_1
,
5395 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5398 * BSpec recommends 8x4 when MSAA is used,
5399 * however in practice 16x4 seems fastest.
5401 * Note that PS/WM thread counts depend on the WIZ hashing
5402 * disable bit, which we don't touch here, but it's good
5403 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5405 I915_WRITE(GEN7_GT_MODE
,
5406 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5408 /* WaSwitchSolVfFArbitrationPriority:hsw */
5409 I915_WRITE(GAM_ECOCHK
, I915_READ(GAM_ECOCHK
) | HSW_ECOCHK_ARB_PRIO_SOL
);
5411 /* WaRsPkgCStateDisplayPMReq:hsw */
5412 I915_WRITE(CHICKEN_PAR1_1
,
5413 I915_READ(CHICKEN_PAR1_1
) | FORCE_ARB_IDLE_PLANES
);
5415 lpt_init_clock_gating(dev
);
5418 static void ivybridge_init_clock_gating(struct drm_device
*dev
)
5420 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5423 ilk_init_lp_watermarks(dev
);
5425 I915_WRITE(ILK_DSPCLK_GATE_D
, ILK_VRHUNIT_CLOCK_GATE_DISABLE
);
5427 /* WaDisableEarlyCull:ivb */
5428 I915_WRITE(_3D_CHICKEN3
,
5429 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5431 /* WaDisableBackToBackFlipFix:ivb */
5432 I915_WRITE(IVB_CHICKEN3
,
5433 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5434 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5436 /* WaDisablePSDDualDispatchEnable:ivb */
5437 if (IS_IVB_GT1(dev
))
5438 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5439 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5441 /* WaDisable_RenderCache_OperationalFlush:ivb */
5442 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5444 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
5445 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1
,
5446 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC
);
5448 /* WaApplyL3ControlAndL3ChickenMode:ivb */
5449 I915_WRITE(GEN7_L3CNTLREG1
,
5450 GEN7_WA_FOR_GEN7_L3_CONTROL
);
5451 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER
,
5452 GEN7_WA_L3_CHICKEN_MODE
);
5453 if (IS_IVB_GT1(dev
))
5454 I915_WRITE(GEN7_ROW_CHICKEN2
,
5455 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5457 /* must write both registers */
5458 I915_WRITE(GEN7_ROW_CHICKEN2
,
5459 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5460 I915_WRITE(GEN7_ROW_CHICKEN2_GT2
,
5461 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5464 /* WaForceL3Serialization:ivb */
5465 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5466 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5469 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5470 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
5472 I915_WRITE(GEN6_UCGCTL2
,
5473 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5475 /* This is required by WaCatErrorRejectionIssue:ivb */
5476 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5477 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5478 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5480 g4x_disable_trickle_feed(dev
);
5482 gen7_setup_fixed_func_scheduler(dev_priv
);
5484 if (0) { /* causes HiZ corruption on ivb:gt1 */
5485 /* enable HiZ Raw Stall Optimization */
5486 I915_WRITE(CACHE_MODE_0_GEN7
,
5487 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE
));
5490 /* WaDisable4x2SubspanOptimization:ivb */
5491 I915_WRITE(CACHE_MODE_1
,
5492 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5495 * BSpec recommends 8x4 when MSAA is used,
5496 * however in practice 16x4 seems fastest.
5498 * Note that PS/WM thread counts depend on the WIZ hashing
5499 * disable bit, which we don't touch here, but it's good
5500 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
5502 I915_WRITE(GEN7_GT_MODE
,
5503 GEN6_WIZ_HASHING_MASK
| GEN6_WIZ_HASHING_16x4
);
5505 snpcr
= I915_READ(GEN6_MBCUNIT_SNPCR
);
5506 snpcr
&= ~GEN6_MBC_SNPCR_MASK
;
5507 snpcr
|= GEN6_MBC_SNPCR_MED
;
5508 I915_WRITE(GEN6_MBCUNIT_SNPCR
, snpcr
);
5510 if (!HAS_PCH_NOP(dev
))
5511 cpt_init_clock_gating(dev
);
5513 gen6_check_mch_setup(dev
);
5516 static void valleyview_init_clock_gating(struct drm_device
*dev
)
5518 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5521 mutex_lock(&dev_priv
->rps
.hw_lock
);
5522 val
= vlv_punit_read(dev_priv
, PUNIT_REG_GPU_FREQ_STS
);
5523 mutex_unlock(&dev_priv
->rps
.hw_lock
);
5524 switch ((val
>> 6) & 3) {
5527 dev_priv
->mem_freq
= 800;
5530 dev_priv
->mem_freq
= 1066;
5533 dev_priv
->mem_freq
= 1333;
5536 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv
->mem_freq
);
5538 dev_priv
->vlv_cdclk_freq
= valleyview_cur_cdclk(dev_priv
);
5539 DRM_DEBUG_DRIVER("Current CD clock rate: %d MHz",
5540 dev_priv
->vlv_cdclk_freq
);
5542 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5544 /* WaDisableEarlyCull:vlv */
5545 I915_WRITE(_3D_CHICKEN3
,
5546 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL
));
5548 /* WaDisableBackToBackFlipFix:vlv */
5549 I915_WRITE(IVB_CHICKEN3
,
5550 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE
|
5551 CHICKEN3_DGMG_DONE_FIX_DISABLE
);
5553 /* WaPsdDispatchEnable:vlv */
5554 /* WaDisablePSDDualDispatchEnable:vlv */
5555 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1
,
5556 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP
|
5557 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE
));
5559 /* WaDisable_RenderCache_OperationalFlush:vlv */
5560 I915_WRITE(CACHE_MODE_0_GEN7
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5562 /* WaForceL3Serialization:vlv */
5563 I915_WRITE(GEN7_L3SQCREG4
, I915_READ(GEN7_L3SQCREG4
) &
5564 ~L3SQ_URB_READ_CAM_MATCH_DISABLE
);
5566 /* WaDisableDopClockGating:vlv */
5567 I915_WRITE(GEN7_ROW_CHICKEN2
,
5568 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5570 /* This is required by WaCatErrorRejectionIssue:vlv */
5571 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
,
5572 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG
) |
5573 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB
);
5575 gen7_setup_fixed_func_scheduler(dev_priv
);
5578 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
5579 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
5581 I915_WRITE(GEN6_UCGCTL2
,
5582 GEN6_RCZUNIT_CLOCK_GATE_DISABLE
);
5584 /* WaDisableL3Bank2xClockGate:vlv
5585 * Disabling L3 clock gating- MMIO 940c[25] = 1
5586 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
5587 I915_WRITE(GEN7_UCGCTL4
,
5588 I915_READ(GEN7_UCGCTL4
) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE
);
5590 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5593 * BSpec says this must be set, even though
5594 * WaDisable4x2SubspanOptimization isn't listed for VLV.
5596 I915_WRITE(CACHE_MODE_1
,
5597 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE
));
5600 * WaIncreaseL3CreditsForVLVB0:vlv
5601 * This is the hardware default actually.
5603 I915_WRITE(GEN7_L3SQCREG1
, VLV_B0_WA_L3SQCREG1_VALUE
);
5606 * WaDisableVLVClockGating_VBIIssue:vlv
5607 * Disable clock gating on th GCFG unit to prevent a delay
5608 * in the reporting of vblank events.
5610 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, GCFG_DIS
);
5613 static void cherryview_init_clock_gating(struct drm_device
*dev
)
5615 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5617 I915_WRITE(DSPCLK_GATE_D
, VRHUNIT_CLOCK_GATE_DISABLE
);
5619 I915_WRITE(MI_ARB_VLV
, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
);
5621 /* WaDisablePartialInstShootdown:chv */
5622 I915_WRITE(GEN8_ROW_CHICKEN
,
5623 _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE
));
5625 /* WaDisableThreadStallDopClockGating:chv */
5626 I915_WRITE(GEN8_ROW_CHICKEN
,
5627 _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE
));
5629 /* WaVSRefCountFullforceMissDisable:chv */
5630 /* WaDSRefCountFullforceMissDisable:chv */
5631 I915_WRITE(GEN7_FF_THREAD_MODE
,
5632 I915_READ(GEN7_FF_THREAD_MODE
) &
5633 ~(GEN8_FF_DS_REF_CNT_FFME
| GEN7_FF_VS_REF_CNT_FFME
));
5635 /* WaDisableSemaphoreAndSyncFlipWait:chv */
5636 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5637 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE
));
5639 /* WaDisableCSUnitClockGating:chv */
5640 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
5641 GEN6_CSUNIT_CLOCK_GATE_DISABLE
);
5643 /* WaDisableSDEUnitClockGating:chv */
5644 I915_WRITE(GEN8_UCGCTL6
, I915_READ(GEN8_UCGCTL6
) |
5645 GEN8_SDEUNIT_CLOCK_GATE_DISABLE
);
5647 /* WaDisableSamplerPowerBypass:chv (pre-production hw) */
5648 I915_WRITE(HALF_SLICE_CHICKEN3
,
5649 _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS
));
5651 /* WaDisableGunitClockGating:chv (pre-production hw) */
5652 I915_WRITE(VLV_GUNIT_CLOCK_GATE
, I915_READ(VLV_GUNIT_CLOCK_GATE
) |
5655 /* WaDisableFfDopClockGating:chv (pre-production hw) */
5656 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL
,
5657 _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE
));
5659 /* WaDisableDopClockGating:chv (pre-production hw) */
5660 I915_WRITE(GEN7_ROW_CHICKEN2
,
5661 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE
));
5662 I915_WRITE(GEN6_UCGCTL1
, I915_READ(GEN6_UCGCTL1
) |
5663 GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE
);
5666 static void g4x_init_clock_gating(struct drm_device
*dev
)
5668 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5669 uint32_t dspclk_gate
;
5671 I915_WRITE(RENCLK_GATE_D1
, 0);
5672 I915_WRITE(RENCLK_GATE_D2
, VF_UNIT_CLOCK_GATE_DISABLE
|
5673 GS_UNIT_CLOCK_GATE_DISABLE
|
5674 CL_UNIT_CLOCK_GATE_DISABLE
);
5675 I915_WRITE(RAMCLK_GATE_D
, 0);
5676 dspclk_gate
= VRHUNIT_CLOCK_GATE_DISABLE
|
5677 OVRUNIT_CLOCK_GATE_DISABLE
|
5678 OVCUNIT_CLOCK_GATE_DISABLE
;
5680 dspclk_gate
|= DSSUNIT_CLOCK_GATE_DISABLE
;
5681 I915_WRITE(DSPCLK_GATE_D
, dspclk_gate
);
5683 /* WaDisableRenderCachePipelinedFlush */
5684 I915_WRITE(CACHE_MODE_0
,
5685 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE
));
5687 /* WaDisable_RenderCache_OperationalFlush:g4x */
5688 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5690 g4x_disable_trickle_feed(dev
);
5693 static void crestline_init_clock_gating(struct drm_device
*dev
)
5695 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5697 I915_WRITE(RENCLK_GATE_D1
, I965_RCC_CLOCK_GATE_DISABLE
);
5698 I915_WRITE(RENCLK_GATE_D2
, 0);
5699 I915_WRITE(DSPCLK_GATE_D
, 0);
5700 I915_WRITE(RAMCLK_GATE_D
, 0);
5701 I915_WRITE16(DEUC
, 0);
5702 I915_WRITE(MI_ARB_STATE
,
5703 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5705 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5706 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5709 static void broadwater_init_clock_gating(struct drm_device
*dev
)
5711 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5713 I915_WRITE(RENCLK_GATE_D1
, I965_RCZ_CLOCK_GATE_DISABLE
|
5714 I965_RCC_CLOCK_GATE_DISABLE
|
5715 I965_RCPB_CLOCK_GATE_DISABLE
|
5716 I965_ISC_CLOCK_GATE_DISABLE
|
5717 I965_FBC_CLOCK_GATE_DISABLE
);
5718 I915_WRITE(RENCLK_GATE_D2
, 0);
5719 I915_WRITE(MI_ARB_STATE
,
5720 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE
));
5722 /* WaDisable_RenderCache_OperationalFlush:gen4 */
5723 I915_WRITE(CACHE_MODE_0
, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE
));
5726 static void gen3_init_clock_gating(struct drm_device
*dev
)
5728 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5729 u32 dstate
= I915_READ(D_STATE
);
5731 dstate
|= DSTATE_PLL_D3_OFF
| DSTATE_GFX_CLOCK_GATING
|
5732 DSTATE_DOT_CLOCK_GATING
;
5733 I915_WRITE(D_STATE
, dstate
);
5735 if (IS_PINEVIEW(dev
))
5736 I915_WRITE(ECOSKPD
, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY
));
5738 /* IIR "flip pending" means done if this bit is set */
5739 I915_WRITE(ECOSKPD
, _MASKED_BIT_DISABLE(ECO_FLIP_DONE
));
5741 /* interrupts should cause a wake up from C3 */
5742 I915_WRITE(INSTPM
, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN
));
5744 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
5745 I915_WRITE(MI_ARB_STATE
, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
5748 static void i85x_init_clock_gating(struct drm_device
*dev
)
5750 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5752 I915_WRITE(RENCLK_GATE_D1
, SV_CLOCK_GATE_DISABLE
);
5754 /* interrupts should cause a wake up from C3 */
5755 I915_WRITE(MI_STATE
, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN
) |
5756 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE
));
5759 static void i830_init_clock_gating(struct drm_device
*dev
)
5761 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5763 I915_WRITE(DSPCLK_GATE_D
, OVRUNIT_CLOCK_GATE_DISABLE
);
5766 void intel_init_clock_gating(struct drm_device
*dev
)
5768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5770 dev_priv
->display
.init_clock_gating(dev
);
5773 void intel_suspend_hw(struct drm_device
*dev
)
5775 if (HAS_PCH_LPT(dev
))
5776 lpt_suspend_hw(dev
);
5779 #define for_each_power_well(i, power_well, domain_mask, power_domains) \
5781 i < (power_domains)->power_well_count && \
5782 ((power_well) = &(power_domains)->power_wells[i]); \
5784 if ((power_well)->domains & (domain_mask))
5786 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
5787 for (i = (power_domains)->power_well_count - 1; \
5788 i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
5790 if ((power_well)->domains & (domain_mask))
5793 * We should only use the power well if we explicitly asked the hardware to
5794 * enable it, so check if it's enabled and also check if we've requested it to
5797 static bool hsw_power_well_enabled(struct drm_i915_private
*dev_priv
,
5798 struct i915_power_well
*power_well
)
5800 return I915_READ(HSW_PWR_WELL_DRIVER
) ==
5801 (HSW_PWR_WELL_ENABLE_REQUEST
| HSW_PWR_WELL_STATE_ENABLED
);
5804 bool intel_display_power_enabled_sw(struct drm_i915_private
*dev_priv
,
5805 enum intel_display_power_domain domain
)
5807 struct i915_power_domains
*power_domains
;
5808 struct i915_power_well
*power_well
;
5812 if (dev_priv
->pm
.suspended
)
5815 power_domains
= &dev_priv
->power_domains
;
5817 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
5818 if (power_well
->always_on
)
5821 if (!power_well
->count
) {
5829 bool intel_display_power_enabled(struct drm_i915_private
*dev_priv
,
5830 enum intel_display_power_domain domain
)
5832 struct i915_power_domains
*power_domains
;
5833 struct i915_power_well
*power_well
;
5837 if (dev_priv
->pm
.suspended
)
5840 power_domains
= &dev_priv
->power_domains
;
5844 mutex_lock(&power_domains
->lock
);
5845 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
5846 if (power_well
->always_on
)
5849 if (!power_well
->ops
->is_enabled(dev_priv
, power_well
)) {
5854 mutex_unlock(&power_domains
->lock
);
5860 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5861 * when not needed anymore. We have 4 registers that can request the power well
5862 * to be enabled, and it will only be disabled if none of the registers is
5863 * requesting it to be enabled.
5865 static void hsw_power_well_post_enable(struct drm_i915_private
*dev_priv
)
5867 struct drm_device
*dev
= dev_priv
->dev
;
5868 unsigned long irqflags
;
5871 * After we re-enable the power well, if we touch VGA register 0x3d5
5872 * we'll get unclaimed register interrupts. This stops after we write
5873 * anything to the VGA MSR register. The vgacon module uses this
5874 * register all the time, so if we unbind our driver and, as a
5875 * consequence, bind vgacon, we'll get stuck in an infinite loop at
5876 * console_unlock(). So make here we touch the VGA MSR register, making
5877 * sure vgacon can keep working normally without triggering interrupts
5878 * and error messages.
5880 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
5881 outb(inb(VGA_MSR_READ
), VGA_MSR_WRITE
);
5882 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
5884 if (IS_BROADWELL(dev
)) {
5885 spin_lock_irqsave(&dev_priv
->irq_lock
, irqflags
);
5886 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_B
),
5887 dev_priv
->de_irq_mask
[PIPE_B
]);
5888 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_B
),
5889 ~dev_priv
->de_irq_mask
[PIPE_B
] |
5891 I915_WRITE(GEN8_DE_PIPE_IMR(PIPE_C
),
5892 dev_priv
->de_irq_mask
[PIPE_C
]);
5893 I915_WRITE(GEN8_DE_PIPE_IER(PIPE_C
),
5894 ~dev_priv
->de_irq_mask
[PIPE_C
] |
5896 POSTING_READ(GEN8_DE_PIPE_IER(PIPE_C
));
5897 spin_unlock_irqrestore(&dev_priv
->irq_lock
, irqflags
);
5901 static void hsw_set_power_well(struct drm_i915_private
*dev_priv
,
5902 struct i915_power_well
*power_well
, bool enable
)
5904 bool is_enabled
, enable_requested
;
5907 tmp
= I915_READ(HSW_PWR_WELL_DRIVER
);
5908 is_enabled
= tmp
& HSW_PWR_WELL_STATE_ENABLED
;
5909 enable_requested
= tmp
& HSW_PWR_WELL_ENABLE_REQUEST
;
5912 if (!enable_requested
)
5913 I915_WRITE(HSW_PWR_WELL_DRIVER
,
5914 HSW_PWR_WELL_ENABLE_REQUEST
);
5917 DRM_DEBUG_KMS("Enabling power well\n");
5918 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER
) &
5919 HSW_PWR_WELL_STATE_ENABLED
), 20))
5920 DRM_ERROR("Timeout enabling power well\n");
5923 hsw_power_well_post_enable(dev_priv
);
5925 if (enable_requested
) {
5926 I915_WRITE(HSW_PWR_WELL_DRIVER
, 0);
5927 POSTING_READ(HSW_PWR_WELL_DRIVER
);
5928 DRM_DEBUG_KMS("Requesting to disable the power well\n");
5933 static void hsw_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
5934 struct i915_power_well
*power_well
)
5936 hsw_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
5939 * We're taking over the BIOS, so clear any requests made by it since
5940 * the driver is in charge now.
5942 if (I915_READ(HSW_PWR_WELL_BIOS
) & HSW_PWR_WELL_ENABLE_REQUEST
)
5943 I915_WRITE(HSW_PWR_WELL_BIOS
, 0);
5946 static void hsw_power_well_enable(struct drm_i915_private
*dev_priv
,
5947 struct i915_power_well
*power_well
)
5949 hsw_set_power_well(dev_priv
, power_well
, true);
5952 static void hsw_power_well_disable(struct drm_i915_private
*dev_priv
,
5953 struct i915_power_well
*power_well
)
5955 hsw_set_power_well(dev_priv
, power_well
, false);
5958 static void i9xx_always_on_power_well_noop(struct drm_i915_private
*dev_priv
,
5959 struct i915_power_well
*power_well
)
5963 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private
*dev_priv
,
5964 struct i915_power_well
*power_well
)
5969 void __vlv_set_power_well(struct drm_i915_private
*dev_priv
,
5970 enum punit_power_well power_well_id
, bool enable
)
5972 struct drm_device
*dev
= dev_priv
->dev
;
5978 if (power_well_id
== PUNIT_POWER_WELL_DPIO_CMN_BC
) {
5981 * Enable the CRI clock source so we can get at the
5982 * display and the reference clock for VGA
5983 * hotplug / manual detection.
5985 I915_WRITE(DPLL(PIPE_B
), I915_READ(DPLL(PIPE_B
)) |
5986 DPLL_REFA_CLK_ENABLE_VLV
|
5987 DPLL_INTEGRATED_CRI_CLK_VLV
);
5988 udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
5991 assert_pll_disabled(dev_priv
, pipe
);
5992 /* Assert common reset */
5993 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) &
5998 mask
= PUNIT_PWRGT_MASK(power_well_id
);
5999 state
= enable
? PUNIT_PWRGT_PWR_ON(power_well_id
) :
6000 PUNIT_PWRGT_PWR_GATE(power_well_id
);
6002 mutex_lock(&dev_priv
->rps
.hw_lock
);
6005 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
6010 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
);
6013 vlv_punit_write(dev_priv
, PUNIT_REG_PWRGT_CTRL
, ctrl
);
6015 if (wait_for(COND
, 100))
6016 DRM_ERROR("timout setting power well state %08x (%08x)\n",
6018 vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
));
6023 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6026 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
6027 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
6028 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
6029 * b. The other bits such as sfr settings / modesel may all
6032 * This should only be done on init and resume from S3 with
6033 * both PLLs disabled, or we risk losing DPIO and PLL
6036 if (power_well_id
== PUNIT_POWER_WELL_DPIO_CMN_BC
&& enable
)
6037 I915_WRITE(DPIO_CTL
, I915_READ(DPIO_CTL
) | DPIO_CMNRST
);
6040 static void vlv_set_power_well(struct drm_i915_private
*dev_priv
,
6041 struct i915_power_well
*power_well
, bool enable
)
6043 enum punit_power_well power_well_id
= power_well
->data
;
6045 __vlv_set_power_well(dev_priv
, power_well_id
, enable
);
6048 static void vlv_power_well_sync_hw(struct drm_i915_private
*dev_priv
,
6049 struct i915_power_well
*power_well
)
6051 vlv_set_power_well(dev_priv
, power_well
, power_well
->count
> 0);
6054 static void vlv_power_well_enable(struct drm_i915_private
*dev_priv
,
6055 struct i915_power_well
*power_well
)
6057 vlv_set_power_well(dev_priv
, power_well
, true);
6060 static void vlv_power_well_disable(struct drm_i915_private
*dev_priv
,
6061 struct i915_power_well
*power_well
)
6063 vlv_set_power_well(dev_priv
, power_well
, false);
6066 static bool vlv_power_well_enabled(struct drm_i915_private
*dev_priv
,
6067 struct i915_power_well
*power_well
)
6069 int power_well_id
= power_well
->data
;
6070 bool enabled
= false;
6075 mask
= PUNIT_PWRGT_MASK(power_well_id
);
6076 ctrl
= PUNIT_PWRGT_PWR_ON(power_well_id
);
6078 mutex_lock(&dev_priv
->rps
.hw_lock
);
6080 state
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_STATUS
) & mask
;
6082 * We only ever set the power-on and power-gate states, anything
6083 * else is unexpected.
6085 WARN_ON(state
!= PUNIT_PWRGT_PWR_ON(power_well_id
) &&
6086 state
!= PUNIT_PWRGT_PWR_GATE(power_well_id
));
6091 * A transient state at this point would mean some unexpected party
6092 * is poking at the power controls too.
6094 ctrl
= vlv_punit_read(dev_priv
, PUNIT_REG_PWRGT_CTRL
) & mask
;
6095 WARN_ON(ctrl
!= state
);
6097 mutex_unlock(&dev_priv
->rps
.hw_lock
);
6102 static void vlv_display_power_well_enable(struct drm_i915_private
*dev_priv
,
6103 struct i915_power_well
*power_well
)
6105 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6107 vlv_set_power_well(dev_priv
, power_well
, true);
6109 spin_lock_irq(&dev_priv
->irq_lock
);
6110 valleyview_enable_display_irqs(dev_priv
);
6111 spin_unlock_irq(&dev_priv
->irq_lock
);
6114 * During driver initialization/resume we can avoid restoring the
6115 * part of the HW/SW state that will be inited anyway explicitly.
6117 if (dev_priv
->power_domains
.initializing
)
6120 intel_hpd_init(dev_priv
->dev
);
6122 i915_redisable_vga_power_on(dev_priv
->dev
);
6125 static void vlv_display_power_well_disable(struct drm_i915_private
*dev_priv
,
6126 struct i915_power_well
*power_well
)
6128 WARN_ON_ONCE(power_well
->data
!= PUNIT_POWER_WELL_DISP2D
);
6130 spin_lock_irq(&dev_priv
->irq_lock
);
6131 valleyview_disable_display_irqs(dev_priv
);
6132 spin_unlock_irq(&dev_priv
->irq_lock
);
6134 vlv_set_power_well(dev_priv
, power_well
, false);
6137 static void check_power_well_state(struct drm_i915_private
*dev_priv
,
6138 struct i915_power_well
*power_well
)
6140 bool enabled
= power_well
->ops
->is_enabled(dev_priv
, power_well
);
6142 if (power_well
->always_on
|| !i915
.disable_power_well
) {
6149 if (enabled
!= (power_well
->count
> 0))
6155 WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n",
6156 power_well
->name
, power_well
->always_on
, enabled
,
6157 power_well
->count
, i915
.disable_power_well
);
6160 void intel_display_power_get(struct drm_i915_private
*dev_priv
,
6161 enum intel_display_power_domain domain
)
6163 struct i915_power_domains
*power_domains
;
6164 struct i915_power_well
*power_well
;
6167 intel_runtime_pm_get(dev_priv
);
6169 power_domains
= &dev_priv
->power_domains
;
6171 mutex_lock(&power_domains
->lock
);
6173 for_each_power_well(i
, power_well
, BIT(domain
), power_domains
) {
6174 if (!power_well
->count
++) {
6175 DRM_DEBUG_KMS("enabling %s\n", power_well
->name
);
6176 power_well
->ops
->enable(dev_priv
, power_well
);
6179 check_power_well_state(dev_priv
, power_well
);
6182 power_domains
->domain_use_count
[domain
]++;
6184 mutex_unlock(&power_domains
->lock
);
6187 void intel_display_power_put(struct drm_i915_private
*dev_priv
,
6188 enum intel_display_power_domain domain
)
6190 struct i915_power_domains
*power_domains
;
6191 struct i915_power_well
*power_well
;
6194 power_domains
= &dev_priv
->power_domains
;
6196 mutex_lock(&power_domains
->lock
);
6198 WARN_ON(!power_domains
->domain_use_count
[domain
]);
6199 power_domains
->domain_use_count
[domain
]--;
6201 for_each_power_well_rev(i
, power_well
, BIT(domain
), power_domains
) {
6202 WARN_ON(!power_well
->count
);
6204 if (!--power_well
->count
&& i915
.disable_power_well
) {
6205 DRM_DEBUG_KMS("disabling %s\n", power_well
->name
);
6206 power_well
->ops
->disable(dev_priv
, power_well
);
6209 check_power_well_state(dev_priv
, power_well
);
6212 mutex_unlock(&power_domains
->lock
);
6214 intel_runtime_pm_put(dev_priv
);
6217 static struct i915_power_domains
*hsw_pwr
;
6219 /* Display audio driver power well request */
6220 void i915_request_power_well(void)
6222 struct drm_i915_private
*dev_priv
;
6224 if (WARN_ON(!hsw_pwr
))
6227 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6229 intel_display_power_get(dev_priv
, POWER_DOMAIN_AUDIO
);
6231 EXPORT_SYMBOL_GPL(i915_request_power_well
);
6233 /* Display audio driver power well release */
6234 void i915_release_power_well(void)
6236 struct drm_i915_private
*dev_priv
;
6238 if (WARN_ON(!hsw_pwr
))
6241 dev_priv
= container_of(hsw_pwr
, struct drm_i915_private
,
6243 intel_display_power_put(dev_priv
, POWER_DOMAIN_AUDIO
);
6245 EXPORT_SYMBOL_GPL(i915_release_power_well
);
6247 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
6249 #define HSW_ALWAYS_ON_POWER_DOMAINS ( \
6250 BIT(POWER_DOMAIN_PIPE_A) | \
6251 BIT(POWER_DOMAIN_TRANSCODER_EDP) | \
6252 BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \
6253 BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \
6254 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6255 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6256 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6257 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6258 BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \
6259 BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \
6260 BIT(POWER_DOMAIN_PORT_CRT) | \
6261 BIT(POWER_DOMAIN_INIT))
6262 #define HSW_DISPLAY_POWER_DOMAINS ( \
6263 (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \
6264 BIT(POWER_DOMAIN_INIT))
6266 #define BDW_ALWAYS_ON_POWER_DOMAINS ( \
6267 HSW_ALWAYS_ON_POWER_DOMAINS | \
6268 BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
6269 #define BDW_DISPLAY_POWER_DOMAINS ( \
6270 (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \
6271 BIT(POWER_DOMAIN_INIT))
6273 #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT)
6274 #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK
6276 #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
6277 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6278 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6279 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6280 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6281 BIT(POWER_DOMAIN_PORT_CRT) | \
6282 BIT(POWER_DOMAIN_INIT))
6284 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
6285 BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \
6286 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6287 BIT(POWER_DOMAIN_INIT))
6289 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
6290 BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \
6291 BIT(POWER_DOMAIN_INIT))
6293 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
6294 BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \
6295 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6296 BIT(POWER_DOMAIN_INIT))
6298 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
6299 BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \
6300 BIT(POWER_DOMAIN_INIT))
6302 static const struct i915_power_well_ops i9xx_always_on_power_well_ops
= {
6303 .sync_hw
= i9xx_always_on_power_well_noop
,
6304 .enable
= i9xx_always_on_power_well_noop
,
6305 .disable
= i9xx_always_on_power_well_noop
,
6306 .is_enabled
= i9xx_always_on_power_well_enabled
,
6309 static struct i915_power_well i9xx_always_on_power_well
[] = {
6311 .name
= "always-on",
6313 .domains
= POWER_DOMAIN_MASK
,
6314 .ops
= &i9xx_always_on_power_well_ops
,
6318 static const struct i915_power_well_ops hsw_power_well_ops
= {
6319 .sync_hw
= hsw_power_well_sync_hw
,
6320 .enable
= hsw_power_well_enable
,
6321 .disable
= hsw_power_well_disable
,
6322 .is_enabled
= hsw_power_well_enabled
,
6325 static struct i915_power_well hsw_power_wells
[] = {
6327 .name
= "always-on",
6329 .domains
= HSW_ALWAYS_ON_POWER_DOMAINS
,
6330 .ops
= &i9xx_always_on_power_well_ops
,
6334 .domains
= HSW_DISPLAY_POWER_DOMAINS
,
6335 .ops
= &hsw_power_well_ops
,
6339 static struct i915_power_well bdw_power_wells
[] = {
6341 .name
= "always-on",
6343 .domains
= BDW_ALWAYS_ON_POWER_DOMAINS
,
6344 .ops
= &i9xx_always_on_power_well_ops
,
6348 .domains
= BDW_DISPLAY_POWER_DOMAINS
,
6349 .ops
= &hsw_power_well_ops
,
6353 static const struct i915_power_well_ops vlv_display_power_well_ops
= {
6354 .sync_hw
= vlv_power_well_sync_hw
,
6355 .enable
= vlv_display_power_well_enable
,
6356 .disable
= vlv_display_power_well_disable
,
6357 .is_enabled
= vlv_power_well_enabled
,
6360 static const struct i915_power_well_ops vlv_dpio_power_well_ops
= {
6361 .sync_hw
= vlv_power_well_sync_hw
,
6362 .enable
= vlv_power_well_enable
,
6363 .disable
= vlv_power_well_disable
,
6364 .is_enabled
= vlv_power_well_enabled
,
6367 static struct i915_power_well vlv_power_wells
[] = {
6369 .name
= "always-on",
6371 .domains
= VLV_ALWAYS_ON_POWER_DOMAINS
,
6372 .ops
= &i9xx_always_on_power_well_ops
,
6376 .domains
= VLV_DISPLAY_POWER_DOMAINS
,
6377 .data
= PUNIT_POWER_WELL_DISP2D
,
6378 .ops
= &vlv_display_power_well_ops
,
6381 .name
= "dpio-tx-b-01",
6382 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6383 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6384 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6385 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6386 .ops
= &vlv_dpio_power_well_ops
,
6387 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_01
,
6390 .name
= "dpio-tx-b-23",
6391 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6392 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6393 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6394 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6395 .ops
= &vlv_dpio_power_well_ops
,
6396 .data
= PUNIT_POWER_WELL_DPIO_TX_B_LANES_23
,
6399 .name
= "dpio-tx-c-01",
6400 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6401 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6402 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6403 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6404 .ops
= &vlv_dpio_power_well_ops
,
6405 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_01
,
6408 .name
= "dpio-tx-c-23",
6409 .domains
= VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS
|
6410 VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS
|
6411 VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS
|
6412 VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS
,
6413 .ops
= &vlv_dpio_power_well_ops
,
6414 .data
= PUNIT_POWER_WELL_DPIO_TX_C_LANES_23
,
6417 .name
= "dpio-common",
6418 .domains
= VLV_DPIO_CMN_BC_POWER_DOMAINS
,
6419 .data
= PUNIT_POWER_WELL_DPIO_CMN_BC
,
6420 .ops
= &vlv_dpio_power_well_ops
,
6424 #define set_power_wells(power_domains, __power_wells) ({ \
6425 (power_domains)->power_wells = (__power_wells); \
6426 (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \
6429 int intel_power_domains_init(struct drm_i915_private
*dev_priv
)
6431 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6433 mutex_init(&power_domains
->lock
);
6436 * The enabling order will be from lower to higher indexed wells,
6437 * the disabling order is reversed.
6439 if (IS_HASWELL(dev_priv
->dev
)) {
6440 set_power_wells(power_domains
, hsw_power_wells
);
6441 hsw_pwr
= power_domains
;
6442 } else if (IS_BROADWELL(dev_priv
->dev
)) {
6443 set_power_wells(power_domains
, bdw_power_wells
);
6444 hsw_pwr
= power_domains
;
6445 } else if (IS_VALLEYVIEW(dev_priv
->dev
)) {
6446 set_power_wells(power_domains
, vlv_power_wells
);
6448 set_power_wells(power_domains
, i9xx_always_on_power_well
);
6454 void intel_power_domains_remove(struct drm_i915_private
*dev_priv
)
6459 static void intel_power_domains_resume(struct drm_i915_private
*dev_priv
)
6461 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6462 struct i915_power_well
*power_well
;
6465 mutex_lock(&power_domains
->lock
);
6466 for_each_power_well(i
, power_well
, POWER_DOMAIN_MASK
, power_domains
)
6467 power_well
->ops
->sync_hw(dev_priv
, power_well
);
6468 mutex_unlock(&power_domains
->lock
);
6471 void intel_power_domains_init_hw(struct drm_i915_private
*dev_priv
)
6473 struct i915_power_domains
*power_domains
= &dev_priv
->power_domains
;
6475 power_domains
->initializing
= true;
6476 /* For now, we need the power well to be always enabled. */
6477 intel_display_set_init_power(dev_priv
, true);
6478 intel_power_domains_resume(dev_priv
);
6479 power_domains
->initializing
= false;
6482 void intel_aux_display_runtime_get(struct drm_i915_private
*dev_priv
)
6484 intel_runtime_pm_get(dev_priv
);
6487 void intel_aux_display_runtime_put(struct drm_i915_private
*dev_priv
)
6489 intel_runtime_pm_put(dev_priv
);
6492 void intel_runtime_pm_get(struct drm_i915_private
*dev_priv
)
6494 struct drm_device
*dev
= dev_priv
->dev
;
6495 struct device
*device
= &dev
->pdev
->dev
;
6497 if (!HAS_RUNTIME_PM(dev
))
6500 pm_runtime_get_sync(device
);
6501 WARN(dev_priv
->pm
.suspended
, "Device still suspended.\n");
6504 void intel_runtime_pm_get_noresume(struct drm_i915_private
*dev_priv
)
6506 struct drm_device
*dev
= dev_priv
->dev
;
6507 struct device
*device
= &dev
->pdev
->dev
;
6509 if (!HAS_RUNTIME_PM(dev
))
6512 WARN(dev_priv
->pm
.suspended
, "Getting nosync-ref while suspended.\n");
6513 pm_runtime_get_noresume(device
);
6516 void intel_runtime_pm_put(struct drm_i915_private
*dev_priv
)
6518 struct drm_device
*dev
= dev_priv
->dev
;
6519 struct device
*device
= &dev
->pdev
->dev
;
6521 if (!HAS_RUNTIME_PM(dev
))
6524 pm_runtime_mark_last_busy(device
);
6525 pm_runtime_put_autosuspend(device
);
6528 void intel_init_runtime_pm(struct drm_i915_private
*dev_priv
)
6530 struct drm_device
*dev
= dev_priv
->dev
;
6531 struct device
*device
= &dev
->pdev
->dev
;
6533 if (!HAS_RUNTIME_PM(dev
))
6536 pm_runtime_set_active(device
);
6539 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6542 if (!intel_enable_rc6(dev
)) {
6543 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6547 pm_runtime_set_autosuspend_delay(device
, 10000); /* 10s */
6548 pm_runtime_mark_last_busy(device
);
6549 pm_runtime_use_autosuspend(device
);
6551 pm_runtime_put_autosuspend(device
);
6554 void intel_fini_runtime_pm(struct drm_i915_private
*dev_priv
)
6556 struct drm_device
*dev
= dev_priv
->dev
;
6557 struct device
*device
= &dev
->pdev
->dev
;
6559 if (!HAS_RUNTIME_PM(dev
))
6562 if (!intel_enable_rc6(dev
))
6565 /* Make sure we're not suspended first. */
6566 pm_runtime_get_sync(device
);
6567 pm_runtime_disable(device
);
6570 /* Set up chip specific power management-related functions */
6571 void intel_init_pm(struct drm_device
*dev
)
6573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6576 if (INTEL_INFO(dev
)->gen
>= 7) {
6577 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
6578 dev_priv
->display
.enable_fbc
= gen7_enable_fbc
;
6579 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
6580 } else if (INTEL_INFO(dev
)->gen
>= 5) {
6581 dev_priv
->display
.fbc_enabled
= ironlake_fbc_enabled
;
6582 dev_priv
->display
.enable_fbc
= ironlake_enable_fbc
;
6583 dev_priv
->display
.disable_fbc
= ironlake_disable_fbc
;
6584 } else if (IS_GM45(dev
)) {
6585 dev_priv
->display
.fbc_enabled
= g4x_fbc_enabled
;
6586 dev_priv
->display
.enable_fbc
= g4x_enable_fbc
;
6587 dev_priv
->display
.disable_fbc
= g4x_disable_fbc
;
6589 dev_priv
->display
.fbc_enabled
= i8xx_fbc_enabled
;
6590 dev_priv
->display
.enable_fbc
= i8xx_enable_fbc
;
6591 dev_priv
->display
.disable_fbc
= i8xx_disable_fbc
;
6593 /* This value was pulled out of someone's hat */
6594 I915_WRITE(FBC_CONTROL
, 500 << FBC_CTL_INTERVAL_SHIFT
);
6599 if (IS_PINEVIEW(dev
))
6600 i915_pineview_get_mem_freq(dev
);
6601 else if (IS_GEN5(dev
))
6602 i915_ironlake_get_mem_freq(dev
);
6604 /* For FIFO watermark updates */
6605 if (HAS_PCH_SPLIT(dev
)) {
6606 ilk_setup_wm_latency(dev
);
6608 if ((IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[1] &&
6609 dev_priv
->wm
.spr_latency
[1] && dev_priv
->wm
.cur_latency
[1]) ||
6610 (!IS_GEN5(dev
) && dev_priv
->wm
.pri_latency
[0] &&
6611 dev_priv
->wm
.spr_latency
[0] && dev_priv
->wm
.cur_latency
[0])) {
6612 dev_priv
->display
.update_wm
= ilk_update_wm
;
6613 dev_priv
->display
.update_sprite_wm
= ilk_update_sprite_wm
;
6615 DRM_DEBUG_KMS("Failed to read display plane latency. "
6620 dev_priv
->display
.init_clock_gating
= ironlake_init_clock_gating
;
6621 else if (IS_GEN6(dev
))
6622 dev_priv
->display
.init_clock_gating
= gen6_init_clock_gating
;
6623 else if (IS_IVYBRIDGE(dev
))
6624 dev_priv
->display
.init_clock_gating
= ivybridge_init_clock_gating
;
6625 else if (IS_HASWELL(dev
))
6626 dev_priv
->display
.init_clock_gating
= haswell_init_clock_gating
;
6627 else if (INTEL_INFO(dev
)->gen
== 8)
6628 dev_priv
->display
.init_clock_gating
= gen8_init_clock_gating
;
6629 } else if (IS_CHERRYVIEW(dev
)) {
6630 dev_priv
->display
.update_wm
= valleyview_update_wm
;
6631 dev_priv
->display
.init_clock_gating
=
6632 cherryview_init_clock_gating
;
6633 } else if (IS_VALLEYVIEW(dev
)) {
6634 dev_priv
->display
.update_wm
= valleyview_update_wm
;
6635 dev_priv
->display
.init_clock_gating
=
6636 valleyview_init_clock_gating
;
6637 } else if (IS_PINEVIEW(dev
)) {
6638 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev
),
6641 dev_priv
->mem_freq
)) {
6642 DRM_INFO("failed to find known CxSR latency "
6643 "(found ddr%s fsb freq %d, mem freq %d), "
6645 (dev_priv
->is_ddr3
== 1) ? "3" : "2",
6646 dev_priv
->fsb_freq
, dev_priv
->mem_freq
);
6647 /* Disable CxSR and never update its watermark again */
6648 pineview_disable_cxsr(dev
);
6649 dev_priv
->display
.update_wm
= NULL
;
6651 dev_priv
->display
.update_wm
= pineview_update_wm
;
6652 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6653 } else if (IS_G4X(dev
)) {
6654 dev_priv
->display
.update_wm
= g4x_update_wm
;
6655 dev_priv
->display
.init_clock_gating
= g4x_init_clock_gating
;
6656 } else if (IS_GEN4(dev
)) {
6657 dev_priv
->display
.update_wm
= i965_update_wm
;
6658 if (IS_CRESTLINE(dev
))
6659 dev_priv
->display
.init_clock_gating
= crestline_init_clock_gating
;
6660 else if (IS_BROADWATER(dev
))
6661 dev_priv
->display
.init_clock_gating
= broadwater_init_clock_gating
;
6662 } else if (IS_GEN3(dev
)) {
6663 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6664 dev_priv
->display
.get_fifo_size
= i9xx_get_fifo_size
;
6665 dev_priv
->display
.init_clock_gating
= gen3_init_clock_gating
;
6666 } else if (IS_GEN2(dev
)) {
6667 if (INTEL_INFO(dev
)->num_pipes
== 1) {
6668 dev_priv
->display
.update_wm
= i845_update_wm
;
6669 dev_priv
->display
.get_fifo_size
= i845_get_fifo_size
;
6671 dev_priv
->display
.update_wm
= i9xx_update_wm
;
6672 dev_priv
->display
.get_fifo_size
= i830_get_fifo_size
;
6675 if (IS_I85X(dev
) || IS_I865G(dev
))
6676 dev_priv
->display
.init_clock_gating
= i85x_init_clock_gating
;
6678 dev_priv
->display
.init_clock_gating
= i830_init_clock_gating
;
6680 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
6684 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
)
6686 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6688 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6689 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6693 I915_WRITE(GEN6_PCODE_DATA
, *val
);
6694 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6696 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6698 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox
);
6702 *val
= I915_READ(GEN6_PCODE_DATA
);
6703 I915_WRITE(GEN6_PCODE_DATA
, 0);
6708 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
)
6710 WARN_ON(!mutex_is_locked(&dev_priv
->rps
.hw_lock
));
6712 if (I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) {
6713 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6717 I915_WRITE(GEN6_PCODE_DATA
, val
);
6718 I915_WRITE(GEN6_PCODE_MAILBOX
, GEN6_PCODE_READY
| mbox
);
6720 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX
) & GEN6_PCODE_READY
) == 0,
6722 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox
);
6726 I915_WRITE(GEN6_PCODE_DATA
, 0);
6731 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
)
6736 switch (dev_priv
->mem_freq
) {
6750 return DIV_ROUND_CLOSEST(dev_priv
->mem_freq
* (val
+ 6 - 0xbd), 4 * div
);
6753 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
)
6758 switch (dev_priv
->mem_freq
) {
6772 return DIV_ROUND_CLOSEST(4 * mul
* val
, dev_priv
->mem_freq
) + 0xbd - 6;
6775 void intel_pm_setup(struct drm_device
*dev
)
6777 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6779 mutex_init(&dev_priv
->rps
.hw_lock
);
6781 INIT_DELAYED_WORK(&dev_priv
->rps
.delayed_resume_work
,
6782 intel_gen6_powersave_work
);
6784 dev_priv
->pm
.suspended
= false;
6785 dev_priv
->pm
.irqs_disabled
= false;