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drm/i915: Force PSR exit by inactivating it.
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / i915 / intel_display.c
blob2fdbedfc970e0d1ae0ef930334b342ea16b1cf14
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_dp_helper.h>
41 #include <drm/drm_crtc_helper.h>
42 #include <drm/drm_plane_helper.h>
43 #include <drm/drm_rect.h>
44 #include <linux/dma_remapping.h>
45
46 /* Primary plane formats supported by all gen */
47 #define COMMON_PRIMARY_FORMATS \
48 DRM_FORMAT_C8, \
49 DRM_FORMAT_RGB565, \
50 DRM_FORMAT_XRGB8888, \
51 DRM_FORMAT_ARGB8888
52
53 /* Primary plane formats for gen <= 3 */
54 static const uint32_t intel_primary_formats_gen2[] = {
55 COMMON_PRIMARY_FORMATS,
56 DRM_FORMAT_XRGB1555,
57 DRM_FORMAT_ARGB1555,
58 };
59
60 /* Primary plane formats for gen >= 4 */
61 static const uint32_t intel_primary_formats_gen4[] = {
62 COMMON_PRIMARY_FORMATS, \
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_ABGR8888,
65 DRM_FORMAT_XRGB2101010,
66 DRM_FORMAT_ARGB2101010,
67 DRM_FORMAT_XBGR2101010,
68 DRM_FORMAT_ABGR2101010,
69 };
70
71 /* Cursor formats */
72 static const uint32_t intel_cursor_formats[] = {
73 DRM_FORMAT_ARGB8888,
74 };
75
76 #define DIV_ROUND_CLOSEST_ULL(ll, d) \
77 ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; })
78
79 static void intel_increase_pllclock(struct drm_crtc *crtc);
80 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
81
82 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
83 struct intel_crtc_config *pipe_config);
84 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
85 struct intel_crtc_config *pipe_config);
86
87 static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
88 int x, int y, struct drm_framebuffer *old_fb);
89 static int intel_framebuffer_init(struct drm_device *dev,
90 struct intel_framebuffer *ifb,
91 struct drm_mode_fb_cmd2 *mode_cmd,
92 struct drm_i915_gem_object *obj);
93 static void intel_dp_set_m_n(struct intel_crtc *crtc);
94 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
96 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
97 struct intel_link_m_n *m_n);
98 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
99 static void haswell_set_pipeconf(struct drm_crtc *crtc);
100 static void intel_set_pipe_csc(struct drm_crtc *crtc);
101 static void vlv_prepare_pll(struct intel_crtc *crtc);
102
103 typedef struct {
104 int min, max;
105 } intel_range_t;
106
107 typedef struct {
108 int dot_limit;
109 int p2_slow, p2_fast;
110 } intel_p2_t;
111
112 typedef struct intel_limit intel_limit_t;
113 struct intel_limit {
114 intel_range_t dot, vco, n, m, m1, m2, p, p1;
115 intel_p2_t p2;
116 };
117
118 int
119 intel_pch_rawclk(struct drm_device *dev)
120 {
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 WARN_ON(!HAS_PCH_SPLIT(dev));
124
125 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
126 }
127
128 static inline u32 /* units of 100MHz */
129 intel_fdi_link_freq(struct drm_device *dev)
130 {
131 if (IS_GEN5(dev)) {
132 struct drm_i915_private *dev_priv = dev->dev_private;
133 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
134 } else
135 return 27;
136 }
137
138 static const intel_limit_t intel_limits_i8xx_dac = {
139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 908000, .max = 1512000 },
141 .n = { .min = 2, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 2, .max = 33 },
147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 4, .p2_fast = 2 },
149 };
150
151 static const intel_limit_t intel_limits_i8xx_dvo = {
152 .dot = { .min = 25000, .max = 350000 },
153 .vco = { .min = 908000, .max = 1512000 },
154 .n = { .min = 2, .max = 16 },
155 .m = { .min = 96, .max = 140 },
156 .m1 = { .min = 18, .max = 26 },
157 .m2 = { .min = 6, .max = 16 },
158 .p = { .min = 4, .max = 128 },
159 .p1 = { .min = 2, .max = 33 },
160 .p2 = { .dot_limit = 165000,
161 .p2_slow = 4, .p2_fast = 4 },
162 };
163
164 static const intel_limit_t intel_limits_i8xx_lvds = {
165 .dot = { .min = 25000, .max = 350000 },
166 .vco = { .min = 908000, .max = 1512000 },
167 .n = { .min = 2, .max = 16 },
168 .m = { .min = 96, .max = 140 },
169 .m1 = { .min = 18, .max = 26 },
170 .m2 = { .min = 6, .max = 16 },
171 .p = { .min = 4, .max = 128 },
172 .p1 = { .min = 1, .max = 6 },
173 .p2 = { .dot_limit = 165000,
174 .p2_slow = 14, .p2_fast = 7 },
175 };
176
177 static const intel_limit_t intel_limits_i9xx_sdvo = {
178 .dot = { .min = 20000, .max = 400000 },
179 .vco = { .min = 1400000, .max = 2800000 },
180 .n = { .min = 1, .max = 6 },
181 .m = { .min = 70, .max = 120 },
182 .m1 = { .min = 8, .max = 18 },
183 .m2 = { .min = 3, .max = 7 },
184 .p = { .min = 5, .max = 80 },
185 .p1 = { .min = 1, .max = 8 },
186 .p2 = { .dot_limit = 200000,
187 .p2_slow = 10, .p2_fast = 5 },
188 };
189
190 static const intel_limit_t intel_limits_i9xx_lvds = {
191 .dot = { .min = 20000, .max = 400000 },
192 .vco = { .min = 1400000, .max = 2800000 },
193 .n = { .min = 1, .max = 6 },
194 .m = { .min = 70, .max = 120 },
195 .m1 = { .min = 8, .max = 18 },
196 .m2 = { .min = 3, .max = 7 },
197 .p = { .min = 7, .max = 98 },
198 .p1 = { .min = 1, .max = 8 },
199 .p2 = { .dot_limit = 112000,
200 .p2_slow = 14, .p2_fast = 7 },
201 };
202
203
204 static const intel_limit_t intel_limits_g4x_sdvo = {
205 .dot = { .min = 25000, .max = 270000 },
206 .vco = { .min = 1750000, .max = 3500000},
207 .n = { .min = 1, .max = 4 },
208 .m = { .min = 104, .max = 138 },
209 .m1 = { .min = 17, .max = 23 },
210 .m2 = { .min = 5, .max = 11 },
211 .p = { .min = 10, .max = 30 },
212 .p1 = { .min = 1, .max = 3},
213 .p2 = { .dot_limit = 270000,
214 .p2_slow = 10,
215 .p2_fast = 10
216 },
217 };
218
219 static const intel_limit_t intel_limits_g4x_hdmi = {
220 .dot = { .min = 22000, .max = 400000 },
221 .vco = { .min = 1750000, .max = 3500000},
222 .n = { .min = 1, .max = 4 },
223 .m = { .min = 104, .max = 138 },
224 .m1 = { .min = 16, .max = 23 },
225 .m2 = { .min = 5, .max = 11 },
226 .p = { .min = 5, .max = 80 },
227 .p1 = { .min = 1, .max = 8},
228 .p2 = { .dot_limit = 165000,
229 .p2_slow = 10, .p2_fast = 5 },
230 };
231
232 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
233 .dot = { .min = 20000, .max = 115000 },
234 .vco = { .min = 1750000, .max = 3500000 },
235 .n = { .min = 1, .max = 3 },
236 .m = { .min = 104, .max = 138 },
237 .m1 = { .min = 17, .max = 23 },
238 .m2 = { .min = 5, .max = 11 },
239 .p = { .min = 28, .max = 112 },
240 .p1 = { .min = 2, .max = 8 },
241 .p2 = { .dot_limit = 0,
242 .p2_slow = 14, .p2_fast = 14
243 },
244 };
245
246 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
247 .dot = { .min = 80000, .max = 224000 },
248 .vco = { .min = 1750000, .max = 3500000 },
249 .n = { .min = 1, .max = 3 },
250 .m = { .min = 104, .max = 138 },
251 .m1 = { .min = 17, .max = 23 },
252 .m2 = { .min = 5, .max = 11 },
253 .p = { .min = 14, .max = 42 },
254 .p1 = { .min = 2, .max = 6 },
255 .p2 = { .dot_limit = 0,
256 .p2_slow = 7, .p2_fast = 7
257 },
258 };
259
260 static const intel_limit_t intel_limits_pineview_sdvo = {
261 .dot = { .min = 20000, .max = 400000},
262 .vco = { .min = 1700000, .max = 3500000 },
263 /* Pineview's Ncounter is a ring counter */
264 .n = { .min = 3, .max = 6 },
265 .m = { .min = 2, .max = 256 },
266 /* Pineview only has one combined m divider, which we treat as m2. */
267 .m1 = { .min = 0, .max = 0 },
268 .m2 = { .min = 0, .max = 254 },
269 .p = { .min = 5, .max = 80 },
270 .p1 = { .min = 1, .max = 8 },
271 .p2 = { .dot_limit = 200000,
272 .p2_slow = 10, .p2_fast = 5 },
273 };
274
275 static const intel_limit_t intel_limits_pineview_lvds = {
276 .dot = { .min = 20000, .max = 400000 },
277 .vco = { .min = 1700000, .max = 3500000 },
278 .n = { .min = 3, .max = 6 },
279 .m = { .min = 2, .max = 256 },
280 .m1 = { .min = 0, .max = 0 },
281 .m2 = { .min = 0, .max = 254 },
282 .p = { .min = 7, .max = 112 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 112000,
285 .p2_slow = 14, .p2_fast = 14 },
286 };
287
288 /* Ironlake / Sandybridge
289 *
290 * We calculate clock using (register_value + 2) for N/M1/M2, so here
291 * the range value for them is (actual_value - 2).
292 */
293 static const intel_limit_t intel_limits_ironlake_dac = {
294 .dot = { .min = 25000, .max = 350000 },
295 .vco = { .min = 1760000, .max = 3510000 },
296 .n = { .min = 1, .max = 5 },
297 .m = { .min = 79, .max = 127 },
298 .m1 = { .min = 12, .max = 22 },
299 .m2 = { .min = 5, .max = 9 },
300 .p = { .min = 5, .max = 80 },
301 .p1 = { .min = 1, .max = 8 },
302 .p2 = { .dot_limit = 225000,
303 .p2_slow = 10, .p2_fast = 5 },
304 };
305
306 static const intel_limit_t intel_limits_ironlake_single_lvds = {
307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 118 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 28, .max = 112 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 14, .p2_fast = 14 },
317 };
318
319 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
320 .dot = { .min = 25000, .max = 350000 },
321 .vco = { .min = 1760000, .max = 3510000 },
322 .n = { .min = 1, .max = 3 },
323 .m = { .min = 79, .max = 127 },
324 .m1 = { .min = 12, .max = 22 },
325 .m2 = { .min = 5, .max = 9 },
326 .p = { .min = 14, .max = 56 },
327 .p1 = { .min = 2, .max = 8 },
328 .p2 = { .dot_limit = 225000,
329 .p2_slow = 7, .p2_fast = 7 },
330 };
331
332 /* LVDS 100mhz refclk limits. */
333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
341 .p1 = { .min = 2, .max = 8 },
342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
344 };
345
346 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
347 .dot = { .min = 25000, .max = 350000 },
348 .vco = { .min = 1760000, .max = 3510000 },
349 .n = { .min = 1, .max = 3 },
350 .m = { .min = 79, .max = 126 },
351 .m1 = { .min = 12, .max = 22 },
352 .m2 = { .min = 5, .max = 9 },
353 .p = { .min = 14, .max = 42 },
354 .p1 = { .min = 2, .max = 6 },
355 .p2 = { .dot_limit = 225000,
356 .p2_slow = 7, .p2_fast = 7 },
357 };
358
359 static const intel_limit_t intel_limits_vlv = {
360 /*
361 * These are the data rate limits (measured in fast clocks)
362 * since those are the strictest limits we have. The fast
363 * clock and actual rate limits are more relaxed, so checking
364 * them would make no difference.
365 */
366 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
367 .vco = { .min = 4000000, .max = 6000000 },
368 .n = { .min = 1, .max = 7 },
369 .m1 = { .min = 2, .max = 3 },
370 .m2 = { .min = 11, .max = 156 },
371 .p1 = { .min = 2, .max = 3 },
372 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
373 };
374
375 static const intel_limit_t intel_limits_chv = {
376 /*
377 * These are the data rate limits (measured in fast clocks)
378 * since those are the strictest limits we have. The fast
379 * clock and actual rate limits are more relaxed, so checking
380 * them would make no difference.
381 */
382 .dot = { .min = 25000 * 5, .max = 540000 * 5},
383 .vco = { .min = 4860000, .max = 6700000 },
384 .n = { .min = 1, .max = 1 },
385 .m1 = { .min = 2, .max = 2 },
386 .m2 = { .min = 24 << 22, .max = 175 << 22 },
387 .p1 = { .min = 2, .max = 4 },
388 .p2 = { .p2_slow = 1, .p2_fast = 14 },
389 };
390
391 static void vlv_clock(int refclk, intel_clock_t *clock)
392 {
393 clock->m = clock->m1 * clock->m2;
394 clock->p = clock->p1 * clock->p2;
395 if (WARN_ON(clock->n == 0 || clock->p == 0))
396 return;
397 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
398 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
399 }
400
401 /**
402 * Returns whether any output on the specified pipe is of the specified type
403 */
404 static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
405 {
406 struct drm_device *dev = crtc->dev;
407 struct intel_encoder *encoder;
408
409 for_each_encoder_on_crtc(dev, crtc, encoder)
410 if (encoder->type == type)
411 return true;
412
413 return false;
414 }
415
416 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
417 int refclk)
418 {
419 struct drm_device *dev = crtc->dev;
420 const intel_limit_t *limit;
421
422 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
423 if (intel_is_dual_link_lvds(dev)) {
424 if (refclk == 100000)
425 limit = &intel_limits_ironlake_dual_lvds_100m;
426 else
427 limit = &intel_limits_ironlake_dual_lvds;
428 } else {
429 if (refclk == 100000)
430 limit = &intel_limits_ironlake_single_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_single_lvds;
433 }
434 } else
435 limit = &intel_limits_ironlake_dac;
436
437 return limit;
438 }
439
440 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
441 {
442 struct drm_device *dev = crtc->dev;
443 const intel_limit_t *limit;
444
445 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
446 if (intel_is_dual_link_lvds(dev))
447 limit = &intel_limits_g4x_dual_channel_lvds;
448 else
449 limit = &intel_limits_g4x_single_channel_lvds;
450 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
451 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
452 limit = &intel_limits_g4x_hdmi;
453 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
454 limit = &intel_limits_g4x_sdvo;
455 } else /* The option is for other outputs */
456 limit = &intel_limits_i9xx_sdvo;
457
458 return limit;
459 }
460
461 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
462 {
463 struct drm_device *dev = crtc->dev;
464 const intel_limit_t *limit;
465
466 if (HAS_PCH_SPLIT(dev))
467 limit = intel_ironlake_limit(crtc, refclk);
468 else if (IS_G4X(dev)) {
469 limit = intel_g4x_limit(crtc);
470 } else if (IS_PINEVIEW(dev)) {
471 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
472 limit = &intel_limits_pineview_lvds;
473 else
474 limit = &intel_limits_pineview_sdvo;
475 } else if (IS_CHERRYVIEW(dev)) {
476 limit = &intel_limits_chv;
477 } else if (IS_VALLEYVIEW(dev)) {
478 limit = &intel_limits_vlv;
479 } else if (!IS_GEN2(dev)) {
480 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
481 limit = &intel_limits_i9xx_lvds;
482 else
483 limit = &intel_limits_i9xx_sdvo;
484 } else {
485 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
486 limit = &intel_limits_i8xx_lvds;
487 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
488 limit = &intel_limits_i8xx_dvo;
489 else
490 limit = &intel_limits_i8xx_dac;
491 }
492 return limit;
493 }
494
495 /* m1 is reserved as 0 in Pineview, n is a ring counter */
496 static void pineview_clock(int refclk, intel_clock_t *clock)
497 {
498 clock->m = clock->m2 + 2;
499 clock->p = clock->p1 * clock->p2;
500 if (WARN_ON(clock->n == 0 || clock->p == 0))
501 return;
502 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
503 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
504 }
505
506 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
507 {
508 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
509 }
510
511 static void i9xx_clock(int refclk, intel_clock_t *clock)
512 {
513 clock->m = i9xx_dpll_compute_m(clock);
514 clock->p = clock->p1 * clock->p2;
515 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
516 return;
517 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
518 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
519 }
520
521 static void chv_clock(int refclk, intel_clock_t *clock)
522 {
523 clock->m = clock->m1 * clock->m2;
524 clock->p = clock->p1 * clock->p2;
525 if (WARN_ON(clock->n == 0 || clock->p == 0))
526 return;
527 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
528 clock->n << 22);
529 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
530 }
531
532 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
533 /**
534 * Returns whether the given set of divisors are valid for a given refclk with
535 * the given connectors.
536 */
537
538 static bool intel_PLL_is_valid(struct drm_device *dev,
539 const intel_limit_t *limit,
540 const intel_clock_t *clock)
541 {
542 if (clock->n < limit->n.min || limit->n.max < clock->n)
543 INTELPllInvalid("n out of range\n");
544 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
545 INTELPllInvalid("p1 out of range\n");
546 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
547 INTELPllInvalid("m2 out of range\n");
548 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
549 INTELPllInvalid("m1 out of range\n");
550
551 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
552 if (clock->m1 <= clock->m2)
553 INTELPllInvalid("m1 <= m2\n");
554
555 if (!IS_VALLEYVIEW(dev)) {
556 if (clock->p < limit->p.min || limit->p.max < clock->p)
557 INTELPllInvalid("p out of range\n");
558 if (clock->m < limit->m.min || limit->m.max < clock->m)
559 INTELPllInvalid("m out of range\n");
560 }
561
562 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
563 INTELPllInvalid("vco out of range\n");
564 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
565 * connector, etc., rather than just a single range.
566 */
567 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
568 INTELPllInvalid("dot out of range\n");
569
570 return true;
571 }
572
573 static bool
574 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
575 int target, int refclk, intel_clock_t *match_clock,
576 intel_clock_t *best_clock)
577 {
578 struct drm_device *dev = crtc->dev;
579 intel_clock_t clock;
580 int err = target;
581
582 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
583 /*
584 * For LVDS just rely on its current settings for dual-channel.
585 * We haven't figured out how to reliably set up different
586 * single/dual channel state, if we even can.
587 */
588 if (intel_is_dual_link_lvds(dev))
589 clock.p2 = limit->p2.p2_fast;
590 else
591 clock.p2 = limit->p2.p2_slow;
592 } else {
593 if (target < limit->p2.dot_limit)
594 clock.p2 = limit->p2.p2_slow;
595 else
596 clock.p2 = limit->p2.p2_fast;
597 }
598
599 memset(best_clock, 0, sizeof(*best_clock));
600
601 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
602 clock.m1++) {
603 for (clock.m2 = limit->m2.min;
604 clock.m2 <= limit->m2.max; clock.m2++) {
605 if (clock.m2 >= clock.m1)
606 break;
607 for (clock.n = limit->n.min;
608 clock.n <= limit->n.max; clock.n++) {
609 for (clock.p1 = limit->p1.min;
610 clock.p1 <= limit->p1.max; clock.p1++) {
611 int this_err;
612
613 i9xx_clock(refclk, &clock);
614 if (!intel_PLL_is_valid(dev, limit,
615 &clock))
616 continue;
617 if (match_clock &&
618 clock.p != match_clock->p)
619 continue;
620
621 this_err = abs(clock.dot - target);
622 if (this_err < err) {
623 *best_clock = clock;
624 err = this_err;
625 }
626 }
627 }
628 }
629 }
630
631 return (err != target);
632 }
633
634 static bool
635 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
636 int target, int refclk, intel_clock_t *match_clock,
637 intel_clock_t *best_clock)
638 {
639 struct drm_device *dev = crtc->dev;
640 intel_clock_t clock;
641 int err = target;
642
643 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
644 /*
645 * For LVDS just rely on its current settings for dual-channel.
646 * We haven't figured out how to reliably set up different
647 * single/dual channel state, if we even can.
648 */
649 if (intel_is_dual_link_lvds(dev))
650 clock.p2 = limit->p2.p2_fast;
651 else
652 clock.p2 = limit->p2.p2_slow;
653 } else {
654 if (target < limit->p2.dot_limit)
655 clock.p2 = limit->p2.p2_slow;
656 else
657 clock.p2 = limit->p2.p2_fast;
658 }
659
660 memset(best_clock, 0, sizeof(*best_clock));
661
662 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
663 clock.m1++) {
664 for (clock.m2 = limit->m2.min;
665 clock.m2 <= limit->m2.max; clock.m2++) {
666 for (clock.n = limit->n.min;
667 clock.n <= limit->n.max; clock.n++) {
668 for (clock.p1 = limit->p1.min;
669 clock.p1 <= limit->p1.max; clock.p1++) {
670 int this_err;
671
672 pineview_clock(refclk, &clock);
673 if (!intel_PLL_is_valid(dev, limit,
674 &clock))
675 continue;
676 if (match_clock &&
677 clock.p != match_clock->p)
678 continue;
679
680 this_err = abs(clock.dot - target);
681 if (this_err < err) {
682 *best_clock = clock;
683 err = this_err;
684 }
685 }
686 }
687 }
688 }
689
690 return (err != target);
691 }
692
693 static bool
694 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
695 int target, int refclk, intel_clock_t *match_clock,
696 intel_clock_t *best_clock)
697 {
698 struct drm_device *dev = crtc->dev;
699 intel_clock_t clock;
700 int max_n;
701 bool found;
702 /* approximately equals target * 0.00585 */
703 int err_most = (target >> 8) + (target >> 9);
704 found = false;
705
706 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
707 if (intel_is_dual_link_lvds(dev))
708 clock.p2 = limit->p2.p2_fast;
709 else
710 clock.p2 = limit->p2.p2_slow;
711 } else {
712 if (target < limit->p2.dot_limit)
713 clock.p2 = limit->p2.p2_slow;
714 else
715 clock.p2 = limit->p2.p2_fast;
716 }
717
718 memset(best_clock, 0, sizeof(*best_clock));
719 max_n = limit->n.max;
720 /* based on hardware requirement, prefer smaller n to precision */
721 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
722 /* based on hardware requirement, prefere larger m1,m2 */
723 for (clock.m1 = limit->m1.max;
724 clock.m1 >= limit->m1.min; clock.m1--) {
725 for (clock.m2 = limit->m2.max;
726 clock.m2 >= limit->m2.min; clock.m2--) {
727 for (clock.p1 = limit->p1.max;
728 clock.p1 >= limit->p1.min; clock.p1--) {
729 int this_err;
730
731 i9xx_clock(refclk, &clock);
732 if (!intel_PLL_is_valid(dev, limit,
733 &clock))
734 continue;
735
736 this_err = abs(clock.dot - target);
737 if (this_err < err_most) {
738 *best_clock = clock;
739 err_most = this_err;
740 max_n = clock.n;
741 found = true;
742 }
743 }
744 }
745 }
746 }
747 return found;
748 }
749
750 static bool
751 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
752 int target, int refclk, intel_clock_t *match_clock,
753 intel_clock_t *best_clock)
754 {
755 struct drm_device *dev = crtc->dev;
756 intel_clock_t clock;
757 unsigned int bestppm = 1000000;
758 /* min update 19.2 MHz */
759 int max_n = min(limit->n.max, refclk / 19200);
760 bool found = false;
761
762 target *= 5; /* fast clock */
763
764 memset(best_clock, 0, sizeof(*best_clock));
765
766 /* based on hardware requirement, prefer smaller n to precision */
767 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
768 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
769 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
770 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
771 clock.p = clock.p1 * clock.p2;
772 /* based on hardware requirement, prefer bigger m1,m2 values */
773 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
774 unsigned int ppm, diff;
775
776 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
777 refclk * clock.m1);
778
779 vlv_clock(refclk, &clock);
780
781 if (!intel_PLL_is_valid(dev, limit,
782 &clock))
783 continue;
784
785 diff = abs(clock.dot - target);
786 ppm = div_u64(1000000ULL * diff, target);
787
788 if (ppm < 100 && clock.p > best_clock->p) {
789 bestppm = 0;
790 *best_clock = clock;
791 found = true;
792 }
793
794 if (bestppm >= 10 && ppm < bestppm - 10) {
795 bestppm = ppm;
796 *best_clock = clock;
797 found = true;
798 }
799 }
800 }
801 }
802 }
803
804 return found;
805 }
806
807 static bool
808 chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811 {
812 struct drm_device *dev = crtc->dev;
813 intel_clock_t clock;
814 uint64_t m2;
815 int found = false;
816
817 memset(best_clock, 0, sizeof(*best_clock));
818
819 /*
820 * Based on hardware doc, the n always set to 1, and m1 always
821 * set to 2. If requires to support 200Mhz refclk, we need to
822 * revisit this because n may not 1 anymore.
823 */
824 clock.n = 1, clock.m1 = 2;
825 target *= 5; /* fast clock */
826
827 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
828 for (clock.p2 = limit->p2.p2_fast;
829 clock.p2 >= limit->p2.p2_slow;
830 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
831
832 clock.p = clock.p1 * clock.p2;
833
834 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
835 clock.n) << 22, refclk * clock.m1);
836
837 if (m2 > INT_MAX/clock.m1)
838 continue;
839
840 clock.m2 = m2;
841
842 chv_clock(refclk, &clock);
843
844 if (!intel_PLL_is_valid(dev, limit, &clock))
845 continue;
846
847 /* based on hardware requirement, prefer bigger p
848 */
849 if (clock.p > best_clock->p) {
850 *best_clock = clock;
851 found = true;
852 }
853 }
854 }
855
856 return found;
857 }
858
859 bool intel_crtc_active(struct drm_crtc *crtc)
860 {
861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
862
863 /* Be paranoid as we can arrive here with only partial
864 * state retrieved from the hardware during setup.
865 *
866 * We can ditch the adjusted_mode.crtc_clock check as soon
867 * as Haswell has gained clock readout/fastboot support.
868 *
869 * We can ditch the crtc->primary->fb check as soon as we can
870 * properly reconstruct framebuffers.
871 */
872 return intel_crtc->active && crtc->primary->fb &&
873 intel_crtc->config.adjusted_mode.crtc_clock;
874 }
875
876 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878 {
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->config.cpu_transcoder;
883 }
884
885 static void g4x_wait_for_vblank(struct drm_device *dev, int pipe)
886 {
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 WARN(1, "vblank wait timed out\n");
894 }
895
896 /**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
905 {
906 struct drm_i915_private *dev_priv = dev->dev_private;
907 int pipestat_reg = PIPESTAT(pipe);
908
909 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
910 g4x_wait_for_vblank(dev, pipe);
911 return;
912 }
913
914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
930 /* Wait for vblank interrupt bit to set */
931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
934 DRM_DEBUG_KMS("vblank wait timed out\n");
935 }
936
937 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
938 {
939 struct drm_i915_private *dev_priv = dev->dev_private;
940 u32 reg = PIPEDSL(pipe);
941 u32 line1, line2;
942 u32 line_mask;
943
944 if (IS_GEN2(dev))
945 line_mask = DSL_LINEMASK_GEN2;
946 else
947 line_mask = DSL_LINEMASK_GEN3;
948
949 line1 = I915_READ(reg) & line_mask;
950 mdelay(5);
951 line2 = I915_READ(reg) & line_mask;
952
953 return line1 == line2;
954 }
955
956 /*
957 * intel_wait_for_pipe_off - wait for pipe to turn off
958 * @dev: drm device
959 * @pipe: pipe to wait for
960 *
961 * After disabling a pipe, we can't wait for vblank in the usual way,
962 * spinning on the vblank interrupt status bit, since we won't actually
963 * see an interrupt when the pipe is disabled.
964 *
965 * On Gen4 and above:
966 * wait for the pipe register state bit to turn off
967 *
968 * Otherwise:
969 * wait for the display line value to settle (it usually
970 * ends up stopping at the start of the next frame).
971 *
972 */
973 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
974 {
975 struct drm_i915_private *dev_priv = dev->dev_private;
976 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
977 pipe);
978
979 if (INTEL_INFO(dev)->gen >= 4) {
980 int reg = PIPECONF(cpu_transcoder);
981
982 /* Wait for the Pipe State to go off */
983 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
984 100))
985 WARN(1, "pipe_off wait timed out\n");
986 } else {
987 /* Wait for the display line to settle */
988 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
989 WARN(1, "pipe_off wait timed out\n");
990 }
991 }
992
993 /*
994 * ibx_digital_port_connected - is the specified port connected?
995 * @dev_priv: i915 private structure
996 * @port: the port to test
997 *
998 * Returns true if @port is connected, false otherwise.
999 */
1000 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1001 struct intel_digital_port *port)
1002 {
1003 u32 bit;
1004
1005 if (HAS_PCH_IBX(dev_priv->dev)) {
1006 switch (port->port) {
1007 case PORT_B:
1008 bit = SDE_PORTB_HOTPLUG;
1009 break;
1010 case PORT_C:
1011 bit = SDE_PORTC_HOTPLUG;
1012 break;
1013 case PORT_D:
1014 bit = SDE_PORTD_HOTPLUG;
1015 break;
1016 default:
1017 return true;
1018 }
1019 } else {
1020 switch (port->port) {
1021 case PORT_B:
1022 bit = SDE_PORTB_HOTPLUG_CPT;
1023 break;
1024 case PORT_C:
1025 bit = SDE_PORTC_HOTPLUG_CPT;
1026 break;
1027 case PORT_D:
1028 bit = SDE_PORTD_HOTPLUG_CPT;
1029 break;
1030 default:
1031 return true;
1032 }
1033 }
1034
1035 return I915_READ(SDEISR) & bit;
1036 }
1037
1038 static const char *state_string(bool enabled)
1039 {
1040 return enabled ? "on" : "off";
1041 }
1042
1043 /* Only for pre-ILK configs */
1044 void assert_pll(struct drm_i915_private *dev_priv,
1045 enum pipe pipe, bool state)
1046 {
1047 int reg;
1048 u32 val;
1049 bool cur_state;
1050
1051 reg = DPLL(pipe);
1052 val = I915_READ(reg);
1053 cur_state = !!(val & DPLL_VCO_ENABLE);
1054 WARN(cur_state != state,
1055 "PLL state assertion failure (expected %s, current %s)\n",
1056 state_string(state), state_string(cur_state));
1057 }
1058
1059 /* XXX: the dsi pll is shared between MIPI DSI ports */
1060 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1061 {
1062 u32 val;
1063 bool cur_state;
1064
1065 mutex_lock(&dev_priv->dpio_lock);
1066 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1067 mutex_unlock(&dev_priv->dpio_lock);
1068
1069 cur_state = val & DSI_PLL_VCO_EN;
1070 WARN(cur_state != state,
1071 "DSI PLL state assertion failure (expected %s, current %s)\n",
1072 state_string(state), state_string(cur_state));
1073 }
1074 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1075 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1076
1077 struct intel_shared_dpll *
1078 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1079 {
1080 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1081
1082 if (crtc->config.shared_dpll < 0)
1083 return NULL;
1084
1085 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
1086 }
1087
1088 /* For ILK+ */
1089 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1090 struct intel_shared_dpll *pll,
1091 bool state)
1092 {
1093 bool cur_state;
1094 struct intel_dpll_hw_state hw_state;
1095
1096 if (HAS_PCH_LPT(dev_priv->dev)) {
1097 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1098 return;
1099 }
1100
1101 if (WARN (!pll,
1102 "asserting DPLL %s with no DPLL\n", state_string(state)))
1103 return;
1104
1105 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1106 WARN(cur_state != state,
1107 "%s assertion failure (expected %s, current %s)\n",
1108 pll->name, state_string(state), state_string(cur_state));
1109 }
1110
1111 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1112 enum pipe pipe, bool state)
1113 {
1114 int reg;
1115 u32 val;
1116 bool cur_state;
1117 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1118 pipe);
1119
1120 if (HAS_DDI(dev_priv->dev)) {
1121 /* DDI does not have a specific FDI_TX register */
1122 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1123 val = I915_READ(reg);
1124 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1125 } else {
1126 reg = FDI_TX_CTL(pipe);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & FDI_TX_ENABLE);
1129 }
1130 WARN(cur_state != state,
1131 "FDI TX state assertion failure (expected %s, current %s)\n",
1132 state_string(state), state_string(cur_state));
1133 }
1134 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1135 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1136
1137 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1138 enum pipe pipe, bool state)
1139 {
1140 int reg;
1141 u32 val;
1142 bool cur_state;
1143
1144 reg = FDI_RX_CTL(pipe);
1145 val = I915_READ(reg);
1146 cur_state = !!(val & FDI_RX_ENABLE);
1147 WARN(cur_state != state,
1148 "FDI RX state assertion failure (expected %s, current %s)\n",
1149 state_string(state), state_string(cur_state));
1150 }
1151 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1152 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1153
1154 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156 {
1157 int reg;
1158 u32 val;
1159
1160 /* ILK FDI PLL is always enabled */
1161 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1162 return;
1163
1164 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1165 if (HAS_DDI(dev_priv->dev))
1166 return;
1167
1168 reg = FDI_TX_CTL(pipe);
1169 val = I915_READ(reg);
1170 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1171 }
1172
1173 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1174 enum pipe pipe, bool state)
1175 {
1176 int reg;
1177 u32 val;
1178 bool cur_state;
1179
1180 reg = FDI_RX_CTL(pipe);
1181 val = I915_READ(reg);
1182 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1183 WARN(cur_state != state,
1184 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1185 state_string(state), state_string(cur_state));
1186 }
1187
1188 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1189 enum pipe pipe)
1190 {
1191 int pp_reg, lvds_reg;
1192 u32 val;
1193 enum pipe panel_pipe = PIPE_A;
1194 bool locked = true;
1195
1196 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1197 pp_reg = PCH_PP_CONTROL;
1198 lvds_reg = PCH_LVDS;
1199 } else {
1200 pp_reg = PP_CONTROL;
1201 lvds_reg = LVDS;
1202 }
1203
1204 val = I915_READ(pp_reg);
1205 if (!(val & PANEL_POWER_ON) ||
1206 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1207 locked = false;
1208
1209 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1210 panel_pipe = PIPE_B;
1211
1212 WARN(panel_pipe == pipe && locked,
1213 "panel assertion failure, pipe %c regs locked\n",
1214 pipe_name(pipe));
1215 }
1216
1217 static void assert_cursor(struct drm_i915_private *dev_priv,
1218 enum pipe pipe, bool state)
1219 {
1220 struct drm_device *dev = dev_priv->dev;
1221 bool cur_state;
1222
1223 if (IS_845G(dev) || IS_I865G(dev))
1224 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1225 else
1226 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1227
1228 WARN(cur_state != state,
1229 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1230 pipe_name(pipe), state_string(state), state_string(cur_state));
1231 }
1232 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1233 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1234
1235 void assert_pipe(struct drm_i915_private *dev_priv,
1236 enum pipe pipe, bool state)
1237 {
1238 int reg;
1239 u32 val;
1240 bool cur_state;
1241 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1242 pipe);
1243
1244 /* if we need the pipe A quirk it must be always on */
1245 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1246 state = true;
1247
1248 if (!intel_display_power_enabled(dev_priv,
1249 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1250 cur_state = false;
1251 } else {
1252 reg = PIPECONF(cpu_transcoder);
1253 val = I915_READ(reg);
1254 cur_state = !!(val & PIPECONF_ENABLE);
1255 }
1256
1257 WARN(cur_state != state,
1258 "pipe %c assertion failure (expected %s, current %s)\n",
1259 pipe_name(pipe), state_string(state), state_string(cur_state));
1260 }
1261
1262 static void assert_plane(struct drm_i915_private *dev_priv,
1263 enum plane plane, bool state)
1264 {
1265 int reg;
1266 u32 val;
1267 bool cur_state;
1268
1269 reg = DSPCNTR(plane);
1270 val = I915_READ(reg);
1271 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1272 WARN(cur_state != state,
1273 "plane %c assertion failure (expected %s, current %s)\n",
1274 plane_name(plane), state_string(state), state_string(cur_state));
1275 }
1276
1277 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1278 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1279
1280 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1281 enum pipe pipe)
1282 {
1283 struct drm_device *dev = dev_priv->dev;
1284 int reg, i;
1285 u32 val;
1286 int cur_pipe;
1287
1288 /* Primary planes are fixed to pipes on gen4+ */
1289 if (INTEL_INFO(dev)->gen >= 4) {
1290 reg = DSPCNTR(pipe);
1291 val = I915_READ(reg);
1292 WARN(val & DISPLAY_PLANE_ENABLE,
1293 "plane %c assertion failure, should be disabled but not\n",
1294 plane_name(pipe));
1295 return;
1296 }
1297
1298 /* Need to check both planes against the pipe */
1299 for_each_pipe(i) {
1300 reg = DSPCNTR(i);
1301 val = I915_READ(reg);
1302 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1303 DISPPLANE_SEL_PIPE_SHIFT;
1304 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1305 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1306 plane_name(i), pipe_name(pipe));
1307 }
1308 }
1309
1310 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1311 enum pipe pipe)
1312 {
1313 struct drm_device *dev = dev_priv->dev;
1314 int reg, sprite;
1315 u32 val;
1316
1317 if (IS_VALLEYVIEW(dev)) {
1318 for_each_sprite(pipe, sprite) {
1319 reg = SPCNTR(pipe, sprite);
1320 val = I915_READ(reg);
1321 WARN(val & SP_ENABLE,
1322 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1323 sprite_name(pipe, sprite), pipe_name(pipe));
1324 }
1325 } else if (INTEL_INFO(dev)->gen >= 7) {
1326 reg = SPRCTL(pipe);
1327 val = I915_READ(reg);
1328 WARN(val & SPRITE_ENABLE,
1329 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1330 plane_name(pipe), pipe_name(pipe));
1331 } else if (INTEL_INFO(dev)->gen >= 5) {
1332 reg = DVSCNTR(pipe);
1333 val = I915_READ(reg);
1334 WARN(val & DVS_ENABLE,
1335 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1336 plane_name(pipe), pipe_name(pipe));
1337 }
1338 }
1339
1340 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1341 {
1342 u32 val;
1343 bool enabled;
1344
1345 WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1346
1347 val = I915_READ(PCH_DREF_CONTROL);
1348 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1349 DREF_SUPERSPREAD_SOURCE_MASK));
1350 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1351 }
1352
1353 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1354 enum pipe pipe)
1355 {
1356 int reg;
1357 u32 val;
1358 bool enabled;
1359
1360 reg = PCH_TRANSCONF(pipe);
1361 val = I915_READ(reg);
1362 enabled = !!(val & TRANS_ENABLE);
1363 WARN(enabled,
1364 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1365 pipe_name(pipe));
1366 }
1367
1368 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1369 enum pipe pipe, u32 port_sel, u32 val)
1370 {
1371 if ((val & DP_PORT_EN) == 0)
1372 return false;
1373
1374 if (HAS_PCH_CPT(dev_priv->dev)) {
1375 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1376 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1377 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1378 return false;
1379 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1380 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1381 return false;
1382 } else {
1383 if ((val & DP_PIPE_MASK) != (pipe << 30))
1384 return false;
1385 }
1386 return true;
1387 }
1388
1389 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1390 enum pipe pipe, u32 val)
1391 {
1392 if ((val & SDVO_ENABLE) == 0)
1393 return false;
1394
1395 if (HAS_PCH_CPT(dev_priv->dev)) {
1396 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1397 return false;
1398 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1399 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1400 return false;
1401 } else {
1402 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1403 return false;
1404 }
1405 return true;
1406 }
1407
1408 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1409 enum pipe pipe, u32 val)
1410 {
1411 if ((val & LVDS_PORT_EN) == 0)
1412 return false;
1413
1414 if (HAS_PCH_CPT(dev_priv->dev)) {
1415 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1416 return false;
1417 } else {
1418 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1419 return false;
1420 }
1421 return true;
1422 }
1423
1424 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1425 enum pipe pipe, u32 val)
1426 {
1427 if ((val & ADPA_DAC_ENABLE) == 0)
1428 return false;
1429 if (HAS_PCH_CPT(dev_priv->dev)) {
1430 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1431 return false;
1432 } else {
1433 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1434 return false;
1435 }
1436 return true;
1437 }
1438
1439 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1440 enum pipe pipe, int reg, u32 port_sel)
1441 {
1442 u32 val = I915_READ(reg);
1443 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1444 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1445 reg, pipe_name(pipe));
1446
1447 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1448 && (val & DP_PIPEB_SELECT),
1449 "IBX PCH dp port still using transcoder B\n");
1450 }
1451
1452 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1453 enum pipe pipe, int reg)
1454 {
1455 u32 val = I915_READ(reg);
1456 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1457 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1458 reg, pipe_name(pipe));
1459
1460 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1461 && (val & SDVO_PIPE_B_SELECT),
1462 "IBX PCH hdmi port still using transcoder B\n");
1463 }
1464
1465 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1466 enum pipe pipe)
1467 {
1468 int reg;
1469 u32 val;
1470
1471 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1472 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1473 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1474
1475 reg = PCH_ADPA;
1476 val = I915_READ(reg);
1477 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1478 "PCH VGA enabled on transcoder %c, should be disabled\n",
1479 pipe_name(pipe));
1480
1481 reg = PCH_LVDS;
1482 val = I915_READ(reg);
1483 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1484 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1485 pipe_name(pipe));
1486
1487 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1488 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1489 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1490 }
1491
1492 static void intel_init_dpio(struct drm_device *dev)
1493 {
1494 struct drm_i915_private *dev_priv = dev->dev_private;
1495
1496 if (!IS_VALLEYVIEW(dev))
1497 return;
1498
1499 /*
1500 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1501 * CHV x1 PHY (DP/HDMI D)
1502 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1503 */
1504 if (IS_CHERRYVIEW(dev)) {
1505 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1506 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1507 } else {
1508 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1509 }
1510 }
1511
1512 static void intel_reset_dpio(struct drm_device *dev)
1513 {
1514 struct drm_i915_private *dev_priv = dev->dev_private;
1515
1516 if (!IS_VALLEYVIEW(dev))
1517 return;
1518
1519 if (IS_CHERRYVIEW(dev)) {
1520 enum dpio_phy phy;
1521 u32 val;
1522
1523 for (phy = DPIO_PHY0; phy < I915_NUM_PHYS_VLV; phy++) {
1524 /* Poll for phypwrgood signal */
1525 if (wait_for(I915_READ(DISPLAY_PHY_STATUS) &
1526 PHY_POWERGOOD(phy), 1))
1527 DRM_ERROR("Display PHY %d is not power up\n", phy);
1528
1529 /*
1530 * Deassert common lane reset for PHY.
1531 *
1532 * This should only be done on init and resume from S3
1533 * with both PLLs disabled, or we risk losing DPIO and
1534 * PLL synchronization.
1535 */
1536 val = I915_READ(DISPLAY_PHY_CONTROL);
1537 I915_WRITE(DISPLAY_PHY_CONTROL,
1538 PHY_COM_LANE_RESET_DEASSERT(phy, val));
1539 }
1540
1541 } else {
1542 /*
1543 * If DPIO has already been reset, e.g. by BIOS, just skip all
1544 * this.
1545 */
1546 if (I915_READ(DPIO_CTL) & DPIO_CMNRST)
1547 return;
1548
1549 /*
1550 * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
1551 * Need to assert and de-assert PHY SB reset by gating the
1552 * common lane power, then un-gating it.
1553 * Simply ungating isn't enough to reset the PHY enough to get
1554 * ports and lanes running.
1555 */
1556 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1557 false);
1558 __vlv_set_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC,
1559 true);
1560 }
1561 }
1562
1563 static void vlv_enable_pll(struct intel_crtc *crtc)
1564 {
1565 struct drm_device *dev = crtc->base.dev;
1566 struct drm_i915_private *dev_priv = dev->dev_private;
1567 int reg = DPLL(crtc->pipe);
1568 u32 dpll = crtc->config.dpll_hw_state.dpll;
1569
1570 assert_pipe_disabled(dev_priv, crtc->pipe);
1571
1572 /* No really, not for ILK+ */
1573 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1574
1575 /* PLL is protected by panel, make sure we can write it */
1576 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1577 assert_panel_unlocked(dev_priv, crtc->pipe);
1578
1579 I915_WRITE(reg, dpll);
1580 POSTING_READ(reg);
1581 udelay(150);
1582
1583 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1584 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1585
1586 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1587 POSTING_READ(DPLL_MD(crtc->pipe));
1588
1589 /* We do this three times for luck */
1590 I915_WRITE(reg, dpll);
1591 POSTING_READ(reg);
1592 udelay(150); /* wait for warmup */
1593 I915_WRITE(reg, dpll);
1594 POSTING_READ(reg);
1595 udelay(150); /* wait for warmup */
1596 I915_WRITE(reg, dpll);
1597 POSTING_READ(reg);
1598 udelay(150); /* wait for warmup */
1599 }
1600
1601 static void chv_enable_pll(struct intel_crtc *crtc)
1602 {
1603 struct drm_device *dev = crtc->base.dev;
1604 struct drm_i915_private *dev_priv = dev->dev_private;
1605 int pipe = crtc->pipe;
1606 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1607 u32 tmp;
1608
1609 assert_pipe_disabled(dev_priv, crtc->pipe);
1610
1611 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1612
1613 mutex_lock(&dev_priv->dpio_lock);
1614
1615 /* Enable back the 10bit clock to display controller */
1616 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1617 tmp |= DPIO_DCLKP_EN;
1618 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1619
1620 /*
1621 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1622 */
1623 udelay(1);
1624
1625 /* Enable PLL */
1626 I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll);
1627
1628 /* Check PLL is locked */
1629 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("PLL %d failed to lock\n", pipe);
1631
1632 /* not sure when this should be written */
1633 I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md);
1634 POSTING_READ(DPLL_MD(pipe));
1635
1636 mutex_unlock(&dev_priv->dpio_lock);
1637 }
1638
1639 static void i9xx_enable_pll(struct intel_crtc *crtc)
1640 {
1641 struct drm_device *dev = crtc->base.dev;
1642 struct drm_i915_private *dev_priv = dev->dev_private;
1643 int reg = DPLL(crtc->pipe);
1644 u32 dpll = crtc->config.dpll_hw_state.dpll;
1645
1646 assert_pipe_disabled(dev_priv, crtc->pipe);
1647
1648 /* No really, not for ILK+ */
1649 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1650
1651 /* PLL is protected by panel, make sure we can write it */
1652 if (IS_MOBILE(dev) && !IS_I830(dev))
1653 assert_panel_unlocked(dev_priv, crtc->pipe);
1654
1655 I915_WRITE(reg, dpll);
1656
1657 /* Wait for the clocks to stabilize. */
1658 POSTING_READ(reg);
1659 udelay(150);
1660
1661 if (INTEL_INFO(dev)->gen >= 4) {
1662 I915_WRITE(DPLL_MD(crtc->pipe),
1663 crtc->config.dpll_hw_state.dpll_md);
1664 } else {
1665 /* The pixel multiplier can only be updated once the
1666 * DPLL is enabled and the clocks are stable.
1667 *
1668 * So write it again.
1669 */
1670 I915_WRITE(reg, dpll);
1671 }
1672
1673 /* We do this three times for luck */
1674 I915_WRITE(reg, dpll);
1675 POSTING_READ(reg);
1676 udelay(150); /* wait for warmup */
1677 I915_WRITE(reg, dpll);
1678 POSTING_READ(reg);
1679 udelay(150); /* wait for warmup */
1680 I915_WRITE(reg, dpll);
1681 POSTING_READ(reg);
1682 udelay(150); /* wait for warmup */
1683 }
1684
1685 /**
1686 * i9xx_disable_pll - disable a PLL
1687 * @dev_priv: i915 private structure
1688 * @pipe: pipe PLL to disable
1689 *
1690 * Disable the PLL for @pipe, making sure the pipe is off first.
1691 *
1692 * Note! This is for pre-ILK only.
1693 */
1694 static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1695 {
1696 /* Don't disable pipe A or pipe A PLLs if needed */
1697 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1698 return;
1699
1700 /* Make sure the pipe isn't still relying on us */
1701 assert_pipe_disabled(dev_priv, pipe);
1702
1703 I915_WRITE(DPLL(pipe), 0);
1704 POSTING_READ(DPLL(pipe));
1705 }
1706
1707 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1708 {
1709 u32 val = 0;
1710
1711 /* Make sure the pipe isn't still relying on us */
1712 assert_pipe_disabled(dev_priv, pipe);
1713
1714 /*
1715 * Leave integrated clock source and reference clock enabled for pipe B.
1716 * The latter is needed for VGA hotplug / manual detection.
1717 */
1718 if (pipe == PIPE_B)
1719 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
1720 I915_WRITE(DPLL(pipe), val);
1721 POSTING_READ(DPLL(pipe));
1722
1723 }
1724
1725 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1726 {
1727 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1728 u32 val;
1729
1730 /* Make sure the pipe isn't still relying on us */
1731 assert_pipe_disabled(dev_priv, pipe);
1732
1733 /* Set PLL en = 0 */
1734 val = DPLL_SSC_REF_CLOCK_CHV;
1735 if (pipe != PIPE_A)
1736 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1737 I915_WRITE(DPLL(pipe), val);
1738 POSTING_READ(DPLL(pipe));
1739
1740 mutex_lock(&dev_priv->dpio_lock);
1741
1742 /* Disable 10bit clock to display controller */
1743 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1744 val &= ~DPIO_DCLKP_EN;
1745 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1746
1747 /* disable left/right clock distribution */
1748 if (pipe != PIPE_B) {
1749 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1750 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1751 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1752 } else {
1753 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1754 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1755 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1756 }
1757
1758 mutex_unlock(&dev_priv->dpio_lock);
1759 }
1760
1761 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1762 struct intel_digital_port *dport)
1763 {
1764 u32 port_mask;
1765 int dpll_reg;
1766
1767 switch (dport->port) {
1768 case PORT_B:
1769 port_mask = DPLL_PORTB_READY_MASK;
1770 dpll_reg = DPLL(0);
1771 break;
1772 case PORT_C:
1773 port_mask = DPLL_PORTC_READY_MASK;
1774 dpll_reg = DPLL(0);
1775 break;
1776 case PORT_D:
1777 port_mask = DPLL_PORTD_READY_MASK;
1778 dpll_reg = DPIO_PHY_STATUS;
1779 break;
1780 default:
1781 BUG();
1782 }
1783
1784 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
1785 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1786 port_name(dport->port), I915_READ(dpll_reg));
1787 }
1788
1789 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1790 {
1791 struct drm_device *dev = crtc->base.dev;
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1793 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1794
1795 if (WARN_ON(pll == NULL))
1796 return;
1797
1798 WARN_ON(!pll->refcount);
1799 if (pll->active == 0) {
1800 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1801 WARN_ON(pll->on);
1802 assert_shared_dpll_disabled(dev_priv, pll);
1803
1804 pll->mode_set(dev_priv, pll);
1805 }
1806 }
1807
1808 /**
1809 * intel_enable_shared_dpll - enable PCH PLL
1810 * @dev_priv: i915 private structure
1811 * @pipe: pipe PLL to enable
1812 *
1813 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1814 * drives the transcoder clock.
1815 */
1816 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1817 {
1818 struct drm_device *dev = crtc->base.dev;
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1820 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1821
1822 if (WARN_ON(pll == NULL))
1823 return;
1824
1825 if (WARN_ON(pll->refcount == 0))
1826 return;
1827
1828 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1829 pll->name, pll->active, pll->on,
1830 crtc->base.base.id);
1831
1832 if (pll->active++) {
1833 WARN_ON(!pll->on);
1834 assert_shared_dpll_enabled(dev_priv, pll);
1835 return;
1836 }
1837 WARN_ON(pll->on);
1838
1839 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1840 pll->enable(dev_priv, pll);
1841 pll->on = true;
1842 }
1843
1844 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1845 {
1846 struct drm_device *dev = crtc->base.dev;
1847 struct drm_i915_private *dev_priv = dev->dev_private;
1848 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1849
1850 /* PCH only available on ILK+ */
1851 BUG_ON(INTEL_INFO(dev)->gen < 5);
1852 if (WARN_ON(pll == NULL))
1853 return;
1854
1855 if (WARN_ON(pll->refcount == 0))
1856 return;
1857
1858 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1859 pll->name, pll->active, pll->on,
1860 crtc->base.base.id);
1861
1862 if (WARN_ON(pll->active == 0)) {
1863 assert_shared_dpll_disabled(dev_priv, pll);
1864 return;
1865 }
1866
1867 assert_shared_dpll_enabled(dev_priv, pll);
1868 WARN_ON(!pll->on);
1869 if (--pll->active)
1870 return;
1871
1872 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1873 pll->disable(dev_priv, pll);
1874 pll->on = false;
1875 }
1876
1877 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1878 enum pipe pipe)
1879 {
1880 struct drm_device *dev = dev_priv->dev;
1881 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1882 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1883 uint32_t reg, val, pipeconf_val;
1884
1885 /* PCH only available on ILK+ */
1886 BUG_ON(INTEL_INFO(dev)->gen < 5);
1887
1888 /* Make sure PCH DPLL is enabled */
1889 assert_shared_dpll_enabled(dev_priv,
1890 intel_crtc_to_shared_dpll(intel_crtc));
1891
1892 /* FDI must be feeding us bits for PCH ports */
1893 assert_fdi_tx_enabled(dev_priv, pipe);
1894 assert_fdi_rx_enabled(dev_priv, pipe);
1895
1896 if (HAS_PCH_CPT(dev)) {
1897 /* Workaround: Set the timing override bit before enabling the
1898 * pch transcoder. */
1899 reg = TRANS_CHICKEN2(pipe);
1900 val = I915_READ(reg);
1901 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1902 I915_WRITE(reg, val);
1903 }
1904
1905 reg = PCH_TRANSCONF(pipe);
1906 val = I915_READ(reg);
1907 pipeconf_val = I915_READ(PIPECONF(pipe));
1908
1909 if (HAS_PCH_IBX(dev_priv->dev)) {
1910 /*
1911 * make the BPC in transcoder be consistent with
1912 * that in pipeconf reg.
1913 */
1914 val &= ~PIPECONF_BPC_MASK;
1915 val |= pipeconf_val & PIPECONF_BPC_MASK;
1916 }
1917
1918 val &= ~TRANS_INTERLACE_MASK;
1919 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1920 if (HAS_PCH_IBX(dev_priv->dev) &&
1921 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1922 val |= TRANS_LEGACY_INTERLACED_ILK;
1923 else
1924 val |= TRANS_INTERLACED;
1925 else
1926 val |= TRANS_PROGRESSIVE;
1927
1928 I915_WRITE(reg, val | TRANS_ENABLE);
1929 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1930 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1931 }
1932
1933 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1934 enum transcoder cpu_transcoder)
1935 {
1936 u32 val, pipeconf_val;
1937
1938 /* PCH only available on ILK+ */
1939 BUG_ON(INTEL_INFO(dev_priv->dev)->gen < 5);
1940
1941 /* FDI must be feeding us bits for PCH ports */
1942 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
1943 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1944
1945 /* Workaround: set timing override bit. */
1946 val = I915_READ(_TRANSA_CHICKEN2);
1947 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1948 I915_WRITE(_TRANSA_CHICKEN2, val);
1949
1950 val = TRANS_ENABLE;
1951 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1952
1953 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1954 PIPECONF_INTERLACED_ILK)
1955 val |= TRANS_INTERLACED;
1956 else
1957 val |= TRANS_PROGRESSIVE;
1958
1959 I915_WRITE(LPT_TRANSCONF, val);
1960 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1961 DRM_ERROR("Failed to enable PCH transcoder\n");
1962 }
1963
1964 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1965 enum pipe pipe)
1966 {
1967 struct drm_device *dev = dev_priv->dev;
1968 uint32_t reg, val;
1969
1970 /* FDI relies on the transcoder */
1971 assert_fdi_tx_disabled(dev_priv, pipe);
1972 assert_fdi_rx_disabled(dev_priv, pipe);
1973
1974 /* Ports must be off as well */
1975 assert_pch_ports_disabled(dev_priv, pipe);
1976
1977 reg = PCH_TRANSCONF(pipe);
1978 val = I915_READ(reg);
1979 val &= ~TRANS_ENABLE;
1980 I915_WRITE(reg, val);
1981 /* wait for PCH transcoder off, transcoder state */
1982 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1983 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1984
1985 if (!HAS_PCH_IBX(dev)) {
1986 /* Workaround: Clear the timing override chicken bit again. */
1987 reg = TRANS_CHICKEN2(pipe);
1988 val = I915_READ(reg);
1989 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1990 I915_WRITE(reg, val);
1991 }
1992 }
1993
1994 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1995 {
1996 u32 val;
1997
1998 val = I915_READ(LPT_TRANSCONF);
1999 val &= ~TRANS_ENABLE;
2000 I915_WRITE(LPT_TRANSCONF, val);
2001 /* wait for PCH transcoder off, transcoder state */
2002 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2003 DRM_ERROR("Failed to disable PCH transcoder\n");
2004
2005 /* Workaround: clear timing override bit. */
2006 val = I915_READ(_TRANSA_CHICKEN2);
2007 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2008 I915_WRITE(_TRANSA_CHICKEN2, val);
2009 }
2010
2011 /**
2012 * intel_enable_pipe - enable a pipe, asserting requirements
2013 * @crtc: crtc responsible for the pipe
2014 *
2015 * Enable @crtc's pipe, making sure that various hardware specific requirements
2016 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2017 */
2018 static void intel_enable_pipe(struct intel_crtc *crtc)
2019 {
2020 struct drm_device *dev = crtc->base.dev;
2021 struct drm_i915_private *dev_priv = dev->dev_private;
2022 enum pipe pipe = crtc->pipe;
2023 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2024 pipe);
2025 enum pipe pch_transcoder;
2026 int reg;
2027 u32 val;
2028
2029 assert_planes_disabled(dev_priv, pipe);
2030 assert_cursor_disabled(dev_priv, pipe);
2031 assert_sprites_disabled(dev_priv, pipe);
2032
2033 if (HAS_PCH_LPT(dev_priv->dev))
2034 pch_transcoder = TRANSCODER_A;
2035 else
2036 pch_transcoder = pipe;
2037
2038 /*
2039 * A pipe without a PLL won't actually be able to drive bits from
2040 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2041 * need the check.
2042 */
2043 if (!HAS_PCH_SPLIT(dev_priv->dev))
2044 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI))
2045 assert_dsi_pll_enabled(dev_priv);
2046 else
2047 assert_pll_enabled(dev_priv, pipe);
2048 else {
2049 if (crtc->config.has_pch_encoder) {
2050 /* if driving the PCH, we need FDI enabled */
2051 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2052 assert_fdi_tx_pll_enabled(dev_priv,
2053 (enum pipe) cpu_transcoder);
2054 }
2055 /* FIXME: assert CPU port conditions for SNB+ */
2056 }
2057
2058 reg = PIPECONF(cpu_transcoder);
2059 val = I915_READ(reg);
2060 if (val & PIPECONF_ENABLE) {
2061 WARN_ON(!(pipe == PIPE_A &&
2062 dev_priv->quirks & QUIRK_PIPEA_FORCE));
2063 return;
2064 }
2065
2066 I915_WRITE(reg, val | PIPECONF_ENABLE);
2067 POSTING_READ(reg);
2068 }
2069
2070 /**
2071 * intel_disable_pipe - disable a pipe, asserting requirements
2072 * @dev_priv: i915 private structure
2073 * @pipe: pipe to disable
2074 *
2075 * Disable @pipe, making sure that various hardware specific requirements
2076 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
2077 *
2078 * @pipe should be %PIPE_A or %PIPE_B.
2079 *
2080 * Will wait until the pipe has shut down before returning.
2081 */
2082 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
2083 enum pipe pipe)
2084 {
2085 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2086 pipe);
2087 int reg;
2088 u32 val;
2089
2090 /*
2091 * Make sure planes won't keep trying to pump pixels to us,
2092 * or we might hang the display.
2093 */
2094 assert_planes_disabled(dev_priv, pipe);
2095 assert_cursor_disabled(dev_priv, pipe);
2096 assert_sprites_disabled(dev_priv, pipe);
2097
2098 /* Don't disable pipe A or pipe A PLLs if needed */
2099 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2100 return;
2101
2102 reg = PIPECONF(cpu_transcoder);
2103 val = I915_READ(reg);
2104 if ((val & PIPECONF_ENABLE) == 0)
2105 return;
2106
2107 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
2108 intel_wait_for_pipe_off(dev_priv->dev, pipe);
2109 }
2110
2111 /*
2112 * Plane regs are double buffered, going from enabled->disabled needs a
2113 * trigger in order to latch. The display address reg provides this.
2114 */
2115 void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2116 enum plane plane)
2117 {
2118 struct drm_device *dev = dev_priv->dev;
2119 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
2120
2121 I915_WRITE(reg, I915_READ(reg));
2122 POSTING_READ(reg);
2123 }
2124
2125 /**
2126 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
2127 * @dev_priv: i915 private structure
2128 * @plane: plane to enable
2129 * @pipe: pipe being fed
2130 *
2131 * Enable @plane on @pipe, making sure that @pipe is running first.
2132 */
2133 static void intel_enable_primary_hw_plane(struct drm_i915_private *dev_priv,
2134 enum plane plane, enum pipe pipe)
2135 {
2136 struct intel_crtc *intel_crtc =
2137 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2138 int reg;
2139 u32 val;
2140
2141 /* If the pipe isn't enabled, we can't pump pixels and may hang */
2142 assert_pipe_enabled(dev_priv, pipe);
2143
2144 if (intel_crtc->primary_enabled)
2145 return;
2146
2147 intel_crtc->primary_enabled = true;
2148
2149 reg = DSPCNTR(plane);
2150 val = I915_READ(reg);
2151 WARN_ON(val & DISPLAY_PLANE_ENABLE);
2152
2153 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
2154 intel_flush_primary_plane(dev_priv, plane);
2155 }
2156
2157 /**
2158 * intel_disable_primary_hw_plane - disable the primary hardware plane
2159 * @dev_priv: i915 private structure
2160 * @plane: plane to disable
2161 * @pipe: pipe consuming the data
2162 *
2163 * Disable @plane; should be an independent operation.
2164 */
2165 static void intel_disable_primary_hw_plane(struct drm_i915_private *dev_priv,
2166 enum plane plane, enum pipe pipe)
2167 {
2168 struct intel_crtc *intel_crtc =
2169 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
2170 int reg;
2171 u32 val;
2172
2173 if (!intel_crtc->primary_enabled)
2174 return;
2175
2176 intel_crtc->primary_enabled = false;
2177
2178 reg = DSPCNTR(plane);
2179 val = I915_READ(reg);
2180 WARN_ON((val & DISPLAY_PLANE_ENABLE) == 0);
2181
2182 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
2183 intel_flush_primary_plane(dev_priv, plane);
2184 }
2185
2186 static bool need_vtd_wa(struct drm_device *dev)
2187 {
2188 #ifdef CONFIG_INTEL_IOMMU
2189 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2190 return true;
2191 #endif
2192 return false;
2193 }
2194
2195 static int intel_align_height(struct drm_device *dev, int height, bool tiled)
2196 {
2197 int tile_height;
2198
2199 tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1;
2200 return ALIGN(height, tile_height);
2201 }
2202
2203 int
2204 intel_pin_and_fence_fb_obj(struct drm_device *dev,
2205 struct drm_i915_gem_object *obj,
2206 struct intel_engine_cs *pipelined)
2207 {
2208 struct drm_i915_private *dev_priv = dev->dev_private;
2209 u32 alignment;
2210 int ret;
2211
2212 switch (obj->tiling_mode) {
2213 case I915_TILING_NONE:
2214 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2215 alignment = 128 * 1024;
2216 else if (INTEL_INFO(dev)->gen >= 4)
2217 alignment = 4 * 1024;
2218 else
2219 alignment = 64 * 1024;
2220 break;
2221 case I915_TILING_X:
2222 /* pin() will align the object as required by fence */
2223 alignment = 0;
2224 break;
2225 case I915_TILING_Y:
2226 WARN(1, "Y tiled bo slipped through, driver bug!\n");
2227 return -EINVAL;
2228 default:
2229 BUG();
2230 }
2231
2232 /* Note that the w/a also requires 64 PTE of padding following the
2233 * bo. We currently fill all unused PTE with the shadow page and so
2234 * we should always have valid PTE following the scanout preventing
2235 * the VT-d warning.
2236 */
2237 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2238 alignment = 256 * 1024;
2239
2240 dev_priv->mm.interruptible = false;
2241 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
2242 if (ret)
2243 goto err_interruptible;
2244
2245 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2246 * fence, whereas 965+ only requires a fence if using
2247 * framebuffer compression. For simplicity, we always install
2248 * a fence as the cost is not that onerous.
2249 */
2250 ret = i915_gem_object_get_fence(obj);
2251 if (ret)
2252 goto err_unpin;
2253
2254 i915_gem_object_pin_fence(obj);
2255
2256 dev_priv->mm.interruptible = true;
2257 return 0;
2258
2259 err_unpin:
2260 i915_gem_object_unpin_from_display_plane(obj);
2261 err_interruptible:
2262 dev_priv->mm.interruptible = true;
2263 return ret;
2264 }
2265
2266 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2267 {
2268 i915_gem_object_unpin_fence(obj);
2269 i915_gem_object_unpin_from_display_plane(obj);
2270 }
2271
2272 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2273 * is assumed to be a power-of-two. */
2274 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2275 unsigned int tiling_mode,
2276 unsigned int cpp,
2277 unsigned int pitch)
2278 {
2279 if (tiling_mode != I915_TILING_NONE) {
2280 unsigned int tile_rows, tiles;
2281
2282 tile_rows = *y / 8;
2283 *y %= 8;
2284
2285 tiles = *x / (512/cpp);
2286 *x %= 512/cpp;
2287
2288 return tile_rows * pitch * 8 + tiles * 4096;
2289 } else {
2290 unsigned int offset;
2291
2292 offset = *y * pitch + *x * cpp;
2293 *y = 0;
2294 *x = (offset & 4095) / cpp;
2295 return offset & -4096;
2296 }
2297 }
2298
2299 int intel_format_to_fourcc(int format)
2300 {
2301 switch (format) {
2302 case DISPPLANE_8BPP:
2303 return DRM_FORMAT_C8;
2304 case DISPPLANE_BGRX555:
2305 return DRM_FORMAT_XRGB1555;
2306 case DISPPLANE_BGRX565:
2307 return DRM_FORMAT_RGB565;
2308 default:
2309 case DISPPLANE_BGRX888:
2310 return DRM_FORMAT_XRGB8888;
2311 case DISPPLANE_RGBX888:
2312 return DRM_FORMAT_XBGR8888;
2313 case DISPPLANE_BGRX101010:
2314 return DRM_FORMAT_XRGB2101010;
2315 case DISPPLANE_RGBX101010:
2316 return DRM_FORMAT_XBGR2101010;
2317 }
2318 }
2319
2320 static bool intel_alloc_plane_obj(struct intel_crtc *crtc,
2321 struct intel_plane_config *plane_config)
2322 {
2323 struct drm_device *dev = crtc->base.dev;
2324 struct drm_i915_gem_object *obj = NULL;
2325 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2326 u32 base = plane_config->base;
2327
2328 if (plane_config->size == 0)
2329 return false;
2330
2331 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base,
2332 plane_config->size);
2333 if (!obj)
2334 return false;
2335
2336 if (plane_config->tiled) {
2337 obj->tiling_mode = I915_TILING_X;
2338 obj->stride = crtc->base.primary->fb->pitches[0];
2339 }
2340
2341 mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format;
2342 mode_cmd.width = crtc->base.primary->fb->width;
2343 mode_cmd.height = crtc->base.primary->fb->height;
2344 mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0];
2345
2346 mutex_lock(&dev->struct_mutex);
2347
2348 if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb),
2349 &mode_cmd, obj)) {
2350 DRM_DEBUG_KMS("intel fb init failed\n");
2351 goto out_unref_obj;
2352 }
2353
2354 mutex_unlock(&dev->struct_mutex);
2355
2356 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2357 return true;
2358
2359 out_unref_obj:
2360 drm_gem_object_unreference(&obj->base);
2361 mutex_unlock(&dev->struct_mutex);
2362 return false;
2363 }
2364
2365 static void intel_find_plane_obj(struct intel_crtc *intel_crtc,
2366 struct intel_plane_config *plane_config)
2367 {
2368 struct drm_device *dev = intel_crtc->base.dev;
2369 struct drm_crtc *c;
2370 struct intel_crtc *i;
2371 struct intel_framebuffer *fb;
2372
2373 if (!intel_crtc->base.primary->fb)
2374 return;
2375
2376 if (intel_alloc_plane_obj(intel_crtc, plane_config))
2377 return;
2378
2379 kfree(intel_crtc->base.primary->fb);
2380 intel_crtc->base.primary->fb = NULL;
2381
2382 /*
2383 * Failed to alloc the obj, check to see if we should share
2384 * an fb with another CRTC instead
2385 */
2386 for_each_crtc(dev, c) {
2387 i = to_intel_crtc(c);
2388
2389 if (c == &intel_crtc->base)
2390 continue;
2391
2392 if (!i->active || !c->primary->fb)
2393 continue;
2394
2395 fb = to_intel_framebuffer(c->primary->fb);
2396 if (i915_gem_obj_ggtt_offset(fb->obj) == plane_config->base) {
2397 drm_framebuffer_reference(c->primary->fb);
2398 intel_crtc->base.primary->fb = c->primary->fb;
2399 break;
2400 }
2401 }
2402 }
2403
2404 static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2405 struct drm_framebuffer *fb,
2406 int x, int y)
2407 {
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 struct intel_framebuffer *intel_fb;
2412 struct drm_i915_gem_object *obj;
2413 int plane = intel_crtc->plane;
2414 unsigned long linear_offset;
2415 u32 dspcntr;
2416 u32 reg;
2417
2418 intel_fb = to_intel_framebuffer(fb);
2419 obj = intel_fb->obj;
2420
2421 reg = DSPCNTR(plane);
2422 dspcntr = I915_READ(reg);
2423 /* Mask out pixel format bits in case we change it */
2424 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2425 switch (fb->pixel_format) {
2426 case DRM_FORMAT_C8:
2427 dspcntr |= DISPPLANE_8BPP;
2428 break;
2429 case DRM_FORMAT_XRGB1555:
2430 case DRM_FORMAT_ARGB1555:
2431 dspcntr |= DISPPLANE_BGRX555;
2432 break;
2433 case DRM_FORMAT_RGB565:
2434 dspcntr |= DISPPLANE_BGRX565;
2435 break;
2436 case DRM_FORMAT_XRGB8888:
2437 case DRM_FORMAT_ARGB8888:
2438 dspcntr |= DISPPLANE_BGRX888;
2439 break;
2440 case DRM_FORMAT_XBGR8888:
2441 case DRM_FORMAT_ABGR8888:
2442 dspcntr |= DISPPLANE_RGBX888;
2443 break;
2444 case DRM_FORMAT_XRGB2101010:
2445 case DRM_FORMAT_ARGB2101010:
2446 dspcntr |= DISPPLANE_BGRX101010;
2447 break;
2448 case DRM_FORMAT_XBGR2101010:
2449 case DRM_FORMAT_ABGR2101010:
2450 dspcntr |= DISPPLANE_RGBX101010;
2451 break;
2452 default:
2453 BUG();
2454 }
2455
2456 if (INTEL_INFO(dev)->gen >= 4) {
2457 if (obj->tiling_mode != I915_TILING_NONE)
2458 dspcntr |= DISPPLANE_TILED;
2459 else
2460 dspcntr &= ~DISPPLANE_TILED;
2461 }
2462
2463 if (IS_G4X(dev))
2464 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2465
2466 I915_WRITE(reg, dspcntr);
2467
2468 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2469
2470 if (INTEL_INFO(dev)->gen >= 4) {
2471 intel_crtc->dspaddr_offset =
2472 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2473 fb->bits_per_pixel / 8,
2474 fb->pitches[0]);
2475 linear_offset -= intel_crtc->dspaddr_offset;
2476 } else {
2477 intel_crtc->dspaddr_offset = linear_offset;
2478 }
2479
2480 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2481 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2482 fb->pitches[0]);
2483 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2484 if (INTEL_INFO(dev)->gen >= 4) {
2485 I915_WRITE(DSPSURF(plane),
2486 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2487 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2488 I915_WRITE(DSPLINOFF(plane), linear_offset);
2489 } else
2490 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2491 POSTING_READ(reg);
2492 }
2493
2494 static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2495 struct drm_framebuffer *fb,
2496 int x, int y)
2497 {
2498 struct drm_device *dev = crtc->dev;
2499 struct drm_i915_private *dev_priv = dev->dev_private;
2500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2501 struct intel_framebuffer *intel_fb;
2502 struct drm_i915_gem_object *obj;
2503 int plane = intel_crtc->plane;
2504 unsigned long linear_offset;
2505 u32 dspcntr;
2506 u32 reg;
2507
2508 intel_fb = to_intel_framebuffer(fb);
2509 obj = intel_fb->obj;
2510
2511 reg = DSPCNTR(plane);
2512 dspcntr = I915_READ(reg);
2513 /* Mask out pixel format bits in case we change it */
2514 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2515 switch (fb->pixel_format) {
2516 case DRM_FORMAT_C8:
2517 dspcntr |= DISPPLANE_8BPP;
2518 break;
2519 case DRM_FORMAT_RGB565:
2520 dspcntr |= DISPPLANE_BGRX565;
2521 break;
2522 case DRM_FORMAT_XRGB8888:
2523 case DRM_FORMAT_ARGB8888:
2524 dspcntr |= DISPPLANE_BGRX888;
2525 break;
2526 case DRM_FORMAT_XBGR8888:
2527 case DRM_FORMAT_ABGR8888:
2528 dspcntr |= DISPPLANE_RGBX888;
2529 break;
2530 case DRM_FORMAT_XRGB2101010:
2531 case DRM_FORMAT_ARGB2101010:
2532 dspcntr |= DISPPLANE_BGRX101010;
2533 break;
2534 case DRM_FORMAT_XBGR2101010:
2535 case DRM_FORMAT_ABGR2101010:
2536 dspcntr |= DISPPLANE_RGBX101010;
2537 break;
2538 default:
2539 BUG();
2540 }
2541
2542 if (obj->tiling_mode != I915_TILING_NONE)
2543 dspcntr |= DISPPLANE_TILED;
2544 else
2545 dspcntr &= ~DISPPLANE_TILED;
2546
2547 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2548 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2549 else
2550 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2551
2552 I915_WRITE(reg, dspcntr);
2553
2554 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2555 intel_crtc->dspaddr_offset =
2556 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2557 fb->bits_per_pixel / 8,
2558 fb->pitches[0]);
2559 linear_offset -= intel_crtc->dspaddr_offset;
2560
2561 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2562 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2563 fb->pitches[0]);
2564 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2565 I915_WRITE(DSPSURF(plane),
2566 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2567 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2568 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2569 } else {
2570 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2571 I915_WRITE(DSPLINOFF(plane), linear_offset);
2572 }
2573 POSTING_READ(reg);
2574 }
2575
2576 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2577 static int
2578 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2579 int x, int y, enum mode_set_atomic state)
2580 {
2581 struct drm_device *dev = crtc->dev;
2582 struct drm_i915_private *dev_priv = dev->dev_private;
2583
2584 if (dev_priv->display.disable_fbc)
2585 dev_priv->display.disable_fbc(dev);
2586 intel_increase_pllclock(crtc);
2587
2588 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2589
2590 return 0;
2591 }
2592
2593 void intel_display_handle_reset(struct drm_device *dev)
2594 {
2595 struct drm_i915_private *dev_priv = dev->dev_private;
2596 struct drm_crtc *crtc;
2597
2598 /*
2599 * Flips in the rings have been nuked by the reset,
2600 * so complete all pending flips so that user space
2601 * will get its events and not get stuck.
2602 *
2603 * Also update the base address of all primary
2604 * planes to the the last fb to make sure we're
2605 * showing the correct fb after a reset.
2606 *
2607 * Need to make two loops over the crtcs so that we
2608 * don't try to grab a crtc mutex before the
2609 * pending_flip_queue really got woken up.
2610 */
2611
2612 for_each_crtc(dev, crtc) {
2613 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2614 enum plane plane = intel_crtc->plane;
2615
2616 intel_prepare_page_flip(dev, plane);
2617 intel_finish_page_flip_plane(dev, plane);
2618 }
2619
2620 for_each_crtc(dev, crtc) {
2621 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2622
2623 drm_modeset_lock(&crtc->mutex, NULL);
2624 /*
2625 * FIXME: Once we have proper support for primary planes (and
2626 * disabling them without disabling the entire crtc) allow again
2627 * a NULL crtc->primary->fb.
2628 */
2629 if (intel_crtc->active && crtc->primary->fb)
2630 dev_priv->display.update_primary_plane(crtc,
2631 crtc->primary->fb,
2632 crtc->x,
2633 crtc->y);
2634 drm_modeset_unlock(&crtc->mutex);
2635 }
2636 }
2637
2638 static int
2639 intel_finish_fb(struct drm_framebuffer *old_fb)
2640 {
2641 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2642 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2643 bool was_interruptible = dev_priv->mm.interruptible;
2644 int ret;
2645
2646 /* Big Hammer, we also need to ensure that any pending
2647 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2648 * current scanout is retired before unpinning the old
2649 * framebuffer.
2650 *
2651 * This should only fail upon a hung GPU, in which case we
2652 * can safely continue.
2653 */
2654 dev_priv->mm.interruptible = false;
2655 ret = i915_gem_object_finish_gpu(obj);
2656 dev_priv->mm.interruptible = was_interruptible;
2657
2658 return ret;
2659 }
2660
2661 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2662 {
2663 struct drm_device *dev = crtc->dev;
2664 struct drm_i915_private *dev_priv = dev->dev_private;
2665 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2666 unsigned long flags;
2667 bool pending;
2668
2669 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2670 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2671 return false;
2672
2673 spin_lock_irqsave(&dev->event_lock, flags);
2674 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2675 spin_unlock_irqrestore(&dev->event_lock, flags);
2676
2677 return pending;
2678 }
2679
2680 static int
2681 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2682 struct drm_framebuffer *fb)
2683 {
2684 struct drm_device *dev = crtc->dev;
2685 struct drm_i915_private *dev_priv = dev->dev_private;
2686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2687 struct drm_framebuffer *old_fb;
2688 int ret;
2689
2690 if (intel_crtc_has_pending_flip(crtc)) {
2691 DRM_ERROR("pipe is still busy with an old pageflip\n");
2692 return -EBUSY;
2693 }
2694
2695 /* no fb bound */
2696 if (!fb) {
2697 DRM_ERROR("No FB bound\n");
2698 return 0;
2699 }
2700
2701 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2702 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2703 plane_name(intel_crtc->plane),
2704 INTEL_INFO(dev)->num_pipes);
2705 return -EINVAL;
2706 }
2707
2708 mutex_lock(&dev->struct_mutex);
2709 ret = intel_pin_and_fence_fb_obj(dev,
2710 to_intel_framebuffer(fb)->obj,
2711 NULL);
2712 mutex_unlock(&dev->struct_mutex);
2713 if (ret != 0) {
2714 DRM_ERROR("pin & fence failed\n");
2715 return ret;
2716 }
2717
2718 /*
2719 * Update pipe size and adjust fitter if needed: the reason for this is
2720 * that in compute_mode_changes we check the native mode (not the pfit
2721 * mode) to see if we can flip rather than do a full mode set. In the
2722 * fastboot case, we'll flip, but if we don't update the pipesrc and
2723 * pfit state, we'll end up with a big fb scanned out into the wrong
2724 * sized surface.
2725 *
2726 * To fix this properly, we need to hoist the checks up into
2727 * compute_mode_changes (or above), check the actual pfit state and
2728 * whether the platform allows pfit disable with pipe active, and only
2729 * then update the pipesrc and pfit state, even on the flip path.
2730 */
2731 if (i915.fastboot) {
2732 const struct drm_display_mode *adjusted_mode =
2733 &intel_crtc->config.adjusted_mode;
2734
2735 I915_WRITE(PIPESRC(intel_crtc->pipe),
2736 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2737 (adjusted_mode->crtc_vdisplay - 1));
2738 if (!intel_crtc->config.pch_pfit.enabled &&
2739 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2740 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2741 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2742 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2743 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2744 }
2745 intel_crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay;
2746 intel_crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay;
2747 }
2748
2749 dev_priv->display.update_primary_plane(crtc, fb, x, y);
2750
2751 old_fb = crtc->primary->fb;
2752 crtc->primary->fb = fb;
2753 crtc->x = x;
2754 crtc->y = y;
2755
2756 if (old_fb) {
2757 if (intel_crtc->active && old_fb != fb)
2758 intel_wait_for_vblank(dev, intel_crtc->pipe);
2759 mutex_lock(&dev->struct_mutex);
2760 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2761 mutex_unlock(&dev->struct_mutex);
2762 }
2763
2764 mutex_lock(&dev->struct_mutex);
2765 intel_update_fbc(dev);
2766 intel_edp_psr_update(dev);
2767 mutex_unlock(&dev->struct_mutex);
2768
2769 return 0;
2770 }
2771
2772 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2773 {
2774 struct drm_device *dev = crtc->dev;
2775 struct drm_i915_private *dev_priv = dev->dev_private;
2776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2777 int pipe = intel_crtc->pipe;
2778 u32 reg, temp;
2779
2780 /* enable normal train */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if (IS_IVYBRIDGE(dev)) {
2784 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2785 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2786 } else {
2787 temp &= ~FDI_LINK_TRAIN_NONE;
2788 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2789 }
2790 I915_WRITE(reg, temp);
2791
2792 reg = FDI_RX_CTL(pipe);
2793 temp = I915_READ(reg);
2794 if (HAS_PCH_CPT(dev)) {
2795 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2796 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2797 } else {
2798 temp &= ~FDI_LINK_TRAIN_NONE;
2799 temp |= FDI_LINK_TRAIN_NONE;
2800 }
2801 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2802
2803 /* wait one idle pattern time */
2804 POSTING_READ(reg);
2805 udelay(1000);
2806
2807 /* IVB wants error correction enabled */
2808 if (IS_IVYBRIDGE(dev))
2809 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2810 FDI_FE_ERRC_ENABLE);
2811 }
2812
2813 static bool pipe_has_enabled_pch(struct intel_crtc *crtc)
2814 {
2815 return crtc->base.enabled && crtc->active &&
2816 crtc->config.has_pch_encoder;
2817 }
2818
2819 static void ivb_modeset_global_resources(struct drm_device *dev)
2820 {
2821 struct drm_i915_private *dev_priv = dev->dev_private;
2822 struct intel_crtc *pipe_B_crtc =
2823 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2824 struct intel_crtc *pipe_C_crtc =
2825 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2826 uint32_t temp;
2827
2828 /*
2829 * When everything is off disable fdi C so that we could enable fdi B
2830 * with all lanes. Note that we don't care about enabled pipes without
2831 * an enabled pch encoder.
2832 */
2833 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2834 !pipe_has_enabled_pch(pipe_C_crtc)) {
2835 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2836 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2837
2838 temp = I915_READ(SOUTH_CHICKEN1);
2839 temp &= ~FDI_BC_BIFURCATION_SELECT;
2840 DRM_DEBUG_KMS("disabling fdi C rx\n");
2841 I915_WRITE(SOUTH_CHICKEN1, temp);
2842 }
2843 }
2844
2845 /* The FDI link training functions for ILK/Ibexpeak. */
2846 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2847 {
2848 struct drm_device *dev = crtc->dev;
2849 struct drm_i915_private *dev_priv = dev->dev_private;
2850 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2851 int pipe = intel_crtc->pipe;
2852 u32 reg, temp, tries;
2853
2854 /* FDI needs bits from pipe first */
2855 assert_pipe_enabled(dev_priv, pipe);
2856
2857 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2858 for train result */
2859 reg = FDI_RX_IMR(pipe);
2860 temp = I915_READ(reg);
2861 temp &= ~FDI_RX_SYMBOL_LOCK;
2862 temp &= ~FDI_RX_BIT_LOCK;
2863 I915_WRITE(reg, temp);
2864 I915_READ(reg);
2865 udelay(150);
2866
2867 /* enable CPU FDI TX and PCH FDI RX */
2868 reg = FDI_TX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2871 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2872 temp &= ~FDI_LINK_TRAIN_NONE;
2873 temp |= FDI_LINK_TRAIN_PATTERN_1;
2874 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2875
2876 reg = FDI_RX_CTL(pipe);
2877 temp = I915_READ(reg);
2878 temp &= ~FDI_LINK_TRAIN_NONE;
2879 temp |= FDI_LINK_TRAIN_PATTERN_1;
2880 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2881
2882 POSTING_READ(reg);
2883 udelay(150);
2884
2885 /* Ironlake workaround, enable clock pointer after FDI enable*/
2886 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2887 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2888 FDI_RX_PHASE_SYNC_POINTER_EN);
2889
2890 reg = FDI_RX_IIR(pipe);
2891 for (tries = 0; tries < 5; tries++) {
2892 temp = I915_READ(reg);
2893 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2894
2895 if ((temp & FDI_RX_BIT_LOCK)) {
2896 DRM_DEBUG_KMS("FDI train 1 done.\n");
2897 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2898 break;
2899 }
2900 }
2901 if (tries == 5)
2902 DRM_ERROR("FDI train 1 fail!\n");
2903
2904 /* Train 2 */
2905 reg = FDI_TX_CTL(pipe);
2906 temp = I915_READ(reg);
2907 temp &= ~FDI_LINK_TRAIN_NONE;
2908 temp |= FDI_LINK_TRAIN_PATTERN_2;
2909 I915_WRITE(reg, temp);
2910
2911 reg = FDI_RX_CTL(pipe);
2912 temp = I915_READ(reg);
2913 temp &= ~FDI_LINK_TRAIN_NONE;
2914 temp |= FDI_LINK_TRAIN_PATTERN_2;
2915 I915_WRITE(reg, temp);
2916
2917 POSTING_READ(reg);
2918 udelay(150);
2919
2920 reg = FDI_RX_IIR(pipe);
2921 for (tries = 0; tries < 5; tries++) {
2922 temp = I915_READ(reg);
2923 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2924
2925 if (temp & FDI_RX_SYMBOL_LOCK) {
2926 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2927 DRM_DEBUG_KMS("FDI train 2 done.\n");
2928 break;
2929 }
2930 }
2931 if (tries == 5)
2932 DRM_ERROR("FDI train 2 fail!\n");
2933
2934 DRM_DEBUG_KMS("FDI train done\n");
2935
2936 }
2937
2938 static const int snb_b_fdi_train_param[] = {
2939 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2940 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2941 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2942 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2943 };
2944
2945 /* The FDI link training functions for SNB/Cougarpoint. */
2946 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2947 {
2948 struct drm_device *dev = crtc->dev;
2949 struct drm_i915_private *dev_priv = dev->dev_private;
2950 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2951 int pipe = intel_crtc->pipe;
2952 u32 reg, temp, i, retry;
2953
2954 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2955 for train result */
2956 reg = FDI_RX_IMR(pipe);
2957 temp = I915_READ(reg);
2958 temp &= ~FDI_RX_SYMBOL_LOCK;
2959 temp &= ~FDI_RX_BIT_LOCK;
2960 I915_WRITE(reg, temp);
2961
2962 POSTING_READ(reg);
2963 udelay(150);
2964
2965 /* enable CPU FDI TX and PCH FDI RX */
2966 reg = FDI_TX_CTL(pipe);
2967 temp = I915_READ(reg);
2968 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2969 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2970 temp &= ~FDI_LINK_TRAIN_NONE;
2971 temp |= FDI_LINK_TRAIN_PATTERN_1;
2972 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2973 /* SNB-B */
2974 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2975 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2976
2977 I915_WRITE(FDI_RX_MISC(pipe),
2978 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2979
2980 reg = FDI_RX_CTL(pipe);
2981 temp = I915_READ(reg);
2982 if (HAS_PCH_CPT(dev)) {
2983 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2984 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2985 } else {
2986 temp &= ~FDI_LINK_TRAIN_NONE;
2987 temp |= FDI_LINK_TRAIN_PATTERN_1;
2988 }
2989 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2990
2991 POSTING_READ(reg);
2992 udelay(150);
2993
2994 for (i = 0; i < 4; i++) {
2995 reg = FDI_TX_CTL(pipe);
2996 temp = I915_READ(reg);
2997 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2998 temp |= snb_b_fdi_train_param[i];
2999 I915_WRITE(reg, temp);
3000
3001 POSTING_READ(reg);
3002 udelay(500);
3003
3004 for (retry = 0; retry < 5; retry++) {
3005 reg = FDI_RX_IIR(pipe);
3006 temp = I915_READ(reg);
3007 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3008 if (temp & FDI_RX_BIT_LOCK) {
3009 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3010 DRM_DEBUG_KMS("FDI train 1 done.\n");
3011 break;
3012 }
3013 udelay(50);
3014 }
3015 if (retry < 5)
3016 break;
3017 }
3018 if (i == 4)
3019 DRM_ERROR("FDI train 1 fail!\n");
3020
3021 /* Train 2 */
3022 reg = FDI_TX_CTL(pipe);
3023 temp = I915_READ(reg);
3024 temp &= ~FDI_LINK_TRAIN_NONE;
3025 temp |= FDI_LINK_TRAIN_PATTERN_2;
3026 if (IS_GEN6(dev)) {
3027 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3028 /* SNB-B */
3029 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3030 }
3031 I915_WRITE(reg, temp);
3032
3033 reg = FDI_RX_CTL(pipe);
3034 temp = I915_READ(reg);
3035 if (HAS_PCH_CPT(dev)) {
3036 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3037 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3038 } else {
3039 temp &= ~FDI_LINK_TRAIN_NONE;
3040 temp |= FDI_LINK_TRAIN_PATTERN_2;
3041 }
3042 I915_WRITE(reg, temp);
3043
3044 POSTING_READ(reg);
3045 udelay(150);
3046
3047 for (i = 0; i < 4; i++) {
3048 reg = FDI_TX_CTL(pipe);
3049 temp = I915_READ(reg);
3050 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3051 temp |= snb_b_fdi_train_param[i];
3052 I915_WRITE(reg, temp);
3053
3054 POSTING_READ(reg);
3055 udelay(500);
3056
3057 for (retry = 0; retry < 5; retry++) {
3058 reg = FDI_RX_IIR(pipe);
3059 temp = I915_READ(reg);
3060 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3061 if (temp & FDI_RX_SYMBOL_LOCK) {
3062 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3063 DRM_DEBUG_KMS("FDI train 2 done.\n");
3064 break;
3065 }
3066 udelay(50);
3067 }
3068 if (retry < 5)
3069 break;
3070 }
3071 if (i == 4)
3072 DRM_ERROR("FDI train 2 fail!\n");
3073
3074 DRM_DEBUG_KMS("FDI train done.\n");
3075 }
3076
3077 /* Manual link training for Ivy Bridge A0 parts */
3078 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3079 {
3080 struct drm_device *dev = crtc->dev;
3081 struct drm_i915_private *dev_priv = dev->dev_private;
3082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3083 int pipe = intel_crtc->pipe;
3084 u32 reg, temp, i, j;
3085
3086 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3087 for train result */
3088 reg = FDI_RX_IMR(pipe);
3089 temp = I915_READ(reg);
3090 temp &= ~FDI_RX_SYMBOL_LOCK;
3091 temp &= ~FDI_RX_BIT_LOCK;
3092 I915_WRITE(reg, temp);
3093
3094 POSTING_READ(reg);
3095 udelay(150);
3096
3097 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3098 I915_READ(FDI_RX_IIR(pipe)));
3099
3100 /* Try each vswing and preemphasis setting twice before moving on */
3101 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3102 /* disable first in case we need to retry */
3103 reg = FDI_TX_CTL(pipe);
3104 temp = I915_READ(reg);
3105 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3106 temp &= ~FDI_TX_ENABLE;
3107 I915_WRITE(reg, temp);
3108
3109 reg = FDI_RX_CTL(pipe);
3110 temp = I915_READ(reg);
3111 temp &= ~FDI_LINK_TRAIN_AUTO;
3112 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3113 temp &= ~FDI_RX_ENABLE;
3114 I915_WRITE(reg, temp);
3115
3116 /* enable CPU FDI TX and PCH FDI RX */
3117 reg = FDI_TX_CTL(pipe);
3118 temp = I915_READ(reg);
3119 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3120 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3121 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3122 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3123 temp |= snb_b_fdi_train_param[j/2];
3124 temp |= FDI_COMPOSITE_SYNC;
3125 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3126
3127 I915_WRITE(FDI_RX_MISC(pipe),
3128 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3129
3130 reg = FDI_RX_CTL(pipe);
3131 temp = I915_READ(reg);
3132 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3133 temp |= FDI_COMPOSITE_SYNC;
3134 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3135
3136 POSTING_READ(reg);
3137 udelay(1); /* should be 0.5us */
3138
3139 for (i = 0; i < 4; i++) {
3140 reg = FDI_RX_IIR(pipe);
3141 temp = I915_READ(reg);
3142 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3143
3144 if (temp & FDI_RX_BIT_LOCK ||
3145 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3146 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3147 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3148 i);
3149 break;
3150 }
3151 udelay(1); /* should be 0.5us */
3152 }
3153 if (i == 4) {
3154 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3155 continue;
3156 }
3157
3158 /* Train 2 */
3159 reg = FDI_TX_CTL(pipe);
3160 temp = I915_READ(reg);
3161 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3162 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3163 I915_WRITE(reg, temp);
3164
3165 reg = FDI_RX_CTL(pipe);
3166 temp = I915_READ(reg);
3167 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3168 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3169 I915_WRITE(reg, temp);
3170
3171 POSTING_READ(reg);
3172 udelay(2); /* should be 1.5us */
3173
3174 for (i = 0; i < 4; i++) {
3175 reg = FDI_RX_IIR(pipe);
3176 temp = I915_READ(reg);
3177 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3178
3179 if (temp & FDI_RX_SYMBOL_LOCK ||
3180 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3181 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3182 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3183 i);
3184 goto train_done;
3185 }
3186 udelay(2); /* should be 1.5us */
3187 }
3188 if (i == 4)
3189 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3190 }
3191
3192 train_done:
3193 DRM_DEBUG_KMS("FDI train done.\n");
3194 }
3195
3196 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3197 {
3198 struct drm_device *dev = intel_crtc->base.dev;
3199 struct drm_i915_private *dev_priv = dev->dev_private;
3200 int pipe = intel_crtc->pipe;
3201 u32 reg, temp;
3202
3203
3204 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3205 reg = FDI_RX_CTL(pipe);
3206 temp = I915_READ(reg);
3207 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3208 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
3209 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3210 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3211
3212 POSTING_READ(reg);
3213 udelay(200);
3214
3215 /* Switch from Rawclk to PCDclk */
3216 temp = I915_READ(reg);
3217 I915_WRITE(reg, temp | FDI_PCDCLK);
3218
3219 POSTING_READ(reg);
3220 udelay(200);
3221
3222 /* Enable CPU FDI TX PLL, always on for Ironlake */
3223 reg = FDI_TX_CTL(pipe);
3224 temp = I915_READ(reg);
3225 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3226 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3227
3228 POSTING_READ(reg);
3229 udelay(100);
3230 }
3231 }
3232
3233 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3234 {
3235 struct drm_device *dev = intel_crtc->base.dev;
3236 struct drm_i915_private *dev_priv = dev->dev_private;
3237 int pipe = intel_crtc->pipe;
3238 u32 reg, temp;
3239
3240 /* Switch from PCDclk to Rawclk */
3241 reg = FDI_RX_CTL(pipe);
3242 temp = I915_READ(reg);
3243 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3244
3245 /* Disable CPU FDI TX PLL */
3246 reg = FDI_TX_CTL(pipe);
3247 temp = I915_READ(reg);
3248 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3249
3250 POSTING_READ(reg);
3251 udelay(100);
3252
3253 reg = FDI_RX_CTL(pipe);
3254 temp = I915_READ(reg);
3255 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3256
3257 /* Wait for the clocks to turn off. */
3258 POSTING_READ(reg);
3259 udelay(100);
3260 }
3261
3262 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3263 {
3264 struct drm_device *dev = crtc->dev;
3265 struct drm_i915_private *dev_priv = dev->dev_private;
3266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3267 int pipe = intel_crtc->pipe;
3268 u32 reg, temp;
3269
3270 /* disable CPU FDI tx and PCH FDI rx */
3271 reg = FDI_TX_CTL(pipe);
3272 temp = I915_READ(reg);
3273 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3274 POSTING_READ(reg);
3275
3276 reg = FDI_RX_CTL(pipe);
3277 temp = I915_READ(reg);
3278 temp &= ~(0x7 << 16);
3279 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3280 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3281
3282 POSTING_READ(reg);
3283 udelay(100);
3284
3285 /* Ironlake workaround, disable clock pointer after downing FDI */
3286 if (HAS_PCH_IBX(dev))
3287 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3288
3289 /* still set train pattern 1 */
3290 reg = FDI_TX_CTL(pipe);
3291 temp = I915_READ(reg);
3292 temp &= ~FDI_LINK_TRAIN_NONE;
3293 temp |= FDI_LINK_TRAIN_PATTERN_1;
3294 I915_WRITE(reg, temp);
3295
3296 reg = FDI_RX_CTL(pipe);
3297 temp = I915_READ(reg);
3298 if (HAS_PCH_CPT(dev)) {
3299 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3300 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3301 } else {
3302 temp &= ~FDI_LINK_TRAIN_NONE;
3303 temp |= FDI_LINK_TRAIN_PATTERN_1;
3304 }
3305 /* BPC in FDI rx is consistent with that in PIPECONF */
3306 temp &= ~(0x07 << 16);
3307 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3308 I915_WRITE(reg, temp);
3309
3310 POSTING_READ(reg);
3311 udelay(100);
3312 }
3313
3314 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3315 {
3316 struct intel_crtc *crtc;
3317
3318 /* Note that we don't need to be called with mode_config.lock here
3319 * as our list of CRTC objects is static for the lifetime of the
3320 * device and so cannot disappear as we iterate. Similarly, we can
3321 * happily treat the predicates as racy, atomic checks as userspace
3322 * cannot claim and pin a new fb without at least acquring the
3323 * struct_mutex and so serialising with us.
3324 */
3325 for_each_intel_crtc(dev, crtc) {
3326 if (atomic_read(&crtc->unpin_work_count) == 0)
3327 continue;
3328
3329 if (crtc->unpin_work)
3330 intel_wait_for_vblank(dev, crtc->pipe);
3331
3332 return true;
3333 }
3334
3335 return false;
3336 }
3337
3338 void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3339 {
3340 struct drm_device *dev = crtc->dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342
3343 if (crtc->primary->fb == NULL)
3344 return;
3345
3346 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3347
3348 WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3349 !intel_crtc_has_pending_flip(crtc),
3350 60*HZ) == 0);
3351
3352 mutex_lock(&dev->struct_mutex);
3353 intel_finish_fb(crtc->primary->fb);
3354 mutex_unlock(&dev->struct_mutex);
3355 }
3356
3357 /* Program iCLKIP clock to the desired frequency */
3358 static void lpt_program_iclkip(struct drm_crtc *crtc)
3359 {
3360 struct drm_device *dev = crtc->dev;
3361 struct drm_i915_private *dev_priv = dev->dev_private;
3362 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
3363 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3364 u32 temp;
3365
3366 mutex_lock(&dev_priv->dpio_lock);
3367
3368 /* It is necessary to ungate the pixclk gate prior to programming
3369 * the divisors, and gate it back when it is done.
3370 */
3371 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3372
3373 /* Disable SSCCTL */
3374 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3375 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3376 SBI_SSCCTL_DISABLE,
3377 SBI_ICLK);
3378
3379 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3380 if (clock == 20000) {
3381 auxdiv = 1;
3382 divsel = 0x41;
3383 phaseinc = 0x20;
3384 } else {
3385 /* The iCLK virtual clock root frequency is in MHz,
3386 * but the adjusted_mode->crtc_clock in in KHz. To get the
3387 * divisors, it is necessary to divide one by another, so we
3388 * convert the virtual clock precision to KHz here for higher
3389 * precision.
3390 */
3391 u32 iclk_virtual_root_freq = 172800 * 1000;
3392 u32 iclk_pi_range = 64;
3393 u32 desired_divisor, msb_divisor_value, pi_value;
3394
3395 desired_divisor = (iclk_virtual_root_freq / clock);
3396 msb_divisor_value = desired_divisor / iclk_pi_range;
3397 pi_value = desired_divisor % iclk_pi_range;
3398
3399 auxdiv = 0;
3400 divsel = msb_divisor_value - 2;
3401 phaseinc = pi_value;
3402 }
3403
3404 /* This should not happen with any sane values */
3405 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3406 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3407 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3408 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3409
3410 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3411 clock,
3412 auxdiv,
3413 divsel,
3414 phasedir,
3415 phaseinc);
3416
3417 /* Program SSCDIVINTPHASE6 */
3418 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
3419 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3420 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3421 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3422 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3423 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3424 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3425 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
3426
3427 /* Program SSCAUXDIV */
3428 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
3429 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3430 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3431 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
3432
3433 /* Enable modulator and associated divider */
3434 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3435 temp &= ~SBI_SSCCTL_DISABLE;
3436 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3437
3438 /* Wait for initialization time */
3439 udelay(24);
3440
3441 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3442
3443 mutex_unlock(&dev_priv->dpio_lock);
3444 }
3445
3446 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3447 enum pipe pch_transcoder)
3448 {
3449 struct drm_device *dev = crtc->base.dev;
3450 struct drm_i915_private *dev_priv = dev->dev_private;
3451 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3452
3453 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3454 I915_READ(HTOTAL(cpu_transcoder)));
3455 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3456 I915_READ(HBLANK(cpu_transcoder)));
3457 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3458 I915_READ(HSYNC(cpu_transcoder)));
3459
3460 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3461 I915_READ(VTOTAL(cpu_transcoder)));
3462 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3463 I915_READ(VBLANK(cpu_transcoder)));
3464 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3465 I915_READ(VSYNC(cpu_transcoder)));
3466 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3467 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3468 }
3469
3470 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
3471 {
3472 struct drm_i915_private *dev_priv = dev->dev_private;
3473 uint32_t temp;
3474
3475 temp = I915_READ(SOUTH_CHICKEN1);
3476 if (temp & FDI_BC_BIFURCATION_SELECT)
3477 return;
3478
3479 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3480 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3481
3482 temp |= FDI_BC_BIFURCATION_SELECT;
3483 DRM_DEBUG_KMS("enabling fdi C rx\n");
3484 I915_WRITE(SOUTH_CHICKEN1, temp);
3485 POSTING_READ(SOUTH_CHICKEN1);
3486 }
3487
3488 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3489 {
3490 struct drm_device *dev = intel_crtc->base.dev;
3491 struct drm_i915_private *dev_priv = dev->dev_private;
3492
3493 switch (intel_crtc->pipe) {
3494 case PIPE_A:
3495 break;
3496 case PIPE_B:
3497 if (intel_crtc->config.fdi_lanes > 2)
3498 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
3499 else
3500 cpt_enable_fdi_bc_bifurcation(dev);
3501
3502 break;
3503 case PIPE_C:
3504 cpt_enable_fdi_bc_bifurcation(dev);
3505
3506 break;
3507 default:
3508 BUG();
3509 }
3510 }
3511
3512 /*
3513 * Enable PCH resources required for PCH ports:
3514 * - PCH PLLs
3515 * - FDI training & RX/TX
3516 * - update transcoder timings
3517 * - DP transcoding bits
3518 * - transcoder
3519 */
3520 static void ironlake_pch_enable(struct drm_crtc *crtc)
3521 {
3522 struct drm_device *dev = crtc->dev;
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3525 int pipe = intel_crtc->pipe;
3526 u32 reg, temp;
3527
3528 assert_pch_transcoder_disabled(dev_priv, pipe);
3529
3530 if (IS_IVYBRIDGE(dev))
3531 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3532
3533 /* Write the TU size bits before fdi link training, so that error
3534 * detection works. */
3535 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3536 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3537
3538 /* For PCH output, training FDI link */
3539 dev_priv->display.fdi_link_train(crtc);
3540
3541 /* We need to program the right clock selection before writing the pixel
3542 * mutliplier into the DPLL. */
3543 if (HAS_PCH_CPT(dev)) {
3544 u32 sel;
3545
3546 temp = I915_READ(PCH_DPLL_SEL);
3547 temp |= TRANS_DPLL_ENABLE(pipe);
3548 sel = TRANS_DPLLB_SEL(pipe);
3549 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
3550 temp |= sel;
3551 else
3552 temp &= ~sel;
3553 I915_WRITE(PCH_DPLL_SEL, temp);
3554 }
3555
3556 /* XXX: pch pll's can be enabled any time before we enable the PCH
3557 * transcoder, and we actually should do this to not upset any PCH
3558 * transcoder that already use the clock when we share it.
3559 *
3560 * Note that enable_shared_dpll tries to do the right thing, but
3561 * get_shared_dpll unconditionally resets the pll - we need that to have
3562 * the right LVDS enable sequence. */
3563 intel_enable_shared_dpll(intel_crtc);
3564
3565 /* set transcoder timing, panel must allow it */
3566 assert_panel_unlocked(dev_priv, pipe);
3567 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
3568
3569 intel_fdi_normal_train(crtc);
3570
3571 /* For PCH DP, enable TRANS_DP_CTL */
3572 if (HAS_PCH_CPT(dev) &&
3573 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3574 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3575 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
3576 reg = TRANS_DP_CTL(pipe);
3577 temp = I915_READ(reg);
3578 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3579 TRANS_DP_SYNC_MASK |
3580 TRANS_DP_BPC_MASK);
3581 temp |= (TRANS_DP_OUTPUT_ENABLE |
3582 TRANS_DP_ENH_FRAMING);
3583 temp |= bpc << 9; /* same format but at 11:9 */
3584
3585 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3586 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3587 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3588 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3589
3590 switch (intel_trans_dp_port_sel(crtc)) {
3591 case PCH_DP_B:
3592 temp |= TRANS_DP_PORT_SEL_B;
3593 break;
3594 case PCH_DP_C:
3595 temp |= TRANS_DP_PORT_SEL_C;
3596 break;
3597 case PCH_DP_D:
3598 temp |= TRANS_DP_PORT_SEL_D;
3599 break;
3600 default:
3601 BUG();
3602 }
3603
3604 I915_WRITE(reg, temp);
3605 }
3606
3607 ironlake_enable_pch_transcoder(dev_priv, pipe);
3608 }
3609
3610 static void lpt_pch_enable(struct drm_crtc *crtc)
3611 {
3612 struct drm_device *dev = crtc->dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3615 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3616
3617 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
3618
3619 lpt_program_iclkip(crtc);
3620
3621 /* Set transcoder timing. */
3622 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3623
3624 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3625 }
3626
3627 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3628 {
3629 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3630
3631 if (pll == NULL)
3632 return;
3633
3634 if (pll->refcount == 0) {
3635 WARN(1, "bad %s refcount\n", pll->name);
3636 return;
3637 }
3638
3639 if (--pll->refcount == 0) {
3640 WARN_ON(pll->on);
3641 WARN_ON(pll->active);
3642 }
3643
3644 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3645 }
3646
3647 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
3648 {
3649 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3650 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3651 enum intel_dpll_id i;
3652
3653 if (pll) {
3654 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3655 crtc->base.base.id, pll->name);
3656 intel_put_shared_dpll(crtc);
3657 }
3658
3659 if (HAS_PCH_IBX(dev_priv->dev)) {
3660 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3661 i = (enum intel_dpll_id) crtc->pipe;
3662 pll = &dev_priv->shared_dplls[i];
3663
3664 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3665 crtc->base.base.id, pll->name);
3666
3667 WARN_ON(pll->refcount);
3668
3669 goto found;
3670 }
3671
3672 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3673 pll = &dev_priv->shared_dplls[i];
3674
3675 /* Only want to check enabled timings first */
3676 if (pll->refcount == 0)
3677 continue;
3678
3679 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3680 sizeof(pll->hw_state)) == 0) {
3681 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3682 crtc->base.base.id,
3683 pll->name, pll->refcount, pll->active);
3684
3685 goto found;
3686 }
3687 }
3688
3689 /* Ok no matching timings, maybe there's a free one? */
3690 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3691 pll = &dev_priv->shared_dplls[i];
3692 if (pll->refcount == 0) {
3693 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3694 crtc->base.base.id, pll->name);
3695 goto found;
3696 }
3697 }
3698
3699 return NULL;
3700
3701 found:
3702 if (pll->refcount == 0)
3703 pll->hw_state = crtc->config.dpll_hw_state;
3704
3705 crtc->config.shared_dpll = i;
3706 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3707 pipe_name(crtc->pipe));
3708
3709 pll->refcount++;
3710
3711 return pll;
3712 }
3713
3714 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3715 {
3716 struct drm_i915_private *dev_priv = dev->dev_private;
3717 int dslreg = PIPEDSL(pipe);
3718 u32 temp;
3719
3720 temp = I915_READ(dslreg);
3721 udelay(500);
3722 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3723 if (wait_for(I915_READ(dslreg) != temp, 5))
3724 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3725 }
3726 }
3727
3728 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3729 {
3730 struct drm_device *dev = crtc->base.dev;
3731 struct drm_i915_private *dev_priv = dev->dev_private;
3732 int pipe = crtc->pipe;
3733
3734 if (crtc->config.pch_pfit.enabled) {
3735 /* Force use of hard-coded filter coefficients
3736 * as some pre-programmed values are broken,
3737 * e.g. x201.
3738 */
3739 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3740 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3741 PF_PIPE_SEL_IVB(pipe));
3742 else
3743 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3744 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3745 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3746 }
3747 }
3748
3749 static void intel_enable_planes(struct drm_crtc *crtc)
3750 {
3751 struct drm_device *dev = crtc->dev;
3752 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3753 struct drm_plane *plane;
3754 struct intel_plane *intel_plane;
3755
3756 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3757 intel_plane = to_intel_plane(plane);
3758 if (intel_plane->pipe == pipe)
3759 intel_plane_restore(&intel_plane->base);
3760 }
3761 }
3762
3763 static void intel_disable_planes(struct drm_crtc *crtc)
3764 {
3765 struct drm_device *dev = crtc->dev;
3766 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3767 struct drm_plane *plane;
3768 struct intel_plane *intel_plane;
3769
3770 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
3771 intel_plane = to_intel_plane(plane);
3772 if (intel_plane->pipe == pipe)
3773 intel_plane_disable(&intel_plane->base);
3774 }
3775 }
3776
3777 void hsw_enable_ips(struct intel_crtc *crtc)
3778 {
3779 struct drm_device *dev = crtc->base.dev;
3780 struct drm_i915_private *dev_priv = dev->dev_private;
3781
3782 if (!crtc->config.ips_enabled)
3783 return;
3784
3785 /* We can only enable IPS after we enable a plane and wait for a vblank */
3786 intel_wait_for_vblank(dev, crtc->pipe);
3787
3788 assert_plane_enabled(dev_priv, crtc->plane);
3789 if (IS_BROADWELL(dev)) {
3790 mutex_lock(&dev_priv->rps.hw_lock);
3791 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
3792 mutex_unlock(&dev_priv->rps.hw_lock);
3793 /* Quoting Art Runyan: "its not safe to expect any particular
3794 * value in IPS_CTL bit 31 after enabling IPS through the
3795 * mailbox." Moreover, the mailbox may return a bogus state,
3796 * so we need to just enable it and continue on.
3797 */
3798 } else {
3799 I915_WRITE(IPS_CTL, IPS_ENABLE);
3800 /* The bit only becomes 1 in the next vblank, so this wait here
3801 * is essentially intel_wait_for_vblank. If we don't have this
3802 * and don't wait for vblanks until the end of crtc_enable, then
3803 * the HW state readout code will complain that the expected
3804 * IPS_CTL value is not the one we read. */
3805 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3806 DRM_ERROR("Timed out waiting for IPS enable\n");
3807 }
3808 }
3809
3810 void hsw_disable_ips(struct intel_crtc *crtc)
3811 {
3812 struct drm_device *dev = crtc->base.dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814
3815 if (!crtc->config.ips_enabled)
3816 return;
3817
3818 assert_plane_enabled(dev_priv, crtc->plane);
3819 if (IS_BROADWELL(dev)) {
3820 mutex_lock(&dev_priv->rps.hw_lock);
3821 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
3822 mutex_unlock(&dev_priv->rps.hw_lock);
3823 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
3824 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
3825 DRM_ERROR("Timed out waiting for IPS disable\n");
3826 } else {
3827 I915_WRITE(IPS_CTL, 0);
3828 POSTING_READ(IPS_CTL);
3829 }
3830
3831 /* We need to wait for a vblank before we can disable the plane. */
3832 intel_wait_for_vblank(dev, crtc->pipe);
3833 }
3834
3835 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3836 static void intel_crtc_load_lut(struct drm_crtc *crtc)
3837 {
3838 struct drm_device *dev = crtc->dev;
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3841 enum pipe pipe = intel_crtc->pipe;
3842 int palreg = PALETTE(pipe);
3843 int i;
3844 bool reenable_ips = false;
3845
3846 /* The clocks have to be on to load the palette. */
3847 if (!crtc->enabled || !intel_crtc->active)
3848 return;
3849
3850 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3851 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3852 assert_dsi_pll_enabled(dev_priv);
3853 else
3854 assert_pll_enabled(dev_priv, pipe);
3855 }
3856
3857 /* use legacy palette for Ironlake */
3858 if (HAS_PCH_SPLIT(dev))
3859 palreg = LGC_PALETTE(pipe);
3860
3861 /* Workaround : Do not read or write the pipe palette/gamma data while
3862 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3863 */
3864 if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled &&
3865 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3866 GAMMA_MODE_MODE_SPLIT)) {
3867 hsw_disable_ips(intel_crtc);
3868 reenable_ips = true;
3869 }
3870
3871 for (i = 0; i < 256; i++) {
3872 I915_WRITE(palreg + 4 * i,
3873 (intel_crtc->lut_r[i] << 16) |
3874 (intel_crtc->lut_g[i] << 8) |
3875 intel_crtc->lut_b[i]);
3876 }
3877
3878 if (reenable_ips)
3879 hsw_enable_ips(intel_crtc);
3880 }
3881
3882 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3883 {
3884 if (!enable && intel_crtc->overlay) {
3885 struct drm_device *dev = intel_crtc->base.dev;
3886 struct drm_i915_private *dev_priv = dev->dev_private;
3887
3888 mutex_lock(&dev->struct_mutex);
3889 dev_priv->mm.interruptible = false;
3890 (void) intel_overlay_switch_off(intel_crtc->overlay);
3891 dev_priv->mm.interruptible = true;
3892 mutex_unlock(&dev->struct_mutex);
3893 }
3894
3895 /* Let userspace switch the overlay on again. In most cases userspace
3896 * has to recompute where to put it anyway.
3897 */
3898 }
3899
3900 /**
3901 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3902 * cursor plane briefly if not already running after enabling the display
3903 * plane.
3904 * This workaround avoids occasional blank screens when self refresh is
3905 * enabled.
3906 */
3907 static void
3908 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3909 {
3910 u32 cntl = I915_READ(CURCNTR(pipe));
3911
3912 if ((cntl & CURSOR_MODE) == 0) {
3913 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3914
3915 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3916 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3917 intel_wait_for_vblank(dev_priv->dev, pipe);
3918 I915_WRITE(CURCNTR(pipe), cntl);
3919 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3920 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3921 }
3922 }
3923
3924 static void intel_crtc_enable_planes(struct drm_crtc *crtc)
3925 {
3926 struct drm_device *dev = crtc->dev;
3927 struct drm_i915_private *dev_priv = dev->dev_private;
3928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3929 int pipe = intel_crtc->pipe;
3930 int plane = intel_crtc->plane;
3931
3932 drm_vblank_on(dev, pipe);
3933
3934 intel_enable_primary_hw_plane(dev_priv, plane, pipe);
3935 intel_enable_planes(crtc);
3936 /* The fixup needs to happen before cursor is enabled */
3937 if (IS_G4X(dev))
3938 g4x_fixup_plane(dev_priv, pipe);
3939 intel_crtc_update_cursor(crtc, true);
3940 intel_crtc_dpms_overlay(intel_crtc, true);
3941
3942 hsw_enable_ips(intel_crtc);
3943
3944 mutex_lock(&dev->struct_mutex);
3945 intel_update_fbc(dev);
3946 intel_edp_psr_update(dev);
3947 mutex_unlock(&dev->struct_mutex);
3948 }
3949
3950 static void intel_crtc_disable_planes(struct drm_crtc *crtc)
3951 {
3952 struct drm_device *dev = crtc->dev;
3953 struct drm_i915_private *dev_priv = dev->dev_private;
3954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3955 int pipe = intel_crtc->pipe;
3956 int plane = intel_crtc->plane;
3957
3958 intel_crtc_wait_for_pending_flips(crtc);
3959
3960 if (dev_priv->fbc.plane == plane)
3961 intel_disable_fbc(dev);
3962
3963 hsw_disable_ips(intel_crtc);
3964
3965 intel_crtc_dpms_overlay(intel_crtc, false);
3966 intel_crtc_update_cursor(crtc, false);
3967 intel_disable_planes(crtc);
3968 intel_disable_primary_hw_plane(dev_priv, plane, pipe);
3969
3970 drm_vblank_off(dev, pipe);
3971 }
3972
3973 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3974 {
3975 struct drm_device *dev = crtc->dev;
3976 struct drm_i915_private *dev_priv = dev->dev_private;
3977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3978 struct intel_encoder *encoder;
3979 int pipe = intel_crtc->pipe;
3980 enum plane plane = intel_crtc->plane;
3981
3982 WARN_ON(!crtc->enabled);
3983
3984 if (intel_crtc->active)
3985 return;
3986
3987 if (intel_crtc->config.has_pch_encoder)
3988 intel_prepare_shared_dpll(intel_crtc);
3989
3990 if (intel_crtc->config.has_dp_encoder)
3991 intel_dp_set_m_n(intel_crtc);
3992
3993 intel_set_pipe_timings(intel_crtc);
3994
3995 if (intel_crtc->config.has_pch_encoder) {
3996 intel_cpu_transcoder_set_m_n(intel_crtc,
3997 &intel_crtc->config.fdi_m_n);
3998 }
3999
4000 ironlake_set_pipeconf(crtc);
4001
4002 /* Set up the display plane register */
4003 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
4004 POSTING_READ(DSPCNTR(plane));
4005
4006 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4007 crtc->x, crtc->y);
4008
4009 intel_crtc->active = true;
4010
4011 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4012 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4013
4014 for_each_encoder_on_crtc(dev, crtc, encoder)
4015 if (encoder->pre_enable)
4016 encoder->pre_enable(encoder);
4017
4018 if (intel_crtc->config.has_pch_encoder) {
4019 /* Note: FDI PLL enabling _must_ be done before we enable the
4020 * cpu pipes, hence this is separate from all the other fdi/pch
4021 * enabling. */
4022 ironlake_fdi_pll_enable(intel_crtc);
4023 } else {
4024 assert_fdi_tx_disabled(dev_priv, pipe);
4025 assert_fdi_rx_disabled(dev_priv, pipe);
4026 }
4027
4028 ironlake_pfit_enable(intel_crtc);
4029
4030 /*
4031 * On ILK+ LUT must be loaded before the pipe is running but with
4032 * clocks enabled
4033 */
4034 intel_crtc_load_lut(crtc);
4035
4036 intel_update_watermarks(crtc);
4037 intel_enable_pipe(intel_crtc);
4038
4039 if (intel_crtc->config.has_pch_encoder)
4040 ironlake_pch_enable(crtc);
4041
4042 for_each_encoder_on_crtc(dev, crtc, encoder)
4043 encoder->enable(encoder);
4044
4045 if (HAS_PCH_CPT(dev))
4046 cpt_verify_modeset(dev, intel_crtc->pipe);
4047
4048 intel_crtc_enable_planes(crtc);
4049 }
4050
4051 /* IPS only exists on ULT machines and is tied to pipe A. */
4052 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4053 {
4054 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
4055 }
4056
4057 /*
4058 * This implements the workaround described in the "notes" section of the mode
4059 * set sequence documentation. When going from no pipes or single pipe to
4060 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4061 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4062 */
4063 static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4064 {
4065 struct drm_device *dev = crtc->base.dev;
4066 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4067
4068 /* We want to get the other_active_crtc only if there's only 1 other
4069 * active crtc. */
4070 for_each_intel_crtc(dev, crtc_it) {
4071 if (!crtc_it->active || crtc_it == crtc)
4072 continue;
4073
4074 if (other_active_crtc)
4075 return;
4076
4077 other_active_crtc = crtc_it;
4078 }
4079 if (!other_active_crtc)
4080 return;
4081
4082 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4083 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4084 }
4085
4086 static void haswell_crtc_enable(struct drm_crtc *crtc)
4087 {
4088 struct drm_device *dev = crtc->dev;
4089 struct drm_i915_private *dev_priv = dev->dev_private;
4090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4091 struct intel_encoder *encoder;
4092 int pipe = intel_crtc->pipe;
4093 enum plane plane = intel_crtc->plane;
4094
4095 WARN_ON(!crtc->enabled);
4096
4097 if (intel_crtc->active)
4098 return;
4099
4100 if (intel_crtc->config.has_dp_encoder)
4101 intel_dp_set_m_n(intel_crtc);
4102
4103 intel_set_pipe_timings(intel_crtc);
4104
4105 if (intel_crtc->config.has_pch_encoder) {
4106 intel_cpu_transcoder_set_m_n(intel_crtc,
4107 &intel_crtc->config.fdi_m_n);
4108 }
4109
4110 haswell_set_pipeconf(crtc);
4111
4112 intel_set_pipe_csc(crtc);
4113
4114 /* Set up the display plane register */
4115 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
4116 POSTING_READ(DSPCNTR(plane));
4117
4118 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4119 crtc->x, crtc->y);
4120
4121 intel_crtc->active = true;
4122
4123 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4124 if (intel_crtc->config.has_pch_encoder)
4125 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4126
4127 if (intel_crtc->config.has_pch_encoder)
4128 dev_priv->display.fdi_link_train(crtc);
4129
4130 for_each_encoder_on_crtc(dev, crtc, encoder)
4131 if (encoder->pre_enable)
4132 encoder->pre_enable(encoder);
4133
4134 intel_ddi_enable_pipe_clock(intel_crtc);
4135
4136 ironlake_pfit_enable(intel_crtc);
4137
4138 /*
4139 * On ILK+ LUT must be loaded before the pipe is running but with
4140 * clocks enabled
4141 */
4142 intel_crtc_load_lut(crtc);
4143
4144 intel_ddi_set_pipe_settings(crtc);
4145 intel_ddi_enable_transcoder_func(crtc);
4146
4147 intel_update_watermarks(crtc);
4148 intel_enable_pipe(intel_crtc);
4149
4150 if (intel_crtc->config.has_pch_encoder)
4151 lpt_pch_enable(crtc);
4152
4153 for_each_encoder_on_crtc(dev, crtc, encoder) {
4154 encoder->enable(encoder);
4155 intel_opregion_notify_encoder(encoder, true);
4156 }
4157
4158 /* If we change the relative order between pipe/planes enabling, we need
4159 * to change the workaround. */
4160 haswell_mode_set_planes_workaround(intel_crtc);
4161 intel_crtc_enable_planes(crtc);
4162 }
4163
4164 static void ironlake_pfit_disable(struct intel_crtc *crtc)
4165 {
4166 struct drm_device *dev = crtc->base.dev;
4167 struct drm_i915_private *dev_priv = dev->dev_private;
4168 int pipe = crtc->pipe;
4169
4170 /* To avoid upsetting the power well on haswell only disable the pfit if
4171 * it's in use. The hw state code will make sure we get this right. */
4172 if (crtc->config.pch_pfit.enabled) {
4173 I915_WRITE(PF_CTL(pipe), 0);
4174 I915_WRITE(PF_WIN_POS(pipe), 0);
4175 I915_WRITE(PF_WIN_SZ(pipe), 0);
4176 }
4177 }
4178
4179 static void ironlake_crtc_disable(struct drm_crtc *crtc)
4180 {
4181 struct drm_device *dev = crtc->dev;
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4184 struct intel_encoder *encoder;
4185 int pipe = intel_crtc->pipe;
4186 u32 reg, temp;
4187
4188 if (!intel_crtc->active)
4189 return;
4190
4191 intel_crtc_disable_planes(crtc);
4192
4193 for_each_encoder_on_crtc(dev, crtc, encoder)
4194 encoder->disable(encoder);
4195
4196 if (intel_crtc->config.has_pch_encoder)
4197 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
4198
4199 intel_disable_pipe(dev_priv, pipe);
4200
4201 ironlake_pfit_disable(intel_crtc);
4202
4203 for_each_encoder_on_crtc(dev, crtc, encoder)
4204 if (encoder->post_disable)
4205 encoder->post_disable(encoder);
4206
4207 if (intel_crtc->config.has_pch_encoder) {
4208 ironlake_fdi_disable(crtc);
4209
4210 ironlake_disable_pch_transcoder(dev_priv, pipe);
4211 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
4212
4213 if (HAS_PCH_CPT(dev)) {
4214 /* disable TRANS_DP_CTL */
4215 reg = TRANS_DP_CTL(pipe);
4216 temp = I915_READ(reg);
4217 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4218 TRANS_DP_PORT_SEL_MASK);
4219 temp |= TRANS_DP_PORT_SEL_NONE;
4220 I915_WRITE(reg, temp);
4221
4222 /* disable DPLL_SEL */
4223 temp = I915_READ(PCH_DPLL_SEL);
4224 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
4225 I915_WRITE(PCH_DPLL_SEL, temp);
4226 }
4227
4228 /* disable PCH DPLL */
4229 intel_disable_shared_dpll(intel_crtc);
4230
4231 ironlake_fdi_pll_disable(intel_crtc);
4232 }
4233
4234 intel_crtc->active = false;
4235 intel_update_watermarks(crtc);
4236
4237 mutex_lock(&dev->struct_mutex);
4238 intel_update_fbc(dev);
4239 intel_edp_psr_update(dev);
4240 mutex_unlock(&dev->struct_mutex);
4241 }
4242
4243 static void haswell_crtc_disable(struct drm_crtc *crtc)
4244 {
4245 struct drm_device *dev = crtc->dev;
4246 struct drm_i915_private *dev_priv = dev->dev_private;
4247 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4248 struct intel_encoder *encoder;
4249 int pipe = intel_crtc->pipe;
4250 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4251
4252 if (!intel_crtc->active)
4253 return;
4254
4255 intel_crtc_disable_planes(crtc);
4256
4257 for_each_encoder_on_crtc(dev, crtc, encoder) {
4258 intel_opregion_notify_encoder(encoder, false);
4259 encoder->disable(encoder);
4260 }
4261
4262 if (intel_crtc->config.has_pch_encoder)
4263 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4264 intel_disable_pipe(dev_priv, pipe);
4265
4266 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4267
4268 ironlake_pfit_disable(intel_crtc);
4269
4270 intel_ddi_disable_pipe_clock(intel_crtc);
4271
4272 for_each_encoder_on_crtc(dev, crtc, encoder)
4273 if (encoder->post_disable)
4274 encoder->post_disable(encoder);
4275
4276 if (intel_crtc->config.has_pch_encoder) {
4277 lpt_disable_pch_transcoder(dev_priv);
4278 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
4279 intel_ddi_fdi_disable(crtc);
4280 }
4281
4282 intel_crtc->active = false;
4283 intel_update_watermarks(crtc);
4284
4285 mutex_lock(&dev->struct_mutex);
4286 intel_update_fbc(dev);
4287 intel_edp_psr_update(dev);
4288 mutex_unlock(&dev->struct_mutex);
4289 }
4290
4291 static void ironlake_crtc_off(struct drm_crtc *crtc)
4292 {
4293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4294 intel_put_shared_dpll(intel_crtc);
4295 }
4296
4297 static void haswell_crtc_off(struct drm_crtc *crtc)
4298 {
4299 intel_ddi_put_crtc_pll(crtc);
4300 }
4301
4302 static void i9xx_pfit_enable(struct intel_crtc *crtc)
4303 {
4304 struct drm_device *dev = crtc->base.dev;
4305 struct drm_i915_private *dev_priv = dev->dev_private;
4306 struct intel_crtc_config *pipe_config = &crtc->config;
4307
4308 if (!crtc->config.gmch_pfit.control)
4309 return;
4310
4311 /*
4312 * The panel fitter should only be adjusted whilst the pipe is disabled,
4313 * according to register description and PRM.
4314 */
4315 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4316 assert_pipe_disabled(dev_priv, crtc->pipe);
4317
4318 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4319 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
4320
4321 /* Border color in case we don't scale up to the full screen. Black by
4322 * default, change to something else for debugging. */
4323 I915_WRITE(BCLRPAT(crtc->pipe), 0);
4324 }
4325
4326 #define for_each_power_domain(domain, mask) \
4327 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4328 if ((1 << (domain)) & (mask))
4329
4330 enum intel_display_power_domain
4331 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4332 {
4333 struct drm_device *dev = intel_encoder->base.dev;
4334 struct intel_digital_port *intel_dig_port;
4335
4336 switch (intel_encoder->type) {
4337 case INTEL_OUTPUT_UNKNOWN:
4338 /* Only DDI platforms should ever use this output type */
4339 WARN_ON_ONCE(!HAS_DDI(dev));
4340 case INTEL_OUTPUT_DISPLAYPORT:
4341 case INTEL_OUTPUT_HDMI:
4342 case INTEL_OUTPUT_EDP:
4343 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
4344 switch (intel_dig_port->port) {
4345 case PORT_A:
4346 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4347 case PORT_B:
4348 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4349 case PORT_C:
4350 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4351 case PORT_D:
4352 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4353 default:
4354 WARN_ON_ONCE(1);
4355 return POWER_DOMAIN_PORT_OTHER;
4356 }
4357 case INTEL_OUTPUT_ANALOG:
4358 return POWER_DOMAIN_PORT_CRT;
4359 case INTEL_OUTPUT_DSI:
4360 return POWER_DOMAIN_PORT_DSI;
4361 default:
4362 return POWER_DOMAIN_PORT_OTHER;
4363 }
4364 }
4365
4366 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
4367 {
4368 struct drm_device *dev = crtc->dev;
4369 struct intel_encoder *intel_encoder;
4370 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4371 enum pipe pipe = intel_crtc->pipe;
4372 bool pfit_enabled = intel_crtc->config.pch_pfit.enabled;
4373 unsigned long mask;
4374 enum transcoder transcoder;
4375
4376 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4377
4378 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4379 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
4380 if (pfit_enabled)
4381 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4382
4383 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4384 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4385
4386 return mask;
4387 }
4388
4389 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
4390 bool enable)
4391 {
4392 if (dev_priv->power_domains.init_power_on == enable)
4393 return;
4394
4395 if (enable)
4396 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
4397 else
4398 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
4399
4400 dev_priv->power_domains.init_power_on = enable;
4401 }
4402
4403 static void modeset_update_crtc_power_domains(struct drm_device *dev)
4404 {
4405 struct drm_i915_private *dev_priv = dev->dev_private;
4406 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4407 struct intel_crtc *crtc;
4408
4409 /*
4410 * First get all needed power domains, then put all unneeded, to avoid
4411 * any unnecessary toggling of the power wells.
4412 */
4413 for_each_intel_crtc(dev, crtc) {
4414 enum intel_display_power_domain domain;
4415
4416 if (!crtc->base.enabled)
4417 continue;
4418
4419 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
4420
4421 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4422 intel_display_power_get(dev_priv, domain);
4423 }
4424
4425 for_each_intel_crtc(dev, crtc) {
4426 enum intel_display_power_domain domain;
4427
4428 for_each_power_domain(domain, crtc->enabled_power_domains)
4429 intel_display_power_put(dev_priv, domain);
4430
4431 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4432 }
4433
4434 intel_display_set_init_power(dev_priv, false);
4435 }
4436
4437 int valleyview_get_vco(struct drm_i915_private *dev_priv)
4438 {
4439 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
4440
4441 /* Obtain SKU information */
4442 mutex_lock(&dev_priv->dpio_lock);
4443 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4444 CCK_FUSE_HPLL_FREQ_MASK;
4445 mutex_unlock(&dev_priv->dpio_lock);
4446
4447 return vco_freq[hpll_freq];
4448 }
4449
4450 /* Adjust CDclk dividers to allow high res or save power if possible */
4451 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
4452 {
4453 struct drm_i915_private *dev_priv = dev->dev_private;
4454 u32 val, cmd;
4455
4456 WARN_ON(valleyview_cur_cdclk(dev_priv) != dev_priv->vlv_cdclk_freq);
4457 dev_priv->vlv_cdclk_freq = cdclk;
4458
4459 if (cdclk >= 320) /* jump to highest voltage for 400MHz too */
4460 cmd = 2;
4461 else if (cdclk == 266)
4462 cmd = 1;
4463 else
4464 cmd = 0;
4465
4466 mutex_lock(&dev_priv->rps.hw_lock);
4467 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4468 val &= ~DSPFREQGUAR_MASK;
4469 val |= (cmd << DSPFREQGUAR_SHIFT);
4470 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
4471 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
4472 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
4473 50)) {
4474 DRM_ERROR("timed out waiting for CDclk change\n");
4475 }
4476 mutex_unlock(&dev_priv->rps.hw_lock);
4477
4478 if (cdclk == 400) {
4479 u32 divider, vco;
4480
4481 vco = valleyview_get_vco(dev_priv);
4482 divider = ((vco << 1) / cdclk) - 1;
4483
4484 mutex_lock(&dev_priv->dpio_lock);
4485 /* adjust cdclk divider */
4486 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4487 val &= ~0xf;
4488 val |= divider;
4489 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
4490 mutex_unlock(&dev_priv->dpio_lock);
4491 }
4492
4493 mutex_lock(&dev_priv->dpio_lock);
4494 /* adjust self-refresh exit latency value */
4495 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
4496 val &= ~0x7f;
4497
4498 /*
4499 * For high bandwidth configs, we set a higher latency in the bunit
4500 * so that the core display fetch happens in time to avoid underruns.
4501 */
4502 if (cdclk == 400)
4503 val |= 4500 / 250; /* 4.5 usec */
4504 else
4505 val |= 3000 / 250; /* 3.0 usec */
4506 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
4507 mutex_unlock(&dev_priv->dpio_lock);
4508
4509 /* Since we changed the CDclk, we need to update the GMBUSFREQ too */
4510 intel_i2c_reset(dev);
4511 }
4512
4513 int valleyview_cur_cdclk(struct drm_i915_private *dev_priv)
4514 {
4515 int cur_cdclk, vco;
4516 int divider;
4517
4518 vco = valleyview_get_vco(dev_priv);
4519
4520 mutex_lock(&dev_priv->dpio_lock);
4521 divider = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
4522 mutex_unlock(&dev_priv->dpio_lock);
4523
4524 divider &= 0xf;
4525
4526 cur_cdclk = (vco << 1) / (divider + 1);
4527
4528 return cur_cdclk;
4529 }
4530
4531 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
4532 int max_pixclk)
4533 {
4534 /*
4535 * Really only a few cases to deal with, as only 4 CDclks are supported:
4536 * 200MHz
4537 * 267MHz
4538 * 320MHz
4539 * 400MHz
4540 * So we check to see whether we're above 90% of the lower bin and
4541 * adjust if needed.
4542 */
4543 if (max_pixclk > 288000) {
4544 return 400;
4545 } else if (max_pixclk > 240000) {
4546 return 320;
4547 } else
4548 return 266;
4549 /* Looks like the 200MHz CDclk freq doesn't work on some configs */
4550 }
4551
4552 /* compute the max pixel clock for new configuration */
4553 static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
4554 {
4555 struct drm_device *dev = dev_priv->dev;
4556 struct intel_crtc *intel_crtc;
4557 int max_pixclk = 0;
4558
4559 for_each_intel_crtc(dev, intel_crtc) {
4560 if (intel_crtc->new_enabled)
4561 max_pixclk = max(max_pixclk,
4562 intel_crtc->new_config->adjusted_mode.crtc_clock);
4563 }
4564
4565 return max_pixclk;
4566 }
4567
4568 static void valleyview_modeset_global_pipes(struct drm_device *dev,
4569 unsigned *prepare_pipes)
4570 {
4571 struct drm_i915_private *dev_priv = dev->dev_private;
4572 struct intel_crtc *intel_crtc;
4573 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4574
4575 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
4576 dev_priv->vlv_cdclk_freq)
4577 return;
4578
4579 /* disable/enable all currently active pipes while we change cdclk */
4580 for_each_intel_crtc(dev, intel_crtc)
4581 if (intel_crtc->base.enabled)
4582 *prepare_pipes |= (1 << intel_crtc->pipe);
4583 }
4584
4585 static void valleyview_modeset_global_resources(struct drm_device *dev)
4586 {
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4588 int max_pixclk = intel_mode_max_pixclk(dev_priv);
4589 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
4590
4591 if (req_cdclk != dev_priv->vlv_cdclk_freq)
4592 valleyview_set_cdclk(dev, req_cdclk);
4593 modeset_update_crtc_power_domains(dev);
4594 }
4595
4596 static void valleyview_crtc_enable(struct drm_crtc *crtc)
4597 {
4598 struct drm_device *dev = crtc->dev;
4599 struct drm_i915_private *dev_priv = dev->dev_private;
4600 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4601 struct intel_encoder *encoder;
4602 int pipe = intel_crtc->pipe;
4603 int plane = intel_crtc->plane;
4604 bool is_dsi;
4605 u32 dspcntr;
4606
4607 WARN_ON(!crtc->enabled);
4608
4609 if (intel_crtc->active)
4610 return;
4611
4612 vlv_prepare_pll(intel_crtc);
4613
4614 /* Set up the display plane register */
4615 dspcntr = DISPPLANE_GAMMA_ENABLE;
4616
4617 if (intel_crtc->config.has_dp_encoder)
4618 intel_dp_set_m_n(intel_crtc);
4619
4620 intel_set_pipe_timings(intel_crtc);
4621
4622 /* pipesrc and dspsize control the size that is scaled from,
4623 * which should always be the user's requested size.
4624 */
4625 I915_WRITE(DSPSIZE(plane),
4626 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4627 (intel_crtc->config.pipe_src_w - 1));
4628 I915_WRITE(DSPPOS(plane), 0);
4629
4630 i9xx_set_pipeconf(intel_crtc);
4631
4632 I915_WRITE(DSPCNTR(plane), dspcntr);
4633 POSTING_READ(DSPCNTR(plane));
4634
4635 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4636 crtc->x, crtc->y);
4637
4638 intel_crtc->active = true;
4639
4640 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4641
4642 for_each_encoder_on_crtc(dev, crtc, encoder)
4643 if (encoder->pre_pll_enable)
4644 encoder->pre_pll_enable(encoder);
4645
4646 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
4647
4648 if (!is_dsi) {
4649 if (IS_CHERRYVIEW(dev))
4650 chv_enable_pll(intel_crtc);
4651 else
4652 vlv_enable_pll(intel_crtc);
4653 }
4654
4655 for_each_encoder_on_crtc(dev, crtc, encoder)
4656 if (encoder->pre_enable)
4657 encoder->pre_enable(encoder);
4658
4659 i9xx_pfit_enable(intel_crtc);
4660
4661 intel_crtc_load_lut(crtc);
4662
4663 intel_update_watermarks(crtc);
4664 intel_enable_pipe(intel_crtc);
4665
4666 for_each_encoder_on_crtc(dev, crtc, encoder)
4667 encoder->enable(encoder);
4668
4669 intel_crtc_enable_planes(crtc);
4670
4671 /* Underruns don't raise interrupts, so check manually. */
4672 i9xx_check_fifo_underruns(dev);
4673 }
4674
4675 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
4676 {
4677 struct drm_device *dev = crtc->base.dev;
4678 struct drm_i915_private *dev_priv = dev->dev_private;
4679
4680 I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0);
4681 I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1);
4682 }
4683
4684 static void i9xx_crtc_enable(struct drm_crtc *crtc)
4685 {
4686 struct drm_device *dev = crtc->dev;
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4689 struct intel_encoder *encoder;
4690 int pipe = intel_crtc->pipe;
4691 int plane = intel_crtc->plane;
4692 u32 dspcntr;
4693
4694 WARN_ON(!crtc->enabled);
4695
4696 if (intel_crtc->active)
4697 return;
4698
4699 i9xx_set_pll_dividers(intel_crtc);
4700
4701 /* Set up the display plane register */
4702 dspcntr = DISPPLANE_GAMMA_ENABLE;
4703
4704 if (pipe == 0)
4705 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4706 else
4707 dspcntr |= DISPPLANE_SEL_PIPE_B;
4708
4709 if (intel_crtc->config.has_dp_encoder)
4710 intel_dp_set_m_n(intel_crtc);
4711
4712 intel_set_pipe_timings(intel_crtc);
4713
4714 /* pipesrc and dspsize control the size that is scaled from,
4715 * which should always be the user's requested size.
4716 */
4717 I915_WRITE(DSPSIZE(plane),
4718 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4719 (intel_crtc->config.pipe_src_w - 1));
4720 I915_WRITE(DSPPOS(plane), 0);
4721
4722 i9xx_set_pipeconf(intel_crtc);
4723
4724 I915_WRITE(DSPCNTR(plane), dspcntr);
4725 POSTING_READ(DSPCNTR(plane));
4726
4727 dev_priv->display.update_primary_plane(crtc, crtc->primary->fb,
4728 crtc->x, crtc->y);
4729
4730 intel_crtc->active = true;
4731
4732 if (!IS_GEN2(dev))
4733 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4734
4735 for_each_encoder_on_crtc(dev, crtc, encoder)
4736 if (encoder->pre_enable)
4737 encoder->pre_enable(encoder);
4738
4739 i9xx_enable_pll(intel_crtc);
4740
4741 i9xx_pfit_enable(intel_crtc);
4742
4743 intel_crtc_load_lut(crtc);
4744
4745 intel_update_watermarks(crtc);
4746 intel_enable_pipe(intel_crtc);
4747
4748 for_each_encoder_on_crtc(dev, crtc, encoder)
4749 encoder->enable(encoder);
4750
4751 intel_crtc_enable_planes(crtc);
4752
4753 /*
4754 * Gen2 reports pipe underruns whenever all planes are disabled.
4755 * So don't enable underrun reporting before at least some planes
4756 * are enabled.
4757 * FIXME: Need to fix the logic to work when we turn off all planes
4758 * but leave the pipe running.
4759 */
4760 if (IS_GEN2(dev))
4761 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
4762
4763 /* Underruns don't raise interrupts, so check manually. */
4764 i9xx_check_fifo_underruns(dev);
4765 }
4766
4767 static void i9xx_pfit_disable(struct intel_crtc *crtc)
4768 {
4769 struct drm_device *dev = crtc->base.dev;
4770 struct drm_i915_private *dev_priv = dev->dev_private;
4771
4772 if (!crtc->config.gmch_pfit.control)
4773 return;
4774
4775 assert_pipe_disabled(dev_priv, crtc->pipe);
4776
4777 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
4778 I915_READ(PFIT_CONTROL));
4779 I915_WRITE(PFIT_CONTROL, 0);
4780 }
4781
4782 static void i9xx_crtc_disable(struct drm_crtc *crtc)
4783 {
4784 struct drm_device *dev = crtc->dev;
4785 struct drm_i915_private *dev_priv = dev->dev_private;
4786 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4787 struct intel_encoder *encoder;
4788 int pipe = intel_crtc->pipe;
4789
4790 if (!intel_crtc->active)
4791 return;
4792
4793 /*
4794 * Gen2 reports pipe underruns whenever all planes are disabled.
4795 * So diasble underrun reporting before all the planes get disabled.
4796 * FIXME: Need to fix the logic to work when we turn off all planes
4797 * but leave the pipe running.
4798 */
4799 if (IS_GEN2(dev))
4800 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4801
4802 intel_crtc_disable_planes(crtc);
4803
4804 for_each_encoder_on_crtc(dev, crtc, encoder)
4805 encoder->disable(encoder);
4806
4807 /*
4808 * On gen2 planes are double buffered but the pipe isn't, so we must
4809 * wait for planes to fully turn off before disabling the pipe.
4810 */
4811 if (IS_GEN2(dev))
4812 intel_wait_for_vblank(dev, pipe);
4813
4814 intel_disable_pipe(dev_priv, pipe);
4815
4816 i9xx_pfit_disable(intel_crtc);
4817
4818 for_each_encoder_on_crtc(dev, crtc, encoder)
4819 if (encoder->post_disable)
4820 encoder->post_disable(encoder);
4821
4822 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) {
4823 if (IS_CHERRYVIEW(dev))
4824 chv_disable_pll(dev_priv, pipe);
4825 else if (IS_VALLEYVIEW(dev))
4826 vlv_disable_pll(dev_priv, pipe);
4827 else
4828 i9xx_disable_pll(dev_priv, pipe);
4829 }
4830
4831 if (!IS_GEN2(dev))
4832 intel_set_cpu_fifo_underrun_reporting(dev, pipe, false);
4833
4834 intel_crtc->active = false;
4835 intel_update_watermarks(crtc);
4836
4837 mutex_lock(&dev->struct_mutex);
4838 intel_update_fbc(dev);
4839 intel_edp_psr_update(dev);
4840 mutex_unlock(&dev->struct_mutex);
4841 }
4842
4843 static void i9xx_crtc_off(struct drm_crtc *crtc)
4844 {
4845 }
4846
4847 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4848 bool enabled)
4849 {
4850 struct drm_device *dev = crtc->dev;
4851 struct drm_i915_master_private *master_priv;
4852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4853 int pipe = intel_crtc->pipe;
4854
4855 if (!dev->primary->master)
4856 return;
4857
4858 master_priv = dev->primary->master->driver_priv;
4859 if (!master_priv->sarea_priv)
4860 return;
4861
4862 switch (pipe) {
4863 case 0:
4864 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4865 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4866 break;
4867 case 1:
4868 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4869 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4870 break;
4871 default:
4872 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
4873 break;
4874 }
4875 }
4876
4877 /**
4878 * Sets the power management mode of the pipe and plane.
4879 */
4880 void intel_crtc_update_dpms(struct drm_crtc *crtc)
4881 {
4882 struct drm_device *dev = crtc->dev;
4883 struct drm_i915_private *dev_priv = dev->dev_private;
4884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4885 struct intel_encoder *intel_encoder;
4886 enum intel_display_power_domain domain;
4887 unsigned long domains;
4888 bool enable = false;
4889
4890 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4891 enable |= intel_encoder->connectors_active;
4892
4893 if (enable) {
4894 if (!intel_crtc->active) {
4895 /*
4896 * FIXME: DDI plls and relevant code isn't converted
4897 * yet, so do runtime PM for DPMS only for all other
4898 * platforms for now.
4899 */
4900 if (!HAS_DDI(dev)) {
4901 domains = get_crtc_power_domains(crtc);
4902 for_each_power_domain(domain, domains)
4903 intel_display_power_get(dev_priv, domain);
4904 intel_crtc->enabled_power_domains = domains;
4905 }
4906
4907 dev_priv->display.crtc_enable(crtc);
4908 }
4909 } else {
4910 if (intel_crtc->active) {
4911 dev_priv->display.crtc_disable(crtc);
4912
4913 if (!HAS_DDI(dev)) {
4914 domains = intel_crtc->enabled_power_domains;
4915 for_each_power_domain(domain, domains)
4916 intel_display_power_put(dev_priv, domain);
4917 intel_crtc->enabled_power_domains = 0;
4918 }
4919 }
4920 }
4921
4922 intel_crtc_update_sarea(crtc, enable);
4923 }
4924
4925 static void intel_crtc_disable(struct drm_crtc *crtc)
4926 {
4927 struct drm_device *dev = crtc->dev;
4928 struct drm_connector *connector;
4929 struct drm_i915_private *dev_priv = dev->dev_private;
4930
4931 /* crtc should still be enabled when we disable it. */
4932 WARN_ON(!crtc->enabled);
4933
4934 dev_priv->display.crtc_disable(crtc);
4935 intel_crtc_update_sarea(crtc, false);
4936 dev_priv->display.off(crtc);
4937
4938 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
4939 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
4940 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
4941
4942 if (crtc->primary->fb) {
4943 mutex_lock(&dev->struct_mutex);
4944 intel_unpin_fb_obj(to_intel_framebuffer(crtc->primary->fb)->obj);
4945 mutex_unlock(&dev->struct_mutex);
4946 crtc->primary->fb = NULL;
4947 }
4948
4949 /* Update computed state. */
4950 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4951 if (!connector->encoder || !connector->encoder->crtc)
4952 continue;
4953
4954 if (connector->encoder->crtc != crtc)
4955 continue;
4956
4957 connector->dpms = DRM_MODE_DPMS_OFF;
4958 to_intel_encoder(connector->encoder)->connectors_active = false;
4959 }
4960 }
4961
4962 void intel_encoder_destroy(struct drm_encoder *encoder)
4963 {
4964 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4965
4966 drm_encoder_cleanup(encoder);
4967 kfree(intel_encoder);
4968 }
4969
4970 /* Simple dpms helper for encoders with just one connector, no cloning and only
4971 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4972 * state of the entire output pipe. */
4973 static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
4974 {
4975 if (mode == DRM_MODE_DPMS_ON) {
4976 encoder->connectors_active = true;
4977
4978 intel_crtc_update_dpms(encoder->base.crtc);
4979 } else {
4980 encoder->connectors_active = false;
4981
4982 intel_crtc_update_dpms(encoder->base.crtc);
4983 }
4984 }
4985
4986 /* Cross check the actual hw state with our own modeset state tracking (and it's
4987 * internal consistency). */
4988 static void intel_connector_check_state(struct intel_connector *connector)
4989 {
4990 if (connector->get_hw_state(connector)) {
4991 struct intel_encoder *encoder = connector->encoder;
4992 struct drm_crtc *crtc;
4993 bool encoder_enabled;
4994 enum pipe pipe;
4995
4996 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4997 connector->base.base.id,
4998 connector->base.name);
4999
5000 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
5001 "wrong connector dpms state\n");
5002 WARN(connector->base.encoder != &encoder->base,
5003 "active connector not linked to encoder\n");
5004 WARN(!encoder->connectors_active,
5005 "encoder->connectors_active not set\n");
5006
5007 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
5008 WARN(!encoder_enabled, "encoder not enabled\n");
5009 if (WARN_ON(!encoder->base.crtc))
5010 return;
5011
5012 crtc = encoder->base.crtc;
5013
5014 WARN(!crtc->enabled, "crtc not enabled\n");
5015 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5016 WARN(pipe != to_intel_crtc(crtc)->pipe,
5017 "encoder active on the wrong pipe\n");
5018 }
5019 }
5020
5021 /* Even simpler default implementation, if there's really no special case to
5022 * consider. */
5023 void intel_connector_dpms(struct drm_connector *connector, int mode)
5024 {
5025 /* All the simple cases only support two dpms states. */
5026 if (mode != DRM_MODE_DPMS_ON)
5027 mode = DRM_MODE_DPMS_OFF;
5028
5029 if (mode == connector->dpms)
5030 return;
5031
5032 connector->dpms = mode;
5033
5034 /* Only need to change hw state when actually enabled */
5035 if (connector->encoder)
5036 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
5037
5038 intel_modeset_check_state(connector->dev);
5039 }
5040
5041 /* Simple connector->get_hw_state implementation for encoders that support only
5042 * one connector and no cloning and hence the encoder state determines the state
5043 * of the connector. */
5044 bool intel_connector_get_hw_state(struct intel_connector *connector)
5045 {
5046 enum pipe pipe = 0;
5047 struct intel_encoder *encoder = connector->encoder;
5048
5049 return encoder->get_hw_state(encoder, &pipe);
5050 }
5051
5052 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5053 struct intel_crtc_config *pipe_config)
5054 {
5055 struct drm_i915_private *dev_priv = dev->dev_private;
5056 struct intel_crtc *pipe_B_crtc =
5057 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5058
5059 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5060 pipe_name(pipe), pipe_config->fdi_lanes);
5061 if (pipe_config->fdi_lanes > 4) {
5062 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5063 pipe_name(pipe), pipe_config->fdi_lanes);
5064 return false;
5065 }
5066
5067 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
5068 if (pipe_config->fdi_lanes > 2) {
5069 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5070 pipe_config->fdi_lanes);
5071 return false;
5072 } else {
5073 return true;
5074 }
5075 }
5076
5077 if (INTEL_INFO(dev)->num_pipes == 2)
5078 return true;
5079
5080 /* Ivybridge 3 pipe is really complicated */
5081 switch (pipe) {
5082 case PIPE_A:
5083 return true;
5084 case PIPE_B:
5085 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5086 pipe_config->fdi_lanes > 2) {
5087 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5088 pipe_name(pipe), pipe_config->fdi_lanes);
5089 return false;
5090 }
5091 return true;
5092 case PIPE_C:
5093 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
5094 pipe_B_crtc->config.fdi_lanes <= 2) {
5095 if (pipe_config->fdi_lanes > 2) {
5096 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5097 pipe_name(pipe), pipe_config->fdi_lanes);
5098 return false;
5099 }
5100 } else {
5101 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5102 return false;
5103 }
5104 return true;
5105 default:
5106 BUG();
5107 }
5108 }
5109
5110 #define RETRY 1
5111 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5112 struct intel_crtc_config *pipe_config)
5113 {
5114 struct drm_device *dev = intel_crtc->base.dev;
5115 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5116 int lane, link_bw, fdi_dotclock;
5117 bool setup_ok, needs_recompute = false;
5118
5119 retry:
5120 /* FDI is a binary signal running at ~2.7GHz, encoding
5121 * each output octet as 10 bits. The actual frequency
5122 * is stored as a divider into a 100MHz clock, and the
5123 * mode pixel clock is stored in units of 1KHz.
5124 * Hence the bw of each lane in terms of the mode signal
5125 * is:
5126 */
5127 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5128
5129 fdi_dotclock = adjusted_mode->crtc_clock;
5130
5131 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
5132 pipe_config->pipe_bpp);
5133
5134 pipe_config->fdi_lanes = lane;
5135
5136 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
5137 link_bw, &pipe_config->fdi_m_n);
5138
5139 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5140 intel_crtc->pipe, pipe_config);
5141 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5142 pipe_config->pipe_bpp -= 2*3;
5143 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5144 pipe_config->pipe_bpp);
5145 needs_recompute = true;
5146 pipe_config->bw_constrained = true;
5147
5148 goto retry;
5149 }
5150
5151 if (needs_recompute)
5152 return RETRY;
5153
5154 return setup_ok ? 0 : -EINVAL;
5155 }
5156
5157 static void hsw_compute_ips_config(struct intel_crtc *crtc,
5158 struct intel_crtc_config *pipe_config)
5159 {
5160 pipe_config->ips_enabled = i915.enable_ips &&
5161 hsw_crtc_supports_ips(crtc) &&
5162 pipe_config->pipe_bpp <= 24;
5163 }
5164
5165 static int intel_crtc_compute_config(struct intel_crtc *crtc,
5166 struct intel_crtc_config *pipe_config)
5167 {
5168 struct drm_device *dev = crtc->base.dev;
5169 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
5170
5171 /* FIXME should check pixel clock limits on all platforms */
5172 if (INTEL_INFO(dev)->gen < 4) {
5173 struct drm_i915_private *dev_priv = dev->dev_private;
5174 int clock_limit =
5175 dev_priv->display.get_display_clock_speed(dev);
5176
5177 /*
5178 * Enable pixel doubling when the dot clock
5179 * is > 90% of the (display) core speed.
5180 *
5181 * GDG double wide on either pipe,
5182 * otherwise pipe A only.
5183 */
5184 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
5185 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
5186 clock_limit *= 2;
5187 pipe_config->double_wide = true;
5188 }
5189
5190 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
5191 return -EINVAL;
5192 }
5193
5194 /*
5195 * Pipe horizontal size must be even in:
5196 * - DVO ganged mode
5197 * - LVDS dual channel mode
5198 * - Double wide pipe
5199 */
5200 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5201 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5202 pipe_config->pipe_src_w &= ~1;
5203
5204 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5205 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
5206 */
5207 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5208 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
5209 return -EINVAL;
5210
5211 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5212 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
5213 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5214 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5215 * for lvds. */
5216 pipe_config->pipe_bpp = 8*3;
5217 }
5218
5219 if (HAS_IPS(dev))
5220 hsw_compute_ips_config(crtc, pipe_config);
5221
5222 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
5223 * clock survives for now. */
5224 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5225 pipe_config->shared_dpll = crtc->config.shared_dpll;
5226
5227 if (pipe_config->has_pch_encoder)
5228 return ironlake_fdi_compute_config(crtc, pipe_config);
5229
5230 return 0;
5231 }
5232
5233 static int valleyview_get_display_clock_speed(struct drm_device *dev)
5234 {
5235 return 400000; /* FIXME */
5236 }
5237
5238 static int i945_get_display_clock_speed(struct drm_device *dev)
5239 {
5240 return 400000;
5241 }
5242
5243 static int i915_get_display_clock_speed(struct drm_device *dev)
5244 {
5245 return 333000;
5246 }
5247
5248 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5249 {
5250 return 200000;
5251 }
5252
5253 static int pnv_get_display_clock_speed(struct drm_device *dev)
5254 {
5255 u16 gcfgc = 0;
5256
5257 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5258
5259 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5260 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5261 return 267000;
5262 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5263 return 333000;
5264 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5265 return 444000;
5266 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5267 return 200000;
5268 default:
5269 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5270 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5271 return 133000;
5272 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5273 return 167000;
5274 }
5275 }
5276
5277 static int i915gm_get_display_clock_speed(struct drm_device *dev)
5278 {
5279 u16 gcfgc = 0;
5280
5281 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5282
5283 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5284 return 133000;
5285 else {
5286 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5287 case GC_DISPLAY_CLOCK_333_MHZ:
5288 return 333000;
5289 default:
5290 case GC_DISPLAY_CLOCK_190_200_MHZ:
5291 return 190000;
5292 }
5293 }
5294 }
5295
5296 static int i865_get_display_clock_speed(struct drm_device *dev)
5297 {
5298 return 266000;
5299 }
5300
5301 static int i855_get_display_clock_speed(struct drm_device *dev)
5302 {
5303 u16 hpllcc = 0;
5304 /* Assume that the hardware is in the high speed state. This
5305 * should be the default.
5306 */
5307 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5308 case GC_CLOCK_133_200:
5309 case GC_CLOCK_100_200:
5310 return 200000;
5311 case GC_CLOCK_166_250:
5312 return 250000;
5313 case GC_CLOCK_100_133:
5314 return 133000;
5315 }
5316
5317 /* Shouldn't happen */
5318 return 0;
5319 }
5320
5321 static int i830_get_display_clock_speed(struct drm_device *dev)
5322 {
5323 return 133000;
5324 }
5325
5326 static void
5327 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
5328 {
5329 while (*num > DATA_LINK_M_N_MASK ||
5330 *den > DATA_LINK_M_N_MASK) {
5331 *num >>= 1;
5332 *den >>= 1;
5333 }
5334 }
5335
5336 static void compute_m_n(unsigned int m, unsigned int n,
5337 uint32_t *ret_m, uint32_t *ret_n)
5338 {
5339 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5340 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5341 intel_reduce_m_n_ratio(ret_m, ret_n);
5342 }
5343
5344 void
5345 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5346 int pixel_clock, int link_clock,
5347 struct intel_link_m_n *m_n)
5348 {
5349 m_n->tu = 64;
5350
5351 compute_m_n(bits_per_pixel * pixel_clock,
5352 link_clock * nlanes * 8,
5353 &m_n->gmch_m, &m_n->gmch_n);
5354
5355 compute_m_n(pixel_clock, link_clock,
5356 &m_n->link_m, &m_n->link_n);
5357 }
5358
5359 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5360 {
5361 if (i915.panel_use_ssc >= 0)
5362 return i915.panel_use_ssc != 0;
5363 return dev_priv->vbt.lvds_use_ssc
5364 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
5365 }
5366
5367 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5368 {
5369 struct drm_device *dev = crtc->dev;
5370 struct drm_i915_private *dev_priv = dev->dev_private;
5371 int refclk;
5372
5373 if (IS_VALLEYVIEW(dev)) {
5374 refclk = 100000;
5375 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5376 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5377 refclk = dev_priv->vbt.lvds_ssc_freq;
5378 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
5379 } else if (!IS_GEN2(dev)) {
5380 refclk = 96000;
5381 } else {
5382 refclk = 48000;
5383 }
5384
5385 return refclk;
5386 }
5387
5388 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
5389 {
5390 return (1 << dpll->n) << 16 | dpll->m2;
5391 }
5392
5393 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
5394 {
5395 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
5396 }
5397
5398 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
5399 intel_clock_t *reduced_clock)
5400 {
5401 struct drm_device *dev = crtc->base.dev;
5402 u32 fp, fp2 = 0;
5403
5404 if (IS_PINEVIEW(dev)) {
5405 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
5406 if (reduced_clock)
5407 fp2 = pnv_dpll_compute_fp(reduced_clock);
5408 } else {
5409 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
5410 if (reduced_clock)
5411 fp2 = i9xx_dpll_compute_fp(reduced_clock);
5412 }
5413
5414 crtc->config.dpll_hw_state.fp0 = fp;
5415
5416 crtc->lowfreq_avail = false;
5417 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5418 reduced_clock && i915.powersave) {
5419 crtc->config.dpll_hw_state.fp1 = fp2;
5420 crtc->lowfreq_avail = true;
5421 } else {
5422 crtc->config.dpll_hw_state.fp1 = fp;
5423 }
5424 }
5425
5426 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
5427 pipe)
5428 {
5429 u32 reg_val;
5430
5431 /*
5432 * PLLB opamp always calibrates to max value of 0x3f, force enable it
5433 * and set it to a reasonable value instead.
5434 */
5435 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5436 reg_val &= 0xffffff00;
5437 reg_val |= 0x00000030;
5438 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5439
5440 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5441 reg_val &= 0x8cffffff;
5442 reg_val = 0x8c000000;
5443 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5444
5445 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
5446 reg_val &= 0xffffff00;
5447 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
5448
5449 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
5450 reg_val &= 0x00ffffff;
5451 reg_val |= 0xb0000000;
5452 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
5453 }
5454
5455 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5456 struct intel_link_m_n *m_n)
5457 {
5458 struct drm_device *dev = crtc->base.dev;
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 int pipe = crtc->pipe;
5461
5462 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5463 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
5464 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
5465 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
5466 }
5467
5468 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5469 struct intel_link_m_n *m_n)
5470 {
5471 struct drm_device *dev = crtc->base.dev;
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 int pipe = crtc->pipe;
5474 enum transcoder transcoder = crtc->config.cpu_transcoder;
5475
5476 if (INTEL_INFO(dev)->gen >= 5) {
5477 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5478 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5479 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5480 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5481 } else {
5482 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5483 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
5484 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
5485 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
5486 }
5487 }
5488
5489 static void intel_dp_set_m_n(struct intel_crtc *crtc)
5490 {
5491 if (crtc->config.has_pch_encoder)
5492 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5493 else
5494 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
5495 }
5496
5497 static void vlv_update_pll(struct intel_crtc *crtc)
5498 {
5499 u32 dpll, dpll_md;
5500
5501 /*
5502 * Enable DPIO clock input. We should never disable the reference
5503 * clock for pipe B, since VGA hotplug / manual detection depends
5504 * on it.
5505 */
5506 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
5507 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
5508 /* We should never disable this, set it here for state tracking */
5509 if (crtc->pipe == PIPE_B)
5510 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5511 dpll |= DPLL_VCO_ENABLE;
5512 crtc->config.dpll_hw_state.dpll = dpll;
5513
5514 dpll_md = (crtc->config.pixel_multiplier - 1)
5515 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5516 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5517 }
5518
5519 static void vlv_prepare_pll(struct intel_crtc *crtc)
5520 {
5521 struct drm_device *dev = crtc->base.dev;
5522 struct drm_i915_private *dev_priv = dev->dev_private;
5523 int pipe = crtc->pipe;
5524 u32 mdiv;
5525 u32 bestn, bestm1, bestm2, bestp1, bestp2;
5526 u32 coreclk, reg_val;
5527
5528 mutex_lock(&dev_priv->dpio_lock);
5529
5530 bestn = crtc->config.dpll.n;
5531 bestm1 = crtc->config.dpll.m1;
5532 bestm2 = crtc->config.dpll.m2;
5533 bestp1 = crtc->config.dpll.p1;
5534 bestp2 = crtc->config.dpll.p2;
5535
5536 /* See eDP HDMI DPIO driver vbios notes doc */
5537
5538 /* PLL B needs special handling */
5539 if (pipe == PIPE_B)
5540 vlv_pllb_recal_opamp(dev_priv, pipe);
5541
5542 /* Set up Tx target for periodic Rcomp update */
5543 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
5544
5545 /* Disable target IRef on PLL */
5546 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
5547 reg_val &= 0x00ffffff;
5548 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
5549
5550 /* Disable fast lock */
5551 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
5552
5553 /* Set idtafcrecal before PLL is enabled */
5554 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
5555 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
5556 mdiv |= ((bestn << DPIO_N_SHIFT));
5557 mdiv |= (1 << DPIO_K_SHIFT);
5558
5559 /*
5560 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
5561 * but we don't support that).
5562 * Note: don't use the DAC post divider as it seems unstable.
5563 */
5564 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5565 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5566
5567 mdiv |= DPIO_ENABLE_CALIBRATION;
5568 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
5569
5570 /* Set HBR and RBR LPF coefficients */
5571 if (crtc->config.port_clock == 162000 ||
5572 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
5573 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5574 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5575 0x009f0003);
5576 else
5577 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
5578 0x00d0000f);
5579
5580 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
5581 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
5582 /* Use SSC source */
5583 if (pipe == PIPE_A)
5584 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5585 0x0df40000);
5586 else
5587 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5588 0x0df70000);
5589 } else { /* HDMI or VGA */
5590 /* Use bend source */
5591 if (pipe == PIPE_A)
5592 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5593 0x0df70000);
5594 else
5595 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
5596 0x0df40000);
5597 }
5598
5599 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
5600 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
5601 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
5602 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
5603 coreclk |= 0x01000000;
5604 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
5605
5606 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
5607 mutex_unlock(&dev_priv->dpio_lock);
5608 }
5609
5610 static void chv_update_pll(struct intel_crtc *crtc)
5611 {
5612 struct drm_device *dev = crtc->base.dev;
5613 struct drm_i915_private *dev_priv = dev->dev_private;
5614 int pipe = crtc->pipe;
5615 int dpll_reg = DPLL(crtc->pipe);
5616 enum dpio_channel port = vlv_pipe_to_channel(pipe);
5617 u32 loopfilter, intcoeff;
5618 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
5619 int refclk;
5620
5621 crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
5622 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
5623 DPLL_VCO_ENABLE;
5624 if (pipe != PIPE_A)
5625 crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
5626
5627 crtc->config.dpll_hw_state.dpll_md =
5628 (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5629
5630 bestn = crtc->config.dpll.n;
5631 bestm2_frac = crtc->config.dpll.m2 & 0x3fffff;
5632 bestm1 = crtc->config.dpll.m1;
5633 bestm2 = crtc->config.dpll.m2 >> 22;
5634 bestp1 = crtc->config.dpll.p1;
5635 bestp2 = crtc->config.dpll.p2;
5636
5637 /*
5638 * Enable Refclk and SSC
5639 */
5640 I915_WRITE(dpll_reg,
5641 crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
5642
5643 mutex_lock(&dev_priv->dpio_lock);
5644
5645 /* p1 and p2 divider */
5646 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
5647 5 << DPIO_CHV_S1_DIV_SHIFT |
5648 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
5649 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
5650 1 << DPIO_CHV_K_DIV_SHIFT);
5651
5652 /* Feedback post-divider - m2 */
5653 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
5654
5655 /* Feedback refclk divider - n and m1 */
5656 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
5657 DPIO_CHV_M1_DIV_BY_2 |
5658 1 << DPIO_CHV_N_DIV_SHIFT);
5659
5660 /* M2 fraction division */
5661 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
5662
5663 /* M2 fraction division enable */
5664 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port),
5665 DPIO_CHV_FRAC_DIV_EN |
5666 (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT));
5667
5668 /* Loop filter */
5669 refclk = i9xx_get_refclk(&crtc->base, 0);
5670 loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT |
5671 2 << DPIO_CHV_GAIN_CTRL_SHIFT;
5672 if (refclk == 100000)
5673 intcoeff = 11;
5674 else if (refclk == 38400)
5675 intcoeff = 10;
5676 else
5677 intcoeff = 9;
5678 loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT;
5679 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
5680
5681 /* AFC Recal */
5682 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
5683 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
5684 DPIO_AFC_RECAL);
5685
5686 mutex_unlock(&dev_priv->dpio_lock);
5687 }
5688
5689 static void i9xx_update_pll(struct intel_crtc *crtc,
5690 intel_clock_t *reduced_clock,
5691 int num_connectors)
5692 {
5693 struct drm_device *dev = crtc->base.dev;
5694 struct drm_i915_private *dev_priv = dev->dev_private;
5695 u32 dpll;
5696 bool is_sdvo;
5697 struct dpll *clock = &crtc->config.dpll;
5698
5699 i9xx_update_pll_dividers(crtc, reduced_clock);
5700
5701 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
5702 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
5703
5704 dpll = DPLL_VGA_MODE_DIS;
5705
5706 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
5707 dpll |= DPLLB_MODE_LVDS;
5708 else
5709 dpll |= DPLLB_MODE_DAC_SERIAL;
5710
5711 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5712 dpll |= (crtc->config.pixel_multiplier - 1)
5713 << SDVO_MULTIPLIER_SHIFT_HIRES;
5714 }
5715
5716 if (is_sdvo)
5717 dpll |= DPLL_SDVO_HIGH_SPEED;
5718
5719 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
5720 dpll |= DPLL_SDVO_HIGH_SPEED;
5721
5722 /* compute bitmask from p1 value */
5723 if (IS_PINEVIEW(dev))
5724 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
5725 else {
5726 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5727 if (IS_G4X(dev) && reduced_clock)
5728 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5729 }
5730 switch (clock->p2) {
5731 case 5:
5732 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5733 break;
5734 case 7:
5735 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5736 break;
5737 case 10:
5738 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5739 break;
5740 case 14:
5741 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5742 break;
5743 }
5744 if (INTEL_INFO(dev)->gen >= 4)
5745 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5746
5747 if (crtc->config.sdvo_tv_clock)
5748 dpll |= PLL_REF_INPUT_TVCLKINBC;
5749 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5750 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5751 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5752 else
5753 dpll |= PLL_REF_INPUT_DREFCLK;
5754
5755 dpll |= DPLL_VCO_ENABLE;
5756 crtc->config.dpll_hw_state.dpll = dpll;
5757
5758 if (INTEL_INFO(dev)->gen >= 4) {
5759 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
5760 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5761 crtc->config.dpll_hw_state.dpll_md = dpll_md;
5762 }
5763 }
5764
5765 static void i8xx_update_pll(struct intel_crtc *crtc,
5766 intel_clock_t *reduced_clock,
5767 int num_connectors)
5768 {
5769 struct drm_device *dev = crtc->base.dev;
5770 struct drm_i915_private *dev_priv = dev->dev_private;
5771 u32 dpll;
5772 struct dpll *clock = &crtc->config.dpll;
5773
5774 i9xx_update_pll_dividers(crtc, reduced_clock);
5775
5776 dpll = DPLL_VGA_MODE_DIS;
5777
5778 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
5779 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5780 } else {
5781 if (clock->p1 == 2)
5782 dpll |= PLL_P1_DIVIDE_BY_TWO;
5783 else
5784 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5785 if (clock->p2 == 4)
5786 dpll |= PLL_P2_DIVIDE_BY_4;
5787 }
5788
5789 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
5790 dpll |= DPLL_DVO_2X_MODE;
5791
5792 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
5793 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5794 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5795 else
5796 dpll |= PLL_REF_INPUT_DREFCLK;
5797
5798 dpll |= DPLL_VCO_ENABLE;
5799 crtc->config.dpll_hw_state.dpll = dpll;
5800 }
5801
5802 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
5803 {
5804 struct drm_device *dev = intel_crtc->base.dev;
5805 struct drm_i915_private *dev_priv = dev->dev_private;
5806 enum pipe pipe = intel_crtc->pipe;
5807 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5808 struct drm_display_mode *adjusted_mode =
5809 &intel_crtc->config.adjusted_mode;
5810 uint32_t crtc_vtotal, crtc_vblank_end;
5811 int vsyncshift = 0;
5812
5813 /* We need to be careful not to changed the adjusted mode, for otherwise
5814 * the hw state checker will get angry at the mismatch. */
5815 crtc_vtotal = adjusted_mode->crtc_vtotal;
5816 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
5817
5818 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5819 /* the chip adds 2 halflines automatically */
5820 crtc_vtotal -= 1;
5821 crtc_vblank_end -= 1;
5822
5823 if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5824 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
5825 else
5826 vsyncshift = adjusted_mode->crtc_hsync_start -
5827 adjusted_mode->crtc_htotal / 2;
5828 if (vsyncshift < 0)
5829 vsyncshift += adjusted_mode->crtc_htotal;
5830 }
5831
5832 if (INTEL_INFO(dev)->gen > 3)
5833 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
5834
5835 I915_WRITE(HTOTAL(cpu_transcoder),
5836 (adjusted_mode->crtc_hdisplay - 1) |
5837 ((adjusted_mode->crtc_htotal - 1) << 16));
5838 I915_WRITE(HBLANK(cpu_transcoder),
5839 (adjusted_mode->crtc_hblank_start - 1) |
5840 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5841 I915_WRITE(HSYNC(cpu_transcoder),
5842 (adjusted_mode->crtc_hsync_start - 1) |
5843 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5844
5845 I915_WRITE(VTOTAL(cpu_transcoder),
5846 (adjusted_mode->crtc_vdisplay - 1) |
5847 ((crtc_vtotal - 1) << 16));
5848 I915_WRITE(VBLANK(cpu_transcoder),
5849 (adjusted_mode->crtc_vblank_start - 1) |
5850 ((crtc_vblank_end - 1) << 16));
5851 I915_WRITE(VSYNC(cpu_transcoder),
5852 (adjusted_mode->crtc_vsync_start - 1) |
5853 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5854
5855 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
5856 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
5857 * documented on the DDI_FUNC_CTL register description, EDP Input Select
5858 * bits. */
5859 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
5860 (pipe == PIPE_B || pipe == PIPE_C))
5861 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
5862
5863 /* pipesrc controls the size that is scaled from, which should
5864 * always be the user's requested size.
5865 */
5866 I915_WRITE(PIPESRC(pipe),
5867 ((intel_crtc->config.pipe_src_w - 1) << 16) |
5868 (intel_crtc->config.pipe_src_h - 1));
5869 }
5870
5871 static void intel_get_pipe_timings(struct intel_crtc *crtc,
5872 struct intel_crtc_config *pipe_config)
5873 {
5874 struct drm_device *dev = crtc->base.dev;
5875 struct drm_i915_private *dev_priv = dev->dev_private;
5876 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
5877 uint32_t tmp;
5878
5879 tmp = I915_READ(HTOTAL(cpu_transcoder));
5880 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
5881 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
5882 tmp = I915_READ(HBLANK(cpu_transcoder));
5883 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
5884 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
5885 tmp = I915_READ(HSYNC(cpu_transcoder));
5886 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
5887 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
5888
5889 tmp = I915_READ(VTOTAL(cpu_transcoder));
5890 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
5891 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
5892 tmp = I915_READ(VBLANK(cpu_transcoder));
5893 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
5894 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
5895 tmp = I915_READ(VSYNC(cpu_transcoder));
5896 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
5897 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
5898
5899 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
5900 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
5901 pipe_config->adjusted_mode.crtc_vtotal += 1;
5902 pipe_config->adjusted_mode.crtc_vblank_end += 1;
5903 }
5904
5905 tmp = I915_READ(PIPESRC(crtc->pipe));
5906 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
5907 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
5908
5909 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
5910 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
5911 }
5912
5913 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5914 struct intel_crtc_config *pipe_config)
5915 {
5916 mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
5917 mode->htotal = pipe_config->adjusted_mode.crtc_htotal;
5918 mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
5919 mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
5920
5921 mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
5922 mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal;
5923 mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
5924 mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
5925
5926 mode->flags = pipe_config->adjusted_mode.flags;
5927
5928 mode->clock = pipe_config->adjusted_mode.crtc_clock;
5929 mode->flags |= pipe_config->adjusted_mode.flags;
5930 }
5931
5932 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
5933 {
5934 struct drm_device *dev = intel_crtc->base.dev;
5935 struct drm_i915_private *dev_priv = dev->dev_private;
5936 uint32_t pipeconf;
5937
5938 pipeconf = 0;
5939
5940 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5941 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5942 pipeconf |= PIPECONF_ENABLE;
5943
5944 if (intel_crtc->config.double_wide)
5945 pipeconf |= PIPECONF_DOUBLE_WIDE;
5946
5947 /* only g4x and later have fancy bpc/dither controls */
5948 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5949 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5950 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5951 pipeconf |= PIPECONF_DITHER_EN |
5952 PIPECONF_DITHER_TYPE_SP;
5953
5954 switch (intel_crtc->config.pipe_bpp) {
5955 case 18:
5956 pipeconf |= PIPECONF_6BPC;
5957 break;
5958 case 24:
5959 pipeconf |= PIPECONF_8BPC;
5960 break;
5961 case 30:
5962 pipeconf |= PIPECONF_10BPC;
5963 break;
5964 default:
5965 /* Case prevented by intel_choose_pipe_bpp_dither. */
5966 BUG();
5967 }
5968 }
5969
5970 if (HAS_PIPE_CXSR(dev)) {
5971 if (intel_crtc->lowfreq_avail) {
5972 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5973 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5974 } else {
5975 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5976 }
5977 }
5978
5979 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
5980 if (INTEL_INFO(dev)->gen < 4 ||
5981 intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO))
5982 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5983 else
5984 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
5985 } else
5986 pipeconf |= PIPECONF_PROGRESSIVE;
5987
5988 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5989 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
5990
5991 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5992 POSTING_READ(PIPECONF(intel_crtc->pipe));
5993 }
5994
5995 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5996 int x, int y,
5997 struct drm_framebuffer *fb)
5998 {
5999 struct drm_device *dev = crtc->dev;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6002 int refclk, num_connectors = 0;
6003 intel_clock_t clock, reduced_clock;
6004 bool ok, has_reduced_clock = false;
6005 bool is_lvds = false, is_dsi = false;
6006 struct intel_encoder *encoder;
6007 const intel_limit_t *limit;
6008
6009 for_each_encoder_on_crtc(dev, crtc, encoder) {
6010 switch (encoder->type) {
6011 case INTEL_OUTPUT_LVDS:
6012 is_lvds = true;
6013 break;
6014 case INTEL_OUTPUT_DSI:
6015 is_dsi = true;
6016 break;
6017 }
6018
6019 num_connectors++;
6020 }
6021
6022 if (is_dsi)
6023 return 0;
6024
6025 if (!intel_crtc->config.clock_set) {
6026 refclk = i9xx_get_refclk(crtc, num_connectors);
6027
6028 /*
6029 * Returns a set of divisors for the desired target clock with
6030 * the given refclk, or FALSE. The returned values represent
6031 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6032 * 2) / p1 / p2.
6033 */
6034 limit = intel_limit(crtc, refclk);
6035 ok = dev_priv->display.find_dpll(limit, crtc,
6036 intel_crtc->config.port_clock,
6037 refclk, NULL, &clock);
6038 if (!ok) {
6039 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6040 return -EINVAL;
6041 }
6042
6043 if (is_lvds && dev_priv->lvds_downclock_avail) {
6044 /*
6045 * Ensure we match the reduced clock's P to the target
6046 * clock. If the clocks don't match, we can't switch
6047 * the display clock by using the FP0/FP1. In such case
6048 * we will disable the LVDS downclock feature.
6049 */
6050 has_reduced_clock =
6051 dev_priv->display.find_dpll(limit, crtc,
6052 dev_priv->lvds_downclock,
6053 refclk, &clock,
6054 &reduced_clock);
6055 }
6056 /* Compat-code for transition, will disappear. */
6057 intel_crtc->config.dpll.n = clock.n;
6058 intel_crtc->config.dpll.m1 = clock.m1;
6059 intel_crtc->config.dpll.m2 = clock.m2;
6060 intel_crtc->config.dpll.p1 = clock.p1;
6061 intel_crtc->config.dpll.p2 = clock.p2;
6062 }
6063
6064 if (IS_GEN2(dev)) {
6065 i8xx_update_pll(intel_crtc,
6066 has_reduced_clock ? &reduced_clock : NULL,
6067 num_connectors);
6068 } else if (IS_CHERRYVIEW(dev)) {
6069 chv_update_pll(intel_crtc);
6070 } else if (IS_VALLEYVIEW(dev)) {
6071 vlv_update_pll(intel_crtc);
6072 } else {
6073 i9xx_update_pll(intel_crtc,
6074 has_reduced_clock ? &reduced_clock : NULL,
6075 num_connectors);
6076 }
6077
6078 return 0;
6079 }
6080
6081 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
6082 struct intel_crtc_config *pipe_config)
6083 {
6084 struct drm_device *dev = crtc->base.dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086 uint32_t tmp;
6087
6088 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6089 return;
6090
6091 tmp = I915_READ(PFIT_CONTROL);
6092 if (!(tmp & PFIT_ENABLE))
6093 return;
6094
6095 /* Check whether the pfit is attached to our pipe. */
6096 if (INTEL_INFO(dev)->gen < 4) {
6097 if (crtc->pipe != PIPE_B)
6098 return;
6099 } else {
6100 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6101 return;
6102 }
6103
6104 pipe_config->gmch_pfit.control = tmp;
6105 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6106 if (INTEL_INFO(dev)->gen < 5)
6107 pipe_config->gmch_pfit.lvds_border_bits =
6108 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6109 }
6110
6111 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
6112 struct intel_crtc_config *pipe_config)
6113 {
6114 struct drm_device *dev = crtc->base.dev;
6115 struct drm_i915_private *dev_priv = dev->dev_private;
6116 int pipe = pipe_config->cpu_transcoder;
6117 intel_clock_t clock;
6118 u32 mdiv;
6119 int refclk = 100000;
6120
6121 mutex_lock(&dev_priv->dpio_lock);
6122 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
6123 mutex_unlock(&dev_priv->dpio_lock);
6124
6125 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6126 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6127 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6128 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6129 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6130
6131 vlv_clock(refclk, &clock);
6132
6133 /* clock.dot is the fast clock */
6134 pipe_config->port_clock = clock.dot / 5;
6135 }
6136
6137 static void i9xx_get_plane_config(struct intel_crtc *crtc,
6138 struct intel_plane_config *plane_config)
6139 {
6140 struct drm_device *dev = crtc->base.dev;
6141 struct drm_i915_private *dev_priv = dev->dev_private;
6142 u32 val, base, offset;
6143 int pipe = crtc->pipe, plane = crtc->plane;
6144 int fourcc, pixel_format;
6145 int aligned_height;
6146
6147 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
6148 if (!crtc->base.primary->fb) {
6149 DRM_DEBUG_KMS("failed to alloc fb\n");
6150 return;
6151 }
6152
6153 val = I915_READ(DSPCNTR(plane));
6154
6155 if (INTEL_INFO(dev)->gen >= 4)
6156 if (val & DISPPLANE_TILED)
6157 plane_config->tiled = true;
6158
6159 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
6160 fourcc = intel_format_to_fourcc(pixel_format);
6161 crtc->base.primary->fb->pixel_format = fourcc;
6162 crtc->base.primary->fb->bits_per_pixel =
6163 drm_format_plane_cpp(fourcc, 0) * 8;
6164
6165 if (INTEL_INFO(dev)->gen >= 4) {
6166 if (plane_config->tiled)
6167 offset = I915_READ(DSPTILEOFF(plane));
6168 else
6169 offset = I915_READ(DSPLINOFF(plane));
6170 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6171 } else {
6172 base = I915_READ(DSPADDR(plane));
6173 }
6174 plane_config->base = base;
6175
6176 val = I915_READ(PIPESRC(pipe));
6177 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
6178 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
6179
6180 val = I915_READ(DSPSTRIDE(pipe));
6181 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
6182
6183 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
6184 plane_config->tiled);
6185
6186 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
6187 aligned_height, PAGE_SIZE);
6188
6189 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6190 pipe, plane, crtc->base.primary->fb->width,
6191 crtc->base.primary->fb->height,
6192 crtc->base.primary->fb->bits_per_pixel, base,
6193 crtc->base.primary->fb->pitches[0],
6194 plane_config->size);
6195
6196 }
6197
6198 static void chv_crtc_clock_get(struct intel_crtc *crtc,
6199 struct intel_crtc_config *pipe_config)
6200 {
6201 struct drm_device *dev = crtc->base.dev;
6202 struct drm_i915_private *dev_priv = dev->dev_private;
6203 int pipe = pipe_config->cpu_transcoder;
6204 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6205 intel_clock_t clock;
6206 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6207 int refclk = 100000;
6208
6209 mutex_lock(&dev_priv->dpio_lock);
6210 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6211 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6212 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6213 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6214 mutex_unlock(&dev_priv->dpio_lock);
6215
6216 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6217 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6218 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6219 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6220 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6221
6222 chv_clock(refclk, &clock);
6223
6224 /* clock.dot is the fast clock */
6225 pipe_config->port_clock = clock.dot / 5;
6226 }
6227
6228 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
6229 struct intel_crtc_config *pipe_config)
6230 {
6231 struct drm_device *dev = crtc->base.dev;
6232 struct drm_i915_private *dev_priv = dev->dev_private;
6233 uint32_t tmp;
6234
6235 if (!intel_display_power_enabled(dev_priv,
6236 POWER_DOMAIN_PIPE(crtc->pipe)))
6237 return false;
6238
6239 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
6240 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6241
6242 tmp = I915_READ(PIPECONF(crtc->pipe));
6243 if (!(tmp & PIPECONF_ENABLE))
6244 return false;
6245
6246 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6247 switch (tmp & PIPECONF_BPC_MASK) {
6248 case PIPECONF_6BPC:
6249 pipe_config->pipe_bpp = 18;
6250 break;
6251 case PIPECONF_8BPC:
6252 pipe_config->pipe_bpp = 24;
6253 break;
6254 case PIPECONF_10BPC:
6255 pipe_config->pipe_bpp = 30;
6256 break;
6257 default:
6258 break;
6259 }
6260 }
6261
6262 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
6263 pipe_config->limited_color_range = true;
6264
6265 if (INTEL_INFO(dev)->gen < 4)
6266 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
6267
6268 intel_get_pipe_timings(crtc, pipe_config);
6269
6270 i9xx_get_pfit_config(crtc, pipe_config);
6271
6272 if (INTEL_INFO(dev)->gen >= 4) {
6273 tmp = I915_READ(DPLL_MD(crtc->pipe));
6274 pipe_config->pixel_multiplier =
6275 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
6276 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
6277 pipe_config->dpll_hw_state.dpll_md = tmp;
6278 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
6279 tmp = I915_READ(DPLL(crtc->pipe));
6280 pipe_config->pixel_multiplier =
6281 ((tmp & SDVO_MULTIPLIER_MASK)
6282 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
6283 } else {
6284 /* Note that on i915G/GM the pixel multiplier is in the sdvo
6285 * port and will be fixed up in the encoder->get_config
6286 * function. */
6287 pipe_config->pixel_multiplier = 1;
6288 }
6289 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
6290 if (!IS_VALLEYVIEW(dev)) {
6291 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
6292 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
6293 } else {
6294 /* Mask out read-only status bits. */
6295 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
6296 DPLL_PORTC_READY_MASK |
6297 DPLL_PORTB_READY_MASK);
6298 }
6299
6300 if (IS_CHERRYVIEW(dev))
6301 chv_crtc_clock_get(crtc, pipe_config);
6302 else if (IS_VALLEYVIEW(dev))
6303 vlv_crtc_clock_get(crtc, pipe_config);
6304 else
6305 i9xx_crtc_clock_get(crtc, pipe_config);
6306
6307 return true;
6308 }
6309
6310 static void ironlake_init_pch_refclk(struct drm_device *dev)
6311 {
6312 struct drm_i915_private *dev_priv = dev->dev_private;
6313 struct drm_mode_config *mode_config = &dev->mode_config;
6314 struct intel_encoder *encoder;
6315 u32 val, final;
6316 bool has_lvds = false;
6317 bool has_cpu_edp = false;
6318 bool has_panel = false;
6319 bool has_ck505 = false;
6320 bool can_ssc = false;
6321
6322 /* We need to take the global config into account */
6323 list_for_each_entry(encoder, &mode_config->encoder_list,
6324 base.head) {
6325 switch (encoder->type) {
6326 case INTEL_OUTPUT_LVDS:
6327 has_panel = true;
6328 has_lvds = true;
6329 break;
6330 case INTEL_OUTPUT_EDP:
6331 has_panel = true;
6332 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
6333 has_cpu_edp = true;
6334 break;
6335 }
6336 }
6337
6338 if (HAS_PCH_IBX(dev)) {
6339 has_ck505 = dev_priv->vbt.display_clock_mode;
6340 can_ssc = has_ck505;
6341 } else {
6342 has_ck505 = false;
6343 can_ssc = true;
6344 }
6345
6346 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
6347 has_panel, has_lvds, has_ck505);
6348
6349 /* Ironlake: try to setup display ref clock before DPLL
6350 * enabling. This is only under driver's control after
6351 * PCH B stepping, previous chipset stepping should be
6352 * ignoring this setting.
6353 */
6354 val = I915_READ(PCH_DREF_CONTROL);
6355
6356 /* As we must carefully and slowly disable/enable each source in turn,
6357 * compute the final state we want first and check if we need to
6358 * make any changes at all.
6359 */
6360 final = val;
6361 final &= ~DREF_NONSPREAD_SOURCE_MASK;
6362 if (has_ck505)
6363 final |= DREF_NONSPREAD_CK505_ENABLE;
6364 else
6365 final |= DREF_NONSPREAD_SOURCE_ENABLE;
6366
6367 final &= ~DREF_SSC_SOURCE_MASK;
6368 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6369 final &= ~DREF_SSC1_ENABLE;
6370
6371 if (has_panel) {
6372 final |= DREF_SSC_SOURCE_ENABLE;
6373
6374 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6375 final |= DREF_SSC1_ENABLE;
6376
6377 if (has_cpu_edp) {
6378 if (intel_panel_use_ssc(dev_priv) && can_ssc)
6379 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6380 else
6381 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6382 } else
6383 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6384 } else {
6385 final |= DREF_SSC_SOURCE_DISABLE;
6386 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6387 }
6388
6389 if (final == val)
6390 return;
6391
6392 /* Always enable nonspread source */
6393 val &= ~DREF_NONSPREAD_SOURCE_MASK;
6394
6395 if (has_ck505)
6396 val |= DREF_NONSPREAD_CK505_ENABLE;
6397 else
6398 val |= DREF_NONSPREAD_SOURCE_ENABLE;
6399
6400 if (has_panel) {
6401 val &= ~DREF_SSC_SOURCE_MASK;
6402 val |= DREF_SSC_SOURCE_ENABLE;
6403
6404 /* SSC must be turned on before enabling the CPU output */
6405 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6406 DRM_DEBUG_KMS("Using SSC on panel\n");
6407 val |= DREF_SSC1_ENABLE;
6408 } else
6409 val &= ~DREF_SSC1_ENABLE;
6410
6411 /* Get SSC going before enabling the outputs */
6412 I915_WRITE(PCH_DREF_CONTROL, val);
6413 POSTING_READ(PCH_DREF_CONTROL);
6414 udelay(200);
6415
6416 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6417
6418 /* Enable CPU source on CPU attached eDP */
6419 if (has_cpu_edp) {
6420 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
6421 DRM_DEBUG_KMS("Using SSC on eDP\n");
6422 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
6423 } else
6424 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
6425 } else
6426 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6427
6428 I915_WRITE(PCH_DREF_CONTROL, val);
6429 POSTING_READ(PCH_DREF_CONTROL);
6430 udelay(200);
6431 } else {
6432 DRM_DEBUG_KMS("Disabling SSC entirely\n");
6433
6434 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
6435
6436 /* Turn off CPU output */
6437 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
6438
6439 I915_WRITE(PCH_DREF_CONTROL, val);
6440 POSTING_READ(PCH_DREF_CONTROL);
6441 udelay(200);
6442
6443 /* Turn off the SSC source */
6444 val &= ~DREF_SSC_SOURCE_MASK;
6445 val |= DREF_SSC_SOURCE_DISABLE;
6446
6447 /* Turn off SSC1 */
6448 val &= ~DREF_SSC1_ENABLE;
6449
6450 I915_WRITE(PCH_DREF_CONTROL, val);
6451 POSTING_READ(PCH_DREF_CONTROL);
6452 udelay(200);
6453 }
6454
6455 BUG_ON(val != final);
6456 }
6457
6458 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
6459 {
6460 uint32_t tmp;
6461
6462 tmp = I915_READ(SOUTH_CHICKEN2);
6463 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
6464 I915_WRITE(SOUTH_CHICKEN2, tmp);
6465
6466 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
6467 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
6468 DRM_ERROR("FDI mPHY reset assert timeout\n");
6469
6470 tmp = I915_READ(SOUTH_CHICKEN2);
6471 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
6472 I915_WRITE(SOUTH_CHICKEN2, tmp);
6473
6474 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
6475 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
6476 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
6477 }
6478
6479 /* WaMPhyProgramming:hsw */
6480 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
6481 {
6482 uint32_t tmp;
6483
6484 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
6485 tmp &= ~(0xFF << 24);
6486 tmp |= (0x12 << 24);
6487 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
6488
6489 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
6490 tmp |= (1 << 11);
6491 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
6492
6493 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
6494 tmp |= (1 << 11);
6495 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
6496
6497 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
6498 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6499 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
6500
6501 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
6502 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
6503 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
6504
6505 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
6506 tmp &= ~(7 << 13);
6507 tmp |= (5 << 13);
6508 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
6509
6510 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
6511 tmp &= ~(7 << 13);
6512 tmp |= (5 << 13);
6513 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
6514
6515 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
6516 tmp &= ~0xFF;
6517 tmp |= 0x1C;
6518 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
6519
6520 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
6521 tmp &= ~0xFF;
6522 tmp |= 0x1C;
6523 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
6524
6525 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
6526 tmp &= ~(0xFF << 16);
6527 tmp |= (0x1C << 16);
6528 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
6529
6530 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
6531 tmp &= ~(0xFF << 16);
6532 tmp |= (0x1C << 16);
6533 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
6534
6535 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
6536 tmp |= (1 << 27);
6537 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
6538
6539 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
6540 tmp |= (1 << 27);
6541 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
6542
6543 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
6544 tmp &= ~(0xF << 28);
6545 tmp |= (4 << 28);
6546 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
6547
6548 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
6549 tmp &= ~(0xF << 28);
6550 tmp |= (4 << 28);
6551 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
6552 }
6553
6554 /* Implements 3 different sequences from BSpec chapter "Display iCLK
6555 * Programming" based on the parameters passed:
6556 * - Sequence to enable CLKOUT_DP
6557 * - Sequence to enable CLKOUT_DP without spread
6558 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
6559 */
6560 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
6561 bool with_fdi)
6562 {
6563 struct drm_i915_private *dev_priv = dev->dev_private;
6564 uint32_t reg, tmp;
6565
6566 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
6567 with_spread = true;
6568 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
6569 with_fdi, "LP PCH doesn't have FDI\n"))
6570 with_fdi = false;
6571
6572 mutex_lock(&dev_priv->dpio_lock);
6573
6574 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6575 tmp &= ~SBI_SSCCTL_DISABLE;
6576 tmp |= SBI_SSCCTL_PATHALT;
6577 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6578
6579 udelay(24);
6580
6581 if (with_spread) {
6582 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6583 tmp &= ~SBI_SSCCTL_PATHALT;
6584 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6585
6586 if (with_fdi) {
6587 lpt_reset_fdi_mphy(dev_priv);
6588 lpt_program_fdi_mphy(dev_priv);
6589 }
6590 }
6591
6592 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6593 SBI_GEN0 : SBI_DBUFF0;
6594 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6595 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6596 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6597
6598 mutex_unlock(&dev_priv->dpio_lock);
6599 }
6600
6601 /* Sequence to disable CLKOUT_DP */
6602 static void lpt_disable_clkout_dp(struct drm_device *dev)
6603 {
6604 struct drm_i915_private *dev_priv = dev->dev_private;
6605 uint32_t reg, tmp;
6606
6607 mutex_lock(&dev_priv->dpio_lock);
6608
6609 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
6610 SBI_GEN0 : SBI_DBUFF0;
6611 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
6612 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
6613 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
6614
6615 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
6616 if (!(tmp & SBI_SSCCTL_DISABLE)) {
6617 if (!(tmp & SBI_SSCCTL_PATHALT)) {
6618 tmp |= SBI_SSCCTL_PATHALT;
6619 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6620 udelay(32);
6621 }
6622 tmp |= SBI_SSCCTL_DISABLE;
6623 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
6624 }
6625
6626 mutex_unlock(&dev_priv->dpio_lock);
6627 }
6628
6629 static void lpt_init_pch_refclk(struct drm_device *dev)
6630 {
6631 struct drm_mode_config *mode_config = &dev->mode_config;
6632 struct intel_encoder *encoder;
6633 bool has_vga = false;
6634
6635 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
6636 switch (encoder->type) {
6637 case INTEL_OUTPUT_ANALOG:
6638 has_vga = true;
6639 break;
6640 }
6641 }
6642
6643 if (has_vga)
6644 lpt_enable_clkout_dp(dev, true, true);
6645 else
6646 lpt_disable_clkout_dp(dev);
6647 }
6648
6649 /*
6650 * Initialize reference clocks when the driver loads
6651 */
6652 void intel_init_pch_refclk(struct drm_device *dev)
6653 {
6654 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
6655 ironlake_init_pch_refclk(dev);
6656 else if (HAS_PCH_LPT(dev))
6657 lpt_init_pch_refclk(dev);
6658 }
6659
6660 static int ironlake_get_refclk(struct drm_crtc *crtc)
6661 {
6662 struct drm_device *dev = crtc->dev;
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664 struct intel_encoder *encoder;
6665 int num_connectors = 0;
6666 bool is_lvds = false;
6667
6668 for_each_encoder_on_crtc(dev, crtc, encoder) {
6669 switch (encoder->type) {
6670 case INTEL_OUTPUT_LVDS:
6671 is_lvds = true;
6672 break;
6673 }
6674 num_connectors++;
6675 }
6676
6677 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
6678 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
6679 dev_priv->vbt.lvds_ssc_freq);
6680 return dev_priv->vbt.lvds_ssc_freq;
6681 }
6682
6683 return 120000;
6684 }
6685
6686 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
6687 {
6688 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
6689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6690 int pipe = intel_crtc->pipe;
6691 uint32_t val;
6692
6693 val = 0;
6694
6695 switch (intel_crtc->config.pipe_bpp) {
6696 case 18:
6697 val |= PIPECONF_6BPC;
6698 break;
6699 case 24:
6700 val |= PIPECONF_8BPC;
6701 break;
6702 case 30:
6703 val |= PIPECONF_10BPC;
6704 break;
6705 case 36:
6706 val |= PIPECONF_12BPC;
6707 break;
6708 default:
6709 /* Case prevented by intel_choose_pipe_bpp_dither. */
6710 BUG();
6711 }
6712
6713 if (intel_crtc->config.dither)
6714 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6715
6716 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6717 val |= PIPECONF_INTERLACED_ILK;
6718 else
6719 val |= PIPECONF_PROGRESSIVE;
6720
6721 if (intel_crtc->config.limited_color_range)
6722 val |= PIPECONF_COLOR_RANGE_SELECT;
6723
6724 I915_WRITE(PIPECONF(pipe), val);
6725 POSTING_READ(PIPECONF(pipe));
6726 }
6727
6728 /*
6729 * Set up the pipe CSC unit.
6730 *
6731 * Currently only full range RGB to limited range RGB conversion
6732 * is supported, but eventually this should handle various
6733 * RGB<->YCbCr scenarios as well.
6734 */
6735 static void intel_set_pipe_csc(struct drm_crtc *crtc)
6736 {
6737 struct drm_device *dev = crtc->dev;
6738 struct drm_i915_private *dev_priv = dev->dev_private;
6739 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6740 int pipe = intel_crtc->pipe;
6741 uint16_t coeff = 0x7800; /* 1.0 */
6742
6743 /*
6744 * TODO: Check what kind of values actually come out of the pipe
6745 * with these coeff/postoff values and adjust to get the best
6746 * accuracy. Perhaps we even need to take the bpc value into
6747 * consideration.
6748 */
6749
6750 if (intel_crtc->config.limited_color_range)
6751 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
6752
6753 /*
6754 * GY/GU and RY/RU should be the other way around according
6755 * to BSpec, but reality doesn't agree. Just set them up in
6756 * a way that results in the correct picture.
6757 */
6758 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
6759 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
6760
6761 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
6762 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
6763
6764 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
6765 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
6766
6767 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
6768 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
6769 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
6770
6771 if (INTEL_INFO(dev)->gen > 6) {
6772 uint16_t postoff = 0;
6773
6774 if (intel_crtc->config.limited_color_range)
6775 postoff = (16 * (1 << 12) / 255) & 0x1fff;
6776
6777 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
6778 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
6779 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
6780
6781 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
6782 } else {
6783 uint32_t mode = CSC_MODE_YUV_TO_RGB;
6784
6785 if (intel_crtc->config.limited_color_range)
6786 mode |= CSC_BLACK_SCREEN_OFFSET;
6787
6788 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
6789 }
6790 }
6791
6792 static void haswell_set_pipeconf(struct drm_crtc *crtc)
6793 {
6794 struct drm_device *dev = crtc->dev;
6795 struct drm_i915_private *dev_priv = dev->dev_private;
6796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6797 enum pipe pipe = intel_crtc->pipe;
6798 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
6799 uint32_t val;
6800
6801 val = 0;
6802
6803 if (IS_HASWELL(dev) && intel_crtc->config.dither)
6804 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
6805
6806 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
6807 val |= PIPECONF_INTERLACED_ILK;
6808 else
6809 val |= PIPECONF_PROGRESSIVE;
6810
6811 I915_WRITE(PIPECONF(cpu_transcoder), val);
6812 POSTING_READ(PIPECONF(cpu_transcoder));
6813
6814 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
6815 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
6816
6817 if (IS_BROADWELL(dev)) {
6818 val = 0;
6819
6820 switch (intel_crtc->config.pipe_bpp) {
6821 case 18:
6822 val |= PIPEMISC_DITHER_6_BPC;
6823 break;
6824 case 24:
6825 val |= PIPEMISC_DITHER_8_BPC;
6826 break;
6827 case 30:
6828 val |= PIPEMISC_DITHER_10_BPC;
6829 break;
6830 case 36:
6831 val |= PIPEMISC_DITHER_12_BPC;
6832 break;
6833 default:
6834 /* Case prevented by pipe_config_set_bpp. */
6835 BUG();
6836 }
6837
6838 if (intel_crtc->config.dither)
6839 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
6840
6841 I915_WRITE(PIPEMISC(pipe), val);
6842 }
6843 }
6844
6845 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6846 intel_clock_t *clock,
6847 bool *has_reduced_clock,
6848 intel_clock_t *reduced_clock)
6849 {
6850 struct drm_device *dev = crtc->dev;
6851 struct drm_i915_private *dev_priv = dev->dev_private;
6852 struct intel_encoder *intel_encoder;
6853 int refclk;
6854 const intel_limit_t *limit;
6855 bool ret, is_lvds = false;
6856
6857 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6858 switch (intel_encoder->type) {
6859 case INTEL_OUTPUT_LVDS:
6860 is_lvds = true;
6861 break;
6862 }
6863 }
6864
6865 refclk = ironlake_get_refclk(crtc);
6866
6867 /*
6868 * Returns a set of divisors for the desired target clock with the given
6869 * refclk, or FALSE. The returned values represent the clock equation:
6870 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
6871 */
6872 limit = intel_limit(crtc, refclk);
6873 ret = dev_priv->display.find_dpll(limit, crtc,
6874 to_intel_crtc(crtc)->config.port_clock,
6875 refclk, NULL, clock);
6876 if (!ret)
6877 return false;
6878
6879 if (is_lvds && dev_priv->lvds_downclock_avail) {
6880 /*
6881 * Ensure we match the reduced clock's P to the target clock.
6882 * If the clocks don't match, we can't switch the display clock
6883 * by using the FP0/FP1. In such case we will disable the LVDS
6884 * downclock feature.
6885 */
6886 *has_reduced_clock =
6887 dev_priv->display.find_dpll(limit, crtc,
6888 dev_priv->lvds_downclock,
6889 refclk, clock,
6890 reduced_clock);
6891 }
6892
6893 return true;
6894 }
6895
6896 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
6897 {
6898 /*
6899 * Account for spread spectrum to avoid
6900 * oversubscribing the link. Max center spread
6901 * is 2.5%; use 5% for safety's sake.
6902 */
6903 u32 bps = target_clock * bpp * 21 / 20;
6904 return DIV_ROUND_UP(bps, link_bw * 8);
6905 }
6906
6907 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6908 {
6909 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
6910 }
6911
6912 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
6913 u32 *fp,
6914 intel_clock_t *reduced_clock, u32 *fp2)
6915 {
6916 struct drm_crtc *crtc = &intel_crtc->base;
6917 struct drm_device *dev = crtc->dev;
6918 struct drm_i915_private *dev_priv = dev->dev_private;
6919 struct intel_encoder *intel_encoder;
6920 uint32_t dpll;
6921 int factor, num_connectors = 0;
6922 bool is_lvds = false, is_sdvo = false;
6923
6924 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
6925 switch (intel_encoder->type) {
6926 case INTEL_OUTPUT_LVDS:
6927 is_lvds = true;
6928 break;
6929 case INTEL_OUTPUT_SDVO:
6930 case INTEL_OUTPUT_HDMI:
6931 is_sdvo = true;
6932 break;
6933 }
6934
6935 num_connectors++;
6936 }
6937
6938 /* Enable autotuning of the PLL clock (if permissible) */
6939 factor = 21;
6940 if (is_lvds) {
6941 if ((intel_panel_use_ssc(dev_priv) &&
6942 dev_priv->vbt.lvds_ssc_freq == 100000) ||
6943 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
6944 factor = 25;
6945 } else if (intel_crtc->config.sdvo_tv_clock)
6946 factor = 20;
6947
6948 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
6949 *fp |= FP_CB_TUNE;
6950
6951 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
6952 *fp2 |= FP_CB_TUNE;
6953
6954 dpll = 0;
6955
6956 if (is_lvds)
6957 dpll |= DPLLB_MODE_LVDS;
6958 else
6959 dpll |= DPLLB_MODE_DAC_SERIAL;
6960
6961 dpll |= (intel_crtc->config.pixel_multiplier - 1)
6962 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
6963
6964 if (is_sdvo)
6965 dpll |= DPLL_SDVO_HIGH_SPEED;
6966 if (intel_crtc->config.has_dp_encoder)
6967 dpll |= DPLL_SDVO_HIGH_SPEED;
6968
6969 /* compute bitmask from p1 value */
6970 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6971 /* also FPA1 */
6972 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6973
6974 switch (intel_crtc->config.dpll.p2) {
6975 case 5:
6976 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6977 break;
6978 case 7:
6979 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6980 break;
6981 case 10:
6982 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6983 break;
6984 case 14:
6985 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6986 break;
6987 }
6988
6989 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6990 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6991 else
6992 dpll |= PLL_REF_INPUT_DREFCLK;
6993
6994 return dpll | DPLL_VCO_ENABLE;
6995 }
6996
6997 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
6998 int x, int y,
6999 struct drm_framebuffer *fb)
7000 {
7001 struct drm_device *dev = crtc->dev;
7002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7003 int num_connectors = 0;
7004 intel_clock_t clock, reduced_clock;
7005 u32 dpll = 0, fp = 0, fp2 = 0;
7006 bool ok, has_reduced_clock = false;
7007 bool is_lvds = false;
7008 struct intel_encoder *encoder;
7009 struct intel_shared_dpll *pll;
7010
7011 for_each_encoder_on_crtc(dev, crtc, encoder) {
7012 switch (encoder->type) {
7013 case INTEL_OUTPUT_LVDS:
7014 is_lvds = true;
7015 break;
7016 }
7017
7018 num_connectors++;
7019 }
7020
7021 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7022 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
7023
7024 ok = ironlake_compute_clocks(crtc, &clock,
7025 &has_reduced_clock, &reduced_clock);
7026 if (!ok && !intel_crtc->config.clock_set) {
7027 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7028 return -EINVAL;
7029 }
7030 /* Compat-code for transition, will disappear. */
7031 if (!intel_crtc->config.clock_set) {
7032 intel_crtc->config.dpll.n = clock.n;
7033 intel_crtc->config.dpll.m1 = clock.m1;
7034 intel_crtc->config.dpll.m2 = clock.m2;
7035 intel_crtc->config.dpll.p1 = clock.p1;
7036 intel_crtc->config.dpll.p2 = clock.p2;
7037 }
7038
7039 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
7040 if (intel_crtc->config.has_pch_encoder) {
7041 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
7042 if (has_reduced_clock)
7043 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
7044
7045 dpll = ironlake_compute_dpll(intel_crtc,
7046 &fp, &reduced_clock,
7047 has_reduced_clock ? &fp2 : NULL);
7048
7049 intel_crtc->config.dpll_hw_state.dpll = dpll;
7050 intel_crtc->config.dpll_hw_state.fp0 = fp;
7051 if (has_reduced_clock)
7052 intel_crtc->config.dpll_hw_state.fp1 = fp2;
7053 else
7054 intel_crtc->config.dpll_hw_state.fp1 = fp;
7055
7056 pll = intel_get_shared_dpll(intel_crtc);
7057 if (pll == NULL) {
7058 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
7059 pipe_name(intel_crtc->pipe));
7060 return -EINVAL;
7061 }
7062 } else
7063 intel_put_shared_dpll(intel_crtc);
7064
7065 if (is_lvds && has_reduced_clock && i915.powersave)
7066 intel_crtc->lowfreq_avail = true;
7067 else
7068 intel_crtc->lowfreq_avail = false;
7069
7070 return 0;
7071 }
7072
7073 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7074 struct intel_link_m_n *m_n)
7075 {
7076 struct drm_device *dev = crtc->base.dev;
7077 struct drm_i915_private *dev_priv = dev->dev_private;
7078 enum pipe pipe = crtc->pipe;
7079
7080 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7081 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7082 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7083 & ~TU_SIZE_MASK;
7084 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7085 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7086 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7087 }
7088
7089 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7090 enum transcoder transcoder,
7091 struct intel_link_m_n *m_n)
7092 {
7093 struct drm_device *dev = crtc->base.dev;
7094 struct drm_i915_private *dev_priv = dev->dev_private;
7095 enum pipe pipe = crtc->pipe;
7096
7097 if (INTEL_INFO(dev)->gen >= 5) {
7098 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7099 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7100 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7101 & ~TU_SIZE_MASK;
7102 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7103 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7104 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7105 } else {
7106 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7107 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7108 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7109 & ~TU_SIZE_MASK;
7110 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7111 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7112 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7113 }
7114 }
7115
7116 void intel_dp_get_m_n(struct intel_crtc *crtc,
7117 struct intel_crtc_config *pipe_config)
7118 {
7119 if (crtc->config.has_pch_encoder)
7120 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7121 else
7122 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7123 &pipe_config->dp_m_n);
7124 }
7125
7126 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
7127 struct intel_crtc_config *pipe_config)
7128 {
7129 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
7130 &pipe_config->fdi_m_n);
7131 }
7132
7133 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
7134 struct intel_crtc_config *pipe_config)
7135 {
7136 struct drm_device *dev = crtc->base.dev;
7137 struct drm_i915_private *dev_priv = dev->dev_private;
7138 uint32_t tmp;
7139
7140 tmp = I915_READ(PF_CTL(crtc->pipe));
7141
7142 if (tmp & PF_ENABLE) {
7143 pipe_config->pch_pfit.enabled = true;
7144 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
7145 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
7146
7147 /* We currently do not free assignements of panel fitters on
7148 * ivb/hsw (since we don't use the higher upscaling modes which
7149 * differentiates them) so just WARN about this case for now. */
7150 if (IS_GEN7(dev)) {
7151 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
7152 PF_PIPE_SEL_IVB(crtc->pipe));
7153 }
7154 }
7155 }
7156
7157 static void ironlake_get_plane_config(struct intel_crtc *crtc,
7158 struct intel_plane_config *plane_config)
7159 {
7160 struct drm_device *dev = crtc->base.dev;
7161 struct drm_i915_private *dev_priv = dev->dev_private;
7162 u32 val, base, offset;
7163 int pipe = crtc->pipe, plane = crtc->plane;
7164 int fourcc, pixel_format;
7165 int aligned_height;
7166
7167 crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL);
7168 if (!crtc->base.primary->fb) {
7169 DRM_DEBUG_KMS("failed to alloc fb\n");
7170 return;
7171 }
7172
7173 val = I915_READ(DSPCNTR(plane));
7174
7175 if (INTEL_INFO(dev)->gen >= 4)
7176 if (val & DISPPLANE_TILED)
7177 plane_config->tiled = true;
7178
7179 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
7180 fourcc = intel_format_to_fourcc(pixel_format);
7181 crtc->base.primary->fb->pixel_format = fourcc;
7182 crtc->base.primary->fb->bits_per_pixel =
7183 drm_format_plane_cpp(fourcc, 0) * 8;
7184
7185 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7186 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
7187 offset = I915_READ(DSPOFFSET(plane));
7188 } else {
7189 if (plane_config->tiled)
7190 offset = I915_READ(DSPTILEOFF(plane));
7191 else
7192 offset = I915_READ(DSPLINOFF(plane));
7193 }
7194 plane_config->base = base;
7195
7196 val = I915_READ(PIPESRC(pipe));
7197 crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1;
7198 crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1;
7199
7200 val = I915_READ(DSPSTRIDE(pipe));
7201 crtc->base.primary->fb->pitches[0] = val & 0xffffff80;
7202
7203 aligned_height = intel_align_height(dev, crtc->base.primary->fb->height,
7204 plane_config->tiled);
7205
7206 plane_config->size = ALIGN(crtc->base.primary->fb->pitches[0] *
7207 aligned_height, PAGE_SIZE);
7208
7209 DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7210 pipe, plane, crtc->base.primary->fb->width,
7211 crtc->base.primary->fb->height,
7212 crtc->base.primary->fb->bits_per_pixel, base,
7213 crtc->base.primary->fb->pitches[0],
7214 plane_config->size);
7215 }
7216
7217 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
7218 struct intel_crtc_config *pipe_config)
7219 {
7220 struct drm_device *dev = crtc->base.dev;
7221 struct drm_i915_private *dev_priv = dev->dev_private;
7222 uint32_t tmp;
7223
7224 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7225 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7226
7227 tmp = I915_READ(PIPECONF(crtc->pipe));
7228 if (!(tmp & PIPECONF_ENABLE))
7229 return false;
7230
7231 switch (tmp & PIPECONF_BPC_MASK) {
7232 case PIPECONF_6BPC:
7233 pipe_config->pipe_bpp = 18;
7234 break;
7235 case PIPECONF_8BPC:
7236 pipe_config->pipe_bpp = 24;
7237 break;
7238 case PIPECONF_10BPC:
7239 pipe_config->pipe_bpp = 30;
7240 break;
7241 case PIPECONF_12BPC:
7242 pipe_config->pipe_bpp = 36;
7243 break;
7244 default:
7245 break;
7246 }
7247
7248 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
7249 pipe_config->limited_color_range = true;
7250
7251 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
7252 struct intel_shared_dpll *pll;
7253
7254 pipe_config->has_pch_encoder = true;
7255
7256 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
7257 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7258 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7259
7260 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7261
7262 if (HAS_PCH_IBX(dev_priv->dev)) {
7263 pipe_config->shared_dpll =
7264 (enum intel_dpll_id) crtc->pipe;
7265 } else {
7266 tmp = I915_READ(PCH_DPLL_SEL);
7267 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
7268 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
7269 else
7270 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
7271 }
7272
7273 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
7274
7275 WARN_ON(!pll->get_hw_state(dev_priv, pll,
7276 &pipe_config->dpll_hw_state));
7277
7278 tmp = pipe_config->dpll_hw_state.dpll;
7279 pipe_config->pixel_multiplier =
7280 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
7281 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
7282
7283 ironlake_pch_clock_get(crtc, pipe_config);
7284 } else {
7285 pipe_config->pixel_multiplier = 1;
7286 }
7287
7288 intel_get_pipe_timings(crtc, pipe_config);
7289
7290 ironlake_get_pfit_config(crtc, pipe_config);
7291
7292 return true;
7293 }
7294
7295 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
7296 {
7297 struct drm_device *dev = dev_priv->dev;
7298 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
7299 struct intel_crtc *crtc;
7300
7301 for_each_intel_crtc(dev, crtc)
7302 WARN(crtc->active, "CRTC for pipe %c enabled\n",
7303 pipe_name(crtc->pipe));
7304
7305 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
7306 WARN(plls->spll_refcount, "SPLL enabled\n");
7307 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
7308 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
7309 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
7310 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
7311 "CPU PWM1 enabled\n");
7312 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
7313 "CPU PWM2 enabled\n");
7314 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
7315 "PCH PWM1 enabled\n");
7316 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
7317 "Utility pin enabled\n");
7318 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
7319
7320 /*
7321 * In theory we can still leave IRQs enabled, as long as only the HPD
7322 * interrupts remain enabled. We used to check for that, but since it's
7323 * gen-specific and since we only disable LCPLL after we fully disable
7324 * the interrupts, the check below should be enough.
7325 */
7326 WARN(!dev_priv->pm.irqs_disabled, "IRQs enabled\n");
7327 }
7328
7329 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
7330 {
7331 struct drm_device *dev = dev_priv->dev;
7332
7333 if (IS_HASWELL(dev)) {
7334 mutex_lock(&dev_priv->rps.hw_lock);
7335 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
7336 val))
7337 DRM_ERROR("Failed to disable D_COMP\n");
7338 mutex_unlock(&dev_priv->rps.hw_lock);
7339 } else {
7340 I915_WRITE(D_COMP, val);
7341 }
7342 POSTING_READ(D_COMP);
7343 }
7344
7345 /*
7346 * This function implements pieces of two sequences from BSpec:
7347 * - Sequence for display software to disable LCPLL
7348 * - Sequence for display software to allow package C8+
7349 * The steps implemented here are just the steps that actually touch the LCPLL
7350 * register. Callers should take care of disabling all the display engine
7351 * functions, doing the mode unset, fixing interrupts, etc.
7352 */
7353 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
7354 bool switch_to_fclk, bool allow_power_down)
7355 {
7356 uint32_t val;
7357
7358 assert_can_disable_lcpll(dev_priv);
7359
7360 val = I915_READ(LCPLL_CTL);
7361
7362 if (switch_to_fclk) {
7363 val |= LCPLL_CD_SOURCE_FCLK;
7364 I915_WRITE(LCPLL_CTL, val);
7365
7366 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
7367 LCPLL_CD_SOURCE_FCLK_DONE, 1))
7368 DRM_ERROR("Switching to FCLK failed\n");
7369
7370 val = I915_READ(LCPLL_CTL);
7371 }
7372
7373 val |= LCPLL_PLL_DISABLE;
7374 I915_WRITE(LCPLL_CTL, val);
7375 POSTING_READ(LCPLL_CTL);
7376
7377 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
7378 DRM_ERROR("LCPLL still locked\n");
7379
7380 val = I915_READ(D_COMP);
7381 val |= D_COMP_COMP_DISABLE;
7382 hsw_write_dcomp(dev_priv, val);
7383 ndelay(100);
7384
7385 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
7386 DRM_ERROR("D_COMP RCOMP still in progress\n");
7387
7388 if (allow_power_down) {
7389 val = I915_READ(LCPLL_CTL);
7390 val |= LCPLL_POWER_DOWN_ALLOW;
7391 I915_WRITE(LCPLL_CTL, val);
7392 POSTING_READ(LCPLL_CTL);
7393 }
7394 }
7395
7396 /*
7397 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
7398 * source.
7399 */
7400 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
7401 {
7402 uint32_t val;
7403 unsigned long irqflags;
7404
7405 val = I915_READ(LCPLL_CTL);
7406
7407 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
7408 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
7409 return;
7410
7411 /*
7412 * Make sure we're not on PC8 state before disabling PC8, otherwise
7413 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
7414 *
7415 * The other problem is that hsw_restore_lcpll() is called as part of
7416 * the runtime PM resume sequence, so we can't just call
7417 * gen6_gt_force_wake_get() because that function calls
7418 * intel_runtime_pm_get(), and we can't change the runtime PM refcount
7419 * while we are on the resume sequence. So to solve this problem we have
7420 * to call special forcewake code that doesn't touch runtime PM and
7421 * doesn't enable the forcewake delayed work.
7422 */
7423 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7424 if (dev_priv->uncore.forcewake_count++ == 0)
7425 dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL);
7426 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7427
7428 if (val & LCPLL_POWER_DOWN_ALLOW) {
7429 val &= ~LCPLL_POWER_DOWN_ALLOW;
7430 I915_WRITE(LCPLL_CTL, val);
7431 POSTING_READ(LCPLL_CTL);
7432 }
7433
7434 val = I915_READ(D_COMP);
7435 val |= D_COMP_COMP_FORCE;
7436 val &= ~D_COMP_COMP_DISABLE;
7437 hsw_write_dcomp(dev_priv, val);
7438
7439 val = I915_READ(LCPLL_CTL);
7440 val &= ~LCPLL_PLL_DISABLE;
7441 I915_WRITE(LCPLL_CTL, val);
7442
7443 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
7444 DRM_ERROR("LCPLL not locked yet\n");
7445
7446 if (val & LCPLL_CD_SOURCE_FCLK) {
7447 val = I915_READ(LCPLL_CTL);
7448 val &= ~LCPLL_CD_SOURCE_FCLK;
7449 I915_WRITE(LCPLL_CTL, val);
7450
7451 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
7452 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
7453 DRM_ERROR("Switching back to LCPLL failed\n");
7454 }
7455
7456 /* See the big comment above. */
7457 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
7458 if (--dev_priv->uncore.forcewake_count == 0)
7459 dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL);
7460 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
7461 }
7462
7463 /*
7464 * Package states C8 and deeper are really deep PC states that can only be
7465 * reached when all the devices on the system allow it, so even if the graphics
7466 * device allows PC8+, it doesn't mean the system will actually get to these
7467 * states. Our driver only allows PC8+ when going into runtime PM.
7468 *
7469 * The requirements for PC8+ are that all the outputs are disabled, the power
7470 * well is disabled and most interrupts are disabled, and these are also
7471 * requirements for runtime PM. When these conditions are met, we manually do
7472 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
7473 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
7474 * hang the machine.
7475 *
7476 * When we really reach PC8 or deeper states (not just when we allow it) we lose
7477 * the state of some registers, so when we come back from PC8+ we need to
7478 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
7479 * need to take care of the registers kept by RC6. Notice that this happens even
7480 * if we don't put the device in PCI D3 state (which is what currently happens
7481 * because of the runtime PM support).
7482 *
7483 * For more, read "Display Sequences for Package C8" on the hardware
7484 * documentation.
7485 */
7486 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
7487 {
7488 struct drm_device *dev = dev_priv->dev;
7489 uint32_t val;
7490
7491 DRM_DEBUG_KMS("Enabling package C8+\n");
7492
7493 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7494 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7495 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7496 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7497 }
7498
7499 lpt_disable_clkout_dp(dev);
7500 hsw_disable_lcpll(dev_priv, true, true);
7501 }
7502
7503 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
7504 {
7505 struct drm_device *dev = dev_priv->dev;
7506 uint32_t val;
7507
7508 DRM_DEBUG_KMS("Disabling package C8+\n");
7509
7510 hsw_restore_lcpll(dev_priv);
7511 lpt_init_pch_refclk(dev);
7512
7513 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
7514 val = I915_READ(SOUTH_DSPCLK_GATE_D);
7515 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
7516 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7517 }
7518
7519 intel_prepare_ddi(dev);
7520 }
7521
7522 static void snb_modeset_global_resources(struct drm_device *dev)
7523 {
7524 modeset_update_crtc_power_domains(dev);
7525 }
7526
7527 static void haswell_modeset_global_resources(struct drm_device *dev)
7528 {
7529 modeset_update_crtc_power_domains(dev);
7530 }
7531
7532 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
7533 int x, int y,
7534 struct drm_framebuffer *fb)
7535 {
7536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7537
7538 if (!intel_ddi_pll_select(intel_crtc))
7539 return -EINVAL;
7540 intel_ddi_pll_enable(intel_crtc);
7541
7542 intel_crtc->lowfreq_avail = false;
7543
7544 return 0;
7545 }
7546
7547 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
7548 struct intel_crtc_config *pipe_config)
7549 {
7550 struct drm_device *dev = crtc->base.dev;
7551 struct drm_i915_private *dev_priv = dev->dev_private;
7552 enum intel_display_power_domain pfit_domain;
7553 uint32_t tmp;
7554
7555 if (!intel_display_power_enabled(dev_priv,
7556 POWER_DOMAIN_PIPE(crtc->pipe)))
7557 return false;
7558
7559 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
7560 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7561
7562 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
7563 if (tmp & TRANS_DDI_FUNC_ENABLE) {
7564 enum pipe trans_edp_pipe;
7565 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
7566 default:
7567 WARN(1, "unknown pipe linked to edp transcoder\n");
7568 case TRANS_DDI_EDP_INPUT_A_ONOFF:
7569 case TRANS_DDI_EDP_INPUT_A_ON:
7570 trans_edp_pipe = PIPE_A;
7571 break;
7572 case TRANS_DDI_EDP_INPUT_B_ONOFF:
7573 trans_edp_pipe = PIPE_B;
7574 break;
7575 case TRANS_DDI_EDP_INPUT_C_ONOFF:
7576 trans_edp_pipe = PIPE_C;
7577 break;
7578 }
7579
7580 if (trans_edp_pipe == crtc->pipe)
7581 pipe_config->cpu_transcoder = TRANSCODER_EDP;
7582 }
7583
7584 if (!intel_display_power_enabled(dev_priv,
7585 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
7586 return false;
7587
7588 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
7589 if (!(tmp & PIPECONF_ENABLE))
7590 return false;
7591
7592 /*
7593 * Haswell has only FDI/PCH transcoder A. It is which is connected to
7594 * DDI E. So just check whether this pipe is wired to DDI E and whether
7595 * the PCH transcoder is on.
7596 */
7597 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
7598 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
7599 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
7600 pipe_config->has_pch_encoder = true;
7601
7602 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
7603 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
7604 FDI_DP_PORT_WIDTH_SHIFT) + 1;
7605
7606 ironlake_get_fdi_m_n_config(crtc, pipe_config);
7607 }
7608
7609 intel_get_pipe_timings(crtc, pipe_config);
7610
7611 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
7612 if (intel_display_power_enabled(dev_priv, pfit_domain))
7613 ironlake_get_pfit_config(crtc, pipe_config);
7614
7615 if (IS_HASWELL(dev))
7616 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
7617 (I915_READ(IPS_CTL) & IPS_ENABLE);
7618
7619 pipe_config->pixel_multiplier = 1;
7620
7621 return true;
7622 }
7623
7624 static struct {
7625 int clock;
7626 u32 config;
7627 } hdmi_audio_clock[] = {
7628 { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 },
7629 { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */
7630 { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 },
7631 { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 },
7632 { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 },
7633 { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 },
7634 { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 },
7635 { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 },
7636 { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 },
7637 { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 },
7638 };
7639
7640 /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */
7641 static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode)
7642 {
7643 int i;
7644
7645 for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) {
7646 if (mode->clock == hdmi_audio_clock[i].clock)
7647 break;
7648 }
7649
7650 if (i == ARRAY_SIZE(hdmi_audio_clock)) {
7651 DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock);
7652 i = 1;
7653 }
7654
7655 DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n",
7656 hdmi_audio_clock[i].clock,
7657 hdmi_audio_clock[i].config);
7658
7659 return hdmi_audio_clock[i].config;
7660 }
7661
7662 static bool intel_eld_uptodate(struct drm_connector *connector,
7663 int reg_eldv, uint32_t bits_eldv,
7664 int reg_elda, uint32_t bits_elda,
7665 int reg_edid)
7666 {
7667 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7668 uint8_t *eld = connector->eld;
7669 uint32_t i;
7670
7671 i = I915_READ(reg_eldv);
7672 i &= bits_eldv;
7673
7674 if (!eld[0])
7675 return !i;
7676
7677 if (!i)
7678 return false;
7679
7680 i = I915_READ(reg_elda);
7681 i &= ~bits_elda;
7682 I915_WRITE(reg_elda, i);
7683
7684 for (i = 0; i < eld[2]; i++)
7685 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
7686 return false;
7687
7688 return true;
7689 }
7690
7691 static void g4x_write_eld(struct drm_connector *connector,
7692 struct drm_crtc *crtc,
7693 struct drm_display_mode *mode)
7694 {
7695 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7696 uint8_t *eld = connector->eld;
7697 uint32_t eldv;
7698 uint32_t len;
7699 uint32_t i;
7700
7701 i = I915_READ(G4X_AUD_VID_DID);
7702
7703 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
7704 eldv = G4X_ELDV_DEVCL_DEVBLC;
7705 else
7706 eldv = G4X_ELDV_DEVCTG;
7707
7708 if (intel_eld_uptodate(connector,
7709 G4X_AUD_CNTL_ST, eldv,
7710 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
7711 G4X_HDMIW_HDMIEDID))
7712 return;
7713
7714 i = I915_READ(G4X_AUD_CNTL_ST);
7715 i &= ~(eldv | G4X_ELD_ADDR);
7716 len = (i >> 9) & 0x1f; /* ELD buffer size */
7717 I915_WRITE(G4X_AUD_CNTL_ST, i);
7718
7719 if (!eld[0])
7720 return;
7721
7722 len = min_t(uint8_t, eld[2], len);
7723 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7724 for (i = 0; i < len; i++)
7725 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
7726
7727 i = I915_READ(G4X_AUD_CNTL_ST);
7728 i |= eldv;
7729 I915_WRITE(G4X_AUD_CNTL_ST, i);
7730 }
7731
7732 static void haswell_write_eld(struct drm_connector *connector,
7733 struct drm_crtc *crtc,
7734 struct drm_display_mode *mode)
7735 {
7736 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7737 uint8_t *eld = connector->eld;
7738 uint32_t eldv;
7739 uint32_t i;
7740 int len;
7741 int pipe = to_intel_crtc(crtc)->pipe;
7742 int tmp;
7743
7744 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
7745 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
7746 int aud_config = HSW_AUD_CFG(pipe);
7747 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
7748
7749 /* Audio output enable */
7750 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
7751 tmp = I915_READ(aud_cntrl_st2);
7752 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
7753 I915_WRITE(aud_cntrl_st2, tmp);
7754 POSTING_READ(aud_cntrl_st2);
7755
7756 assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
7757
7758 /* Set ELD valid state */
7759 tmp = I915_READ(aud_cntrl_st2);
7760 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
7761 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
7762 I915_WRITE(aud_cntrl_st2, tmp);
7763 tmp = I915_READ(aud_cntrl_st2);
7764 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
7765
7766 /* Enable HDMI mode */
7767 tmp = I915_READ(aud_config);
7768 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
7769 /* clear N_programing_enable and N_value_index */
7770 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
7771 I915_WRITE(aud_config, tmp);
7772
7773 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7774
7775 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7776
7777 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7778 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7779 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7780 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7781 } else {
7782 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7783 }
7784
7785 if (intel_eld_uptodate(connector,
7786 aud_cntrl_st2, eldv,
7787 aud_cntl_st, IBX_ELD_ADDRESS,
7788 hdmiw_hdmiedid))
7789 return;
7790
7791 i = I915_READ(aud_cntrl_st2);
7792 i &= ~eldv;
7793 I915_WRITE(aud_cntrl_st2, i);
7794
7795 if (!eld[0])
7796 return;
7797
7798 i = I915_READ(aud_cntl_st);
7799 i &= ~IBX_ELD_ADDRESS;
7800 I915_WRITE(aud_cntl_st, i);
7801 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
7802 DRM_DEBUG_DRIVER("port num:%d\n", i);
7803
7804 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7805 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7806 for (i = 0; i < len; i++)
7807 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7808
7809 i = I915_READ(aud_cntrl_st2);
7810 i |= eldv;
7811 I915_WRITE(aud_cntrl_st2, i);
7812
7813 }
7814
7815 static void ironlake_write_eld(struct drm_connector *connector,
7816 struct drm_crtc *crtc,
7817 struct drm_display_mode *mode)
7818 {
7819 struct drm_i915_private *dev_priv = connector->dev->dev_private;
7820 uint8_t *eld = connector->eld;
7821 uint32_t eldv;
7822 uint32_t i;
7823 int len;
7824 int hdmiw_hdmiedid;
7825 int aud_config;
7826 int aud_cntl_st;
7827 int aud_cntrl_st2;
7828 int pipe = to_intel_crtc(crtc)->pipe;
7829
7830 if (HAS_PCH_IBX(connector->dev)) {
7831 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
7832 aud_config = IBX_AUD_CFG(pipe);
7833 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
7834 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
7835 } else if (IS_VALLEYVIEW(connector->dev)) {
7836 hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe);
7837 aud_config = VLV_AUD_CFG(pipe);
7838 aud_cntl_st = VLV_AUD_CNTL_ST(pipe);
7839 aud_cntrl_st2 = VLV_AUD_CNTL_ST2;
7840 } else {
7841 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
7842 aud_config = CPT_AUD_CFG(pipe);
7843 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
7844 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
7845 }
7846
7847 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
7848
7849 if (IS_VALLEYVIEW(connector->dev)) {
7850 struct intel_encoder *intel_encoder;
7851 struct intel_digital_port *intel_dig_port;
7852
7853 intel_encoder = intel_attached_encoder(connector);
7854 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
7855 i = intel_dig_port->port;
7856 } else {
7857 i = I915_READ(aud_cntl_st);
7858 i = (i >> 29) & DIP_PORT_SEL_MASK;
7859 /* DIP_Port_Select, 0x1 = PortB */
7860 }
7861
7862 if (!i) {
7863 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
7864 /* operate blindly on all ports */
7865 eldv = IBX_ELD_VALIDB;
7866 eldv |= IBX_ELD_VALIDB << 4;
7867 eldv |= IBX_ELD_VALIDB << 8;
7868 } else {
7869 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
7870 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
7871 }
7872
7873 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
7874 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
7875 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
7876 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
7877 } else {
7878 I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode));
7879 }
7880
7881 if (intel_eld_uptodate(connector,
7882 aud_cntrl_st2, eldv,
7883 aud_cntl_st, IBX_ELD_ADDRESS,
7884 hdmiw_hdmiedid))
7885 return;
7886
7887 i = I915_READ(aud_cntrl_st2);
7888 i &= ~eldv;
7889 I915_WRITE(aud_cntrl_st2, i);
7890
7891 if (!eld[0])
7892 return;
7893
7894 i = I915_READ(aud_cntl_st);
7895 i &= ~IBX_ELD_ADDRESS;
7896 I915_WRITE(aud_cntl_st, i);
7897
7898 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
7899 DRM_DEBUG_DRIVER("ELD size %d\n", len);
7900 for (i = 0; i < len; i++)
7901 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
7902
7903 i = I915_READ(aud_cntrl_st2);
7904 i |= eldv;
7905 I915_WRITE(aud_cntrl_st2, i);
7906 }
7907
7908 void intel_write_eld(struct drm_encoder *encoder,
7909 struct drm_display_mode *mode)
7910 {
7911 struct drm_crtc *crtc = encoder->crtc;
7912 struct drm_connector *connector;
7913 struct drm_device *dev = encoder->dev;
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915
7916 connector = drm_select_eld(encoder, mode);
7917 if (!connector)
7918 return;
7919
7920 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7921 connector->base.id,
7922 connector->name,
7923 connector->encoder->base.id,
7924 connector->encoder->name);
7925
7926 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
7927
7928 if (dev_priv->display.write_eld)
7929 dev_priv->display.write_eld(connector, crtc, mode);
7930 }
7931
7932 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
7933 {
7934 struct drm_device *dev = crtc->dev;
7935 struct drm_i915_private *dev_priv = dev->dev_private;
7936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7937 uint32_t cntl;
7938
7939 if (base != intel_crtc->cursor_base) {
7940 /* On these chipsets we can only modify the base whilst
7941 * the cursor is disabled.
7942 */
7943 if (intel_crtc->cursor_cntl) {
7944 I915_WRITE(_CURACNTR, 0);
7945 POSTING_READ(_CURACNTR);
7946 intel_crtc->cursor_cntl = 0;
7947 }
7948
7949 I915_WRITE(_CURABASE, base);
7950 POSTING_READ(_CURABASE);
7951 }
7952
7953 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7954 cntl = 0;
7955 if (base)
7956 cntl = (CURSOR_ENABLE |
7957 CURSOR_GAMMA_ENABLE |
7958 CURSOR_FORMAT_ARGB);
7959 if (intel_crtc->cursor_cntl != cntl) {
7960 I915_WRITE(_CURACNTR, cntl);
7961 POSTING_READ(_CURACNTR);
7962 intel_crtc->cursor_cntl = cntl;
7963 }
7964 }
7965
7966 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7967 {
7968 struct drm_device *dev = crtc->dev;
7969 struct drm_i915_private *dev_priv = dev->dev_private;
7970 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7971 int pipe = intel_crtc->pipe;
7972 uint32_t cntl;
7973
7974 cntl = 0;
7975 if (base) {
7976 cntl = MCURSOR_GAMMA_ENABLE;
7977 switch (intel_crtc->cursor_width) {
7978 case 64:
7979 cntl |= CURSOR_MODE_64_ARGB_AX;
7980 break;
7981 case 128:
7982 cntl |= CURSOR_MODE_128_ARGB_AX;
7983 break;
7984 case 256:
7985 cntl |= CURSOR_MODE_256_ARGB_AX;
7986 break;
7987 default:
7988 WARN_ON(1);
7989 return;
7990 }
7991 cntl |= pipe << 28; /* Connect to correct pipe */
7992 }
7993 if (intel_crtc->cursor_cntl != cntl) {
7994 I915_WRITE(CURCNTR(pipe), cntl);
7995 POSTING_READ(CURCNTR(pipe));
7996 intel_crtc->cursor_cntl = cntl;
7997 }
7998
7999 /* and commit changes on next vblank */
8000 I915_WRITE(CURBASE(pipe), base);
8001 POSTING_READ(CURBASE(pipe));
8002 }
8003
8004 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
8005 {
8006 struct drm_device *dev = crtc->dev;
8007 struct drm_i915_private *dev_priv = dev->dev_private;
8008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8009 int pipe = intel_crtc->pipe;
8010 uint32_t cntl;
8011
8012 cntl = 0;
8013 if (base) {
8014 cntl = MCURSOR_GAMMA_ENABLE;
8015 switch (intel_crtc->cursor_width) {
8016 case 64:
8017 cntl |= CURSOR_MODE_64_ARGB_AX;
8018 break;
8019 case 128:
8020 cntl |= CURSOR_MODE_128_ARGB_AX;
8021 break;
8022 case 256:
8023 cntl |= CURSOR_MODE_256_ARGB_AX;
8024 break;
8025 default:
8026 WARN_ON(1);
8027 return;
8028 }
8029 }
8030 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8031 cntl |= CURSOR_PIPE_CSC_ENABLE;
8032
8033 if (intel_crtc->cursor_cntl != cntl) {
8034 I915_WRITE(CURCNTR(pipe), cntl);
8035 POSTING_READ(CURCNTR(pipe));
8036 intel_crtc->cursor_cntl = cntl;
8037 }
8038
8039 /* and commit changes on next vblank */
8040 I915_WRITE(CURBASE(pipe), base);
8041 POSTING_READ(CURBASE(pipe));
8042 }
8043
8044 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
8045 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8046 bool on)
8047 {
8048 struct drm_device *dev = crtc->dev;
8049 struct drm_i915_private *dev_priv = dev->dev_private;
8050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8051 int pipe = intel_crtc->pipe;
8052 int x = crtc->cursor_x;
8053 int y = crtc->cursor_y;
8054 u32 base = 0, pos = 0;
8055
8056 if (on)
8057 base = intel_crtc->cursor_addr;
8058
8059 if (x >= intel_crtc->config.pipe_src_w)
8060 base = 0;
8061
8062 if (y >= intel_crtc->config.pipe_src_h)
8063 base = 0;
8064
8065 if (x < 0) {
8066 if (x + intel_crtc->cursor_width <= 0)
8067 base = 0;
8068
8069 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8070 x = -x;
8071 }
8072 pos |= x << CURSOR_X_SHIFT;
8073
8074 if (y < 0) {
8075 if (y + intel_crtc->cursor_height <= 0)
8076 base = 0;
8077
8078 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8079 y = -y;
8080 }
8081 pos |= y << CURSOR_Y_SHIFT;
8082
8083 if (base == 0 && intel_crtc->cursor_base == 0)
8084 return;
8085
8086 I915_WRITE(CURPOS(pipe), pos);
8087
8088 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_BROADWELL(dev))
8089 ivb_update_cursor(crtc, base);
8090 else if (IS_845G(dev) || IS_I865G(dev))
8091 i845_update_cursor(crtc, base);
8092 else
8093 i9xx_update_cursor(crtc, base);
8094 intel_crtc->cursor_base = base;
8095 }
8096
8097 /*
8098 * intel_crtc_cursor_set_obj - Set cursor to specified GEM object
8099 *
8100 * Note that the object's reference will be consumed if the update fails. If
8101 * the update succeeds, the reference of the old object (if any) will be
8102 * consumed.
8103 */
8104 static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc,
8105 struct drm_i915_gem_object *obj,
8106 uint32_t width, uint32_t height)
8107 {
8108 struct drm_device *dev = crtc->dev;
8109 struct drm_i915_private *dev_priv = dev->dev_private;
8110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8111 unsigned old_width;
8112 uint32_t addr;
8113 int ret;
8114
8115 /* if we want to turn off the cursor ignore width and height */
8116 if (!obj) {
8117 DRM_DEBUG_KMS("cursor off\n");
8118 addr = 0;
8119 obj = NULL;
8120 mutex_lock(&dev->struct_mutex);
8121 goto finish;
8122 }
8123
8124 /* Check for which cursor types we support */
8125 if (!((width == 64 && height == 64) ||
8126 (width == 128 && height == 128 && !IS_GEN2(dev)) ||
8127 (width == 256 && height == 256 && !IS_GEN2(dev)))) {
8128 DRM_DEBUG("Cursor dimension not supported\n");
8129 return -EINVAL;
8130 }
8131
8132 if (obj->base.size < width * height * 4) {
8133 DRM_DEBUG_KMS("buffer is too small\n");
8134 ret = -ENOMEM;
8135 goto fail;
8136 }
8137
8138 /* we only need to pin inside GTT if cursor is non-phy */
8139 mutex_lock(&dev->struct_mutex);
8140 if (!INTEL_INFO(dev)->cursor_needs_physical) {
8141 unsigned alignment;
8142
8143 if (obj->tiling_mode) {
8144 DRM_DEBUG_KMS("cursor cannot be tiled\n");
8145 ret = -EINVAL;
8146 goto fail_locked;
8147 }
8148
8149 /* Note that the w/a also requires 2 PTE of padding following
8150 * the bo. We currently fill all unused PTE with the shadow
8151 * page and so we should always have valid PTE following the
8152 * cursor preventing the VT-d warning.
8153 */
8154 alignment = 0;
8155 if (need_vtd_wa(dev))
8156 alignment = 64*1024;
8157
8158 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
8159 if (ret) {
8160 DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n");
8161 goto fail_locked;
8162 }
8163
8164 ret = i915_gem_object_put_fence(obj);
8165 if (ret) {
8166 DRM_DEBUG_KMS("failed to release fence for cursor");
8167 goto fail_unpin;
8168 }
8169
8170 addr = i915_gem_obj_ggtt_offset(obj);
8171 } else {
8172 int align = IS_I830(dev) ? 16 * 1024 : 256;
8173 ret = i915_gem_object_attach_phys(obj, align);
8174 if (ret) {
8175 DRM_DEBUG_KMS("failed to attach phys object\n");
8176 goto fail_locked;
8177 }
8178 addr = obj->phys_handle->busaddr;
8179 }
8180
8181 if (IS_GEN2(dev))
8182 I915_WRITE(CURSIZE, (height << 12) | width);
8183
8184 finish:
8185 if (intel_crtc->cursor_bo) {
8186 if (!INTEL_INFO(dev)->cursor_needs_physical)
8187 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
8188 }
8189
8190 mutex_unlock(&dev->struct_mutex);
8191
8192 old_width = intel_crtc->cursor_width;
8193
8194 intel_crtc->cursor_addr = addr;
8195 intel_crtc->cursor_bo = obj;
8196 intel_crtc->cursor_width = width;
8197 intel_crtc->cursor_height = height;
8198
8199 if (intel_crtc->active) {
8200 if (old_width != width)
8201 intel_update_watermarks(crtc);
8202 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
8203 }
8204
8205 return 0;
8206 fail_unpin:
8207 i915_gem_object_unpin_from_display_plane(obj);
8208 fail_locked:
8209 mutex_unlock(&dev->struct_mutex);
8210 fail:
8211 drm_gem_object_unreference_unlocked(&obj->base);
8212 return ret;
8213 }
8214
8215 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
8216 u16 *blue, uint32_t start, uint32_t size)
8217 {
8218 int end = (start + size > 256) ? 256 : start + size, i;
8219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8220
8221 for (i = start; i < end; i++) {
8222 intel_crtc->lut_r[i] = red[i] >> 8;
8223 intel_crtc->lut_g[i] = green[i] >> 8;
8224 intel_crtc->lut_b[i] = blue[i] >> 8;
8225 }
8226
8227 intel_crtc_load_lut(crtc);
8228 }
8229
8230 /* VESA 640x480x72Hz mode to set on the pipe */
8231 static struct drm_display_mode load_detect_mode = {
8232 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8233 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8234 };
8235
8236 struct drm_framebuffer *
8237 __intel_framebuffer_create(struct drm_device *dev,
8238 struct drm_mode_fb_cmd2 *mode_cmd,
8239 struct drm_i915_gem_object *obj)
8240 {
8241 struct intel_framebuffer *intel_fb;
8242 int ret;
8243
8244 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8245 if (!intel_fb) {
8246 drm_gem_object_unreference_unlocked(&obj->base);
8247 return ERR_PTR(-ENOMEM);
8248 }
8249
8250 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
8251 if (ret)
8252 goto err;
8253
8254 return &intel_fb->base;
8255 err:
8256 drm_gem_object_unreference_unlocked(&obj->base);
8257 kfree(intel_fb);
8258
8259 return ERR_PTR(ret);
8260 }
8261
8262 static struct drm_framebuffer *
8263 intel_framebuffer_create(struct drm_device *dev,
8264 struct drm_mode_fb_cmd2 *mode_cmd,
8265 struct drm_i915_gem_object *obj)
8266 {
8267 struct drm_framebuffer *fb;
8268 int ret;
8269
8270 ret = i915_mutex_lock_interruptible(dev);
8271 if (ret)
8272 return ERR_PTR(ret);
8273 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8274 mutex_unlock(&dev->struct_mutex);
8275
8276 return fb;
8277 }
8278
8279 static u32
8280 intel_framebuffer_pitch_for_width(int width, int bpp)
8281 {
8282 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8283 return ALIGN(pitch, 64);
8284 }
8285
8286 static u32
8287 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8288 {
8289 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
8290 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
8291 }
8292
8293 static struct drm_framebuffer *
8294 intel_framebuffer_create_for_mode(struct drm_device *dev,
8295 struct drm_display_mode *mode,
8296 int depth, int bpp)
8297 {
8298 struct drm_i915_gem_object *obj;
8299 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
8300
8301 obj = i915_gem_alloc_object(dev,
8302 intel_framebuffer_size_for_mode(mode, bpp));
8303 if (obj == NULL)
8304 return ERR_PTR(-ENOMEM);
8305
8306 mode_cmd.width = mode->hdisplay;
8307 mode_cmd.height = mode->vdisplay;
8308 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8309 bpp);
8310 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
8311
8312 return intel_framebuffer_create(dev, &mode_cmd, obj);
8313 }
8314
8315 static struct drm_framebuffer *
8316 mode_fits_in_fbdev(struct drm_device *dev,
8317 struct drm_display_mode *mode)
8318 {
8319 #ifdef CONFIG_DRM_I915_FBDEV
8320 struct drm_i915_private *dev_priv = dev->dev_private;
8321 struct drm_i915_gem_object *obj;
8322 struct drm_framebuffer *fb;
8323
8324 if (!dev_priv->fbdev)
8325 return NULL;
8326
8327 if (!dev_priv->fbdev->fb)
8328 return NULL;
8329
8330 obj = dev_priv->fbdev->fb->obj;
8331 BUG_ON(!obj);
8332
8333 fb = &dev_priv->fbdev->fb->base;
8334 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8335 fb->bits_per_pixel))
8336 return NULL;
8337
8338 if (obj->base.size < mode->vdisplay * fb->pitches[0])
8339 return NULL;
8340
8341 return fb;
8342 #else
8343 return NULL;
8344 #endif
8345 }
8346
8347 bool intel_get_load_detect_pipe(struct drm_connector *connector,
8348 struct drm_display_mode *mode,
8349 struct intel_load_detect_pipe *old,
8350 struct drm_modeset_acquire_ctx *ctx)
8351 {
8352 struct intel_crtc *intel_crtc;
8353 struct intel_encoder *intel_encoder =
8354 intel_attached_encoder(connector);
8355 struct drm_crtc *possible_crtc;
8356 struct drm_encoder *encoder = &intel_encoder->base;
8357 struct drm_crtc *crtc = NULL;
8358 struct drm_device *dev = encoder->dev;
8359 struct drm_framebuffer *fb;
8360 struct drm_mode_config *config = &dev->mode_config;
8361 int ret, i = -1;
8362
8363 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8364 connector->base.id, connector->name,
8365 encoder->base.id, encoder->name);
8366
8367 drm_modeset_acquire_init(ctx, 0);
8368
8369 retry:
8370 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8371 if (ret)
8372 goto fail_unlock;
8373
8374 /*
8375 * Algorithm gets a little messy:
8376 *
8377 * - if the connector already has an assigned crtc, use it (but make
8378 * sure it's on first)
8379 *
8380 * - try to find the first unused crtc that can drive this connector,
8381 * and use that if we find one
8382 */
8383
8384 /* See if we already have a CRTC for this connector */
8385 if (encoder->crtc) {
8386 crtc = encoder->crtc;
8387
8388 ret = drm_modeset_lock(&crtc->mutex, ctx);
8389 if (ret)
8390 goto fail_unlock;
8391
8392 old->dpms_mode = connector->dpms;
8393 old->load_detect_temp = false;
8394
8395 /* Make sure the crtc and connector are running */
8396 if (connector->dpms != DRM_MODE_DPMS_ON)
8397 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8398
8399 return true;
8400 }
8401
8402 /* Find an unused one (if possible) */
8403 for_each_crtc(dev, possible_crtc) {
8404 i++;
8405 if (!(encoder->possible_crtcs & (1 << i)))
8406 continue;
8407 if (!possible_crtc->enabled) {
8408 crtc = possible_crtc;
8409 break;
8410 }
8411 }
8412
8413 /*
8414 * If we didn't find an unused CRTC, don't use any.
8415 */
8416 if (!crtc) {
8417 DRM_DEBUG_KMS("no pipe available for load-detect\n");
8418 goto fail_unlock;
8419 }
8420
8421 ret = drm_modeset_lock(&crtc->mutex, ctx);
8422 if (ret)
8423 goto fail_unlock;
8424 intel_encoder->new_crtc = to_intel_crtc(crtc);
8425 to_intel_connector(connector)->new_encoder = intel_encoder;
8426
8427 intel_crtc = to_intel_crtc(crtc);
8428 intel_crtc->new_enabled = true;
8429 intel_crtc->new_config = &intel_crtc->config;
8430 old->dpms_mode = connector->dpms;
8431 old->load_detect_temp = true;
8432 old->release_fb = NULL;
8433
8434 if (!mode)
8435 mode = &load_detect_mode;
8436
8437 /* We need a framebuffer large enough to accommodate all accesses
8438 * that the plane may generate whilst we perform load detection.
8439 * We can not rely on the fbcon either being present (we get called
8440 * during its initialisation to detect all boot displays, or it may
8441 * not even exist) or that it is large enough to satisfy the
8442 * requested mode.
8443 */
8444 fb = mode_fits_in_fbdev(dev, mode);
8445 if (fb == NULL) {
8446 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
8447 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
8448 old->release_fb = fb;
8449 } else
8450 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
8451 if (IS_ERR(fb)) {
8452 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
8453 goto fail;
8454 }
8455
8456 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
8457 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
8458 if (old->release_fb)
8459 old->release_fb->funcs->destroy(old->release_fb);
8460 goto fail;
8461 }
8462
8463 /* let the connector get through one full cycle before testing */
8464 intel_wait_for_vblank(dev, intel_crtc->pipe);
8465 return true;
8466
8467 fail:
8468 intel_crtc->new_enabled = crtc->enabled;
8469 if (intel_crtc->new_enabled)
8470 intel_crtc->new_config = &intel_crtc->config;
8471 else
8472 intel_crtc->new_config = NULL;
8473 fail_unlock:
8474 if (ret == -EDEADLK) {
8475 drm_modeset_backoff(ctx);
8476 goto retry;
8477 }
8478
8479 drm_modeset_drop_locks(ctx);
8480 drm_modeset_acquire_fini(ctx);
8481
8482 return false;
8483 }
8484
8485 void intel_release_load_detect_pipe(struct drm_connector *connector,
8486 struct intel_load_detect_pipe *old,
8487 struct drm_modeset_acquire_ctx *ctx)
8488 {
8489 struct intel_encoder *intel_encoder =
8490 intel_attached_encoder(connector);
8491 struct drm_encoder *encoder = &intel_encoder->base;
8492 struct drm_crtc *crtc = encoder->crtc;
8493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8494
8495 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
8496 connector->base.id, connector->name,
8497 encoder->base.id, encoder->name);
8498
8499 if (old->load_detect_temp) {
8500 to_intel_connector(connector)->new_encoder = NULL;
8501 intel_encoder->new_crtc = NULL;
8502 intel_crtc->new_enabled = false;
8503 intel_crtc->new_config = NULL;
8504 intel_set_mode(crtc, NULL, 0, 0, NULL);
8505
8506 if (old->release_fb) {
8507 drm_framebuffer_unregister_private(old->release_fb);
8508 drm_framebuffer_unreference(old->release_fb);
8509 }
8510
8511 goto unlock;
8512 return;
8513 }
8514
8515 /* Switch crtc and encoder back off if necessary */
8516 if (old->dpms_mode != DRM_MODE_DPMS_ON)
8517 connector->funcs->dpms(connector, old->dpms_mode);
8518
8519 unlock:
8520 drm_modeset_drop_locks(ctx);
8521 drm_modeset_acquire_fini(ctx);
8522 }
8523
8524 static int i9xx_pll_refclk(struct drm_device *dev,
8525 const struct intel_crtc_config *pipe_config)
8526 {
8527 struct drm_i915_private *dev_priv = dev->dev_private;
8528 u32 dpll = pipe_config->dpll_hw_state.dpll;
8529
8530 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
8531 return dev_priv->vbt.lvds_ssc_freq;
8532 else if (HAS_PCH_SPLIT(dev))
8533 return 120000;
8534 else if (!IS_GEN2(dev))
8535 return 96000;
8536 else
8537 return 48000;
8538 }
8539
8540 /* Returns the clock of the currently programmed mode of the given pipe. */
8541 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
8542 struct intel_crtc_config *pipe_config)
8543 {
8544 struct drm_device *dev = crtc->base.dev;
8545 struct drm_i915_private *dev_priv = dev->dev_private;
8546 int pipe = pipe_config->cpu_transcoder;
8547 u32 dpll = pipe_config->dpll_hw_state.dpll;
8548 u32 fp;
8549 intel_clock_t clock;
8550 int refclk = i9xx_pll_refclk(dev, pipe_config);
8551
8552 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
8553 fp = pipe_config->dpll_hw_state.fp0;
8554 else
8555 fp = pipe_config->dpll_hw_state.fp1;
8556
8557 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
8558 if (IS_PINEVIEW(dev)) {
8559 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
8560 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
8561 } else {
8562 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
8563 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
8564 }
8565
8566 if (!IS_GEN2(dev)) {
8567 if (IS_PINEVIEW(dev))
8568 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
8569 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
8570 else
8571 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
8572 DPLL_FPA01_P1_POST_DIV_SHIFT);
8573
8574 switch (dpll & DPLL_MODE_MASK) {
8575 case DPLLB_MODE_DAC_SERIAL:
8576 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
8577 5 : 10;
8578 break;
8579 case DPLLB_MODE_LVDS:
8580 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
8581 7 : 14;
8582 break;
8583 default:
8584 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
8585 "mode\n", (int)(dpll & DPLL_MODE_MASK));
8586 return;
8587 }
8588
8589 if (IS_PINEVIEW(dev))
8590 pineview_clock(refclk, &clock);
8591 else
8592 i9xx_clock(refclk, &clock);
8593 } else {
8594 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
8595 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
8596
8597 if (is_lvds) {
8598 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
8599 DPLL_FPA01_P1_POST_DIV_SHIFT);
8600
8601 if (lvds & LVDS_CLKB_POWER_UP)
8602 clock.p2 = 7;
8603 else
8604 clock.p2 = 14;
8605 } else {
8606 if (dpll & PLL_P1_DIVIDE_BY_TWO)
8607 clock.p1 = 2;
8608 else {
8609 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
8610 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
8611 }
8612 if (dpll & PLL_P2_DIVIDE_BY_4)
8613 clock.p2 = 4;
8614 else
8615 clock.p2 = 2;
8616 }
8617
8618 i9xx_clock(refclk, &clock);
8619 }
8620
8621 /*
8622 * This value includes pixel_multiplier. We will use
8623 * port_clock to compute adjusted_mode.crtc_clock in the
8624 * encoder's get_config() function.
8625 */
8626 pipe_config->port_clock = clock.dot;
8627 }
8628
8629 int intel_dotclock_calculate(int link_freq,
8630 const struct intel_link_m_n *m_n)
8631 {
8632 /*
8633 * The calculation for the data clock is:
8634 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
8635 * But we want to avoid losing precison if possible, so:
8636 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
8637 *
8638 * and the link clock is simpler:
8639 * link_clock = (m * link_clock) / n
8640 */
8641
8642 if (!m_n->link_n)
8643 return 0;
8644
8645 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
8646 }
8647
8648 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
8649 struct intel_crtc_config *pipe_config)
8650 {
8651 struct drm_device *dev = crtc->base.dev;
8652
8653 /* read out port_clock from the DPLL */
8654 i9xx_crtc_clock_get(crtc, pipe_config);
8655
8656 /*
8657 * This value does not include pixel_multiplier.
8658 * We will check that port_clock and adjusted_mode.crtc_clock
8659 * agree once we know their relationship in the encoder's
8660 * get_config() function.
8661 */
8662 pipe_config->adjusted_mode.crtc_clock =
8663 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
8664 &pipe_config->fdi_m_n);
8665 }
8666
8667 /** Returns the currently programmed mode of the given pipe. */
8668 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
8669 struct drm_crtc *crtc)
8670 {
8671 struct drm_i915_private *dev_priv = dev->dev_private;
8672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8673 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8674 struct drm_display_mode *mode;
8675 struct intel_crtc_config pipe_config;
8676 int htot = I915_READ(HTOTAL(cpu_transcoder));
8677 int hsync = I915_READ(HSYNC(cpu_transcoder));
8678 int vtot = I915_READ(VTOTAL(cpu_transcoder));
8679 int vsync = I915_READ(VSYNC(cpu_transcoder));
8680 enum pipe pipe = intel_crtc->pipe;
8681
8682 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
8683 if (!mode)
8684 return NULL;
8685
8686 /*
8687 * Construct a pipe_config sufficient for getting the clock info
8688 * back out of crtc_clock_get.
8689 *
8690 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
8691 * to use a real value here instead.
8692 */
8693 pipe_config.cpu_transcoder = (enum transcoder) pipe;
8694 pipe_config.pixel_multiplier = 1;
8695 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
8696 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
8697 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
8698 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
8699
8700 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
8701 mode->hdisplay = (htot & 0xffff) + 1;
8702 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
8703 mode->hsync_start = (hsync & 0xffff) + 1;
8704 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
8705 mode->vdisplay = (vtot & 0xffff) + 1;
8706 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
8707 mode->vsync_start = (vsync & 0xffff) + 1;
8708 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
8709
8710 drm_mode_set_name(mode);
8711
8712 return mode;
8713 }
8714
8715 static void intel_increase_pllclock(struct drm_crtc *crtc)
8716 {
8717 struct drm_device *dev = crtc->dev;
8718 struct drm_i915_private *dev_priv = dev->dev_private;
8719 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8720 int pipe = intel_crtc->pipe;
8721 int dpll_reg = DPLL(pipe);
8722 int dpll;
8723
8724 if (HAS_PCH_SPLIT(dev))
8725 return;
8726
8727 if (!dev_priv->lvds_downclock_avail)
8728 return;
8729
8730 dpll = I915_READ(dpll_reg);
8731 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
8732 DRM_DEBUG_DRIVER("upclocking LVDS\n");
8733
8734 assert_panel_unlocked(dev_priv, pipe);
8735
8736 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
8737 I915_WRITE(dpll_reg, dpll);
8738 intel_wait_for_vblank(dev, pipe);
8739
8740 dpll = I915_READ(dpll_reg);
8741 if (dpll & DISPLAY_RATE_SELECT_FPA1)
8742 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
8743 }
8744 }
8745
8746 static void intel_decrease_pllclock(struct drm_crtc *crtc)
8747 {
8748 struct drm_device *dev = crtc->dev;
8749 struct drm_i915_private *dev_priv = dev->dev_private;
8750 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8751
8752 if (HAS_PCH_SPLIT(dev))
8753 return;
8754
8755 if (!dev_priv->lvds_downclock_avail)
8756 return;
8757
8758 /*
8759 * Since this is called by a timer, we should never get here in
8760 * the manual case.
8761 */
8762 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
8763 int pipe = intel_crtc->pipe;
8764 int dpll_reg = DPLL(pipe);
8765 int dpll;
8766
8767 DRM_DEBUG_DRIVER("downclocking LVDS\n");
8768
8769 assert_panel_unlocked(dev_priv, pipe);
8770
8771 dpll = I915_READ(dpll_reg);
8772 dpll |= DISPLAY_RATE_SELECT_FPA1;
8773 I915_WRITE(dpll_reg, dpll);
8774 intel_wait_for_vblank(dev, pipe);
8775 dpll = I915_READ(dpll_reg);
8776 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
8777 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
8778 }
8779
8780 }
8781
8782 void intel_mark_busy(struct drm_device *dev)
8783 {
8784 struct drm_i915_private *dev_priv = dev->dev_private;
8785
8786 if (dev_priv->mm.busy)
8787 return;
8788
8789 intel_runtime_pm_get(dev_priv);
8790 i915_update_gfx_val(dev_priv);
8791 dev_priv->mm.busy = true;
8792 }
8793
8794 void intel_mark_idle(struct drm_device *dev)
8795 {
8796 struct drm_i915_private *dev_priv = dev->dev_private;
8797 struct drm_crtc *crtc;
8798
8799 if (!dev_priv->mm.busy)
8800 return;
8801
8802 dev_priv->mm.busy = false;
8803
8804 if (!i915.powersave)
8805 goto out;
8806
8807 for_each_crtc(dev, crtc) {
8808 if (!crtc->primary->fb)
8809 continue;
8810
8811 intel_decrease_pllclock(crtc);
8812 }
8813
8814 if (INTEL_INFO(dev)->gen >= 6)
8815 gen6_rps_idle(dev->dev_private);
8816
8817 out:
8818 intel_runtime_pm_put(dev_priv);
8819 }
8820
8821
8822 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
8823 struct intel_engine_cs *ring)
8824 {
8825 struct drm_device *dev = obj->base.dev;
8826 struct drm_crtc *crtc;
8827
8828 intel_edp_psr_exit(dev, true);
8829
8830 if (!i915.powersave)
8831 return;
8832
8833 for_each_crtc(dev, crtc) {
8834 if (!crtc->primary->fb)
8835 continue;
8836
8837 if (to_intel_framebuffer(crtc->primary->fb)->obj != obj)
8838 continue;
8839
8840 intel_increase_pllclock(crtc);
8841 if (ring && intel_fbc_enabled(dev))
8842 ring->fbc_dirty = true;
8843 }
8844 }
8845
8846 static void intel_crtc_destroy(struct drm_crtc *crtc)
8847 {
8848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8849 struct drm_device *dev = crtc->dev;
8850 struct intel_unpin_work *work;
8851 unsigned long flags;
8852
8853 spin_lock_irqsave(&dev->event_lock, flags);
8854 work = intel_crtc->unpin_work;
8855 intel_crtc->unpin_work = NULL;
8856 spin_unlock_irqrestore(&dev->event_lock, flags);
8857
8858 if (work) {
8859 cancel_work_sync(&work->work);
8860 kfree(work);
8861 }
8862
8863 drm_crtc_cleanup(crtc);
8864
8865 kfree(intel_crtc);
8866 }
8867
8868 static void intel_unpin_work_fn(struct work_struct *__work)
8869 {
8870 struct intel_unpin_work *work =
8871 container_of(__work, struct intel_unpin_work, work);
8872 struct drm_device *dev = work->crtc->dev;
8873
8874 mutex_lock(&dev->struct_mutex);
8875 intel_unpin_fb_obj(work->old_fb_obj);
8876 drm_gem_object_unreference(&work->pending_flip_obj->base);
8877 drm_gem_object_unreference(&work->old_fb_obj->base);
8878
8879 intel_update_fbc(dev);
8880 mutex_unlock(&dev->struct_mutex);
8881
8882 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
8883 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
8884
8885 kfree(work);
8886 }
8887
8888 static void do_intel_finish_page_flip(struct drm_device *dev,
8889 struct drm_crtc *crtc)
8890 {
8891 struct drm_i915_private *dev_priv = dev->dev_private;
8892 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8893 struct intel_unpin_work *work;
8894 unsigned long flags;
8895
8896 /* Ignore early vblank irqs */
8897 if (intel_crtc == NULL)
8898 return;
8899
8900 spin_lock_irqsave(&dev->event_lock, flags);
8901 work = intel_crtc->unpin_work;
8902
8903 /* Ensure we don't miss a work->pending update ... */
8904 smp_rmb();
8905
8906 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
8907 spin_unlock_irqrestore(&dev->event_lock, flags);
8908 return;
8909 }
8910
8911 /* and that the unpin work is consistent wrt ->pending. */
8912 smp_rmb();
8913
8914 intel_crtc->unpin_work = NULL;
8915
8916 if (work->event)
8917 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
8918
8919 drm_crtc_vblank_put(crtc);
8920
8921 spin_unlock_irqrestore(&dev->event_lock, flags);
8922
8923 wake_up_all(&dev_priv->pending_flip_queue);
8924
8925 queue_work(dev_priv->wq, &work->work);
8926
8927 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
8928 }
8929
8930 void intel_finish_page_flip(struct drm_device *dev, int pipe)
8931 {
8932 struct drm_i915_private *dev_priv = dev->dev_private;
8933 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
8934
8935 do_intel_finish_page_flip(dev, crtc);
8936 }
8937
8938 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
8939 {
8940 struct drm_i915_private *dev_priv = dev->dev_private;
8941 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
8942
8943 do_intel_finish_page_flip(dev, crtc);
8944 }
8945
8946 /* Is 'a' after or equal to 'b'? */
8947 static bool g4x_flip_count_after_eq(u32 a, u32 b)
8948 {
8949 return !((a - b) & 0x80000000);
8950 }
8951
8952 static bool page_flip_finished(struct intel_crtc *crtc)
8953 {
8954 struct drm_device *dev = crtc->base.dev;
8955 struct drm_i915_private *dev_priv = dev->dev_private;
8956
8957 /*
8958 * The relevant registers doen't exist on pre-ctg.
8959 * As the flip done interrupt doesn't trigger for mmio
8960 * flips on gmch platforms, a flip count check isn't
8961 * really needed there. But since ctg has the registers,
8962 * include it in the check anyway.
8963 */
8964 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
8965 return true;
8966
8967 /*
8968 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
8969 * used the same base address. In that case the mmio flip might
8970 * have completed, but the CS hasn't even executed the flip yet.
8971 *
8972 * A flip count check isn't enough as the CS might have updated
8973 * the base address just after start of vblank, but before we
8974 * managed to process the interrupt. This means we'd complete the
8975 * CS flip too soon.
8976 *
8977 * Combining both checks should get us a good enough result. It may
8978 * still happen that the CS flip has been executed, but has not
8979 * yet actually completed. But in case the base address is the same
8980 * anyway, we don't really care.
8981 */
8982 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
8983 crtc->unpin_work->gtt_offset &&
8984 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
8985 crtc->unpin_work->flip_count);
8986 }
8987
8988 void intel_prepare_page_flip(struct drm_device *dev, int plane)
8989 {
8990 struct drm_i915_private *dev_priv = dev->dev_private;
8991 struct intel_crtc *intel_crtc =
8992 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
8993 unsigned long flags;
8994
8995 /* NB: An MMIO update of the plane base pointer will also
8996 * generate a page-flip completion irq, i.e. every modeset
8997 * is also accompanied by a spurious intel_prepare_page_flip().
8998 */
8999 spin_lock_irqsave(&dev->event_lock, flags);
9000 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
9001 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
9002 spin_unlock_irqrestore(&dev->event_lock, flags);
9003 }
9004
9005 static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
9006 {
9007 /* Ensure that the work item is consistent when activating it ... */
9008 smp_wmb();
9009 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9010 /* and that it is marked active as soon as the irq could fire. */
9011 smp_wmb();
9012 }
9013
9014 static int intel_gen2_queue_flip(struct drm_device *dev,
9015 struct drm_crtc *crtc,
9016 struct drm_framebuffer *fb,
9017 struct drm_i915_gem_object *obj,
9018 struct intel_engine_cs *ring,
9019 uint32_t flags)
9020 {
9021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9022 u32 flip_mask;
9023 int ret;
9024
9025 ret = intel_ring_begin(ring, 6);
9026 if (ret)
9027 return ret;
9028
9029 /* Can't queue multiple flips, so wait for the previous
9030 * one to finish before executing the next.
9031 */
9032 if (intel_crtc->plane)
9033 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9034 else
9035 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9036 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9037 intel_ring_emit(ring, MI_NOOP);
9038 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9039 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9040 intel_ring_emit(ring, fb->pitches[0]);
9041 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9042 intel_ring_emit(ring, 0); /* aux display base address, unused */
9043
9044 intel_mark_page_flip_active(intel_crtc);
9045 __intel_ring_advance(ring);
9046 return 0;
9047 }
9048
9049 static int intel_gen3_queue_flip(struct drm_device *dev,
9050 struct drm_crtc *crtc,
9051 struct drm_framebuffer *fb,
9052 struct drm_i915_gem_object *obj,
9053 struct intel_engine_cs *ring,
9054 uint32_t flags)
9055 {
9056 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9057 u32 flip_mask;
9058 int ret;
9059
9060 ret = intel_ring_begin(ring, 6);
9061 if (ret)
9062 return ret;
9063
9064 if (intel_crtc->plane)
9065 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9066 else
9067 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
9068 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9069 intel_ring_emit(ring, MI_NOOP);
9070 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9071 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9072 intel_ring_emit(ring, fb->pitches[0]);
9073 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9074 intel_ring_emit(ring, MI_NOOP);
9075
9076 intel_mark_page_flip_active(intel_crtc);
9077 __intel_ring_advance(ring);
9078 return 0;
9079 }
9080
9081 static int intel_gen4_queue_flip(struct drm_device *dev,
9082 struct drm_crtc *crtc,
9083 struct drm_framebuffer *fb,
9084 struct drm_i915_gem_object *obj,
9085 struct intel_engine_cs *ring,
9086 uint32_t flags)
9087 {
9088 struct drm_i915_private *dev_priv = dev->dev_private;
9089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9090 uint32_t pf, pipesrc;
9091 int ret;
9092
9093 ret = intel_ring_begin(ring, 4);
9094 if (ret)
9095 return ret;
9096
9097 /* i965+ uses the linear or tiled offsets from the
9098 * Display Registers (which do not change across a page-flip)
9099 * so we need only reprogram the base address.
9100 */
9101 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9102 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9103 intel_ring_emit(ring, fb->pitches[0]);
9104 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
9105 obj->tiling_mode);
9106
9107 /* XXX Enabling the panel-fitter across page-flip is so far
9108 * untested on non-native modes, so ignore it for now.
9109 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9110 */
9111 pf = 0;
9112 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9113 intel_ring_emit(ring, pf | pipesrc);
9114
9115 intel_mark_page_flip_active(intel_crtc);
9116 __intel_ring_advance(ring);
9117 return 0;
9118 }
9119
9120 static int intel_gen6_queue_flip(struct drm_device *dev,
9121 struct drm_crtc *crtc,
9122 struct drm_framebuffer *fb,
9123 struct drm_i915_gem_object *obj,
9124 struct intel_engine_cs *ring,
9125 uint32_t flags)
9126 {
9127 struct drm_i915_private *dev_priv = dev->dev_private;
9128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9129 uint32_t pf, pipesrc;
9130 int ret;
9131
9132 ret = intel_ring_begin(ring, 4);
9133 if (ret)
9134 return ret;
9135
9136 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9137 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9138 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
9139 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9140
9141 /* Contrary to the suggestions in the documentation,
9142 * "Enable Panel Fitter" does not seem to be required when page
9143 * flipping with a non-native mode, and worse causes a normal
9144 * modeset to fail.
9145 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9146 */
9147 pf = 0;
9148 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
9149 intel_ring_emit(ring, pf | pipesrc);
9150
9151 intel_mark_page_flip_active(intel_crtc);
9152 __intel_ring_advance(ring);
9153 return 0;
9154 }
9155
9156 static int intel_gen7_queue_flip(struct drm_device *dev,
9157 struct drm_crtc *crtc,
9158 struct drm_framebuffer *fb,
9159 struct drm_i915_gem_object *obj,
9160 struct intel_engine_cs *ring,
9161 uint32_t flags)
9162 {
9163 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9164 uint32_t plane_bit = 0;
9165 int len, ret;
9166
9167 switch (intel_crtc->plane) {
9168 case PLANE_A:
9169 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9170 break;
9171 case PLANE_B:
9172 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9173 break;
9174 case PLANE_C:
9175 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9176 break;
9177 default:
9178 WARN_ONCE(1, "unknown plane in flip command\n");
9179 return -ENODEV;
9180 }
9181
9182 len = 4;
9183 if (ring->id == RCS) {
9184 len += 6;
9185 /*
9186 * On Gen 8, SRM is now taking an extra dword to accommodate
9187 * 48bits addresses, and we need a NOOP for the batch size to
9188 * stay even.
9189 */
9190 if (IS_GEN8(dev))
9191 len += 2;
9192 }
9193
9194 /*
9195 * BSpec MI_DISPLAY_FLIP for IVB:
9196 * "The full packet must be contained within the same cache line."
9197 *
9198 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9199 * cacheline, if we ever start emitting more commands before
9200 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9201 * then do the cacheline alignment, and finally emit the
9202 * MI_DISPLAY_FLIP.
9203 */
9204 ret = intel_ring_cacheline_align(ring);
9205 if (ret)
9206 return ret;
9207
9208 ret = intel_ring_begin(ring, len);
9209 if (ret)
9210 return ret;
9211
9212 /* Unmask the flip-done completion message. Note that the bspec says that
9213 * we should do this for both the BCS and RCS, and that we must not unmask
9214 * more than one flip event at any time (or ensure that one flip message
9215 * can be sent by waiting for flip-done prior to queueing new flips).
9216 * Experimentation says that BCS works despite DERRMR masking all
9217 * flip-done completion events and that unmasking all planes at once
9218 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9219 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9220 */
9221 if (ring->id == RCS) {
9222 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9223 intel_ring_emit(ring, DERRMR);
9224 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9225 DERRMR_PIPEB_PRI_FLIP_DONE |
9226 DERRMR_PIPEC_PRI_FLIP_DONE));
9227 if (IS_GEN8(dev))
9228 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9229 MI_SRM_LRM_GLOBAL_GTT);
9230 else
9231 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9232 MI_SRM_LRM_GLOBAL_GTT);
9233 intel_ring_emit(ring, DERRMR);
9234 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
9235 if (IS_GEN8(dev)) {
9236 intel_ring_emit(ring, 0);
9237 intel_ring_emit(ring, MI_NOOP);
9238 }
9239 }
9240
9241 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
9242 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
9243 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
9244 intel_ring_emit(ring, (MI_NOOP));
9245
9246 intel_mark_page_flip_active(intel_crtc);
9247 __intel_ring_advance(ring);
9248 return 0;
9249 }
9250
9251 static int intel_default_queue_flip(struct drm_device *dev,
9252 struct drm_crtc *crtc,
9253 struct drm_framebuffer *fb,
9254 struct drm_i915_gem_object *obj,
9255 struct intel_engine_cs *ring,
9256 uint32_t flags)
9257 {
9258 return -ENODEV;
9259 }
9260
9261 static int intel_crtc_page_flip(struct drm_crtc *crtc,
9262 struct drm_framebuffer *fb,
9263 struct drm_pending_vblank_event *event,
9264 uint32_t page_flip_flags)
9265 {
9266 struct drm_device *dev = crtc->dev;
9267 struct drm_i915_private *dev_priv = dev->dev_private;
9268 struct drm_framebuffer *old_fb = crtc->primary->fb;
9269 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
9270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9271 struct intel_unpin_work *work;
9272 struct intel_engine_cs *ring;
9273 unsigned long flags;
9274 int ret;
9275
9276 /* Can't change pixel format via MI display flips. */
9277 if (fb->pixel_format != crtc->primary->fb->pixel_format)
9278 return -EINVAL;
9279
9280 /*
9281 * TILEOFF/LINOFF registers can't be changed via MI display flips.
9282 * Note that pitch changes could also affect these register.
9283 */
9284 if (INTEL_INFO(dev)->gen > 3 &&
9285 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
9286 fb->pitches[0] != crtc->primary->fb->pitches[0]))
9287 return -EINVAL;
9288
9289 if (i915_terminally_wedged(&dev_priv->gpu_error))
9290 goto out_hang;
9291
9292 work = kzalloc(sizeof(*work), GFP_KERNEL);
9293 if (work == NULL)
9294 return -ENOMEM;
9295
9296 /* Exit PSR early in page flip */
9297 intel_edp_psr_exit(dev, true);
9298
9299 work->event = event;
9300 work->crtc = crtc;
9301 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
9302 INIT_WORK(&work->work, intel_unpin_work_fn);
9303
9304 ret = drm_crtc_vblank_get(crtc);
9305 if (ret)
9306 goto free_work;
9307
9308 /* We borrow the event spin lock for protecting unpin_work */
9309 spin_lock_irqsave(&dev->event_lock, flags);
9310 if (intel_crtc->unpin_work) {
9311 spin_unlock_irqrestore(&dev->event_lock, flags);
9312 kfree(work);
9313 drm_crtc_vblank_put(crtc);
9314
9315 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
9316 return -EBUSY;
9317 }
9318 intel_crtc->unpin_work = work;
9319 spin_unlock_irqrestore(&dev->event_lock, flags);
9320
9321 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
9322 flush_workqueue(dev_priv->wq);
9323
9324 ret = i915_mutex_lock_interruptible(dev);
9325 if (ret)
9326 goto cleanup;
9327
9328 /* Reference the objects for the scheduled work. */
9329 drm_gem_object_reference(&work->old_fb_obj->base);
9330 drm_gem_object_reference(&obj->base);
9331
9332 crtc->primary->fb = fb;
9333
9334 work->pending_flip_obj = obj;
9335
9336 work->enable_stall_check = true;
9337
9338 atomic_inc(&intel_crtc->unpin_work_count);
9339 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
9340
9341 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
9342 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(intel_crtc->pipe)) + 1;
9343
9344 if (IS_VALLEYVIEW(dev)) {
9345 ring = &dev_priv->ring[BCS];
9346 } else if (INTEL_INFO(dev)->gen >= 7) {
9347 ring = obj->ring;
9348 if (ring == NULL || ring->id != RCS)
9349 ring = &dev_priv->ring[BCS];
9350 } else {
9351 ring = &dev_priv->ring[RCS];
9352 }
9353
9354 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
9355 if (ret)
9356 goto cleanup_pending;
9357
9358 work->gtt_offset =
9359 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset;
9360
9361 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, page_flip_flags);
9362 if (ret)
9363 goto cleanup_unpin;
9364
9365 intel_disable_fbc(dev);
9366 intel_mark_fb_busy(obj, NULL);
9367 mutex_unlock(&dev->struct_mutex);
9368
9369 trace_i915_flip_request(intel_crtc->plane, obj);
9370
9371 return 0;
9372
9373 cleanup_unpin:
9374 intel_unpin_fb_obj(obj);
9375 cleanup_pending:
9376 atomic_dec(&intel_crtc->unpin_work_count);
9377 crtc->primary->fb = old_fb;
9378 drm_gem_object_unreference(&work->old_fb_obj->base);
9379 drm_gem_object_unreference(&obj->base);
9380 mutex_unlock(&dev->struct_mutex);
9381
9382 cleanup:
9383 spin_lock_irqsave(&dev->event_lock, flags);
9384 intel_crtc->unpin_work = NULL;
9385 spin_unlock_irqrestore(&dev->event_lock, flags);
9386
9387 drm_crtc_vblank_put(crtc);
9388 free_work:
9389 kfree(work);
9390
9391 if (ret == -EIO) {
9392 out_hang:
9393 intel_crtc_wait_for_pending_flips(crtc);
9394 ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb);
9395 if (ret == 0 && event)
9396 drm_send_vblank_event(dev, intel_crtc->pipe, event);
9397 }
9398 return ret;
9399 }
9400
9401 static struct drm_crtc_helper_funcs intel_helper_funcs = {
9402 .mode_set_base_atomic = intel_pipe_set_base_atomic,
9403 .load_lut = intel_crtc_load_lut,
9404 };
9405
9406 /**
9407 * intel_modeset_update_staged_output_state
9408 *
9409 * Updates the staged output configuration state, e.g. after we've read out the
9410 * current hw state.
9411 */
9412 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
9413 {
9414 struct intel_crtc *crtc;
9415 struct intel_encoder *encoder;
9416 struct intel_connector *connector;
9417
9418 list_for_each_entry(connector, &dev->mode_config.connector_list,
9419 base.head) {
9420 connector->new_encoder =
9421 to_intel_encoder(connector->base.encoder);
9422 }
9423
9424 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9425 base.head) {
9426 encoder->new_crtc =
9427 to_intel_crtc(encoder->base.crtc);
9428 }
9429
9430 for_each_intel_crtc(dev, crtc) {
9431 crtc->new_enabled = crtc->base.enabled;
9432
9433 if (crtc->new_enabled)
9434 crtc->new_config = &crtc->config;
9435 else
9436 crtc->new_config = NULL;
9437 }
9438 }
9439
9440 /**
9441 * intel_modeset_commit_output_state
9442 *
9443 * This function copies the stage display pipe configuration to the real one.
9444 */
9445 static void intel_modeset_commit_output_state(struct drm_device *dev)
9446 {
9447 struct intel_crtc *crtc;
9448 struct intel_encoder *encoder;
9449 struct intel_connector *connector;
9450
9451 list_for_each_entry(connector, &dev->mode_config.connector_list,
9452 base.head) {
9453 connector->base.encoder = &connector->new_encoder->base;
9454 }
9455
9456 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9457 base.head) {
9458 encoder->base.crtc = &encoder->new_crtc->base;
9459 }
9460
9461 for_each_intel_crtc(dev, crtc) {
9462 crtc->base.enabled = crtc->new_enabled;
9463 }
9464 }
9465
9466 static void
9467 connected_sink_compute_bpp(struct intel_connector *connector,
9468 struct intel_crtc_config *pipe_config)
9469 {
9470 int bpp = pipe_config->pipe_bpp;
9471
9472 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
9473 connector->base.base.id,
9474 connector->base.name);
9475
9476 /* Don't use an invalid EDID bpc value */
9477 if (connector->base.display_info.bpc &&
9478 connector->base.display_info.bpc * 3 < bpp) {
9479 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
9480 bpp, connector->base.display_info.bpc*3);
9481 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
9482 }
9483
9484 /* Clamp bpp to 8 on screens without EDID 1.4 */
9485 if (connector->base.display_info.bpc == 0 && bpp > 24) {
9486 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
9487 bpp);
9488 pipe_config->pipe_bpp = 24;
9489 }
9490 }
9491
9492 static int
9493 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
9494 struct drm_framebuffer *fb,
9495 struct intel_crtc_config *pipe_config)
9496 {
9497 struct drm_device *dev = crtc->base.dev;
9498 struct intel_connector *connector;
9499 int bpp;
9500
9501 switch (fb->pixel_format) {
9502 case DRM_FORMAT_C8:
9503 bpp = 8*3; /* since we go through a colormap */
9504 break;
9505 case DRM_FORMAT_XRGB1555:
9506 case DRM_FORMAT_ARGB1555:
9507 /* checked in intel_framebuffer_init already */
9508 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
9509 return -EINVAL;
9510 case DRM_FORMAT_RGB565:
9511 bpp = 6*3; /* min is 18bpp */
9512 break;
9513 case DRM_FORMAT_XBGR8888:
9514 case DRM_FORMAT_ABGR8888:
9515 /* checked in intel_framebuffer_init already */
9516 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9517 return -EINVAL;
9518 case DRM_FORMAT_XRGB8888:
9519 case DRM_FORMAT_ARGB8888:
9520 bpp = 8*3;
9521 break;
9522 case DRM_FORMAT_XRGB2101010:
9523 case DRM_FORMAT_ARGB2101010:
9524 case DRM_FORMAT_XBGR2101010:
9525 case DRM_FORMAT_ABGR2101010:
9526 /* checked in intel_framebuffer_init already */
9527 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
9528 return -EINVAL;
9529 bpp = 10*3;
9530 break;
9531 /* TODO: gen4+ supports 16 bpc floating point, too. */
9532 default:
9533 DRM_DEBUG_KMS("unsupported depth\n");
9534 return -EINVAL;
9535 }
9536
9537 pipe_config->pipe_bpp = bpp;
9538
9539 /* Clamp display bpp to EDID value */
9540 list_for_each_entry(connector, &dev->mode_config.connector_list,
9541 base.head) {
9542 if (!connector->new_encoder ||
9543 connector->new_encoder->new_crtc != crtc)
9544 continue;
9545
9546 connected_sink_compute_bpp(connector, pipe_config);
9547 }
9548
9549 return bpp;
9550 }
9551
9552 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
9553 {
9554 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
9555 "type: 0x%x flags: 0x%x\n",
9556 mode->crtc_clock,
9557 mode->crtc_hdisplay, mode->crtc_hsync_start,
9558 mode->crtc_hsync_end, mode->crtc_htotal,
9559 mode->crtc_vdisplay, mode->crtc_vsync_start,
9560 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
9561 }
9562
9563 static void intel_dump_pipe_config(struct intel_crtc *crtc,
9564 struct intel_crtc_config *pipe_config,
9565 const char *context)
9566 {
9567 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
9568 context, pipe_name(crtc->pipe));
9569
9570 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
9571 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
9572 pipe_config->pipe_bpp, pipe_config->dither);
9573 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9574 pipe_config->has_pch_encoder,
9575 pipe_config->fdi_lanes,
9576 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
9577 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
9578 pipe_config->fdi_m_n.tu);
9579 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
9580 pipe_config->has_dp_encoder,
9581 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
9582 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
9583 pipe_config->dp_m_n.tu);
9584 DRM_DEBUG_KMS("requested mode:\n");
9585 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
9586 DRM_DEBUG_KMS("adjusted mode:\n");
9587 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
9588 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
9589 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
9590 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
9591 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
9592 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
9593 pipe_config->gmch_pfit.control,
9594 pipe_config->gmch_pfit.pgm_ratios,
9595 pipe_config->gmch_pfit.lvds_border_bits);
9596 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
9597 pipe_config->pch_pfit.pos,
9598 pipe_config->pch_pfit.size,
9599 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
9600 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
9601 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
9602 }
9603
9604 static bool encoders_cloneable(const struct intel_encoder *a,
9605 const struct intel_encoder *b)
9606 {
9607 /* masks could be asymmetric, so check both ways */
9608 return a == b || (a->cloneable & (1 << b->type) &&
9609 b->cloneable & (1 << a->type));
9610 }
9611
9612 static bool check_single_encoder_cloning(struct intel_crtc *crtc,
9613 struct intel_encoder *encoder)
9614 {
9615 struct drm_device *dev = crtc->base.dev;
9616 struct intel_encoder *source_encoder;
9617
9618 list_for_each_entry(source_encoder,
9619 &dev->mode_config.encoder_list, base.head) {
9620 if (source_encoder->new_crtc != crtc)
9621 continue;
9622
9623 if (!encoders_cloneable(encoder, source_encoder))
9624 return false;
9625 }
9626
9627 return true;
9628 }
9629
9630 static bool check_encoder_cloning(struct intel_crtc *crtc)
9631 {
9632 struct drm_device *dev = crtc->base.dev;
9633 struct intel_encoder *encoder;
9634
9635 list_for_each_entry(encoder,
9636 &dev->mode_config.encoder_list, base.head) {
9637 if (encoder->new_crtc != crtc)
9638 continue;
9639
9640 if (!check_single_encoder_cloning(crtc, encoder))
9641 return false;
9642 }
9643
9644 return true;
9645 }
9646
9647 static struct intel_crtc_config *
9648 intel_modeset_pipe_config(struct drm_crtc *crtc,
9649 struct drm_framebuffer *fb,
9650 struct drm_display_mode *mode)
9651 {
9652 struct drm_device *dev = crtc->dev;
9653 struct intel_encoder *encoder;
9654 struct intel_crtc_config *pipe_config;
9655 int plane_bpp, ret = -EINVAL;
9656 bool retry = true;
9657
9658 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
9659 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
9660 return ERR_PTR(-EINVAL);
9661 }
9662
9663 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
9664 if (!pipe_config)
9665 return ERR_PTR(-ENOMEM);
9666
9667 drm_mode_copy(&pipe_config->adjusted_mode, mode);
9668 drm_mode_copy(&pipe_config->requested_mode, mode);
9669
9670 pipe_config->cpu_transcoder =
9671 (enum transcoder) to_intel_crtc(crtc)->pipe;
9672 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9673
9674 /*
9675 * Sanitize sync polarity flags based on requested ones. If neither
9676 * positive or negative polarity is requested, treat this as meaning
9677 * negative polarity.
9678 */
9679 if (!(pipe_config->adjusted_mode.flags &
9680 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
9681 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
9682
9683 if (!(pipe_config->adjusted_mode.flags &
9684 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
9685 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
9686
9687 /* Compute a starting value for pipe_config->pipe_bpp taking the source
9688 * plane pixel format and any sink constraints into account. Returns the
9689 * source plane bpp so that dithering can be selected on mismatches
9690 * after encoders and crtc also have had their say. */
9691 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
9692 fb, pipe_config);
9693 if (plane_bpp < 0)
9694 goto fail;
9695
9696 /*
9697 * Determine the real pipe dimensions. Note that stereo modes can
9698 * increase the actual pipe size due to the frame doubling and
9699 * insertion of additional space for blanks between the frame. This
9700 * is stored in the crtc timings. We use the requested mode to do this
9701 * computation to clearly distinguish it from the adjusted mode, which
9702 * can be changed by the connectors in the below retry loop.
9703 */
9704 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
9705 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
9706 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
9707
9708 encoder_retry:
9709 /* Ensure the port clock defaults are reset when retrying. */
9710 pipe_config->port_clock = 0;
9711 pipe_config->pixel_multiplier = 1;
9712
9713 /* Fill in default crtc timings, allow encoders to overwrite them. */
9714 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
9715
9716 /* Pass our mode to the connectors and the CRTC to give them a chance to
9717 * adjust it according to limitations or connector properties, and also
9718 * a chance to reject the mode entirely.
9719 */
9720 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9721 base.head) {
9722
9723 if (&encoder->new_crtc->base != crtc)
9724 continue;
9725
9726 if (!(encoder->compute_config(encoder, pipe_config))) {
9727 DRM_DEBUG_KMS("Encoder config failure\n");
9728 goto fail;
9729 }
9730 }
9731
9732 /* Set default port clock if not overwritten by the encoder. Needs to be
9733 * done afterwards in case the encoder adjusts the mode. */
9734 if (!pipe_config->port_clock)
9735 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
9736 * pipe_config->pixel_multiplier;
9737
9738 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
9739 if (ret < 0) {
9740 DRM_DEBUG_KMS("CRTC fixup failed\n");
9741 goto fail;
9742 }
9743
9744 if (ret == RETRY) {
9745 if (WARN(!retry, "loop in pipe configuration computation\n")) {
9746 ret = -EINVAL;
9747 goto fail;
9748 }
9749
9750 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
9751 retry = false;
9752 goto encoder_retry;
9753 }
9754
9755 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
9756 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
9757 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
9758
9759 return pipe_config;
9760 fail:
9761 kfree(pipe_config);
9762 return ERR_PTR(ret);
9763 }
9764
9765 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
9766 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
9767 static void
9768 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
9769 unsigned *prepare_pipes, unsigned *disable_pipes)
9770 {
9771 struct intel_crtc *intel_crtc;
9772 struct drm_device *dev = crtc->dev;
9773 struct intel_encoder *encoder;
9774 struct intel_connector *connector;
9775 struct drm_crtc *tmp_crtc;
9776
9777 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
9778
9779 /* Check which crtcs have changed outputs connected to them, these need
9780 * to be part of the prepare_pipes mask. We don't (yet) support global
9781 * modeset across multiple crtcs, so modeset_pipes will only have one
9782 * bit set at most. */
9783 list_for_each_entry(connector, &dev->mode_config.connector_list,
9784 base.head) {
9785 if (connector->base.encoder == &connector->new_encoder->base)
9786 continue;
9787
9788 if (connector->base.encoder) {
9789 tmp_crtc = connector->base.encoder->crtc;
9790
9791 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9792 }
9793
9794 if (connector->new_encoder)
9795 *prepare_pipes |=
9796 1 << connector->new_encoder->new_crtc->pipe;
9797 }
9798
9799 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9800 base.head) {
9801 if (encoder->base.crtc == &encoder->new_crtc->base)
9802 continue;
9803
9804 if (encoder->base.crtc) {
9805 tmp_crtc = encoder->base.crtc;
9806
9807 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
9808 }
9809
9810 if (encoder->new_crtc)
9811 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
9812 }
9813
9814 /* Check for pipes that will be enabled/disabled ... */
9815 for_each_intel_crtc(dev, intel_crtc) {
9816 if (intel_crtc->base.enabled == intel_crtc->new_enabled)
9817 continue;
9818
9819 if (!intel_crtc->new_enabled)
9820 *disable_pipes |= 1 << intel_crtc->pipe;
9821 else
9822 *prepare_pipes |= 1 << intel_crtc->pipe;
9823 }
9824
9825
9826 /* set_mode is also used to update properties on life display pipes. */
9827 intel_crtc = to_intel_crtc(crtc);
9828 if (intel_crtc->new_enabled)
9829 *prepare_pipes |= 1 << intel_crtc->pipe;
9830
9831 /*
9832 * For simplicity do a full modeset on any pipe where the output routing
9833 * changed. We could be more clever, but that would require us to be
9834 * more careful with calling the relevant encoder->mode_set functions.
9835 */
9836 if (*prepare_pipes)
9837 *modeset_pipes = *prepare_pipes;
9838
9839 /* ... and mask these out. */
9840 *modeset_pipes &= ~(*disable_pipes);
9841 *prepare_pipes &= ~(*disable_pipes);
9842
9843 /*
9844 * HACK: We don't (yet) fully support global modesets. intel_set_config
9845 * obies this rule, but the modeset restore mode of
9846 * intel_modeset_setup_hw_state does not.
9847 */
9848 *modeset_pipes &= 1 << intel_crtc->pipe;
9849 *prepare_pipes &= 1 << intel_crtc->pipe;
9850
9851 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
9852 *modeset_pipes, *prepare_pipes, *disable_pipes);
9853 }
9854
9855 static bool intel_crtc_in_use(struct drm_crtc *crtc)
9856 {
9857 struct drm_encoder *encoder;
9858 struct drm_device *dev = crtc->dev;
9859
9860 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
9861 if (encoder->crtc == crtc)
9862 return true;
9863
9864 return false;
9865 }
9866
9867 static void
9868 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
9869 {
9870 struct intel_encoder *intel_encoder;
9871 struct intel_crtc *intel_crtc;
9872 struct drm_connector *connector;
9873
9874 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
9875 base.head) {
9876 if (!intel_encoder->base.crtc)
9877 continue;
9878
9879 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
9880
9881 if (prepare_pipes & (1 << intel_crtc->pipe))
9882 intel_encoder->connectors_active = false;
9883 }
9884
9885 intel_modeset_commit_output_state(dev);
9886
9887 /* Double check state. */
9888 for_each_intel_crtc(dev, intel_crtc) {
9889 WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base));
9890 WARN_ON(intel_crtc->new_config &&
9891 intel_crtc->new_config != &intel_crtc->config);
9892 WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config);
9893 }
9894
9895 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
9896 if (!connector->encoder || !connector->encoder->crtc)
9897 continue;
9898
9899 intel_crtc = to_intel_crtc(connector->encoder->crtc);
9900
9901 if (prepare_pipes & (1 << intel_crtc->pipe)) {
9902 struct drm_property *dpms_property =
9903 dev->mode_config.dpms_property;
9904
9905 connector->dpms = DRM_MODE_DPMS_ON;
9906 drm_object_property_set_value(&connector->base,
9907 dpms_property,
9908 DRM_MODE_DPMS_ON);
9909
9910 intel_encoder = to_intel_encoder(connector->encoder);
9911 intel_encoder->connectors_active = true;
9912 }
9913 }
9914
9915 }
9916
9917 static bool intel_fuzzy_clock_check(int clock1, int clock2)
9918 {
9919 int diff;
9920
9921 if (clock1 == clock2)
9922 return true;
9923
9924 if (!clock1 || !clock2)
9925 return false;
9926
9927 diff = abs(clock1 - clock2);
9928
9929 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
9930 return true;
9931
9932 return false;
9933 }
9934
9935 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
9936 list_for_each_entry((intel_crtc), \
9937 &(dev)->mode_config.crtc_list, \
9938 base.head) \
9939 if (mask & (1 <<(intel_crtc)->pipe))
9940
9941 static bool
9942 intel_pipe_config_compare(struct drm_device *dev,
9943 struct intel_crtc_config *current_config,
9944 struct intel_crtc_config *pipe_config)
9945 {
9946 #define PIPE_CONF_CHECK_X(name) \
9947 if (current_config->name != pipe_config->name) { \
9948 DRM_ERROR("mismatch in " #name " " \
9949 "(expected 0x%08x, found 0x%08x)\n", \
9950 current_config->name, \
9951 pipe_config->name); \
9952 return false; \
9953 }
9954
9955 #define PIPE_CONF_CHECK_I(name) \
9956 if (current_config->name != pipe_config->name) { \
9957 DRM_ERROR("mismatch in " #name " " \
9958 "(expected %i, found %i)\n", \
9959 current_config->name, \
9960 pipe_config->name); \
9961 return false; \
9962 }
9963
9964 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
9965 if ((current_config->name ^ pipe_config->name) & (mask)) { \
9966 DRM_ERROR("mismatch in " #name "(" #mask ") " \
9967 "(expected %i, found %i)\n", \
9968 current_config->name & (mask), \
9969 pipe_config->name & (mask)); \
9970 return false; \
9971 }
9972
9973 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
9974 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
9975 DRM_ERROR("mismatch in " #name " " \
9976 "(expected %i, found %i)\n", \
9977 current_config->name, \
9978 pipe_config->name); \
9979 return false; \
9980 }
9981
9982 #define PIPE_CONF_QUIRK(quirk) \
9983 ((current_config->quirks | pipe_config->quirks) & (quirk))
9984
9985 PIPE_CONF_CHECK_I(cpu_transcoder);
9986
9987 PIPE_CONF_CHECK_I(has_pch_encoder);
9988 PIPE_CONF_CHECK_I(fdi_lanes);
9989 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
9990 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
9991 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
9992 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
9993 PIPE_CONF_CHECK_I(fdi_m_n.tu);
9994
9995 PIPE_CONF_CHECK_I(has_dp_encoder);
9996 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
9997 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
9998 PIPE_CONF_CHECK_I(dp_m_n.link_m);
9999 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10000 PIPE_CONF_CHECK_I(dp_m_n.tu);
10001
10002 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
10003 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
10004 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
10005 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
10006 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
10007 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
10008
10009 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
10010 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
10011 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
10012 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
10013 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
10014 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
10015
10016 PIPE_CONF_CHECK_I(pixel_multiplier);
10017 PIPE_CONF_CHECK_I(has_hdmi_sink);
10018 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10019 IS_VALLEYVIEW(dev))
10020 PIPE_CONF_CHECK_I(limited_color_range);
10021
10022 PIPE_CONF_CHECK_I(has_audio);
10023
10024 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10025 DRM_MODE_FLAG_INTERLACE);
10026
10027 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
10028 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10029 DRM_MODE_FLAG_PHSYNC);
10030 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10031 DRM_MODE_FLAG_NHSYNC);
10032 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10033 DRM_MODE_FLAG_PVSYNC);
10034 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
10035 DRM_MODE_FLAG_NVSYNC);
10036 }
10037
10038 PIPE_CONF_CHECK_I(pipe_src_w);
10039 PIPE_CONF_CHECK_I(pipe_src_h);
10040
10041 /*
10042 * FIXME: BIOS likes to set up a cloned config with lvds+external
10043 * screen. Since we don't yet re-compute the pipe config when moving
10044 * just the lvds port away to another pipe the sw tracking won't match.
10045 *
10046 * Proper atomic modesets with recomputed global state will fix this.
10047 * Until then just don't check gmch state for inherited modes.
10048 */
10049 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10050 PIPE_CONF_CHECK_I(gmch_pfit.control);
10051 /* pfit ratios are autocomputed by the hw on gen4+ */
10052 if (INTEL_INFO(dev)->gen < 4)
10053 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10054 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10055 }
10056
10057 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10058 if (current_config->pch_pfit.enabled) {
10059 PIPE_CONF_CHECK_I(pch_pfit.pos);
10060 PIPE_CONF_CHECK_I(pch_pfit.size);
10061 }
10062
10063 /* BDW+ don't expose a synchronous way to read the state */
10064 if (IS_HASWELL(dev))
10065 PIPE_CONF_CHECK_I(ips_enabled);
10066
10067 PIPE_CONF_CHECK_I(double_wide);
10068
10069 PIPE_CONF_CHECK_I(shared_dpll);
10070 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
10071 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
10072 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10073 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
10074
10075 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10076 PIPE_CONF_CHECK_I(pipe_bpp);
10077
10078 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
10079 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
10080
10081 #undef PIPE_CONF_CHECK_X
10082 #undef PIPE_CONF_CHECK_I
10083 #undef PIPE_CONF_CHECK_FLAGS
10084 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
10085 #undef PIPE_CONF_QUIRK
10086
10087 return true;
10088 }
10089
10090 static void
10091 check_connector_state(struct drm_device *dev)
10092 {
10093 struct intel_connector *connector;
10094
10095 list_for_each_entry(connector, &dev->mode_config.connector_list,
10096 base.head) {
10097 /* This also checks the encoder/connector hw state with the
10098 * ->get_hw_state callbacks. */
10099 intel_connector_check_state(connector);
10100
10101 WARN(&connector->new_encoder->base != connector->base.encoder,
10102 "connector's staged encoder doesn't match current encoder\n");
10103 }
10104 }
10105
10106 static void
10107 check_encoder_state(struct drm_device *dev)
10108 {
10109 struct intel_encoder *encoder;
10110 struct intel_connector *connector;
10111
10112 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10113 base.head) {
10114 bool enabled = false;
10115 bool active = false;
10116 enum pipe pipe, tracked_pipe;
10117
10118 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
10119 encoder->base.base.id,
10120 encoder->base.name);
10121
10122 WARN(&encoder->new_crtc->base != encoder->base.crtc,
10123 "encoder's stage crtc doesn't match current crtc\n");
10124 WARN(encoder->connectors_active && !encoder->base.crtc,
10125 "encoder's active_connectors set, but no crtc\n");
10126
10127 list_for_each_entry(connector, &dev->mode_config.connector_list,
10128 base.head) {
10129 if (connector->base.encoder != &encoder->base)
10130 continue;
10131 enabled = true;
10132 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
10133 active = true;
10134 }
10135 WARN(!!encoder->base.crtc != enabled,
10136 "encoder's enabled state mismatch "
10137 "(expected %i, found %i)\n",
10138 !!encoder->base.crtc, enabled);
10139 WARN(active && !encoder->base.crtc,
10140 "active encoder with no crtc\n");
10141
10142 WARN(encoder->connectors_active != active,
10143 "encoder's computed active state doesn't match tracked active state "
10144 "(expected %i, found %i)\n", active, encoder->connectors_active);
10145
10146 active = encoder->get_hw_state(encoder, &pipe);
10147 WARN(active != encoder->connectors_active,
10148 "encoder's hw state doesn't match sw tracking "
10149 "(expected %i, found %i)\n",
10150 encoder->connectors_active, active);
10151
10152 if (!encoder->base.crtc)
10153 continue;
10154
10155 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
10156 WARN(active && pipe != tracked_pipe,
10157 "active encoder's pipe doesn't match"
10158 "(expected %i, found %i)\n",
10159 tracked_pipe, pipe);
10160
10161 }
10162 }
10163
10164 static void
10165 check_crtc_state(struct drm_device *dev)
10166 {
10167 struct drm_i915_private *dev_priv = dev->dev_private;
10168 struct intel_crtc *crtc;
10169 struct intel_encoder *encoder;
10170 struct intel_crtc_config pipe_config;
10171
10172 for_each_intel_crtc(dev, crtc) {
10173 bool enabled = false;
10174 bool active = false;
10175
10176 memset(&pipe_config, 0, sizeof(pipe_config));
10177
10178 DRM_DEBUG_KMS("[CRTC:%d]\n",
10179 crtc->base.base.id);
10180
10181 WARN(crtc->active && !crtc->base.enabled,
10182 "active crtc, but not enabled in sw tracking\n");
10183
10184 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10185 base.head) {
10186 if (encoder->base.crtc != &crtc->base)
10187 continue;
10188 enabled = true;
10189 if (encoder->connectors_active)
10190 active = true;
10191 }
10192
10193 WARN(active != crtc->active,
10194 "crtc's computed active state doesn't match tracked active state "
10195 "(expected %i, found %i)\n", active, crtc->active);
10196 WARN(enabled != crtc->base.enabled,
10197 "crtc's computed enabled state doesn't match tracked enabled state "
10198 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
10199
10200 active = dev_priv->display.get_pipe_config(crtc,
10201 &pipe_config);
10202
10203 /* hw state is inconsistent with the pipe A quirk */
10204 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
10205 active = crtc->active;
10206
10207 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10208 base.head) {
10209 enum pipe pipe;
10210 if (encoder->base.crtc != &crtc->base)
10211 continue;
10212 if (encoder->get_hw_state(encoder, &pipe))
10213 encoder->get_config(encoder, &pipe_config);
10214 }
10215
10216 WARN(crtc->active != active,
10217 "crtc active state doesn't match with hw state "
10218 "(expected %i, found %i)\n", crtc->active, active);
10219
10220 if (active &&
10221 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
10222 WARN(1, "pipe state doesn't match!\n");
10223 intel_dump_pipe_config(crtc, &pipe_config,
10224 "[hw state]");
10225 intel_dump_pipe_config(crtc, &crtc->config,
10226 "[sw state]");
10227 }
10228 }
10229 }
10230
10231 static void
10232 check_shared_dpll_state(struct drm_device *dev)
10233 {
10234 struct drm_i915_private *dev_priv = dev->dev_private;
10235 struct intel_crtc *crtc;
10236 struct intel_dpll_hw_state dpll_hw_state;
10237 int i;
10238
10239 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10240 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10241 int enabled_crtcs = 0, active_crtcs = 0;
10242 bool active;
10243
10244 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
10245
10246 DRM_DEBUG_KMS("%s\n", pll->name);
10247
10248 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
10249
10250 WARN(pll->active > pll->refcount,
10251 "more active pll users than references: %i vs %i\n",
10252 pll->active, pll->refcount);
10253 WARN(pll->active && !pll->on,
10254 "pll in active use but not on in sw tracking\n");
10255 WARN(pll->on && !pll->active,
10256 "pll in on but not on in use in sw tracking\n");
10257 WARN(pll->on != active,
10258 "pll on state mismatch (expected %i, found %i)\n",
10259 pll->on, active);
10260
10261 for_each_intel_crtc(dev, crtc) {
10262 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
10263 enabled_crtcs++;
10264 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10265 active_crtcs++;
10266 }
10267 WARN(pll->active != active_crtcs,
10268 "pll active crtcs mismatch (expected %i, found %i)\n",
10269 pll->active, active_crtcs);
10270 WARN(pll->refcount != enabled_crtcs,
10271 "pll enabled crtcs mismatch (expected %i, found %i)\n",
10272 pll->refcount, enabled_crtcs);
10273
10274 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
10275 sizeof(dpll_hw_state)),
10276 "pll hw state mismatch\n");
10277 }
10278 }
10279
10280 void
10281 intel_modeset_check_state(struct drm_device *dev)
10282 {
10283 check_connector_state(dev);
10284 check_encoder_state(dev);
10285 check_crtc_state(dev);
10286 check_shared_dpll_state(dev);
10287 }
10288
10289 void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
10290 int dotclock)
10291 {
10292 /*
10293 * FDI already provided one idea for the dotclock.
10294 * Yell if the encoder disagrees.
10295 */
10296 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
10297 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
10298 pipe_config->adjusted_mode.crtc_clock, dotclock);
10299 }
10300
10301 static void update_scanline_offset(struct intel_crtc *crtc)
10302 {
10303 struct drm_device *dev = crtc->base.dev;
10304
10305 /*
10306 * The scanline counter increments at the leading edge of hsync.
10307 *
10308 * On most platforms it starts counting from vtotal-1 on the
10309 * first active line. That means the scanline counter value is
10310 * always one less than what we would expect. Ie. just after
10311 * start of vblank, which also occurs at start of hsync (on the
10312 * last active line), the scanline counter will read vblank_start-1.
10313 *
10314 * On gen2 the scanline counter starts counting from 1 instead
10315 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
10316 * to keep the value positive), instead of adding one.
10317 *
10318 * On HSW+ the behaviour of the scanline counter depends on the output
10319 * type. For DP ports it behaves like most other platforms, but on HDMI
10320 * there's an extra 1 line difference. So we need to add two instead of
10321 * one to the value.
10322 */
10323 if (IS_GEN2(dev)) {
10324 const struct drm_display_mode *mode = &crtc->config.adjusted_mode;
10325 int vtotal;
10326
10327 vtotal = mode->crtc_vtotal;
10328 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
10329 vtotal /= 2;
10330
10331 crtc->scanline_offset = vtotal - 1;
10332 } else if (HAS_DDI(dev) &&
10333 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) {
10334 crtc->scanline_offset = 2;
10335 } else
10336 crtc->scanline_offset = 1;
10337 }
10338
10339 static int __intel_set_mode(struct drm_crtc *crtc,
10340 struct drm_display_mode *mode,
10341 int x, int y, struct drm_framebuffer *fb)
10342 {
10343 struct drm_device *dev = crtc->dev;
10344 struct drm_i915_private *dev_priv = dev->dev_private;
10345 struct drm_display_mode *saved_mode;
10346 struct intel_crtc_config *pipe_config = NULL;
10347 struct intel_crtc *intel_crtc;
10348 unsigned disable_pipes, prepare_pipes, modeset_pipes;
10349 int ret = 0;
10350
10351 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
10352 if (!saved_mode)
10353 return -ENOMEM;
10354
10355 intel_modeset_affected_pipes(crtc, &modeset_pipes,
10356 &prepare_pipes, &disable_pipes);
10357
10358 *saved_mode = crtc->mode;
10359
10360 /* Hack: Because we don't (yet) support global modeset on multiple
10361 * crtcs, we don't keep track of the new mode for more than one crtc.
10362 * Hence simply check whether any bit is set in modeset_pipes in all the
10363 * pieces of code that are not yet converted to deal with mutliple crtcs
10364 * changing their mode at the same time. */
10365 if (modeset_pipes) {
10366 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
10367 if (IS_ERR(pipe_config)) {
10368 ret = PTR_ERR(pipe_config);
10369 pipe_config = NULL;
10370
10371 goto out;
10372 }
10373 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
10374 "[modeset]");
10375 to_intel_crtc(crtc)->new_config = pipe_config;
10376 }
10377
10378 /*
10379 * See if the config requires any additional preparation, e.g.
10380 * to adjust global state with pipes off. We need to do this
10381 * here so we can get the modeset_pipe updated config for the new
10382 * mode set on this crtc. For other crtcs we need to use the
10383 * adjusted_mode bits in the crtc directly.
10384 */
10385 if (IS_VALLEYVIEW(dev)) {
10386 valleyview_modeset_global_pipes(dev, &prepare_pipes);
10387
10388 /* may have added more to prepare_pipes than we should */
10389 prepare_pipes &= ~disable_pipes;
10390 }
10391
10392 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
10393 intel_crtc_disable(&intel_crtc->base);
10394
10395 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10396 if (intel_crtc->base.enabled)
10397 dev_priv->display.crtc_disable(&intel_crtc->base);
10398 }
10399
10400 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
10401 * to set it here already despite that we pass it down the callchain.
10402 */
10403 if (modeset_pipes) {
10404 crtc->mode = *mode;
10405 /* mode_set/enable/disable functions rely on a correct pipe
10406 * config. */
10407 to_intel_crtc(crtc)->config = *pipe_config;
10408 to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config;
10409
10410 /*
10411 * Calculate and store various constants which
10412 * are later needed by vblank and swap-completion
10413 * timestamping. They are derived from true hwmode.
10414 */
10415 drm_calc_timestamping_constants(crtc,
10416 &pipe_config->adjusted_mode);
10417 }
10418
10419 /* Only after disabling all output pipelines that will be changed can we
10420 * update the the output configuration. */
10421 intel_modeset_update_state(dev, prepare_pipes);
10422
10423 if (dev_priv->display.modeset_global_resources)
10424 dev_priv->display.modeset_global_resources(dev);
10425
10426 /* Set up the DPLL and any encoders state that needs to adjust or depend
10427 * on the DPLL.
10428 */
10429 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
10430 struct drm_framebuffer *old_fb;
10431
10432 mutex_lock(&dev->struct_mutex);
10433 ret = intel_pin_and_fence_fb_obj(dev,
10434 to_intel_framebuffer(fb)->obj,
10435 NULL);
10436 if (ret != 0) {
10437 DRM_ERROR("pin & fence failed\n");
10438 mutex_unlock(&dev->struct_mutex);
10439 goto done;
10440 }
10441 old_fb = crtc->primary->fb;
10442 if (old_fb)
10443 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
10444 mutex_unlock(&dev->struct_mutex);
10445
10446 crtc->primary->fb = fb;
10447 crtc->x = x;
10448 crtc->y = y;
10449
10450 ret = dev_priv->display.crtc_mode_set(&intel_crtc->base,
10451 x, y, fb);
10452 if (ret)
10453 goto done;
10454 }
10455
10456 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
10457 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
10458 update_scanline_offset(intel_crtc);
10459
10460 dev_priv->display.crtc_enable(&intel_crtc->base);
10461 }
10462
10463 /* FIXME: add subpixel order */
10464 done:
10465 if (ret && crtc->enabled)
10466 crtc->mode = *saved_mode;
10467
10468 out:
10469 kfree(pipe_config);
10470 kfree(saved_mode);
10471 return ret;
10472 }
10473
10474 static int intel_set_mode(struct drm_crtc *crtc,
10475 struct drm_display_mode *mode,
10476 int x, int y, struct drm_framebuffer *fb)
10477 {
10478 int ret;
10479
10480 ret = __intel_set_mode(crtc, mode, x, y, fb);
10481
10482 if (ret == 0)
10483 intel_modeset_check_state(crtc->dev);
10484
10485 return ret;
10486 }
10487
10488 void intel_crtc_restore_mode(struct drm_crtc *crtc)
10489 {
10490 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
10491 }
10492
10493 #undef for_each_intel_crtc_masked
10494
10495 static void intel_set_config_free(struct intel_set_config *config)
10496 {
10497 if (!config)
10498 return;
10499
10500 kfree(config->save_connector_encoders);
10501 kfree(config->save_encoder_crtcs);
10502 kfree(config->save_crtc_enabled);
10503 kfree(config);
10504 }
10505
10506 static int intel_set_config_save_state(struct drm_device *dev,
10507 struct intel_set_config *config)
10508 {
10509 struct drm_crtc *crtc;
10510 struct drm_encoder *encoder;
10511 struct drm_connector *connector;
10512 int count;
10513
10514 config->save_crtc_enabled =
10515 kcalloc(dev->mode_config.num_crtc,
10516 sizeof(bool), GFP_KERNEL);
10517 if (!config->save_crtc_enabled)
10518 return -ENOMEM;
10519
10520 config->save_encoder_crtcs =
10521 kcalloc(dev->mode_config.num_encoder,
10522 sizeof(struct drm_crtc *), GFP_KERNEL);
10523 if (!config->save_encoder_crtcs)
10524 return -ENOMEM;
10525
10526 config->save_connector_encoders =
10527 kcalloc(dev->mode_config.num_connector,
10528 sizeof(struct drm_encoder *), GFP_KERNEL);
10529 if (!config->save_connector_encoders)
10530 return -ENOMEM;
10531
10532 /* Copy data. Note that driver private data is not affected.
10533 * Should anything bad happen only the expected state is
10534 * restored, not the drivers personal bookkeeping.
10535 */
10536 count = 0;
10537 for_each_crtc(dev, crtc) {
10538 config->save_crtc_enabled[count++] = crtc->enabled;
10539 }
10540
10541 count = 0;
10542 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
10543 config->save_encoder_crtcs[count++] = encoder->crtc;
10544 }
10545
10546 count = 0;
10547 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10548 config->save_connector_encoders[count++] = connector->encoder;
10549 }
10550
10551 return 0;
10552 }
10553
10554 static void intel_set_config_restore_state(struct drm_device *dev,
10555 struct intel_set_config *config)
10556 {
10557 struct intel_crtc *crtc;
10558 struct intel_encoder *encoder;
10559 struct intel_connector *connector;
10560 int count;
10561
10562 count = 0;
10563 for_each_intel_crtc(dev, crtc) {
10564 crtc->new_enabled = config->save_crtc_enabled[count++];
10565
10566 if (crtc->new_enabled)
10567 crtc->new_config = &crtc->config;
10568 else
10569 crtc->new_config = NULL;
10570 }
10571
10572 count = 0;
10573 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10574 encoder->new_crtc =
10575 to_intel_crtc(config->save_encoder_crtcs[count++]);
10576 }
10577
10578 count = 0;
10579 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10580 connector->new_encoder =
10581 to_intel_encoder(config->save_connector_encoders[count++]);
10582 }
10583 }
10584
10585 static bool
10586 is_crtc_connector_off(struct drm_mode_set *set)
10587 {
10588 int i;
10589
10590 if (set->num_connectors == 0)
10591 return false;
10592
10593 if (WARN_ON(set->connectors == NULL))
10594 return false;
10595
10596 for (i = 0; i < set->num_connectors; i++)
10597 if (set->connectors[i]->encoder &&
10598 set->connectors[i]->encoder->crtc == set->crtc &&
10599 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
10600 return true;
10601
10602 return false;
10603 }
10604
10605 static void
10606 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
10607 struct intel_set_config *config)
10608 {
10609
10610 /* We should be able to check here if the fb has the same properties
10611 * and then just flip_or_move it */
10612 if (is_crtc_connector_off(set)) {
10613 config->mode_changed = true;
10614 } else if (set->crtc->primary->fb != set->fb) {
10615 /*
10616 * If we have no fb, we can only flip as long as the crtc is
10617 * active, otherwise we need a full mode set. The crtc may
10618 * be active if we've only disabled the primary plane, or
10619 * in fastboot situations.
10620 */
10621 if (set->crtc->primary->fb == NULL) {
10622 struct intel_crtc *intel_crtc =
10623 to_intel_crtc(set->crtc);
10624
10625 if (intel_crtc->active) {
10626 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
10627 config->fb_changed = true;
10628 } else {
10629 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
10630 config->mode_changed = true;
10631 }
10632 } else if (set->fb == NULL) {
10633 config->mode_changed = true;
10634 } else if (set->fb->pixel_format !=
10635 set->crtc->primary->fb->pixel_format) {
10636 config->mode_changed = true;
10637 } else {
10638 config->fb_changed = true;
10639 }
10640 }
10641
10642 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
10643 config->fb_changed = true;
10644
10645 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
10646 DRM_DEBUG_KMS("modes are different, full mode set\n");
10647 drm_mode_debug_printmodeline(&set->crtc->mode);
10648 drm_mode_debug_printmodeline(set->mode);
10649 config->mode_changed = true;
10650 }
10651
10652 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
10653 set->crtc->base.id, config->mode_changed, config->fb_changed);
10654 }
10655
10656 static int
10657 intel_modeset_stage_output_state(struct drm_device *dev,
10658 struct drm_mode_set *set,
10659 struct intel_set_config *config)
10660 {
10661 struct intel_connector *connector;
10662 struct intel_encoder *encoder;
10663 struct intel_crtc *crtc;
10664 int ro;
10665
10666 /* The upper layers ensure that we either disable a crtc or have a list
10667 * of connectors. For paranoia, double-check this. */
10668 WARN_ON(!set->fb && (set->num_connectors != 0));
10669 WARN_ON(set->fb && (set->num_connectors == 0));
10670
10671 list_for_each_entry(connector, &dev->mode_config.connector_list,
10672 base.head) {
10673 /* Otherwise traverse passed in connector list and get encoders
10674 * for them. */
10675 for (ro = 0; ro < set->num_connectors; ro++) {
10676 if (set->connectors[ro] == &connector->base) {
10677 connector->new_encoder = connector->encoder;
10678 break;
10679 }
10680 }
10681
10682 /* If we disable the crtc, disable all its connectors. Also, if
10683 * the connector is on the changing crtc but not on the new
10684 * connector list, disable it. */
10685 if ((!set->fb || ro == set->num_connectors) &&
10686 connector->base.encoder &&
10687 connector->base.encoder->crtc == set->crtc) {
10688 connector->new_encoder = NULL;
10689
10690 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
10691 connector->base.base.id,
10692 connector->base.name);
10693 }
10694
10695
10696 if (&connector->new_encoder->base != connector->base.encoder) {
10697 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
10698 config->mode_changed = true;
10699 }
10700 }
10701 /* connector->new_encoder is now updated for all connectors. */
10702
10703 /* Update crtc of enabled connectors. */
10704 list_for_each_entry(connector, &dev->mode_config.connector_list,
10705 base.head) {
10706 struct drm_crtc *new_crtc;
10707
10708 if (!connector->new_encoder)
10709 continue;
10710
10711 new_crtc = connector->new_encoder->base.crtc;
10712
10713 for (ro = 0; ro < set->num_connectors; ro++) {
10714 if (set->connectors[ro] == &connector->base)
10715 new_crtc = set->crtc;
10716 }
10717
10718 /* Make sure the new CRTC will work with the encoder */
10719 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
10720 new_crtc)) {
10721 return -EINVAL;
10722 }
10723 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
10724
10725 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
10726 connector->base.base.id,
10727 connector->base.name,
10728 new_crtc->base.id);
10729 }
10730
10731 /* Check for any encoders that needs to be disabled. */
10732 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10733 base.head) {
10734 int num_connectors = 0;
10735 list_for_each_entry(connector,
10736 &dev->mode_config.connector_list,
10737 base.head) {
10738 if (connector->new_encoder == encoder) {
10739 WARN_ON(!connector->new_encoder->new_crtc);
10740 num_connectors++;
10741 }
10742 }
10743
10744 if (num_connectors == 0)
10745 encoder->new_crtc = NULL;
10746 else if (num_connectors > 1)
10747 return -EINVAL;
10748
10749 /* Only now check for crtc changes so we don't miss encoders
10750 * that will be disabled. */
10751 if (&encoder->new_crtc->base != encoder->base.crtc) {
10752 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
10753 config->mode_changed = true;
10754 }
10755 }
10756 /* Now we've also updated encoder->new_crtc for all encoders. */
10757
10758 for_each_intel_crtc(dev, crtc) {
10759 crtc->new_enabled = false;
10760
10761 list_for_each_entry(encoder,
10762 &dev->mode_config.encoder_list,
10763 base.head) {
10764 if (encoder->new_crtc == crtc) {
10765 crtc->new_enabled = true;
10766 break;
10767 }
10768 }
10769
10770 if (crtc->new_enabled != crtc->base.enabled) {
10771 DRM_DEBUG_KMS("crtc %sabled, full mode switch\n",
10772 crtc->new_enabled ? "en" : "dis");
10773 config->mode_changed = true;
10774 }
10775
10776 if (crtc->new_enabled)
10777 crtc->new_config = &crtc->config;
10778 else
10779 crtc->new_config = NULL;
10780 }
10781
10782 return 0;
10783 }
10784
10785 static void disable_crtc_nofb(struct intel_crtc *crtc)
10786 {
10787 struct drm_device *dev = crtc->base.dev;
10788 struct intel_encoder *encoder;
10789 struct intel_connector *connector;
10790
10791 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
10792 pipe_name(crtc->pipe));
10793
10794 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
10795 if (connector->new_encoder &&
10796 connector->new_encoder->new_crtc == crtc)
10797 connector->new_encoder = NULL;
10798 }
10799
10800 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
10801 if (encoder->new_crtc == crtc)
10802 encoder->new_crtc = NULL;
10803 }
10804
10805 crtc->new_enabled = false;
10806 crtc->new_config = NULL;
10807 }
10808
10809 static int intel_crtc_set_config(struct drm_mode_set *set)
10810 {
10811 struct drm_device *dev;
10812 struct drm_mode_set save_set;
10813 struct intel_set_config *config;
10814 int ret;
10815
10816 BUG_ON(!set);
10817 BUG_ON(!set->crtc);
10818 BUG_ON(!set->crtc->helper_private);
10819
10820 /* Enforce sane interface api - has been abused by the fb helper. */
10821 BUG_ON(!set->mode && set->fb);
10822 BUG_ON(set->fb && set->num_connectors == 0);
10823
10824 if (set->fb) {
10825 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
10826 set->crtc->base.id, set->fb->base.id,
10827 (int)set->num_connectors, set->x, set->y);
10828 } else {
10829 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
10830 }
10831
10832 dev = set->crtc->dev;
10833
10834 ret = -ENOMEM;
10835 config = kzalloc(sizeof(*config), GFP_KERNEL);
10836 if (!config)
10837 goto out_config;
10838
10839 ret = intel_set_config_save_state(dev, config);
10840 if (ret)
10841 goto out_config;
10842
10843 save_set.crtc = set->crtc;
10844 save_set.mode = &set->crtc->mode;
10845 save_set.x = set->crtc->x;
10846 save_set.y = set->crtc->y;
10847 save_set.fb = set->crtc->primary->fb;
10848
10849 /* Compute whether we need a full modeset, only an fb base update or no
10850 * change at all. In the future we might also check whether only the
10851 * mode changed, e.g. for LVDS where we only change the panel fitter in
10852 * such cases. */
10853 intel_set_config_compute_mode_changes(set, config);
10854
10855 ret = intel_modeset_stage_output_state(dev, set, config);
10856 if (ret)
10857 goto fail;
10858
10859 if (config->mode_changed) {
10860 ret = intel_set_mode(set->crtc, set->mode,
10861 set->x, set->y, set->fb);
10862 } else if (config->fb_changed) {
10863 struct drm_i915_private *dev_priv = dev->dev_private;
10864 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
10865
10866 intel_crtc_wait_for_pending_flips(set->crtc);
10867
10868 ret = intel_pipe_set_base(set->crtc,
10869 set->x, set->y, set->fb);
10870
10871 /*
10872 * We need to make sure the primary plane is re-enabled if it
10873 * has previously been turned off.
10874 */
10875 if (!intel_crtc->primary_enabled && ret == 0) {
10876 WARN_ON(!intel_crtc->active);
10877 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
10878 intel_crtc->pipe);
10879 }
10880
10881 /*
10882 * In the fastboot case this may be our only check of the
10883 * state after boot. It would be better to only do it on
10884 * the first update, but we don't have a nice way of doing that
10885 * (and really, set_config isn't used much for high freq page
10886 * flipping, so increasing its cost here shouldn't be a big
10887 * deal).
10888 */
10889 if (i915.fastboot && ret == 0)
10890 intel_modeset_check_state(set->crtc->dev);
10891 }
10892
10893 if (ret) {
10894 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
10895 set->crtc->base.id, ret);
10896 fail:
10897 intel_set_config_restore_state(dev, config);
10898
10899 /*
10900 * HACK: if the pipe was on, but we didn't have a framebuffer,
10901 * force the pipe off to avoid oopsing in the modeset code
10902 * due to fb==NULL. This should only happen during boot since
10903 * we don't yet reconstruct the FB from the hardware state.
10904 */
10905 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
10906 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
10907
10908 /* Try to restore the config */
10909 if (config->mode_changed &&
10910 intel_set_mode(save_set.crtc, save_set.mode,
10911 save_set.x, save_set.y, save_set.fb))
10912 DRM_ERROR("failed to restore config after modeset failure\n");
10913 }
10914
10915 out_config:
10916 intel_set_config_free(config);
10917 return ret;
10918 }
10919
10920 static const struct drm_crtc_funcs intel_crtc_funcs = {
10921 .gamma_set = intel_crtc_gamma_set,
10922 .set_config = intel_crtc_set_config,
10923 .destroy = intel_crtc_destroy,
10924 .page_flip = intel_crtc_page_flip,
10925 };
10926
10927 static void intel_cpu_pll_init(struct drm_device *dev)
10928 {
10929 if (HAS_DDI(dev))
10930 intel_ddi_pll_init(dev);
10931 }
10932
10933 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
10934 struct intel_shared_dpll *pll,
10935 struct intel_dpll_hw_state *hw_state)
10936 {
10937 uint32_t val;
10938
10939 val = I915_READ(PCH_DPLL(pll->id));
10940 hw_state->dpll = val;
10941 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
10942 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
10943
10944 return val & DPLL_VCO_ENABLE;
10945 }
10946
10947 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
10948 struct intel_shared_dpll *pll)
10949 {
10950 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
10951 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
10952 }
10953
10954 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
10955 struct intel_shared_dpll *pll)
10956 {
10957 /* PCH refclock must be enabled first */
10958 ibx_assert_pch_refclk_enabled(dev_priv);
10959
10960 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10961
10962 /* Wait for the clocks to stabilize. */
10963 POSTING_READ(PCH_DPLL(pll->id));
10964 udelay(150);
10965
10966 /* The pixel multiplier can only be updated once the
10967 * DPLL is enabled and the clocks are stable.
10968 *
10969 * So write it again.
10970 */
10971 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
10972 POSTING_READ(PCH_DPLL(pll->id));
10973 udelay(200);
10974 }
10975
10976 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
10977 struct intel_shared_dpll *pll)
10978 {
10979 struct drm_device *dev = dev_priv->dev;
10980 struct intel_crtc *crtc;
10981
10982 /* Make sure no transcoder isn't still depending on us. */
10983 for_each_intel_crtc(dev, crtc) {
10984 if (intel_crtc_to_shared_dpll(crtc) == pll)
10985 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
10986 }
10987
10988 I915_WRITE(PCH_DPLL(pll->id), 0);
10989 POSTING_READ(PCH_DPLL(pll->id));
10990 udelay(200);
10991 }
10992
10993 static char *ibx_pch_dpll_names[] = {
10994 "PCH DPLL A",
10995 "PCH DPLL B",
10996 };
10997
10998 static void ibx_pch_dpll_init(struct drm_device *dev)
10999 {
11000 struct drm_i915_private *dev_priv = dev->dev_private;
11001 int i;
11002
11003 dev_priv->num_shared_dpll = 2;
11004
11005 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11006 dev_priv->shared_dplls[i].id = i;
11007 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
11008 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
11009 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
11010 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
11011 dev_priv->shared_dplls[i].get_hw_state =
11012 ibx_pch_dpll_get_hw_state;
11013 }
11014 }
11015
11016 static void intel_shared_dpll_init(struct drm_device *dev)
11017 {
11018 struct drm_i915_private *dev_priv = dev->dev_private;
11019
11020 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
11021 ibx_pch_dpll_init(dev);
11022 else
11023 dev_priv->num_shared_dpll = 0;
11024
11025 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
11026 }
11027
11028 static int
11029 intel_primary_plane_disable(struct drm_plane *plane)
11030 {
11031 struct drm_device *dev = plane->dev;
11032 struct drm_i915_private *dev_priv = dev->dev_private;
11033 struct intel_plane *intel_plane = to_intel_plane(plane);
11034 struct intel_crtc *intel_crtc;
11035
11036 if (!plane->fb)
11037 return 0;
11038
11039 BUG_ON(!plane->crtc);
11040
11041 intel_crtc = to_intel_crtc(plane->crtc);
11042
11043 /*
11044 * Even though we checked plane->fb above, it's still possible that
11045 * the primary plane has been implicitly disabled because the crtc
11046 * coordinates given weren't visible, or because we detected
11047 * that it was 100% covered by a sprite plane. Or, the CRTC may be
11048 * off and we've set a fb, but haven't actually turned on the CRTC yet.
11049 * In either case, we need to unpin the FB and let the fb pointer get
11050 * updated, but otherwise we don't need to touch the hardware.
11051 */
11052 if (!intel_crtc->primary_enabled)
11053 goto disable_unpin;
11054
11055 intel_crtc_wait_for_pending_flips(plane->crtc);
11056 intel_disable_primary_hw_plane(dev_priv, intel_plane->plane,
11057 intel_plane->pipe);
11058
11059 disable_unpin:
11060 intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
11061 plane->fb = NULL;
11062
11063 return 0;
11064 }
11065
11066 static int
11067 intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc,
11068 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11069 unsigned int crtc_w, unsigned int crtc_h,
11070 uint32_t src_x, uint32_t src_y,
11071 uint32_t src_w, uint32_t src_h)
11072 {
11073 struct drm_device *dev = crtc->dev;
11074 struct drm_i915_private *dev_priv = dev->dev_private;
11075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11076 struct intel_plane *intel_plane = to_intel_plane(plane);
11077 struct drm_rect dest = {
11078 /* integer pixels */
11079 .x1 = crtc_x,
11080 .y1 = crtc_y,
11081 .x2 = crtc_x + crtc_w,
11082 .y2 = crtc_y + crtc_h,
11083 };
11084 struct drm_rect src = {
11085 /* 16.16 fixed point */
11086 .x1 = src_x,
11087 .y1 = src_y,
11088 .x2 = src_x + src_w,
11089 .y2 = src_y + src_h,
11090 };
11091 const struct drm_rect clip = {
11092 /* integer pixels */
11093 .x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0,
11094 .y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0,
11095 };
11096 bool visible;
11097 int ret;
11098
11099 ret = drm_plane_helper_check_update(plane, crtc, fb,
11100 &src, &dest, &clip,
11101 DRM_PLANE_HELPER_NO_SCALING,
11102 DRM_PLANE_HELPER_NO_SCALING,
11103 false, true, &visible);
11104
11105 if (ret)
11106 return ret;
11107
11108 /*
11109 * If the CRTC isn't enabled, we're just pinning the framebuffer,
11110 * updating the fb pointer, and returning without touching the
11111 * hardware. This allows us to later do a drmModeSetCrtc with fb=-1 to
11112 * turn on the display with all planes setup as desired.
11113 */
11114 if (!crtc->enabled) {
11115 /*
11116 * If we already called setplane while the crtc was disabled,
11117 * we may have an fb pinned; unpin it.
11118 */
11119 if (plane->fb)
11120 intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
11121
11122 /* Pin and return without programming hardware */
11123 return intel_pin_and_fence_fb_obj(dev,
11124 to_intel_framebuffer(fb)->obj,
11125 NULL);
11126 }
11127
11128 intel_crtc_wait_for_pending_flips(crtc);
11129
11130 /*
11131 * If clipping results in a non-visible primary plane, we'll disable
11132 * the primary plane. Note that this is a bit different than what
11133 * happens if userspace explicitly disables the plane by passing fb=0
11134 * because plane->fb still gets set and pinned.
11135 */
11136 if (!visible) {
11137 /*
11138 * Try to pin the new fb first so that we can bail out if we
11139 * fail.
11140 */
11141 if (plane->fb != fb) {
11142 ret = intel_pin_and_fence_fb_obj(dev,
11143 to_intel_framebuffer(fb)->obj,
11144 NULL);
11145 if (ret)
11146 return ret;
11147 }
11148
11149 if (intel_crtc->primary_enabled)
11150 intel_disable_primary_hw_plane(dev_priv,
11151 intel_plane->plane,
11152 intel_plane->pipe);
11153
11154
11155 if (plane->fb != fb)
11156 if (plane->fb)
11157 intel_unpin_fb_obj(to_intel_framebuffer(plane->fb)->obj);
11158
11159 return 0;
11160 }
11161
11162 ret = intel_pipe_set_base(crtc, src.x1, src.y1, fb);
11163 if (ret)
11164 return ret;
11165
11166 if (!intel_crtc->primary_enabled)
11167 intel_enable_primary_hw_plane(dev_priv, intel_crtc->plane,
11168 intel_crtc->pipe);
11169
11170 return 0;
11171 }
11172
11173 /* Common destruction function for both primary and cursor planes */
11174 static void intel_plane_destroy(struct drm_plane *plane)
11175 {
11176 struct intel_plane *intel_plane = to_intel_plane(plane);
11177 drm_plane_cleanup(plane);
11178 kfree(intel_plane);
11179 }
11180
11181 static const struct drm_plane_funcs intel_primary_plane_funcs = {
11182 .update_plane = intel_primary_plane_setplane,
11183 .disable_plane = intel_primary_plane_disable,
11184 .destroy = intel_plane_destroy,
11185 };
11186
11187 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
11188 int pipe)
11189 {
11190 struct intel_plane *primary;
11191 const uint32_t *intel_primary_formats;
11192 int num_formats;
11193
11194 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
11195 if (primary == NULL)
11196 return NULL;
11197
11198 primary->can_scale = false;
11199 primary->max_downscale = 1;
11200 primary->pipe = pipe;
11201 primary->plane = pipe;
11202 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
11203 primary->plane = !pipe;
11204
11205 if (INTEL_INFO(dev)->gen <= 3) {
11206 intel_primary_formats = intel_primary_formats_gen2;
11207 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
11208 } else {
11209 intel_primary_formats = intel_primary_formats_gen4;
11210 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
11211 }
11212
11213 drm_universal_plane_init(dev, &primary->base, 0,
11214 &intel_primary_plane_funcs,
11215 intel_primary_formats, num_formats,
11216 DRM_PLANE_TYPE_PRIMARY);
11217 return &primary->base;
11218 }
11219
11220 static int
11221 intel_cursor_plane_disable(struct drm_plane *plane)
11222 {
11223 if (!plane->fb)
11224 return 0;
11225
11226 BUG_ON(!plane->crtc);
11227
11228 return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0);
11229 }
11230
11231 static int
11232 intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
11233 struct drm_framebuffer *fb, int crtc_x, int crtc_y,
11234 unsigned int crtc_w, unsigned int crtc_h,
11235 uint32_t src_x, uint32_t src_y,
11236 uint32_t src_w, uint32_t src_h)
11237 {
11238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11239 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11240 struct drm_i915_gem_object *obj = intel_fb->obj;
11241 struct drm_rect dest = {
11242 /* integer pixels */
11243 .x1 = crtc_x,
11244 .y1 = crtc_y,
11245 .x2 = crtc_x + crtc_w,
11246 .y2 = crtc_y + crtc_h,
11247 };
11248 struct drm_rect src = {
11249 /* 16.16 fixed point */
11250 .x1 = src_x,
11251 .y1 = src_y,
11252 .x2 = src_x + src_w,
11253 .y2 = src_y + src_h,
11254 };
11255 const struct drm_rect clip = {
11256 /* integer pixels */
11257 .x2 = intel_crtc->config.pipe_src_w,
11258 .y2 = intel_crtc->config.pipe_src_h,
11259 };
11260 bool visible;
11261 int ret;
11262
11263 ret = drm_plane_helper_check_update(plane, crtc, fb,
11264 &src, &dest, &clip,
11265 DRM_PLANE_HELPER_NO_SCALING,
11266 DRM_PLANE_HELPER_NO_SCALING,
11267 true, true, &visible);
11268 if (ret)
11269 return ret;
11270
11271 crtc->cursor_x = crtc_x;
11272 crtc->cursor_y = crtc_y;
11273 if (fb != crtc->cursor->fb) {
11274 return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h);
11275 } else {
11276 intel_crtc_update_cursor(crtc, visible);
11277 return 0;
11278 }
11279 }
11280 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
11281 .update_plane = intel_cursor_plane_update,
11282 .disable_plane = intel_cursor_plane_disable,
11283 .destroy = intel_plane_destroy,
11284 };
11285
11286 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
11287 int pipe)
11288 {
11289 struct intel_plane *cursor;
11290
11291 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
11292 if (cursor == NULL)
11293 return NULL;
11294
11295 cursor->can_scale = false;
11296 cursor->max_downscale = 1;
11297 cursor->pipe = pipe;
11298 cursor->plane = pipe;
11299
11300 drm_universal_plane_init(dev, &cursor->base, 0,
11301 &intel_cursor_plane_funcs,
11302 intel_cursor_formats,
11303 ARRAY_SIZE(intel_cursor_formats),
11304 DRM_PLANE_TYPE_CURSOR);
11305 return &cursor->base;
11306 }
11307
11308 static void intel_crtc_init(struct drm_device *dev, int pipe)
11309 {
11310 struct drm_i915_private *dev_priv = dev->dev_private;
11311 struct intel_crtc *intel_crtc;
11312 struct drm_plane *primary = NULL;
11313 struct drm_plane *cursor = NULL;
11314 int i, ret;
11315
11316 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
11317 if (intel_crtc == NULL)
11318 return;
11319
11320 primary = intel_primary_plane_create(dev, pipe);
11321 if (!primary)
11322 goto fail;
11323
11324 cursor = intel_cursor_plane_create(dev, pipe);
11325 if (!cursor)
11326 goto fail;
11327
11328 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
11329 cursor, &intel_crtc_funcs);
11330 if (ret)
11331 goto fail;
11332
11333 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
11334 for (i = 0; i < 256; i++) {
11335 intel_crtc->lut_r[i] = i;
11336 intel_crtc->lut_g[i] = i;
11337 intel_crtc->lut_b[i] = i;
11338 }
11339
11340 /*
11341 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
11342 * is hooked to plane B. Hence we want plane A feeding pipe B.
11343 */
11344 intel_crtc->pipe = pipe;
11345 intel_crtc->plane = pipe;
11346 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
11347 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
11348 intel_crtc->plane = !pipe;
11349 }
11350
11351 intel_crtc->cursor_base = ~0;
11352 intel_crtc->cursor_cntl = ~0;
11353
11354 init_waitqueue_head(&intel_crtc->vbl_wait);
11355
11356 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
11357 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
11358 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
11359 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
11360
11361 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
11362
11363 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
11364 return;
11365
11366 fail:
11367 if (primary)
11368 drm_plane_cleanup(primary);
11369 if (cursor)
11370 drm_plane_cleanup(cursor);
11371 kfree(intel_crtc);
11372 }
11373
11374 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
11375 {
11376 struct drm_encoder *encoder = connector->base.encoder;
11377 struct drm_device *dev = connector->base.dev;
11378
11379 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
11380
11381 if (!encoder)
11382 return INVALID_PIPE;
11383
11384 return to_intel_crtc(encoder->crtc)->pipe;
11385 }
11386
11387 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
11388 struct drm_file *file)
11389 {
11390 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
11391 struct drm_mode_object *drmmode_obj;
11392 struct intel_crtc *crtc;
11393
11394 if (!drm_core_check_feature(dev, DRIVER_MODESET))
11395 return -ENODEV;
11396
11397 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
11398 DRM_MODE_OBJECT_CRTC);
11399
11400 if (!drmmode_obj) {
11401 DRM_ERROR("no such CRTC id\n");
11402 return -ENOENT;
11403 }
11404
11405 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
11406 pipe_from_crtc_id->pipe = crtc->pipe;
11407
11408 return 0;
11409 }
11410
11411 static int intel_encoder_clones(struct intel_encoder *encoder)
11412 {
11413 struct drm_device *dev = encoder->base.dev;
11414 struct intel_encoder *source_encoder;
11415 int index_mask = 0;
11416 int entry = 0;
11417
11418 list_for_each_entry(source_encoder,
11419 &dev->mode_config.encoder_list, base.head) {
11420 if (encoders_cloneable(encoder, source_encoder))
11421 index_mask |= (1 << entry);
11422
11423 entry++;
11424 }
11425
11426 return index_mask;
11427 }
11428
11429 static bool has_edp_a(struct drm_device *dev)
11430 {
11431 struct drm_i915_private *dev_priv = dev->dev_private;
11432
11433 if (!IS_MOBILE(dev))
11434 return false;
11435
11436 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
11437 return false;
11438
11439 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
11440 return false;
11441
11442 return true;
11443 }
11444
11445 const char *intel_output_name(int output)
11446 {
11447 static const char *names[] = {
11448 [INTEL_OUTPUT_UNUSED] = "Unused",
11449 [INTEL_OUTPUT_ANALOG] = "Analog",
11450 [INTEL_OUTPUT_DVO] = "DVO",
11451 [INTEL_OUTPUT_SDVO] = "SDVO",
11452 [INTEL_OUTPUT_LVDS] = "LVDS",
11453 [INTEL_OUTPUT_TVOUT] = "TV",
11454 [INTEL_OUTPUT_HDMI] = "HDMI",
11455 [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort",
11456 [INTEL_OUTPUT_EDP] = "eDP",
11457 [INTEL_OUTPUT_DSI] = "DSI",
11458 [INTEL_OUTPUT_UNKNOWN] = "Unknown",
11459 };
11460
11461 if (output < 0 || output >= ARRAY_SIZE(names) || !names[output])
11462 return "Invalid";
11463
11464 return names[output];
11465 }
11466
11467 static void intel_setup_outputs(struct drm_device *dev)
11468 {
11469 struct drm_i915_private *dev_priv = dev->dev_private;
11470 struct intel_encoder *encoder;
11471 bool dpd_is_edp = false;
11472
11473 intel_lvds_init(dev);
11474
11475 if (!IS_ULT(dev) && !IS_CHERRYVIEW(dev) && dev_priv->vbt.int_crt_support)
11476 intel_crt_init(dev);
11477
11478 if (HAS_DDI(dev)) {
11479 int found;
11480
11481 /* Haswell uses DDI functions to detect digital outputs */
11482 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
11483 /* DDI A only supports eDP */
11484 if (found)
11485 intel_ddi_init(dev, PORT_A);
11486
11487 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
11488 * register */
11489 found = I915_READ(SFUSE_STRAP);
11490
11491 if (found & SFUSE_STRAP_DDIB_DETECTED)
11492 intel_ddi_init(dev, PORT_B);
11493 if (found & SFUSE_STRAP_DDIC_DETECTED)
11494 intel_ddi_init(dev, PORT_C);
11495 if (found & SFUSE_STRAP_DDID_DETECTED)
11496 intel_ddi_init(dev, PORT_D);
11497 } else if (HAS_PCH_SPLIT(dev)) {
11498 int found;
11499 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
11500
11501 if (has_edp_a(dev))
11502 intel_dp_init(dev, DP_A, PORT_A);
11503
11504 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
11505 /* PCH SDVOB multiplex with HDMIB */
11506 found = intel_sdvo_init(dev, PCH_SDVOB, true);
11507 if (!found)
11508 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
11509 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
11510 intel_dp_init(dev, PCH_DP_B, PORT_B);
11511 }
11512
11513 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
11514 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
11515
11516 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
11517 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
11518
11519 if (I915_READ(PCH_DP_C) & DP_DETECTED)
11520 intel_dp_init(dev, PCH_DP_C, PORT_C);
11521
11522 if (I915_READ(PCH_DP_D) & DP_DETECTED)
11523 intel_dp_init(dev, PCH_DP_D, PORT_D);
11524 } else if (IS_VALLEYVIEW(dev)) {
11525 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
11526 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
11527 PORT_B);
11528 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
11529 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
11530 }
11531
11532 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
11533 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
11534 PORT_C);
11535 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
11536 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
11537 }
11538
11539 if (IS_CHERRYVIEW(dev)) {
11540 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) {
11541 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
11542 PORT_D);
11543 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
11544 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
11545 }
11546 }
11547
11548 intel_dsi_init(dev);
11549 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
11550 bool found = false;
11551
11552 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11553 DRM_DEBUG_KMS("probing SDVOB\n");
11554 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
11555 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
11556 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
11557 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
11558 }
11559
11560 if (!found && SUPPORTS_INTEGRATED_DP(dev))
11561 intel_dp_init(dev, DP_B, PORT_B);
11562 }
11563
11564 /* Before G4X SDVOC doesn't have its own detect register */
11565
11566 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
11567 DRM_DEBUG_KMS("probing SDVOC\n");
11568 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
11569 }
11570
11571 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
11572
11573 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
11574 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
11575 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
11576 }
11577 if (SUPPORTS_INTEGRATED_DP(dev))
11578 intel_dp_init(dev, DP_C, PORT_C);
11579 }
11580
11581 if (SUPPORTS_INTEGRATED_DP(dev) &&
11582 (I915_READ(DP_D) & DP_DETECTED))
11583 intel_dp_init(dev, DP_D, PORT_D);
11584 } else if (IS_GEN2(dev))
11585 intel_dvo_init(dev);
11586
11587 if (SUPPORTS_TV(dev))
11588 intel_tv_init(dev);
11589
11590 intel_edp_psr_init(dev);
11591
11592 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
11593 encoder->base.possible_crtcs = encoder->crtc_mask;
11594 encoder->base.possible_clones =
11595 intel_encoder_clones(encoder);
11596 }
11597
11598 intel_init_pch_refclk(dev);
11599
11600 drm_helper_move_panel_connectors_to_head(dev);
11601 }
11602
11603 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
11604 {
11605 struct drm_device *dev = fb->dev;
11606 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11607
11608 drm_framebuffer_cleanup(fb);
11609 mutex_lock(&dev->struct_mutex);
11610 WARN_ON(!intel_fb->obj->framebuffer_references--);
11611 drm_gem_object_unreference(&intel_fb->obj->base);
11612 mutex_unlock(&dev->struct_mutex);
11613 kfree(intel_fb);
11614 }
11615
11616 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
11617 struct drm_file *file,
11618 unsigned int *handle)
11619 {
11620 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
11621 struct drm_i915_gem_object *obj = intel_fb->obj;
11622
11623 return drm_gem_handle_create(file, &obj->base, handle);
11624 }
11625
11626 static const struct drm_framebuffer_funcs intel_fb_funcs = {
11627 .destroy = intel_user_framebuffer_destroy,
11628 .create_handle = intel_user_framebuffer_create_handle,
11629 };
11630
11631 static int intel_framebuffer_init(struct drm_device *dev,
11632 struct intel_framebuffer *intel_fb,
11633 struct drm_mode_fb_cmd2 *mode_cmd,
11634 struct drm_i915_gem_object *obj)
11635 {
11636 int aligned_height;
11637 int pitch_limit;
11638 int ret;
11639
11640 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
11641
11642 if (obj->tiling_mode == I915_TILING_Y) {
11643 DRM_DEBUG("hardware does not support tiling Y\n");
11644 return -EINVAL;
11645 }
11646
11647 if (mode_cmd->pitches[0] & 63) {
11648 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
11649 mode_cmd->pitches[0]);
11650 return -EINVAL;
11651 }
11652
11653 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
11654 pitch_limit = 32*1024;
11655 } else if (INTEL_INFO(dev)->gen >= 4) {
11656 if (obj->tiling_mode)
11657 pitch_limit = 16*1024;
11658 else
11659 pitch_limit = 32*1024;
11660 } else if (INTEL_INFO(dev)->gen >= 3) {
11661 if (obj->tiling_mode)
11662 pitch_limit = 8*1024;
11663 else
11664 pitch_limit = 16*1024;
11665 } else
11666 /* XXX DSPC is limited to 4k tiled */
11667 pitch_limit = 8*1024;
11668
11669 if (mode_cmd->pitches[0] > pitch_limit) {
11670 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
11671 obj->tiling_mode ? "tiled" : "linear",
11672 mode_cmd->pitches[0], pitch_limit);
11673 return -EINVAL;
11674 }
11675
11676 if (obj->tiling_mode != I915_TILING_NONE &&
11677 mode_cmd->pitches[0] != obj->stride) {
11678 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
11679 mode_cmd->pitches[0], obj->stride);
11680 return -EINVAL;
11681 }
11682
11683 /* Reject formats not supported by any plane early. */
11684 switch (mode_cmd->pixel_format) {
11685 case DRM_FORMAT_C8:
11686 case DRM_FORMAT_RGB565:
11687 case DRM_FORMAT_XRGB8888:
11688 case DRM_FORMAT_ARGB8888:
11689 break;
11690 case DRM_FORMAT_XRGB1555:
11691 case DRM_FORMAT_ARGB1555:
11692 if (INTEL_INFO(dev)->gen > 3) {
11693 DRM_DEBUG("unsupported pixel format: %s\n",
11694 drm_get_format_name(mode_cmd->pixel_format));
11695 return -EINVAL;
11696 }
11697 break;
11698 case DRM_FORMAT_XBGR8888:
11699 case DRM_FORMAT_ABGR8888:
11700 case DRM_FORMAT_XRGB2101010:
11701 case DRM_FORMAT_ARGB2101010:
11702 case DRM_FORMAT_XBGR2101010:
11703 case DRM_FORMAT_ABGR2101010:
11704 if (INTEL_INFO(dev)->gen < 4) {
11705 DRM_DEBUG("unsupported pixel format: %s\n",
11706 drm_get_format_name(mode_cmd->pixel_format));
11707 return -EINVAL;
11708 }
11709 break;
11710 case DRM_FORMAT_YUYV:
11711 case DRM_FORMAT_UYVY:
11712 case DRM_FORMAT_YVYU:
11713 case DRM_FORMAT_VYUY:
11714 if (INTEL_INFO(dev)->gen < 5) {
11715 DRM_DEBUG("unsupported pixel format: %s\n",
11716 drm_get_format_name(mode_cmd->pixel_format));
11717 return -EINVAL;
11718 }
11719 break;
11720 default:
11721 DRM_DEBUG("unsupported pixel format: %s\n",
11722 drm_get_format_name(mode_cmd->pixel_format));
11723 return -EINVAL;
11724 }
11725
11726 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
11727 if (mode_cmd->offsets[0] != 0)
11728 return -EINVAL;
11729
11730 aligned_height = intel_align_height(dev, mode_cmd->height,
11731 obj->tiling_mode);
11732 /* FIXME drm helper for size checks (especially planar formats)? */
11733 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
11734 return -EINVAL;
11735
11736 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
11737 intel_fb->obj = obj;
11738 intel_fb->obj->framebuffer_references++;
11739
11740 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
11741 if (ret) {
11742 DRM_ERROR("framebuffer init failed %d\n", ret);
11743 return ret;
11744 }
11745
11746 return 0;
11747 }
11748
11749 static struct drm_framebuffer *
11750 intel_user_framebuffer_create(struct drm_device *dev,
11751 struct drm_file *filp,
11752 struct drm_mode_fb_cmd2 *mode_cmd)
11753 {
11754 struct drm_i915_gem_object *obj;
11755
11756 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
11757 mode_cmd->handles[0]));
11758 if (&obj->base == NULL)
11759 return ERR_PTR(-ENOENT);
11760
11761 return intel_framebuffer_create(dev, mode_cmd, obj);
11762 }
11763
11764 #ifndef CONFIG_DRM_I915_FBDEV
11765 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
11766 {
11767 }
11768 #endif
11769
11770 static const struct drm_mode_config_funcs intel_mode_funcs = {
11771 .fb_create = intel_user_framebuffer_create,
11772 .output_poll_changed = intel_fbdev_output_poll_changed,
11773 };
11774
11775 /* Set up chip specific display functions */
11776 static void intel_init_display(struct drm_device *dev)
11777 {
11778 struct drm_i915_private *dev_priv = dev->dev_private;
11779
11780 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
11781 dev_priv->display.find_dpll = g4x_find_best_dpll;
11782 else if (IS_CHERRYVIEW(dev))
11783 dev_priv->display.find_dpll = chv_find_best_dpll;
11784 else if (IS_VALLEYVIEW(dev))
11785 dev_priv->display.find_dpll = vlv_find_best_dpll;
11786 else if (IS_PINEVIEW(dev))
11787 dev_priv->display.find_dpll = pnv_find_best_dpll;
11788 else
11789 dev_priv->display.find_dpll = i9xx_find_best_dpll;
11790
11791 if (HAS_DDI(dev)) {
11792 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
11793 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11794 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
11795 dev_priv->display.crtc_enable = haswell_crtc_enable;
11796 dev_priv->display.crtc_disable = haswell_crtc_disable;
11797 dev_priv->display.off = haswell_crtc_off;
11798 dev_priv->display.update_primary_plane =
11799 ironlake_update_primary_plane;
11800 } else if (HAS_PCH_SPLIT(dev)) {
11801 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
11802 dev_priv->display.get_plane_config = ironlake_get_plane_config;
11803 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
11804 dev_priv->display.crtc_enable = ironlake_crtc_enable;
11805 dev_priv->display.crtc_disable = ironlake_crtc_disable;
11806 dev_priv->display.off = ironlake_crtc_off;
11807 dev_priv->display.update_primary_plane =
11808 ironlake_update_primary_plane;
11809 } else if (IS_VALLEYVIEW(dev)) {
11810 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11811 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11812 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11813 dev_priv->display.crtc_enable = valleyview_crtc_enable;
11814 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11815 dev_priv->display.off = i9xx_crtc_off;
11816 dev_priv->display.update_primary_plane =
11817 i9xx_update_primary_plane;
11818 } else {
11819 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
11820 dev_priv->display.get_plane_config = i9xx_get_plane_config;
11821 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
11822 dev_priv->display.crtc_enable = i9xx_crtc_enable;
11823 dev_priv->display.crtc_disable = i9xx_crtc_disable;
11824 dev_priv->display.off = i9xx_crtc_off;
11825 dev_priv->display.update_primary_plane =
11826 i9xx_update_primary_plane;
11827 }
11828
11829 /* Returns the core display clock speed */
11830 if (IS_VALLEYVIEW(dev))
11831 dev_priv->display.get_display_clock_speed =
11832 valleyview_get_display_clock_speed;
11833 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
11834 dev_priv->display.get_display_clock_speed =
11835 i945_get_display_clock_speed;
11836 else if (IS_I915G(dev))
11837 dev_priv->display.get_display_clock_speed =
11838 i915_get_display_clock_speed;
11839 else if (IS_I945GM(dev) || IS_845G(dev))
11840 dev_priv->display.get_display_clock_speed =
11841 i9xx_misc_get_display_clock_speed;
11842 else if (IS_PINEVIEW(dev))
11843 dev_priv->display.get_display_clock_speed =
11844 pnv_get_display_clock_speed;
11845 else if (IS_I915GM(dev))
11846 dev_priv->display.get_display_clock_speed =
11847 i915gm_get_display_clock_speed;
11848 else if (IS_I865G(dev))
11849 dev_priv->display.get_display_clock_speed =
11850 i865_get_display_clock_speed;
11851 else if (IS_I85X(dev))
11852 dev_priv->display.get_display_clock_speed =
11853 i855_get_display_clock_speed;
11854 else /* 852, 830 */
11855 dev_priv->display.get_display_clock_speed =
11856 i830_get_display_clock_speed;
11857
11858 if (HAS_PCH_SPLIT(dev)) {
11859 if (IS_GEN5(dev)) {
11860 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
11861 dev_priv->display.write_eld = ironlake_write_eld;
11862 } else if (IS_GEN6(dev)) {
11863 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
11864 dev_priv->display.write_eld = ironlake_write_eld;
11865 dev_priv->display.modeset_global_resources =
11866 snb_modeset_global_resources;
11867 } else if (IS_IVYBRIDGE(dev)) {
11868 /* FIXME: detect B0+ stepping and use auto training */
11869 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
11870 dev_priv->display.write_eld = ironlake_write_eld;
11871 dev_priv->display.modeset_global_resources =
11872 ivb_modeset_global_resources;
11873 } else if (IS_HASWELL(dev) || IS_GEN8(dev)) {
11874 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
11875 dev_priv->display.write_eld = haswell_write_eld;
11876 dev_priv->display.modeset_global_resources =
11877 haswell_modeset_global_resources;
11878 }
11879 } else if (IS_G4X(dev)) {
11880 dev_priv->display.write_eld = g4x_write_eld;
11881 } else if (IS_VALLEYVIEW(dev)) {
11882 dev_priv->display.modeset_global_resources =
11883 valleyview_modeset_global_resources;
11884 dev_priv->display.write_eld = ironlake_write_eld;
11885 }
11886
11887 /* Default just returns -ENODEV to indicate unsupported */
11888 dev_priv->display.queue_flip = intel_default_queue_flip;
11889
11890 switch (INTEL_INFO(dev)->gen) {
11891 case 2:
11892 dev_priv->display.queue_flip = intel_gen2_queue_flip;
11893 break;
11894
11895 case 3:
11896 dev_priv->display.queue_flip = intel_gen3_queue_flip;
11897 break;
11898
11899 case 4:
11900 case 5:
11901 dev_priv->display.queue_flip = intel_gen4_queue_flip;
11902 break;
11903
11904 case 6:
11905 dev_priv->display.queue_flip = intel_gen6_queue_flip;
11906 break;
11907 case 7:
11908 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
11909 dev_priv->display.queue_flip = intel_gen7_queue_flip;
11910 break;
11911 }
11912
11913 intel_panel_init_backlight_funcs(dev);
11914 }
11915
11916 /*
11917 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
11918 * resume, or other times. This quirk makes sure that's the case for
11919 * affected systems.
11920 */
11921 static void quirk_pipea_force(struct drm_device *dev)
11922 {
11923 struct drm_i915_private *dev_priv = dev->dev_private;
11924
11925 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
11926 DRM_INFO("applying pipe a force quirk\n");
11927 }
11928
11929 /*
11930 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
11931 */
11932 static void quirk_ssc_force_disable(struct drm_device *dev)
11933 {
11934 struct drm_i915_private *dev_priv = dev->dev_private;
11935 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
11936 DRM_INFO("applying lvds SSC disable quirk\n");
11937 }
11938
11939 /*
11940 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
11941 * brightness value
11942 */
11943 static void quirk_invert_brightness(struct drm_device *dev)
11944 {
11945 struct drm_i915_private *dev_priv = dev->dev_private;
11946 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
11947 DRM_INFO("applying inverted panel brightness quirk\n");
11948 }
11949
11950 struct intel_quirk {
11951 int device;
11952 int subsystem_vendor;
11953 int subsystem_device;
11954 void (*hook)(struct drm_device *dev);
11955 };
11956
11957 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
11958 struct intel_dmi_quirk {
11959 void (*hook)(struct drm_device *dev);
11960 const struct dmi_system_id (*dmi_id_list)[];
11961 };
11962
11963 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
11964 {
11965 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
11966 return 1;
11967 }
11968
11969 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
11970 {
11971 .dmi_id_list = &(const struct dmi_system_id[]) {
11972 {
11973 .callback = intel_dmi_reverse_brightness,
11974 .ident = "NCR Corporation",
11975 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
11976 DMI_MATCH(DMI_PRODUCT_NAME, ""),
11977 },
11978 },
11979 { } /* terminating entry */
11980 },
11981 .hook = quirk_invert_brightness,
11982 },
11983 };
11984
11985 static struct intel_quirk intel_quirks[] = {
11986 /* HP Mini needs pipe A force quirk (LP: #322104) */
11987 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
11988
11989 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
11990 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
11991
11992 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
11993 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
11994
11995 /* Lenovo U160 cannot use SSC on LVDS */
11996 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
11997
11998 /* Sony Vaio Y cannot use SSC on LVDS */
11999 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
12000
12001 /* Acer Aspire 5734Z must invert backlight brightness */
12002 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
12003
12004 /* Acer/eMachines G725 */
12005 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
12006
12007 /* Acer/eMachines e725 */
12008 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
12009
12010 /* Acer/Packard Bell NCL20 */
12011 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
12012
12013 /* Acer Aspire 4736Z */
12014 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
12015
12016 /* Acer Aspire 5336 */
12017 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
12018 };
12019
12020 static void intel_init_quirks(struct drm_device *dev)
12021 {
12022 struct pci_dev *d = dev->pdev;
12023 int i;
12024
12025 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
12026 struct intel_quirk *q = &intel_quirks[i];
12027
12028 if (d->device == q->device &&
12029 (d->subsystem_vendor == q->subsystem_vendor ||
12030 q->subsystem_vendor == PCI_ANY_ID) &&
12031 (d->subsystem_device == q->subsystem_device ||
12032 q->subsystem_device == PCI_ANY_ID))
12033 q->hook(dev);
12034 }
12035 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
12036 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
12037 intel_dmi_quirks[i].hook(dev);
12038 }
12039 }
12040
12041 /* Disable the VGA plane that we never use */
12042 static void i915_disable_vga(struct drm_device *dev)
12043 {
12044 struct drm_i915_private *dev_priv = dev->dev_private;
12045 u8 sr1;
12046 u32 vga_reg = i915_vgacntrl_reg(dev);
12047
12048 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
12049 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
12050 outb(SR01, VGA_SR_INDEX);
12051 sr1 = inb(VGA_SR_DATA);
12052 outb(sr1 | 1<<5, VGA_SR_DATA);
12053 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
12054 udelay(300);
12055
12056 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
12057 POSTING_READ(vga_reg);
12058 }
12059
12060 void intel_modeset_init_hw(struct drm_device *dev)
12061 {
12062 intel_prepare_ddi(dev);
12063
12064 intel_init_clock_gating(dev);
12065
12066 intel_reset_dpio(dev);
12067
12068 intel_enable_gt_powersave(dev);
12069 }
12070
12071 void intel_modeset_suspend_hw(struct drm_device *dev)
12072 {
12073 intel_suspend_hw(dev);
12074 }
12075
12076 void intel_modeset_init(struct drm_device *dev)
12077 {
12078 struct drm_i915_private *dev_priv = dev->dev_private;
12079 int sprite, ret;
12080 enum pipe pipe;
12081 struct intel_crtc *crtc;
12082
12083 drm_mode_config_init(dev);
12084
12085 dev->mode_config.min_width = 0;
12086 dev->mode_config.min_height = 0;
12087
12088 dev->mode_config.preferred_depth = 24;
12089 dev->mode_config.prefer_shadow = 1;
12090
12091 dev->mode_config.funcs = &intel_mode_funcs;
12092
12093 intel_init_quirks(dev);
12094
12095 intel_init_pm(dev);
12096
12097 if (INTEL_INFO(dev)->num_pipes == 0)
12098 return;
12099
12100 intel_init_display(dev);
12101
12102 if (IS_GEN2(dev)) {
12103 dev->mode_config.max_width = 2048;
12104 dev->mode_config.max_height = 2048;
12105 } else if (IS_GEN3(dev)) {
12106 dev->mode_config.max_width = 4096;
12107 dev->mode_config.max_height = 4096;
12108 } else {
12109 dev->mode_config.max_width = 8192;
12110 dev->mode_config.max_height = 8192;
12111 }
12112
12113 if (IS_GEN2(dev)) {
12114 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
12115 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
12116 } else {
12117 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
12118 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
12119 }
12120
12121 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
12122
12123 DRM_DEBUG_KMS("%d display pipe%s available.\n",
12124 INTEL_INFO(dev)->num_pipes,
12125 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
12126
12127 for_each_pipe(pipe) {
12128 intel_crtc_init(dev, pipe);
12129 for_each_sprite(pipe, sprite) {
12130 ret = intel_plane_init(dev, pipe, sprite);
12131 if (ret)
12132 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
12133 pipe_name(pipe), sprite_name(pipe, sprite), ret);
12134 }
12135 }
12136
12137 intel_init_dpio(dev);
12138 intel_reset_dpio(dev);
12139
12140 intel_cpu_pll_init(dev);
12141 intel_shared_dpll_init(dev);
12142
12143 /* Just disable it once at startup */
12144 i915_disable_vga(dev);
12145 intel_setup_outputs(dev);
12146
12147 /* Just in case the BIOS is doing something questionable. */
12148 intel_disable_fbc(dev);
12149
12150 drm_modeset_lock_all(dev);
12151 intel_modeset_setup_hw_state(dev, false);
12152 drm_modeset_unlock_all(dev);
12153
12154 for_each_intel_crtc(dev, crtc) {
12155 if (!crtc->active)
12156 continue;
12157
12158 /*
12159 * Note that reserving the BIOS fb up front prevents us
12160 * from stuffing other stolen allocations like the ring
12161 * on top. This prevents some ugliness at boot time, and
12162 * can even allow for smooth boot transitions if the BIOS
12163 * fb is large enough for the active pipe configuration.
12164 */
12165 if (dev_priv->display.get_plane_config) {
12166 dev_priv->display.get_plane_config(crtc,
12167 &crtc->plane_config);
12168 /*
12169 * If the fb is shared between multiple heads, we'll
12170 * just get the first one.
12171 */
12172 intel_find_plane_obj(crtc, &crtc->plane_config);
12173 }
12174 }
12175 }
12176
12177 static void intel_enable_pipe_a(struct drm_device *dev)
12178 {
12179 struct intel_connector *connector;
12180 struct drm_connector *crt = NULL;
12181 struct intel_load_detect_pipe load_detect_temp;
12182 struct drm_modeset_acquire_ctx ctx;
12183
12184 /* We can't just switch on the pipe A, we need to set things up with a
12185 * proper mode and output configuration. As a gross hack, enable pipe A
12186 * by enabling the load detect pipe once. */
12187 list_for_each_entry(connector,
12188 &dev->mode_config.connector_list,
12189 base.head) {
12190 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
12191 crt = &connector->base;
12192 break;
12193 }
12194 }
12195
12196 if (!crt)
12197 return;
12198
12199 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, &ctx))
12200 intel_release_load_detect_pipe(crt, &load_detect_temp, &ctx);
12201
12202
12203 }
12204
12205 static bool
12206 intel_check_plane_mapping(struct intel_crtc *crtc)
12207 {
12208 struct drm_device *dev = crtc->base.dev;
12209 struct drm_i915_private *dev_priv = dev->dev_private;
12210 u32 reg, val;
12211
12212 if (INTEL_INFO(dev)->num_pipes == 1)
12213 return true;
12214
12215 reg = DSPCNTR(!crtc->plane);
12216 val = I915_READ(reg);
12217
12218 if ((val & DISPLAY_PLANE_ENABLE) &&
12219 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
12220 return false;
12221
12222 return true;
12223 }
12224
12225 static void intel_sanitize_crtc(struct intel_crtc *crtc)
12226 {
12227 struct drm_device *dev = crtc->base.dev;
12228 struct drm_i915_private *dev_priv = dev->dev_private;
12229 u32 reg;
12230
12231 /* Clear any frame start delays used for debugging left by the BIOS */
12232 reg = PIPECONF(crtc->config.cpu_transcoder);
12233 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
12234
12235 /* restore vblank interrupts to correct state */
12236 if (crtc->active)
12237 drm_vblank_on(dev, crtc->pipe);
12238 else
12239 drm_vblank_off(dev, crtc->pipe);
12240
12241 /* We need to sanitize the plane -> pipe mapping first because this will
12242 * disable the crtc (and hence change the state) if it is wrong. Note
12243 * that gen4+ has a fixed plane -> pipe mapping. */
12244 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
12245 struct intel_connector *connector;
12246 bool plane;
12247
12248 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
12249 crtc->base.base.id);
12250
12251 /* Pipe has the wrong plane attached and the plane is active.
12252 * Temporarily change the plane mapping and disable everything
12253 * ... */
12254 plane = crtc->plane;
12255 crtc->plane = !plane;
12256 dev_priv->display.crtc_disable(&crtc->base);
12257 crtc->plane = plane;
12258
12259 /* ... and break all links. */
12260 list_for_each_entry(connector, &dev->mode_config.connector_list,
12261 base.head) {
12262 if (connector->encoder->base.crtc != &crtc->base)
12263 continue;
12264
12265 connector->base.dpms = DRM_MODE_DPMS_OFF;
12266 connector->base.encoder = NULL;
12267 }
12268 /* multiple connectors may have the same encoder:
12269 * handle them and break crtc link separately */
12270 list_for_each_entry(connector, &dev->mode_config.connector_list,
12271 base.head)
12272 if (connector->encoder->base.crtc == &crtc->base) {
12273 connector->encoder->base.crtc = NULL;
12274 connector->encoder->connectors_active = false;
12275 }
12276
12277 WARN_ON(crtc->active);
12278 crtc->base.enabled = false;
12279 }
12280
12281 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
12282 crtc->pipe == PIPE_A && !crtc->active) {
12283 /* BIOS forgot to enable pipe A, this mostly happens after
12284 * resume. Force-enable the pipe to fix this, the update_dpms
12285 * call below we restore the pipe to the right state, but leave
12286 * the required bits on. */
12287 intel_enable_pipe_a(dev);
12288 }
12289
12290 /* Adjust the state of the output pipe according to whether we
12291 * have active connectors/encoders. */
12292 intel_crtc_update_dpms(&crtc->base);
12293
12294 if (crtc->active != crtc->base.enabled) {
12295 struct intel_encoder *encoder;
12296
12297 /* This can happen either due to bugs in the get_hw_state
12298 * functions or because the pipe is force-enabled due to the
12299 * pipe A quirk. */
12300 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
12301 crtc->base.base.id,
12302 crtc->base.enabled ? "enabled" : "disabled",
12303 crtc->active ? "enabled" : "disabled");
12304
12305 crtc->base.enabled = crtc->active;
12306
12307 /* Because we only establish the connector -> encoder ->
12308 * crtc links if something is active, this means the
12309 * crtc is now deactivated. Break the links. connector
12310 * -> encoder links are only establish when things are
12311 * actually up, hence no need to break them. */
12312 WARN_ON(crtc->active);
12313
12314 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
12315 WARN_ON(encoder->connectors_active);
12316 encoder->base.crtc = NULL;
12317 }
12318 }
12319
12320 if (crtc->active || IS_VALLEYVIEW(dev) || INTEL_INFO(dev)->gen < 5) {
12321 /*
12322 * We start out with underrun reporting disabled to avoid races.
12323 * For correct bookkeeping mark this on active crtcs.
12324 *
12325 * Also on gmch platforms we dont have any hardware bits to
12326 * disable the underrun reporting. Which means we need to start
12327 * out with underrun reporting disabled also on inactive pipes,
12328 * since otherwise we'll complain about the garbage we read when
12329 * e.g. coming up after runtime pm.
12330 *
12331 * No protection against concurrent access is required - at
12332 * worst a fifo underrun happens which also sets this to false.
12333 */
12334 crtc->cpu_fifo_underrun_disabled = true;
12335 crtc->pch_fifo_underrun_disabled = true;
12336
12337 update_scanline_offset(crtc);
12338 }
12339 }
12340
12341 static void intel_sanitize_encoder(struct intel_encoder *encoder)
12342 {
12343 struct intel_connector *connector;
12344 struct drm_device *dev = encoder->base.dev;
12345
12346 /* We need to check both for a crtc link (meaning that the
12347 * encoder is active and trying to read from a pipe) and the
12348 * pipe itself being active. */
12349 bool has_active_crtc = encoder->base.crtc &&
12350 to_intel_crtc(encoder->base.crtc)->active;
12351
12352 if (encoder->connectors_active && !has_active_crtc) {
12353 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
12354 encoder->base.base.id,
12355 encoder->base.name);
12356
12357 /* Connector is active, but has no active pipe. This is
12358 * fallout from our resume register restoring. Disable
12359 * the encoder manually again. */
12360 if (encoder->base.crtc) {
12361 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
12362 encoder->base.base.id,
12363 encoder->base.name);
12364 encoder->disable(encoder);
12365 }
12366 encoder->base.crtc = NULL;
12367 encoder->connectors_active = false;
12368
12369 /* Inconsistent output/port/pipe state happens presumably due to
12370 * a bug in one of the get_hw_state functions. Or someplace else
12371 * in our code, like the register restore mess on resume. Clamp
12372 * things to off as a safer default. */
12373 list_for_each_entry(connector,
12374 &dev->mode_config.connector_list,
12375 base.head) {
12376 if (connector->encoder != encoder)
12377 continue;
12378 connector->base.dpms = DRM_MODE_DPMS_OFF;
12379 connector->base.encoder = NULL;
12380 }
12381 }
12382 /* Enabled encoders without active connectors will be fixed in
12383 * the crtc fixup. */
12384 }
12385
12386 void i915_redisable_vga_power_on(struct drm_device *dev)
12387 {
12388 struct drm_i915_private *dev_priv = dev->dev_private;
12389 u32 vga_reg = i915_vgacntrl_reg(dev);
12390
12391 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
12392 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
12393 i915_disable_vga(dev);
12394 }
12395 }
12396
12397 void i915_redisable_vga(struct drm_device *dev)
12398 {
12399 struct drm_i915_private *dev_priv = dev->dev_private;
12400
12401 /* This function can be called both from intel_modeset_setup_hw_state or
12402 * at a very early point in our resume sequence, where the power well
12403 * structures are not yet restored. Since this function is at a very
12404 * paranoid "someone might have enabled VGA while we were not looking"
12405 * level, just check if the power well is enabled instead of trying to
12406 * follow the "don't touch the power well if we don't need it" policy
12407 * the rest of the driver uses. */
12408 if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA))
12409 return;
12410
12411 i915_redisable_vga_power_on(dev);
12412 }
12413
12414 static bool primary_get_hw_state(struct intel_crtc *crtc)
12415 {
12416 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
12417
12418 if (!crtc->active)
12419 return false;
12420
12421 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
12422 }
12423
12424 static void intel_modeset_readout_hw_state(struct drm_device *dev)
12425 {
12426 struct drm_i915_private *dev_priv = dev->dev_private;
12427 enum pipe pipe;
12428 struct intel_crtc *crtc;
12429 struct intel_encoder *encoder;
12430 struct intel_connector *connector;
12431 int i;
12432
12433 for_each_intel_crtc(dev, crtc) {
12434 memset(&crtc->config, 0, sizeof(crtc->config));
12435
12436 crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
12437
12438 crtc->active = dev_priv->display.get_pipe_config(crtc,
12439 &crtc->config);
12440
12441 crtc->base.enabled = crtc->active;
12442 crtc->primary_enabled = primary_get_hw_state(crtc);
12443
12444 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
12445 crtc->base.base.id,
12446 crtc->active ? "enabled" : "disabled");
12447 }
12448
12449 /* FIXME: Smash this into the new shared dpll infrastructure. */
12450 if (HAS_DDI(dev))
12451 intel_ddi_setup_hw_pll_state(dev);
12452
12453 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12454 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12455
12456 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
12457 pll->active = 0;
12458 for_each_intel_crtc(dev, crtc) {
12459 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12460 pll->active++;
12461 }
12462 pll->refcount = pll->active;
12463
12464 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
12465 pll->name, pll->refcount, pll->on);
12466 }
12467
12468 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12469 base.head) {
12470 pipe = 0;
12471
12472 if (encoder->get_hw_state(encoder, &pipe)) {
12473 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12474 encoder->base.crtc = &crtc->base;
12475 encoder->get_config(encoder, &crtc->config);
12476 } else {
12477 encoder->base.crtc = NULL;
12478 }
12479
12480 encoder->connectors_active = false;
12481 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
12482 encoder->base.base.id,
12483 encoder->base.name,
12484 encoder->base.crtc ? "enabled" : "disabled",
12485 pipe_name(pipe));
12486 }
12487
12488 list_for_each_entry(connector, &dev->mode_config.connector_list,
12489 base.head) {
12490 if (connector->get_hw_state(connector)) {
12491 connector->base.dpms = DRM_MODE_DPMS_ON;
12492 connector->encoder->connectors_active = true;
12493 connector->base.encoder = &connector->encoder->base;
12494 } else {
12495 connector->base.dpms = DRM_MODE_DPMS_OFF;
12496 connector->base.encoder = NULL;
12497 }
12498 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
12499 connector->base.base.id,
12500 connector->base.name,
12501 connector->base.encoder ? "enabled" : "disabled");
12502 }
12503 }
12504
12505 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
12506 * and i915 state tracking structures. */
12507 void intel_modeset_setup_hw_state(struct drm_device *dev,
12508 bool force_restore)
12509 {
12510 struct drm_i915_private *dev_priv = dev->dev_private;
12511 enum pipe pipe;
12512 struct intel_crtc *crtc;
12513 struct intel_encoder *encoder;
12514 int i;
12515
12516 intel_modeset_readout_hw_state(dev);
12517
12518 /*
12519 * Now that we have the config, copy it to each CRTC struct
12520 * Note that this could go away if we move to using crtc_config
12521 * checking everywhere.
12522 */
12523 for_each_intel_crtc(dev, crtc) {
12524 if (crtc->active && i915.fastboot) {
12525 intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config);
12526 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
12527 crtc->base.base.id);
12528 drm_mode_debug_printmodeline(&crtc->base.mode);
12529 }
12530 }
12531
12532 /* HW state is read out, now we need to sanitize this mess. */
12533 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
12534 base.head) {
12535 intel_sanitize_encoder(encoder);
12536 }
12537
12538 for_each_pipe(pipe) {
12539 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
12540 intel_sanitize_crtc(crtc);
12541 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
12542 }
12543
12544 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12545 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12546
12547 if (!pll->on || pll->active)
12548 continue;
12549
12550 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
12551
12552 pll->disable(dev_priv, pll);
12553 pll->on = false;
12554 }
12555
12556 if (HAS_PCH_SPLIT(dev))
12557 ilk_wm_get_hw_state(dev);
12558
12559 if (force_restore) {
12560 i915_redisable_vga(dev);
12561
12562 /*
12563 * We need to use raw interfaces for restoring state to avoid
12564 * checking (bogus) intermediate states.
12565 */
12566 for_each_pipe(pipe) {
12567 struct drm_crtc *crtc =
12568 dev_priv->pipe_to_crtc_mapping[pipe];
12569
12570 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
12571 crtc->primary->fb);
12572 }
12573 } else {
12574 intel_modeset_update_staged_output_state(dev);
12575 }
12576
12577 intel_modeset_check_state(dev);
12578 }
12579
12580 void intel_modeset_gem_init(struct drm_device *dev)
12581 {
12582 struct drm_crtc *c;
12583 struct intel_framebuffer *fb;
12584
12585 mutex_lock(&dev->struct_mutex);
12586 intel_init_gt_powersave(dev);
12587 mutex_unlock(&dev->struct_mutex);
12588
12589 intel_modeset_init_hw(dev);
12590
12591 intel_setup_overlay(dev);
12592
12593 /*
12594 * Make sure any fbs we allocated at startup are properly
12595 * pinned & fenced. When we do the allocation it's too early
12596 * for this.
12597 */
12598 mutex_lock(&dev->struct_mutex);
12599 for_each_crtc(dev, c) {
12600 if (!c->primary->fb)
12601 continue;
12602
12603 fb = to_intel_framebuffer(c->primary->fb);
12604 if (intel_pin_and_fence_fb_obj(dev, fb->obj, NULL)) {
12605 DRM_ERROR("failed to pin boot fb on pipe %d\n",
12606 to_intel_crtc(c)->pipe);
12607 drm_framebuffer_unreference(c->primary->fb);
12608 c->primary->fb = NULL;
12609 }
12610 }
12611 mutex_unlock(&dev->struct_mutex);
12612 }
12613
12614 void intel_connector_unregister(struct intel_connector *intel_connector)
12615 {
12616 struct drm_connector *connector = &intel_connector->base;
12617
12618 intel_panel_destroy_backlight(connector);
12619 drm_sysfs_connector_remove(connector);
12620 }
12621
12622 void intel_modeset_cleanup(struct drm_device *dev)
12623 {
12624 struct drm_i915_private *dev_priv = dev->dev_private;
12625 struct drm_crtc *crtc;
12626 struct drm_connector *connector;
12627
12628 /*
12629 * Interrupts and polling as the first thing to avoid creating havoc.
12630 * Too much stuff here (turning of rps, connectors, ...) would
12631 * experience fancy races otherwise.
12632 */
12633 drm_irq_uninstall(dev);
12634 cancel_work_sync(&dev_priv->hotplug_work);
12635 /*
12636 * Due to the hpd irq storm handling the hotplug work can re-arm the
12637 * poll handlers. Hence disable polling after hpd handling is shut down.
12638 */
12639 drm_kms_helper_poll_fini(dev);
12640
12641 mutex_lock(&dev->struct_mutex);
12642
12643 intel_unregister_dsm_handler();
12644
12645 for_each_crtc(dev, crtc) {
12646 /* Skip inactive CRTCs */
12647 if (!crtc->primary->fb)
12648 continue;
12649
12650 intel_increase_pllclock(crtc);
12651 }
12652
12653 intel_disable_fbc(dev);
12654
12655 intel_disable_gt_powersave(dev);
12656
12657 ironlake_teardown_rc6(dev);
12658
12659 mutex_unlock(&dev->struct_mutex);
12660
12661 /* flush any delayed tasks or pending work */
12662 flush_scheduled_work();
12663
12664 /* destroy the backlight and sysfs files before encoders/connectors */
12665 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12666 struct intel_connector *intel_connector;
12667
12668 intel_connector = to_intel_connector(connector);
12669 intel_connector->unregister(intel_connector);
12670 }
12671
12672 drm_mode_config_cleanup(dev);
12673
12674 intel_cleanup_overlay(dev);
12675
12676 mutex_lock(&dev->struct_mutex);
12677 intel_cleanup_gt_powersave(dev);
12678 mutex_unlock(&dev->struct_mutex);
12679 }
12680
12681 /*
12682 * Return which encoder is currently attached for connector.
12683 */
12684 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
12685 {
12686 return &intel_attached_encoder(connector)->base;
12687 }
12688
12689 void intel_connector_attach_encoder(struct intel_connector *connector,
12690 struct intel_encoder *encoder)
12691 {
12692 connector->encoder = encoder;
12693 drm_mode_connector_attach_encoder(&connector->base,
12694 &encoder->base);
12695 }
12696
12697 /*
12698 * set vga decode state - true == enable VGA decode
12699 */
12700 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
12701 {
12702 struct drm_i915_private *dev_priv = dev->dev_private;
12703 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
12704 u16 gmch_ctrl;
12705
12706 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
12707 DRM_ERROR("failed to read control word\n");
12708 return -EIO;
12709 }
12710
12711 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
12712 return 0;
12713
12714 if (state)
12715 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
12716 else
12717 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
12718
12719 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
12720 DRM_ERROR("failed to write control word\n");
12721 return -EIO;
12722 }
12723
12724 return 0;
12725 }
12726
12727 struct intel_display_error_state {
12728
12729 u32 power_well_driver;
12730
12731 int num_transcoders;
12732
12733 struct intel_cursor_error_state {
12734 u32 control;
12735 u32 position;
12736 u32 base;
12737 u32 size;
12738 } cursor[I915_MAX_PIPES];
12739
12740 struct intel_pipe_error_state {
12741 bool power_domain_on;
12742 u32 source;
12743 u32 stat;
12744 } pipe[I915_MAX_PIPES];
12745
12746 struct intel_plane_error_state {
12747 u32 control;
12748 u32 stride;
12749 u32 size;
12750 u32 pos;
12751 u32 addr;
12752 u32 surface;
12753 u32 tile_offset;
12754 } plane[I915_MAX_PIPES];
12755
12756 struct intel_transcoder_error_state {
12757 bool power_domain_on;
12758 enum transcoder cpu_transcoder;
12759
12760 u32 conf;
12761
12762 u32 htotal;
12763 u32 hblank;
12764 u32 hsync;
12765 u32 vtotal;
12766 u32 vblank;
12767 u32 vsync;
12768 } transcoder[4];
12769 };
12770
12771 struct intel_display_error_state *
12772 intel_display_capture_error_state(struct drm_device *dev)
12773 {
12774 struct drm_i915_private *dev_priv = dev->dev_private;
12775 struct intel_display_error_state *error;
12776 int transcoders[] = {
12777 TRANSCODER_A,
12778 TRANSCODER_B,
12779 TRANSCODER_C,
12780 TRANSCODER_EDP,
12781 };
12782 int i;
12783
12784 if (INTEL_INFO(dev)->num_pipes == 0)
12785 return NULL;
12786
12787 error = kzalloc(sizeof(*error), GFP_ATOMIC);
12788 if (error == NULL)
12789 return NULL;
12790
12791 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12792 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
12793
12794 for_each_pipe(i) {
12795 error->pipe[i].power_domain_on =
12796 intel_display_power_enabled_sw(dev_priv,
12797 POWER_DOMAIN_PIPE(i));
12798 if (!error->pipe[i].power_domain_on)
12799 continue;
12800
12801 error->cursor[i].control = I915_READ(CURCNTR(i));
12802 error->cursor[i].position = I915_READ(CURPOS(i));
12803 error->cursor[i].base = I915_READ(CURBASE(i));
12804
12805 error->plane[i].control = I915_READ(DSPCNTR(i));
12806 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
12807 if (INTEL_INFO(dev)->gen <= 3) {
12808 error->plane[i].size = I915_READ(DSPSIZE(i));
12809 error->plane[i].pos = I915_READ(DSPPOS(i));
12810 }
12811 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12812 error->plane[i].addr = I915_READ(DSPADDR(i));
12813 if (INTEL_INFO(dev)->gen >= 4) {
12814 error->plane[i].surface = I915_READ(DSPSURF(i));
12815 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
12816 }
12817
12818 error->pipe[i].source = I915_READ(PIPESRC(i));
12819
12820 if (!HAS_PCH_SPLIT(dev))
12821 error->pipe[i].stat = I915_READ(PIPESTAT(i));
12822 }
12823
12824 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
12825 if (HAS_DDI(dev_priv->dev))
12826 error->num_transcoders++; /* Account for eDP. */
12827
12828 for (i = 0; i < error->num_transcoders; i++) {
12829 enum transcoder cpu_transcoder = transcoders[i];
12830
12831 error->transcoder[i].power_domain_on =
12832 intel_display_power_enabled_sw(dev_priv,
12833 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
12834 if (!error->transcoder[i].power_domain_on)
12835 continue;
12836
12837 error->transcoder[i].cpu_transcoder = cpu_transcoder;
12838
12839 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
12840 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
12841 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
12842 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
12843 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
12844 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
12845 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
12846 }
12847
12848 return error;
12849 }
12850
12851 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
12852
12853 void
12854 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
12855 struct drm_device *dev,
12856 struct intel_display_error_state *error)
12857 {
12858 int i;
12859
12860 if (!error)
12861 return;
12862
12863 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
12864 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
12865 err_printf(m, "PWR_WELL_CTL2: %08x\n",
12866 error->power_well_driver);
12867 for_each_pipe(i) {
12868 err_printf(m, "Pipe [%d]:\n", i);
12869 err_printf(m, " Power: %s\n",
12870 error->pipe[i].power_domain_on ? "on" : "off");
12871 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
12872 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
12873
12874 err_printf(m, "Plane [%d]:\n", i);
12875 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
12876 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
12877 if (INTEL_INFO(dev)->gen <= 3) {
12878 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
12879 err_printf(m, " POS: %08x\n", error->plane[i].pos);
12880 }
12881 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
12882 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
12883 if (INTEL_INFO(dev)->gen >= 4) {
12884 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
12885 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
12886 }
12887
12888 err_printf(m, "Cursor [%d]:\n", i);
12889 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
12890 err_printf(m, " POS: %08x\n", error->cursor[i].position);
12891 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
12892 }
12893
12894 for (i = 0; i < error->num_transcoders; i++) {
12895 err_printf(m, "CPU transcoder: %c\n",
12896 transcoder_name(error->transcoder[i].cpu_transcoder));
12897 err_printf(m, " Power: %s\n",
12898 error->transcoder[i].power_domain_on ? "on" : "off");
12899 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
12900 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
12901 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
12902 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
12903 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
12904 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
12905 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
12906 }
12907 }
(deprecated) Btrfs devel tree