2 * Copyright © 2008 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 * Eric Anholt <eric@anholt.net>
29 #include <drm/drm_vma_manager.h>
30 #include <drm/i915_drm.h>
32 #include "i915_trace.h"
33 #include "intel_drv.h"
34 #include <linux/oom.h>
35 #include <linux/shmem_fs.h>
36 #include <linux/slab.h>
37 #include <linux/swap.h>
38 #include <linux/pci.h>
39 #include <linux/dma-buf.h>
41 static void i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
);
42 static void i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
44 static __must_check
int
45 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
48 i915_gem_object_retire(struct drm_i915_gem_object
*obj
);
50 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
51 struct drm_i915_gem_object
*obj
);
52 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
53 struct drm_i915_fence_reg
*fence
,
56 static unsigned long i915_gem_shrinker_count(struct shrinker
*shrinker
,
57 struct shrink_control
*sc
);
58 static unsigned long i915_gem_shrinker_scan(struct shrinker
*shrinker
,
59 struct shrink_control
*sc
);
60 static int i915_gem_shrinker_oom(struct notifier_block
*nb
,
63 static unsigned long i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
);
64 static unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
66 static bool cpu_cache_is_coherent(struct drm_device
*dev
,
67 enum i915_cache_level level
)
69 return HAS_LLC(dev
) || level
!= I915_CACHE_NONE
;
72 static bool cpu_write_needs_clflush(struct drm_i915_gem_object
*obj
)
74 if (!cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
77 return obj
->pin_display
;
80 static inline void i915_gem_object_fence_lost(struct drm_i915_gem_object
*obj
)
83 i915_gem_release_mmap(obj
);
85 /* As we do not have an associated fence register, we will force
86 * a tiling change if we ever need to acquire one.
88 obj
->fence_dirty
= false;
89 obj
->fence_reg
= I915_FENCE_REG_NONE
;
92 /* some bookkeeping */
93 static void i915_gem_info_add_obj(struct drm_i915_private
*dev_priv
,
96 spin_lock(&dev_priv
->mm
.object_stat_lock
);
97 dev_priv
->mm
.object_count
++;
98 dev_priv
->mm
.object_memory
+= size
;
99 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
102 static void i915_gem_info_remove_obj(struct drm_i915_private
*dev_priv
,
105 spin_lock(&dev_priv
->mm
.object_stat_lock
);
106 dev_priv
->mm
.object_count
--;
107 dev_priv
->mm
.object_memory
-= size
;
108 spin_unlock(&dev_priv
->mm
.object_stat_lock
);
112 i915_gem_wait_for_error(struct i915_gpu_error
*error
)
116 #define EXIT_COND (!i915_reset_in_progress(error) || \
117 i915_terminally_wedged(error))
122 * Only wait 10 seconds for the gpu reset to complete to avoid hanging
123 * userspace. If it takes that long something really bad is going on and
124 * we should simply try to bail out and fail as gracefully as possible.
126 ret
= wait_event_interruptible_timeout(error
->reset_queue
,
130 DRM_ERROR("Timed out waiting for the gpu reset to complete\n");
132 } else if (ret
< 0) {
140 int i915_mutex_lock_interruptible(struct drm_device
*dev
)
142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
145 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
149 ret
= mutex_lock_interruptible(&dev
->struct_mutex
);
153 WARN_ON(i915_verify_lists(dev
));
158 i915_gem_object_is_inactive(struct drm_i915_gem_object
*obj
)
160 return i915_gem_obj_bound_any(obj
) && !obj
->active
;
164 i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
165 struct drm_file
*file
)
167 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
168 struct drm_i915_gem_init
*args
= data
;
170 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
173 if (args
->gtt_start
>= args
->gtt_end
||
174 (args
->gtt_end
| args
->gtt_start
) & (PAGE_SIZE
- 1))
177 /* GEM with user mode setting was never supported on ilk and later. */
178 if (INTEL_INFO(dev
)->gen
>= 5)
181 mutex_lock(&dev
->struct_mutex
);
182 i915_gem_setup_global_gtt(dev
, args
->gtt_start
, args
->gtt_end
,
184 dev_priv
->gtt
.mappable_end
= args
->gtt_end
;
185 mutex_unlock(&dev
->struct_mutex
);
191 i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
192 struct drm_file
*file
)
194 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
195 struct drm_i915_gem_get_aperture
*args
= data
;
196 struct drm_i915_gem_object
*obj
;
200 mutex_lock(&dev
->struct_mutex
);
201 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
)
202 if (i915_gem_obj_is_pinned(obj
))
203 pinned
+= i915_gem_obj_ggtt_size(obj
);
204 mutex_unlock(&dev
->struct_mutex
);
206 args
->aper_size
= dev_priv
->gtt
.base
.total
;
207 args
->aper_available_size
= args
->aper_size
- pinned
;
212 static void i915_gem_object_detach_phys(struct drm_i915_gem_object
*obj
)
214 drm_dma_handle_t
*phys
= obj
->phys_handle
;
219 if (obj
->madv
== I915_MADV_WILLNEED
) {
220 struct address_space
*mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
221 char *vaddr
= phys
->vaddr
;
224 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
225 struct page
*page
= shmem_read_mapping_page(mapping
, i
);
227 char *dst
= kmap_atomic(page
);
228 memcpy(dst
, vaddr
, PAGE_SIZE
);
229 drm_clflush_virt_range(dst
, PAGE_SIZE
);
232 set_page_dirty(page
);
233 mark_page_accessed(page
);
234 page_cache_release(page
);
238 i915_gem_chipset_flush(obj
->base
.dev
);
242 set_memory_wb((unsigned long)phys
->vaddr
, phys
->size
/ PAGE_SIZE
);
244 drm_pci_free(obj
->base
.dev
, phys
);
245 obj
->phys_handle
= NULL
;
249 i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
252 drm_dma_handle_t
*phys
;
253 struct address_space
*mapping
;
257 if (obj
->phys_handle
) {
258 if ((unsigned long)obj
->phys_handle
->vaddr
& (align
-1))
264 if (obj
->madv
!= I915_MADV_WILLNEED
)
267 if (obj
->base
.filp
== NULL
)
270 /* create a new object */
271 phys
= drm_pci_alloc(obj
->base
.dev
, obj
->base
.size
, align
);
277 set_memory_wc((unsigned long)vaddr
, phys
->size
/ PAGE_SIZE
);
279 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
280 for (i
= 0; i
< obj
->base
.size
/ PAGE_SIZE
; i
++) {
284 page
= shmem_read_mapping_page(mapping
, i
);
287 set_memory_wb((unsigned long)phys
->vaddr
, phys
->size
/ PAGE_SIZE
);
289 drm_pci_free(obj
->base
.dev
, phys
);
290 return PTR_ERR(page
);
293 src
= kmap_atomic(page
);
294 memcpy(vaddr
, src
, PAGE_SIZE
);
297 mark_page_accessed(page
);
298 page_cache_release(page
);
303 obj
->phys_handle
= phys
;
308 i915_gem_phys_pwrite(struct drm_i915_gem_object
*obj
,
309 struct drm_i915_gem_pwrite
*args
,
310 struct drm_file
*file_priv
)
312 struct drm_device
*dev
= obj
->base
.dev
;
313 void *vaddr
= obj
->phys_handle
->vaddr
+ args
->offset
;
314 char __user
*user_data
= to_user_ptr(args
->data_ptr
);
316 if (__copy_from_user_inatomic_nocache(vaddr
, user_data
, args
->size
)) {
317 unsigned long unwritten
;
319 /* The physical object once assigned is fixed for the lifetime
320 * of the obj, so we can safely drop the lock and continue
323 mutex_unlock(&dev
->struct_mutex
);
324 unwritten
= copy_from_user(vaddr
, user_data
, args
->size
);
325 mutex_lock(&dev
->struct_mutex
);
330 i915_gem_chipset_flush(dev
);
334 void *i915_gem_object_alloc(struct drm_device
*dev
)
336 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
337 return kmem_cache_zalloc(dev_priv
->slab
, GFP_KERNEL
);
340 void i915_gem_object_free(struct drm_i915_gem_object
*obj
)
342 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
343 kmem_cache_free(dev_priv
->slab
, obj
);
347 i915_gem_create(struct drm_file
*file
,
348 struct drm_device
*dev
,
352 struct drm_i915_gem_object
*obj
;
356 size
= roundup(size
, PAGE_SIZE
);
360 /* Allocate the new object */
361 obj
= i915_gem_alloc_object(dev
, size
);
365 ret
= drm_gem_handle_create(file
, &obj
->base
, &handle
);
366 /* drop reference from allocate - handle holds it now */
367 drm_gem_object_unreference_unlocked(&obj
->base
);
376 i915_gem_dumb_create(struct drm_file
*file
,
377 struct drm_device
*dev
,
378 struct drm_mode_create_dumb
*args
)
380 /* have to work out size/pitch and return them */
381 args
->pitch
= ALIGN(args
->width
* DIV_ROUND_UP(args
->bpp
, 8), 64);
382 args
->size
= args
->pitch
* args
->height
;
383 return i915_gem_create(file
, dev
,
384 args
->size
, &args
->handle
);
388 * Creates a new mm object and returns a handle to it.
391 i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
392 struct drm_file
*file
)
394 struct drm_i915_gem_create
*args
= data
;
396 return i915_gem_create(file
, dev
,
397 args
->size
, &args
->handle
);
401 __copy_to_user_swizzled(char __user
*cpu_vaddr
,
402 const char *gpu_vaddr
, int gpu_offset
,
405 int ret
, cpu_offset
= 0;
408 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
409 int this_length
= min(cacheline_end
- gpu_offset
, length
);
410 int swizzled_gpu_offset
= gpu_offset
^ 64;
412 ret
= __copy_to_user(cpu_vaddr
+ cpu_offset
,
413 gpu_vaddr
+ swizzled_gpu_offset
,
418 cpu_offset
+= this_length
;
419 gpu_offset
+= this_length
;
420 length
-= this_length
;
427 __copy_from_user_swizzled(char *gpu_vaddr
, int gpu_offset
,
428 const char __user
*cpu_vaddr
,
431 int ret
, cpu_offset
= 0;
434 int cacheline_end
= ALIGN(gpu_offset
+ 1, 64);
435 int this_length
= min(cacheline_end
- gpu_offset
, length
);
436 int swizzled_gpu_offset
= gpu_offset
^ 64;
438 ret
= __copy_from_user(gpu_vaddr
+ swizzled_gpu_offset
,
439 cpu_vaddr
+ cpu_offset
,
444 cpu_offset
+= this_length
;
445 gpu_offset
+= this_length
;
446 length
-= this_length
;
453 * Pins the specified object's pages and synchronizes the object with
454 * GPU accesses. Sets needs_clflush to non-zero if the caller should
455 * flush the object from the CPU cache.
457 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
467 if (!(obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
)) {
468 /* If we're not in the cpu read domain, set ourself into the gtt
469 * read domain and manually flush cachelines (if required). This
470 * optimizes for the case when the gpu will dirty the data
471 * anyway again before the next pread happens. */
472 *needs_clflush
= !cpu_cache_is_coherent(obj
->base
.dev
,
474 ret
= i915_gem_object_wait_rendering(obj
, true);
478 i915_gem_object_retire(obj
);
481 ret
= i915_gem_object_get_pages(obj
);
485 i915_gem_object_pin_pages(obj
);
490 /* Per-page copy function for the shmem pread fastpath.
491 * Flushes invalid cachelines before reading the target if
492 * needs_clflush is set. */
494 shmem_pread_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
495 char __user
*user_data
,
496 bool page_do_bit17_swizzling
, bool needs_clflush
)
501 if (unlikely(page_do_bit17_swizzling
))
504 vaddr
= kmap_atomic(page
);
506 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
508 ret
= __copy_to_user_inatomic(user_data
,
509 vaddr
+ shmem_page_offset
,
511 kunmap_atomic(vaddr
);
513 return ret
? -EFAULT
: 0;
517 shmem_clflush_swizzled_range(char *addr
, unsigned long length
,
520 if (unlikely(swizzled
)) {
521 unsigned long start
= (unsigned long) addr
;
522 unsigned long end
= (unsigned long) addr
+ length
;
524 /* For swizzling simply ensure that we always flush both
525 * channels. Lame, but simple and it works. Swizzled
526 * pwrite/pread is far from a hotpath - current userspace
527 * doesn't use it at all. */
528 start
= round_down(start
, 128);
529 end
= round_up(end
, 128);
531 drm_clflush_virt_range((void *)start
, end
- start
);
533 drm_clflush_virt_range(addr
, length
);
538 /* Only difference to the fast-path function is that this can handle bit17
539 * and uses non-atomic copy and kmap functions. */
541 shmem_pread_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
542 char __user
*user_data
,
543 bool page_do_bit17_swizzling
, bool needs_clflush
)
550 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
552 page_do_bit17_swizzling
);
554 if (page_do_bit17_swizzling
)
555 ret
= __copy_to_user_swizzled(user_data
,
556 vaddr
, shmem_page_offset
,
559 ret
= __copy_to_user(user_data
,
560 vaddr
+ shmem_page_offset
,
564 return ret
? - EFAULT
: 0;
568 i915_gem_shmem_pread(struct drm_device
*dev
,
569 struct drm_i915_gem_object
*obj
,
570 struct drm_i915_gem_pread
*args
,
571 struct drm_file
*file
)
573 char __user
*user_data
;
576 int shmem_page_offset
, page_length
, ret
= 0;
577 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
579 int needs_clflush
= 0;
580 struct sg_page_iter sg_iter
;
582 user_data
= to_user_ptr(args
->data_ptr
);
585 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
587 ret
= i915_gem_obj_prepare_shmem_read(obj
, &needs_clflush
);
591 offset
= args
->offset
;
593 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
594 offset
>> PAGE_SHIFT
) {
595 struct page
*page
= sg_page_iter_page(&sg_iter
);
600 /* Operation in this page
602 * shmem_page_offset = offset within page in shmem file
603 * page_length = bytes to copy for this page
605 shmem_page_offset
= offset_in_page(offset
);
606 page_length
= remain
;
607 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
608 page_length
= PAGE_SIZE
- shmem_page_offset
;
610 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
611 (page_to_phys(page
) & (1 << 17)) != 0;
613 ret
= shmem_pread_fast(page
, shmem_page_offset
, page_length
,
614 user_data
, page_do_bit17_swizzling
,
619 mutex_unlock(&dev
->struct_mutex
);
621 if (likely(!i915
.prefault_disable
) && !prefaulted
) {
622 ret
= fault_in_multipages_writeable(user_data
, remain
);
623 /* Userspace is tricking us, but we've already clobbered
624 * its pages with the prefault and promised to write the
625 * data up to the first fault. Hence ignore any errors
626 * and just continue. */
631 ret
= shmem_pread_slow(page
, shmem_page_offset
, page_length
,
632 user_data
, page_do_bit17_swizzling
,
635 mutex_lock(&dev
->struct_mutex
);
641 remain
-= page_length
;
642 user_data
+= page_length
;
643 offset
+= page_length
;
647 i915_gem_object_unpin_pages(obj
);
653 * Reads data from the object referenced by handle.
655 * On error, the contents of *data are undefined.
658 i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
659 struct drm_file
*file
)
661 struct drm_i915_gem_pread
*args
= data
;
662 struct drm_i915_gem_object
*obj
;
668 if (!access_ok(VERIFY_WRITE
,
669 to_user_ptr(args
->data_ptr
),
673 ret
= i915_mutex_lock_interruptible(dev
);
677 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
678 if (&obj
->base
== NULL
) {
683 /* Bounds check source. */
684 if (args
->offset
> obj
->base
.size
||
685 args
->size
> obj
->base
.size
- args
->offset
) {
690 /* prime objects have no backing filp to GEM pread/pwrite
693 if (!obj
->base
.filp
) {
698 trace_i915_gem_object_pread(obj
, args
->offset
, args
->size
);
700 ret
= i915_gem_shmem_pread(dev
, obj
, args
, file
);
703 drm_gem_object_unreference(&obj
->base
);
705 mutex_unlock(&dev
->struct_mutex
);
709 /* This is the fast write path which cannot handle
710 * page faults in the source data
714 fast_user_write(struct io_mapping
*mapping
,
715 loff_t page_base
, int page_offset
,
716 char __user
*user_data
,
719 void __iomem
*vaddr_atomic
;
721 unsigned long unwritten
;
723 vaddr_atomic
= io_mapping_map_atomic_wc(mapping
, page_base
);
724 /* We can use the cpu mem copy function because this is X86. */
725 vaddr
= (void __force
*)vaddr_atomic
+ page_offset
;
726 unwritten
= __copy_from_user_inatomic_nocache(vaddr
,
728 io_mapping_unmap_atomic(vaddr_atomic
);
733 * This is the fast pwrite path, where we copy the data directly from the
734 * user into the GTT, uncached.
737 i915_gem_gtt_pwrite_fast(struct drm_device
*dev
,
738 struct drm_i915_gem_object
*obj
,
739 struct drm_i915_gem_pwrite
*args
,
740 struct drm_file
*file
)
742 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
744 loff_t offset
, page_base
;
745 char __user
*user_data
;
746 int page_offset
, page_length
, ret
;
748 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
| PIN_NONBLOCK
);
752 ret
= i915_gem_object_set_to_gtt_domain(obj
, true);
756 ret
= i915_gem_object_put_fence(obj
);
760 user_data
= to_user_ptr(args
->data_ptr
);
763 offset
= i915_gem_obj_ggtt_offset(obj
) + args
->offset
;
766 /* Operation in this page
768 * page_base = page offset within aperture
769 * page_offset = offset within page
770 * page_length = bytes to copy for this page
772 page_base
= offset
& PAGE_MASK
;
773 page_offset
= offset_in_page(offset
);
774 page_length
= remain
;
775 if ((page_offset
+ remain
) > PAGE_SIZE
)
776 page_length
= PAGE_SIZE
- page_offset
;
778 /* If we get a fault while copying data, then (presumably) our
779 * source page isn't available. Return the error and we'll
780 * retry in the slow path.
782 if (fast_user_write(dev_priv
->gtt
.mappable
, page_base
,
783 page_offset
, user_data
, page_length
)) {
788 remain
-= page_length
;
789 user_data
+= page_length
;
790 offset
+= page_length
;
794 i915_gem_object_ggtt_unpin(obj
);
799 /* Per-page copy function for the shmem pwrite fastpath.
800 * Flushes invalid cachelines before writing to the target if
801 * needs_clflush_before is set and flushes out any written cachelines after
802 * writing if needs_clflush is set. */
804 shmem_pwrite_fast(struct page
*page
, int shmem_page_offset
, int page_length
,
805 char __user
*user_data
,
806 bool page_do_bit17_swizzling
,
807 bool needs_clflush_before
,
808 bool needs_clflush_after
)
813 if (unlikely(page_do_bit17_swizzling
))
816 vaddr
= kmap_atomic(page
);
817 if (needs_clflush_before
)
818 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
820 ret
= __copy_from_user_inatomic(vaddr
+ shmem_page_offset
,
821 user_data
, page_length
);
822 if (needs_clflush_after
)
823 drm_clflush_virt_range(vaddr
+ shmem_page_offset
,
825 kunmap_atomic(vaddr
);
827 return ret
? -EFAULT
: 0;
830 /* Only difference to the fast-path function is that this can handle bit17
831 * and uses non-atomic copy and kmap functions. */
833 shmem_pwrite_slow(struct page
*page
, int shmem_page_offset
, int page_length
,
834 char __user
*user_data
,
835 bool page_do_bit17_swizzling
,
836 bool needs_clflush_before
,
837 bool needs_clflush_after
)
843 if (unlikely(needs_clflush_before
|| page_do_bit17_swizzling
))
844 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
846 page_do_bit17_swizzling
);
847 if (page_do_bit17_swizzling
)
848 ret
= __copy_from_user_swizzled(vaddr
, shmem_page_offset
,
852 ret
= __copy_from_user(vaddr
+ shmem_page_offset
,
855 if (needs_clflush_after
)
856 shmem_clflush_swizzled_range(vaddr
+ shmem_page_offset
,
858 page_do_bit17_swizzling
);
861 return ret
? -EFAULT
: 0;
865 i915_gem_shmem_pwrite(struct drm_device
*dev
,
866 struct drm_i915_gem_object
*obj
,
867 struct drm_i915_gem_pwrite
*args
,
868 struct drm_file
*file
)
872 char __user
*user_data
;
873 int shmem_page_offset
, page_length
, ret
= 0;
874 int obj_do_bit17_swizzling
, page_do_bit17_swizzling
;
875 int hit_slowpath
= 0;
876 int needs_clflush_after
= 0;
877 int needs_clflush_before
= 0;
878 struct sg_page_iter sg_iter
;
880 user_data
= to_user_ptr(args
->data_ptr
);
883 obj_do_bit17_swizzling
= i915_gem_object_needs_bit17_swizzle(obj
);
885 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
886 /* If we're not in the cpu write domain, set ourself into the gtt
887 * write domain and manually flush cachelines (if required). This
888 * optimizes for the case when the gpu will use the data
889 * right away and we therefore have to clflush anyway. */
890 needs_clflush_after
= cpu_write_needs_clflush(obj
);
891 ret
= i915_gem_object_wait_rendering(obj
, false);
895 i915_gem_object_retire(obj
);
897 /* Same trick applies to invalidate partially written cachelines read
899 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0)
900 needs_clflush_before
=
901 !cpu_cache_is_coherent(dev
, obj
->cache_level
);
903 ret
= i915_gem_object_get_pages(obj
);
907 i915_gem_object_pin_pages(obj
);
909 offset
= args
->offset
;
912 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
,
913 offset
>> PAGE_SHIFT
) {
914 struct page
*page
= sg_page_iter_page(&sg_iter
);
915 int partial_cacheline_write
;
920 /* Operation in this page
922 * shmem_page_offset = offset within page in shmem file
923 * page_length = bytes to copy for this page
925 shmem_page_offset
= offset_in_page(offset
);
927 page_length
= remain
;
928 if ((shmem_page_offset
+ page_length
) > PAGE_SIZE
)
929 page_length
= PAGE_SIZE
- shmem_page_offset
;
931 /* If we don't overwrite a cacheline completely we need to be
932 * careful to have up-to-date data by first clflushing. Don't
933 * overcomplicate things and flush the entire patch. */
934 partial_cacheline_write
= needs_clflush_before
&&
935 ((shmem_page_offset
| page_length
)
936 & (boot_cpu_data
.x86_clflush_size
- 1));
938 page_do_bit17_swizzling
= obj_do_bit17_swizzling
&&
939 (page_to_phys(page
) & (1 << 17)) != 0;
941 ret
= shmem_pwrite_fast(page
, shmem_page_offset
, page_length
,
942 user_data
, page_do_bit17_swizzling
,
943 partial_cacheline_write
,
944 needs_clflush_after
);
949 mutex_unlock(&dev
->struct_mutex
);
950 ret
= shmem_pwrite_slow(page
, shmem_page_offset
, page_length
,
951 user_data
, page_do_bit17_swizzling
,
952 partial_cacheline_write
,
953 needs_clflush_after
);
955 mutex_lock(&dev
->struct_mutex
);
961 remain
-= page_length
;
962 user_data
+= page_length
;
963 offset
+= page_length
;
967 i915_gem_object_unpin_pages(obj
);
971 * Fixup: Flush cpu caches in case we didn't flush the dirty
972 * cachelines in-line while writing and the object moved
973 * out of the cpu write domain while we've dropped the lock.
975 if (!needs_clflush_after
&&
976 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
) {
977 if (i915_gem_clflush_object(obj
, obj
->pin_display
))
978 i915_gem_chipset_flush(dev
);
982 if (needs_clflush_after
)
983 i915_gem_chipset_flush(dev
);
989 * Writes data to the object referenced by handle.
991 * On error, the contents of the buffer that were to be modified are undefined.
994 i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
995 struct drm_file
*file
)
997 struct drm_i915_gem_pwrite
*args
= data
;
998 struct drm_i915_gem_object
*obj
;
1001 if (args
->size
== 0)
1004 if (!access_ok(VERIFY_READ
,
1005 to_user_ptr(args
->data_ptr
),
1009 if (likely(!i915
.prefault_disable
)) {
1010 ret
= fault_in_multipages_readable(to_user_ptr(args
->data_ptr
),
1016 ret
= i915_mutex_lock_interruptible(dev
);
1020 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1021 if (&obj
->base
== NULL
) {
1026 /* Bounds check destination. */
1027 if (args
->offset
> obj
->base
.size
||
1028 args
->size
> obj
->base
.size
- args
->offset
) {
1033 /* prime objects have no backing filp to GEM pread/pwrite
1036 if (!obj
->base
.filp
) {
1041 trace_i915_gem_object_pwrite(obj
, args
->offset
, args
->size
);
1044 /* We can only do the GTT pwrite on untiled buffers, as otherwise
1045 * it would end up going through the fenced access, and we'll get
1046 * different detiling behavior between reading and writing.
1047 * pread/pwrite currently are reading and writing from the CPU
1048 * perspective, requiring manual detiling by the client.
1050 if (obj
->phys_handle
) {
1051 ret
= i915_gem_phys_pwrite(obj
, args
, file
);
1055 if (obj
->tiling_mode
== I915_TILING_NONE
&&
1056 obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
&&
1057 cpu_write_needs_clflush(obj
)) {
1058 ret
= i915_gem_gtt_pwrite_fast(dev
, obj
, args
, file
);
1059 /* Note that the gtt paths might fail with non-page-backed user
1060 * pointers (e.g. gtt mappings when moving data between
1061 * textures). Fallback to the shmem path in that case. */
1064 if (ret
== -EFAULT
|| ret
== -ENOSPC
)
1065 ret
= i915_gem_shmem_pwrite(dev
, obj
, args
, file
);
1068 drm_gem_object_unreference(&obj
->base
);
1070 mutex_unlock(&dev
->struct_mutex
);
1075 i915_gem_check_wedge(struct i915_gpu_error
*error
,
1078 if (i915_reset_in_progress(error
)) {
1079 /* Non-interruptible callers can't handle -EAGAIN, hence return
1080 * -EIO unconditionally for these. */
1084 /* Recovery complete, but the reset failed ... */
1085 if (i915_terminally_wedged(error
))
1095 * Compare seqno against outstanding lazy request. Emit a request if they are
1099 i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
)
1103 BUG_ON(!mutex_is_locked(&ring
->dev
->struct_mutex
));
1106 if (seqno
== ring
->outstanding_lazy_seqno
)
1107 ret
= i915_add_request(ring
, NULL
);
1112 static void fake_irq(unsigned long data
)
1114 wake_up_process((struct task_struct
*)data
);
1117 static bool missed_irq(struct drm_i915_private
*dev_priv
,
1118 struct intel_engine_cs
*ring
)
1120 return test_bit(ring
->id
, &dev_priv
->gpu_error
.missed_irq_rings
);
1123 static bool can_wait_boost(struct drm_i915_file_private
*file_priv
)
1125 if (file_priv
== NULL
)
1128 return !atomic_xchg(&file_priv
->rps_wait_boost
, true);
1132 * __wait_seqno - wait until execution of seqno has finished
1133 * @ring: the ring expected to report seqno
1135 * @reset_counter: reset sequence associated with the given seqno
1136 * @interruptible: do an interruptible wait (normally yes)
1137 * @timeout: in - how long to wait (NULL forever); out - how much time remaining
1139 * Note: It is of utmost importance that the passed in seqno and reset_counter
1140 * values have been read by the caller in an smp safe manner. Where read-side
1141 * locks are involved, it is sufficient to read the reset_counter before
1142 * unlocking the lock that protects the seqno. For lockless tricks, the
1143 * reset_counter _must_ be read before, and an appropriate smp_rmb must be
1146 * Returns 0 if the seqno was found within the alloted time. Else returns the
1147 * errno with remaining time filled in timeout argument.
1149 static int __wait_seqno(struct intel_engine_cs
*ring
, u32 seqno
,
1150 unsigned reset_counter
,
1152 struct timespec
*timeout
,
1153 struct drm_i915_file_private
*file_priv
)
1155 struct drm_device
*dev
= ring
->dev
;
1156 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1157 const bool irq_test_in_progress
=
1158 ACCESS_ONCE(dev_priv
->gpu_error
.test_irq_rings
) & intel_ring_flag(ring
);
1159 struct timespec before
, now
;
1161 unsigned long timeout_expire
;
1164 WARN(dev_priv
->pm
.irqs_disabled
, "IRQs disabled\n");
1166 if (i915_seqno_passed(ring
->get_seqno(ring
, true), seqno
))
1169 timeout_expire
= timeout
? jiffies
+ timespec_to_jiffies_timeout(timeout
) : 0;
1171 if (INTEL_INFO(dev
)->gen
>= 6 && can_wait_boost(file_priv
)) {
1172 gen6_rps_boost(dev_priv
);
1174 mod_delayed_work(dev_priv
->wq
,
1175 &file_priv
->mm
.idle_work
,
1176 msecs_to_jiffies(100));
1179 if (!irq_test_in_progress
&& WARN_ON(!ring
->irq_get(ring
)))
1182 /* Record current time in case interrupted by signal, or wedged */
1183 trace_i915_gem_request_wait_begin(ring
, seqno
);
1184 getrawmonotonic(&before
);
1186 struct timer_list timer
;
1188 prepare_to_wait(&ring
->irq_queue
, &wait
,
1189 interruptible
? TASK_INTERRUPTIBLE
: TASK_UNINTERRUPTIBLE
);
1191 /* We need to check whether any gpu reset happened in between
1192 * the caller grabbing the seqno and now ... */
1193 if (reset_counter
!= atomic_read(&dev_priv
->gpu_error
.reset_counter
)) {
1194 /* ... but upgrade the -EAGAIN to an -EIO if the gpu
1195 * is truely gone. */
1196 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1202 if (i915_seqno_passed(ring
->get_seqno(ring
, false), seqno
)) {
1207 if (interruptible
&& signal_pending(current
)) {
1212 if (timeout
&& time_after_eq(jiffies
, timeout_expire
)) {
1217 timer
.function
= NULL
;
1218 if (timeout
|| missed_irq(dev_priv
, ring
)) {
1219 unsigned long expire
;
1221 setup_timer_on_stack(&timer
, fake_irq
, (unsigned long)current
);
1222 expire
= missed_irq(dev_priv
, ring
) ? jiffies
+ 1 : timeout_expire
;
1223 mod_timer(&timer
, expire
);
1228 if (timer
.function
) {
1229 del_singleshot_timer_sync(&timer
);
1230 destroy_timer_on_stack(&timer
);
1233 getrawmonotonic(&now
);
1234 trace_i915_gem_request_wait_end(ring
, seqno
);
1236 if (!irq_test_in_progress
)
1237 ring
->irq_put(ring
);
1239 finish_wait(&ring
->irq_queue
, &wait
);
1242 struct timespec sleep_time
= timespec_sub(now
, before
);
1243 *timeout
= timespec_sub(*timeout
, sleep_time
);
1244 if (!timespec_valid(timeout
)) /* i.e. negative time remains */
1245 set_normalized_timespec(timeout
, 0, 0);
1252 * Waits for a sequence number to be signaled, and cleans up the
1253 * request and object lists appropriately for that event.
1256 i915_wait_seqno(struct intel_engine_cs
*ring
, uint32_t seqno
)
1258 struct drm_device
*dev
= ring
->dev
;
1259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1260 bool interruptible
= dev_priv
->mm
.interruptible
;
1263 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1266 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, interruptible
);
1270 ret
= i915_gem_check_olr(ring
, seqno
);
1274 return __wait_seqno(ring
, seqno
,
1275 atomic_read(&dev_priv
->gpu_error
.reset_counter
),
1276 interruptible
, NULL
, NULL
);
1280 i915_gem_object_wait_rendering__tail(struct drm_i915_gem_object
*obj
,
1281 struct intel_engine_cs
*ring
)
1286 /* Manually manage the write flush as we may have not yet
1287 * retired the buffer.
1289 * Note that the last_write_seqno is always the earlier of
1290 * the two (read/write) seqno, so if we haved successfully waited,
1291 * we know we have passed the last write.
1293 obj
->last_write_seqno
= 0;
1299 * Ensures that all rendering to the object has completed and the object is
1300 * safe to unbind from the GTT or access from the CPU.
1302 static __must_check
int
1303 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
1306 struct intel_engine_cs
*ring
= obj
->ring
;
1310 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1314 ret
= i915_wait_seqno(ring
, seqno
);
1318 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1321 /* A nonblocking variant of the above wait. This is a highly dangerous routine
1322 * as the object state may change during this call.
1324 static __must_check
int
1325 i915_gem_object_wait_rendering__nonblocking(struct drm_i915_gem_object
*obj
,
1326 struct drm_i915_file_private
*file_priv
,
1329 struct drm_device
*dev
= obj
->base
.dev
;
1330 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1331 struct intel_engine_cs
*ring
= obj
->ring
;
1332 unsigned reset_counter
;
1336 BUG_ON(!mutex_is_locked(&dev
->struct_mutex
));
1337 BUG_ON(!dev_priv
->mm
.interruptible
);
1339 seqno
= readonly
? obj
->last_write_seqno
: obj
->last_read_seqno
;
1343 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, true);
1347 ret
= i915_gem_check_olr(ring
, seqno
);
1351 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
1352 mutex_unlock(&dev
->struct_mutex
);
1353 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, file_priv
);
1354 mutex_lock(&dev
->struct_mutex
);
1358 return i915_gem_object_wait_rendering__tail(obj
, ring
);
1362 * Called when user space prepares to use an object with the CPU, either
1363 * through the mmap ioctl's mapping or a GTT mapping.
1366 i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1367 struct drm_file
*file
)
1369 struct drm_i915_gem_set_domain
*args
= data
;
1370 struct drm_i915_gem_object
*obj
;
1371 uint32_t read_domains
= args
->read_domains
;
1372 uint32_t write_domain
= args
->write_domain
;
1375 /* Only handle setting domains to types used by the CPU. */
1376 if (write_domain
& I915_GEM_GPU_DOMAINS
)
1379 if (read_domains
& I915_GEM_GPU_DOMAINS
)
1382 /* Having something in the write domain implies it's in the read
1383 * domain, and only that read domain. Enforce that in the request.
1385 if (write_domain
!= 0 && read_domains
!= write_domain
)
1388 ret
= i915_mutex_lock_interruptible(dev
);
1392 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1393 if (&obj
->base
== NULL
) {
1398 intel_edp_psr_exit(dev
, true);
1400 /* Try to flush the object off the GPU without holding the lock.
1401 * We will repeat the flush holding the lock in the normal manner
1402 * to catch cases where we are gazumped.
1404 ret
= i915_gem_object_wait_rendering__nonblocking(obj
,
1410 if (read_domains
& I915_GEM_DOMAIN_GTT
) {
1411 ret
= i915_gem_object_set_to_gtt_domain(obj
, write_domain
!= 0);
1413 /* Silently promote "you're not bound, there was nothing to do"
1414 * to success, since the client was just asking us to
1415 * make sure everything was done.
1420 ret
= i915_gem_object_set_to_cpu_domain(obj
, write_domain
!= 0);
1424 drm_gem_object_unreference(&obj
->base
);
1426 mutex_unlock(&dev
->struct_mutex
);
1431 * Called when user space has done writes to this buffer
1434 i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1435 struct drm_file
*file
)
1437 struct drm_i915_gem_sw_finish
*args
= data
;
1438 struct drm_i915_gem_object
*obj
;
1441 ret
= i915_mutex_lock_interruptible(dev
);
1445 intel_edp_psr_exit(dev
, true);
1447 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
1448 if (&obj
->base
== NULL
) {
1453 /* Pinned buffers may be scanout, so flush the cache */
1454 if (obj
->pin_display
)
1455 i915_gem_object_flush_cpu_write_domain(obj
, true);
1457 drm_gem_object_unreference(&obj
->base
);
1459 mutex_unlock(&dev
->struct_mutex
);
1464 * Maps the contents of an object, returning the address it is mapped
1467 * While the mapping holds a reference on the contents of the object, it doesn't
1468 * imply a ref on the object itself.
1471 i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1472 struct drm_file
*file
)
1474 struct drm_i915_gem_mmap
*args
= data
;
1475 struct drm_gem_object
*obj
;
1478 obj
= drm_gem_object_lookup(dev
, file
, args
->handle
);
1482 /* prime objects have no backing filp to GEM mmap
1486 drm_gem_object_unreference_unlocked(obj
);
1490 addr
= vm_mmap(obj
->filp
, 0, args
->size
,
1491 PROT_READ
| PROT_WRITE
, MAP_SHARED
,
1493 drm_gem_object_unreference_unlocked(obj
);
1494 if (IS_ERR((void *)addr
))
1497 args
->addr_ptr
= (uint64_t) addr
;
1503 * i915_gem_fault - fault a page into the GTT
1504 * vma: VMA in question
1507 * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped
1508 * from userspace. The fault handler takes care of binding the object to
1509 * the GTT (if needed), allocating and programming a fence register (again,
1510 * only if needed based on whether the old reg is still valid or the object
1511 * is tiled) and inserting a new PTE into the faulting process.
1513 * Note that the faulting process may involve evicting existing objects
1514 * from the GTT and/or fence registers to make room. So performance may
1515 * suffer if the GTT working set is large or there are few fence registers
1518 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
)
1520 struct drm_i915_gem_object
*obj
= to_intel_bo(vma
->vm_private_data
);
1521 struct drm_device
*dev
= obj
->base
.dev
;
1522 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1523 pgoff_t page_offset
;
1526 bool write
= !!(vmf
->flags
& FAULT_FLAG_WRITE
);
1528 intel_runtime_pm_get(dev_priv
);
1530 /* We don't use vmf->pgoff since that has the fake offset */
1531 page_offset
= ((unsigned long)vmf
->virtual_address
- vma
->vm_start
) >>
1534 ret
= i915_mutex_lock_interruptible(dev
);
1538 trace_i915_gem_object_fault(obj
, page_offset
, true, write
);
1540 /* Try to flush the object off the GPU first without holding the lock.
1541 * Upon reacquiring the lock, we will perform our sanity checks and then
1542 * repeat the flush holding the lock in the normal manner to catch cases
1543 * where we are gazumped.
1545 ret
= i915_gem_object_wait_rendering__nonblocking(obj
, NULL
, !write
);
1549 /* Access to snoopable pages through the GTT is incoherent. */
1550 if (obj
->cache_level
!= I915_CACHE_NONE
&& !HAS_LLC(dev
)) {
1555 /* Now bind it into the GTT if needed */
1556 ret
= i915_gem_obj_ggtt_pin(obj
, 0, PIN_MAPPABLE
);
1560 ret
= i915_gem_object_set_to_gtt_domain(obj
, write
);
1564 ret
= i915_gem_object_get_fence(obj
);
1568 /* Finally, remap it using the new GTT offset */
1569 pfn
= dev_priv
->gtt
.mappable_base
+ i915_gem_obj_ggtt_offset(obj
);
1572 if (!obj
->fault_mappable
) {
1575 for (i
= 0; i
< obj
->base
.size
>> PAGE_SHIFT
; i
++) {
1576 ret
= vm_insert_pfn(vma
,
1577 (unsigned long)vma
->vm_start
+ i
* PAGE_SIZE
,
1583 obj
->fault_mappable
= true;
1585 ret
= vm_insert_pfn(vma
,
1586 (unsigned long)vmf
->virtual_address
,
1589 i915_gem_object_ggtt_unpin(obj
);
1591 mutex_unlock(&dev
->struct_mutex
);
1595 /* If this -EIO is due to a gpu hang, give the reset code a
1596 * chance to clean up the mess. Otherwise return the proper
1598 if (i915_terminally_wedged(&dev_priv
->gpu_error
)) {
1599 ret
= VM_FAULT_SIGBUS
;
1604 * EAGAIN means the gpu is hung and we'll wait for the error
1605 * handler to reset everything when re-faulting in
1606 * i915_mutex_lock_interruptible.
1613 * EBUSY is ok: this just means that another thread
1614 * already did the job.
1616 ret
= VM_FAULT_NOPAGE
;
1623 ret
= VM_FAULT_SIGBUS
;
1626 WARN_ONCE(ret
, "unhandled error in i915_gem_fault: %i\n", ret
);
1627 ret
= VM_FAULT_SIGBUS
;
1631 intel_runtime_pm_put(dev_priv
);
1635 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
)
1637 struct i915_vma
*vma
;
1640 * Only the global gtt is relevant for gtt memory mappings, so restrict
1641 * list traversal to objects bound into the global address space. Note
1642 * that the active list should be empty, but better safe than sorry.
1644 WARN_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
1645 list_for_each_entry(vma
, &dev_priv
->gtt
.base
.active_list
, mm_list
)
1646 i915_gem_release_mmap(vma
->obj
);
1647 list_for_each_entry(vma
, &dev_priv
->gtt
.base
.inactive_list
, mm_list
)
1648 i915_gem_release_mmap(vma
->obj
);
1652 * i915_gem_release_mmap - remove physical page mappings
1653 * @obj: obj in question
1655 * Preserve the reservation of the mmapping with the DRM core code, but
1656 * relinquish ownership of the pages back to the system.
1658 * It is vital that we remove the page mapping if we have mapped a tiled
1659 * object through the GTT and then lose the fence register due to
1660 * resource pressure. Similarly if the object has been moved out of the
1661 * aperture, than pages mapped into userspace must be revoked. Removing the
1662 * mapping will then trigger a page fault on the next user access, allowing
1663 * fixup by i915_gem_fault().
1666 i915_gem_release_mmap(struct drm_i915_gem_object
*obj
)
1668 if (!obj
->fault_mappable
)
1671 drm_vma_node_unmap(&obj
->base
.vma_node
,
1672 obj
->base
.dev
->anon_inode
->i_mapping
);
1673 obj
->fault_mappable
= false;
1677 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
)
1681 if (INTEL_INFO(dev
)->gen
>= 4 ||
1682 tiling_mode
== I915_TILING_NONE
)
1685 /* Previous chips need a power-of-two fence region when tiling */
1686 if (INTEL_INFO(dev
)->gen
== 3)
1687 gtt_size
= 1024*1024;
1689 gtt_size
= 512*1024;
1691 while (gtt_size
< size
)
1698 * i915_gem_get_gtt_alignment - return required GTT alignment for an object
1699 * @obj: object to check
1701 * Return the required GTT alignment for an object, taking into account
1702 * potential fence register mapping.
1705 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1706 int tiling_mode
, bool fenced
)
1709 * Minimum alignment is 4k (GTT page size), but might be greater
1710 * if a fence register is needed for the object.
1712 if (INTEL_INFO(dev
)->gen
>= 4 || (!fenced
&& IS_G33(dev
)) ||
1713 tiling_mode
== I915_TILING_NONE
)
1717 * Previous chips need to be aligned to the size of the smallest
1718 * fence register that can contain the object.
1720 return i915_gem_get_gtt_size(dev
, size
, tiling_mode
);
1723 static int i915_gem_object_create_mmap_offset(struct drm_i915_gem_object
*obj
)
1725 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1728 if (drm_vma_node_has_offset(&obj
->base
.vma_node
))
1731 dev_priv
->mm
.shrinker_no_lock_stealing
= true;
1733 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1737 /* Badly fragmented mmap space? The only way we can recover
1738 * space is by destroying unwanted objects. We can't randomly release
1739 * mmap_offsets as userspace expects them to be persistent for the
1740 * lifetime of the objects. The closest we can is to release the
1741 * offsets on purgeable objects by truncating it and marking it purged,
1742 * which prevents userspace from ever using that object again.
1744 i915_gem_purge(dev_priv
, obj
->base
.size
>> PAGE_SHIFT
);
1745 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1749 i915_gem_shrink_all(dev_priv
);
1750 ret
= drm_gem_create_mmap_offset(&obj
->base
);
1752 dev_priv
->mm
.shrinker_no_lock_stealing
= false;
1757 static void i915_gem_object_free_mmap_offset(struct drm_i915_gem_object
*obj
)
1759 drm_gem_free_mmap_offset(&obj
->base
);
1763 i915_gem_mmap_gtt(struct drm_file
*file
,
1764 struct drm_device
*dev
,
1768 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1769 struct drm_i915_gem_object
*obj
;
1772 ret
= i915_mutex_lock_interruptible(dev
);
1776 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
1777 if (&obj
->base
== NULL
) {
1782 if (obj
->base
.size
> dev_priv
->gtt
.mappable_end
) {
1787 if (obj
->madv
!= I915_MADV_WILLNEED
) {
1788 DRM_DEBUG("Attempting to mmap a purgeable buffer\n");
1793 ret
= i915_gem_object_create_mmap_offset(obj
);
1797 *offset
= drm_vma_node_offset_addr(&obj
->base
.vma_node
);
1800 drm_gem_object_unreference(&obj
->base
);
1802 mutex_unlock(&dev
->struct_mutex
);
1807 * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing
1809 * @data: GTT mapping ioctl data
1810 * @file: GEM object info
1812 * Simply returns the fake offset to userspace so it can mmap it.
1813 * The mmap call will end up in drm_gem_mmap(), which will set things
1814 * up so we can get faults in the handler above.
1816 * The fault handler will take care of binding the object into the GTT
1817 * (since it may have been evicted to make room for something), allocating
1818 * a fence register, and mapping the appropriate aperture address into
1822 i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1823 struct drm_file
*file
)
1825 struct drm_i915_gem_mmap_gtt
*args
= data
;
1827 return i915_gem_mmap_gtt(file
, dev
, args
->handle
, &args
->offset
);
1831 i915_gem_object_is_purgeable(struct drm_i915_gem_object
*obj
)
1833 return obj
->madv
== I915_MADV_DONTNEED
;
1836 /* Immediately discard the backing storage */
1838 i915_gem_object_truncate(struct drm_i915_gem_object
*obj
)
1840 i915_gem_object_free_mmap_offset(obj
);
1842 if (obj
->base
.filp
== NULL
)
1845 /* Our goal here is to return as much of the memory as
1846 * is possible back to the system as we are called from OOM.
1847 * To do this we must instruct the shmfs to drop all of its
1848 * backing pages, *now*.
1850 shmem_truncate_range(file_inode(obj
->base
.filp
), 0, (loff_t
)-1);
1851 obj
->madv
= __I915_MADV_PURGED
;
1854 /* Try to discard unwanted pages */
1856 i915_gem_object_invalidate(struct drm_i915_gem_object
*obj
)
1858 struct address_space
*mapping
;
1860 switch (obj
->madv
) {
1861 case I915_MADV_DONTNEED
:
1862 i915_gem_object_truncate(obj
);
1863 case __I915_MADV_PURGED
:
1867 if (obj
->base
.filp
== NULL
)
1870 mapping
= file_inode(obj
->base
.filp
)->i_mapping
,
1871 invalidate_mapping_pages(mapping
, 0, (loff_t
)-1);
1875 i915_gem_object_put_pages_gtt(struct drm_i915_gem_object
*obj
)
1877 struct sg_page_iter sg_iter
;
1880 BUG_ON(obj
->madv
== __I915_MADV_PURGED
);
1882 ret
= i915_gem_object_set_to_cpu_domain(obj
, true);
1884 /* In the event of a disaster, abandon all caches and
1885 * hope for the best.
1887 WARN_ON(ret
!= -EIO
);
1888 i915_gem_clflush_object(obj
, true);
1889 obj
->base
.read_domains
= obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
1892 if (i915_gem_object_needs_bit17_swizzle(obj
))
1893 i915_gem_object_save_bit_17_swizzle(obj
);
1895 if (obj
->madv
== I915_MADV_DONTNEED
)
1898 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, 0) {
1899 struct page
*page
= sg_page_iter_page(&sg_iter
);
1902 set_page_dirty(page
);
1904 if (obj
->madv
== I915_MADV_WILLNEED
)
1905 mark_page_accessed(page
);
1907 page_cache_release(page
);
1911 sg_free_table(obj
->pages
);
1916 i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
)
1918 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
1920 if (obj
->pages
== NULL
)
1923 if (obj
->pages_pin_count
)
1926 BUG_ON(i915_gem_obj_bound_any(obj
));
1928 /* ->put_pages might need to allocate memory for the bit17 swizzle
1929 * array, hence protect them from being reaped by removing them from gtt
1931 list_del(&obj
->global_list
);
1933 ops
->put_pages(obj
);
1936 i915_gem_object_invalidate(obj
);
1941 static unsigned long
1942 __i915_gem_shrink(struct drm_i915_private
*dev_priv
, long target
,
1943 bool purgeable_only
)
1945 struct list_head still_in_list
;
1946 struct drm_i915_gem_object
*obj
;
1947 unsigned long count
= 0;
1950 * As we may completely rewrite the (un)bound list whilst unbinding
1951 * (due to retiring requests) we have to strictly process only
1952 * one element of the list at the time, and recheck the list
1953 * on every iteration.
1955 * In particular, we must hold a reference whilst removing the
1956 * object as we may end up waiting for and/or retiring the objects.
1957 * This might release the final reference (held by the active list)
1958 * and result in the object being freed from under us. This is
1959 * similar to the precautions the eviction code must take whilst
1962 * Also note that although these lists do not hold a reference to
1963 * the object we can safely grab one here: The final object
1964 * unreferencing and the bound_list are both protected by the
1965 * dev->struct_mutex and so we won't ever be able to observe an
1966 * object on the bound_list with a reference count equals 0.
1968 INIT_LIST_HEAD(&still_in_list
);
1969 while (count
< target
&& !list_empty(&dev_priv
->mm
.unbound_list
)) {
1970 obj
= list_first_entry(&dev_priv
->mm
.unbound_list
,
1971 typeof(*obj
), global_list
);
1972 list_move_tail(&obj
->global_list
, &still_in_list
);
1974 if (!i915_gem_object_is_purgeable(obj
) && purgeable_only
)
1977 drm_gem_object_reference(&obj
->base
);
1979 if (i915_gem_object_put_pages(obj
) == 0)
1980 count
+= obj
->base
.size
>> PAGE_SHIFT
;
1982 drm_gem_object_unreference(&obj
->base
);
1984 list_splice(&still_in_list
, &dev_priv
->mm
.unbound_list
);
1986 INIT_LIST_HEAD(&still_in_list
);
1987 while (count
< target
&& !list_empty(&dev_priv
->mm
.bound_list
)) {
1988 struct i915_vma
*vma
, *v
;
1990 obj
= list_first_entry(&dev_priv
->mm
.bound_list
,
1991 typeof(*obj
), global_list
);
1992 list_move_tail(&obj
->global_list
, &still_in_list
);
1994 if (!i915_gem_object_is_purgeable(obj
) && purgeable_only
)
1997 drm_gem_object_reference(&obj
->base
);
1999 list_for_each_entry_safe(vma
, v
, &obj
->vma_list
, vma_link
)
2000 if (i915_vma_unbind(vma
))
2003 if (i915_gem_object_put_pages(obj
) == 0)
2004 count
+= obj
->base
.size
>> PAGE_SHIFT
;
2006 drm_gem_object_unreference(&obj
->base
);
2008 list_splice(&still_in_list
, &dev_priv
->mm
.bound_list
);
2013 static unsigned long
2014 i915_gem_purge(struct drm_i915_private
*dev_priv
, long target
)
2016 return __i915_gem_shrink(dev_priv
, target
, true);
2019 static unsigned long
2020 i915_gem_shrink_all(struct drm_i915_private
*dev_priv
)
2022 i915_gem_evict_everything(dev_priv
->dev
);
2023 return __i915_gem_shrink(dev_priv
, LONG_MAX
, false);
2027 i915_gem_object_get_pages_gtt(struct drm_i915_gem_object
*obj
)
2029 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2031 struct address_space
*mapping
;
2032 struct sg_table
*st
;
2033 struct scatterlist
*sg
;
2034 struct sg_page_iter sg_iter
;
2036 unsigned long last_pfn
= 0; /* suppress gcc warning */
2039 /* Assert that the object is not currently in any GPU domain. As it
2040 * wasn't in the GTT, there shouldn't be any way it could have been in
2043 BUG_ON(obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
);
2044 BUG_ON(obj
->base
.write_domain
& I915_GEM_GPU_DOMAINS
);
2046 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
2050 page_count
= obj
->base
.size
/ PAGE_SIZE
;
2051 if (sg_alloc_table(st
, page_count
, GFP_KERNEL
)) {
2056 /* Get the list of pages out of our struct file. They'll be pinned
2057 * at this point until we release them.
2059 * Fail silently without starting the shrinker
2061 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
2062 gfp
= mapping_gfp_mask(mapping
);
2063 gfp
|= __GFP_NORETRY
| __GFP_NOWARN
| __GFP_NO_KSWAPD
;
2064 gfp
&= ~(__GFP_IO
| __GFP_WAIT
);
2067 for (i
= 0; i
< page_count
; i
++) {
2068 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2070 i915_gem_purge(dev_priv
, page_count
);
2071 page
= shmem_read_mapping_page_gfp(mapping
, i
, gfp
);
2074 /* We've tried hard to allocate the memory by reaping
2075 * our own buffer, now let the real VM do its job and
2076 * go down in flames if truly OOM.
2078 i915_gem_shrink_all(dev_priv
);
2079 page
= shmem_read_mapping_page(mapping
, i
);
2083 #ifdef CONFIG_SWIOTLB
2084 if (swiotlb_nr_tbl()) {
2086 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2091 if (!i
|| page_to_pfn(page
) != last_pfn
+ 1) {
2095 sg_set_page(sg
, page
, PAGE_SIZE
, 0);
2097 sg
->length
+= PAGE_SIZE
;
2099 last_pfn
= page_to_pfn(page
);
2101 /* Check that the i965g/gm workaround works. */
2102 WARN_ON((gfp
& __GFP_DMA32
) && (last_pfn
>= 0x00100000UL
));
2104 #ifdef CONFIG_SWIOTLB
2105 if (!swiotlb_nr_tbl())
2110 if (i915_gem_object_needs_bit17_swizzle(obj
))
2111 i915_gem_object_do_bit_17_swizzle(obj
);
2117 for_each_sg_page(st
->sgl
, &sg_iter
, st
->nents
, 0)
2118 page_cache_release(sg_page_iter_page(&sg_iter
));
2122 /* shmemfs first checks if there is enough memory to allocate the page
2123 * and reports ENOSPC should there be insufficient, along with the usual
2124 * ENOMEM for a genuine allocation failure.
2126 * We use ENOSPC in our driver to mean that we have run out of aperture
2127 * space and so want to translate the error from shmemfs back to our
2128 * usual understanding of ENOMEM.
2130 if (PTR_ERR(page
) == -ENOSPC
)
2133 return PTR_ERR(page
);
2136 /* Ensure that the associated pages are gathered from the backing storage
2137 * and pinned into our object. i915_gem_object_get_pages() may be called
2138 * multiple times before they are released by a single call to
2139 * i915_gem_object_put_pages() - once the pages are no longer referenced
2140 * either as a result of memory pressure (reaping pages under the shrinker)
2141 * or as the object is itself released.
2144 i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
)
2146 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2147 const struct drm_i915_gem_object_ops
*ops
= obj
->ops
;
2153 if (obj
->madv
!= I915_MADV_WILLNEED
) {
2154 DRM_DEBUG("Attempting to obtain a purgeable object\n");
2158 BUG_ON(obj
->pages_pin_count
);
2160 ret
= ops
->get_pages(obj
);
2164 list_add_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2169 i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
2170 struct intel_engine_cs
*ring
)
2172 struct drm_device
*dev
= obj
->base
.dev
;
2173 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2174 u32 seqno
= intel_ring_get_seqno(ring
);
2176 BUG_ON(ring
== NULL
);
2177 if (obj
->ring
!= ring
&& obj
->last_write_seqno
) {
2178 /* Keep the seqno relative to the current ring */
2179 obj
->last_write_seqno
= seqno
;
2183 /* Add a reference if we're newly entering the active list. */
2185 drm_gem_object_reference(&obj
->base
);
2189 list_move_tail(&obj
->ring_list
, &ring
->active_list
);
2191 obj
->last_read_seqno
= seqno
;
2193 if (obj
->fenced_gpu_access
) {
2194 obj
->last_fenced_seqno
= seqno
;
2196 /* Bump MRU to take account of the delayed flush */
2197 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2198 struct drm_i915_fence_reg
*reg
;
2200 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
2201 list_move_tail(®
->lru_list
,
2202 &dev_priv
->mm
.fence_list
);
2207 void i915_vma_move_to_active(struct i915_vma
*vma
,
2208 struct intel_engine_cs
*ring
)
2210 list_move_tail(&vma
->mm_list
, &vma
->vm
->active_list
);
2211 return i915_gem_object_move_to_active(vma
->obj
, ring
);
2215 i915_gem_object_move_to_inactive(struct drm_i915_gem_object
*obj
)
2217 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2218 struct i915_address_space
*vm
;
2219 struct i915_vma
*vma
;
2221 BUG_ON(obj
->base
.write_domain
& ~I915_GEM_GPU_DOMAINS
);
2222 BUG_ON(!obj
->active
);
2224 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
2225 vma
= i915_gem_obj_to_vma(obj
, vm
);
2226 if (vma
&& !list_empty(&vma
->mm_list
))
2227 list_move_tail(&vma
->mm_list
, &vm
->inactive_list
);
2230 list_del_init(&obj
->ring_list
);
2233 obj
->last_read_seqno
= 0;
2234 obj
->last_write_seqno
= 0;
2235 obj
->base
.write_domain
= 0;
2237 obj
->last_fenced_seqno
= 0;
2238 obj
->fenced_gpu_access
= false;
2241 drm_gem_object_unreference(&obj
->base
);
2243 WARN_ON(i915_verify_lists(dev
));
2247 i915_gem_object_retire(struct drm_i915_gem_object
*obj
)
2249 struct intel_engine_cs
*ring
= obj
->ring
;
2254 if (i915_seqno_passed(ring
->get_seqno(ring
, true),
2255 obj
->last_read_seqno
))
2256 i915_gem_object_move_to_inactive(obj
);
2260 i915_gem_init_seqno(struct drm_device
*dev
, u32 seqno
)
2262 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2263 struct intel_engine_cs
*ring
;
2266 /* Carefully retire all requests without writing to the rings */
2267 for_each_ring(ring
, dev_priv
, i
) {
2268 ret
= intel_ring_idle(ring
);
2272 i915_gem_retire_requests(dev
);
2274 /* Finally reset hw state */
2275 for_each_ring(ring
, dev_priv
, i
) {
2276 intel_ring_init_seqno(ring
, seqno
);
2278 for (j
= 0; j
< ARRAY_SIZE(ring
->semaphore
.sync_seqno
); j
++)
2279 ring
->semaphore
.sync_seqno
[j
] = 0;
2285 int i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
)
2287 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2293 /* HWS page needs to be set less than what we
2294 * will inject to ring
2296 ret
= i915_gem_init_seqno(dev
, seqno
- 1);
2300 /* Carefully set the last_seqno value so that wrap
2301 * detection still works
2303 dev_priv
->next_seqno
= seqno
;
2304 dev_priv
->last_seqno
= seqno
- 1;
2305 if (dev_priv
->last_seqno
== 0)
2306 dev_priv
->last_seqno
--;
2312 i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
)
2314 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2316 /* reserve 0 for non-seqno */
2317 if (dev_priv
->next_seqno
== 0) {
2318 int ret
= i915_gem_init_seqno(dev
, 0);
2322 dev_priv
->next_seqno
= 1;
2325 *seqno
= dev_priv
->last_seqno
= dev_priv
->next_seqno
++;
2329 int __i915_add_request(struct intel_engine_cs
*ring
,
2330 struct drm_file
*file
,
2331 struct drm_i915_gem_object
*obj
,
2334 struct drm_i915_private
*dev_priv
= ring
->dev
->dev_private
;
2335 struct drm_i915_gem_request
*request
;
2336 u32 request_ring_position
, request_start
;
2339 request_start
= intel_ring_get_tail(ring
);
2341 * Emit any outstanding flushes - execbuf can fail to emit the flush
2342 * after having emitted the batchbuffer command. Hence we need to fix
2343 * things up similar to emitting the lazy request. The difference here
2344 * is that the flush _must_ happen before the next request, no matter
2347 ret
= intel_ring_flush_all_caches(ring
);
2351 request
= ring
->preallocated_lazy_request
;
2352 if (WARN_ON(request
== NULL
))
2355 /* Record the position of the start of the request so that
2356 * should we detect the updated seqno part-way through the
2357 * GPU processing the request, we never over-estimate the
2358 * position of the head.
2360 request_ring_position
= intel_ring_get_tail(ring
);
2362 ret
= ring
->add_request(ring
);
2366 request
->seqno
= intel_ring_get_seqno(ring
);
2367 request
->ring
= ring
;
2368 request
->head
= request_start
;
2369 request
->tail
= request_ring_position
;
2371 /* Whilst this request exists, batch_obj will be on the
2372 * active_list, and so will hold the active reference. Only when this
2373 * request is retired will the the batch_obj be moved onto the
2374 * inactive_list and lose its active reference. Hence we do not need
2375 * to explicitly hold another reference here.
2377 request
->batch_obj
= obj
;
2379 /* Hold a reference to the current context so that we can inspect
2380 * it later in case a hangcheck error event fires.
2382 request
->ctx
= ring
->last_context
;
2384 i915_gem_context_reference(request
->ctx
);
2386 request
->emitted_jiffies
= jiffies
;
2387 list_add_tail(&request
->list
, &ring
->request_list
);
2388 request
->file_priv
= NULL
;
2391 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
2393 spin_lock(&file_priv
->mm
.lock
);
2394 request
->file_priv
= file_priv
;
2395 list_add_tail(&request
->client_list
,
2396 &file_priv
->mm
.request_list
);
2397 spin_unlock(&file_priv
->mm
.lock
);
2400 trace_i915_gem_request_add(ring
, request
->seqno
);
2401 ring
->outstanding_lazy_seqno
= 0;
2402 ring
->preallocated_lazy_request
= NULL
;
2404 if (!dev_priv
->ums
.mm_suspended
) {
2405 i915_queue_hangcheck(ring
->dev
);
2407 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
2408 queue_delayed_work(dev_priv
->wq
,
2409 &dev_priv
->mm
.retire_work
,
2410 round_jiffies_up_relative(HZ
));
2411 intel_mark_busy(dev_priv
->dev
);
2415 *out_seqno
= request
->seqno
;
2420 i915_gem_request_remove_from_client(struct drm_i915_gem_request
*request
)
2422 struct drm_i915_file_private
*file_priv
= request
->file_priv
;
2427 spin_lock(&file_priv
->mm
.lock
);
2428 list_del(&request
->client_list
);
2429 request
->file_priv
= NULL
;
2430 spin_unlock(&file_priv
->mm
.lock
);
2433 static bool i915_context_is_banned(struct drm_i915_private
*dev_priv
,
2434 const struct intel_context
*ctx
)
2436 unsigned long elapsed
;
2438 elapsed
= get_seconds() - ctx
->hang_stats
.guilty_ts
;
2440 if (ctx
->hang_stats
.banned
)
2443 if (elapsed
<= DRM_I915_CTX_BAN_PERIOD
) {
2444 if (!i915_gem_context_is_default(ctx
)) {
2445 DRM_DEBUG("context hanging too fast, banning!\n");
2447 } else if (i915_stop_ring_allow_ban(dev_priv
)) {
2448 if (i915_stop_ring_allow_warn(dev_priv
))
2449 DRM_ERROR("gpu hanging too fast, banning!\n");
2457 static void i915_set_reset_status(struct drm_i915_private
*dev_priv
,
2458 struct intel_context
*ctx
,
2461 struct i915_ctx_hang_stats
*hs
;
2466 hs
= &ctx
->hang_stats
;
2469 hs
->banned
= i915_context_is_banned(dev_priv
, ctx
);
2471 hs
->guilty_ts
= get_seconds();
2473 hs
->batch_pending
++;
2477 static void i915_gem_free_request(struct drm_i915_gem_request
*request
)
2479 list_del(&request
->list
);
2480 i915_gem_request_remove_from_client(request
);
2483 i915_gem_context_unreference(request
->ctx
);
2488 struct drm_i915_gem_request
*
2489 i915_gem_find_active_request(struct intel_engine_cs
*ring
)
2491 struct drm_i915_gem_request
*request
;
2492 u32 completed_seqno
;
2494 completed_seqno
= ring
->get_seqno(ring
, false);
2496 list_for_each_entry(request
, &ring
->request_list
, list
) {
2497 if (i915_seqno_passed(completed_seqno
, request
->seqno
))
2506 static void i915_gem_reset_ring_status(struct drm_i915_private
*dev_priv
,
2507 struct intel_engine_cs
*ring
)
2509 struct drm_i915_gem_request
*request
;
2512 request
= i915_gem_find_active_request(ring
);
2514 if (request
== NULL
)
2517 ring_hung
= ring
->hangcheck
.score
>= HANGCHECK_SCORE_RING_HUNG
;
2519 i915_set_reset_status(dev_priv
, request
->ctx
, ring_hung
);
2521 list_for_each_entry_continue(request
, &ring
->request_list
, list
)
2522 i915_set_reset_status(dev_priv
, request
->ctx
, false);
2525 static void i915_gem_reset_ring_cleanup(struct drm_i915_private
*dev_priv
,
2526 struct intel_engine_cs
*ring
)
2528 while (!list_empty(&ring
->active_list
)) {
2529 struct drm_i915_gem_object
*obj
;
2531 obj
= list_first_entry(&ring
->active_list
,
2532 struct drm_i915_gem_object
,
2535 i915_gem_object_move_to_inactive(obj
);
2539 * We must free the requests after all the corresponding objects have
2540 * been moved off active lists. Which is the same order as the normal
2541 * retire_requests function does. This is important if object hold
2542 * implicit references on things like e.g. ppgtt address spaces through
2545 while (!list_empty(&ring
->request_list
)) {
2546 struct drm_i915_gem_request
*request
;
2548 request
= list_first_entry(&ring
->request_list
,
2549 struct drm_i915_gem_request
,
2552 i915_gem_free_request(request
);
2555 /* These may not have been flush before the reset, do so now */
2556 kfree(ring
->preallocated_lazy_request
);
2557 ring
->preallocated_lazy_request
= NULL
;
2558 ring
->outstanding_lazy_seqno
= 0;
2561 void i915_gem_restore_fences(struct drm_device
*dev
)
2563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2566 for (i
= 0; i
< dev_priv
->num_fence_regs
; i
++) {
2567 struct drm_i915_fence_reg
*reg
= &dev_priv
->fence_regs
[i
];
2570 * Commit delayed tiling changes if we have an object still
2571 * attached to the fence, otherwise just clear the fence.
2574 i915_gem_object_update_fence(reg
->obj
, reg
,
2575 reg
->obj
->tiling_mode
);
2577 i915_gem_write_fence(dev
, i
, NULL
);
2582 void i915_gem_reset(struct drm_device
*dev
)
2584 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2585 struct intel_engine_cs
*ring
;
2589 * Before we free the objects from the requests, we need to inspect
2590 * them for finding the guilty party. As the requests only borrow
2591 * their reference to the objects, the inspection must be done first.
2593 for_each_ring(ring
, dev_priv
, i
)
2594 i915_gem_reset_ring_status(dev_priv
, ring
);
2596 for_each_ring(ring
, dev_priv
, i
)
2597 i915_gem_reset_ring_cleanup(dev_priv
, ring
);
2599 i915_gem_context_reset(dev
);
2601 i915_gem_restore_fences(dev
);
2605 * This function clears the request list as sequence numbers are passed.
2608 i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
)
2612 if (list_empty(&ring
->request_list
))
2615 WARN_ON(i915_verify_lists(ring
->dev
));
2617 seqno
= ring
->get_seqno(ring
, true);
2619 /* Move any buffers on the active list that are no longer referenced
2620 * by the ringbuffer to the flushing/inactive lists as appropriate,
2621 * before we free the context associated with the requests.
2623 while (!list_empty(&ring
->active_list
)) {
2624 struct drm_i915_gem_object
*obj
;
2626 obj
= list_first_entry(&ring
->active_list
,
2627 struct drm_i915_gem_object
,
2630 if (!i915_seqno_passed(seqno
, obj
->last_read_seqno
))
2633 i915_gem_object_move_to_inactive(obj
);
2637 while (!list_empty(&ring
->request_list
)) {
2638 struct drm_i915_gem_request
*request
;
2640 request
= list_first_entry(&ring
->request_list
,
2641 struct drm_i915_gem_request
,
2644 if (!i915_seqno_passed(seqno
, request
->seqno
))
2647 trace_i915_gem_request_retire(ring
, request
->seqno
);
2648 /* We know the GPU must have read the request to have
2649 * sent us the seqno + interrupt, so use the position
2650 * of tail of the request to update the last known position
2653 ring
->buffer
->last_retired_head
= request
->tail
;
2655 i915_gem_free_request(request
);
2658 if (unlikely(ring
->trace_irq_seqno
&&
2659 i915_seqno_passed(seqno
, ring
->trace_irq_seqno
))) {
2660 ring
->irq_put(ring
);
2661 ring
->trace_irq_seqno
= 0;
2664 WARN_ON(i915_verify_lists(ring
->dev
));
2668 i915_gem_retire_requests(struct drm_device
*dev
)
2670 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2671 struct intel_engine_cs
*ring
;
2675 for_each_ring(ring
, dev_priv
, i
) {
2676 i915_gem_retire_requests_ring(ring
);
2677 idle
&= list_empty(&ring
->request_list
);
2681 mod_delayed_work(dev_priv
->wq
,
2682 &dev_priv
->mm
.idle_work
,
2683 msecs_to_jiffies(100));
2689 i915_gem_retire_work_handler(struct work_struct
*work
)
2691 struct drm_i915_private
*dev_priv
=
2692 container_of(work
, typeof(*dev_priv
), mm
.retire_work
.work
);
2693 struct drm_device
*dev
= dev_priv
->dev
;
2696 /* Come back later if the device is busy... */
2698 if (mutex_trylock(&dev
->struct_mutex
)) {
2699 idle
= i915_gem_retire_requests(dev
);
2700 mutex_unlock(&dev
->struct_mutex
);
2703 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
,
2704 round_jiffies_up_relative(HZ
));
2708 i915_gem_idle_work_handler(struct work_struct
*work
)
2710 struct drm_i915_private
*dev_priv
=
2711 container_of(work
, typeof(*dev_priv
), mm
.idle_work
.work
);
2713 intel_mark_idle(dev_priv
->dev
);
2717 * Ensures that an object will eventually get non-busy by flushing any required
2718 * write domains, emitting any outstanding lazy request and retiring and
2719 * completed requests.
2722 i915_gem_object_flush_active(struct drm_i915_gem_object
*obj
)
2727 ret
= i915_gem_check_olr(obj
->ring
, obj
->last_read_seqno
);
2731 i915_gem_retire_requests_ring(obj
->ring
);
2738 * i915_gem_wait_ioctl - implements DRM_IOCTL_I915_GEM_WAIT
2739 * @DRM_IOCTL_ARGS: standard ioctl arguments
2741 * Returns 0 if successful, else an error is returned with the remaining time in
2742 * the timeout parameter.
2743 * -ETIME: object is still busy after timeout
2744 * -ERESTARTSYS: signal interrupted the wait
2745 * -ENONENT: object doesn't exist
2746 * Also possible, but rare:
2747 * -EAGAIN: GPU wedged
2749 * -ENODEV: Internal IRQ fail
2750 * -E?: The add request failed
2752 * The wait ioctl with a timeout of 0 reimplements the busy ioctl. With any
2753 * non-zero timeout parameter the wait ioctl will wait for the given number of
2754 * nanoseconds on an object becoming unbusy. Since the wait itself does so
2755 * without holding struct_mutex the object may become re-busied before this
2756 * function completes. A similar but shorter * race condition exists in the busy
2760 i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*file
)
2762 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2763 struct drm_i915_gem_wait
*args
= data
;
2764 struct drm_i915_gem_object
*obj
;
2765 struct intel_engine_cs
*ring
= NULL
;
2766 struct timespec timeout_stack
, *timeout
= NULL
;
2767 unsigned reset_counter
;
2771 if (args
->timeout_ns
>= 0) {
2772 timeout_stack
= ns_to_timespec(args
->timeout_ns
);
2773 timeout
= &timeout_stack
;
2776 ret
= i915_mutex_lock_interruptible(dev
);
2780 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->bo_handle
));
2781 if (&obj
->base
== NULL
) {
2782 mutex_unlock(&dev
->struct_mutex
);
2786 /* Need to make sure the object gets inactive eventually. */
2787 ret
= i915_gem_object_flush_active(obj
);
2792 seqno
= obj
->last_read_seqno
;
2799 /* Do this after OLR check to make sure we make forward progress polling
2800 * on this IOCTL with a 0 timeout (like busy ioctl)
2802 if (!args
->timeout_ns
) {
2807 drm_gem_object_unreference(&obj
->base
);
2808 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
2809 mutex_unlock(&dev
->struct_mutex
);
2811 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, timeout
, file
->driver_priv
);
2813 args
->timeout_ns
= timespec_to_ns(timeout
);
2817 drm_gem_object_unreference(&obj
->base
);
2818 mutex_unlock(&dev
->struct_mutex
);
2823 * i915_gem_object_sync - sync an object to a ring.
2825 * @obj: object which may be in use on another ring.
2826 * @to: ring we wish to use the object on. May be NULL.
2828 * This code is meant to abstract object synchronization with the GPU.
2829 * Calling with NULL implies synchronizing the object with the CPU
2830 * rather than a particular GPU ring.
2832 * Returns 0 if successful, else propagates up the lower layer error.
2835 i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2836 struct intel_engine_cs
*to
)
2838 struct intel_engine_cs
*from
= obj
->ring
;
2842 if (from
== NULL
|| to
== from
)
2845 if (to
== NULL
|| !i915_semaphore_is_enabled(obj
->base
.dev
))
2846 return i915_gem_object_wait_rendering(obj
, false);
2848 idx
= intel_ring_sync_index(from
, to
);
2850 seqno
= obj
->last_read_seqno
;
2851 if (seqno
<= from
->semaphore
.sync_seqno
[idx
])
2854 ret
= i915_gem_check_olr(obj
->ring
, seqno
);
2858 trace_i915_gem_ring_sync_to(from
, to
, seqno
);
2859 ret
= to
->semaphore
.sync_to(to
, from
, seqno
);
2861 /* We use last_read_seqno because sync_to()
2862 * might have just caused seqno wrap under
2865 from
->semaphore
.sync_seqno
[idx
] = obj
->last_read_seqno
;
2870 static void i915_gem_object_finish_gtt(struct drm_i915_gem_object
*obj
)
2872 u32 old_write_domain
, old_read_domains
;
2874 /* Force a pagefault for domain tracking on next user access */
2875 i915_gem_release_mmap(obj
);
2877 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
2880 /* Wait for any direct GTT access to complete */
2883 old_read_domains
= obj
->base
.read_domains
;
2884 old_write_domain
= obj
->base
.write_domain
;
2886 obj
->base
.read_domains
&= ~I915_GEM_DOMAIN_GTT
;
2887 obj
->base
.write_domain
&= ~I915_GEM_DOMAIN_GTT
;
2889 trace_i915_gem_object_change_domain(obj
,
2894 int i915_vma_unbind(struct i915_vma
*vma
)
2896 struct drm_i915_gem_object
*obj
= vma
->obj
;
2897 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2900 if (list_empty(&vma
->vma_link
))
2903 if (!drm_mm_node_allocated(&vma
->node
)) {
2904 i915_gem_vma_destroy(vma
);
2911 BUG_ON(obj
->pages
== NULL
);
2913 ret
= i915_gem_object_finish_gpu(obj
);
2916 /* Continue on if we fail due to EIO, the GPU is hung so we
2917 * should be safe and we need to cleanup or else we might
2918 * cause memory corruption through use-after-free.
2921 if (i915_is_ggtt(vma
->vm
)) {
2922 i915_gem_object_finish_gtt(obj
);
2924 /* release the fence reg _after_ flushing */
2925 ret
= i915_gem_object_put_fence(obj
);
2930 trace_i915_vma_unbind(vma
);
2932 vma
->unbind_vma(vma
);
2934 i915_gem_gtt_finish_object(obj
);
2936 list_del_init(&vma
->mm_list
);
2937 /* Avoid an unnecessary call to unbind on rebind. */
2938 if (i915_is_ggtt(vma
->vm
))
2939 obj
->map_and_fenceable
= true;
2941 drm_mm_remove_node(&vma
->node
);
2942 i915_gem_vma_destroy(vma
);
2944 /* Since the unbound list is global, only move to that list if
2945 * no more VMAs exist. */
2946 if (list_empty(&obj
->vma_list
))
2947 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.unbound_list
);
2949 /* And finally now the object is completely decoupled from this vma,
2950 * we can drop its hold on the backing storage and allow it to be
2951 * reaped by the shrinker.
2953 i915_gem_object_unpin_pages(obj
);
2958 int i915_gpu_idle(struct drm_device
*dev
)
2960 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2961 struct intel_engine_cs
*ring
;
2964 /* Flush everything onto the inactive list. */
2965 for_each_ring(ring
, dev_priv
, i
) {
2966 ret
= i915_switch_context(ring
, ring
->default_context
);
2970 ret
= intel_ring_idle(ring
);
2978 static void i965_write_fence_reg(struct drm_device
*dev
, int reg
,
2979 struct drm_i915_gem_object
*obj
)
2981 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2983 int fence_pitch_shift
;
2985 if (INTEL_INFO(dev
)->gen
>= 6) {
2986 fence_reg
= FENCE_REG_SANDYBRIDGE_0
;
2987 fence_pitch_shift
= SANDYBRIDGE_FENCE_PITCH_SHIFT
;
2989 fence_reg
= FENCE_REG_965_0
;
2990 fence_pitch_shift
= I965_FENCE_PITCH_SHIFT
;
2993 fence_reg
+= reg
* 8;
2995 /* To w/a incoherency with non-atomic 64-bit register updates,
2996 * we split the 64-bit update into two 32-bit writes. In order
2997 * for a partial fence not to be evaluated between writes, we
2998 * precede the update with write to turn off the fence register,
2999 * and only enable the fence as the last step.
3001 * For extra levels of paranoia, we make sure each step lands
3002 * before applying the next step.
3004 I915_WRITE(fence_reg
, 0);
3005 POSTING_READ(fence_reg
);
3008 u32 size
= i915_gem_obj_ggtt_size(obj
);
3011 val
= (uint64_t)((i915_gem_obj_ggtt_offset(obj
) + size
- 4096) &
3013 val
|= i915_gem_obj_ggtt_offset(obj
) & 0xfffff000;
3014 val
|= (uint64_t)((obj
->stride
/ 128) - 1) << fence_pitch_shift
;
3015 if (obj
->tiling_mode
== I915_TILING_Y
)
3016 val
|= 1 << I965_FENCE_TILING_Y_SHIFT
;
3017 val
|= I965_FENCE_REG_VALID
;
3019 I915_WRITE(fence_reg
+ 4, val
>> 32);
3020 POSTING_READ(fence_reg
+ 4);
3022 I915_WRITE(fence_reg
+ 0, val
);
3023 POSTING_READ(fence_reg
);
3025 I915_WRITE(fence_reg
+ 4, 0);
3026 POSTING_READ(fence_reg
+ 4);
3030 static void i915_write_fence_reg(struct drm_device
*dev
, int reg
,
3031 struct drm_i915_gem_object
*obj
)
3033 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3037 u32 size
= i915_gem_obj_ggtt_size(obj
);
3041 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I915_FENCE_START_MASK
) ||
3042 (size
& -size
) != size
||
3043 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3044 "object 0x%08lx [fenceable? %d] not 1M or pot-size (0x%08x) aligned\n",
3045 i915_gem_obj_ggtt_offset(obj
), obj
->map_and_fenceable
, size
);
3047 if (obj
->tiling_mode
== I915_TILING_Y
&& HAS_128_BYTE_Y_TILING(dev
))
3052 /* Note: pitch better be a power of two tile widths */
3053 pitch_val
= obj
->stride
/ tile_width
;
3054 pitch_val
= ffs(pitch_val
) - 1;
3056 val
= i915_gem_obj_ggtt_offset(obj
);
3057 if (obj
->tiling_mode
== I915_TILING_Y
)
3058 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3059 val
|= I915_FENCE_SIZE_BITS(size
);
3060 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3061 val
|= I830_FENCE_REG_VALID
;
3066 reg
= FENCE_REG_830_0
+ reg
* 4;
3068 reg
= FENCE_REG_945_8
+ (reg
- 8) * 4;
3070 I915_WRITE(reg
, val
);
3074 static void i830_write_fence_reg(struct drm_device
*dev
, int reg
,
3075 struct drm_i915_gem_object
*obj
)
3077 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3081 u32 size
= i915_gem_obj_ggtt_size(obj
);
3084 WARN((i915_gem_obj_ggtt_offset(obj
) & ~I830_FENCE_START_MASK
) ||
3085 (size
& -size
) != size
||
3086 (i915_gem_obj_ggtt_offset(obj
) & (size
- 1)),
3087 "object 0x%08lx not 512K or pot-size 0x%08x aligned\n",
3088 i915_gem_obj_ggtt_offset(obj
), size
);
3090 pitch_val
= obj
->stride
/ 128;
3091 pitch_val
= ffs(pitch_val
) - 1;
3093 val
= i915_gem_obj_ggtt_offset(obj
);
3094 if (obj
->tiling_mode
== I915_TILING_Y
)
3095 val
|= 1 << I830_FENCE_TILING_Y_SHIFT
;
3096 val
|= I830_FENCE_SIZE_BITS(size
);
3097 val
|= pitch_val
<< I830_FENCE_PITCH_SHIFT
;
3098 val
|= I830_FENCE_REG_VALID
;
3102 I915_WRITE(FENCE_REG_830_0
+ reg
* 4, val
);
3103 POSTING_READ(FENCE_REG_830_0
+ reg
* 4);
3106 inline static bool i915_gem_object_needs_mb(struct drm_i915_gem_object
*obj
)
3108 return obj
&& obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
;
3111 static void i915_gem_write_fence(struct drm_device
*dev
, int reg
,
3112 struct drm_i915_gem_object
*obj
)
3114 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3116 /* Ensure that all CPU reads are completed before installing a fence
3117 * and all writes before removing the fence.
3119 if (i915_gem_object_needs_mb(dev_priv
->fence_regs
[reg
].obj
))
3122 WARN(obj
&& (!obj
->stride
|| !obj
->tiling_mode
),
3123 "bogus fence setup with stride: 0x%x, tiling mode: %i\n",
3124 obj
->stride
, obj
->tiling_mode
);
3126 switch (INTEL_INFO(dev
)->gen
) {
3131 case 4: i965_write_fence_reg(dev
, reg
, obj
); break;
3132 case 3: i915_write_fence_reg(dev
, reg
, obj
); break;
3133 case 2: i830_write_fence_reg(dev
, reg
, obj
); break;
3137 /* And similarly be paranoid that no direct access to this region
3138 * is reordered to before the fence is installed.
3140 if (i915_gem_object_needs_mb(obj
))
3144 static inline int fence_number(struct drm_i915_private
*dev_priv
,
3145 struct drm_i915_fence_reg
*fence
)
3147 return fence
- dev_priv
->fence_regs
;
3150 static void i915_gem_object_update_fence(struct drm_i915_gem_object
*obj
,
3151 struct drm_i915_fence_reg
*fence
,
3154 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3155 int reg
= fence_number(dev_priv
, fence
);
3157 i915_gem_write_fence(obj
->base
.dev
, reg
, enable
? obj
: NULL
);
3160 obj
->fence_reg
= reg
;
3162 list_move_tail(&fence
->lru_list
, &dev_priv
->mm
.fence_list
);
3164 obj
->fence_reg
= I915_FENCE_REG_NONE
;
3166 list_del_init(&fence
->lru_list
);
3168 obj
->fence_dirty
= false;
3172 i915_gem_object_wait_fence(struct drm_i915_gem_object
*obj
)
3174 if (obj
->last_fenced_seqno
) {
3175 int ret
= i915_wait_seqno(obj
->ring
, obj
->last_fenced_seqno
);
3179 obj
->last_fenced_seqno
= 0;
3182 obj
->fenced_gpu_access
= false;
3187 i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
)
3189 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3190 struct drm_i915_fence_reg
*fence
;
3193 ret
= i915_gem_object_wait_fence(obj
);
3197 if (obj
->fence_reg
== I915_FENCE_REG_NONE
)
3200 fence
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3202 if (WARN_ON(fence
->pin_count
))
3205 i915_gem_object_fence_lost(obj
);
3206 i915_gem_object_update_fence(obj
, fence
, false);
3211 static struct drm_i915_fence_reg
*
3212 i915_find_fence_reg(struct drm_device
*dev
)
3214 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3215 struct drm_i915_fence_reg
*reg
, *avail
;
3218 /* First try to find a free reg */
3220 for (i
= dev_priv
->fence_reg_start
; i
< dev_priv
->num_fence_regs
; i
++) {
3221 reg
= &dev_priv
->fence_regs
[i
];
3225 if (!reg
->pin_count
)
3232 /* None available, try to steal one or wait for a user to finish */
3233 list_for_each_entry(reg
, &dev_priv
->mm
.fence_list
, lru_list
) {
3241 /* Wait for completion of pending flips which consume fences */
3242 if (intel_has_pending_fb_unpin(dev
))
3243 return ERR_PTR(-EAGAIN
);
3245 return ERR_PTR(-EDEADLK
);
3249 * i915_gem_object_get_fence - set up fencing for an object
3250 * @obj: object to map through a fence reg
3252 * When mapping objects through the GTT, userspace wants to be able to write
3253 * to them without having to worry about swizzling if the object is tiled.
3254 * This function walks the fence regs looking for a free one for @obj,
3255 * stealing one if it can't find any.
3257 * It then sets up the reg based on the object's properties: address, pitch
3258 * and tiling format.
3260 * For an untiled surface, this removes any existing fence.
3263 i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
)
3265 struct drm_device
*dev
= obj
->base
.dev
;
3266 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3267 bool enable
= obj
->tiling_mode
!= I915_TILING_NONE
;
3268 struct drm_i915_fence_reg
*reg
;
3271 /* Have we updated the tiling parameters upon the object and so
3272 * will need to serialise the write to the associated fence register?
3274 if (obj
->fence_dirty
) {
3275 ret
= i915_gem_object_wait_fence(obj
);
3280 /* Just update our place in the LRU if our fence is getting reused. */
3281 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
3282 reg
= &dev_priv
->fence_regs
[obj
->fence_reg
];
3283 if (!obj
->fence_dirty
) {
3284 list_move_tail(®
->lru_list
,
3285 &dev_priv
->mm
.fence_list
);
3288 } else if (enable
) {
3289 reg
= i915_find_fence_reg(dev
);
3291 return PTR_ERR(reg
);
3294 struct drm_i915_gem_object
*old
= reg
->obj
;
3296 ret
= i915_gem_object_wait_fence(old
);
3300 i915_gem_object_fence_lost(old
);
3305 i915_gem_object_update_fence(obj
, reg
, enable
);
3310 static bool i915_gem_valid_gtt_space(struct drm_device
*dev
,
3311 struct drm_mm_node
*gtt_space
,
3312 unsigned long cache_level
)
3314 struct drm_mm_node
*other
;
3316 /* On non-LLC machines we have to be careful when putting differing
3317 * types of snoopable memory together to avoid the prefetcher
3318 * crossing memory domains and dying.
3323 if (!drm_mm_node_allocated(gtt_space
))
3326 if (list_empty(>t_space
->node_list
))
3329 other
= list_entry(gtt_space
->node_list
.prev
, struct drm_mm_node
, node_list
);
3330 if (other
->allocated
&& !other
->hole_follows
&& other
->color
!= cache_level
)
3333 other
= list_entry(gtt_space
->node_list
.next
, struct drm_mm_node
, node_list
);
3334 if (other
->allocated
&& !gtt_space
->hole_follows
&& other
->color
!= cache_level
)
3340 static void i915_gem_verify_gtt(struct drm_device
*dev
)
3343 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3344 struct drm_i915_gem_object
*obj
;
3347 list_for_each_entry(obj
, &dev_priv
->mm
.gtt_list
, global_list
) {
3348 if (obj
->gtt_space
== NULL
) {
3349 printk(KERN_ERR
"object found on GTT list with no space reserved\n");
3354 if (obj
->cache_level
!= obj
->gtt_space
->color
) {
3355 printk(KERN_ERR
"object reserved space [%08lx, %08lx] with wrong color, cache_level=%x, color=%lx\n",
3356 i915_gem_obj_ggtt_offset(obj
),
3357 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3359 obj
->gtt_space
->color
);
3364 if (!i915_gem_valid_gtt_space(dev
,
3366 obj
->cache_level
)) {
3367 printk(KERN_ERR
"invalid GTT space found at [%08lx, %08lx] - color=%x\n",
3368 i915_gem_obj_ggtt_offset(obj
),
3369 i915_gem_obj_ggtt_offset(obj
) + i915_gem_obj_ggtt_size(obj
),
3381 * Finds free space in the GTT aperture and binds the object there.
3383 static struct i915_vma
*
3384 i915_gem_object_bind_to_vm(struct drm_i915_gem_object
*obj
,
3385 struct i915_address_space
*vm
,
3389 struct drm_device
*dev
= obj
->base
.dev
;
3390 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3391 u32 size
, fence_size
, fence_alignment
, unfenced_alignment
;
3392 unsigned long start
=
3393 flags
& PIN_OFFSET_BIAS
? flags
& PIN_OFFSET_MASK
: 0;
3395 flags
& PIN_MAPPABLE
? dev_priv
->gtt
.mappable_end
: vm
->total
;
3396 struct i915_vma
*vma
;
3399 fence_size
= i915_gem_get_gtt_size(dev
,
3402 fence_alignment
= i915_gem_get_gtt_alignment(dev
,
3404 obj
->tiling_mode
, true);
3405 unfenced_alignment
=
3406 i915_gem_get_gtt_alignment(dev
,
3408 obj
->tiling_mode
, false);
3411 alignment
= flags
& PIN_MAPPABLE
? fence_alignment
:
3413 if (flags
& PIN_MAPPABLE
&& alignment
& (fence_alignment
- 1)) {
3414 DRM_DEBUG("Invalid object alignment requested %u\n", alignment
);
3415 return ERR_PTR(-EINVAL
);
3418 size
= flags
& PIN_MAPPABLE
? fence_size
: obj
->base
.size
;
3420 /* If the object is bigger than the entire aperture, reject it early
3421 * before evicting everything in a vain attempt to find space.
3423 if (obj
->base
.size
> end
) {
3424 DRM_DEBUG("Attempting to bind an object larger than the aperture: object=%zd > %s aperture=%lu\n",
3426 flags
& PIN_MAPPABLE
? "mappable" : "total",
3428 return ERR_PTR(-E2BIG
);
3431 ret
= i915_gem_object_get_pages(obj
);
3433 return ERR_PTR(ret
);
3435 i915_gem_object_pin_pages(obj
);
3437 vma
= i915_gem_obj_lookup_or_create_vma(obj
, vm
);
3442 ret
= drm_mm_insert_node_in_range_generic(&vm
->mm
, &vma
->node
,
3446 DRM_MM_SEARCH_DEFAULT
,
3447 DRM_MM_CREATE_DEFAULT
);
3449 ret
= i915_gem_evict_something(dev
, vm
, size
, alignment
,
3458 if (WARN_ON(!i915_gem_valid_gtt_space(dev
, &vma
->node
,
3459 obj
->cache_level
))) {
3461 goto err_remove_node
;
3464 ret
= i915_gem_gtt_prepare_object(obj
);
3466 goto err_remove_node
;
3468 list_move_tail(&obj
->global_list
, &dev_priv
->mm
.bound_list
);
3469 list_add_tail(&vma
->mm_list
, &vm
->inactive_list
);
3471 if (i915_is_ggtt(vm
)) {
3472 bool mappable
, fenceable
;
3474 fenceable
= (vma
->node
.size
== fence_size
&&
3475 (vma
->node
.start
& (fence_alignment
- 1)) == 0);
3477 mappable
= (vma
->node
.start
+ obj
->base
.size
<=
3478 dev_priv
->gtt
.mappable_end
);
3480 obj
->map_and_fenceable
= mappable
&& fenceable
;
3483 WARN_ON(flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
);
3485 trace_i915_vma_bind(vma
, flags
);
3486 vma
->bind_vma(vma
, obj
->cache_level
,
3487 flags
& (PIN_MAPPABLE
| PIN_GLOBAL
) ? GLOBAL_BIND
: 0);
3489 i915_gem_verify_gtt(dev
);
3493 drm_mm_remove_node(&vma
->node
);
3495 i915_gem_vma_destroy(vma
);
3498 i915_gem_object_unpin_pages(obj
);
3503 i915_gem_clflush_object(struct drm_i915_gem_object
*obj
,
3506 /* If we don't have a page list set up, then we're not pinned
3507 * to GPU, and we can ignore the cache flush because it'll happen
3508 * again at bind time.
3510 if (obj
->pages
== NULL
)
3514 * Stolen memory is always coherent with the GPU as it is explicitly
3515 * marked as wc by the system, or the system is cache-coherent.
3520 /* If the GPU is snooping the contents of the CPU cache,
3521 * we do not need to manually clear the CPU cache lines. However,
3522 * the caches are only snooped when the render cache is
3523 * flushed/invalidated. As we always have to emit invalidations
3524 * and flushes when moving into and out of the RENDER domain, correct
3525 * snooping behaviour occurs naturally as the result of our domain
3528 if (!force
&& cpu_cache_is_coherent(obj
->base
.dev
, obj
->cache_level
))
3531 trace_i915_gem_object_clflush(obj
);
3532 drm_clflush_sg(obj
->pages
);
3537 /** Flushes the GTT write domain for the object if it's dirty. */
3539 i915_gem_object_flush_gtt_write_domain(struct drm_i915_gem_object
*obj
)
3541 uint32_t old_write_domain
;
3543 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_GTT
)
3546 /* No actual flushing is required for the GTT write domain. Writes
3547 * to it immediately go to main memory as far as we know, so there's
3548 * no chipset flush. It also doesn't land in render cache.
3550 * However, we do have to enforce the order so that all writes through
3551 * the GTT land before any writes to the device, such as updates to
3556 old_write_domain
= obj
->base
.write_domain
;
3557 obj
->base
.write_domain
= 0;
3559 trace_i915_gem_object_change_domain(obj
,
3560 obj
->base
.read_domains
,
3564 /** Flushes the CPU write domain for the object if it's dirty. */
3566 i915_gem_object_flush_cpu_write_domain(struct drm_i915_gem_object
*obj
,
3569 uint32_t old_write_domain
;
3571 if (obj
->base
.write_domain
!= I915_GEM_DOMAIN_CPU
)
3574 if (i915_gem_clflush_object(obj
, force
))
3575 i915_gem_chipset_flush(obj
->base
.dev
);
3577 old_write_domain
= obj
->base
.write_domain
;
3578 obj
->base
.write_domain
= 0;
3580 trace_i915_gem_object_change_domain(obj
,
3581 obj
->base
.read_domains
,
3586 * Moves a single object to the GTT read, and possibly write domain.
3588 * This function returns when the move is complete, including waiting on
3592 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
, bool write
)
3594 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3595 uint32_t old_write_domain
, old_read_domains
;
3598 /* Not valid to be called on unbound objects. */
3599 if (!i915_gem_obj_bound_any(obj
))
3602 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_GTT
)
3605 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3609 i915_gem_object_retire(obj
);
3610 i915_gem_object_flush_cpu_write_domain(obj
, false);
3612 /* Serialise direct access to this object with the barriers for
3613 * coherent writes from the GPU, by effectively invalidating the
3614 * GTT domain upon first access.
3616 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_GTT
) == 0)
3619 old_write_domain
= obj
->base
.write_domain
;
3620 old_read_domains
= obj
->base
.read_domains
;
3622 /* It should now be out of any other write domains, and we can update
3623 * the domain values for our changes.
3625 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_GTT
) != 0);
3626 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3628 obj
->base
.read_domains
= I915_GEM_DOMAIN_GTT
;
3629 obj
->base
.write_domain
= I915_GEM_DOMAIN_GTT
;
3633 trace_i915_gem_object_change_domain(obj
,
3637 /* And bump the LRU for this access */
3638 if (i915_gem_object_is_inactive(obj
)) {
3639 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
3641 list_move_tail(&vma
->mm_list
,
3642 &dev_priv
->gtt
.base
.inactive_list
);
3649 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3650 enum i915_cache_level cache_level
)
3652 struct drm_device
*dev
= obj
->base
.dev
;
3653 struct i915_vma
*vma
, *next
;
3656 if (obj
->cache_level
== cache_level
)
3659 if (i915_gem_obj_is_pinned(obj
)) {
3660 DRM_DEBUG("can not change the cache level of pinned objects\n");
3664 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
3665 if (!i915_gem_valid_gtt_space(dev
, &vma
->node
, cache_level
)) {
3666 ret
= i915_vma_unbind(vma
);
3672 if (i915_gem_obj_bound_any(obj
)) {
3673 ret
= i915_gem_object_finish_gpu(obj
);
3677 i915_gem_object_finish_gtt(obj
);
3679 /* Before SandyBridge, you could not use tiling or fence
3680 * registers with snooped memory, so relinquish any fences
3681 * currently pointing to our region in the aperture.
3683 if (INTEL_INFO(dev
)->gen
< 6) {
3684 ret
= i915_gem_object_put_fence(obj
);
3689 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3690 if (drm_mm_node_allocated(&vma
->node
))
3691 vma
->bind_vma(vma
, cache_level
,
3692 obj
->has_global_gtt_mapping
? GLOBAL_BIND
: 0);
3695 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
3696 vma
->node
.color
= cache_level
;
3697 obj
->cache_level
= cache_level
;
3699 if (cpu_write_needs_clflush(obj
)) {
3700 u32 old_read_domains
, old_write_domain
;
3702 /* If we're coming from LLC cached, then we haven't
3703 * actually been tracking whether the data is in the
3704 * CPU cache or not, since we only allow one bit set
3705 * in obj->write_domain and have been skipping the clflushes.
3706 * Just set it to the CPU cache for now.
3708 i915_gem_object_retire(obj
);
3709 WARN_ON(obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
);
3711 old_read_domains
= obj
->base
.read_domains
;
3712 old_write_domain
= obj
->base
.write_domain
;
3714 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3715 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3717 trace_i915_gem_object_change_domain(obj
,
3722 i915_gem_verify_gtt(dev
);
3726 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3727 struct drm_file
*file
)
3729 struct drm_i915_gem_caching
*args
= data
;
3730 struct drm_i915_gem_object
*obj
;
3733 ret
= i915_mutex_lock_interruptible(dev
);
3737 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3738 if (&obj
->base
== NULL
) {
3743 switch (obj
->cache_level
) {
3744 case I915_CACHE_LLC
:
3745 case I915_CACHE_L3_LLC
:
3746 args
->caching
= I915_CACHING_CACHED
;
3750 args
->caching
= I915_CACHING_DISPLAY
;
3754 args
->caching
= I915_CACHING_NONE
;
3758 drm_gem_object_unreference(&obj
->base
);
3760 mutex_unlock(&dev
->struct_mutex
);
3764 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3765 struct drm_file
*file
)
3767 struct drm_i915_gem_caching
*args
= data
;
3768 struct drm_i915_gem_object
*obj
;
3769 enum i915_cache_level level
;
3772 switch (args
->caching
) {
3773 case I915_CACHING_NONE
:
3774 level
= I915_CACHE_NONE
;
3776 case I915_CACHING_CACHED
:
3777 level
= I915_CACHE_LLC
;
3779 case I915_CACHING_DISPLAY
:
3780 level
= HAS_WT(dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
;
3786 ret
= i915_mutex_lock_interruptible(dev
);
3790 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
3791 if (&obj
->base
== NULL
) {
3796 ret
= i915_gem_object_set_cache_level(obj
, level
);
3798 drm_gem_object_unreference(&obj
->base
);
3800 mutex_unlock(&dev
->struct_mutex
);
3804 static bool is_pin_display(struct drm_i915_gem_object
*obj
)
3806 struct i915_vma
*vma
;
3808 if (list_empty(&obj
->vma_list
))
3811 vma
= i915_gem_obj_to_ggtt(obj
);
3815 /* There are 3 sources that pin objects:
3816 * 1. The display engine (scanouts, sprites, cursors);
3817 * 2. Reservations for execbuffer;
3820 * We can ignore reservations as we hold the struct_mutex and
3821 * are only called outside of the reservation path. The user
3822 * can only increment pin_count once, and so if after
3823 * subtracting the potential reference by the user, any pin_count
3824 * remains, it must be due to another use by the display engine.
3826 return vma
->pin_count
- !!obj
->user_pin_count
;
3830 * Prepare buffer for display plane (scanout, cursors, etc).
3831 * Can be called from an uninterruptible phase (modesetting) and allows
3832 * any flushes to be pipelined (for pageflips).
3835 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3837 struct intel_engine_cs
*pipelined
)
3839 u32 old_read_domains
, old_write_domain
;
3840 bool was_pin_display
;
3843 if (pipelined
!= obj
->ring
) {
3844 ret
= i915_gem_object_sync(obj
, pipelined
);
3849 /* Mark the pin_display early so that we account for the
3850 * display coherency whilst setting up the cache domains.
3852 was_pin_display
= obj
->pin_display
;
3853 obj
->pin_display
= true;
3855 /* The display engine is not coherent with the LLC cache on gen6. As
3856 * a result, we make sure that the pinning that is about to occur is
3857 * done with uncached PTEs. This is lowest common denominator for all
3860 * However for gen6+, we could do better by using the GFDT bit instead
3861 * of uncaching, which would allow us to flush all the LLC-cached data
3862 * with that bit in the PTE to main memory with just one PIPE_CONTROL.
3864 ret
= i915_gem_object_set_cache_level(obj
,
3865 HAS_WT(obj
->base
.dev
) ? I915_CACHE_WT
: I915_CACHE_NONE
);
3867 goto err_unpin_display
;
3869 /* As the user may map the buffer once pinned in the display plane
3870 * (e.g. libkms for the bootup splash), we have to ensure that we
3871 * always use map_and_fenceable for all scanout buffers.
3873 ret
= i915_gem_obj_ggtt_pin(obj
, alignment
, PIN_MAPPABLE
);
3875 goto err_unpin_display
;
3877 i915_gem_object_flush_cpu_write_domain(obj
, true);
3879 old_write_domain
= obj
->base
.write_domain
;
3880 old_read_domains
= obj
->base
.read_domains
;
3882 /* It should now be out of any other write domains, and we can update
3883 * the domain values for our changes.
3885 obj
->base
.write_domain
= 0;
3886 obj
->base
.read_domains
|= I915_GEM_DOMAIN_GTT
;
3888 trace_i915_gem_object_change_domain(obj
,
3895 WARN_ON(was_pin_display
!= is_pin_display(obj
));
3896 obj
->pin_display
= was_pin_display
;
3901 i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
)
3903 i915_gem_object_ggtt_unpin(obj
);
3904 obj
->pin_display
= is_pin_display(obj
);
3908 i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
)
3912 if ((obj
->base
.read_domains
& I915_GEM_GPU_DOMAINS
) == 0)
3915 ret
= i915_gem_object_wait_rendering(obj
, false);
3919 /* Ensure that we invalidate the GPU's caches and TLBs. */
3920 obj
->base
.read_domains
&= ~I915_GEM_GPU_DOMAINS
;
3925 * Moves a single object to the CPU read, and possibly write domain.
3927 * This function returns when the move is complete, including waiting on
3931 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
)
3933 uint32_t old_write_domain
, old_read_domains
;
3936 if (obj
->base
.write_domain
== I915_GEM_DOMAIN_CPU
)
3939 ret
= i915_gem_object_wait_rendering(obj
, !write
);
3943 i915_gem_object_retire(obj
);
3944 i915_gem_object_flush_gtt_write_domain(obj
);
3946 old_write_domain
= obj
->base
.write_domain
;
3947 old_read_domains
= obj
->base
.read_domains
;
3949 /* Flush the CPU cache if it's still invalid. */
3950 if ((obj
->base
.read_domains
& I915_GEM_DOMAIN_CPU
) == 0) {
3951 i915_gem_clflush_object(obj
, false);
3953 obj
->base
.read_domains
|= I915_GEM_DOMAIN_CPU
;
3956 /* It should now be out of any other write domains, and we can update
3957 * the domain values for our changes.
3959 BUG_ON((obj
->base
.write_domain
& ~I915_GEM_DOMAIN_CPU
) != 0);
3961 /* If we're writing through the CPU, then the GPU read domains will
3962 * need to be invalidated at next use.
3965 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
3966 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
3969 trace_i915_gem_object_change_domain(obj
,
3976 /* Throttle our rendering by waiting until the ring has completed our requests
3977 * emitted over 20 msec ago.
3979 * Note that if we were to use the current jiffies each time around the loop,
3980 * we wouldn't escape the function with any frames outstanding if the time to
3981 * render a frame was over 20ms.
3983 * This should get us reasonable parallelism between CPU and GPU but also
3984 * relatively low latency when blocking on a particular request to finish.
3987 i915_gem_ring_throttle(struct drm_device
*dev
, struct drm_file
*file
)
3989 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3990 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
3991 unsigned long recent_enough
= jiffies
- msecs_to_jiffies(20);
3992 struct drm_i915_gem_request
*request
;
3993 struct intel_engine_cs
*ring
= NULL
;
3994 unsigned reset_counter
;
3998 ret
= i915_gem_wait_for_error(&dev_priv
->gpu_error
);
4002 ret
= i915_gem_check_wedge(&dev_priv
->gpu_error
, false);
4006 spin_lock(&file_priv
->mm
.lock
);
4007 list_for_each_entry(request
, &file_priv
->mm
.request_list
, client_list
) {
4008 if (time_after_eq(request
->emitted_jiffies
, recent_enough
))
4011 ring
= request
->ring
;
4012 seqno
= request
->seqno
;
4014 reset_counter
= atomic_read(&dev_priv
->gpu_error
.reset_counter
);
4015 spin_unlock(&file_priv
->mm
.lock
);
4020 ret
= __wait_seqno(ring
, seqno
, reset_counter
, true, NULL
, NULL
);
4022 queue_delayed_work(dev_priv
->wq
, &dev_priv
->mm
.retire_work
, 0);
4028 i915_vma_misplaced(struct i915_vma
*vma
, uint32_t alignment
, uint64_t flags
)
4030 struct drm_i915_gem_object
*obj
= vma
->obj
;
4033 vma
->node
.start
& (alignment
- 1))
4036 if (flags
& PIN_MAPPABLE
&& !obj
->map_and_fenceable
)
4039 if (flags
& PIN_OFFSET_BIAS
&&
4040 vma
->node
.start
< (flags
& PIN_OFFSET_MASK
))
4047 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
4048 struct i915_address_space
*vm
,
4052 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4053 struct i915_vma
*vma
;
4056 if (WARN_ON(vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
))
4059 if (WARN_ON(flags
& (PIN_GLOBAL
| PIN_MAPPABLE
) && !i915_is_ggtt(vm
)))
4062 vma
= i915_gem_obj_to_vma(obj
, vm
);
4064 if (WARN_ON(vma
->pin_count
== DRM_I915_GEM_OBJECT_MAX_PIN_COUNT
))
4067 if (i915_vma_misplaced(vma
, alignment
, flags
)) {
4068 WARN(vma
->pin_count
,
4069 "bo is already pinned with incorrect alignment:"
4070 " offset=%lx, req.alignment=%x, req.map_and_fenceable=%d,"
4071 " obj->map_and_fenceable=%d\n",
4072 i915_gem_obj_offset(obj
, vm
), alignment
,
4073 !!(flags
& PIN_MAPPABLE
),
4074 obj
->map_and_fenceable
);
4075 ret
= i915_vma_unbind(vma
);
4083 if (vma
== NULL
|| !drm_mm_node_allocated(&vma
->node
)) {
4084 vma
= i915_gem_object_bind_to_vm(obj
, vm
, alignment
, flags
);
4086 return PTR_ERR(vma
);
4089 if (flags
& PIN_GLOBAL
&& !obj
->has_global_gtt_mapping
)
4090 vma
->bind_vma(vma
, obj
->cache_level
, GLOBAL_BIND
);
4093 if (flags
& PIN_MAPPABLE
)
4094 obj
->pin_mappable
|= true;
4100 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
4102 struct i915_vma
*vma
= i915_gem_obj_to_ggtt(obj
);
4105 BUG_ON(vma
->pin_count
== 0);
4106 BUG_ON(!i915_gem_obj_ggtt_bound(obj
));
4108 if (--vma
->pin_count
== 0)
4109 obj
->pin_mappable
= false;
4113 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
4115 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4116 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4117 struct i915_vma
*ggtt_vma
= i915_gem_obj_to_ggtt(obj
);
4119 WARN_ON(!ggtt_vma
||
4120 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
>
4121 ggtt_vma
->pin_count
);
4122 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
4129 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
4131 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
4132 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
4133 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
4134 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
4139 i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
4140 struct drm_file
*file
)
4142 struct drm_i915_gem_pin
*args
= data
;
4143 struct drm_i915_gem_object
*obj
;
4146 if (INTEL_INFO(dev
)->gen
>= 6)
4149 ret
= i915_mutex_lock_interruptible(dev
);
4153 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4154 if (&obj
->base
== NULL
) {
4159 if (obj
->madv
!= I915_MADV_WILLNEED
) {
4160 DRM_DEBUG("Attempting to pin a purgeable buffer\n");
4165 if (obj
->pin_filp
!= NULL
&& obj
->pin_filp
!= file
) {
4166 DRM_DEBUG("Already pinned in i915_gem_pin_ioctl(): %d\n",
4172 if (obj
->user_pin_count
== ULONG_MAX
) {
4177 if (obj
->user_pin_count
== 0) {
4178 ret
= i915_gem_obj_ggtt_pin(obj
, args
->alignment
, PIN_MAPPABLE
);
4183 obj
->user_pin_count
++;
4184 obj
->pin_filp
= file
;
4186 args
->offset
= i915_gem_obj_ggtt_offset(obj
);
4188 drm_gem_object_unreference(&obj
->base
);
4190 mutex_unlock(&dev
->struct_mutex
);
4195 i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
4196 struct drm_file
*file
)
4198 struct drm_i915_gem_pin
*args
= data
;
4199 struct drm_i915_gem_object
*obj
;
4202 ret
= i915_mutex_lock_interruptible(dev
);
4206 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4207 if (&obj
->base
== NULL
) {
4212 if (obj
->pin_filp
!= file
) {
4213 DRM_DEBUG("Not pinned by caller in i915_gem_pin_ioctl(): %d\n",
4218 obj
->user_pin_count
--;
4219 if (obj
->user_pin_count
== 0) {
4220 obj
->pin_filp
= NULL
;
4221 i915_gem_object_ggtt_unpin(obj
);
4225 drm_gem_object_unreference(&obj
->base
);
4227 mutex_unlock(&dev
->struct_mutex
);
4232 i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
4233 struct drm_file
*file
)
4235 struct drm_i915_gem_busy
*args
= data
;
4236 struct drm_i915_gem_object
*obj
;
4239 ret
= i915_mutex_lock_interruptible(dev
);
4243 intel_edp_psr_exit(dev
, true);
4245 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, args
->handle
));
4246 if (&obj
->base
== NULL
) {
4251 /* Count all active objects as busy, even if they are currently not used
4252 * by the gpu. Users of this interface expect objects to eventually
4253 * become non-busy without any further actions, therefore emit any
4254 * necessary flushes here.
4256 ret
= i915_gem_object_flush_active(obj
);
4258 args
->busy
= obj
->active
;
4260 BUILD_BUG_ON(I915_NUM_RINGS
> 16);
4261 args
->busy
|= intel_ring_flag(obj
->ring
) << 16;
4264 drm_gem_object_unreference(&obj
->base
);
4266 mutex_unlock(&dev
->struct_mutex
);
4271 i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
4272 struct drm_file
*file_priv
)
4274 return i915_gem_ring_throttle(dev
, file_priv
);
4278 i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
4279 struct drm_file
*file_priv
)
4281 struct drm_i915_gem_madvise
*args
= data
;
4282 struct drm_i915_gem_object
*obj
;
4285 switch (args
->madv
) {
4286 case I915_MADV_DONTNEED
:
4287 case I915_MADV_WILLNEED
:
4293 ret
= i915_mutex_lock_interruptible(dev
);
4297 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file_priv
, args
->handle
));
4298 if (&obj
->base
== NULL
) {
4303 if (i915_gem_obj_is_pinned(obj
)) {
4308 if (obj
->madv
!= __I915_MADV_PURGED
)
4309 obj
->madv
= args
->madv
;
4311 /* if the object is no longer attached, discard its backing storage */
4312 if (i915_gem_object_is_purgeable(obj
) && obj
->pages
== NULL
)
4313 i915_gem_object_truncate(obj
);
4315 args
->retained
= obj
->madv
!= __I915_MADV_PURGED
;
4318 drm_gem_object_unreference(&obj
->base
);
4320 mutex_unlock(&dev
->struct_mutex
);
4324 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
4325 const struct drm_i915_gem_object_ops
*ops
)
4327 INIT_LIST_HEAD(&obj
->global_list
);
4328 INIT_LIST_HEAD(&obj
->ring_list
);
4329 INIT_LIST_HEAD(&obj
->obj_exec_link
);
4330 INIT_LIST_HEAD(&obj
->vma_list
);
4334 obj
->fence_reg
= I915_FENCE_REG_NONE
;
4335 obj
->madv
= I915_MADV_WILLNEED
;
4336 /* Avoid an unnecessary call to unbind on the first bind. */
4337 obj
->map_and_fenceable
= true;
4339 i915_gem_info_add_obj(obj
->base
.dev
->dev_private
, obj
->base
.size
);
4342 static const struct drm_i915_gem_object_ops i915_gem_object_ops
= {
4343 .get_pages
= i915_gem_object_get_pages_gtt
,
4344 .put_pages
= i915_gem_object_put_pages_gtt
,
4347 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
4350 struct drm_i915_gem_object
*obj
;
4351 struct address_space
*mapping
;
4354 obj
= i915_gem_object_alloc(dev
);
4358 if (drm_gem_object_init(dev
, &obj
->base
, size
) != 0) {
4359 i915_gem_object_free(obj
);
4363 mask
= GFP_HIGHUSER
| __GFP_RECLAIMABLE
;
4364 if (IS_CRESTLINE(dev
) || IS_BROADWATER(dev
)) {
4365 /* 965gm cannot relocate objects above 4GiB. */
4366 mask
&= ~__GFP_HIGHMEM
;
4367 mask
|= __GFP_DMA32
;
4370 mapping
= file_inode(obj
->base
.filp
)->i_mapping
;
4371 mapping_set_gfp_mask(mapping
, mask
);
4373 i915_gem_object_init(obj
, &i915_gem_object_ops
);
4375 obj
->base
.write_domain
= I915_GEM_DOMAIN_CPU
;
4376 obj
->base
.read_domains
= I915_GEM_DOMAIN_CPU
;
4379 /* On some devices, we can have the GPU use the LLC (the CPU
4380 * cache) for about a 10% performance improvement
4381 * compared to uncached. Graphics requests other than
4382 * display scanout are coherent with the CPU in
4383 * accessing this cache. This means in this mode we
4384 * don't need to clflush on the CPU side, and on the
4385 * GPU side we only need to flush internal caches to
4386 * get data visible to the CPU.
4388 * However, we maintain the display planes as UC, and so
4389 * need to rebind when first used as such.
4391 obj
->cache_level
= I915_CACHE_LLC
;
4393 obj
->cache_level
= I915_CACHE_NONE
;
4395 trace_i915_gem_object_create(obj
);
4400 static bool discard_backing_storage(struct drm_i915_gem_object
*obj
)
4402 /* If we are the last user of the backing storage (be it shmemfs
4403 * pages or stolen etc), we know that the pages are going to be
4404 * immediately released. In this case, we can then skip copying
4405 * back the contents from the GPU.
4408 if (obj
->madv
!= I915_MADV_WILLNEED
)
4411 if (obj
->base
.filp
== NULL
)
4414 /* At first glance, this looks racy, but then again so would be
4415 * userspace racing mmap against close. However, the first external
4416 * reference to the filp can only be obtained through the
4417 * i915_gem_mmap_ioctl() which safeguards us against the user
4418 * acquiring such a reference whilst we are in the middle of
4419 * freeing the object.
4421 return atomic_long_read(&obj
->base
.filp
->f_count
) == 1;
4424 void i915_gem_free_object(struct drm_gem_object
*gem_obj
)
4426 struct drm_i915_gem_object
*obj
= to_intel_bo(gem_obj
);
4427 struct drm_device
*dev
= obj
->base
.dev
;
4428 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4429 struct i915_vma
*vma
, *next
;
4431 intel_runtime_pm_get(dev_priv
);
4433 trace_i915_gem_object_destroy(obj
);
4435 list_for_each_entry_safe(vma
, next
, &obj
->vma_list
, vma_link
) {
4439 ret
= i915_vma_unbind(vma
);
4440 if (WARN_ON(ret
== -ERESTARTSYS
)) {
4441 bool was_interruptible
;
4443 was_interruptible
= dev_priv
->mm
.interruptible
;
4444 dev_priv
->mm
.interruptible
= false;
4446 WARN_ON(i915_vma_unbind(vma
));
4448 dev_priv
->mm
.interruptible
= was_interruptible
;
4452 i915_gem_object_detach_phys(obj
);
4454 /* Stolen objects don't hold a ref, but do hold pin count. Fix that up
4455 * before progressing. */
4457 i915_gem_object_unpin_pages(obj
);
4459 if (WARN_ON(obj
->pages_pin_count
))
4460 obj
->pages_pin_count
= 0;
4461 if (discard_backing_storage(obj
))
4462 obj
->madv
= I915_MADV_DONTNEED
;
4463 i915_gem_object_put_pages(obj
);
4464 i915_gem_object_free_mmap_offset(obj
);
4468 if (obj
->base
.import_attach
)
4469 drm_prime_gem_destroy(&obj
->base
, NULL
);
4471 if (obj
->ops
->release
)
4472 obj
->ops
->release(obj
);
4474 drm_gem_object_release(&obj
->base
);
4475 i915_gem_info_remove_obj(dev_priv
, obj
->base
.size
);
4478 i915_gem_object_free(obj
);
4480 intel_runtime_pm_put(dev_priv
);
4483 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
4484 struct i915_address_space
*vm
)
4486 struct i915_vma
*vma
;
4487 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
4494 void i915_gem_vma_destroy(struct i915_vma
*vma
)
4496 WARN_ON(vma
->node
.allocated
);
4498 /* Keep the vma as a placeholder in the execbuffer reservation lists */
4499 if (!list_empty(&vma
->exec_list
))
4502 list_del(&vma
->vma_link
);
4508 i915_gem_stop_ringbuffers(struct drm_device
*dev
)
4510 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4511 struct intel_engine_cs
*ring
;
4514 for_each_ring(ring
, dev_priv
, i
)
4515 intel_stop_ring_buffer(ring
);
4519 i915_gem_suspend(struct drm_device
*dev
)
4521 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4524 mutex_lock(&dev
->struct_mutex
);
4525 if (dev_priv
->ums
.mm_suspended
)
4528 ret
= i915_gpu_idle(dev
);
4532 i915_gem_retire_requests(dev
);
4534 /* Under UMS, be paranoid and evict. */
4535 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4536 i915_gem_evict_everything(dev
);
4538 i915_kernel_lost_context(dev
);
4539 i915_gem_stop_ringbuffers(dev
);
4541 /* Hack! Don't let anybody do execbuf while we don't control the chip.
4542 * We need to replace this with a semaphore, or something.
4543 * And not confound ums.mm_suspended!
4545 dev_priv
->ums
.mm_suspended
= !drm_core_check_feature(dev
,
4547 mutex_unlock(&dev
->struct_mutex
);
4549 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
4550 cancel_delayed_work_sync(&dev_priv
->mm
.retire_work
);
4551 cancel_delayed_work_sync(&dev_priv
->mm
.idle_work
);
4556 mutex_unlock(&dev
->struct_mutex
);
4560 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
)
4562 struct drm_device
*dev
= ring
->dev
;
4563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4564 u32 reg_base
= GEN7_L3LOG_BASE
+ (slice
* 0x200);
4565 u32
*remap_info
= dev_priv
->l3_parity
.remap_info
[slice
];
4568 if (!HAS_L3_DPF(dev
) || !remap_info
)
4571 ret
= intel_ring_begin(ring
, GEN7_L3LOG_SIZE
/ 4 * 3);
4576 * Note: We do not worry about the concurrent register cacheline hang
4577 * here because no other code should access these registers other than
4578 * at initialization time.
4580 for (i
= 0; i
< GEN7_L3LOG_SIZE
; i
+= 4) {
4581 intel_ring_emit(ring
, MI_LOAD_REGISTER_IMM(1));
4582 intel_ring_emit(ring
, reg_base
+ i
);
4583 intel_ring_emit(ring
, remap_info
[i
/4]);
4586 intel_ring_advance(ring
);
4591 void i915_gem_init_swizzling(struct drm_device
*dev
)
4593 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4595 if (INTEL_INFO(dev
)->gen
< 5 ||
4596 dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_NONE
)
4599 I915_WRITE(DISP_ARB_CTL
, I915_READ(DISP_ARB_CTL
) |
4600 DISP_TILE_SURFACE_SWIZZLING
);
4605 I915_WRITE(TILECTL
, I915_READ(TILECTL
) | TILECTL_SWZCTL
);
4607 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_SNB
));
4608 else if (IS_GEN7(dev
))
4609 I915_WRITE(ARB_MODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_IVB
));
4610 else if (IS_GEN8(dev
))
4611 I915_WRITE(GAMTARBMODE
, _MASKED_BIT_ENABLE(ARB_MODE_SWIZZLE_BDW
));
4617 intel_enable_blt(struct drm_device
*dev
)
4622 /* The blitter was dysfunctional on early prototypes */
4623 if (IS_GEN6(dev
) && dev
->pdev
->revision
< 8) {
4624 DRM_INFO("BLT not supported on this pre-production hardware;"
4625 " graphics performance will be degraded.\n");
4632 static int i915_gem_init_rings(struct drm_device
*dev
)
4634 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4637 ret
= intel_init_render_ring_buffer(dev
);
4642 ret
= intel_init_bsd_ring_buffer(dev
);
4644 goto cleanup_render_ring
;
4647 if (intel_enable_blt(dev
)) {
4648 ret
= intel_init_blt_ring_buffer(dev
);
4650 goto cleanup_bsd_ring
;
4653 if (HAS_VEBOX(dev
)) {
4654 ret
= intel_init_vebox_ring_buffer(dev
);
4656 goto cleanup_blt_ring
;
4659 if (HAS_BSD2(dev
)) {
4660 ret
= intel_init_bsd2_ring_buffer(dev
);
4662 goto cleanup_vebox_ring
;
4665 ret
= i915_gem_set_seqno(dev
, ((u32
)~0 - 0x1000));
4667 goto cleanup_bsd2_ring
;
4672 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS2
]);
4674 intel_cleanup_ring_buffer(&dev_priv
->ring
[VECS
]);
4676 intel_cleanup_ring_buffer(&dev_priv
->ring
[BCS
]);
4678 intel_cleanup_ring_buffer(&dev_priv
->ring
[VCS
]);
4679 cleanup_render_ring
:
4680 intel_cleanup_ring_buffer(&dev_priv
->ring
[RCS
]);
4686 i915_gem_init_hw(struct drm_device
*dev
)
4688 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4691 if (INTEL_INFO(dev
)->gen
< 6 && !intel_enable_gtt())
4694 if (dev_priv
->ellc_size
)
4695 I915_WRITE(HSW_IDICR
, I915_READ(HSW_IDICR
) | IDIHASHMSK(0xf));
4697 if (IS_HASWELL(dev
))
4698 I915_WRITE(MI_PREDICATE_RESULT_2
, IS_HSW_GT3(dev
) ?
4699 LOWER_SLICE_ENABLED
: LOWER_SLICE_DISABLED
);
4701 if (HAS_PCH_NOP(dev
)) {
4702 if (IS_IVYBRIDGE(dev
)) {
4703 u32 temp
= I915_READ(GEN7_MSG_CTL
);
4704 temp
&= ~(WAIT_FOR_PCH_FLR_ACK
| WAIT_FOR_PCH_RESET_ACK
);
4705 I915_WRITE(GEN7_MSG_CTL
, temp
);
4706 } else if (INTEL_INFO(dev
)->gen
>= 7) {
4707 u32 temp
= I915_READ(HSW_NDE_RSTWRN_OPT
);
4708 temp
&= ~RESET_PCH_HANDSHAKE_ENABLE
;
4709 I915_WRITE(HSW_NDE_RSTWRN_OPT
, temp
);
4713 i915_gem_init_swizzling(dev
);
4715 ret
= i915_gem_init_rings(dev
);
4719 for (i
= 0; i
< NUM_L3_SLICES(dev
); i
++)
4720 i915_gem_l3_remap(&dev_priv
->ring
[RCS
], i
);
4723 * XXX: Contexts should only be initialized once. Doing a switch to the
4724 * default context switch however is something we'd like to do after
4725 * reset or thaw (the latter may not actually be necessary for HW, but
4726 * goes with our code better). Context switching requires rings (for
4727 * the do_switch), but before enabling PPGTT. So don't move this.
4729 ret
= i915_gem_context_enable(dev_priv
);
4730 if (ret
&& ret
!= -EIO
) {
4731 DRM_ERROR("Context enable failed %d\n", ret
);
4732 i915_gem_cleanup_ringbuffer(dev
);
4738 int i915_gem_init(struct drm_device
*dev
)
4740 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4743 mutex_lock(&dev
->struct_mutex
);
4745 if (IS_VALLEYVIEW(dev
)) {
4746 /* VLVA0 (potential hack), BIOS isn't actually waking us */
4747 I915_WRITE(VLV_GTLC_WAKE_CTRL
, VLV_GTLC_ALLOWWAKEREQ
);
4748 if (wait_for((I915_READ(VLV_GTLC_PW_STATUS
) &
4749 VLV_GTLC_ALLOWWAKEACK
), 10))
4750 DRM_DEBUG_DRIVER("allow wake ack timed out\n");
4753 i915_gem_init_userptr(dev
);
4754 i915_gem_init_global_gtt(dev
);
4756 ret
= i915_gem_context_init(dev
);
4758 mutex_unlock(&dev
->struct_mutex
);
4762 ret
= i915_gem_init_hw(dev
);
4764 /* Allow ring initialisation to fail by marking the GPU as
4765 * wedged. But we only want to do this where the GPU is angry,
4766 * for all other failure, such as an allocation failure, bail.
4768 DRM_ERROR("Failed to initialize GPU, declaring it wedged\n");
4769 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
4772 mutex_unlock(&dev
->struct_mutex
);
4774 /* Allow hardware batchbuffers unless told otherwise, but not for KMS. */
4775 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4776 dev_priv
->dri1
.allow_batchbuffer
= 1;
4781 i915_gem_cleanup_ringbuffer(struct drm_device
*dev
)
4783 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4784 struct intel_engine_cs
*ring
;
4787 for_each_ring(ring
, dev_priv
, i
)
4788 intel_cleanup_ring_buffer(ring
);
4792 i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
4793 struct drm_file
*file_priv
)
4795 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4798 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4801 if (i915_reset_in_progress(&dev_priv
->gpu_error
)) {
4802 DRM_ERROR("Reenabling wedged hardware, good luck\n");
4803 atomic_set(&dev_priv
->gpu_error
.reset_counter
, 0);
4806 mutex_lock(&dev
->struct_mutex
);
4807 dev_priv
->ums
.mm_suspended
= 0;
4809 ret
= i915_gem_init_hw(dev
);
4811 mutex_unlock(&dev
->struct_mutex
);
4815 BUG_ON(!list_empty(&dev_priv
->gtt
.base
.active_list
));
4817 ret
= drm_irq_install(dev
, dev
->pdev
->irq
);
4819 goto cleanup_ringbuffer
;
4820 mutex_unlock(&dev
->struct_mutex
);
4825 i915_gem_cleanup_ringbuffer(dev
);
4826 dev_priv
->ums
.mm_suspended
= 1;
4827 mutex_unlock(&dev
->struct_mutex
);
4833 i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
4834 struct drm_file
*file_priv
)
4836 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4839 mutex_lock(&dev
->struct_mutex
);
4840 drm_irq_uninstall(dev
);
4841 mutex_unlock(&dev
->struct_mutex
);
4843 return i915_gem_suspend(dev
);
4847 i915_gem_lastclose(struct drm_device
*dev
)
4851 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
4854 ret
= i915_gem_suspend(dev
);
4856 DRM_ERROR("failed to idle hardware: %d\n", ret
);
4860 init_ring_lists(struct intel_engine_cs
*ring
)
4862 INIT_LIST_HEAD(&ring
->active_list
);
4863 INIT_LIST_HEAD(&ring
->request_list
);
4866 void i915_init_vm(struct drm_i915_private
*dev_priv
,
4867 struct i915_address_space
*vm
)
4869 if (!i915_is_ggtt(vm
))
4870 drm_mm_init(&vm
->mm
, vm
->start
, vm
->total
);
4871 vm
->dev
= dev_priv
->dev
;
4872 INIT_LIST_HEAD(&vm
->active_list
);
4873 INIT_LIST_HEAD(&vm
->inactive_list
);
4874 INIT_LIST_HEAD(&vm
->global_link
);
4875 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
4879 i915_gem_load(struct drm_device
*dev
)
4881 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4885 kmem_cache_create("i915_gem_object",
4886 sizeof(struct drm_i915_gem_object
), 0,
4890 INIT_LIST_HEAD(&dev_priv
->vm_list
);
4891 i915_init_vm(dev_priv
, &dev_priv
->gtt
.base
);
4893 INIT_LIST_HEAD(&dev_priv
->context_list
);
4894 INIT_LIST_HEAD(&dev_priv
->mm
.unbound_list
);
4895 INIT_LIST_HEAD(&dev_priv
->mm
.bound_list
);
4896 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4897 for (i
= 0; i
< I915_NUM_RINGS
; i
++)
4898 init_ring_lists(&dev_priv
->ring
[i
]);
4899 for (i
= 0; i
< I915_MAX_NUM_FENCES
; i
++)
4900 INIT_LIST_HEAD(&dev_priv
->fence_regs
[i
].lru_list
);
4901 INIT_DELAYED_WORK(&dev_priv
->mm
.retire_work
,
4902 i915_gem_retire_work_handler
);
4903 INIT_DELAYED_WORK(&dev_priv
->mm
.idle_work
,
4904 i915_gem_idle_work_handler
);
4905 init_waitqueue_head(&dev_priv
->gpu_error
.reset_queue
);
4907 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
4908 if (!drm_core_check_feature(dev
, DRIVER_MODESET
) && IS_GEN3(dev
)) {
4909 I915_WRITE(MI_ARB_STATE
,
4910 _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE
));
4913 dev_priv
->relative_constants_mode
= I915_EXEC_CONSTANTS_REL_GENERAL
;
4915 /* Old X drivers will take 0-2 for front, back, depth buffers */
4916 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
4917 dev_priv
->fence_reg_start
= 3;
4919 if (INTEL_INFO(dev
)->gen
>= 7 && !IS_VALLEYVIEW(dev
))
4920 dev_priv
->num_fence_regs
= 32;
4921 else if (INTEL_INFO(dev
)->gen
>= 4 || IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4922 dev_priv
->num_fence_regs
= 16;
4924 dev_priv
->num_fence_regs
= 8;
4926 /* Initialize fence registers to zero */
4927 INIT_LIST_HEAD(&dev_priv
->mm
.fence_list
);
4928 i915_gem_restore_fences(dev
);
4930 i915_gem_detect_bit_6_swizzle(dev
);
4931 init_waitqueue_head(&dev_priv
->pending_flip_queue
);
4933 dev_priv
->mm
.interruptible
= true;
4935 dev_priv
->mm
.shrinker
.scan_objects
= i915_gem_shrinker_scan
;
4936 dev_priv
->mm
.shrinker
.count_objects
= i915_gem_shrinker_count
;
4937 dev_priv
->mm
.shrinker
.seeks
= DEFAULT_SEEKS
;
4938 register_shrinker(&dev_priv
->mm
.shrinker
);
4940 dev_priv
->mm
.oom_notifier
.notifier_call
= i915_gem_shrinker_oom
;
4941 register_oom_notifier(&dev_priv
->mm
.oom_notifier
);
4944 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
)
4946 struct drm_i915_file_private
*file_priv
= file
->driver_priv
;
4948 cancel_delayed_work_sync(&file_priv
->mm
.idle_work
);
4950 /* Clean up our request list when the client is going away, so that
4951 * later retire_requests won't dereference our soon-to-be-gone
4954 spin_lock(&file_priv
->mm
.lock
);
4955 while (!list_empty(&file_priv
->mm
.request_list
)) {
4956 struct drm_i915_gem_request
*request
;
4958 request
= list_first_entry(&file_priv
->mm
.request_list
,
4959 struct drm_i915_gem_request
,
4961 list_del(&request
->client_list
);
4962 request
->file_priv
= NULL
;
4964 spin_unlock(&file_priv
->mm
.lock
);
4968 i915_gem_file_idle_work_handler(struct work_struct
*work
)
4970 struct drm_i915_file_private
*file_priv
=
4971 container_of(work
, typeof(*file_priv
), mm
.idle_work
.work
);
4973 atomic_set(&file_priv
->rps_wait_boost
, false);
4976 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
)
4978 struct drm_i915_file_private
*file_priv
;
4981 DRM_DEBUG_DRIVER("\n");
4983 file_priv
= kzalloc(sizeof(*file_priv
), GFP_KERNEL
);
4987 file
->driver_priv
= file_priv
;
4988 file_priv
->dev_priv
= dev
->dev_private
;
4989 file_priv
->file
= file
;
4991 spin_lock_init(&file_priv
->mm
.lock
);
4992 INIT_LIST_HEAD(&file_priv
->mm
.request_list
);
4993 INIT_DELAYED_WORK(&file_priv
->mm
.idle_work
,
4994 i915_gem_file_idle_work_handler
);
4996 ret
= i915_gem_context_open(dev
, file
);
5003 static bool mutex_is_locked_by(struct mutex
*mutex
, struct task_struct
*task
)
5005 if (!mutex_is_locked(mutex
))
5008 #if defined(CONFIG_SMP) || defined(CONFIG_DEBUG_MUTEXES)
5009 return mutex
->owner
== task
;
5011 /* Since UP may be pre-empted, we cannot assume that we own the lock */
5016 static bool i915_gem_shrinker_lock(struct drm_device
*dev
, bool *unlock
)
5018 if (!mutex_trylock(&dev
->struct_mutex
)) {
5019 if (!mutex_is_locked_by(&dev
->struct_mutex
, current
))
5022 if (to_i915(dev
)->mm
.shrinker_no_lock_stealing
)
5032 static int num_vma_bound(struct drm_i915_gem_object
*obj
)
5034 struct i915_vma
*vma
;
5037 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
5038 if (drm_mm_node_allocated(&vma
->node
))
5044 static unsigned long
5045 i915_gem_shrinker_count(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5047 struct drm_i915_private
*dev_priv
=
5048 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5049 struct drm_device
*dev
= dev_priv
->dev
;
5050 struct drm_i915_gem_object
*obj
;
5051 unsigned long count
;
5054 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5058 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
)
5059 if (obj
->pages_pin_count
== 0)
5060 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5062 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5063 if (!i915_gem_obj_is_pinned(obj
) &&
5064 obj
->pages_pin_count
== num_vma_bound(obj
))
5065 count
+= obj
->base
.size
>> PAGE_SHIFT
;
5069 mutex_unlock(&dev
->struct_mutex
);
5074 /* All the new VM stuff */
5075 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
5076 struct i915_address_space
*vm
)
5078 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5079 struct i915_vma
*vma
;
5081 if (!dev_priv
->mm
.aliasing_ppgtt
||
5082 vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
5083 vm
= &dev_priv
->gtt
.base
;
5085 BUG_ON(list_empty(&o
->vma_list
));
5086 list_for_each_entry(vma
, &o
->vma_list
, vma_link
) {
5088 return vma
->node
.start
;
5094 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
5095 struct i915_address_space
*vm
)
5097 struct i915_vma
*vma
;
5099 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5100 if (vma
->vm
== vm
&& drm_mm_node_allocated(&vma
->node
))
5106 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
)
5108 struct i915_vma
*vma
;
5110 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5111 if (drm_mm_node_allocated(&vma
->node
))
5117 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
5118 struct i915_address_space
*vm
)
5120 struct drm_i915_private
*dev_priv
= o
->base
.dev
->dev_private
;
5121 struct i915_vma
*vma
;
5123 if (!dev_priv
->mm
.aliasing_ppgtt
||
5124 vm
== &dev_priv
->mm
.aliasing_ppgtt
->base
)
5125 vm
= &dev_priv
->gtt
.base
;
5127 BUG_ON(list_empty(&o
->vma_list
));
5129 list_for_each_entry(vma
, &o
->vma_list
, vma_link
)
5131 return vma
->node
.size
;
5136 static unsigned long
5137 i915_gem_shrinker_scan(struct shrinker
*shrinker
, struct shrink_control
*sc
)
5139 struct drm_i915_private
*dev_priv
=
5140 container_of(shrinker
, struct drm_i915_private
, mm
.shrinker
);
5141 struct drm_device
*dev
= dev_priv
->dev
;
5142 unsigned long freed
;
5145 if (!i915_gem_shrinker_lock(dev
, &unlock
))
5148 freed
= i915_gem_purge(dev_priv
, sc
->nr_to_scan
);
5149 if (freed
< sc
->nr_to_scan
)
5150 freed
+= __i915_gem_shrink(dev_priv
,
5151 sc
->nr_to_scan
- freed
,
5154 mutex_unlock(&dev
->struct_mutex
);
5160 i915_gem_shrinker_oom(struct notifier_block
*nb
, unsigned long event
, void *ptr
)
5162 struct drm_i915_private
*dev_priv
=
5163 container_of(nb
, struct drm_i915_private
, mm
.oom_notifier
);
5164 struct drm_device
*dev
= dev_priv
->dev
;
5165 struct drm_i915_gem_object
*obj
;
5166 unsigned long timeout
= msecs_to_jiffies(5000) + 1;
5167 unsigned long pinned
, bound
, unbound
, freed
;
5168 bool was_interruptible
;
5171 while (!i915_gem_shrinker_lock(dev
, &unlock
) && --timeout
)
5172 schedule_timeout_killable(1);
5174 pr_err("Unable to purge GPU memory due lock contention.\n");
5178 was_interruptible
= dev_priv
->mm
.interruptible
;
5179 dev_priv
->mm
.interruptible
= false;
5181 freed
= i915_gem_shrink_all(dev_priv
);
5183 dev_priv
->mm
.interruptible
= was_interruptible
;
5185 /* Because we may be allocating inside our own driver, we cannot
5186 * assert that there are no objects with pinned pages that are not
5187 * being pointed to by hardware.
5189 unbound
= bound
= pinned
= 0;
5190 list_for_each_entry(obj
, &dev_priv
->mm
.unbound_list
, global_list
) {
5191 if (!obj
->base
.filp
) /* not backed by a freeable object */
5194 if (obj
->pages_pin_count
)
5195 pinned
+= obj
->base
.size
;
5197 unbound
+= obj
->base
.size
;
5199 list_for_each_entry(obj
, &dev_priv
->mm
.bound_list
, global_list
) {
5200 if (!obj
->base
.filp
)
5203 if (obj
->pages_pin_count
)
5204 pinned
+= obj
->base
.size
;
5206 bound
+= obj
->base
.size
;
5210 mutex_unlock(&dev
->struct_mutex
);
5212 pr_info("Purging GPU memory, %lu bytes freed, %lu bytes still pinned.\n",
5214 if (unbound
|| bound
)
5215 pr_err("%lu and %lu bytes still available in the "
5216 "bound and unbound GPU page lists.\n",
5219 *(unsigned long *)ptr
+= freed
;
5223 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
5225 struct i915_vma
*vma
;
5227 /* This WARN has probably outlived its usefulness (callers already
5228 * WARN if they don't find the GGTT vma they expect). When removing,
5229 * remember to remove the pre-check in is_pin_display() as well */
5230 if (WARN_ON(list_empty(&obj
->vma_list
)))
5233 vma
= list_first_entry(&obj
->vma_list
, typeof(*vma
), vma_link
);
5234 if (vma
->vm
!= obj_to_ggtt(obj
))