2 * Low-level exception handling code
4 * Copyright (C) 2012 ARM Ltd.
5 * Authors: Catalin Marinas <catalin.marinas@arm.com>
6 * Will Deacon <will.deacon@arm.com>
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
21 #include <linux/init.h>
22 #include <linux/linkage.h>
24 #include <asm/alternative.h>
25 #include <asm/assembler.h>
26 #include <asm/asm-offsets.h>
27 #include <asm/cpufeature.h>
28 #include <asm/errno.h>
31 #include <asm/memory.h>
32 #include <asm/ptrace.h>
33 #include <asm/thread_info.h>
34 #include <linux/uaccess.h>
35 #include <asm/unistd.h>
38 * Context tracking subsystem. Used to instrument transitions
39 * between user and kernel mode.
41 .macro ct_user_exit, syscall = 0
42 #ifdef CONFIG_CONTEXT_TRACKING
43 bl context_tracking_user_exit
46 * Save/restore needed during syscalls. Restore syscall arguments from
47 * the values already saved on stack during kernel_entry.
50 ldp x2, x3, [sp, #S_X2]
51 ldp x4, x5, [sp, #S_X4]
52 ldp x6, x7, [sp, #S_X6]
58 #ifdef CONFIG_CONTEXT_TRACKING
59 bl context_tracking_user_enter
72 .macro kernel_entry, el, regsize = 64
73 sub sp, sp, #S_FRAME_SIZE
75 mov w0, w0 // zero upper 32 bits of x0
77 stp x0, x1, [sp, #16 * 0]
78 stp x2, x3, [sp, #16 * 1]
79 stp x4, x5, [sp, #16 * 2]
80 stp x6, x7, [sp, #16 * 3]
81 stp x8, x9, [sp, #16 * 4]
82 stp x10, x11, [sp, #16 * 5]
83 stp x12, x13, [sp, #16 * 6]
84 stp x14, x15, [sp, #16 * 7]
85 stp x16, x17, [sp, #16 * 8]
86 stp x18, x19, [sp, #16 * 9]
87 stp x20, x21, [sp, #16 * 10]
88 stp x22, x23, [sp, #16 * 11]
89 stp x24, x25, [sp, #16 * 12]
90 stp x26, x27, [sp, #16 * 13]
91 stp x28, x29, [sp, #16 * 14]
95 ldr_this_cpu tsk, __entry_task, x20 // Ensure MDSCR_EL1.SS is clear,
96 ldr x19, [tsk, #TSK_TI_FLAGS] // since we can unmask debug
97 disable_step_tsk x19, x20 // exceptions when scheduling.
99 mov x29, xzr // fp pointed to user-space
101 add x21, sp, #S_FRAME_SIZE
103 /* Save the task's original addr_limit and set USER_DS (TASK_SIZE_64) */
104 ldr x20, [tsk, #TSK_TI_ADDR_LIMIT]
105 str x20, [sp, #S_ORIG_ADDR_LIMIT]
106 mov x20, #TASK_SIZE_64
107 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
108 /* No need to reset PSTATE.UAO, hardware's already set it to 0 for us */
109 .endif /* \el == 0 */
112 stp lr, x21, [sp, #S_LR]
114 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
116 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
117 * EL0, there is no need to check the state of TTBR0_EL1 since
118 * accesses are always enabled.
119 * Note that the meaning of this bit differs from the ARMv8.1 PAN
120 * feature as all TTBR0_EL1 accesses are disabled, not just those to
123 alternative_if ARM64_HAS_PAN
124 b 1f // skip TTBR0 PAN
125 alternative_else_nop_endif
129 tst x21, #0xffff << 48 // Check for the reserved ASID
130 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
131 b.eq 1f // TTBR0 access already disabled
132 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
135 __uaccess_ttbr0_disable x21
139 stp x22, x23, [sp, #S_PC]
142 * Set syscallno to -1 by default (overridden later if real syscall).
146 str x21, [sp, #S_SYSCALLNO]
150 * Set sp_el0 to current thread_info.
157 * Registers that may be useful after this macro is invoked:
161 * x23 - aborted PSTATE
165 .macro kernel_exit, el
167 /* Restore the task's original addr_limit. */
168 ldr x20, [sp, #S_ORIG_ADDR_LIMIT]
169 str x20, [tsk, #TSK_TI_ADDR_LIMIT]
171 /* No need to restore UAO, it will be restored from SPSR_EL1 */
174 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
179 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
181 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
184 alternative_if ARM64_HAS_PAN
185 b 2f // skip TTBR0 PAN
186 alternative_else_nop_endif
189 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
192 __uaccess_ttbr0_enable x0
196 * Enable errata workarounds only if returning to user. The only
197 * workaround currently required for TTBR0_EL1 changes are for the
198 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
201 post_ttbr0_update_workaround
205 and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
211 ldr x23, [sp, #S_SP] // load return stack pointer
213 #ifdef CONFIG_ARM64_ERRATUM_845719
214 alternative_if ARM64_WORKAROUND_845719
216 #ifdef CONFIG_PID_IN_CONTEXTIDR
217 mrs x29, contextidr_el1
218 msr contextidr_el1, x29
220 msr contextidr_el1, xzr
223 alternative_else_nop_endif
227 msr elr_el1, x21 // set up the return data
229 ldp x0, x1, [sp, #16 * 0]
230 ldp x2, x3, [sp, #16 * 1]
231 ldp x4, x5, [sp, #16 * 2]
232 ldp x6, x7, [sp, #16 * 3]
233 ldp x8, x9, [sp, #16 * 4]
234 ldp x10, x11, [sp, #16 * 5]
235 ldp x12, x13, [sp, #16 * 6]
236 ldp x14, x15, [sp, #16 * 7]
237 ldp x16, x17, [sp, #16 * 8]
238 ldp x18, x19, [sp, #16 * 9]
239 ldp x20, x21, [sp, #16 * 10]
240 ldp x22, x23, [sp, #16 * 11]
241 ldp x24, x25, [sp, #16 * 12]
242 ldp x26, x27, [sp, #16 * 13]
243 ldp x28, x29, [sp, #16 * 14]
245 add sp, sp, #S_FRAME_SIZE // restore sp
246 eret // return to kernel
249 .macro irq_stack_entry
250 mov x19, sp // preserve the original sp
253 * Compare sp with the base of the task stack.
254 * If the top ~(THREAD_SIZE - 1) bits match, we are on a task stack,
255 * and should switch to the irq stack.
257 ldr x25, [tsk, TSK_STACK]
259 and x25, x25, #~(THREAD_SIZE - 1)
262 adr_this_cpu x25, irq_stack, x26
263 mov x26, #IRQ_STACK_START_SP
266 /* switch to the irq stack */
270 * Add a dummy stack frame, this non-standard format is fixed up
273 stp x29, x19, [sp, #-16]!
280 * x19 should be preserved between irq_stack_entry and
283 .macro irq_stack_exit
288 * These are the registers used in the syscall handler, and allow us to
289 * have in theory up to 7 arguments to a function - x0 to x6.
291 * x7 is reserved for the system call number in 32-bit mode.
293 sc_nr .req x25 // number of system calls
294 scno .req x26 // syscall number
295 stbl .req x27 // syscall table pointer
296 tsk .req x28 // current thread_info
299 * Interrupt handling.
302 ldr_l x1, handle_arch_irq
314 .pushsection ".entry.text", "ax"
318 ventry el1_sync_invalid // Synchronous EL1t
319 ventry el1_irq_invalid // IRQ EL1t
320 ventry el1_fiq_invalid // FIQ EL1t
321 ventry el1_error_invalid // Error EL1t
323 ventry el1_sync // Synchronous EL1h
324 ventry el1_irq // IRQ EL1h
325 ventry el1_fiq_invalid // FIQ EL1h
326 ventry el1_error_invalid // Error EL1h
328 ventry el0_sync // Synchronous 64-bit EL0
329 ventry el0_irq // IRQ 64-bit EL0
330 ventry el0_fiq_invalid // FIQ 64-bit EL0
331 ventry el0_error_invalid // Error 64-bit EL0
334 ventry el0_sync_compat // Synchronous 32-bit EL0
335 ventry el0_irq_compat // IRQ 32-bit EL0
336 ventry el0_fiq_invalid_compat // FIQ 32-bit EL0
337 ventry el0_error_invalid_compat // Error 32-bit EL0
339 ventry el0_sync_invalid // Synchronous 32-bit EL0
340 ventry el0_irq_invalid // IRQ 32-bit EL0
341 ventry el0_fiq_invalid // FIQ 32-bit EL0
342 ventry el0_error_invalid // Error 32-bit EL0
347 * Invalid mode handlers
349 .macro inv_entry, el, reason, regsize = 64
350 kernel_entry \el, \regsize
358 inv_entry 0, BAD_SYNC
359 ENDPROC(el0_sync_invalid)
363 ENDPROC(el0_irq_invalid)
367 ENDPROC(el0_fiq_invalid)
370 inv_entry 0, BAD_ERROR
371 ENDPROC(el0_error_invalid)
374 el0_fiq_invalid_compat:
375 inv_entry 0, BAD_FIQ, 32
376 ENDPROC(el0_fiq_invalid_compat)
378 el0_error_invalid_compat:
379 inv_entry 0, BAD_ERROR, 32
380 ENDPROC(el0_error_invalid_compat)
384 inv_entry 1, BAD_SYNC
385 ENDPROC(el1_sync_invalid)
389 ENDPROC(el1_irq_invalid)
393 ENDPROC(el1_fiq_invalid)
396 inv_entry 1, BAD_ERROR
397 ENDPROC(el1_error_invalid)
405 mrs x1, esr_el1 // read the syndrome register
406 lsr x24, x1, #ESR_ELx_EC_SHIFT // exception class
407 cmp x24, #ESR_ELx_EC_DABT_CUR // data abort in EL1
409 cmp x24, #ESR_ELx_EC_IABT_CUR // instruction abort in EL1
411 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
413 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
415 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
417 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL1
419 cmp x24, #ESR_ELx_EC_BREAKPT_CUR // debug exception in EL1
425 * Fall through to the Data abort case
429 * Data abort handling
433 // re-enable interrupts if they were enabled in the aborted context
434 tbnz x23, #7, 1f // PSR_I_BIT
437 mov x2, sp // struct pt_regs
440 // disable interrupts before pulling preserved data off the stack
445 * Stack or PC alignment exception handling
453 * Undefined instruction
460 * Debug exception handling
462 cmp x24, #ESR_ELx_EC_BRK64 // if BRK64
463 cinc x24, x24, eq // set bit '0'
464 tbz x24, #0, el1_inv // EL1 only
466 mov x2, sp // struct pt_regs
467 bl do_debug_exception
470 // TODO: add support for undefined instructions in kernel mode
482 #ifdef CONFIG_TRACE_IRQFLAGS
483 bl trace_hardirqs_off
488 #ifdef CONFIG_PREEMPT
489 ldr w24, [tsk, #TSK_TI_PREEMPT] // get preempt count
490 cbnz w24, 1f // preempt count != 0
491 ldr x0, [tsk, #TSK_TI_FLAGS] // get flags
492 tbz x0, #TIF_NEED_RESCHED, 1f // needs rescheduling?
496 #ifdef CONFIG_TRACE_IRQFLAGS
502 #ifdef CONFIG_PREEMPT
505 1: bl preempt_schedule_irq // irq en/disable is done inside
506 ldr x0, [tsk, #TSK_TI_FLAGS] // get new tasks TI_FLAGS
507 tbnz x0, #TIF_NEED_RESCHED, 1b // needs rescheduling?
517 mrs x25, esr_el1 // read the syndrome register
518 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
519 cmp x24, #ESR_ELx_EC_SVC64 // SVC in 64-bit state
521 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
523 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
525 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
527 cmp x24, #ESR_ELx_EC_FP_EXC64 // FP/ASIMD exception
529 cmp x24, #ESR_ELx_EC_SYS64 // configurable trap
531 cmp x24, #ESR_ELx_EC_SP_ALIGN // stack alignment exception
533 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
535 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
537 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
545 mrs x25, esr_el1 // read the syndrome register
546 lsr x24, x25, #ESR_ELx_EC_SHIFT // exception class
547 cmp x24, #ESR_ELx_EC_SVC32 // SVC in 32-bit state
549 cmp x24, #ESR_ELx_EC_DABT_LOW // data abort in EL0
551 cmp x24, #ESR_ELx_EC_IABT_LOW // instruction abort in EL0
553 cmp x24, #ESR_ELx_EC_FP_ASIMD // FP/ASIMD access
555 cmp x24, #ESR_ELx_EC_FP_EXC32 // FP/ASIMD exception
557 cmp x24, #ESR_ELx_EC_PC_ALIGN // pc alignment exception
559 cmp x24, #ESR_ELx_EC_UNKNOWN // unknown exception in EL0
561 cmp x24, #ESR_ELx_EC_CP15_32 // CP15 MRC/MCR trap
563 cmp x24, #ESR_ELx_EC_CP15_64 // CP15 MRRC/MCRR trap
565 cmp x24, #ESR_ELx_EC_CP14_MR // CP14 MRC/MCR trap
567 cmp x24, #ESR_ELx_EC_CP14_LS // CP14 LDC/STC trap
569 cmp x24, #ESR_ELx_EC_CP14_64 // CP14 MRRC/MCRR trap
571 cmp x24, #ESR_ELx_EC_BREAKPT_LOW // debug exception in EL0
576 * AArch32 syscall handling
578 adrp stbl, compat_sys_call_table // load compat syscall table pointer
579 uxtw scno, w7 // syscall number in w7 (r7)
580 mov sc_nr, #__NR_compat_syscalls
591 * Data abort handling
594 // enable interrupts before calling the main handler
597 bic x0, x26, #(0xff << 56)
604 * Instruction abort handling
607 // enable interrupts before calling the main handler
617 * Floating Point or Advanced SIMD access
627 * Floating Point or Advanced SIMD exception
637 * Stack or PC alignment exception handling
640 // enable interrupts before calling the main handler
650 * Undefined instruction
652 // enable interrupts before calling the main handler
660 * System instructions, for trapped cache maintenance instructions
670 * Debug exception handling
672 tbnz x24, #0, el0_inv // EL0 only
676 bl do_debug_exception
695 #ifdef CONFIG_TRACE_IRQFLAGS
696 bl trace_hardirqs_off
702 #ifdef CONFIG_TRACE_IRQFLAGS
709 * Register switch for AArch64. The callee-saved registers need to be saved
710 * and restored. On entry:
711 * x0 = previous task_struct (must be preserved across the switch)
712 * x1 = next task_struct
713 * Previous and next are guaranteed not to be the same.
717 mov x10, #THREAD_CPU_CONTEXT
720 stp x19, x20, [x8], #16 // store callee-saved registers
721 stp x21, x22, [x8], #16
722 stp x23, x24, [x8], #16
723 stp x25, x26, [x8], #16
724 stp x27, x28, [x8], #16
725 stp x29, x9, [x8], #16
728 ldp x19, x20, [x8], #16 // restore callee-saved registers
729 ldp x21, x22, [x8], #16
730 ldp x23, x24, [x8], #16
731 ldp x25, x26, [x8], #16
732 ldp x27, x28, [x8], #16
733 ldp x29, x9, [x8], #16
738 ENDPROC(cpu_switch_to)
741 * This is the fast syscall return path. We do as little as possible here,
742 * and this includes saving x0 back into the kernel stack.
745 disable_irq // disable interrupts
746 str x0, [sp, #S_X0] // returned x0
747 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for syscall tracing
748 and x2, x1, #_TIF_SYSCALL_WORK
749 cbnz x2, ret_fast_syscall_trace
750 and x2, x1, #_TIF_WORK_MASK
751 cbnz x2, work_pending
752 enable_step_tsk x1, x2
754 ret_fast_syscall_trace:
755 enable_irq // enable interrupts
756 b __sys_trace_return_skipped // we already saved x0
759 * Ok, we need to do extra processing, enter the slow path.
764 #ifdef CONFIG_TRACE_IRQFLAGS
765 bl trace_hardirqs_on // enabled while in userspace
767 ldr x1, [tsk, #TSK_TI_FLAGS] // re-check for single-step
770 * "slow" syscall return path.
773 disable_irq // disable interrupts
774 ldr x1, [tsk, #TSK_TI_FLAGS]
775 and x2, x1, #_TIF_WORK_MASK
776 cbnz x2, work_pending
778 enable_step_tsk x1, x2
783 * This is how we return from a fork.
787 cbz x19, 1f // not a kernel thread
790 1: get_thread_info tsk
792 ENDPROC(ret_from_fork)
799 adrp stbl, sys_call_table // load syscall table pointer
800 uxtw scno, w8 // syscall number in w8
801 mov sc_nr, #__NR_syscalls
802 el0_svc_naked: // compat entry point
803 stp x0, scno, [sp, #S_ORIG_X0] // save the original x0 and syscall number
807 ldr x16, [tsk, #TSK_TI_FLAGS] // check for syscall hooks
808 tst x16, #_TIF_SYSCALL_WORK
810 cmp scno, sc_nr // check upper syscall limit
812 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
813 blr x16 // call sys_* routine
822 * This is the really slow path. We're going to be doing context
823 * switches, and waiting for our parent to respond.
826 mov w0, #-1 // set default errno for
827 cmp scno, x0 // user-issued syscall(-1)
832 bl syscall_trace_enter
833 cmp w0, #-1 // skip the syscall?
834 b.eq __sys_trace_return_skipped
835 uxtw scno, w0 // syscall number (possibly new)
836 mov x1, sp // pointer to regs
837 cmp scno, sc_nr // check upper syscall limit
839 ldp x0, x1, [sp] // restore the syscall args
840 ldp x2, x3, [sp, #S_X2]
841 ldp x4, x5, [sp, #S_X4]
842 ldp x6, x7, [sp, #S_X6]
843 ldr x16, [stbl, scno, lsl #3] // address in the syscall table
844 blr x16 // call sys_* routine
847 str x0, [sp, #S_X0] // save returned x0
848 __sys_trace_return_skipped:
850 bl syscall_trace_exit
858 .popsection // .entry.text
861 * Special system call wrappers.
863 ENTRY(sys_rt_sigreturn_wrapper)
866 ENDPROC(sys_rt_sigreturn_wrapper)