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drm/i915: Factor out intel_tile_width()
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / i915 / intel_display.c
blobd86e47a9cf6ff551f6e9959eb45b870bf66aa03d
1 /*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
35 #include <drm/drmP.h>
36 #include "intel_drv.h"
37 #include <drm/i915_drm.h>
38 #include "i915_drv.h"
39 #include "i915_trace.h"
40 #include <drm/drm_atomic.h>
41 #include <drm/drm_atomic_helper.h>
42 #include <drm/drm_dp_helper.h>
43 #include <drm/drm_crtc_helper.h>
44 #include <drm/drm_plane_helper.h>
45 #include <drm/drm_rect.h>
46 #include <linux/dma_remapping.h>
47 #include <linux/reservation.h>
48 #include <linux/dma-buf.h>
49
50 /* Primary plane formats for gen <= 3 */
51 static const uint32_t i8xx_primary_formats[] = {
52 DRM_FORMAT_C8,
53 DRM_FORMAT_RGB565,
54 DRM_FORMAT_XRGB1555,
55 DRM_FORMAT_XRGB8888,
56 };
57
58 /* Primary plane formats for gen >= 4 */
59 static const uint32_t i965_primary_formats[] = {
60 DRM_FORMAT_C8,
61 DRM_FORMAT_RGB565,
62 DRM_FORMAT_XRGB8888,
63 DRM_FORMAT_XBGR8888,
64 DRM_FORMAT_XRGB2101010,
65 DRM_FORMAT_XBGR2101010,
66 };
67
68 static const uint32_t skl_primary_formats[] = {
69 DRM_FORMAT_C8,
70 DRM_FORMAT_RGB565,
71 DRM_FORMAT_XRGB8888,
72 DRM_FORMAT_XBGR8888,
73 DRM_FORMAT_ARGB8888,
74 DRM_FORMAT_ABGR8888,
75 DRM_FORMAT_XRGB2101010,
76 DRM_FORMAT_XBGR2101010,
77 DRM_FORMAT_YUYV,
78 DRM_FORMAT_YVYU,
79 DRM_FORMAT_UYVY,
80 DRM_FORMAT_VYUY,
81 };
82
83 /* Cursor formats */
84 static const uint32_t intel_cursor_formats[] = {
85 DRM_FORMAT_ARGB8888,
86 };
87
88 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
89 struct intel_crtc_state *pipe_config);
90 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
91 struct intel_crtc_state *pipe_config);
92
93 static int intel_framebuffer_init(struct drm_device *dev,
94 struct intel_framebuffer *ifb,
95 struct drm_mode_fb_cmd2 *mode_cmd,
96 struct drm_i915_gem_object *obj);
97 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
98 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
99 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
100 struct intel_link_m_n *m_n,
101 struct intel_link_m_n *m2_n2);
102 static void ironlake_set_pipeconf(struct drm_crtc *crtc);
103 static void haswell_set_pipeconf(struct drm_crtc *crtc);
104 static void intel_set_pipe_csc(struct drm_crtc *crtc);
105 static void vlv_prepare_pll(struct intel_crtc *crtc,
106 const struct intel_crtc_state *pipe_config);
107 static void chv_prepare_pll(struct intel_crtc *crtc,
108 const struct intel_crtc_state *pipe_config);
109 static void intel_begin_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
110 static void intel_finish_crtc_commit(struct drm_crtc *, struct drm_crtc_state *);
111 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
112 struct intel_crtc_state *crtc_state);
113 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
114 int num_connectors);
115 static void skylake_pfit_enable(struct intel_crtc *crtc);
116 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force);
117 static void ironlake_pfit_enable(struct intel_crtc *crtc);
118 static void intel_modeset_setup_hw_state(struct drm_device *dev);
119 static void intel_pre_disable_primary(struct drm_crtc *crtc);
120
121 typedef struct {
122 int min, max;
123 } intel_range_t;
124
125 typedef struct {
126 int dot_limit;
127 int p2_slow, p2_fast;
128 } intel_p2_t;
129
130 typedef struct intel_limit intel_limit_t;
131 struct intel_limit {
132 intel_range_t dot, vco, n, m, m1, m2, p, p1;
133 intel_p2_t p2;
134 };
135
136 /* returns HPLL frequency in kHz */
137 static int valleyview_get_vco(struct drm_i915_private *dev_priv)
138 {
139 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
140
141 /* Obtain SKU information */
142 mutex_lock(&dev_priv->sb_lock);
143 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
144 CCK_FUSE_HPLL_FREQ_MASK;
145 mutex_unlock(&dev_priv->sb_lock);
146
147 return vco_freq[hpll_freq] * 1000;
148 }
149
150 static int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
151 const char *name, u32 reg)
152 {
153 u32 val;
154 int divider;
155
156 if (dev_priv->hpll_freq == 0)
157 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
158
159 mutex_lock(&dev_priv->sb_lock);
160 val = vlv_cck_read(dev_priv, reg);
161 mutex_unlock(&dev_priv->sb_lock);
162
163 divider = val & CCK_FREQUENCY_VALUES;
164
165 WARN((val & CCK_FREQUENCY_STATUS) !=
166 (divider << CCK_FREQUENCY_STATUS_SHIFT),
167 "%s change in progress\n", name);
168
169 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
170 }
171
172 int
173 intel_pch_rawclk(struct drm_device *dev)
174 {
175 struct drm_i915_private *dev_priv = dev->dev_private;
176
177 WARN_ON(!HAS_PCH_SPLIT(dev));
178
179 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
180 }
181
182 /* hrawclock is 1/4 the FSB frequency */
183 int intel_hrawclk(struct drm_device *dev)
184 {
185 struct drm_i915_private *dev_priv = dev->dev_private;
186 uint32_t clkcfg;
187
188 /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
189 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
190 return 200;
191
192 clkcfg = I915_READ(CLKCFG);
193 switch (clkcfg & CLKCFG_FSB_MASK) {
194 case CLKCFG_FSB_400:
195 return 100;
196 case CLKCFG_FSB_533:
197 return 133;
198 case CLKCFG_FSB_667:
199 return 166;
200 case CLKCFG_FSB_800:
201 return 200;
202 case CLKCFG_FSB_1067:
203 return 266;
204 case CLKCFG_FSB_1333:
205 return 333;
206 /* these two are just a guess; one of them might be right */
207 case CLKCFG_FSB_1600:
208 case CLKCFG_FSB_1600_ALT:
209 return 400;
210 default:
211 return 133;
212 }
213 }
214
215 static void intel_update_czclk(struct drm_i915_private *dev_priv)
216 {
217 if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
218 return;
219
220 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
221 CCK_CZ_CLOCK_CONTROL);
222
223 DRM_DEBUG_DRIVER("CZ clock rate: %d kHz\n", dev_priv->czclk_freq);
224 }
225
226 static inline u32 /* units of 100MHz */
227 intel_fdi_link_freq(struct drm_device *dev)
228 {
229 if (IS_GEN5(dev)) {
230 struct drm_i915_private *dev_priv = dev->dev_private;
231 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
232 } else
233 return 27;
234 }
235
236 static const intel_limit_t intel_limits_i8xx_dac = {
237 .dot = { .min = 25000, .max = 350000 },
238 .vco = { .min = 908000, .max = 1512000 },
239 .n = { .min = 2, .max = 16 },
240 .m = { .min = 96, .max = 140 },
241 .m1 = { .min = 18, .max = 26 },
242 .m2 = { .min = 6, .max = 16 },
243 .p = { .min = 4, .max = 128 },
244 .p1 = { .min = 2, .max = 33 },
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 4, .p2_fast = 2 },
247 };
248
249 static const intel_limit_t intel_limits_i8xx_dvo = {
250 .dot = { .min = 25000, .max = 350000 },
251 .vco = { .min = 908000, .max = 1512000 },
252 .n = { .min = 2, .max = 16 },
253 .m = { .min = 96, .max = 140 },
254 .m1 = { .min = 18, .max = 26 },
255 .m2 = { .min = 6, .max = 16 },
256 .p = { .min = 4, .max = 128 },
257 .p1 = { .min = 2, .max = 33 },
258 .p2 = { .dot_limit = 165000,
259 .p2_slow = 4, .p2_fast = 4 },
260 };
261
262 static const intel_limit_t intel_limits_i8xx_lvds = {
263 .dot = { .min = 25000, .max = 350000 },
264 .vco = { .min = 908000, .max = 1512000 },
265 .n = { .min = 2, .max = 16 },
266 .m = { .min = 96, .max = 140 },
267 .m1 = { .min = 18, .max = 26 },
268 .m2 = { .min = 6, .max = 16 },
269 .p = { .min = 4, .max = 128 },
270 .p1 = { .min = 1, .max = 6 },
271 .p2 = { .dot_limit = 165000,
272 .p2_slow = 14, .p2_fast = 7 },
273 };
274
275 static const intel_limit_t intel_limits_i9xx_sdvo = {
276 .dot = { .min = 20000, .max = 400000 },
277 .vco = { .min = 1400000, .max = 2800000 },
278 .n = { .min = 1, .max = 6 },
279 .m = { .min = 70, .max = 120 },
280 .m1 = { .min = 8, .max = 18 },
281 .m2 = { .min = 3, .max = 7 },
282 .p = { .min = 5, .max = 80 },
283 .p1 = { .min = 1, .max = 8 },
284 .p2 = { .dot_limit = 200000,
285 .p2_slow = 10, .p2_fast = 5 },
286 };
287
288 static const intel_limit_t intel_limits_i9xx_lvds = {
289 .dot = { .min = 20000, .max = 400000 },
290 .vco = { .min = 1400000, .max = 2800000 },
291 .n = { .min = 1, .max = 6 },
292 .m = { .min = 70, .max = 120 },
293 .m1 = { .min = 8, .max = 18 },
294 .m2 = { .min = 3, .max = 7 },
295 .p = { .min = 7, .max = 98 },
296 .p1 = { .min = 1, .max = 8 },
297 .p2 = { .dot_limit = 112000,
298 .p2_slow = 14, .p2_fast = 7 },
299 };
300
301
302 static const intel_limit_t intel_limits_g4x_sdvo = {
303 .dot = { .min = 25000, .max = 270000 },
304 .vco = { .min = 1750000, .max = 3500000},
305 .n = { .min = 1, .max = 4 },
306 .m = { .min = 104, .max = 138 },
307 .m1 = { .min = 17, .max = 23 },
308 .m2 = { .min = 5, .max = 11 },
309 .p = { .min = 10, .max = 30 },
310 .p1 = { .min = 1, .max = 3},
311 .p2 = { .dot_limit = 270000,
312 .p2_slow = 10,
313 .p2_fast = 10
314 },
315 };
316
317 static const intel_limit_t intel_limits_g4x_hdmi = {
318 .dot = { .min = 22000, .max = 400000 },
319 .vco = { .min = 1750000, .max = 3500000},
320 .n = { .min = 1, .max = 4 },
321 .m = { .min = 104, .max = 138 },
322 .m1 = { .min = 16, .max = 23 },
323 .m2 = { .min = 5, .max = 11 },
324 .p = { .min = 5, .max = 80 },
325 .p1 = { .min = 1, .max = 8},
326 .p2 = { .dot_limit = 165000,
327 .p2_slow = 10, .p2_fast = 5 },
328 };
329
330 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
331 .dot = { .min = 20000, .max = 115000 },
332 .vco = { .min = 1750000, .max = 3500000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 104, .max = 138 },
335 .m1 = { .min = 17, .max = 23 },
336 .m2 = { .min = 5, .max = 11 },
337 .p = { .min = 28, .max = 112 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 0,
340 .p2_slow = 14, .p2_fast = 14
341 },
342 };
343
344 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
345 .dot = { .min = 80000, .max = 224000 },
346 .vco = { .min = 1750000, .max = 3500000 },
347 .n = { .min = 1, .max = 3 },
348 .m = { .min = 104, .max = 138 },
349 .m1 = { .min = 17, .max = 23 },
350 .m2 = { .min = 5, .max = 11 },
351 .p = { .min = 14, .max = 42 },
352 .p1 = { .min = 2, .max = 6 },
353 .p2 = { .dot_limit = 0,
354 .p2_slow = 7, .p2_fast = 7
355 },
356 };
357
358 static const intel_limit_t intel_limits_pineview_sdvo = {
359 .dot = { .min = 20000, .max = 400000},
360 .vco = { .min = 1700000, .max = 3500000 },
361 /* Pineview's Ncounter is a ring counter */
362 .n = { .min = 3, .max = 6 },
363 .m = { .min = 2, .max = 256 },
364 /* Pineview only has one combined m divider, which we treat as m2. */
365 .m1 = { .min = 0, .max = 0 },
366 .m2 = { .min = 0, .max = 254 },
367 .p = { .min = 5, .max = 80 },
368 .p1 = { .min = 1, .max = 8 },
369 .p2 = { .dot_limit = 200000,
370 .p2_slow = 10, .p2_fast = 5 },
371 };
372
373 static const intel_limit_t intel_limits_pineview_lvds = {
374 .dot = { .min = 20000, .max = 400000 },
375 .vco = { .min = 1700000, .max = 3500000 },
376 .n = { .min = 3, .max = 6 },
377 .m = { .min = 2, .max = 256 },
378 .m1 = { .min = 0, .max = 0 },
379 .m2 = { .min = 0, .max = 254 },
380 .p = { .min = 7, .max = 112 },
381 .p1 = { .min = 1, .max = 8 },
382 .p2 = { .dot_limit = 112000,
383 .p2_slow = 14, .p2_fast = 14 },
384 };
385
386 /* Ironlake / Sandybridge
387 *
388 * We calculate clock using (register_value + 2) for N/M1/M2, so here
389 * the range value for them is (actual_value - 2).
390 */
391 static const intel_limit_t intel_limits_ironlake_dac = {
392 .dot = { .min = 25000, .max = 350000 },
393 .vco = { .min = 1760000, .max = 3510000 },
394 .n = { .min = 1, .max = 5 },
395 .m = { .min = 79, .max = 127 },
396 .m1 = { .min = 12, .max = 22 },
397 .m2 = { .min = 5, .max = 9 },
398 .p = { .min = 5, .max = 80 },
399 .p1 = { .min = 1, .max = 8 },
400 .p2 = { .dot_limit = 225000,
401 .p2_slow = 10, .p2_fast = 5 },
402 };
403
404 static const intel_limit_t intel_limits_ironlake_single_lvds = {
405 .dot = { .min = 25000, .max = 350000 },
406 .vco = { .min = 1760000, .max = 3510000 },
407 .n = { .min = 1, .max = 3 },
408 .m = { .min = 79, .max = 118 },
409 .m1 = { .min = 12, .max = 22 },
410 .m2 = { .min = 5, .max = 9 },
411 .p = { .min = 28, .max = 112 },
412 .p1 = { .min = 2, .max = 8 },
413 .p2 = { .dot_limit = 225000,
414 .p2_slow = 14, .p2_fast = 14 },
415 };
416
417 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
418 .dot = { .min = 25000, .max = 350000 },
419 .vco = { .min = 1760000, .max = 3510000 },
420 .n = { .min = 1, .max = 3 },
421 .m = { .min = 79, .max = 127 },
422 .m1 = { .min = 12, .max = 22 },
423 .m2 = { .min = 5, .max = 9 },
424 .p = { .min = 14, .max = 56 },
425 .p1 = { .min = 2, .max = 8 },
426 .p2 = { .dot_limit = 225000,
427 .p2_slow = 7, .p2_fast = 7 },
428 };
429
430 /* LVDS 100mhz refclk limits. */
431 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
432 .dot = { .min = 25000, .max = 350000 },
433 .vco = { .min = 1760000, .max = 3510000 },
434 .n = { .min = 1, .max = 2 },
435 .m = { .min = 79, .max = 126 },
436 .m1 = { .min = 12, .max = 22 },
437 .m2 = { .min = 5, .max = 9 },
438 .p = { .min = 28, .max = 112 },
439 .p1 = { .min = 2, .max = 8 },
440 .p2 = { .dot_limit = 225000,
441 .p2_slow = 14, .p2_fast = 14 },
442 };
443
444 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
445 .dot = { .min = 25000, .max = 350000 },
446 .vco = { .min = 1760000, .max = 3510000 },
447 .n = { .min = 1, .max = 3 },
448 .m = { .min = 79, .max = 126 },
449 .m1 = { .min = 12, .max = 22 },
450 .m2 = { .min = 5, .max = 9 },
451 .p = { .min = 14, .max = 42 },
452 .p1 = { .min = 2, .max = 6 },
453 .p2 = { .dot_limit = 225000,
454 .p2_slow = 7, .p2_fast = 7 },
455 };
456
457 static const intel_limit_t intel_limits_vlv = {
458 /*
459 * These are the data rate limits (measured in fast clocks)
460 * since those are the strictest limits we have. The fast
461 * clock and actual rate limits are more relaxed, so checking
462 * them would make no difference.
463 */
464 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
465 .vco = { .min = 4000000, .max = 6000000 },
466 .n = { .min = 1, .max = 7 },
467 .m1 = { .min = 2, .max = 3 },
468 .m2 = { .min = 11, .max = 156 },
469 .p1 = { .min = 2, .max = 3 },
470 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
471 };
472
473 static const intel_limit_t intel_limits_chv = {
474 /*
475 * These are the data rate limits (measured in fast clocks)
476 * since those are the strictest limits we have. The fast
477 * clock and actual rate limits are more relaxed, so checking
478 * them would make no difference.
479 */
480 .dot = { .min = 25000 * 5, .max = 540000 * 5},
481 .vco = { .min = 4800000, .max = 6480000 },
482 .n = { .min = 1, .max = 1 },
483 .m1 = { .min = 2, .max = 2 },
484 .m2 = { .min = 24 << 22, .max = 175 << 22 },
485 .p1 = { .min = 2, .max = 4 },
486 .p2 = { .p2_slow = 1, .p2_fast = 14 },
487 };
488
489 static const intel_limit_t intel_limits_bxt = {
490 /* FIXME: find real dot limits */
491 .dot = { .min = 0, .max = INT_MAX },
492 .vco = { .min = 4800000, .max = 6700000 },
493 .n = { .min = 1, .max = 1 },
494 .m1 = { .min = 2, .max = 2 },
495 /* FIXME: find real m2 limits */
496 .m2 = { .min = 2 << 22, .max = 255 << 22 },
497 .p1 = { .min = 2, .max = 4 },
498 .p2 = { .p2_slow = 1, .p2_fast = 20 },
499 };
500
501 static bool
502 needs_modeset(struct drm_crtc_state *state)
503 {
504 return drm_atomic_crtc_needs_modeset(state);
505 }
506
507 /**
508 * Returns whether any output on the specified pipe is of the specified type
509 */
510 bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
511 {
512 struct drm_device *dev = crtc->base.dev;
513 struct intel_encoder *encoder;
514
515 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
516 if (encoder->type == type)
517 return true;
518
519 return false;
520 }
521
522 /**
523 * Returns whether any output on the specified pipe will have the specified
524 * type after a staged modeset is complete, i.e., the same as
525 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
526 * encoder->crtc.
527 */
528 static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
529 int type)
530 {
531 struct drm_atomic_state *state = crtc_state->base.state;
532 struct drm_connector *connector;
533 struct drm_connector_state *connector_state;
534 struct intel_encoder *encoder;
535 int i, num_connectors = 0;
536
537 for_each_connector_in_state(state, connector, connector_state, i) {
538 if (connector_state->crtc != crtc_state->base.crtc)
539 continue;
540
541 num_connectors++;
542
543 encoder = to_intel_encoder(connector_state->best_encoder);
544 if (encoder->type == type)
545 return true;
546 }
547
548 WARN_ON(num_connectors == 0);
549
550 return false;
551 }
552
553 static const intel_limit_t *
554 intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
555 {
556 struct drm_device *dev = crtc_state->base.crtc->dev;
557 const intel_limit_t *limit;
558
559 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
560 if (intel_is_dual_link_lvds(dev)) {
561 if (refclk == 100000)
562 limit = &intel_limits_ironlake_dual_lvds_100m;
563 else
564 limit = &intel_limits_ironlake_dual_lvds;
565 } else {
566 if (refclk == 100000)
567 limit = &intel_limits_ironlake_single_lvds_100m;
568 else
569 limit = &intel_limits_ironlake_single_lvds;
570 }
571 } else
572 limit = &intel_limits_ironlake_dac;
573
574 return limit;
575 }
576
577 static const intel_limit_t *
578 intel_g4x_limit(struct intel_crtc_state *crtc_state)
579 {
580 struct drm_device *dev = crtc_state->base.crtc->dev;
581 const intel_limit_t *limit;
582
583 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
584 if (intel_is_dual_link_lvds(dev))
585 limit = &intel_limits_g4x_dual_channel_lvds;
586 else
587 limit = &intel_limits_g4x_single_channel_lvds;
588 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
589 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
590 limit = &intel_limits_g4x_hdmi;
591 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
592 limit = &intel_limits_g4x_sdvo;
593 } else /* The option is for other outputs */
594 limit = &intel_limits_i9xx_sdvo;
595
596 return limit;
597 }
598
599 static const intel_limit_t *
600 intel_limit(struct intel_crtc_state *crtc_state, int refclk)
601 {
602 struct drm_device *dev = crtc_state->base.crtc->dev;
603 const intel_limit_t *limit;
604
605 if (IS_BROXTON(dev))
606 limit = &intel_limits_bxt;
607 else if (HAS_PCH_SPLIT(dev))
608 limit = intel_ironlake_limit(crtc_state, refclk);
609 else if (IS_G4X(dev)) {
610 limit = intel_g4x_limit(crtc_state);
611 } else if (IS_PINEVIEW(dev)) {
612 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
613 limit = &intel_limits_pineview_lvds;
614 else
615 limit = &intel_limits_pineview_sdvo;
616 } else if (IS_CHERRYVIEW(dev)) {
617 limit = &intel_limits_chv;
618 } else if (IS_VALLEYVIEW(dev)) {
619 limit = &intel_limits_vlv;
620 } else if (!IS_GEN2(dev)) {
621 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
622 limit = &intel_limits_i9xx_lvds;
623 else
624 limit = &intel_limits_i9xx_sdvo;
625 } else {
626 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
627 limit = &intel_limits_i8xx_lvds;
628 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
629 limit = &intel_limits_i8xx_dvo;
630 else
631 limit = &intel_limits_i8xx_dac;
632 }
633 return limit;
634 }
635
636 /*
637 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
638 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
639 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
640 * The helpers' return value is the rate of the clock that is fed to the
641 * display engine's pipe which can be the above fast dot clock rate or a
642 * divided-down version of it.
643 */
644 /* m1 is reserved as 0 in Pineview, n is a ring counter */
645 static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
646 {
647 clock->m = clock->m2 + 2;
648 clock->p = clock->p1 * clock->p2;
649 if (WARN_ON(clock->n == 0 || clock->p == 0))
650 return 0;
651 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
652 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
653
654 return clock->dot;
655 }
656
657 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
658 {
659 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
660 }
661
662 static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
663 {
664 clock->m = i9xx_dpll_compute_m(clock);
665 clock->p = clock->p1 * clock->p2;
666 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
667 return 0;
668 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
669 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
670
671 return clock->dot;
672 }
673
674 static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
675 {
676 clock->m = clock->m1 * clock->m2;
677 clock->p = clock->p1 * clock->p2;
678 if (WARN_ON(clock->n == 0 || clock->p == 0))
679 return 0;
680 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
681 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
682
683 return clock->dot / 5;
684 }
685
686 int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
687 {
688 clock->m = clock->m1 * clock->m2;
689 clock->p = clock->p1 * clock->p2;
690 if (WARN_ON(clock->n == 0 || clock->p == 0))
691 return 0;
692 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
693 clock->n << 22);
694 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
695
696 return clock->dot / 5;
697 }
698
699 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
700 /**
701 * Returns whether the given set of divisors are valid for a given refclk with
702 * the given connectors.
703 */
704
705 static bool intel_PLL_is_valid(struct drm_device *dev,
706 const intel_limit_t *limit,
707 const intel_clock_t *clock)
708 {
709 if (clock->n < limit->n.min || limit->n.max < clock->n)
710 INTELPllInvalid("n out of range\n");
711 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
712 INTELPllInvalid("p1 out of range\n");
713 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
714 INTELPllInvalid("m2 out of range\n");
715 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
716 INTELPllInvalid("m1 out of range\n");
717
718 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) &&
719 !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev))
720 if (clock->m1 <= clock->m2)
721 INTELPllInvalid("m1 <= m2\n");
722
723 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && !IS_BROXTON(dev)) {
724 if (clock->p < limit->p.min || limit->p.max < clock->p)
725 INTELPllInvalid("p out of range\n");
726 if (clock->m < limit->m.min || limit->m.max < clock->m)
727 INTELPllInvalid("m out of range\n");
728 }
729
730 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
731 INTELPllInvalid("vco out of range\n");
732 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
733 * connector, etc., rather than just a single range.
734 */
735 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
736 INTELPllInvalid("dot out of range\n");
737
738 return true;
739 }
740
741 static int
742 i9xx_select_p2_div(const intel_limit_t *limit,
743 const struct intel_crtc_state *crtc_state,
744 int target)
745 {
746 struct drm_device *dev = crtc_state->base.crtc->dev;
747
748 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
749 /*
750 * For LVDS just rely on its current settings for dual-channel.
751 * We haven't figured out how to reliably set up different
752 * single/dual channel state, if we even can.
753 */
754 if (intel_is_dual_link_lvds(dev))
755 return limit->p2.p2_fast;
756 else
757 return limit->p2.p2_slow;
758 } else {
759 if (target < limit->p2.dot_limit)
760 return limit->p2.p2_slow;
761 else
762 return limit->p2.p2_fast;
763 }
764 }
765
766 static bool
767 i9xx_find_best_dpll(const intel_limit_t *limit,
768 struct intel_crtc_state *crtc_state,
769 int target, int refclk, intel_clock_t *match_clock,
770 intel_clock_t *best_clock)
771 {
772 struct drm_device *dev = crtc_state->base.crtc->dev;
773 intel_clock_t clock;
774 int err = target;
775
776 memset(best_clock, 0, sizeof(*best_clock));
777
778 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
779
780 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
781 clock.m1++) {
782 for (clock.m2 = limit->m2.min;
783 clock.m2 <= limit->m2.max; clock.m2++) {
784 if (clock.m2 >= clock.m1)
785 break;
786 for (clock.n = limit->n.min;
787 clock.n <= limit->n.max; clock.n++) {
788 for (clock.p1 = limit->p1.min;
789 clock.p1 <= limit->p1.max; clock.p1++) {
790 int this_err;
791
792 i9xx_calc_dpll_params(refclk, &clock);
793 if (!intel_PLL_is_valid(dev, limit,
794 &clock))
795 continue;
796 if (match_clock &&
797 clock.p != match_clock->p)
798 continue;
799
800 this_err = abs(clock.dot - target);
801 if (this_err < err) {
802 *best_clock = clock;
803 err = this_err;
804 }
805 }
806 }
807 }
808 }
809
810 return (err != target);
811 }
812
813 static bool
814 pnv_find_best_dpll(const intel_limit_t *limit,
815 struct intel_crtc_state *crtc_state,
816 int target, int refclk, intel_clock_t *match_clock,
817 intel_clock_t *best_clock)
818 {
819 struct drm_device *dev = crtc_state->base.crtc->dev;
820 intel_clock_t clock;
821 int err = target;
822
823 memset(best_clock, 0, sizeof(*best_clock));
824
825 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
826
827 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
828 clock.m1++) {
829 for (clock.m2 = limit->m2.min;
830 clock.m2 <= limit->m2.max; clock.m2++) {
831 for (clock.n = limit->n.min;
832 clock.n <= limit->n.max; clock.n++) {
833 for (clock.p1 = limit->p1.min;
834 clock.p1 <= limit->p1.max; clock.p1++) {
835 int this_err;
836
837 pnv_calc_dpll_params(refclk, &clock);
838 if (!intel_PLL_is_valid(dev, limit,
839 &clock))
840 continue;
841 if (match_clock &&
842 clock.p != match_clock->p)
843 continue;
844
845 this_err = abs(clock.dot - target);
846 if (this_err < err) {
847 *best_clock = clock;
848 err = this_err;
849 }
850 }
851 }
852 }
853 }
854
855 return (err != target);
856 }
857
858 static bool
859 g4x_find_best_dpll(const intel_limit_t *limit,
860 struct intel_crtc_state *crtc_state,
861 int target, int refclk, intel_clock_t *match_clock,
862 intel_clock_t *best_clock)
863 {
864 struct drm_device *dev = crtc_state->base.crtc->dev;
865 intel_clock_t clock;
866 int max_n;
867 bool found = false;
868 /* approximately equals target * 0.00585 */
869 int err_most = (target >> 8) + (target >> 9);
870
871 memset(best_clock, 0, sizeof(*best_clock));
872
873 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
874
875 max_n = limit->n.max;
876 /* based on hardware requirement, prefer smaller n to precision */
877 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
878 /* based on hardware requirement, prefere larger m1,m2 */
879 for (clock.m1 = limit->m1.max;
880 clock.m1 >= limit->m1.min; clock.m1--) {
881 for (clock.m2 = limit->m2.max;
882 clock.m2 >= limit->m2.min; clock.m2--) {
883 for (clock.p1 = limit->p1.max;
884 clock.p1 >= limit->p1.min; clock.p1--) {
885 int this_err;
886
887 i9xx_calc_dpll_params(refclk, &clock);
888 if (!intel_PLL_is_valid(dev, limit,
889 &clock))
890 continue;
891
892 this_err = abs(clock.dot - target);
893 if (this_err < err_most) {
894 *best_clock = clock;
895 err_most = this_err;
896 max_n = clock.n;
897 found = true;
898 }
899 }
900 }
901 }
902 }
903 return found;
904 }
905
906 /*
907 * Check if the calculated PLL configuration is more optimal compared to the
908 * best configuration and error found so far. Return the calculated error.
909 */
910 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
911 const intel_clock_t *calculated_clock,
912 const intel_clock_t *best_clock,
913 unsigned int best_error_ppm,
914 unsigned int *error_ppm)
915 {
916 /*
917 * For CHV ignore the error and consider only the P value.
918 * Prefer a bigger P value based on HW requirements.
919 */
920 if (IS_CHERRYVIEW(dev)) {
921 *error_ppm = 0;
922
923 return calculated_clock->p > best_clock->p;
924 }
925
926 if (WARN_ON_ONCE(!target_freq))
927 return false;
928
929 *error_ppm = div_u64(1000000ULL *
930 abs(target_freq - calculated_clock->dot),
931 target_freq);
932 /*
933 * Prefer a better P value over a better (smaller) error if the error
934 * is small. Ensure this preference for future configurations too by
935 * setting the error to 0.
936 */
937 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
938 *error_ppm = 0;
939
940 return true;
941 }
942
943 return *error_ppm + 10 < best_error_ppm;
944 }
945
946 static bool
947 vlv_find_best_dpll(const intel_limit_t *limit,
948 struct intel_crtc_state *crtc_state,
949 int target, int refclk, intel_clock_t *match_clock,
950 intel_clock_t *best_clock)
951 {
952 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
953 struct drm_device *dev = crtc->base.dev;
954 intel_clock_t clock;
955 unsigned int bestppm = 1000000;
956 /* min update 19.2 MHz */
957 int max_n = min(limit->n.max, refclk / 19200);
958 bool found = false;
959
960 target *= 5; /* fast clock */
961
962 memset(best_clock, 0, sizeof(*best_clock));
963
964 /* based on hardware requirement, prefer smaller n to precision */
965 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
966 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
967 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
968 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
969 clock.p = clock.p1 * clock.p2;
970 /* based on hardware requirement, prefer bigger m1,m2 values */
971 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
972 unsigned int ppm;
973
974 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
975 refclk * clock.m1);
976
977 vlv_calc_dpll_params(refclk, &clock);
978
979 if (!intel_PLL_is_valid(dev, limit,
980 &clock))
981 continue;
982
983 if (!vlv_PLL_is_optimal(dev, target,
984 &clock,
985 best_clock,
986 bestppm, &ppm))
987 continue;
988
989 *best_clock = clock;
990 bestppm = ppm;
991 found = true;
992 }
993 }
994 }
995 }
996
997 return found;
998 }
999
1000 static bool
1001 chv_find_best_dpll(const intel_limit_t *limit,
1002 struct intel_crtc_state *crtc_state,
1003 int target, int refclk, intel_clock_t *match_clock,
1004 intel_clock_t *best_clock)
1005 {
1006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1007 struct drm_device *dev = crtc->base.dev;
1008 unsigned int best_error_ppm;
1009 intel_clock_t clock;
1010 uint64_t m2;
1011 int found = false;
1012
1013 memset(best_clock, 0, sizeof(*best_clock));
1014 best_error_ppm = 1000000;
1015
1016 /*
1017 * Based on hardware doc, the n always set to 1, and m1 always
1018 * set to 2. If requires to support 200Mhz refclk, we need to
1019 * revisit this because n may not 1 anymore.
1020 */
1021 clock.n = 1, clock.m1 = 2;
1022 target *= 5; /* fast clock */
1023
1024 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
1025 for (clock.p2 = limit->p2.p2_fast;
1026 clock.p2 >= limit->p2.p2_slow;
1027 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
1028 unsigned int error_ppm;
1029
1030 clock.p = clock.p1 * clock.p2;
1031
1032 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
1033 clock.n) << 22, refclk * clock.m1);
1034
1035 if (m2 > INT_MAX/clock.m1)
1036 continue;
1037
1038 clock.m2 = m2;
1039
1040 chv_calc_dpll_params(refclk, &clock);
1041
1042 if (!intel_PLL_is_valid(dev, limit, &clock))
1043 continue;
1044
1045 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
1046 best_error_ppm, &error_ppm))
1047 continue;
1048
1049 *best_clock = clock;
1050 best_error_ppm = error_ppm;
1051 found = true;
1052 }
1053 }
1054
1055 return found;
1056 }
1057
1058 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
1059 intel_clock_t *best_clock)
1060 {
1061 int refclk = i9xx_get_refclk(crtc_state, 0);
1062
1063 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
1064 target_clock, refclk, NULL, best_clock);
1065 }
1066
1067 bool intel_crtc_active(struct drm_crtc *crtc)
1068 {
1069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1070
1071 /* Be paranoid as we can arrive here with only partial
1072 * state retrieved from the hardware during setup.
1073 *
1074 * We can ditch the adjusted_mode.crtc_clock check as soon
1075 * as Haswell has gained clock readout/fastboot support.
1076 *
1077 * We can ditch the crtc->primary->fb check as soon as we can
1078 * properly reconstruct framebuffers.
1079 *
1080 * FIXME: The intel_crtc->active here should be switched to
1081 * crtc->state->active once we have proper CRTC states wired up
1082 * for atomic.
1083 */
1084 return intel_crtc->active && crtc->primary->state->fb &&
1085 intel_crtc->config->base.adjusted_mode.crtc_clock;
1086 }
1087
1088 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1089 enum pipe pipe)
1090 {
1091 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1092 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1093
1094 return intel_crtc->config->cpu_transcoder;
1095 }
1096
1097 static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1098 {
1099 struct drm_i915_private *dev_priv = dev->dev_private;
1100 i915_reg_t reg = PIPEDSL(pipe);
1101 u32 line1, line2;
1102 u32 line_mask;
1103
1104 if (IS_GEN2(dev))
1105 line_mask = DSL_LINEMASK_GEN2;
1106 else
1107 line_mask = DSL_LINEMASK_GEN3;
1108
1109 line1 = I915_READ(reg) & line_mask;
1110 msleep(5);
1111 line2 = I915_READ(reg) & line_mask;
1112
1113 return line1 == line2;
1114 }
1115
1116 /*
1117 * intel_wait_for_pipe_off - wait for pipe to turn off
1118 * @crtc: crtc whose pipe to wait for
1119 *
1120 * After disabling a pipe, we can't wait for vblank in the usual way,
1121 * spinning on the vblank interrupt status bit, since we won't actually
1122 * see an interrupt when the pipe is disabled.
1123 *
1124 * On Gen4 and above:
1125 * wait for the pipe register state bit to turn off
1126 *
1127 * Otherwise:
1128 * wait for the display line value to settle (it usually
1129 * ends up stopping at the start of the next frame).
1130 *
1131 */
1132 static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
1133 {
1134 struct drm_device *dev = crtc->base.dev;
1135 struct drm_i915_private *dev_priv = dev->dev_private;
1136 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
1137 enum pipe pipe = crtc->pipe;
1138
1139 if (INTEL_INFO(dev)->gen >= 4) {
1140 i915_reg_t reg = PIPECONF(cpu_transcoder);
1141
1142 /* Wait for the Pipe State to go off */
1143 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1144 100))
1145 WARN(1, "pipe_off wait timed out\n");
1146 } else {
1147 /* Wait for the display line to settle */
1148 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
1149 WARN(1, "pipe_off wait timed out\n");
1150 }
1151 }
1152
1153 static const char *state_string(bool enabled)
1154 {
1155 return enabled ? "on" : "off";
1156 }
1157
1158 /* Only for pre-ILK configs */
1159 void assert_pll(struct drm_i915_private *dev_priv,
1160 enum pipe pipe, bool state)
1161 {
1162 u32 val;
1163 bool cur_state;
1164
1165 val = I915_READ(DPLL(pipe));
1166 cur_state = !!(val & DPLL_VCO_ENABLE);
1167 I915_STATE_WARN(cur_state != state,
1168 "PLL state assertion failure (expected %s, current %s)\n",
1169 state_string(state), state_string(cur_state));
1170 }
1171
1172 /* XXX: the dsi pll is shared between MIPI DSI ports */
1173 static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1174 {
1175 u32 val;
1176 bool cur_state;
1177
1178 mutex_lock(&dev_priv->sb_lock);
1179 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1180 mutex_unlock(&dev_priv->sb_lock);
1181
1182 cur_state = val & DSI_PLL_VCO_EN;
1183 I915_STATE_WARN(cur_state != state,
1184 "DSI PLL state assertion failure (expected %s, current %s)\n",
1185 state_string(state), state_string(cur_state));
1186 }
1187 #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1188 #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1189
1190 struct intel_shared_dpll *
1191 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1192 {
1193 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1194
1195 if (crtc->config->shared_dpll < 0)
1196 return NULL;
1197
1198 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
1199 }
1200
1201 /* For ILK+ */
1202 void assert_shared_dpll(struct drm_i915_private *dev_priv,
1203 struct intel_shared_dpll *pll,
1204 bool state)
1205 {
1206 bool cur_state;
1207 struct intel_dpll_hw_state hw_state;
1208
1209 if (WARN (!pll,
1210 "asserting DPLL %s with no DPLL\n", state_string(state)))
1211 return;
1212
1213 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
1214 I915_STATE_WARN(cur_state != state,
1215 "%s assertion failure (expected %s, current %s)\n",
1216 pll->name, state_string(state), state_string(cur_state));
1217 }
1218
1219 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1220 enum pipe pipe, bool state)
1221 {
1222 bool cur_state;
1223 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1224 pipe);
1225
1226 if (HAS_DDI(dev_priv->dev)) {
1227 /* DDI does not have a specific FDI_TX register */
1228 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1229 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1230 } else {
1231 u32 val = I915_READ(FDI_TX_CTL(pipe));
1232 cur_state = !!(val & FDI_TX_ENABLE);
1233 }
1234 I915_STATE_WARN(cur_state != state,
1235 "FDI TX state assertion failure (expected %s, current %s)\n",
1236 state_string(state), state_string(cur_state));
1237 }
1238 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1239 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1240
1241 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, bool state)
1243 {
1244 u32 val;
1245 bool cur_state;
1246
1247 val = I915_READ(FDI_RX_CTL(pipe));
1248 cur_state = !!(val & FDI_RX_ENABLE);
1249 I915_STATE_WARN(cur_state != state,
1250 "FDI RX state assertion failure (expected %s, current %s)\n",
1251 state_string(state), state_string(cur_state));
1252 }
1253 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1254 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1255
1256 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe)
1258 {
1259 u32 val;
1260
1261 /* ILK FDI PLL is always enabled */
1262 if (INTEL_INFO(dev_priv->dev)->gen == 5)
1263 return;
1264
1265 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1266 if (HAS_DDI(dev_priv->dev))
1267 return;
1268
1269 val = I915_READ(FDI_TX_CTL(pipe));
1270 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1271 }
1272
1273 void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, bool state)
1275 {
1276 u32 val;
1277 bool cur_state;
1278
1279 val = I915_READ(FDI_RX_CTL(pipe));
1280 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1281 I915_STATE_WARN(cur_state != state,
1282 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1283 state_string(state), state_string(cur_state));
1284 }
1285
1286 void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1287 enum pipe pipe)
1288 {
1289 struct drm_device *dev = dev_priv->dev;
1290 i915_reg_t pp_reg;
1291 u32 val;
1292 enum pipe panel_pipe = PIPE_A;
1293 bool locked = true;
1294
1295 if (WARN_ON(HAS_DDI(dev)))
1296 return;
1297
1298 if (HAS_PCH_SPLIT(dev)) {
1299 u32 port_sel;
1300
1301 pp_reg = PCH_PP_CONTROL;
1302 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1303
1304 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1305 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1306 panel_pipe = PIPE_B;
1307 /* XXX: else fix for eDP */
1308 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1309 /* presumably write lock depends on pipe, not port select */
1310 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1311 panel_pipe = pipe;
1312 } else {
1313 pp_reg = PP_CONTROL;
1314 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1315 panel_pipe = PIPE_B;
1316 }
1317
1318 val = I915_READ(pp_reg);
1319 if (!(val & PANEL_POWER_ON) ||
1320 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
1321 locked = false;
1322
1323 I915_STATE_WARN(panel_pipe == pipe && locked,
1324 "panel assertion failure, pipe %c regs locked\n",
1325 pipe_name(pipe));
1326 }
1327
1328 static void assert_cursor(struct drm_i915_private *dev_priv,
1329 enum pipe pipe, bool state)
1330 {
1331 struct drm_device *dev = dev_priv->dev;
1332 bool cur_state;
1333
1334 if (IS_845G(dev) || IS_I865G(dev))
1335 cur_state = I915_READ(CURCNTR(PIPE_A)) & CURSOR_ENABLE;
1336 else
1337 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1338
1339 I915_STATE_WARN(cur_state != state,
1340 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1341 pipe_name(pipe), state_string(state), state_string(cur_state));
1342 }
1343 #define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1344 #define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1345
1346 void assert_pipe(struct drm_i915_private *dev_priv,
1347 enum pipe pipe, bool state)
1348 {
1349 bool cur_state;
1350 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1351 pipe);
1352
1353 /* if we need the pipe quirk it must be always on */
1354 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1355 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1356 state = true;
1357
1358 if (!intel_display_power_is_enabled(dev_priv,
1359 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1360 cur_state = false;
1361 } else {
1362 u32 val = I915_READ(PIPECONF(cpu_transcoder));
1363 cur_state = !!(val & PIPECONF_ENABLE);
1364 }
1365
1366 I915_STATE_WARN(cur_state != state,
1367 "pipe %c assertion failure (expected %s, current %s)\n",
1368 pipe_name(pipe), state_string(state), state_string(cur_state));
1369 }
1370
1371 static void assert_plane(struct drm_i915_private *dev_priv,
1372 enum plane plane, bool state)
1373 {
1374 u32 val;
1375 bool cur_state;
1376
1377 val = I915_READ(DSPCNTR(plane));
1378 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1379 I915_STATE_WARN(cur_state != state,
1380 "plane %c assertion failure (expected %s, current %s)\n",
1381 plane_name(plane), state_string(state), state_string(cur_state));
1382 }
1383
1384 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1385 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1386
1387 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe)
1389 {
1390 struct drm_device *dev = dev_priv->dev;
1391 int i;
1392
1393 /* Primary planes are fixed to pipes on gen4+ */
1394 if (INTEL_INFO(dev)->gen >= 4) {
1395 u32 val = I915_READ(DSPCNTR(pipe));
1396 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
1397 "plane %c assertion failure, should be disabled but not\n",
1398 plane_name(pipe));
1399 return;
1400 }
1401
1402 /* Need to check both planes against the pipe */
1403 for_each_pipe(dev_priv, i) {
1404 u32 val = I915_READ(DSPCNTR(i));
1405 enum pipe cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1406 DISPPLANE_SEL_PIPE_SHIFT;
1407 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1408 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1409 plane_name(i), pipe_name(pipe));
1410 }
1411 }
1412
1413 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1414 enum pipe pipe)
1415 {
1416 struct drm_device *dev = dev_priv->dev;
1417 int sprite;
1418
1419 if (INTEL_INFO(dev)->gen >= 9) {
1420 for_each_sprite(dev_priv, pipe, sprite) {
1421 u32 val = I915_READ(PLANE_CTL(pipe, sprite));
1422 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
1423 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1424 sprite, pipe_name(pipe));
1425 }
1426 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
1427 for_each_sprite(dev_priv, pipe, sprite) {
1428 u32 val = I915_READ(SPCNTR(pipe, sprite));
1429 I915_STATE_WARN(val & SP_ENABLE,
1430 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1431 sprite_name(pipe, sprite), pipe_name(pipe));
1432 }
1433 } else if (INTEL_INFO(dev)->gen >= 7) {
1434 u32 val = I915_READ(SPRCTL(pipe));
1435 I915_STATE_WARN(val & SPRITE_ENABLE,
1436 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1437 plane_name(pipe), pipe_name(pipe));
1438 } else if (INTEL_INFO(dev)->gen >= 5) {
1439 u32 val = I915_READ(DVSCNTR(pipe));
1440 I915_STATE_WARN(val & DVS_ENABLE,
1441 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1442 plane_name(pipe), pipe_name(pipe));
1443 }
1444 }
1445
1446 static void assert_vblank_disabled(struct drm_crtc *crtc)
1447 {
1448 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
1449 drm_crtc_vblank_put(crtc);
1450 }
1451
1452 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1453 {
1454 u32 val;
1455 bool enabled;
1456
1457 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
1458
1459 val = I915_READ(PCH_DREF_CONTROL);
1460 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1461 DREF_SUPERSPREAD_SOURCE_MASK));
1462 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1463 }
1464
1465 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1466 enum pipe pipe)
1467 {
1468 u32 val;
1469 bool enabled;
1470
1471 val = I915_READ(PCH_TRANSCONF(pipe));
1472 enabled = !!(val & TRANS_ENABLE);
1473 I915_STATE_WARN(enabled,
1474 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1475 pipe_name(pipe));
1476 }
1477
1478 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1479 enum pipe pipe, u32 port_sel, u32 val)
1480 {
1481 if ((val & DP_PORT_EN) == 0)
1482 return false;
1483
1484 if (HAS_PCH_CPT(dev_priv->dev)) {
1485 u32 trans_dp_ctl = I915_READ(TRANS_DP_CTL(pipe));
1486 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1487 return false;
1488 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1489 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1490 return false;
1491 } else {
1492 if ((val & DP_PIPE_MASK) != (pipe << 30))
1493 return false;
1494 }
1495 return true;
1496 }
1497
1498 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1499 enum pipe pipe, u32 val)
1500 {
1501 if ((val & SDVO_ENABLE) == 0)
1502 return false;
1503
1504 if (HAS_PCH_CPT(dev_priv->dev)) {
1505 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1506 return false;
1507 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1508 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1509 return false;
1510 } else {
1511 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1512 return false;
1513 }
1514 return true;
1515 }
1516
1517 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1518 enum pipe pipe, u32 val)
1519 {
1520 if ((val & LVDS_PORT_EN) == 0)
1521 return false;
1522
1523 if (HAS_PCH_CPT(dev_priv->dev)) {
1524 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1525 return false;
1526 } else {
1527 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1528 return false;
1529 }
1530 return true;
1531 }
1532
1533 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1534 enum pipe pipe, u32 val)
1535 {
1536 if ((val & ADPA_DAC_ENABLE) == 0)
1537 return false;
1538 if (HAS_PCH_CPT(dev_priv->dev)) {
1539 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1540 return false;
1541 } else {
1542 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1543 return false;
1544 }
1545 return true;
1546 }
1547
1548 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, i915_reg_t reg,
1550 u32 port_sel)
1551 {
1552 u32 val = I915_READ(reg);
1553 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1554 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1555 i915_mmio_reg_offset(reg), pipe_name(pipe));
1556
1557 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1558 && (val & DP_PIPEB_SELECT),
1559 "IBX PCH dp port still using transcoder B\n");
1560 }
1561
1562 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1563 enum pipe pipe, i915_reg_t reg)
1564 {
1565 u32 val = I915_READ(reg);
1566 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1567 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1568 i915_mmio_reg_offset(reg), pipe_name(pipe));
1569
1570 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1571 && (val & SDVO_PIPE_B_SELECT),
1572 "IBX PCH hdmi port still using transcoder B\n");
1573 }
1574
1575 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1576 enum pipe pipe)
1577 {
1578 u32 val;
1579
1580 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1581 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1582 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1583
1584 val = I915_READ(PCH_ADPA);
1585 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1586 "PCH VGA enabled on transcoder %c, should be disabled\n",
1587 pipe_name(pipe));
1588
1589 val = I915_READ(PCH_LVDS);
1590 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1591 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1592 pipe_name(pipe));
1593
1594 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1595 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1596 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1597 }
1598
1599 static void vlv_enable_pll(struct intel_crtc *crtc,
1600 const struct intel_crtc_state *pipe_config)
1601 {
1602 struct drm_device *dev = crtc->base.dev;
1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604 i915_reg_t reg = DPLL(crtc->pipe);
1605 u32 dpll = pipe_config->dpll_hw_state.dpll;
1606
1607 assert_pipe_disabled(dev_priv, crtc->pipe);
1608
1609 /* PLL is protected by panel, make sure we can write it */
1610 if (IS_MOBILE(dev_priv->dev))
1611 assert_panel_unlocked(dev_priv, crtc->pipe);
1612
1613 I915_WRITE(reg, dpll);
1614 POSTING_READ(reg);
1615 udelay(150);
1616
1617 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1618 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1619
1620 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
1621 POSTING_READ(DPLL_MD(crtc->pipe));
1622
1623 /* We do this three times for luck */
1624 I915_WRITE(reg, dpll);
1625 POSTING_READ(reg);
1626 udelay(150); /* wait for warmup */
1627 I915_WRITE(reg, dpll);
1628 POSTING_READ(reg);
1629 udelay(150); /* wait for warmup */
1630 I915_WRITE(reg, dpll);
1631 POSTING_READ(reg);
1632 udelay(150); /* wait for warmup */
1633 }
1634
1635 static void chv_enable_pll(struct intel_crtc *crtc,
1636 const struct intel_crtc_state *pipe_config)
1637 {
1638 struct drm_device *dev = crtc->base.dev;
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640 int pipe = crtc->pipe;
1641 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1642 u32 tmp;
1643
1644 assert_pipe_disabled(dev_priv, crtc->pipe);
1645
1646 mutex_lock(&dev_priv->sb_lock);
1647
1648 /* Enable back the 10bit clock to display controller */
1649 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1650 tmp |= DPIO_DCLKP_EN;
1651 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1652
1653 mutex_unlock(&dev_priv->sb_lock);
1654
1655 /*
1656 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1657 */
1658 udelay(1);
1659
1660 /* Enable PLL */
1661 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
1662
1663 /* Check PLL is locked */
1664 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1665 DRM_ERROR("PLL %d failed to lock\n", pipe);
1666
1667 /* not sure when this should be written */
1668 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
1669 POSTING_READ(DPLL_MD(pipe));
1670 }
1671
1672 static int intel_num_dvo_pipes(struct drm_device *dev)
1673 {
1674 struct intel_crtc *crtc;
1675 int count = 0;
1676
1677 for_each_intel_crtc(dev, crtc)
1678 count += crtc->base.state->active &&
1679 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1680
1681 return count;
1682 }
1683
1684 static void i9xx_enable_pll(struct intel_crtc *crtc)
1685 {
1686 struct drm_device *dev = crtc->base.dev;
1687 struct drm_i915_private *dev_priv = dev->dev_private;
1688 i915_reg_t reg = DPLL(crtc->pipe);
1689 u32 dpll = crtc->config->dpll_hw_state.dpll;
1690
1691 assert_pipe_disabled(dev_priv, crtc->pipe);
1692
1693 /* No really, not for ILK+ */
1694 BUG_ON(INTEL_INFO(dev)->gen >= 5);
1695
1696 /* PLL is protected by panel, make sure we can write it */
1697 if (IS_MOBILE(dev) && !IS_I830(dev))
1698 assert_panel_unlocked(dev_priv, crtc->pipe);
1699
1700 /* Enable DVO 2x clock on both PLLs if necessary */
1701 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1702 /*
1703 * It appears to be important that we don't enable this
1704 * for the current pipe before otherwise configuring the
1705 * PLL. No idea how this should be handled if multiple
1706 * DVO outputs are enabled simultaneosly.
1707 */
1708 dpll |= DPLL_DVO_2X_MODE;
1709 I915_WRITE(DPLL(!crtc->pipe),
1710 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1711 }
1712
1713 /*
1714 * Apparently we need to have VGA mode enabled prior to changing
1715 * the P1/P2 dividers. Otherwise the DPLL will keep using the old
1716 * dividers, even though the register value does change.
1717 */
1718 I915_WRITE(reg, 0);
1719
1720 I915_WRITE(reg, dpll);
1721
1722 /* Wait for the clocks to stabilize. */
1723 POSTING_READ(reg);
1724 udelay(150);
1725
1726 if (INTEL_INFO(dev)->gen >= 4) {
1727 I915_WRITE(DPLL_MD(crtc->pipe),
1728 crtc->config->dpll_hw_state.dpll_md);
1729 } else {
1730 /* The pixel multiplier can only be updated once the
1731 * DPLL is enabled and the clocks are stable.
1732 *
1733 * So write it again.
1734 */
1735 I915_WRITE(reg, dpll);
1736 }
1737
1738 /* We do this three times for luck */
1739 I915_WRITE(reg, dpll);
1740 POSTING_READ(reg);
1741 udelay(150); /* wait for warmup */
1742 I915_WRITE(reg, dpll);
1743 POSTING_READ(reg);
1744 udelay(150); /* wait for warmup */
1745 I915_WRITE(reg, dpll);
1746 POSTING_READ(reg);
1747 udelay(150); /* wait for warmup */
1748 }
1749
1750 /**
1751 * i9xx_disable_pll - disable a PLL
1752 * @dev_priv: i915 private structure
1753 * @pipe: pipe PLL to disable
1754 *
1755 * Disable the PLL for @pipe, making sure the pipe is off first.
1756 *
1757 * Note! This is for pre-ILK only.
1758 */
1759 static void i9xx_disable_pll(struct intel_crtc *crtc)
1760 {
1761 struct drm_device *dev = crtc->base.dev;
1762 struct drm_i915_private *dev_priv = dev->dev_private;
1763 enum pipe pipe = crtc->pipe;
1764
1765 /* Disable DVO 2x clock on both PLLs if necessary */
1766 if (IS_I830(dev) &&
1767 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1768 !intel_num_dvo_pipes(dev)) {
1769 I915_WRITE(DPLL(PIPE_B),
1770 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1771 I915_WRITE(DPLL(PIPE_A),
1772 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1773 }
1774
1775 /* Don't disable pipe or pipe PLLs if needed */
1776 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1777 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
1778 return;
1779
1780 /* Make sure the pipe isn't still relying on us */
1781 assert_pipe_disabled(dev_priv, pipe);
1782
1783 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
1784 POSTING_READ(DPLL(pipe));
1785 }
1786
1787 static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1788 {
1789 u32 val;
1790
1791 /* Make sure the pipe isn't still relying on us */
1792 assert_pipe_disabled(dev_priv, pipe);
1793
1794 /*
1795 * Leave integrated clock source and reference clock enabled for pipe B.
1796 * The latter is needed for VGA hotplug / manual detection.
1797 */
1798 val = DPLL_VGA_MODE_DIS;
1799 if (pipe == PIPE_B)
1800 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
1801 I915_WRITE(DPLL(pipe), val);
1802 POSTING_READ(DPLL(pipe));
1803
1804 }
1805
1806 static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1807 {
1808 enum dpio_channel port = vlv_pipe_to_channel(pipe);
1809 u32 val;
1810
1811 /* Make sure the pipe isn't still relying on us */
1812 assert_pipe_disabled(dev_priv, pipe);
1813
1814 /* Set PLL en = 0 */
1815 val = DPLL_SSC_REF_CLK_CHV |
1816 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
1817 if (pipe != PIPE_A)
1818 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1819 I915_WRITE(DPLL(pipe), val);
1820 POSTING_READ(DPLL(pipe));
1821
1822 mutex_lock(&dev_priv->sb_lock);
1823
1824 /* Disable 10bit clock to display controller */
1825 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1826 val &= ~DPIO_DCLKP_EN;
1827 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1828
1829 mutex_unlock(&dev_priv->sb_lock);
1830 }
1831
1832 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1833 struct intel_digital_port *dport,
1834 unsigned int expected_mask)
1835 {
1836 u32 port_mask;
1837 i915_reg_t dpll_reg;
1838
1839 switch (dport->port) {
1840 case PORT_B:
1841 port_mask = DPLL_PORTB_READY_MASK;
1842 dpll_reg = DPLL(0);
1843 break;
1844 case PORT_C:
1845 port_mask = DPLL_PORTC_READY_MASK;
1846 dpll_reg = DPLL(0);
1847 expected_mask <<= 4;
1848 break;
1849 case PORT_D:
1850 port_mask = DPLL_PORTD_READY_MASK;
1851 dpll_reg = DPIO_PHY_STATUS;
1852 break;
1853 default:
1854 BUG();
1855 }
1856
1857 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1858 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1859 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
1860 }
1861
1862 static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1863 {
1864 struct drm_device *dev = crtc->base.dev;
1865 struct drm_i915_private *dev_priv = dev->dev_private;
1866 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1867
1868 if (WARN_ON(pll == NULL))
1869 return;
1870
1871 WARN_ON(!pll->config.crtc_mask);
1872 if (pll->active == 0) {
1873 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1874 WARN_ON(pll->on);
1875 assert_shared_dpll_disabled(dev_priv, pll);
1876
1877 pll->mode_set(dev_priv, pll);
1878 }
1879 }
1880
1881 /**
1882 * intel_enable_shared_dpll - enable PCH PLL
1883 * @dev_priv: i915 private structure
1884 * @pipe: pipe PLL to enable
1885 *
1886 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1887 * drives the transcoder clock.
1888 */
1889 static void intel_enable_shared_dpll(struct intel_crtc *crtc)
1890 {
1891 struct drm_device *dev = crtc->base.dev;
1892 struct drm_i915_private *dev_priv = dev->dev_private;
1893 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1894
1895 if (WARN_ON(pll == NULL))
1896 return;
1897
1898 if (WARN_ON(pll->config.crtc_mask == 0))
1899 return;
1900
1901 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
1902 pll->name, pll->active, pll->on,
1903 crtc->base.base.id);
1904
1905 if (pll->active++) {
1906 WARN_ON(!pll->on);
1907 assert_shared_dpll_enabled(dev_priv, pll);
1908 return;
1909 }
1910 WARN_ON(pll->on);
1911
1912 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1913
1914 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1915 pll->enable(dev_priv, pll);
1916 pll->on = true;
1917 }
1918
1919 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1920 {
1921 struct drm_device *dev = crtc->base.dev;
1922 struct drm_i915_private *dev_priv = dev->dev_private;
1923 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1924
1925 /* PCH only available on ILK+ */
1926 if (INTEL_INFO(dev)->gen < 5)
1927 return;
1928
1929 if (pll == NULL)
1930 return;
1931
1932 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
1933 return;
1934
1935 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1936 pll->name, pll->active, pll->on,
1937 crtc->base.base.id);
1938
1939 if (WARN_ON(pll->active == 0)) {
1940 assert_shared_dpll_disabled(dev_priv, pll);
1941 return;
1942 }
1943
1944 assert_shared_dpll_enabled(dev_priv, pll);
1945 WARN_ON(!pll->on);
1946 if (--pll->active)
1947 return;
1948
1949 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1950 pll->disable(dev_priv, pll);
1951 pll->on = false;
1952
1953 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
1954 }
1955
1956 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1957 enum pipe pipe)
1958 {
1959 struct drm_device *dev = dev_priv->dev;
1960 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1962 i915_reg_t reg;
1963 uint32_t val, pipeconf_val;
1964
1965 /* PCH only available on ILK+ */
1966 BUG_ON(!HAS_PCH_SPLIT(dev));
1967
1968 /* Make sure PCH DPLL is enabled */
1969 assert_shared_dpll_enabled(dev_priv,
1970 intel_crtc_to_shared_dpll(intel_crtc));
1971
1972 /* FDI must be feeding us bits for PCH ports */
1973 assert_fdi_tx_enabled(dev_priv, pipe);
1974 assert_fdi_rx_enabled(dev_priv, pipe);
1975
1976 if (HAS_PCH_CPT(dev)) {
1977 /* Workaround: Set the timing override bit before enabling the
1978 * pch transcoder. */
1979 reg = TRANS_CHICKEN2(pipe);
1980 val = I915_READ(reg);
1981 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1982 I915_WRITE(reg, val);
1983 }
1984
1985 reg = PCH_TRANSCONF(pipe);
1986 val = I915_READ(reg);
1987 pipeconf_val = I915_READ(PIPECONF(pipe));
1988
1989 if (HAS_PCH_IBX(dev_priv->dev)) {
1990 /*
1991 * Make the BPC in transcoder be consistent with
1992 * that in pipeconf reg. For HDMI we must use 8bpc
1993 * here for both 8bpc and 12bpc.
1994 */
1995 val &= ~PIPECONF_BPC_MASK;
1996 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
1997 val |= PIPECONF_8BPC;
1998 else
1999 val |= pipeconf_val & PIPECONF_BPC_MASK;
2000 }
2001
2002 val &= ~TRANS_INTERLACE_MASK;
2003 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
2004 if (HAS_PCH_IBX(dev_priv->dev) &&
2005 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
2006 val |= TRANS_LEGACY_INTERLACED_ILK;
2007 else
2008 val |= TRANS_INTERLACED;
2009 else
2010 val |= TRANS_PROGRESSIVE;
2011
2012 I915_WRITE(reg, val | TRANS_ENABLE);
2013 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2014 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
2015 }
2016
2017 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
2018 enum transcoder cpu_transcoder)
2019 {
2020 u32 val, pipeconf_val;
2021
2022 /* PCH only available on ILK+ */
2023 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
2024
2025 /* FDI must be feeding us bits for PCH ports */
2026 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
2027 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
2028
2029 /* Workaround: set timing override bit. */
2030 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2031 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2032 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2033
2034 val = TRANS_ENABLE;
2035 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
2036
2037 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2038 PIPECONF_INTERLACED_ILK)
2039 val |= TRANS_INTERLACED;
2040 else
2041 val |= TRANS_PROGRESSIVE;
2042
2043 I915_WRITE(LPT_TRANSCONF, val);
2044 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
2045 DRM_ERROR("Failed to enable PCH transcoder\n");
2046 }
2047
2048 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2049 enum pipe pipe)
2050 {
2051 struct drm_device *dev = dev_priv->dev;
2052 i915_reg_t reg;
2053 uint32_t val;
2054
2055 /* FDI relies on the transcoder */
2056 assert_fdi_tx_disabled(dev_priv, pipe);
2057 assert_fdi_rx_disabled(dev_priv, pipe);
2058
2059 /* Ports must be off as well */
2060 assert_pch_ports_disabled(dev_priv, pipe);
2061
2062 reg = PCH_TRANSCONF(pipe);
2063 val = I915_READ(reg);
2064 val &= ~TRANS_ENABLE;
2065 I915_WRITE(reg, val);
2066 /* wait for PCH transcoder off, transcoder state */
2067 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2068 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
2069
2070 if (HAS_PCH_CPT(dev)) {
2071 /* Workaround: Clear the timing override chicken bit again. */
2072 reg = TRANS_CHICKEN2(pipe);
2073 val = I915_READ(reg);
2074 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2075 I915_WRITE(reg, val);
2076 }
2077 }
2078
2079 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
2080 {
2081 u32 val;
2082
2083 val = I915_READ(LPT_TRANSCONF);
2084 val &= ~TRANS_ENABLE;
2085 I915_WRITE(LPT_TRANSCONF, val);
2086 /* wait for PCH transcoder off, transcoder state */
2087 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
2088 DRM_ERROR("Failed to disable PCH transcoder\n");
2089
2090 /* Workaround: clear timing override bit. */
2091 val = I915_READ(TRANS_CHICKEN2(PIPE_A));
2092 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2093 I915_WRITE(TRANS_CHICKEN2(PIPE_A), val);
2094 }
2095
2096 /**
2097 * intel_enable_pipe - enable a pipe, asserting requirements
2098 * @crtc: crtc responsible for the pipe
2099 *
2100 * Enable @crtc's pipe, making sure that various hardware specific requirements
2101 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
2102 */
2103 static void intel_enable_pipe(struct intel_crtc *crtc)
2104 {
2105 struct drm_device *dev = crtc->base.dev;
2106 struct drm_i915_private *dev_priv = dev->dev_private;
2107 enum pipe pipe = crtc->pipe;
2108 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2109 enum pipe pch_transcoder;
2110 i915_reg_t reg;
2111 u32 val;
2112
2113 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2114
2115 assert_planes_disabled(dev_priv, pipe);
2116 assert_cursor_disabled(dev_priv, pipe);
2117 assert_sprites_disabled(dev_priv, pipe);
2118
2119 if (HAS_PCH_LPT(dev_priv->dev))
2120 pch_transcoder = TRANSCODER_A;
2121 else
2122 pch_transcoder = pipe;
2123
2124 /*
2125 * A pipe without a PLL won't actually be able to drive bits from
2126 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2127 * need the check.
2128 */
2129 if (HAS_GMCH_DISPLAY(dev_priv->dev))
2130 if (crtc->config->has_dsi_encoder)
2131 assert_dsi_pll_enabled(dev_priv);
2132 else
2133 assert_pll_enabled(dev_priv, pipe);
2134 else {
2135 if (crtc->config->has_pch_encoder) {
2136 /* if driving the PCH, we need FDI enabled */
2137 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
2138 assert_fdi_tx_pll_enabled(dev_priv,
2139 (enum pipe) cpu_transcoder);
2140 }
2141 /* FIXME: assert CPU port conditions for SNB+ */
2142 }
2143
2144 reg = PIPECONF(cpu_transcoder);
2145 val = I915_READ(reg);
2146 if (val & PIPECONF_ENABLE) {
2147 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2148 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
2149 return;
2150 }
2151
2152 I915_WRITE(reg, val | PIPECONF_ENABLE);
2153 POSTING_READ(reg);
2154
2155 /*
2156 * Until the pipe starts DSL will read as 0, which would cause
2157 * an apparent vblank timestamp jump, which messes up also the
2158 * frame count when it's derived from the timestamps. So let's
2159 * wait for the pipe to start properly before we call
2160 * drm_crtc_vblank_on()
2161 */
2162 if (dev->max_vblank_count == 0 &&
2163 wait_for(intel_get_crtc_scanline(crtc) != crtc->scanline_offset, 50))
2164 DRM_ERROR("pipe %c didn't start\n", pipe_name(pipe));
2165 }
2166
2167 /**
2168 * intel_disable_pipe - disable a pipe, asserting requirements
2169 * @crtc: crtc whose pipes is to be disabled
2170 *
2171 * Disable the pipe of @crtc, making sure that various hardware
2172 * specific requirements are met, if applicable, e.g. plane
2173 * disabled, panel fitter off, etc.
2174 *
2175 * Will wait until the pipe has shut down before returning.
2176 */
2177 static void intel_disable_pipe(struct intel_crtc *crtc)
2178 {
2179 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
2180 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
2181 enum pipe pipe = crtc->pipe;
2182 i915_reg_t reg;
2183 u32 val;
2184
2185 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2186
2187 /*
2188 * Make sure planes won't keep trying to pump pixels to us,
2189 * or we might hang the display.
2190 */
2191 assert_planes_disabled(dev_priv, pipe);
2192 assert_cursor_disabled(dev_priv, pipe);
2193 assert_sprites_disabled(dev_priv, pipe);
2194
2195 reg = PIPECONF(cpu_transcoder);
2196 val = I915_READ(reg);
2197 if ((val & PIPECONF_ENABLE) == 0)
2198 return;
2199
2200 /*
2201 * Double wide has implications for planes
2202 * so best keep it disabled when not needed.
2203 */
2204 if (crtc->config->double_wide)
2205 val &= ~PIPECONF_DOUBLE_WIDE;
2206
2207 /* Don't disable pipe or pipe PLLs if needed */
2208 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2209 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
2210 val &= ~PIPECONF_ENABLE;
2211
2212 I915_WRITE(reg, val);
2213 if ((val & PIPECONF_ENABLE) == 0)
2214 intel_wait_for_pipe_off(crtc);
2215 }
2216
2217 static bool need_vtd_wa(struct drm_device *dev)
2218 {
2219 #ifdef CONFIG_INTEL_IOMMU
2220 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2221 return true;
2222 #endif
2223 return false;
2224 }
2225
2226 static unsigned int intel_tile_width(const struct drm_i915_private *dev_priv,
2227 uint64_t fb_modifier, unsigned int cpp)
2228 {
2229 switch (fb_modifier) {
2230 case DRM_FORMAT_MOD_NONE:
2231 return cpp;
2232 case I915_FORMAT_MOD_X_TILED:
2233 if (IS_GEN2(dev_priv))
2234 return 128;
2235 else
2236 return 512;
2237 case I915_FORMAT_MOD_Y_TILED:
2238 if (IS_GEN2(dev_priv) || HAS_128_BYTE_Y_TILING(dev_priv))
2239 return 128;
2240 else
2241 return 512;
2242 case I915_FORMAT_MOD_Yf_TILED:
2243 switch (cpp) {
2244 case 1:
2245 return 64;
2246 case 2:
2247 case 4:
2248 return 128;
2249 case 8:
2250 case 16:
2251 return 256;
2252 default:
2253 MISSING_CASE(cpp);
2254 return cpp;
2255 }
2256 break;
2257 default:
2258 MISSING_CASE(fb_modifier);
2259 return cpp;
2260 }
2261 }
2262
2263 unsigned int
2264 intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2265 uint64_t fb_format_modifier, unsigned int plane)
2266 {
2267 unsigned int tile_height;
2268 uint32_t pixel_bytes;
2269
2270 switch (fb_format_modifier) {
2271 case DRM_FORMAT_MOD_NONE:
2272 tile_height = 1;
2273 break;
2274 case I915_FORMAT_MOD_X_TILED:
2275 tile_height = IS_GEN2(dev) ? 16 : 8;
2276 break;
2277 case I915_FORMAT_MOD_Y_TILED:
2278 tile_height = 32;
2279 break;
2280 case I915_FORMAT_MOD_Yf_TILED:
2281 pixel_bytes = drm_format_plane_cpp(pixel_format, plane);
2282 switch (pixel_bytes) {
2283 default:
2284 case 1:
2285 tile_height = 64;
2286 break;
2287 case 2:
2288 case 4:
2289 tile_height = 32;
2290 break;
2291 case 8:
2292 tile_height = 16;
2293 break;
2294 case 16:
2295 WARN_ONCE(1,
2296 "128-bit pixels are not supported for display!");
2297 tile_height = 16;
2298 break;
2299 }
2300 break;
2301 default:
2302 MISSING_CASE(fb_format_modifier);
2303 tile_height = 1;
2304 break;
2305 }
2306
2307 return tile_height;
2308 }
2309
2310 unsigned int
2311 intel_fb_align_height(struct drm_device *dev, unsigned int height,
2312 uint32_t pixel_format, uint64_t fb_format_modifier)
2313 {
2314 return ALIGN(height, intel_tile_height(dev, pixel_format,
2315 fb_format_modifier, 0));
2316 }
2317
2318 static void
2319 intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2320 const struct drm_plane_state *plane_state)
2321 {
2322 struct intel_rotation_info *info = &view->params.rotation_info;
2323 unsigned int tile_height, tile_pitch;
2324
2325 *view = i915_ggtt_view_normal;
2326
2327 if (!plane_state)
2328 return;
2329
2330 if (!intel_rotation_90_or_270(plane_state->rotation))
2331 return;
2332
2333 *view = i915_ggtt_view_rotated;
2334
2335 info->height = fb->height;
2336 info->pixel_format = fb->pixel_format;
2337 info->pitch = fb->pitches[0];
2338 info->uv_offset = fb->offsets[1];
2339 info->fb_modifier = fb->modifier[0];
2340
2341 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2342 fb->modifier[0], 0);
2343 tile_pitch = PAGE_SIZE / tile_height;
2344 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2345 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2346 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2347
2348 if (info->pixel_format == DRM_FORMAT_NV12) {
2349 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2350 fb->modifier[0], 1);
2351 tile_pitch = PAGE_SIZE / tile_height;
2352 info->width_pages_uv = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2353 info->height_pages_uv = DIV_ROUND_UP(fb->height / 2,
2354 tile_height);
2355 info->size_uv = info->width_pages_uv * info->height_pages_uv *
2356 PAGE_SIZE;
2357 }
2358 }
2359
2360 static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2361 {
2362 if (INTEL_INFO(dev_priv)->gen >= 9)
2363 return 256 * 1024;
2364 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2365 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2366 return 128 * 1024;
2367 else if (INTEL_INFO(dev_priv)->gen >= 4)
2368 return 4 * 1024;
2369 else
2370 return 0;
2371 }
2372
2373 int
2374 intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2375 struct drm_framebuffer *fb,
2376 const struct drm_plane_state *plane_state)
2377 {
2378 struct drm_device *dev = fb->dev;
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2381 struct i915_ggtt_view view;
2382 u32 alignment;
2383 int ret;
2384
2385 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2386
2387 switch (fb->modifier[0]) {
2388 case DRM_FORMAT_MOD_NONE:
2389 alignment = intel_linear_alignment(dev_priv);
2390 break;
2391 case I915_FORMAT_MOD_X_TILED:
2392 if (INTEL_INFO(dev)->gen >= 9)
2393 alignment = 256 * 1024;
2394 else {
2395 /* pin() will align the object as required by fence */
2396 alignment = 0;
2397 }
2398 break;
2399 case I915_FORMAT_MOD_Y_TILED:
2400 case I915_FORMAT_MOD_Yf_TILED:
2401 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2402 "Y tiling bo slipped through, driver bug!\n"))
2403 return -EINVAL;
2404 alignment = 1 * 1024 * 1024;
2405 break;
2406 default:
2407 MISSING_CASE(fb->modifier[0]);
2408 return -EINVAL;
2409 }
2410
2411 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2412
2413 /* Note that the w/a also requires 64 PTE of padding following the
2414 * bo. We currently fill all unused PTE with the shadow page and so
2415 * we should always have valid PTE following the scanout preventing
2416 * the VT-d warning.
2417 */
2418 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2419 alignment = 256 * 1024;
2420
2421 /*
2422 * Global gtt pte registers are special registers which actually forward
2423 * writes to a chunk of system memory. Which means that there is no risk
2424 * that the register values disappear as soon as we call
2425 * intel_runtime_pm_put(), so it is correct to wrap only the
2426 * pin/unpin/fence and not more.
2427 */
2428 intel_runtime_pm_get(dev_priv);
2429
2430 ret = i915_gem_object_pin_to_display_plane(obj, alignment,
2431 &view);
2432 if (ret)
2433 goto err_pm;
2434
2435 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2436 * fence, whereas 965+ only requires a fence if using
2437 * framebuffer compression. For simplicity, we always install
2438 * a fence as the cost is not that onerous.
2439 */
2440 if (view.type == I915_GGTT_VIEW_NORMAL) {
2441 ret = i915_gem_object_get_fence(obj);
2442 if (ret == -EDEADLK) {
2443 /*
2444 * -EDEADLK means there are no free fences
2445 * no pending flips.
2446 *
2447 * This is propagated to atomic, but it uses
2448 * -EDEADLK to force a locking recovery, so
2449 * change the returned error to -EBUSY.
2450 */
2451 ret = -EBUSY;
2452 goto err_unpin;
2453 } else if (ret)
2454 goto err_unpin;
2455
2456 i915_gem_object_pin_fence(obj);
2457 }
2458
2459 intel_runtime_pm_put(dev_priv);
2460 return 0;
2461
2462 err_unpin:
2463 i915_gem_object_unpin_from_display_plane(obj, &view);
2464 err_pm:
2465 intel_runtime_pm_put(dev_priv);
2466 return ret;
2467 }
2468
2469 static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2470 const struct drm_plane_state *plane_state)
2471 {
2472 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2473 struct i915_ggtt_view view;
2474
2475 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2476
2477 intel_fill_fb_ggtt_view(&view, fb, plane_state);
2478
2479 if (view.type == I915_GGTT_VIEW_NORMAL)
2480 i915_gem_object_unpin_fence(obj);
2481
2482 i915_gem_object_unpin_from_display_plane(obj, &view);
2483 }
2484
2485 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2486 * is assumed to be a power-of-two. */
2487 unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2488 int *x, int *y,
2489 uint64_t fb_modifier,
2490 unsigned int cpp,
2491 unsigned int pitch)
2492 {
2493 if (fb_modifier != DRM_FORMAT_MOD_NONE) {
2494 unsigned int tile_rows, tiles;
2495
2496 tile_rows = *y / 8;
2497 *y %= 8;
2498
2499 tiles = *x / (512/cpp);
2500 *x %= 512/cpp;
2501
2502 return tile_rows * pitch * 8 + tiles * 4096;
2503 } else {
2504 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
2505 unsigned int offset;
2506
2507 offset = *y * pitch + *x * cpp;
2508 *y = (offset & alignment) / pitch;
2509 *x = ((offset & alignment) - *y * pitch) / cpp;
2510 return offset & ~alignment;
2511 }
2512 }
2513
2514 static int i9xx_format_to_fourcc(int format)
2515 {
2516 switch (format) {
2517 case DISPPLANE_8BPP:
2518 return DRM_FORMAT_C8;
2519 case DISPPLANE_BGRX555:
2520 return DRM_FORMAT_XRGB1555;
2521 case DISPPLANE_BGRX565:
2522 return DRM_FORMAT_RGB565;
2523 default:
2524 case DISPPLANE_BGRX888:
2525 return DRM_FORMAT_XRGB8888;
2526 case DISPPLANE_RGBX888:
2527 return DRM_FORMAT_XBGR8888;
2528 case DISPPLANE_BGRX101010:
2529 return DRM_FORMAT_XRGB2101010;
2530 case DISPPLANE_RGBX101010:
2531 return DRM_FORMAT_XBGR2101010;
2532 }
2533 }
2534
2535 static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2536 {
2537 switch (format) {
2538 case PLANE_CTL_FORMAT_RGB_565:
2539 return DRM_FORMAT_RGB565;
2540 default:
2541 case PLANE_CTL_FORMAT_XRGB_8888:
2542 if (rgb_order) {
2543 if (alpha)
2544 return DRM_FORMAT_ABGR8888;
2545 else
2546 return DRM_FORMAT_XBGR8888;
2547 } else {
2548 if (alpha)
2549 return DRM_FORMAT_ARGB8888;
2550 else
2551 return DRM_FORMAT_XRGB8888;
2552 }
2553 case PLANE_CTL_FORMAT_XRGB_2101010:
2554 if (rgb_order)
2555 return DRM_FORMAT_XBGR2101010;
2556 else
2557 return DRM_FORMAT_XRGB2101010;
2558 }
2559 }
2560
2561 static bool
2562 intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2563 struct intel_initial_plane_config *plane_config)
2564 {
2565 struct drm_device *dev = crtc->base.dev;
2566 struct drm_i915_private *dev_priv = to_i915(dev);
2567 struct drm_i915_gem_object *obj = NULL;
2568 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2569 struct drm_framebuffer *fb = &plane_config->fb->base;
2570 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2571 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2572 PAGE_SIZE);
2573
2574 size_aligned -= base_aligned;
2575
2576 if (plane_config->size == 0)
2577 return false;
2578
2579 /* If the FB is too big, just don't use it since fbdev is not very
2580 * important and we should probably use that space with FBC or other
2581 * features. */
2582 if (size_aligned * 2 > dev_priv->gtt.stolen_usable_size)
2583 return false;
2584
2585 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2586 base_aligned,
2587 base_aligned,
2588 size_aligned);
2589 if (!obj)
2590 return false;
2591
2592 obj->tiling_mode = plane_config->tiling;
2593 if (obj->tiling_mode == I915_TILING_X)
2594 obj->stride = fb->pitches[0];
2595
2596 mode_cmd.pixel_format = fb->pixel_format;
2597 mode_cmd.width = fb->width;
2598 mode_cmd.height = fb->height;
2599 mode_cmd.pitches[0] = fb->pitches[0];
2600 mode_cmd.modifier[0] = fb->modifier[0];
2601 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
2602
2603 mutex_lock(&dev->struct_mutex);
2604 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
2605 &mode_cmd, obj)) {
2606 DRM_DEBUG_KMS("intel fb init failed\n");
2607 goto out_unref_obj;
2608 }
2609 mutex_unlock(&dev->struct_mutex);
2610
2611 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
2612 return true;
2613
2614 out_unref_obj:
2615 drm_gem_object_unreference(&obj->base);
2616 mutex_unlock(&dev->struct_mutex);
2617 return false;
2618 }
2619
2620 /* Update plane->state->fb to match plane->fb after driver-internal updates */
2621 static void
2622 update_state_fb(struct drm_plane *plane)
2623 {
2624 if (plane->fb == plane->state->fb)
2625 return;
2626
2627 if (plane->state->fb)
2628 drm_framebuffer_unreference(plane->state->fb);
2629 plane->state->fb = plane->fb;
2630 if (plane->state->fb)
2631 drm_framebuffer_reference(plane->state->fb);
2632 }
2633
2634 static void
2635 intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2636 struct intel_initial_plane_config *plane_config)
2637 {
2638 struct drm_device *dev = intel_crtc->base.dev;
2639 struct drm_i915_private *dev_priv = dev->dev_private;
2640 struct drm_crtc *c;
2641 struct intel_crtc *i;
2642 struct drm_i915_gem_object *obj;
2643 struct drm_plane *primary = intel_crtc->base.primary;
2644 struct drm_plane_state *plane_state = primary->state;
2645 struct drm_crtc_state *crtc_state = intel_crtc->base.state;
2646 struct intel_plane *intel_plane = to_intel_plane(primary);
2647 struct intel_plane_state *intel_state =
2648 to_intel_plane_state(plane_state);
2649 struct drm_framebuffer *fb;
2650
2651 if (!plane_config->fb)
2652 return;
2653
2654 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
2655 fb = &plane_config->fb->base;
2656 goto valid_fb;
2657 }
2658
2659 kfree(plane_config->fb);
2660
2661 /*
2662 * Failed to alloc the obj, check to see if we should share
2663 * an fb with another CRTC instead
2664 */
2665 for_each_crtc(dev, c) {
2666 i = to_intel_crtc(c);
2667
2668 if (c == &intel_crtc->base)
2669 continue;
2670
2671 if (!i->active)
2672 continue;
2673
2674 fb = c->primary->fb;
2675 if (!fb)
2676 continue;
2677
2678 obj = intel_fb_obj(fb);
2679 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
2680 drm_framebuffer_reference(fb);
2681 goto valid_fb;
2682 }
2683 }
2684
2685 /*
2686 * We've failed to reconstruct the BIOS FB. Current display state
2687 * indicates that the primary plane is visible, but has a NULL FB,
2688 * which will lead to problems later if we don't fix it up. The
2689 * simplest solution is to just disable the primary plane now and
2690 * pretend the BIOS never had it enabled.
2691 */
2692 to_intel_plane_state(plane_state)->visible = false;
2693 crtc_state->plane_mask &= ~(1 << drm_plane_index(primary));
2694 intel_pre_disable_primary(&intel_crtc->base);
2695 intel_plane->disable_plane(primary, &intel_crtc->base);
2696
2697 return;
2698
2699 valid_fb:
2700 plane_state->src_x = 0;
2701 plane_state->src_y = 0;
2702 plane_state->src_w = fb->width << 16;
2703 plane_state->src_h = fb->height << 16;
2704
2705 plane_state->crtc_x = 0;
2706 plane_state->crtc_y = 0;
2707 plane_state->crtc_w = fb->width;
2708 plane_state->crtc_h = fb->height;
2709
2710 intel_state->src.x1 = plane_state->src_x;
2711 intel_state->src.y1 = plane_state->src_y;
2712 intel_state->src.x2 = plane_state->src_x + plane_state->src_w;
2713 intel_state->src.y2 = plane_state->src_y + plane_state->src_h;
2714 intel_state->dst.x1 = plane_state->crtc_x;
2715 intel_state->dst.y1 = plane_state->crtc_y;
2716 intel_state->dst.x2 = plane_state->crtc_x + plane_state->crtc_w;
2717 intel_state->dst.y2 = plane_state->crtc_y + plane_state->crtc_h;
2718
2719 obj = intel_fb_obj(fb);
2720 if (obj->tiling_mode != I915_TILING_NONE)
2721 dev_priv->preserve_bios_swizzle = true;
2722
2723 drm_framebuffer_reference(fb);
2724 primary->fb = primary->state->fb = fb;
2725 primary->crtc = primary->state->crtc = &intel_crtc->base;
2726 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
2727 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
2728 }
2729
2730 static void i9xx_update_primary_plane(struct drm_plane *primary,
2731 const struct intel_crtc_state *crtc_state,
2732 const struct intel_plane_state *plane_state)
2733 {
2734 struct drm_device *dev = primary->dev;
2735 struct drm_i915_private *dev_priv = dev->dev_private;
2736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2737 struct drm_framebuffer *fb = plane_state->base.fb;
2738 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2739 int plane = intel_crtc->plane;
2740 unsigned long linear_offset;
2741 int x = plane_state->src.x1 >> 16;
2742 int y = plane_state->src.y1 >> 16;
2743 u32 dspcntr;
2744 i915_reg_t reg = DSPCNTR(plane);
2745 int pixel_size;
2746
2747 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2748
2749 dspcntr = DISPPLANE_GAMMA_ENABLE;
2750
2751 dspcntr |= DISPLAY_PLANE_ENABLE;
2752
2753 if (INTEL_INFO(dev)->gen < 4) {
2754 if (intel_crtc->pipe == PIPE_B)
2755 dspcntr |= DISPPLANE_SEL_PIPE_B;
2756
2757 /* pipesrc and dspsize control the size that is scaled from,
2758 * which should always be the user's requested size.
2759 */
2760 I915_WRITE(DSPSIZE(plane),
2761 ((crtc_state->pipe_src_h - 1) << 16) |
2762 (crtc_state->pipe_src_w - 1));
2763 I915_WRITE(DSPPOS(plane), 0);
2764 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2765 I915_WRITE(PRIMSIZE(plane),
2766 ((crtc_state->pipe_src_h - 1) << 16) |
2767 (crtc_state->pipe_src_w - 1));
2768 I915_WRITE(PRIMPOS(plane), 0);
2769 I915_WRITE(PRIMCNSTALPHA(plane), 0);
2770 }
2771
2772 switch (fb->pixel_format) {
2773 case DRM_FORMAT_C8:
2774 dspcntr |= DISPPLANE_8BPP;
2775 break;
2776 case DRM_FORMAT_XRGB1555:
2777 dspcntr |= DISPPLANE_BGRX555;
2778 break;
2779 case DRM_FORMAT_RGB565:
2780 dspcntr |= DISPPLANE_BGRX565;
2781 break;
2782 case DRM_FORMAT_XRGB8888:
2783 dspcntr |= DISPPLANE_BGRX888;
2784 break;
2785 case DRM_FORMAT_XBGR8888:
2786 dspcntr |= DISPPLANE_RGBX888;
2787 break;
2788 case DRM_FORMAT_XRGB2101010:
2789 dspcntr |= DISPPLANE_BGRX101010;
2790 break;
2791 case DRM_FORMAT_XBGR2101010:
2792 dspcntr |= DISPPLANE_RGBX101010;
2793 break;
2794 default:
2795 BUG();
2796 }
2797
2798 if (INTEL_INFO(dev)->gen >= 4 &&
2799 obj->tiling_mode != I915_TILING_NONE)
2800 dspcntr |= DISPPLANE_TILED;
2801
2802 if (IS_G4X(dev))
2803 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2804
2805 linear_offset = y * fb->pitches[0] + x * pixel_size;
2806
2807 if (INTEL_INFO(dev)->gen >= 4) {
2808 intel_crtc->dspaddr_offset =
2809 intel_gen4_compute_page_offset(dev_priv, &x, &y,
2810 fb->modifier[0],
2811 pixel_size,
2812 fb->pitches[0]);
2813 linear_offset -= intel_crtc->dspaddr_offset;
2814 } else {
2815 intel_crtc->dspaddr_offset = linear_offset;
2816 }
2817
2818 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2819 dspcntr |= DISPPLANE_ROTATE_180;
2820
2821 x += (crtc_state->pipe_src_w - 1);
2822 y += (crtc_state->pipe_src_h - 1);
2823
2824 /* Finding the last pixel of the last line of the display
2825 data and adding to linear_offset*/
2826 linear_offset +=
2827 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2828 (crtc_state->pipe_src_w - 1) * pixel_size;
2829 }
2830
2831 intel_crtc->adjusted_x = x;
2832 intel_crtc->adjusted_y = y;
2833
2834 I915_WRITE(reg, dspcntr);
2835
2836 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2837 if (INTEL_INFO(dev)->gen >= 4) {
2838 I915_WRITE(DSPSURF(plane),
2839 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2840 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2841 I915_WRITE(DSPLINOFF(plane), linear_offset);
2842 } else
2843 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
2844 POSTING_READ(reg);
2845 }
2846
2847 static void i9xx_disable_primary_plane(struct drm_plane *primary,
2848 struct drm_crtc *crtc)
2849 {
2850 struct drm_device *dev = crtc->dev;
2851 struct drm_i915_private *dev_priv = dev->dev_private;
2852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2853 int plane = intel_crtc->plane;
2854
2855 I915_WRITE(DSPCNTR(plane), 0);
2856 if (INTEL_INFO(dev_priv)->gen >= 4)
2857 I915_WRITE(DSPSURF(plane), 0);
2858 else
2859 I915_WRITE(DSPADDR(plane), 0);
2860 POSTING_READ(DSPCNTR(plane));
2861 }
2862
2863 static void ironlake_update_primary_plane(struct drm_plane *primary,
2864 const struct intel_crtc_state *crtc_state,
2865 const struct intel_plane_state *plane_state)
2866 {
2867 struct drm_device *dev = primary->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
2869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
2870 struct drm_framebuffer *fb = plane_state->base.fb;
2871 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
2872 int plane = intel_crtc->plane;
2873 unsigned long linear_offset;
2874 u32 dspcntr;
2875 i915_reg_t reg = DSPCNTR(plane);
2876 int pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2877 int x = plane_state->src.x1 >> 16;
2878 int y = plane_state->src.y1 >> 16;
2879
2880 dspcntr = DISPPLANE_GAMMA_ENABLE;
2881 dspcntr |= DISPLAY_PLANE_ENABLE;
2882
2883 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2884 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
2885
2886 switch (fb->pixel_format) {
2887 case DRM_FORMAT_C8:
2888 dspcntr |= DISPPLANE_8BPP;
2889 break;
2890 case DRM_FORMAT_RGB565:
2891 dspcntr |= DISPPLANE_BGRX565;
2892 break;
2893 case DRM_FORMAT_XRGB8888:
2894 dspcntr |= DISPPLANE_BGRX888;
2895 break;
2896 case DRM_FORMAT_XBGR8888:
2897 dspcntr |= DISPPLANE_RGBX888;
2898 break;
2899 case DRM_FORMAT_XRGB2101010:
2900 dspcntr |= DISPPLANE_BGRX101010;
2901 break;
2902 case DRM_FORMAT_XBGR2101010:
2903 dspcntr |= DISPPLANE_RGBX101010;
2904 break;
2905 default:
2906 BUG();
2907 }
2908
2909 if (obj->tiling_mode != I915_TILING_NONE)
2910 dspcntr |= DISPPLANE_TILED;
2911
2912 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
2913 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2914
2915 linear_offset = y * fb->pitches[0] + x * pixel_size;
2916 intel_crtc->dspaddr_offset =
2917 intel_gen4_compute_page_offset(dev_priv, &x, &y,
2918 fb->modifier[0],
2919 pixel_size,
2920 fb->pitches[0]);
2921 linear_offset -= intel_crtc->dspaddr_offset;
2922 if (plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
2923 dspcntr |= DISPPLANE_ROTATE_180;
2924
2925 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
2926 x += (crtc_state->pipe_src_w - 1);
2927 y += (crtc_state->pipe_src_h - 1);
2928
2929 /* Finding the last pixel of the last line of the display
2930 data and adding to linear_offset*/
2931 linear_offset +=
2932 (crtc_state->pipe_src_h - 1) * fb->pitches[0] +
2933 (crtc_state->pipe_src_w - 1) * pixel_size;
2934 }
2935 }
2936
2937 intel_crtc->adjusted_x = x;
2938 intel_crtc->adjusted_y = y;
2939
2940 I915_WRITE(reg, dspcntr);
2941
2942 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2943 I915_WRITE(DSPSURF(plane),
2944 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
2945 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2946 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2947 } else {
2948 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2949 I915_WRITE(DSPLINOFF(plane), linear_offset);
2950 }
2951 POSTING_READ(reg);
2952 }
2953
2954 u32 intel_fb_stride_alignment(const struct drm_i915_private *dev_priv,
2955 uint64_t fb_modifier, uint32_t pixel_format)
2956 {
2957 if (fb_modifier == DRM_FORMAT_MOD_NONE) {
2958 return 64;
2959 } else {
2960 int cpp = drm_format_plane_cpp(pixel_format, 0);
2961
2962 return intel_tile_width(dev_priv, fb_modifier, cpp);
2963 }
2964 }
2965
2966 u32 intel_plane_obj_offset(struct intel_plane *intel_plane,
2967 struct drm_i915_gem_object *obj,
2968 unsigned int plane)
2969 {
2970 struct i915_ggtt_view view;
2971 struct i915_vma *vma;
2972 u64 offset;
2973
2974 intel_fill_fb_ggtt_view(&view, intel_plane->base.fb,
2975 intel_plane->base.state);
2976
2977 vma = i915_gem_obj_to_ggtt_view(obj, &view);
2978 if (WARN(!vma, "ggtt vma for display object not found! (view=%u)\n",
2979 view.type))
2980 return -1;
2981
2982 offset = vma->node.start;
2983
2984 if (plane == 1) {
2985 offset += vma->ggtt_view.params.rotation_info.uv_start_page *
2986 PAGE_SIZE;
2987 }
2988
2989 WARN_ON(upper_32_bits(offset));
2990
2991 return lower_32_bits(offset);
2992 }
2993
2994 static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2995 {
2996 struct drm_device *dev = intel_crtc->base.dev;
2997 struct drm_i915_private *dev_priv = dev->dev_private;
2998
2999 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
3000 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
3001 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
3002 }
3003
3004 /*
3005 * This function detaches (aka. unbinds) unused scalers in hardware
3006 */
3007 static void skl_detach_scalers(struct intel_crtc *intel_crtc)
3008 {
3009 struct intel_crtc_scaler_state *scaler_state;
3010 int i;
3011
3012 scaler_state = &intel_crtc->config->scaler_state;
3013
3014 /* loop through and disable scalers that aren't in use */
3015 for (i = 0; i < intel_crtc->num_scalers; i++) {
3016 if (!scaler_state->scalers[i].in_use)
3017 skl_detach_scaler(intel_crtc, i);
3018 }
3019 }
3020
3021 u32 skl_plane_ctl_format(uint32_t pixel_format)
3022 {
3023 switch (pixel_format) {
3024 case DRM_FORMAT_C8:
3025 return PLANE_CTL_FORMAT_INDEXED;
3026 case DRM_FORMAT_RGB565:
3027 return PLANE_CTL_FORMAT_RGB_565;
3028 case DRM_FORMAT_XBGR8888:
3029 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
3030 case DRM_FORMAT_XRGB8888:
3031 return PLANE_CTL_FORMAT_XRGB_8888;
3032 /*
3033 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
3034 * to be already pre-multiplied. We need to add a knob (or a different
3035 * DRM_FORMAT) for user-space to configure that.
3036 */
3037 case DRM_FORMAT_ABGR8888:
3038 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
3039 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3040 case DRM_FORMAT_ARGB8888:
3041 return PLANE_CTL_FORMAT_XRGB_8888 |
3042 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
3043 case DRM_FORMAT_XRGB2101010:
3044 return PLANE_CTL_FORMAT_XRGB_2101010;
3045 case DRM_FORMAT_XBGR2101010:
3046 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
3047 case DRM_FORMAT_YUYV:
3048 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
3049 case DRM_FORMAT_YVYU:
3050 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
3051 case DRM_FORMAT_UYVY:
3052 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3053 case DRM_FORMAT_VYUY:
3054 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
3055 default:
3056 MISSING_CASE(pixel_format);
3057 }
3058
3059 return 0;
3060 }
3061
3062 u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3063 {
3064 switch (fb_modifier) {
3065 case DRM_FORMAT_MOD_NONE:
3066 break;
3067 case I915_FORMAT_MOD_X_TILED:
3068 return PLANE_CTL_TILED_X;
3069 case I915_FORMAT_MOD_Y_TILED:
3070 return PLANE_CTL_TILED_Y;
3071 case I915_FORMAT_MOD_Yf_TILED:
3072 return PLANE_CTL_TILED_YF;
3073 default:
3074 MISSING_CASE(fb_modifier);
3075 }
3076
3077 return 0;
3078 }
3079
3080 u32 skl_plane_ctl_rotation(unsigned int rotation)
3081 {
3082 switch (rotation) {
3083 case BIT(DRM_ROTATE_0):
3084 break;
3085 /*
3086 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3087 * while i915 HW rotation is clockwise, thats why this swapping.
3088 */
3089 case BIT(DRM_ROTATE_90):
3090 return PLANE_CTL_ROTATE_270;
3091 case BIT(DRM_ROTATE_180):
3092 return PLANE_CTL_ROTATE_180;
3093 case BIT(DRM_ROTATE_270):
3094 return PLANE_CTL_ROTATE_90;
3095 default:
3096 MISSING_CASE(rotation);
3097 }
3098
3099 return 0;
3100 }
3101
3102 static void skylake_update_primary_plane(struct drm_plane *plane,
3103 const struct intel_crtc_state *crtc_state,
3104 const struct intel_plane_state *plane_state)
3105 {
3106 struct drm_device *dev = plane->dev;
3107 struct drm_i915_private *dev_priv = dev->dev_private;
3108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
3109 struct drm_framebuffer *fb = plane_state->base.fb;
3110 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
3111 int pipe = intel_crtc->pipe;
3112 u32 plane_ctl, stride_div, stride;
3113 u32 tile_height, plane_offset, plane_size;
3114 unsigned int rotation = plane_state->base.rotation;
3115 int x_offset, y_offset;
3116 u32 surf_addr;
3117 int scaler_id = plane_state->scaler_id;
3118 int src_x = plane_state->src.x1 >> 16;
3119 int src_y = plane_state->src.y1 >> 16;
3120 int src_w = drm_rect_width(&plane_state->src) >> 16;
3121 int src_h = drm_rect_height(&plane_state->src) >> 16;
3122 int dst_x = plane_state->dst.x1;
3123 int dst_y = plane_state->dst.y1;
3124 int dst_w = drm_rect_width(&plane_state->dst);
3125 int dst_h = drm_rect_height(&plane_state->dst);
3126
3127 plane_ctl = PLANE_CTL_ENABLE |
3128 PLANE_CTL_PIPE_GAMMA_ENABLE |
3129 PLANE_CTL_PIPE_CSC_ENABLE;
3130
3131 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3132 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3133 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3134 plane_ctl |= skl_plane_ctl_rotation(rotation);
3135
3136 stride_div = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
3137 fb->pixel_format);
3138 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj, 0);
3139
3140 WARN_ON(drm_rect_width(&plane_state->src) == 0);
3141
3142 if (intel_rotation_90_or_270(rotation)) {
3143 /* stride = Surface height in tiles */
3144 tile_height = intel_tile_height(dev, fb->pixel_format,
3145 fb->modifier[0], 0);
3146 stride = DIV_ROUND_UP(fb->height, tile_height);
3147 x_offset = stride * tile_height - src_y - src_h;
3148 y_offset = src_x;
3149 plane_size = (src_w - 1) << 16 | (src_h - 1);
3150 } else {
3151 stride = fb->pitches[0] / stride_div;
3152 x_offset = src_x;
3153 y_offset = src_y;
3154 plane_size = (src_h - 1) << 16 | (src_w - 1);
3155 }
3156 plane_offset = y_offset << 16 | x_offset;
3157
3158 intel_crtc->adjusted_x = x_offset;
3159 intel_crtc->adjusted_y = y_offset;
3160
3161 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3162 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3163 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3164 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
3165
3166 if (scaler_id >= 0) {
3167 uint32_t ps_ctrl = 0;
3168
3169 WARN_ON(!dst_w || !dst_h);
3170 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3171 crtc_state->scaler_state.scalers[scaler_id].mode;
3172 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3173 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3174 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3175 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3176 I915_WRITE(PLANE_POS(pipe, 0), 0);
3177 } else {
3178 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3179 }
3180
3181 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
3182
3183 POSTING_READ(PLANE_SURF(pipe, 0));
3184 }
3185
3186 static void skylake_disable_primary_plane(struct drm_plane *primary,
3187 struct drm_crtc *crtc)
3188 {
3189 struct drm_device *dev = crtc->dev;
3190 struct drm_i915_private *dev_priv = dev->dev_private;
3191 int pipe = to_intel_crtc(crtc)->pipe;
3192
3193 if (dev_priv->fbc.deactivate)
3194 dev_priv->fbc.deactivate(dev_priv);
3195
3196 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3197 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3198 POSTING_READ(PLANE_SURF(pipe, 0));
3199 }
3200
3201 /* Assume fb object is pinned & idle & fenced and just update base pointers */
3202 static int
3203 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3204 int x, int y, enum mode_set_atomic state)
3205 {
3206 /* Support for kgdboc is disabled, this needs a major rework. */
3207 DRM_ERROR("legacy panic handler not supported any more.\n");
3208
3209 return -ENODEV;
3210 }
3211
3212 static void intel_complete_page_flips(struct drm_device *dev)
3213 {
3214 struct drm_crtc *crtc;
3215
3216 for_each_crtc(dev, crtc) {
3217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3218 enum plane plane = intel_crtc->plane;
3219
3220 intel_prepare_page_flip(dev, plane);
3221 intel_finish_page_flip_plane(dev, plane);
3222 }
3223 }
3224
3225 static void intel_update_primary_planes(struct drm_device *dev)
3226 {
3227 struct drm_crtc *crtc;
3228
3229 for_each_crtc(dev, crtc) {
3230 struct intel_plane *plane = to_intel_plane(crtc->primary);
3231 struct intel_plane_state *plane_state;
3232
3233 drm_modeset_lock_crtc(crtc, &plane->base);
3234 plane_state = to_intel_plane_state(plane->base.state);
3235
3236 if (plane_state->visible)
3237 plane->update_plane(&plane->base,
3238 to_intel_crtc_state(crtc->state),
3239 plane_state);
3240
3241 drm_modeset_unlock_crtc(crtc);
3242 }
3243 }
3244
3245 void intel_prepare_reset(struct drm_device *dev)
3246 {
3247 /* no reset support for gen2 */
3248 if (IS_GEN2(dev))
3249 return;
3250
3251 /* reset doesn't touch the display */
3252 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3253 return;
3254
3255 drm_modeset_lock_all(dev);
3256 /*
3257 * Disabling the crtcs gracefully seems nicer. Also the
3258 * g33 docs say we should at least disable all the planes.
3259 */
3260 intel_display_suspend(dev);
3261 }
3262
3263 void intel_finish_reset(struct drm_device *dev)
3264 {
3265 struct drm_i915_private *dev_priv = to_i915(dev);
3266
3267 /*
3268 * Flips in the rings will be nuked by the reset,
3269 * so complete all pending flips so that user space
3270 * will get its events and not get stuck.
3271 */
3272 intel_complete_page_flips(dev);
3273
3274 /* no reset support for gen2 */
3275 if (IS_GEN2(dev))
3276 return;
3277
3278 /* reset doesn't touch the display */
3279 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3280 /*
3281 * Flips in the rings have been nuked by the reset,
3282 * so update the base address of all primary
3283 * planes to the the last fb to make sure we're
3284 * showing the correct fb after a reset.
3285 *
3286 * FIXME: Atomic will make this obsolete since we won't schedule
3287 * CS-based flips (which might get lost in gpu resets) any more.
3288 */
3289 intel_update_primary_planes(dev);
3290 return;
3291 }
3292
3293 /*
3294 * The display has been reset as well,
3295 * so need a full re-initialization.
3296 */
3297 intel_runtime_pm_disable_interrupts(dev_priv);
3298 intel_runtime_pm_enable_interrupts(dev_priv);
3299
3300 intel_modeset_init_hw(dev);
3301
3302 spin_lock_irq(&dev_priv->irq_lock);
3303 if (dev_priv->display.hpd_irq_setup)
3304 dev_priv->display.hpd_irq_setup(dev);
3305 spin_unlock_irq(&dev_priv->irq_lock);
3306
3307 intel_display_resume(dev);
3308
3309 intel_hpd_init(dev_priv);
3310
3311 drm_modeset_unlock_all(dev);
3312 }
3313
3314 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3315 {
3316 struct drm_device *dev = crtc->dev;
3317 struct drm_i915_private *dev_priv = dev->dev_private;
3318 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3319 bool pending;
3320
3321 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3322 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3323 return false;
3324
3325 spin_lock_irq(&dev->event_lock);
3326 pending = to_intel_crtc(crtc)->unpin_work != NULL;
3327 spin_unlock_irq(&dev->event_lock);
3328
3329 return pending;
3330 }
3331
3332 static void intel_update_pipe_config(struct intel_crtc *crtc,
3333 struct intel_crtc_state *old_crtc_state)
3334 {
3335 struct drm_device *dev = crtc->base.dev;
3336 struct drm_i915_private *dev_priv = dev->dev_private;
3337 struct intel_crtc_state *pipe_config =
3338 to_intel_crtc_state(crtc->base.state);
3339
3340 /* drm_atomic_helper_update_legacy_modeset_state might not be called. */
3341 crtc->base.mode = crtc->base.state->mode;
3342
3343 DRM_DEBUG_KMS("Updating pipe size %ix%i -> %ix%i\n",
3344 old_crtc_state->pipe_src_w, old_crtc_state->pipe_src_h,
3345 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
3346
3347 if (HAS_DDI(dev))
3348 intel_set_pipe_csc(&crtc->base);
3349
3350 /*
3351 * Update pipe size and adjust fitter if needed: the reason for this is
3352 * that in compute_mode_changes we check the native mode (not the pfit
3353 * mode) to see if we can flip rather than do a full mode set. In the
3354 * fastboot case, we'll flip, but if we don't update the pipesrc and
3355 * pfit state, we'll end up with a big fb scanned out into the wrong
3356 * sized surface.
3357 */
3358
3359 I915_WRITE(PIPESRC(crtc->pipe),
3360 ((pipe_config->pipe_src_w - 1) << 16) |
3361 (pipe_config->pipe_src_h - 1));
3362
3363 /* on skylake this is done by detaching scalers */
3364 if (INTEL_INFO(dev)->gen >= 9) {
3365 skl_detach_scalers(crtc);
3366
3367 if (pipe_config->pch_pfit.enabled)
3368 skylake_pfit_enable(crtc);
3369 } else if (HAS_PCH_SPLIT(dev)) {
3370 if (pipe_config->pch_pfit.enabled)
3371 ironlake_pfit_enable(crtc);
3372 else if (old_crtc_state->pch_pfit.enabled)
3373 ironlake_pfit_disable(crtc, true);
3374 }
3375 }
3376
3377 static void intel_fdi_normal_train(struct drm_crtc *crtc)
3378 {
3379 struct drm_device *dev = crtc->dev;
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3382 int pipe = intel_crtc->pipe;
3383 i915_reg_t reg;
3384 u32 temp;
3385
3386 /* enable normal train */
3387 reg = FDI_TX_CTL(pipe);
3388 temp = I915_READ(reg);
3389 if (IS_IVYBRIDGE(dev)) {
3390 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3391 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
3392 } else {
3393 temp &= ~FDI_LINK_TRAIN_NONE;
3394 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
3395 }
3396 I915_WRITE(reg, temp);
3397
3398 reg = FDI_RX_CTL(pipe);
3399 temp = I915_READ(reg);
3400 if (HAS_PCH_CPT(dev)) {
3401 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3402 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3403 } else {
3404 temp &= ~FDI_LINK_TRAIN_NONE;
3405 temp |= FDI_LINK_TRAIN_NONE;
3406 }
3407 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3408
3409 /* wait one idle pattern time */
3410 POSTING_READ(reg);
3411 udelay(1000);
3412
3413 /* IVB wants error correction enabled */
3414 if (IS_IVYBRIDGE(dev))
3415 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3416 FDI_FE_ERRC_ENABLE);
3417 }
3418
3419 /* The FDI link training functions for ILK/Ibexpeak. */
3420 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3421 {
3422 struct drm_device *dev = crtc->dev;
3423 struct drm_i915_private *dev_priv = dev->dev_private;
3424 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3425 int pipe = intel_crtc->pipe;
3426 i915_reg_t reg;
3427 u32 temp, tries;
3428
3429 /* FDI needs bits from pipe first */
3430 assert_pipe_enabled(dev_priv, pipe);
3431
3432 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3433 for train result */
3434 reg = FDI_RX_IMR(pipe);
3435 temp = I915_READ(reg);
3436 temp &= ~FDI_RX_SYMBOL_LOCK;
3437 temp &= ~FDI_RX_BIT_LOCK;
3438 I915_WRITE(reg, temp);
3439 I915_READ(reg);
3440 udelay(150);
3441
3442 /* enable CPU FDI TX and PCH FDI RX */
3443 reg = FDI_TX_CTL(pipe);
3444 temp = I915_READ(reg);
3445 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3446 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3447 temp &= ~FDI_LINK_TRAIN_NONE;
3448 temp |= FDI_LINK_TRAIN_PATTERN_1;
3449 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3450
3451 reg = FDI_RX_CTL(pipe);
3452 temp = I915_READ(reg);
3453 temp &= ~FDI_LINK_TRAIN_NONE;
3454 temp |= FDI_LINK_TRAIN_PATTERN_1;
3455 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3456
3457 POSTING_READ(reg);
3458 udelay(150);
3459
3460 /* Ironlake workaround, enable clock pointer after FDI enable*/
3461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3462 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3463 FDI_RX_PHASE_SYNC_POINTER_EN);
3464
3465 reg = FDI_RX_IIR(pipe);
3466 for (tries = 0; tries < 5; tries++) {
3467 temp = I915_READ(reg);
3468 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3469
3470 if ((temp & FDI_RX_BIT_LOCK)) {
3471 DRM_DEBUG_KMS("FDI train 1 done.\n");
3472 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3473 break;
3474 }
3475 }
3476 if (tries == 5)
3477 DRM_ERROR("FDI train 1 fail!\n");
3478
3479 /* Train 2 */
3480 reg = FDI_TX_CTL(pipe);
3481 temp = I915_READ(reg);
3482 temp &= ~FDI_LINK_TRAIN_NONE;
3483 temp |= FDI_LINK_TRAIN_PATTERN_2;
3484 I915_WRITE(reg, temp);
3485
3486 reg = FDI_RX_CTL(pipe);
3487 temp = I915_READ(reg);
3488 temp &= ~FDI_LINK_TRAIN_NONE;
3489 temp |= FDI_LINK_TRAIN_PATTERN_2;
3490 I915_WRITE(reg, temp);
3491
3492 POSTING_READ(reg);
3493 udelay(150);
3494
3495 reg = FDI_RX_IIR(pipe);
3496 for (tries = 0; tries < 5; tries++) {
3497 temp = I915_READ(reg);
3498 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3499
3500 if (temp & FDI_RX_SYMBOL_LOCK) {
3501 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3502 DRM_DEBUG_KMS("FDI train 2 done.\n");
3503 break;
3504 }
3505 }
3506 if (tries == 5)
3507 DRM_ERROR("FDI train 2 fail!\n");
3508
3509 DRM_DEBUG_KMS("FDI train done\n");
3510
3511 }
3512
3513 static const int snb_b_fdi_train_param[] = {
3514 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3515 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3516 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3517 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3518 };
3519
3520 /* The FDI link training functions for SNB/Cougarpoint. */
3521 static void gen6_fdi_link_train(struct drm_crtc *crtc)
3522 {
3523 struct drm_device *dev = crtc->dev;
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526 int pipe = intel_crtc->pipe;
3527 i915_reg_t reg;
3528 u32 temp, i, retry;
3529
3530 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3531 for train result */
3532 reg = FDI_RX_IMR(pipe);
3533 temp = I915_READ(reg);
3534 temp &= ~FDI_RX_SYMBOL_LOCK;
3535 temp &= ~FDI_RX_BIT_LOCK;
3536 I915_WRITE(reg, temp);
3537
3538 POSTING_READ(reg);
3539 udelay(150);
3540
3541 /* enable CPU FDI TX and PCH FDI RX */
3542 reg = FDI_TX_CTL(pipe);
3543 temp = I915_READ(reg);
3544 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3545 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3549 /* SNB-B */
3550 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3551 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3552
3553 I915_WRITE(FDI_RX_MISC(pipe),
3554 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3555
3556 reg = FDI_RX_CTL(pipe);
3557 temp = I915_READ(reg);
3558 if (HAS_PCH_CPT(dev)) {
3559 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3560 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3561 } else {
3562 temp &= ~FDI_LINK_TRAIN_NONE;
3563 temp |= FDI_LINK_TRAIN_PATTERN_1;
3564 }
3565 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3566
3567 POSTING_READ(reg);
3568 udelay(150);
3569
3570 for (i = 0; i < 4; i++) {
3571 reg = FDI_TX_CTL(pipe);
3572 temp = I915_READ(reg);
3573 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3574 temp |= snb_b_fdi_train_param[i];
3575 I915_WRITE(reg, temp);
3576
3577 POSTING_READ(reg);
3578 udelay(500);
3579
3580 for (retry = 0; retry < 5; retry++) {
3581 reg = FDI_RX_IIR(pipe);
3582 temp = I915_READ(reg);
3583 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3584 if (temp & FDI_RX_BIT_LOCK) {
3585 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3586 DRM_DEBUG_KMS("FDI train 1 done.\n");
3587 break;
3588 }
3589 udelay(50);
3590 }
3591 if (retry < 5)
3592 break;
3593 }
3594 if (i == 4)
3595 DRM_ERROR("FDI train 1 fail!\n");
3596
3597 /* Train 2 */
3598 reg = FDI_TX_CTL(pipe);
3599 temp = I915_READ(reg);
3600 temp &= ~FDI_LINK_TRAIN_NONE;
3601 temp |= FDI_LINK_TRAIN_PATTERN_2;
3602 if (IS_GEN6(dev)) {
3603 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3604 /* SNB-B */
3605 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3606 }
3607 I915_WRITE(reg, temp);
3608
3609 reg = FDI_RX_CTL(pipe);
3610 temp = I915_READ(reg);
3611 if (HAS_PCH_CPT(dev)) {
3612 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3613 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3614 } else {
3615 temp &= ~FDI_LINK_TRAIN_NONE;
3616 temp |= FDI_LINK_TRAIN_PATTERN_2;
3617 }
3618 I915_WRITE(reg, temp);
3619
3620 POSTING_READ(reg);
3621 udelay(150);
3622
3623 for (i = 0; i < 4; i++) {
3624 reg = FDI_TX_CTL(pipe);
3625 temp = I915_READ(reg);
3626 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3627 temp |= snb_b_fdi_train_param[i];
3628 I915_WRITE(reg, temp);
3629
3630 POSTING_READ(reg);
3631 udelay(500);
3632
3633 for (retry = 0; retry < 5; retry++) {
3634 reg = FDI_RX_IIR(pipe);
3635 temp = I915_READ(reg);
3636 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3637 if (temp & FDI_RX_SYMBOL_LOCK) {
3638 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3639 DRM_DEBUG_KMS("FDI train 2 done.\n");
3640 break;
3641 }
3642 udelay(50);
3643 }
3644 if (retry < 5)
3645 break;
3646 }
3647 if (i == 4)
3648 DRM_ERROR("FDI train 2 fail!\n");
3649
3650 DRM_DEBUG_KMS("FDI train done.\n");
3651 }
3652
3653 /* Manual link training for Ivy Bridge A0 parts */
3654 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3655 {
3656 struct drm_device *dev = crtc->dev;
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3659 int pipe = intel_crtc->pipe;
3660 i915_reg_t reg;
3661 u32 temp, i, j;
3662
3663 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3664 for train result */
3665 reg = FDI_RX_IMR(pipe);
3666 temp = I915_READ(reg);
3667 temp &= ~FDI_RX_SYMBOL_LOCK;
3668 temp &= ~FDI_RX_BIT_LOCK;
3669 I915_WRITE(reg, temp);
3670
3671 POSTING_READ(reg);
3672 udelay(150);
3673
3674 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3675 I915_READ(FDI_RX_IIR(pipe)));
3676
3677 /* Try each vswing and preemphasis setting twice before moving on */
3678 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3679 /* disable first in case we need to retry */
3680 reg = FDI_TX_CTL(pipe);
3681 temp = I915_READ(reg);
3682 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3683 temp &= ~FDI_TX_ENABLE;
3684 I915_WRITE(reg, temp);
3685
3686 reg = FDI_RX_CTL(pipe);
3687 temp = I915_READ(reg);
3688 temp &= ~FDI_LINK_TRAIN_AUTO;
3689 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3690 temp &= ~FDI_RX_ENABLE;
3691 I915_WRITE(reg, temp);
3692
3693 /* enable CPU FDI TX and PCH FDI RX */
3694 reg = FDI_TX_CTL(pipe);
3695 temp = I915_READ(reg);
3696 temp &= ~FDI_DP_PORT_WIDTH_MASK;
3697 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3698 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
3699 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3700 temp |= snb_b_fdi_train_param[j/2];
3701 temp |= FDI_COMPOSITE_SYNC;
3702 I915_WRITE(reg, temp | FDI_TX_ENABLE);
3703
3704 I915_WRITE(FDI_RX_MISC(pipe),
3705 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3706
3707 reg = FDI_RX_CTL(pipe);
3708 temp = I915_READ(reg);
3709 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3710 temp |= FDI_COMPOSITE_SYNC;
3711 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3712
3713 POSTING_READ(reg);
3714 udelay(1); /* should be 0.5us */
3715
3716 for (i = 0; i < 4; i++) {
3717 reg = FDI_RX_IIR(pipe);
3718 temp = I915_READ(reg);
3719 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3720
3721 if (temp & FDI_RX_BIT_LOCK ||
3722 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3723 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3724 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3725 i);
3726 break;
3727 }
3728 udelay(1); /* should be 0.5us */
3729 }
3730 if (i == 4) {
3731 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3732 continue;
3733 }
3734
3735 /* Train 2 */
3736 reg = FDI_TX_CTL(pipe);
3737 temp = I915_READ(reg);
3738 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3739 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3740 I915_WRITE(reg, temp);
3741
3742 reg = FDI_RX_CTL(pipe);
3743 temp = I915_READ(reg);
3744 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3745 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3746 I915_WRITE(reg, temp);
3747
3748 POSTING_READ(reg);
3749 udelay(2); /* should be 1.5us */
3750
3751 for (i = 0; i < 4; i++) {
3752 reg = FDI_RX_IIR(pipe);
3753 temp = I915_READ(reg);
3754 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3755
3756 if (temp & FDI_RX_SYMBOL_LOCK ||
3757 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3758 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3759 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3760 i);
3761 goto train_done;
3762 }
3763 udelay(2); /* should be 1.5us */
3764 }
3765 if (i == 4)
3766 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
3767 }
3768
3769 train_done:
3770 DRM_DEBUG_KMS("FDI train done.\n");
3771 }
3772
3773 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
3774 {
3775 struct drm_device *dev = intel_crtc->base.dev;
3776 struct drm_i915_private *dev_priv = dev->dev_private;
3777 int pipe = intel_crtc->pipe;
3778 i915_reg_t reg;
3779 u32 temp;
3780
3781 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
3785 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
3786 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3787 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3788
3789 POSTING_READ(reg);
3790 udelay(200);
3791
3792 /* Switch from Rawclk to PCDclk */
3793 temp = I915_READ(reg);
3794 I915_WRITE(reg, temp | FDI_PCDCLK);
3795
3796 POSTING_READ(reg);
3797 udelay(200);
3798
3799 /* Enable CPU FDI TX PLL, always on for Ironlake */
3800 reg = FDI_TX_CTL(pipe);
3801 temp = I915_READ(reg);
3802 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3803 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
3804
3805 POSTING_READ(reg);
3806 udelay(100);
3807 }
3808 }
3809
3810 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3811 {
3812 struct drm_device *dev = intel_crtc->base.dev;
3813 struct drm_i915_private *dev_priv = dev->dev_private;
3814 int pipe = intel_crtc->pipe;
3815 i915_reg_t reg;
3816 u32 temp;
3817
3818 /* Switch from PCDclk to Rawclk */
3819 reg = FDI_RX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3822
3823 /* Disable CPU FDI TX PLL */
3824 reg = FDI_TX_CTL(pipe);
3825 temp = I915_READ(reg);
3826 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3827
3828 POSTING_READ(reg);
3829 udelay(100);
3830
3831 reg = FDI_RX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3834
3835 /* Wait for the clocks to turn off. */
3836 POSTING_READ(reg);
3837 udelay(100);
3838 }
3839
3840 static void ironlake_fdi_disable(struct drm_crtc *crtc)
3841 {
3842 struct drm_device *dev = crtc->dev;
3843 struct drm_i915_private *dev_priv = dev->dev_private;
3844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3845 int pipe = intel_crtc->pipe;
3846 i915_reg_t reg;
3847 u32 temp;
3848
3849 /* disable CPU FDI tx and PCH FDI rx */
3850 reg = FDI_TX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3853 POSTING_READ(reg);
3854
3855 reg = FDI_RX_CTL(pipe);
3856 temp = I915_READ(reg);
3857 temp &= ~(0x7 << 16);
3858 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3859 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3860
3861 POSTING_READ(reg);
3862 udelay(100);
3863
3864 /* Ironlake workaround, disable clock pointer after downing FDI */
3865 if (HAS_PCH_IBX(dev))
3866 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3867
3868 /* still set train pattern 1 */
3869 reg = FDI_TX_CTL(pipe);
3870 temp = I915_READ(reg);
3871 temp &= ~FDI_LINK_TRAIN_NONE;
3872 temp |= FDI_LINK_TRAIN_PATTERN_1;
3873 I915_WRITE(reg, temp);
3874
3875 reg = FDI_RX_CTL(pipe);
3876 temp = I915_READ(reg);
3877 if (HAS_PCH_CPT(dev)) {
3878 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3879 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3880 } else {
3881 temp &= ~FDI_LINK_TRAIN_NONE;
3882 temp |= FDI_LINK_TRAIN_PATTERN_1;
3883 }
3884 /* BPC in FDI rx is consistent with that in PIPECONF */
3885 temp &= ~(0x07 << 16);
3886 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
3887 I915_WRITE(reg, temp);
3888
3889 POSTING_READ(reg);
3890 udelay(100);
3891 }
3892
3893 bool intel_has_pending_fb_unpin(struct drm_device *dev)
3894 {
3895 struct intel_crtc *crtc;
3896
3897 /* Note that we don't need to be called with mode_config.lock here
3898 * as our list of CRTC objects is static for the lifetime of the
3899 * device and so cannot disappear as we iterate. Similarly, we can
3900 * happily treat the predicates as racy, atomic checks as userspace
3901 * cannot claim and pin a new fb without at least acquring the
3902 * struct_mutex and so serialising with us.
3903 */
3904 for_each_intel_crtc(dev, crtc) {
3905 if (atomic_read(&crtc->unpin_work_count) == 0)
3906 continue;
3907
3908 if (crtc->unpin_work)
3909 intel_wait_for_vblank(dev, crtc->pipe);
3910
3911 return true;
3912 }
3913
3914 return false;
3915 }
3916
3917 static void page_flip_completed(struct intel_crtc *intel_crtc)
3918 {
3919 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3920 struct intel_unpin_work *work = intel_crtc->unpin_work;
3921
3922 /* ensure that the unpin work is consistent wrt ->pending. */
3923 smp_rmb();
3924 intel_crtc->unpin_work = NULL;
3925
3926 if (work->event)
3927 drm_send_vblank_event(intel_crtc->base.dev,
3928 intel_crtc->pipe,
3929 work->event);
3930
3931 drm_crtc_vblank_put(&intel_crtc->base);
3932
3933 wake_up_all(&dev_priv->pending_flip_queue);
3934 queue_work(dev_priv->wq, &work->work);
3935
3936 trace_i915_flip_complete(intel_crtc->plane,
3937 work->pending_flip_obj);
3938 }
3939
3940 static int intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
3941 {
3942 struct drm_device *dev = crtc->dev;
3943 struct drm_i915_private *dev_priv = dev->dev_private;
3944 long ret;
3945
3946 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
3947
3948 ret = wait_event_interruptible_timeout(
3949 dev_priv->pending_flip_queue,
3950 !intel_crtc_has_pending_flip(crtc),
3951 60*HZ);
3952
3953 if (ret < 0)
3954 return ret;
3955
3956 if (ret == 0) {
3957 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3958
3959 spin_lock_irq(&dev->event_lock);
3960 if (intel_crtc->unpin_work) {
3961 WARN_ONCE(1, "Removing stuck page flip\n");
3962 page_flip_completed(intel_crtc);
3963 }
3964 spin_unlock_irq(&dev->event_lock);
3965 }
3966
3967 return 0;
3968 }
3969
3970 static void lpt_disable_iclkip(struct drm_i915_private *dev_priv)
3971 {
3972 u32 temp;
3973
3974 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3975
3976 mutex_lock(&dev_priv->sb_lock);
3977
3978 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
3979 temp |= SBI_SSCCTL_DISABLE;
3980 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
3981
3982 mutex_unlock(&dev_priv->sb_lock);
3983 }
3984
3985 /* Program iCLKIP clock to the desired frequency */
3986 static void lpt_program_iclkip(struct drm_crtc *crtc)
3987 {
3988 struct drm_device *dev = crtc->dev;
3989 struct drm_i915_private *dev_priv = dev->dev_private;
3990 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
3991 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3992 u32 temp;
3993
3994 lpt_disable_iclkip(dev_priv);
3995
3996 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3997 if (clock == 20000) {
3998 auxdiv = 1;
3999 divsel = 0x41;
4000 phaseinc = 0x20;
4001 } else {
4002 /* The iCLK virtual clock root frequency is in MHz,
4003 * but the adjusted_mode->crtc_clock in in KHz. To get the
4004 * divisors, it is necessary to divide one by another, so we
4005 * convert the virtual clock precision to KHz here for higher
4006 * precision.
4007 */
4008 u32 iclk_virtual_root_freq = 172800 * 1000;
4009 u32 iclk_pi_range = 64;
4010 u32 desired_divisor, msb_divisor_value, pi_value;
4011
4012 desired_divisor = DIV_ROUND_CLOSEST(iclk_virtual_root_freq, clock);
4013 msb_divisor_value = desired_divisor / iclk_pi_range;
4014 pi_value = desired_divisor % iclk_pi_range;
4015
4016 auxdiv = 0;
4017 divsel = msb_divisor_value - 2;
4018 phaseinc = pi_value;
4019 }
4020
4021 /* This should not happen with any sane values */
4022 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4023 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4024 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4025 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4026
4027 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
4028 clock,
4029 auxdiv,
4030 divsel,
4031 phasedir,
4032 phaseinc);
4033
4034 mutex_lock(&dev_priv->sb_lock);
4035
4036 /* Program SSCDIVINTPHASE6 */
4037 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
4038 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4039 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4040 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4041 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4042 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4043 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
4044 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
4045
4046 /* Program SSCAUXDIV */
4047 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
4048 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4049 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
4050 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
4051
4052 /* Enable modulator and associated divider */
4053 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
4054 temp &= ~SBI_SSCCTL_DISABLE;
4055 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
4056
4057 mutex_unlock(&dev_priv->sb_lock);
4058
4059 /* Wait for initialization time */
4060 udelay(24);
4061
4062 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
4063 }
4064
4065 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4066 enum pipe pch_transcoder)
4067 {
4068 struct drm_device *dev = crtc->base.dev;
4069 struct drm_i915_private *dev_priv = dev->dev_private;
4070 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
4071
4072 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4073 I915_READ(HTOTAL(cpu_transcoder)));
4074 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4075 I915_READ(HBLANK(cpu_transcoder)));
4076 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4077 I915_READ(HSYNC(cpu_transcoder)));
4078
4079 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4080 I915_READ(VTOTAL(cpu_transcoder)));
4081 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4082 I915_READ(VBLANK(cpu_transcoder)));
4083 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4084 I915_READ(VSYNC(cpu_transcoder)));
4085 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4086 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4087 }
4088
4089 static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
4090 {
4091 struct drm_i915_private *dev_priv = dev->dev_private;
4092 uint32_t temp;
4093
4094 temp = I915_READ(SOUTH_CHICKEN1);
4095 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
4096 return;
4097
4098 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4099 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4100
4101 temp &= ~FDI_BC_BIFURCATION_SELECT;
4102 if (enable)
4103 temp |= FDI_BC_BIFURCATION_SELECT;
4104
4105 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
4106 I915_WRITE(SOUTH_CHICKEN1, temp);
4107 POSTING_READ(SOUTH_CHICKEN1);
4108 }
4109
4110 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4111 {
4112 struct drm_device *dev = intel_crtc->base.dev;
4113
4114 switch (intel_crtc->pipe) {
4115 case PIPE_A:
4116 break;
4117 case PIPE_B:
4118 if (intel_crtc->config->fdi_lanes > 2)
4119 cpt_set_fdi_bc_bifurcation(dev, false);
4120 else
4121 cpt_set_fdi_bc_bifurcation(dev, true);
4122
4123 break;
4124 case PIPE_C:
4125 cpt_set_fdi_bc_bifurcation(dev, true);
4126
4127 break;
4128 default:
4129 BUG();
4130 }
4131 }
4132
4133 /* Return which DP Port should be selected for Transcoder DP control */
4134 static enum port
4135 intel_trans_dp_port_sel(struct drm_crtc *crtc)
4136 {
4137 struct drm_device *dev = crtc->dev;
4138 struct intel_encoder *encoder;
4139
4140 for_each_encoder_on_crtc(dev, crtc, encoder) {
4141 if (encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
4142 encoder->type == INTEL_OUTPUT_EDP)
4143 return enc_to_dig_port(&encoder->base)->port;
4144 }
4145
4146 return -1;
4147 }
4148
4149 /*
4150 * Enable PCH resources required for PCH ports:
4151 * - PCH PLLs
4152 * - FDI training & RX/TX
4153 * - update transcoder timings
4154 * - DP transcoding bits
4155 * - transcoder
4156 */
4157 static void ironlake_pch_enable(struct drm_crtc *crtc)
4158 {
4159 struct drm_device *dev = crtc->dev;
4160 struct drm_i915_private *dev_priv = dev->dev_private;
4161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4162 int pipe = intel_crtc->pipe;
4163 u32 temp;
4164
4165 assert_pch_transcoder_disabled(dev_priv, pipe);
4166
4167 if (IS_IVYBRIDGE(dev))
4168 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4169
4170 /* Write the TU size bits before fdi link training, so that error
4171 * detection works. */
4172 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4173 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4174
4175 /*
4176 * Sometimes spurious CPU pipe underruns happen during FDI
4177 * training, at least with VGA+HDMI cloning. Suppress them.
4178 */
4179 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4180
4181 /* For PCH output, training FDI link */
4182 dev_priv->display.fdi_link_train(crtc);
4183
4184 /* We need to program the right clock selection before writing the pixel
4185 * mutliplier into the DPLL. */
4186 if (HAS_PCH_CPT(dev)) {
4187 u32 sel;
4188
4189 temp = I915_READ(PCH_DPLL_SEL);
4190 temp |= TRANS_DPLL_ENABLE(pipe);
4191 sel = TRANS_DPLLB_SEL(pipe);
4192 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
4193 temp |= sel;
4194 else
4195 temp &= ~sel;
4196 I915_WRITE(PCH_DPLL_SEL, temp);
4197 }
4198
4199 /* XXX: pch pll's can be enabled any time before we enable the PCH
4200 * transcoder, and we actually should do this to not upset any PCH
4201 * transcoder that already use the clock when we share it.
4202 *
4203 * Note that enable_shared_dpll tries to do the right thing, but
4204 * get_shared_dpll unconditionally resets the pll - we need that to have
4205 * the right LVDS enable sequence. */
4206 intel_enable_shared_dpll(intel_crtc);
4207
4208 /* set transcoder timing, panel must allow it */
4209 assert_panel_unlocked(dev_priv, pipe);
4210 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
4211
4212 intel_fdi_normal_train(crtc);
4213
4214 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4215
4216 /* For PCH DP, enable TRANS_DP_CTL */
4217 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
4218 const struct drm_display_mode *adjusted_mode =
4219 &intel_crtc->config->base.adjusted_mode;
4220 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
4221 i915_reg_t reg = TRANS_DP_CTL(pipe);
4222 temp = I915_READ(reg);
4223 temp &= ~(TRANS_DP_PORT_SEL_MASK |
4224 TRANS_DP_SYNC_MASK |
4225 TRANS_DP_BPC_MASK);
4226 temp |= TRANS_DP_OUTPUT_ENABLE;
4227 temp |= bpc << 9; /* same format but at 11:9 */
4228
4229 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
4230 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
4231 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
4232 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
4233
4234 switch (intel_trans_dp_port_sel(crtc)) {
4235 case PORT_B:
4236 temp |= TRANS_DP_PORT_SEL_B;
4237 break;
4238 case PORT_C:
4239 temp |= TRANS_DP_PORT_SEL_C;
4240 break;
4241 case PORT_D:
4242 temp |= TRANS_DP_PORT_SEL_D;
4243 break;
4244 default:
4245 BUG();
4246 }
4247
4248 I915_WRITE(reg, temp);
4249 }
4250
4251 ironlake_enable_pch_transcoder(dev_priv, pipe);
4252 }
4253
4254 static void lpt_pch_enable(struct drm_crtc *crtc)
4255 {
4256 struct drm_device *dev = crtc->dev;
4257 struct drm_i915_private *dev_priv = dev->dev_private;
4258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4259 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
4260
4261 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
4262
4263 lpt_program_iclkip(crtc);
4264
4265 /* Set transcoder timing. */
4266 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
4267
4268 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
4269 }
4270
4271 struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4272 struct intel_crtc_state *crtc_state)
4273 {
4274 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
4275 struct intel_shared_dpll *pll;
4276 struct intel_shared_dpll_config *shared_dpll;
4277 enum intel_dpll_id i;
4278 int max = dev_priv->num_shared_dpll;
4279
4280 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4281
4282 if (HAS_PCH_IBX(dev_priv->dev)) {
4283 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
4284 i = (enum intel_dpll_id) crtc->pipe;
4285 pll = &dev_priv->shared_dplls[i];
4286
4287 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4288 crtc->base.base.id, pll->name);
4289
4290 WARN_ON(shared_dpll[i].crtc_mask);
4291
4292 goto found;
4293 }
4294
4295 if (IS_BROXTON(dev_priv->dev)) {
4296 /* PLL is attached to port in bxt */
4297 struct intel_encoder *encoder;
4298 struct intel_digital_port *intel_dig_port;
4299
4300 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4301 if (WARN_ON(!encoder))
4302 return NULL;
4303
4304 intel_dig_port = enc_to_dig_port(&encoder->base);
4305 /* 1:1 mapping between ports and PLLs */
4306 i = (enum intel_dpll_id)intel_dig_port->port;
4307 pll = &dev_priv->shared_dplls[i];
4308 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4309 crtc->base.base.id, pll->name);
4310 WARN_ON(shared_dpll[i].crtc_mask);
4311
4312 goto found;
4313 } else if (INTEL_INFO(dev_priv)->gen < 9 && HAS_DDI(dev_priv))
4314 /* Do not consider SPLL */
4315 max = 2;
4316
4317 for (i = 0; i < max; i++) {
4318 pll = &dev_priv->shared_dplls[i];
4319
4320 /* Only want to check enabled timings first */
4321 if (shared_dpll[i].crtc_mask == 0)
4322 continue;
4323
4324 if (memcmp(&crtc_state->dpll_hw_state,
4325 &shared_dpll[i].hw_state,
4326 sizeof(crtc_state->dpll_hw_state)) == 0) {
4327 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
4328 crtc->base.base.id, pll->name,
4329 shared_dpll[i].crtc_mask,
4330 pll->active);
4331 goto found;
4332 }
4333 }
4334
4335 /* Ok no matching timings, maybe there's a free one? */
4336 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4337 pll = &dev_priv->shared_dplls[i];
4338 if (shared_dpll[i].crtc_mask == 0) {
4339 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4340 crtc->base.base.id, pll->name);
4341 goto found;
4342 }
4343 }
4344
4345 return NULL;
4346
4347 found:
4348 if (shared_dpll[i].crtc_mask == 0)
4349 shared_dpll[i].hw_state =
4350 crtc_state->dpll_hw_state;
4351
4352 crtc_state->shared_dpll = i;
4353 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4354 pipe_name(crtc->pipe));
4355
4356 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
4357
4358 return pll;
4359 }
4360
4361 static void intel_shared_dpll_commit(struct drm_atomic_state *state)
4362 {
4363 struct drm_i915_private *dev_priv = to_i915(state->dev);
4364 struct intel_shared_dpll_config *shared_dpll;
4365 struct intel_shared_dpll *pll;
4366 enum intel_dpll_id i;
4367
4368 if (!to_intel_atomic_state(state)->dpll_set)
4369 return;
4370
4371 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
4372 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4373 pll = &dev_priv->shared_dplls[i];
4374 pll->config = shared_dpll[i];
4375 }
4376 }
4377
4378 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
4379 {
4380 struct drm_i915_private *dev_priv = dev->dev_private;
4381 i915_reg_t dslreg = PIPEDSL(pipe);
4382 u32 temp;
4383
4384 temp = I915_READ(dslreg);
4385 udelay(500);
4386 if (wait_for(I915_READ(dslreg) != temp, 5)) {
4387 if (wait_for(I915_READ(dslreg) != temp, 5))
4388 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
4389 }
4390 }
4391
4392 static int
4393 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4394 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4395 int src_w, int src_h, int dst_w, int dst_h)
4396 {
4397 struct intel_crtc_scaler_state *scaler_state =
4398 &crtc_state->scaler_state;
4399 struct intel_crtc *intel_crtc =
4400 to_intel_crtc(crtc_state->base.crtc);
4401 int need_scaling;
4402
4403 need_scaling = intel_rotation_90_or_270(rotation) ?
4404 (src_h != dst_w || src_w != dst_h):
4405 (src_w != dst_w || src_h != dst_h);
4406
4407 /*
4408 * if plane is being disabled or scaler is no more required or force detach
4409 * - free scaler binded to this plane/crtc
4410 * - in order to do this, update crtc->scaler_usage
4411 *
4412 * Here scaler state in crtc_state is set free so that
4413 * scaler can be assigned to other user. Actual register
4414 * update to free the scaler is done in plane/panel-fit programming.
4415 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4416 */
4417 if (force_detach || !need_scaling) {
4418 if (*scaler_id >= 0) {
4419 scaler_state->scaler_users &= ~(1 << scaler_user);
4420 scaler_state->scalers[*scaler_id].in_use = 0;
4421
4422 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4423 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4424 intel_crtc->pipe, scaler_user, *scaler_id,
4425 scaler_state->scaler_users);
4426 *scaler_id = -1;
4427 }
4428 return 0;
4429 }
4430
4431 /* range checks */
4432 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4433 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4434
4435 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4436 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4437 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
4438 "size is out of scaler range\n",
4439 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
4440 return -EINVAL;
4441 }
4442
4443 /* mark this plane as a scaler user in crtc_state */
4444 scaler_state->scaler_users |= (1 << scaler_user);
4445 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4446 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4447 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4448 scaler_state->scaler_users);
4449
4450 return 0;
4451 }
4452
4453 /**
4454 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4455 *
4456 * @state: crtc's scaler state
4457 *
4458 * Return
4459 * 0 - scaler_usage updated successfully
4460 * error - requested scaling cannot be supported or other error condition
4461 */
4462 int skl_update_scaler_crtc(struct intel_crtc_state *state)
4463 {
4464 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4465 const struct drm_display_mode *adjusted_mode = &state->base.adjusted_mode;
4466
4467 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4468 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4469
4470 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
4471 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4472 state->pipe_src_w, state->pipe_src_h,
4473 adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
4474 }
4475
4476 /**
4477 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4478 *
4479 * @state: crtc's scaler state
4480 * @plane_state: atomic plane state to update
4481 *
4482 * Return
4483 * 0 - scaler_usage updated successfully
4484 * error - requested scaling cannot be supported or other error condition
4485 */
4486 static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4487 struct intel_plane_state *plane_state)
4488 {
4489
4490 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
4491 struct intel_plane *intel_plane =
4492 to_intel_plane(plane_state->base.plane);
4493 struct drm_framebuffer *fb = plane_state->base.fb;
4494 int ret;
4495
4496 bool force_detach = !fb || !plane_state->visible;
4497
4498 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4499 intel_plane->base.base.id, intel_crtc->pipe,
4500 drm_plane_index(&intel_plane->base));
4501
4502 ret = skl_update_scaler(crtc_state, force_detach,
4503 drm_plane_index(&intel_plane->base),
4504 &plane_state->scaler_id,
4505 plane_state->base.rotation,
4506 drm_rect_width(&plane_state->src) >> 16,
4507 drm_rect_height(&plane_state->src) >> 16,
4508 drm_rect_width(&plane_state->dst),
4509 drm_rect_height(&plane_state->dst));
4510
4511 if (ret || plane_state->scaler_id < 0)
4512 return ret;
4513
4514 /* check colorkey */
4515 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
4516 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
4517 intel_plane->base.base.id);
4518 return -EINVAL;
4519 }
4520
4521 /* Check src format */
4522 switch (fb->pixel_format) {
4523 case DRM_FORMAT_RGB565:
4524 case DRM_FORMAT_XBGR8888:
4525 case DRM_FORMAT_XRGB8888:
4526 case DRM_FORMAT_ABGR8888:
4527 case DRM_FORMAT_ARGB8888:
4528 case DRM_FORMAT_XRGB2101010:
4529 case DRM_FORMAT_XBGR2101010:
4530 case DRM_FORMAT_YUYV:
4531 case DRM_FORMAT_YVYU:
4532 case DRM_FORMAT_UYVY:
4533 case DRM_FORMAT_VYUY:
4534 break;
4535 default:
4536 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4537 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4538 return -EINVAL;
4539 }
4540
4541 return 0;
4542 }
4543
4544 static void skylake_scaler_disable(struct intel_crtc *crtc)
4545 {
4546 int i;
4547
4548 for (i = 0; i < crtc->num_scalers; i++)
4549 skl_detach_scaler(crtc, i);
4550 }
4551
4552 static void skylake_pfit_enable(struct intel_crtc *crtc)
4553 {
4554 struct drm_device *dev = crtc->base.dev;
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556 int pipe = crtc->pipe;
4557 struct intel_crtc_scaler_state *scaler_state =
4558 &crtc->config->scaler_state;
4559
4560 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4561
4562 if (crtc->config->pch_pfit.enabled) {
4563 int id;
4564
4565 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4566 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4567 return;
4568 }
4569
4570 id = scaler_state->scaler_id;
4571 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4572 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4573 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4574 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4575
4576 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
4577 }
4578 }
4579
4580 static void ironlake_pfit_enable(struct intel_crtc *crtc)
4581 {
4582 struct drm_device *dev = crtc->base.dev;
4583 struct drm_i915_private *dev_priv = dev->dev_private;
4584 int pipe = crtc->pipe;
4585
4586 if (crtc->config->pch_pfit.enabled) {
4587 /* Force use of hard-coded filter coefficients
4588 * as some pre-programmed values are broken,
4589 * e.g. x201.
4590 */
4591 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4592 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4593 PF_PIPE_SEL_IVB(pipe));
4594 else
4595 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
4596 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4597 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
4598 }
4599 }
4600
4601 void hsw_enable_ips(struct intel_crtc *crtc)
4602 {
4603 struct drm_device *dev = crtc->base.dev;
4604 struct drm_i915_private *dev_priv = dev->dev_private;
4605
4606 if (!crtc->config->ips_enabled)
4607 return;
4608
4609 /* We can only enable IPS after we enable a plane and wait for a vblank */
4610 intel_wait_for_vblank(dev, crtc->pipe);
4611
4612 assert_plane_enabled(dev_priv, crtc->plane);
4613 if (IS_BROADWELL(dev)) {
4614 mutex_lock(&dev_priv->rps.hw_lock);
4615 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4616 mutex_unlock(&dev_priv->rps.hw_lock);
4617 /* Quoting Art Runyan: "its not safe to expect any particular
4618 * value in IPS_CTL bit 31 after enabling IPS through the
4619 * mailbox." Moreover, the mailbox may return a bogus state,
4620 * so we need to just enable it and continue on.
4621 */
4622 } else {
4623 I915_WRITE(IPS_CTL, IPS_ENABLE);
4624 /* The bit only becomes 1 in the next vblank, so this wait here
4625 * is essentially intel_wait_for_vblank. If we don't have this
4626 * and don't wait for vblanks until the end of crtc_enable, then
4627 * the HW state readout code will complain that the expected
4628 * IPS_CTL value is not the one we read. */
4629 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4630 DRM_ERROR("Timed out waiting for IPS enable\n");
4631 }
4632 }
4633
4634 void hsw_disable_ips(struct intel_crtc *crtc)
4635 {
4636 struct drm_device *dev = crtc->base.dev;
4637 struct drm_i915_private *dev_priv = dev->dev_private;
4638
4639 if (!crtc->config->ips_enabled)
4640 return;
4641
4642 assert_plane_enabled(dev_priv, crtc->plane);
4643 if (IS_BROADWELL(dev)) {
4644 mutex_lock(&dev_priv->rps.hw_lock);
4645 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4646 mutex_unlock(&dev_priv->rps.hw_lock);
4647 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4648 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4649 DRM_ERROR("Timed out waiting for IPS disable\n");
4650 } else {
4651 I915_WRITE(IPS_CTL, 0);
4652 POSTING_READ(IPS_CTL);
4653 }
4654
4655 /* We need to wait for a vblank before we can disable the plane. */
4656 intel_wait_for_vblank(dev, crtc->pipe);
4657 }
4658
4659 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4660 static void intel_crtc_load_lut(struct drm_crtc *crtc)
4661 {
4662 struct drm_device *dev = crtc->dev;
4663 struct drm_i915_private *dev_priv = dev->dev_private;
4664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4665 enum pipe pipe = intel_crtc->pipe;
4666 int i;
4667 bool reenable_ips = false;
4668
4669 /* The clocks have to be on to load the palette. */
4670 if (!crtc->state->active)
4671 return;
4672
4673 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
4674 if (intel_crtc->config->has_dsi_encoder)
4675 assert_dsi_pll_enabled(dev_priv);
4676 else
4677 assert_pll_enabled(dev_priv, pipe);
4678 }
4679
4680 /* Workaround : Do not read or write the pipe palette/gamma data while
4681 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4682 */
4683 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
4684 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4685 GAMMA_MODE_MODE_SPLIT)) {
4686 hsw_disable_ips(intel_crtc);
4687 reenable_ips = true;
4688 }
4689
4690 for (i = 0; i < 256; i++) {
4691 i915_reg_t palreg;
4692
4693 if (HAS_GMCH_DISPLAY(dev))
4694 palreg = PALETTE(pipe, i);
4695 else
4696 palreg = LGC_PALETTE(pipe, i);
4697
4698 I915_WRITE(palreg,
4699 (intel_crtc->lut_r[i] << 16) |
4700 (intel_crtc->lut_g[i] << 8) |
4701 intel_crtc->lut_b[i]);
4702 }
4703
4704 if (reenable_ips)
4705 hsw_enable_ips(intel_crtc);
4706 }
4707
4708 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
4709 {
4710 if (intel_crtc->overlay) {
4711 struct drm_device *dev = intel_crtc->base.dev;
4712 struct drm_i915_private *dev_priv = dev->dev_private;
4713
4714 mutex_lock(&dev->struct_mutex);
4715 dev_priv->mm.interruptible = false;
4716 (void) intel_overlay_switch_off(intel_crtc->overlay);
4717 dev_priv->mm.interruptible = true;
4718 mutex_unlock(&dev->struct_mutex);
4719 }
4720
4721 /* Let userspace switch the overlay on again. In most cases userspace
4722 * has to recompute where to put it anyway.
4723 */
4724 }
4725
4726 /**
4727 * intel_post_enable_primary - Perform operations after enabling primary plane
4728 * @crtc: the CRTC whose primary plane was just enabled
4729 *
4730 * Performs potentially sleeping operations that must be done after the primary
4731 * plane is enabled, such as updating FBC and IPS. Note that this may be
4732 * called due to an explicit primary plane update, or due to an implicit
4733 * re-enable that is caused when a sprite plane is updated to no longer
4734 * completely hide the primary plane.
4735 */
4736 static void
4737 intel_post_enable_primary(struct drm_crtc *crtc)
4738 {
4739 struct drm_device *dev = crtc->dev;
4740 struct drm_i915_private *dev_priv = dev->dev_private;
4741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4742 int pipe = intel_crtc->pipe;
4743
4744 /*
4745 * FIXME IPS should be fine as long as one plane is
4746 * enabled, but in practice it seems to have problems
4747 * when going from primary only to sprite only and vice
4748 * versa.
4749 */
4750 hsw_enable_ips(intel_crtc);
4751
4752 /*
4753 * Gen2 reports pipe underruns whenever all planes are disabled.
4754 * So don't enable underrun reporting before at least some planes
4755 * are enabled.
4756 * FIXME: Need to fix the logic to work when we turn off all planes
4757 * but leave the pipe running.
4758 */
4759 if (IS_GEN2(dev))
4760 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4761
4762 /* Underruns don't always raise interrupts, so check manually. */
4763 intel_check_cpu_fifo_underruns(dev_priv);
4764 intel_check_pch_fifo_underruns(dev_priv);
4765 }
4766
4767 /**
4768 * intel_pre_disable_primary - Perform operations before disabling primary plane
4769 * @crtc: the CRTC whose primary plane is to be disabled
4770 *
4771 * Performs potentially sleeping operations that must be done before the
4772 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4773 * be called due to an explicit primary plane update, or due to an implicit
4774 * disable that is caused when a sprite plane completely hides the primary
4775 * plane.
4776 */
4777 static void
4778 intel_pre_disable_primary(struct drm_crtc *crtc)
4779 {
4780 struct drm_device *dev = crtc->dev;
4781 struct drm_i915_private *dev_priv = dev->dev_private;
4782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4783 int pipe = intel_crtc->pipe;
4784
4785 /*
4786 * Gen2 reports pipe underruns whenever all planes are disabled.
4787 * So diasble underrun reporting before all the planes get disabled.
4788 * FIXME: Need to fix the logic to work when we turn off all planes
4789 * but leave the pipe running.
4790 */
4791 if (IS_GEN2(dev))
4792 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4793
4794 /*
4795 * Vblank time updates from the shadow to live plane control register
4796 * are blocked if the memory self-refresh mode is active at that
4797 * moment. So to make sure the plane gets truly disabled, disable
4798 * first the self-refresh mode. The self-refresh enable bit in turn
4799 * will be checked/applied by the HW only at the next frame start
4800 * event which is after the vblank start event, so we need to have a
4801 * wait-for-vblank between disabling the plane and the pipe.
4802 */
4803 if (HAS_GMCH_DISPLAY(dev)) {
4804 intel_set_memory_cxsr(dev_priv, false);
4805 dev_priv->wm.vlv.cxsr = false;
4806 intel_wait_for_vblank(dev, pipe);
4807 }
4808
4809 /*
4810 * FIXME IPS should be fine as long as one plane is
4811 * enabled, but in practice it seems to have problems
4812 * when going from primary only to sprite only and vice
4813 * versa.
4814 */
4815 hsw_disable_ips(intel_crtc);
4816 }
4817
4818 static void intel_post_plane_update(struct intel_crtc *crtc)
4819 {
4820 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4821 struct intel_crtc_state *pipe_config =
4822 to_intel_crtc_state(crtc->base.state);
4823 struct drm_device *dev = crtc->base.dev;
4824
4825 if (atomic->wait_vblank)
4826 intel_wait_for_vblank(dev, crtc->pipe);
4827
4828 intel_frontbuffer_flip(dev, atomic->fb_bits);
4829
4830 crtc->wm.cxsr_allowed = true;
4831
4832 if (pipe_config->wm_changed && pipe_config->base.active)
4833 intel_update_watermarks(&crtc->base);
4834
4835 if (atomic->update_fbc)
4836 intel_fbc_update(crtc);
4837
4838 if (atomic->post_enable_primary)
4839 intel_post_enable_primary(&crtc->base);
4840
4841 memset(atomic, 0, sizeof(*atomic));
4842 }
4843
4844 static void intel_pre_plane_update(struct intel_crtc *crtc)
4845 {
4846 struct drm_device *dev = crtc->base.dev;
4847 struct drm_i915_private *dev_priv = dev->dev_private;
4848 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4849 struct intel_crtc_state *pipe_config =
4850 to_intel_crtc_state(crtc->base.state);
4851
4852 if (atomic->disable_fbc)
4853 intel_fbc_deactivate(crtc);
4854
4855 if (crtc->atomic.disable_ips)
4856 hsw_disable_ips(crtc);
4857
4858 if (atomic->pre_disable_primary)
4859 intel_pre_disable_primary(&crtc->base);
4860
4861 if (pipe_config->disable_cxsr) {
4862 crtc->wm.cxsr_allowed = false;
4863 intel_set_memory_cxsr(dev_priv, false);
4864 }
4865
4866 /*
4867 * IVB workaround: must disable low power watermarks for at least
4868 * one frame before enabling scaling. LP watermarks can be re-enabled
4869 * when scaling is disabled.
4870 *
4871 * WaCxSRDisabledForSpriteScaling:ivb
4872 */
4873 if (pipe_config->disable_lp_wm) {
4874 ilk_disable_lp_wm(dev);
4875 intel_wait_for_vblank(dev, crtc->pipe);
4876 }
4877
4878 /*
4879 * If we're doing a modeset, we're done. No need to do any pre-vblank
4880 * watermark programming here.
4881 */
4882 if (needs_modeset(&pipe_config->base))
4883 return;
4884
4885 /*
4886 * For platforms that support atomic watermarks, program the
4887 * 'intermediate' watermarks immediately. On pre-gen9 platforms, these
4888 * will be the intermediate values that are safe for both pre- and
4889 * post- vblank; when vblank happens, the 'active' values will be set
4890 * to the final 'target' values and we'll do this again to get the
4891 * optimal watermarks. For gen9+ platforms, the values we program here
4892 * will be the final target values which will get automatically latched
4893 * at vblank time; no further programming will be necessary.
4894 *
4895 * If a platform hasn't been transitioned to atomic watermarks yet,
4896 * we'll continue to update watermarks the old way, if flags tell
4897 * us to.
4898 */
4899 if (dev_priv->display.initial_watermarks != NULL)
4900 dev_priv->display.initial_watermarks(pipe_config);
4901 else if (pipe_config->wm_changed)
4902 intel_update_watermarks(&crtc->base);
4903 }
4904
4905 static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
4906 {
4907 struct drm_device *dev = crtc->dev;
4908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4909 struct drm_plane *p;
4910 int pipe = intel_crtc->pipe;
4911
4912 intel_crtc_dpms_overlay_disable(intel_crtc);
4913
4914 drm_for_each_plane_mask(p, dev, plane_mask)
4915 to_intel_plane(p)->disable_plane(p, crtc);
4916
4917 /*
4918 * FIXME: Once we grow proper nuclear flip support out of this we need
4919 * to compute the mask of flip planes precisely. For the time being
4920 * consider this a flip to a NULL plane.
4921 */
4922 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
4923 }
4924
4925 static void ironlake_crtc_enable(struct drm_crtc *crtc)
4926 {
4927 struct drm_device *dev = crtc->dev;
4928 struct drm_i915_private *dev_priv = dev->dev_private;
4929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4930 struct intel_encoder *encoder;
4931 int pipe = intel_crtc->pipe;
4932
4933 if (WARN_ON(intel_crtc->active))
4934 return;
4935
4936 if (intel_crtc->config->has_pch_encoder)
4937 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
4938
4939 if (intel_crtc->config->has_pch_encoder)
4940 intel_prepare_shared_dpll(intel_crtc);
4941
4942 if (intel_crtc->config->has_dp_encoder)
4943 intel_dp_set_m_n(intel_crtc, M1_N1);
4944
4945 intel_set_pipe_timings(intel_crtc);
4946
4947 if (intel_crtc->config->has_pch_encoder) {
4948 intel_cpu_transcoder_set_m_n(intel_crtc,
4949 &intel_crtc->config->fdi_m_n, NULL);
4950 }
4951
4952 ironlake_set_pipeconf(crtc);
4953
4954 intel_crtc->active = true;
4955
4956 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4957
4958 for_each_encoder_on_crtc(dev, crtc, encoder)
4959 if (encoder->pre_enable)
4960 encoder->pre_enable(encoder);
4961
4962 if (intel_crtc->config->has_pch_encoder) {
4963 /* Note: FDI PLL enabling _must_ be done before we enable the
4964 * cpu pipes, hence this is separate from all the other fdi/pch
4965 * enabling. */
4966 ironlake_fdi_pll_enable(intel_crtc);
4967 } else {
4968 assert_fdi_tx_disabled(dev_priv, pipe);
4969 assert_fdi_rx_disabled(dev_priv, pipe);
4970 }
4971
4972 ironlake_pfit_enable(intel_crtc);
4973
4974 /*
4975 * On ILK+ LUT must be loaded before the pipe is running but with
4976 * clocks enabled
4977 */
4978 intel_crtc_load_lut(crtc);
4979
4980 intel_update_watermarks(crtc);
4981 intel_enable_pipe(intel_crtc);
4982
4983 if (intel_crtc->config->has_pch_encoder)
4984 ironlake_pch_enable(crtc);
4985
4986 assert_vblank_disabled(crtc);
4987 drm_crtc_vblank_on(crtc);
4988
4989 for_each_encoder_on_crtc(dev, crtc, encoder)
4990 encoder->enable(encoder);
4991
4992 if (HAS_PCH_CPT(dev))
4993 cpt_verify_modeset(dev, intel_crtc->pipe);
4994
4995 /* Must wait for vblank to avoid spurious PCH FIFO underruns */
4996 if (intel_crtc->config->has_pch_encoder)
4997 intel_wait_for_vblank(dev, pipe);
4998 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
4999
5000 intel_fbc_enable(intel_crtc);
5001 }
5002
5003 /* IPS only exists on ULT machines and is tied to pipe A. */
5004 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
5005 {
5006 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
5007 }
5008
5009 static void haswell_crtc_enable(struct drm_crtc *crtc)
5010 {
5011 struct drm_device *dev = crtc->dev;
5012 struct drm_i915_private *dev_priv = dev->dev_private;
5013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5014 struct intel_encoder *encoder;
5015 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
5016 struct intel_crtc_state *pipe_config =
5017 to_intel_crtc_state(crtc->state);
5018
5019 if (WARN_ON(intel_crtc->active))
5020 return;
5021
5022 if (intel_crtc->config->has_pch_encoder)
5023 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5024 false);
5025
5026 if (intel_crtc_to_shared_dpll(intel_crtc))
5027 intel_enable_shared_dpll(intel_crtc);
5028
5029 if (intel_crtc->config->has_dp_encoder)
5030 intel_dp_set_m_n(intel_crtc, M1_N1);
5031
5032 intel_set_pipe_timings(intel_crtc);
5033
5034 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5035 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5036 intel_crtc->config->pixel_multiplier - 1);
5037 }
5038
5039 if (intel_crtc->config->has_pch_encoder) {
5040 intel_cpu_transcoder_set_m_n(intel_crtc,
5041 &intel_crtc->config->fdi_m_n, NULL);
5042 }
5043
5044 haswell_set_pipeconf(crtc);
5045
5046 intel_set_pipe_csc(crtc);
5047
5048 intel_crtc->active = true;
5049
5050 if (intel_crtc->config->has_pch_encoder)
5051 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5052 else
5053 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5054
5055 for_each_encoder_on_crtc(dev, crtc, encoder) {
5056 if (encoder->pre_enable)
5057 encoder->pre_enable(encoder);
5058 }
5059
5060 if (intel_crtc->config->has_pch_encoder)
5061 dev_priv->display.fdi_link_train(crtc);
5062
5063 if (!intel_crtc->config->has_dsi_encoder)
5064 intel_ddi_enable_pipe_clock(intel_crtc);
5065
5066 if (INTEL_INFO(dev)->gen >= 9)
5067 skylake_pfit_enable(intel_crtc);
5068 else
5069 ironlake_pfit_enable(intel_crtc);
5070
5071 /*
5072 * On ILK+ LUT must be loaded before the pipe is running but with
5073 * clocks enabled
5074 */
5075 intel_crtc_load_lut(crtc);
5076
5077 intel_ddi_set_pipe_settings(crtc);
5078 if (!intel_crtc->config->has_dsi_encoder)
5079 intel_ddi_enable_transcoder_func(crtc);
5080
5081 intel_update_watermarks(crtc);
5082 intel_enable_pipe(intel_crtc);
5083
5084 if (intel_crtc->config->has_pch_encoder)
5085 lpt_pch_enable(crtc);
5086
5087 if (intel_crtc->config->dp_encoder_is_mst)
5088 intel_ddi_set_vc_payload_alloc(crtc, true);
5089
5090 assert_vblank_disabled(crtc);
5091 drm_crtc_vblank_on(crtc);
5092
5093 for_each_encoder_on_crtc(dev, crtc, encoder) {
5094 encoder->enable(encoder);
5095 intel_opregion_notify_encoder(encoder, true);
5096 }
5097
5098 if (intel_crtc->config->has_pch_encoder) {
5099 intel_wait_for_vblank(dev, pipe);
5100 intel_wait_for_vblank(dev, pipe);
5101 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5102 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5103 true);
5104 }
5105
5106 /* If we change the relative order between pipe/planes enabling, we need
5107 * to change the workaround. */
5108 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
5109 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
5110 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5111 intel_wait_for_vblank(dev, hsw_workaround_pipe);
5112 }
5113
5114 intel_fbc_enable(intel_crtc);
5115 }
5116
5117 static void ironlake_pfit_disable(struct intel_crtc *crtc, bool force)
5118 {
5119 struct drm_device *dev = crtc->base.dev;
5120 struct drm_i915_private *dev_priv = dev->dev_private;
5121 int pipe = crtc->pipe;
5122
5123 /* To avoid upsetting the power well on haswell only disable the pfit if
5124 * it's in use. The hw state code will make sure we get this right. */
5125 if (force || crtc->config->pch_pfit.enabled) {
5126 I915_WRITE(PF_CTL(pipe), 0);
5127 I915_WRITE(PF_WIN_POS(pipe), 0);
5128 I915_WRITE(PF_WIN_SZ(pipe), 0);
5129 }
5130 }
5131
5132 static void ironlake_crtc_disable(struct drm_crtc *crtc)
5133 {
5134 struct drm_device *dev = crtc->dev;
5135 struct drm_i915_private *dev_priv = dev->dev_private;
5136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5137 struct intel_encoder *encoder;
5138 int pipe = intel_crtc->pipe;
5139
5140 if (intel_crtc->config->has_pch_encoder)
5141 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
5142
5143 for_each_encoder_on_crtc(dev, crtc, encoder)
5144 encoder->disable(encoder);
5145
5146 drm_crtc_vblank_off(crtc);
5147 assert_vblank_disabled(crtc);
5148
5149 /*
5150 * Sometimes spurious CPU pipe underruns happen when the
5151 * pipe is already disabled, but FDI RX/TX is still enabled.
5152 * Happens at least with VGA+HDMI cloning. Suppress them.
5153 */
5154 if (intel_crtc->config->has_pch_encoder)
5155 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
5156
5157 intel_disable_pipe(intel_crtc);
5158
5159 ironlake_pfit_disable(intel_crtc, false);
5160
5161 if (intel_crtc->config->has_pch_encoder) {
5162 ironlake_fdi_disable(crtc);
5163 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
5164 }
5165
5166 for_each_encoder_on_crtc(dev, crtc, encoder)
5167 if (encoder->post_disable)
5168 encoder->post_disable(encoder);
5169
5170 if (intel_crtc->config->has_pch_encoder) {
5171 ironlake_disable_pch_transcoder(dev_priv, pipe);
5172
5173 if (HAS_PCH_CPT(dev)) {
5174 i915_reg_t reg;
5175 u32 temp;
5176
5177 /* disable TRANS_DP_CTL */
5178 reg = TRANS_DP_CTL(pipe);
5179 temp = I915_READ(reg);
5180 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5181 TRANS_DP_PORT_SEL_MASK);
5182 temp |= TRANS_DP_PORT_SEL_NONE;
5183 I915_WRITE(reg, temp);
5184
5185 /* disable DPLL_SEL */
5186 temp = I915_READ(PCH_DPLL_SEL);
5187 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
5188 I915_WRITE(PCH_DPLL_SEL, temp);
5189 }
5190
5191 ironlake_fdi_pll_disable(intel_crtc);
5192 }
5193
5194 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
5195
5196 intel_fbc_disable_crtc(intel_crtc);
5197 }
5198
5199 static void haswell_crtc_disable(struct drm_crtc *crtc)
5200 {
5201 struct drm_device *dev = crtc->dev;
5202 struct drm_i915_private *dev_priv = dev->dev_private;
5203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5204 struct intel_encoder *encoder;
5205 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
5206
5207 if (intel_crtc->config->has_pch_encoder)
5208 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5209 false);
5210
5211 for_each_encoder_on_crtc(dev, crtc, encoder) {
5212 intel_opregion_notify_encoder(encoder, false);
5213 encoder->disable(encoder);
5214 }
5215
5216 drm_crtc_vblank_off(crtc);
5217 assert_vblank_disabled(crtc);
5218
5219 intel_disable_pipe(intel_crtc);
5220
5221 if (intel_crtc->config->dp_encoder_is_mst)
5222 intel_ddi_set_vc_payload_alloc(crtc, false);
5223
5224 if (!intel_crtc->config->has_dsi_encoder)
5225 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
5226
5227 if (INTEL_INFO(dev)->gen >= 9)
5228 skylake_scaler_disable(intel_crtc);
5229 else
5230 ironlake_pfit_disable(intel_crtc, false);
5231
5232 if (!intel_crtc->config->has_dsi_encoder)
5233 intel_ddi_disable_pipe_clock(intel_crtc);
5234
5235 for_each_encoder_on_crtc(dev, crtc, encoder)
5236 if (encoder->post_disable)
5237 encoder->post_disable(encoder);
5238
5239 if (intel_crtc->config->has_pch_encoder) {
5240 lpt_disable_pch_transcoder(dev_priv);
5241 lpt_disable_iclkip(dev_priv);
5242 intel_ddi_fdi_disable(crtc);
5243
5244 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5245 true);
5246 }
5247
5248 intel_fbc_disable_crtc(intel_crtc);
5249 }
5250
5251 static void i9xx_pfit_enable(struct intel_crtc *crtc)
5252 {
5253 struct drm_device *dev = crtc->base.dev;
5254 struct drm_i915_private *dev_priv = dev->dev_private;
5255 struct intel_crtc_state *pipe_config = crtc->config;
5256
5257 if (!pipe_config->gmch_pfit.control)
5258 return;
5259
5260 /*
5261 * The panel fitter should only be adjusted whilst the pipe is disabled,
5262 * according to register description and PRM.
5263 */
5264 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5265 assert_pipe_disabled(dev_priv, crtc->pipe);
5266
5267 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5268 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5269
5270 /* Border color in case we don't scale up to the full screen. Black by
5271 * default, change to something else for debugging. */
5272 I915_WRITE(BCLRPAT(crtc->pipe), 0);
5273 }
5274
5275 static enum intel_display_power_domain port_to_power_domain(enum port port)
5276 {
5277 switch (port) {
5278 case PORT_A:
5279 return POWER_DOMAIN_PORT_DDI_A_LANES;
5280 case PORT_B:
5281 return POWER_DOMAIN_PORT_DDI_B_LANES;
5282 case PORT_C:
5283 return POWER_DOMAIN_PORT_DDI_C_LANES;
5284 case PORT_D:
5285 return POWER_DOMAIN_PORT_DDI_D_LANES;
5286 case PORT_E:
5287 return POWER_DOMAIN_PORT_DDI_E_LANES;
5288 default:
5289 MISSING_CASE(port);
5290 return POWER_DOMAIN_PORT_OTHER;
5291 }
5292 }
5293
5294 static enum intel_display_power_domain port_to_aux_power_domain(enum port port)
5295 {
5296 switch (port) {
5297 case PORT_A:
5298 return POWER_DOMAIN_AUX_A;
5299 case PORT_B:
5300 return POWER_DOMAIN_AUX_B;
5301 case PORT_C:
5302 return POWER_DOMAIN_AUX_C;
5303 case PORT_D:
5304 return POWER_DOMAIN_AUX_D;
5305 case PORT_E:
5306 /* FIXME: Check VBT for actual wiring of PORT E */
5307 return POWER_DOMAIN_AUX_D;
5308 default:
5309 MISSING_CASE(port);
5310 return POWER_DOMAIN_AUX_A;
5311 }
5312 }
5313
5314 enum intel_display_power_domain
5315 intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5316 {
5317 struct drm_device *dev = intel_encoder->base.dev;
5318 struct intel_digital_port *intel_dig_port;
5319
5320 switch (intel_encoder->type) {
5321 case INTEL_OUTPUT_UNKNOWN:
5322 /* Only DDI platforms should ever use this output type */
5323 WARN_ON_ONCE(!HAS_DDI(dev));
5324 case INTEL_OUTPUT_DISPLAYPORT:
5325 case INTEL_OUTPUT_HDMI:
5326 case INTEL_OUTPUT_EDP:
5327 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5328 return port_to_power_domain(intel_dig_port->port);
5329 case INTEL_OUTPUT_DP_MST:
5330 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5331 return port_to_power_domain(intel_dig_port->port);
5332 case INTEL_OUTPUT_ANALOG:
5333 return POWER_DOMAIN_PORT_CRT;
5334 case INTEL_OUTPUT_DSI:
5335 return POWER_DOMAIN_PORT_DSI;
5336 default:
5337 return POWER_DOMAIN_PORT_OTHER;
5338 }
5339 }
5340
5341 enum intel_display_power_domain
5342 intel_display_port_aux_power_domain(struct intel_encoder *intel_encoder)
5343 {
5344 struct drm_device *dev = intel_encoder->base.dev;
5345 struct intel_digital_port *intel_dig_port;
5346
5347 switch (intel_encoder->type) {
5348 case INTEL_OUTPUT_UNKNOWN:
5349 case INTEL_OUTPUT_HDMI:
5350 /*
5351 * Only DDI platforms should ever use these output types.
5352 * We can get here after the HDMI detect code has already set
5353 * the type of the shared encoder. Since we can't be sure
5354 * what's the status of the given connectors, play safe and
5355 * run the DP detection too.
5356 */
5357 WARN_ON_ONCE(!HAS_DDI(dev));
5358 case INTEL_OUTPUT_DISPLAYPORT:
5359 case INTEL_OUTPUT_EDP:
5360 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
5361 return port_to_aux_power_domain(intel_dig_port->port);
5362 case INTEL_OUTPUT_DP_MST:
5363 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5364 return port_to_aux_power_domain(intel_dig_port->port);
5365 default:
5366 MISSING_CASE(intel_encoder->type);
5367 return POWER_DOMAIN_AUX_A;
5368 }
5369 }
5370
5371 static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
5372 {
5373 struct drm_device *dev = crtc->dev;
5374 struct intel_encoder *intel_encoder;
5375 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5376 enum pipe pipe = intel_crtc->pipe;
5377 unsigned long mask;
5378 enum transcoder transcoder = intel_crtc->config->cpu_transcoder;
5379
5380 if (!crtc->state->active)
5381 return 0;
5382
5383 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5384 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
5385 if (intel_crtc->config->pch_pfit.enabled ||
5386 intel_crtc->config->pch_pfit.force_thru)
5387 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5388
5389 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5390 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5391
5392 return mask;
5393 }
5394
5395 static unsigned long modeset_get_crtc_power_domains(struct drm_crtc *crtc)
5396 {
5397 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5399 enum intel_display_power_domain domain;
5400 unsigned long domains, new_domains, old_domains;
5401
5402 old_domains = intel_crtc->enabled_power_domains;
5403 intel_crtc->enabled_power_domains = new_domains = get_crtc_power_domains(crtc);
5404
5405 domains = new_domains & ~old_domains;
5406
5407 for_each_power_domain(domain, domains)
5408 intel_display_power_get(dev_priv, domain);
5409
5410 return old_domains & ~new_domains;
5411 }
5412
5413 static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
5414 unsigned long domains)
5415 {
5416 enum intel_display_power_domain domain;
5417
5418 for_each_power_domain(domain, domains)
5419 intel_display_power_put(dev_priv, domain);
5420 }
5421
5422 static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
5423 {
5424 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
5425 struct drm_device *dev = state->dev;
5426 struct drm_i915_private *dev_priv = dev->dev_private;
5427 unsigned long put_domains[I915_MAX_PIPES] = {};
5428 struct drm_crtc_state *crtc_state;
5429 struct drm_crtc *crtc;
5430 int i;
5431
5432 for_each_crtc_in_state(state, crtc, crtc_state, i) {
5433 if (needs_modeset(crtc->state))
5434 put_domains[to_intel_crtc(crtc)->pipe] =
5435 modeset_get_crtc_power_domains(crtc);
5436 }
5437
5438 if (dev_priv->display.modeset_commit_cdclk &&
5439 intel_state->dev_cdclk != dev_priv->cdclk_freq)
5440 dev_priv->display.modeset_commit_cdclk(state);
5441
5442 for (i = 0; i < I915_MAX_PIPES; i++)
5443 if (put_domains[i])
5444 modeset_put_power_domains(dev_priv, put_domains[i]);
5445 }
5446
5447 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
5448 {
5449 int max_cdclk_freq = dev_priv->max_cdclk_freq;
5450
5451 if (INTEL_INFO(dev_priv)->gen >= 9 ||
5452 IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
5453 return max_cdclk_freq;
5454 else if (IS_CHERRYVIEW(dev_priv))
5455 return max_cdclk_freq*95/100;
5456 else if (INTEL_INFO(dev_priv)->gen < 4)
5457 return 2*max_cdclk_freq*90/100;
5458 else
5459 return max_cdclk_freq*90/100;
5460 }
5461
5462 static void intel_update_max_cdclk(struct drm_device *dev)
5463 {
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465
5466 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
5467 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5468
5469 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5470 dev_priv->max_cdclk_freq = 675000;
5471 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5472 dev_priv->max_cdclk_freq = 540000;
5473 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5474 dev_priv->max_cdclk_freq = 450000;
5475 else
5476 dev_priv->max_cdclk_freq = 337500;
5477 } else if (IS_BROADWELL(dev)) {
5478 /*
5479 * FIXME with extra cooling we can allow
5480 * 540 MHz for ULX and 675 Mhz for ULT.
5481 * How can we know if extra cooling is
5482 * available? PCI ID, VTB, something else?
5483 */
5484 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5485 dev_priv->max_cdclk_freq = 450000;
5486 else if (IS_BDW_ULX(dev))
5487 dev_priv->max_cdclk_freq = 450000;
5488 else if (IS_BDW_ULT(dev))
5489 dev_priv->max_cdclk_freq = 540000;
5490 else
5491 dev_priv->max_cdclk_freq = 675000;
5492 } else if (IS_CHERRYVIEW(dev)) {
5493 dev_priv->max_cdclk_freq = 320000;
5494 } else if (IS_VALLEYVIEW(dev)) {
5495 dev_priv->max_cdclk_freq = 400000;
5496 } else {
5497 /* otherwise assume cdclk is fixed */
5498 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5499 }
5500
5501 dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
5502
5503 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5504 dev_priv->max_cdclk_freq);
5505
5506 DRM_DEBUG_DRIVER("Max dotclock rate: %d kHz\n",
5507 dev_priv->max_dotclk_freq);
5508 }
5509
5510 static void intel_update_cdclk(struct drm_device *dev)
5511 {
5512 struct drm_i915_private *dev_priv = dev->dev_private;
5513
5514 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5515 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5516 dev_priv->cdclk_freq);
5517
5518 /*
5519 * Program the gmbus_freq based on the cdclk frequency.
5520 * BSpec erroneously claims we should aim for 4MHz, but
5521 * in fact 1MHz is the correct frequency.
5522 */
5523 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5524 /*
5525 * Program the gmbus_freq based on the cdclk frequency.
5526 * BSpec erroneously claims we should aim for 4MHz, but
5527 * in fact 1MHz is the correct frequency.
5528 */
5529 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5530 }
5531
5532 if (dev_priv->max_cdclk_freq == 0)
5533 intel_update_max_cdclk(dev);
5534 }
5535
5536 static void broxton_set_cdclk(struct drm_device *dev, int frequency)
5537 {
5538 struct drm_i915_private *dev_priv = dev->dev_private;
5539 uint32_t divider;
5540 uint32_t ratio;
5541 uint32_t current_freq;
5542 int ret;
5543
5544 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5545 switch (frequency) {
5546 case 144000:
5547 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5548 ratio = BXT_DE_PLL_RATIO(60);
5549 break;
5550 case 288000:
5551 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5552 ratio = BXT_DE_PLL_RATIO(60);
5553 break;
5554 case 384000:
5555 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5556 ratio = BXT_DE_PLL_RATIO(60);
5557 break;
5558 case 576000:
5559 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5560 ratio = BXT_DE_PLL_RATIO(60);
5561 break;
5562 case 624000:
5563 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5564 ratio = BXT_DE_PLL_RATIO(65);
5565 break;
5566 case 19200:
5567 /*
5568 * Bypass frequency with DE PLL disabled. Init ratio, divider
5569 * to suppress GCC warning.
5570 */
5571 ratio = 0;
5572 divider = 0;
5573 break;
5574 default:
5575 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5576
5577 return;
5578 }
5579
5580 mutex_lock(&dev_priv->rps.hw_lock);
5581 /* Inform power controller of upcoming frequency change */
5582 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5583 0x80000000);
5584 mutex_unlock(&dev_priv->rps.hw_lock);
5585
5586 if (ret) {
5587 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5588 ret, frequency);
5589 return;
5590 }
5591
5592 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5593 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5594 current_freq = current_freq * 500 + 1000;
5595
5596 /*
5597 * DE PLL has to be disabled when
5598 * - setting to 19.2MHz (bypass, PLL isn't used)
5599 * - before setting to 624MHz (PLL needs toggling)
5600 * - before setting to any frequency from 624MHz (PLL needs toggling)
5601 */
5602 if (frequency == 19200 || frequency == 624000 ||
5603 current_freq == 624000) {
5604 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5605 /* Timeout 200us */
5606 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5607 1))
5608 DRM_ERROR("timout waiting for DE PLL unlock\n");
5609 }
5610
5611 if (frequency != 19200) {
5612 uint32_t val;
5613
5614 val = I915_READ(BXT_DE_PLL_CTL);
5615 val &= ~BXT_DE_PLL_RATIO_MASK;
5616 val |= ratio;
5617 I915_WRITE(BXT_DE_PLL_CTL, val);
5618
5619 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5620 /* Timeout 200us */
5621 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5622 DRM_ERROR("timeout waiting for DE PLL lock\n");
5623
5624 val = I915_READ(CDCLK_CTL);
5625 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5626 val |= divider;
5627 /*
5628 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5629 * enable otherwise.
5630 */
5631 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5632 if (frequency >= 500000)
5633 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5634
5635 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5636 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5637 val |= (frequency - 1000) / 500;
5638 I915_WRITE(CDCLK_CTL, val);
5639 }
5640
5641 mutex_lock(&dev_priv->rps.hw_lock);
5642 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5643 DIV_ROUND_UP(frequency, 25000));
5644 mutex_unlock(&dev_priv->rps.hw_lock);
5645
5646 if (ret) {
5647 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5648 ret, frequency);
5649 return;
5650 }
5651
5652 intel_update_cdclk(dev);
5653 }
5654
5655 void broxton_init_cdclk(struct drm_device *dev)
5656 {
5657 struct drm_i915_private *dev_priv = dev->dev_private;
5658 uint32_t val;
5659
5660 /*
5661 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5662 * or else the reset will hang because there is no PCH to respond.
5663 * Move the handshake programming to initialization sequence.
5664 * Previously was left up to BIOS.
5665 */
5666 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5667 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5668 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5669
5670 /* Enable PG1 for cdclk */
5671 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5672
5673 /* check if cd clock is enabled */
5674 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5675 DRM_DEBUG_KMS("Display already initialized\n");
5676 return;
5677 }
5678
5679 /*
5680 * FIXME:
5681 * - The initial CDCLK needs to be read from VBT.
5682 * Need to make this change after VBT has changes for BXT.
5683 * - check if setting the max (or any) cdclk freq is really necessary
5684 * here, it belongs to modeset time
5685 */
5686 broxton_set_cdclk(dev, 624000);
5687
5688 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5689 POSTING_READ(DBUF_CTL);
5690
5691 udelay(10);
5692
5693 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5694 DRM_ERROR("DBuf power enable timeout!\n");
5695 }
5696
5697 void broxton_uninit_cdclk(struct drm_device *dev)
5698 {
5699 struct drm_i915_private *dev_priv = dev->dev_private;
5700
5701 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5702 POSTING_READ(DBUF_CTL);
5703
5704 udelay(10);
5705
5706 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5707 DRM_ERROR("DBuf power disable timeout!\n");
5708
5709 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5710 broxton_set_cdclk(dev, 19200);
5711
5712 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5713 }
5714
5715 static const struct skl_cdclk_entry {
5716 unsigned int freq;
5717 unsigned int vco;
5718 } skl_cdclk_frequencies[] = {
5719 { .freq = 308570, .vco = 8640 },
5720 { .freq = 337500, .vco = 8100 },
5721 { .freq = 432000, .vco = 8640 },
5722 { .freq = 450000, .vco = 8100 },
5723 { .freq = 540000, .vco = 8100 },
5724 { .freq = 617140, .vco = 8640 },
5725 { .freq = 675000, .vco = 8100 },
5726 };
5727
5728 static unsigned int skl_cdclk_decimal(unsigned int freq)
5729 {
5730 return (freq - 1000) / 500;
5731 }
5732
5733 static unsigned int skl_cdclk_get_vco(unsigned int freq)
5734 {
5735 unsigned int i;
5736
5737 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5738 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5739
5740 if (e->freq == freq)
5741 return e->vco;
5742 }
5743
5744 return 8100;
5745 }
5746
5747 static void
5748 skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5749 {
5750 unsigned int min_freq;
5751 u32 val;
5752
5753 /* select the minimum CDCLK before enabling DPLL 0 */
5754 val = I915_READ(CDCLK_CTL);
5755 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5756 val |= CDCLK_FREQ_337_308;
5757
5758 if (required_vco == 8640)
5759 min_freq = 308570;
5760 else
5761 min_freq = 337500;
5762
5763 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5764
5765 I915_WRITE(CDCLK_CTL, val);
5766 POSTING_READ(CDCLK_CTL);
5767
5768 /*
5769 * We always enable DPLL0 with the lowest link rate possible, but still
5770 * taking into account the VCO required to operate the eDP panel at the
5771 * desired frequency. The usual DP link rates operate with a VCO of
5772 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5773 * The modeset code is responsible for the selection of the exact link
5774 * rate later on, with the constraint of choosing a frequency that
5775 * works with required_vco.
5776 */
5777 val = I915_READ(DPLL_CTRL1);
5778
5779 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5780 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5781 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5782 if (required_vco == 8640)
5783 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5784 SKL_DPLL0);
5785 else
5786 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5787 SKL_DPLL0);
5788
5789 I915_WRITE(DPLL_CTRL1, val);
5790 POSTING_READ(DPLL_CTRL1);
5791
5792 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5793
5794 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5795 DRM_ERROR("DPLL0 not locked\n");
5796 }
5797
5798 static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5799 {
5800 int ret;
5801 u32 val;
5802
5803 /* inform PCU we want to change CDCLK */
5804 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5805 mutex_lock(&dev_priv->rps.hw_lock);
5806 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5807 mutex_unlock(&dev_priv->rps.hw_lock);
5808
5809 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5810 }
5811
5812 static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5813 {
5814 unsigned int i;
5815
5816 for (i = 0; i < 15; i++) {
5817 if (skl_cdclk_pcu_ready(dev_priv))
5818 return true;
5819 udelay(10);
5820 }
5821
5822 return false;
5823 }
5824
5825 static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5826 {
5827 struct drm_device *dev = dev_priv->dev;
5828 u32 freq_select, pcu_ack;
5829
5830 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5831
5832 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5833 DRM_ERROR("failed to inform PCU about cdclk change\n");
5834 return;
5835 }
5836
5837 /* set CDCLK_CTL */
5838 switch(freq) {
5839 case 450000:
5840 case 432000:
5841 freq_select = CDCLK_FREQ_450_432;
5842 pcu_ack = 1;
5843 break;
5844 case 540000:
5845 freq_select = CDCLK_FREQ_540;
5846 pcu_ack = 2;
5847 break;
5848 case 308570:
5849 case 337500:
5850 default:
5851 freq_select = CDCLK_FREQ_337_308;
5852 pcu_ack = 0;
5853 break;
5854 case 617140:
5855 case 675000:
5856 freq_select = CDCLK_FREQ_675_617;
5857 pcu_ack = 3;
5858 break;
5859 }
5860
5861 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5862 POSTING_READ(CDCLK_CTL);
5863
5864 /* inform PCU of the change */
5865 mutex_lock(&dev_priv->rps.hw_lock);
5866 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5867 mutex_unlock(&dev_priv->rps.hw_lock);
5868
5869 intel_update_cdclk(dev);
5870 }
5871
5872 void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5873 {
5874 /* disable DBUF power */
5875 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5876 POSTING_READ(DBUF_CTL);
5877
5878 udelay(10);
5879
5880 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5881 DRM_ERROR("DBuf power disable timeout\n");
5882
5883 /* disable DPLL0 */
5884 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5885 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5886 DRM_ERROR("Couldn't disable DPLL0\n");
5887 }
5888
5889 void skl_init_cdclk(struct drm_i915_private *dev_priv)
5890 {
5891 unsigned int required_vco;
5892
5893 /* DPLL0 not enabled (happens on early BIOS versions) */
5894 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) {
5895 /* enable DPLL0 */
5896 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5897 skl_dpll0_enable(dev_priv, required_vco);
5898 }
5899
5900 /* set CDCLK to the frequency the BIOS chose */
5901 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5902
5903 /* enable DBUF power */
5904 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5905 POSTING_READ(DBUF_CTL);
5906
5907 udelay(10);
5908
5909 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5910 DRM_ERROR("DBuf power enable timeout\n");
5911 }
5912
5913 int skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
5914 {
5915 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
5916 uint32_t cdctl = I915_READ(CDCLK_CTL);
5917 int freq = dev_priv->skl_boot_cdclk;
5918
5919 /*
5920 * check if the pre-os intialized the display
5921 * There is SWF18 scratchpad register defined which is set by the
5922 * pre-os which can be used by the OS drivers to check the status
5923 */
5924 if ((I915_READ(SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
5925 goto sanitize;
5926
5927 /* Is PLL enabled and locked ? */
5928 if (!((lcpll1 & LCPLL_PLL_ENABLE) && (lcpll1 & LCPLL_PLL_LOCK)))
5929 goto sanitize;
5930
5931 /* DPLL okay; verify the cdclock
5932 *
5933 * Noticed in some instances that the freq selection is correct but
5934 * decimal part is programmed wrong from BIOS where pre-os does not
5935 * enable display. Verify the same as well.
5936 */
5937 if (cdctl == ((cdctl & CDCLK_FREQ_SEL_MASK) | skl_cdclk_decimal(freq)))
5938 /* All well; nothing to sanitize */
5939 return false;
5940 sanitize:
5941 /*
5942 * As of now initialize with max cdclk till
5943 * we get dynamic cdclk support
5944 * */
5945 dev_priv->skl_boot_cdclk = dev_priv->max_cdclk_freq;
5946 skl_init_cdclk(dev_priv);
5947
5948 /* we did have to sanitize */
5949 return true;
5950 }
5951
5952 /* Adjust CDclk dividers to allow high res or save power if possible */
5953 static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5954 {
5955 struct drm_i915_private *dev_priv = dev->dev_private;
5956 u32 val, cmd;
5957
5958 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5959 != dev_priv->cdclk_freq);
5960
5961 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
5962 cmd = 2;
5963 else if (cdclk == 266667)
5964 cmd = 1;
5965 else
5966 cmd = 0;
5967
5968 mutex_lock(&dev_priv->rps.hw_lock);
5969 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5970 val &= ~DSPFREQGUAR_MASK;
5971 val |= (cmd << DSPFREQGUAR_SHIFT);
5972 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5973 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5974 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5975 50)) {
5976 DRM_ERROR("timed out waiting for CDclk change\n");
5977 }
5978 mutex_unlock(&dev_priv->rps.hw_lock);
5979
5980 mutex_lock(&dev_priv->sb_lock);
5981
5982 if (cdclk == 400000) {
5983 u32 divider;
5984
5985 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5986
5987 /* adjust cdclk divider */
5988 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5989 val &= ~CCK_FREQUENCY_VALUES;
5990 val |= divider;
5991 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
5992
5993 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5994 CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
5995 50))
5996 DRM_ERROR("timed out waiting for CDclk change\n");
5997 }
5998
5999 /* adjust self-refresh exit latency value */
6000 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
6001 val &= ~0x7f;
6002
6003 /*
6004 * For high bandwidth configs, we set a higher latency in the bunit
6005 * so that the core display fetch happens in time to avoid underruns.
6006 */
6007 if (cdclk == 400000)
6008 val |= 4500 / 250; /* 4.5 usec */
6009 else
6010 val |= 3000 / 250; /* 3.0 usec */
6011 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
6012
6013 mutex_unlock(&dev_priv->sb_lock);
6014
6015 intel_update_cdclk(dev);
6016 }
6017
6018 static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
6019 {
6020 struct drm_i915_private *dev_priv = dev->dev_private;
6021 u32 val, cmd;
6022
6023 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
6024 != dev_priv->cdclk_freq);
6025
6026 switch (cdclk) {
6027 case 333333:
6028 case 320000:
6029 case 266667:
6030 case 200000:
6031 break;
6032 default:
6033 MISSING_CASE(cdclk);
6034 return;
6035 }
6036
6037 /*
6038 * Specs are full of misinformation, but testing on actual
6039 * hardware has shown that we just need to write the desired
6040 * CCK divider into the Punit register.
6041 */
6042 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
6043
6044 mutex_lock(&dev_priv->rps.hw_lock);
6045 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
6046 val &= ~DSPFREQGUAR_MASK_CHV;
6047 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
6048 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
6049 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
6050 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
6051 50)) {
6052 DRM_ERROR("timed out waiting for CDclk change\n");
6053 }
6054 mutex_unlock(&dev_priv->rps.hw_lock);
6055
6056 intel_update_cdclk(dev);
6057 }
6058
6059 static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
6060 int max_pixclk)
6061 {
6062 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6063 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
6064
6065 /*
6066 * Really only a few cases to deal with, as only 4 CDclks are supported:
6067 * 200MHz
6068 * 267MHz
6069 * 320/333MHz (depends on HPLL freq)
6070 * 400MHz (VLV only)
6071 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
6072 * of the lower bin and adjust if needed.
6073 *
6074 * We seem to get an unstable or solid color picture at 200MHz.
6075 * Not sure what's wrong. For now use 200MHz only when all pipes
6076 * are off.
6077 */
6078 if (!IS_CHERRYVIEW(dev_priv) &&
6079 max_pixclk > freq_320*limit/100)
6080 return 400000;
6081 else if (max_pixclk > 266667*limit/100)
6082 return freq_320;
6083 else if (max_pixclk > 0)
6084 return 266667;
6085 else
6086 return 200000;
6087 }
6088
6089 static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
6090 int max_pixclk)
6091 {
6092 /*
6093 * FIXME:
6094 * - remove the guardband, it's not needed on BXT
6095 * - set 19.2MHz bypass frequency if there are no active pipes
6096 */
6097 if (max_pixclk > 576000*9/10)
6098 return 624000;
6099 else if (max_pixclk > 384000*9/10)
6100 return 576000;
6101 else if (max_pixclk > 288000*9/10)
6102 return 384000;
6103 else if (max_pixclk > 144000*9/10)
6104 return 288000;
6105 else
6106 return 144000;
6107 }
6108
6109 /* Compute the max pixel clock for new configuration. Uses atomic state if
6110 * that's non-NULL, look at current state otherwise. */
6111 static int intel_mode_max_pixclk(struct drm_device *dev,
6112 struct drm_atomic_state *state)
6113 {
6114 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
6115 struct drm_i915_private *dev_priv = dev->dev_private;
6116 struct drm_crtc *crtc;
6117 struct drm_crtc_state *crtc_state;
6118 unsigned max_pixclk = 0, i;
6119 enum pipe pipe;
6120
6121 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
6122 sizeof(intel_state->min_pixclk));
6123
6124 for_each_crtc_in_state(state, crtc, crtc_state, i) {
6125 int pixclk = 0;
6126
6127 if (crtc_state->enable)
6128 pixclk = crtc_state->adjusted_mode.crtc_clock;
6129
6130 intel_state->min_pixclk[i] = pixclk;
6131 }
6132
6133 if (!intel_state->active_crtcs)
6134 return 0;
6135
6136 for_each_pipe(dev_priv, pipe)
6137 max_pixclk = max(intel_state->min_pixclk[pipe], max_pixclk);
6138
6139 return max_pixclk;
6140 }
6141
6142 static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
6143 {
6144 struct drm_device *dev = state->dev;
6145 struct drm_i915_private *dev_priv = dev->dev_private;
6146 int max_pixclk = intel_mode_max_pixclk(dev, state);
6147 struct intel_atomic_state *intel_state =
6148 to_intel_atomic_state(state);
6149
6150 if (max_pixclk < 0)
6151 return max_pixclk;
6152
6153 intel_state->cdclk = intel_state->dev_cdclk =
6154 valleyview_calc_cdclk(dev_priv, max_pixclk);
6155
6156 if (!intel_state->active_crtcs)
6157 intel_state->dev_cdclk = valleyview_calc_cdclk(dev_priv, 0);
6158
6159 return 0;
6160 }
6161
6162 static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
6163 {
6164 struct drm_device *dev = state->dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
6166 int max_pixclk = intel_mode_max_pixclk(dev, state);
6167 struct intel_atomic_state *intel_state =
6168 to_intel_atomic_state(state);
6169
6170 if (max_pixclk < 0)
6171 return max_pixclk;
6172
6173 intel_state->cdclk = intel_state->dev_cdclk =
6174 broxton_calc_cdclk(dev_priv, max_pixclk);
6175
6176 if (!intel_state->active_crtcs)
6177 intel_state->dev_cdclk = broxton_calc_cdclk(dev_priv, 0);
6178
6179 return 0;
6180 }
6181
6182 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
6183 {
6184 unsigned int credits, default_credits;
6185
6186 if (IS_CHERRYVIEW(dev_priv))
6187 default_credits = PFI_CREDIT(12);
6188 else
6189 default_credits = PFI_CREDIT(8);
6190
6191 if (dev_priv->cdclk_freq >= dev_priv->czclk_freq) {
6192 /* CHV suggested value is 31 or 63 */
6193 if (IS_CHERRYVIEW(dev_priv))
6194 credits = PFI_CREDIT_63;
6195 else
6196 credits = PFI_CREDIT(15);
6197 } else {
6198 credits = default_credits;
6199 }
6200
6201 /*
6202 * WA - write default credits before re-programming
6203 * FIXME: should we also set the resend bit here?
6204 */
6205 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6206 default_credits);
6207
6208 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6209 credits | PFI_CREDIT_RESEND);
6210
6211 /*
6212 * FIXME is this guaranteed to clear
6213 * immediately or should we poll for it?
6214 */
6215 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6216 }
6217
6218 static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
6219 {
6220 struct drm_device *dev = old_state->dev;
6221 struct drm_i915_private *dev_priv = dev->dev_private;
6222 struct intel_atomic_state *old_intel_state =
6223 to_intel_atomic_state(old_state);
6224 unsigned req_cdclk = old_intel_state->dev_cdclk;
6225
6226 /*
6227 * FIXME: We can end up here with all power domains off, yet
6228 * with a CDCLK frequency other than the minimum. To account
6229 * for this take the PIPE-A power domain, which covers the HW
6230 * blocks needed for the following programming. This can be
6231 * removed once it's guaranteed that we get here either with
6232 * the minimum CDCLK set, or the required power domains
6233 * enabled.
6234 */
6235 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6236
6237 if (IS_CHERRYVIEW(dev))
6238 cherryview_set_cdclk(dev, req_cdclk);
6239 else
6240 valleyview_set_cdclk(dev, req_cdclk);
6241
6242 vlv_program_pfi_credits(dev_priv);
6243
6244 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
6245 }
6246
6247 static void valleyview_crtc_enable(struct drm_crtc *crtc)
6248 {
6249 struct drm_device *dev = crtc->dev;
6250 struct drm_i915_private *dev_priv = to_i915(dev);
6251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6252 struct intel_encoder *encoder;
6253 int pipe = intel_crtc->pipe;
6254
6255 if (WARN_ON(intel_crtc->active))
6256 return;
6257
6258 if (intel_crtc->config->has_dp_encoder)
6259 intel_dp_set_m_n(intel_crtc, M1_N1);
6260
6261 intel_set_pipe_timings(intel_crtc);
6262
6263 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6264 struct drm_i915_private *dev_priv = dev->dev_private;
6265
6266 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6267 I915_WRITE(CHV_CANVAS(pipe), 0);
6268 }
6269
6270 i9xx_set_pipeconf(intel_crtc);
6271
6272 intel_crtc->active = true;
6273
6274 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6275
6276 for_each_encoder_on_crtc(dev, crtc, encoder)
6277 if (encoder->pre_pll_enable)
6278 encoder->pre_pll_enable(encoder);
6279
6280 if (!intel_crtc->config->has_dsi_encoder) {
6281 if (IS_CHERRYVIEW(dev)) {
6282 chv_prepare_pll(intel_crtc, intel_crtc->config);
6283 chv_enable_pll(intel_crtc, intel_crtc->config);
6284 } else {
6285 vlv_prepare_pll(intel_crtc, intel_crtc->config);
6286 vlv_enable_pll(intel_crtc, intel_crtc->config);
6287 }
6288 }
6289
6290 for_each_encoder_on_crtc(dev, crtc, encoder)
6291 if (encoder->pre_enable)
6292 encoder->pre_enable(encoder);
6293
6294 i9xx_pfit_enable(intel_crtc);
6295
6296 intel_crtc_load_lut(crtc);
6297
6298 intel_enable_pipe(intel_crtc);
6299
6300 assert_vblank_disabled(crtc);
6301 drm_crtc_vblank_on(crtc);
6302
6303 for_each_encoder_on_crtc(dev, crtc, encoder)
6304 encoder->enable(encoder);
6305 }
6306
6307 static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6308 {
6309 struct drm_device *dev = crtc->base.dev;
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311
6312 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6313 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
6314 }
6315
6316 static void i9xx_crtc_enable(struct drm_crtc *crtc)
6317 {
6318 struct drm_device *dev = crtc->dev;
6319 struct drm_i915_private *dev_priv = to_i915(dev);
6320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6321 struct intel_encoder *encoder;
6322 int pipe = intel_crtc->pipe;
6323
6324 if (WARN_ON(intel_crtc->active))
6325 return;
6326
6327 i9xx_set_pll_dividers(intel_crtc);
6328
6329 if (intel_crtc->config->has_dp_encoder)
6330 intel_dp_set_m_n(intel_crtc, M1_N1);
6331
6332 intel_set_pipe_timings(intel_crtc);
6333
6334 i9xx_set_pipeconf(intel_crtc);
6335
6336 intel_crtc->active = true;
6337
6338 if (!IS_GEN2(dev))
6339 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
6340
6341 for_each_encoder_on_crtc(dev, crtc, encoder)
6342 if (encoder->pre_enable)
6343 encoder->pre_enable(encoder);
6344
6345 i9xx_enable_pll(intel_crtc);
6346
6347 i9xx_pfit_enable(intel_crtc);
6348
6349 intel_crtc_load_lut(crtc);
6350
6351 intel_update_watermarks(crtc);
6352 intel_enable_pipe(intel_crtc);
6353
6354 assert_vblank_disabled(crtc);
6355 drm_crtc_vblank_on(crtc);
6356
6357 for_each_encoder_on_crtc(dev, crtc, encoder)
6358 encoder->enable(encoder);
6359
6360 intel_fbc_enable(intel_crtc);
6361 }
6362
6363 static void i9xx_pfit_disable(struct intel_crtc *crtc)
6364 {
6365 struct drm_device *dev = crtc->base.dev;
6366 struct drm_i915_private *dev_priv = dev->dev_private;
6367
6368 if (!crtc->config->gmch_pfit.control)
6369 return;
6370
6371 assert_pipe_disabled(dev_priv, crtc->pipe);
6372
6373 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6374 I915_READ(PFIT_CONTROL));
6375 I915_WRITE(PFIT_CONTROL, 0);
6376 }
6377
6378 static void i9xx_crtc_disable(struct drm_crtc *crtc)
6379 {
6380 struct drm_device *dev = crtc->dev;
6381 struct drm_i915_private *dev_priv = dev->dev_private;
6382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6383 struct intel_encoder *encoder;
6384 int pipe = intel_crtc->pipe;
6385
6386 /*
6387 * On gen2 planes are double buffered but the pipe isn't, so we must
6388 * wait for planes to fully turn off before disabling the pipe.
6389 * We also need to wait on all gmch platforms because of the
6390 * self-refresh mode constraint explained above.
6391 */
6392 intel_wait_for_vblank(dev, pipe);
6393
6394 for_each_encoder_on_crtc(dev, crtc, encoder)
6395 encoder->disable(encoder);
6396
6397 drm_crtc_vblank_off(crtc);
6398 assert_vblank_disabled(crtc);
6399
6400 intel_disable_pipe(intel_crtc);
6401
6402 i9xx_pfit_disable(intel_crtc);
6403
6404 for_each_encoder_on_crtc(dev, crtc, encoder)
6405 if (encoder->post_disable)
6406 encoder->post_disable(encoder);
6407
6408 if (!intel_crtc->config->has_dsi_encoder) {
6409 if (IS_CHERRYVIEW(dev))
6410 chv_disable_pll(dev_priv, pipe);
6411 else if (IS_VALLEYVIEW(dev))
6412 vlv_disable_pll(dev_priv, pipe);
6413 else
6414 i9xx_disable_pll(intel_crtc);
6415 }
6416
6417 for_each_encoder_on_crtc(dev, crtc, encoder)
6418 if (encoder->post_pll_disable)
6419 encoder->post_pll_disable(encoder);
6420
6421 if (!IS_GEN2(dev))
6422 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
6423
6424 intel_fbc_disable_crtc(intel_crtc);
6425 }
6426
6427 static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6428 {
6429 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6430 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6431 enum intel_display_power_domain domain;
6432 unsigned long domains;
6433
6434 if (!intel_crtc->active)
6435 return;
6436
6437 if (to_intel_plane_state(crtc->primary->state)->visible) {
6438 WARN_ON(intel_crtc->unpin_work);
6439
6440 intel_pre_disable_primary(crtc);
6441
6442 intel_crtc_disable_planes(crtc, 1 << drm_plane_index(crtc->primary));
6443 to_intel_plane_state(crtc->primary->state)->visible = false;
6444 }
6445
6446 dev_priv->display.crtc_disable(crtc);
6447 intel_crtc->active = false;
6448 intel_update_watermarks(crtc);
6449 intel_disable_shared_dpll(intel_crtc);
6450
6451 domains = intel_crtc->enabled_power_domains;
6452 for_each_power_domain(domain, domains)
6453 intel_display_power_put(dev_priv, domain);
6454 intel_crtc->enabled_power_domains = 0;
6455
6456 dev_priv->active_crtcs &= ~(1 << intel_crtc->pipe);
6457 dev_priv->min_pixclk[intel_crtc->pipe] = 0;
6458 }
6459
6460 /*
6461 * turn all crtc's off, but do not adjust state
6462 * This has to be paired with a call to intel_modeset_setup_hw_state.
6463 */
6464 int intel_display_suspend(struct drm_device *dev)
6465 {
6466 struct drm_mode_config *config = &dev->mode_config;
6467 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
6468 struct drm_atomic_state *state;
6469 struct drm_crtc *crtc;
6470 unsigned crtc_mask = 0;
6471 int ret = 0;
6472
6473 if (WARN_ON(!ctx))
6474 return 0;
6475
6476 lockdep_assert_held(&ctx->ww_ctx);
6477 state = drm_atomic_state_alloc(dev);
6478 if (WARN_ON(!state))
6479 return -ENOMEM;
6480
6481 state->acquire_ctx = ctx;
6482 state->allow_modeset = true;
6483
6484 for_each_crtc(dev, crtc) {
6485 struct drm_crtc_state *crtc_state =
6486 drm_atomic_get_crtc_state(state, crtc);
6487
6488 ret = PTR_ERR_OR_ZERO(crtc_state);
6489 if (ret)
6490 goto free;
6491
6492 if (!crtc_state->active)
6493 continue;
6494
6495 crtc_state->active = false;
6496 crtc_mask |= 1 << drm_crtc_index(crtc);
6497 }
6498
6499 if (crtc_mask) {
6500 ret = drm_atomic_commit(state);
6501
6502 if (!ret) {
6503 for_each_crtc(dev, crtc)
6504 if (crtc_mask & (1 << drm_crtc_index(crtc)))
6505 crtc->state->active = true;
6506
6507 return ret;
6508 }
6509 }
6510
6511 free:
6512 if (ret)
6513 DRM_ERROR("Suspending crtc's failed with %i\n", ret);
6514 drm_atomic_state_free(state);
6515 return ret;
6516 }
6517
6518 void intel_encoder_destroy(struct drm_encoder *encoder)
6519 {
6520 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
6521
6522 drm_encoder_cleanup(encoder);
6523 kfree(intel_encoder);
6524 }
6525
6526 /* Cross check the actual hw state with our own modeset state tracking (and it's
6527 * internal consistency). */
6528 static void intel_connector_check_state(struct intel_connector *connector)
6529 {
6530 struct drm_crtc *crtc = connector->base.state->crtc;
6531
6532 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6533 connector->base.base.id,
6534 connector->base.name);
6535
6536 if (connector->get_hw_state(connector)) {
6537 struct intel_encoder *encoder = connector->encoder;
6538 struct drm_connector_state *conn_state = connector->base.state;
6539
6540 I915_STATE_WARN(!crtc,
6541 "connector enabled without attached crtc\n");
6542
6543 if (!crtc)
6544 return;
6545
6546 I915_STATE_WARN(!crtc->state->active,
6547 "connector is active, but attached crtc isn't\n");
6548
6549 if (!encoder || encoder->type == INTEL_OUTPUT_DP_MST)
6550 return;
6551
6552 I915_STATE_WARN(conn_state->best_encoder != &encoder->base,
6553 "atomic encoder doesn't match attached encoder\n");
6554
6555 I915_STATE_WARN(conn_state->crtc != encoder->base.crtc,
6556 "attached encoder crtc differs from connector crtc\n");
6557 } else {
6558 I915_STATE_WARN(crtc && crtc->state->active,
6559 "attached crtc is active, but connector isn't\n");
6560 I915_STATE_WARN(!crtc && connector->base.state->best_encoder,
6561 "best encoder set without crtc!\n");
6562 }
6563 }
6564
6565 int intel_connector_init(struct intel_connector *connector)
6566 {
6567 struct drm_connector_state *connector_state;
6568
6569 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6570 if (!connector_state)
6571 return -ENOMEM;
6572
6573 connector->base.state = connector_state;
6574 return 0;
6575 }
6576
6577 struct intel_connector *intel_connector_alloc(void)
6578 {
6579 struct intel_connector *connector;
6580
6581 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6582 if (!connector)
6583 return NULL;
6584
6585 if (intel_connector_init(connector) < 0) {
6586 kfree(connector);
6587 return NULL;
6588 }
6589
6590 return connector;
6591 }
6592
6593 /* Simple connector->get_hw_state implementation for encoders that support only
6594 * one connector and no cloning and hence the encoder state determines the state
6595 * of the connector. */
6596 bool intel_connector_get_hw_state(struct intel_connector *connector)
6597 {
6598 enum pipe pipe = 0;
6599 struct intel_encoder *encoder = connector->encoder;
6600
6601 return encoder->get_hw_state(encoder, &pipe);
6602 }
6603
6604 static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
6605 {
6606 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6607 return crtc_state->fdi_lanes;
6608
6609 return 0;
6610 }
6611
6612 static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
6613 struct intel_crtc_state *pipe_config)
6614 {
6615 struct drm_atomic_state *state = pipe_config->base.state;
6616 struct intel_crtc *other_crtc;
6617 struct intel_crtc_state *other_crtc_state;
6618
6619 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6620 pipe_name(pipe), pipe_config->fdi_lanes);
6621 if (pipe_config->fdi_lanes > 4) {
6622 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6623 pipe_name(pipe), pipe_config->fdi_lanes);
6624 return -EINVAL;
6625 }
6626
6627 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
6628 if (pipe_config->fdi_lanes > 2) {
6629 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6630 pipe_config->fdi_lanes);
6631 return -EINVAL;
6632 } else {
6633 return 0;
6634 }
6635 }
6636
6637 if (INTEL_INFO(dev)->num_pipes == 2)
6638 return 0;
6639
6640 /* Ivybridge 3 pipe is really complicated */
6641 switch (pipe) {
6642 case PIPE_A:
6643 return 0;
6644 case PIPE_B:
6645 if (pipe_config->fdi_lanes <= 2)
6646 return 0;
6647
6648 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6649 other_crtc_state =
6650 intel_atomic_get_crtc_state(state, other_crtc);
6651 if (IS_ERR(other_crtc_state))
6652 return PTR_ERR(other_crtc_state);
6653
6654 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
6655 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6656 pipe_name(pipe), pipe_config->fdi_lanes);
6657 return -EINVAL;
6658 }
6659 return 0;
6660 case PIPE_C:
6661 if (pipe_config->fdi_lanes > 2) {
6662 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6663 pipe_name(pipe), pipe_config->fdi_lanes);
6664 return -EINVAL;
6665 }
6666
6667 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6668 other_crtc_state =
6669 intel_atomic_get_crtc_state(state, other_crtc);
6670 if (IS_ERR(other_crtc_state))
6671 return PTR_ERR(other_crtc_state);
6672
6673 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
6674 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6675 return -EINVAL;
6676 }
6677 return 0;
6678 default:
6679 BUG();
6680 }
6681 }
6682
6683 #define RETRY 1
6684 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
6685 struct intel_crtc_state *pipe_config)
6686 {
6687 struct drm_device *dev = intel_crtc->base.dev;
6688 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6689 int lane, link_bw, fdi_dotclock, ret;
6690 bool needs_recompute = false;
6691
6692 retry:
6693 /* FDI is a binary signal running at ~2.7GHz, encoding
6694 * each output octet as 10 bits. The actual frequency
6695 * is stored as a divider into a 100MHz clock, and the
6696 * mode pixel clock is stored in units of 1KHz.
6697 * Hence the bw of each lane in terms of the mode signal
6698 * is:
6699 */
6700 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6701
6702 fdi_dotclock = adjusted_mode->crtc_clock;
6703
6704 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
6705 pipe_config->pipe_bpp);
6706
6707 pipe_config->fdi_lanes = lane;
6708
6709 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
6710 link_bw, &pipe_config->fdi_m_n);
6711
6712 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6713 intel_crtc->pipe, pipe_config);
6714 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
6715 pipe_config->pipe_bpp -= 2*3;
6716 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6717 pipe_config->pipe_bpp);
6718 needs_recompute = true;
6719 pipe_config->bw_constrained = true;
6720
6721 goto retry;
6722 }
6723
6724 if (needs_recompute)
6725 return RETRY;
6726
6727 return ret;
6728 }
6729
6730 static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6731 struct intel_crtc_state *pipe_config)
6732 {
6733 if (pipe_config->pipe_bpp > 24)
6734 return false;
6735
6736 /* HSW can handle pixel rate up to cdclk? */
6737 if (IS_HASWELL(dev_priv->dev))
6738 return true;
6739
6740 /*
6741 * We compare against max which means we must take
6742 * the increased cdclk requirement into account when
6743 * calculating the new cdclk.
6744 *
6745 * Should measure whether using a lower cdclk w/o IPS
6746 */
6747 return ilk_pipe_pixel_rate(pipe_config) <=
6748 dev_priv->max_cdclk_freq * 95 / 100;
6749 }
6750
6751 static void hsw_compute_ips_config(struct intel_crtc *crtc,
6752 struct intel_crtc_state *pipe_config)
6753 {
6754 struct drm_device *dev = crtc->base.dev;
6755 struct drm_i915_private *dev_priv = dev->dev_private;
6756
6757 pipe_config->ips_enabled = i915.enable_ips &&
6758 hsw_crtc_supports_ips(crtc) &&
6759 pipe_config_supports_ips(dev_priv, pipe_config);
6760 }
6761
6762 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
6763 {
6764 const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6765
6766 /* GDG double wide on either pipe, otherwise pipe A only */
6767 return INTEL_INFO(dev_priv)->gen < 4 &&
6768 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
6769 }
6770
6771 static int intel_crtc_compute_config(struct intel_crtc *crtc,
6772 struct intel_crtc_state *pipe_config)
6773 {
6774 struct drm_device *dev = crtc->base.dev;
6775 struct drm_i915_private *dev_priv = dev->dev_private;
6776 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6777
6778 /* FIXME should check pixel clock limits on all platforms */
6779 if (INTEL_INFO(dev)->gen < 4) {
6780 int clock_limit = dev_priv->max_cdclk_freq * 9 / 10;
6781
6782 /*
6783 * Enable double wide mode when the dot clock
6784 * is > 90% of the (display) core speed.
6785 */
6786 if (intel_crtc_supports_double_wide(crtc) &&
6787 adjusted_mode->crtc_clock > clock_limit) {
6788 clock_limit *= 2;
6789 pipe_config->double_wide = true;
6790 }
6791
6792 if (adjusted_mode->crtc_clock > clock_limit) {
6793 DRM_DEBUG_KMS("requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
6794 adjusted_mode->crtc_clock, clock_limit,
6795 yesno(pipe_config->double_wide));
6796 return -EINVAL;
6797 }
6798 }
6799
6800 /*
6801 * Pipe horizontal size must be even in:
6802 * - DVO ganged mode
6803 * - LVDS dual channel mode
6804 * - Double wide pipe
6805 */
6806 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
6807 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6808 pipe_config->pipe_src_w &= ~1;
6809
6810 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6811 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
6812 */
6813 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6814 adjusted_mode->crtc_hsync_start == adjusted_mode->crtc_hdisplay)
6815 return -EINVAL;
6816
6817 if (HAS_IPS(dev))
6818 hsw_compute_ips_config(crtc, pipe_config);
6819
6820 if (pipe_config->has_pch_encoder)
6821 return ironlake_fdi_compute_config(crtc, pipe_config);
6822
6823 return 0;
6824 }
6825
6826 static int skylake_get_display_clock_speed(struct drm_device *dev)
6827 {
6828 struct drm_i915_private *dev_priv = to_i915(dev);
6829 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6830 uint32_t cdctl = I915_READ(CDCLK_CTL);
6831 uint32_t linkrate;
6832
6833 if (!(lcpll1 & LCPLL_PLL_ENABLE))
6834 return 24000; /* 24MHz is the cd freq with NSSC ref */
6835
6836 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6837 return 540000;
6838
6839 linkrate = (I915_READ(DPLL_CTRL1) &
6840 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
6841
6842 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6843 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
6844 /* vco 8640 */
6845 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6846 case CDCLK_FREQ_450_432:
6847 return 432000;
6848 case CDCLK_FREQ_337_308:
6849 return 308570;
6850 case CDCLK_FREQ_675_617:
6851 return 617140;
6852 default:
6853 WARN(1, "Unknown cd freq selection\n");
6854 }
6855 } else {
6856 /* vco 8100 */
6857 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6858 case CDCLK_FREQ_450_432:
6859 return 450000;
6860 case CDCLK_FREQ_337_308:
6861 return 337500;
6862 case CDCLK_FREQ_675_617:
6863 return 675000;
6864 default:
6865 WARN(1, "Unknown cd freq selection\n");
6866 }
6867 }
6868
6869 /* error case, do as if DPLL0 isn't enabled */
6870 return 24000;
6871 }
6872
6873 static int broxton_get_display_clock_speed(struct drm_device *dev)
6874 {
6875 struct drm_i915_private *dev_priv = to_i915(dev);
6876 uint32_t cdctl = I915_READ(CDCLK_CTL);
6877 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6878 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6879 int cdclk;
6880
6881 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6882 return 19200;
6883
6884 cdclk = 19200 * pll_ratio / 2;
6885
6886 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6887 case BXT_CDCLK_CD2X_DIV_SEL_1:
6888 return cdclk; /* 576MHz or 624MHz */
6889 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6890 return cdclk * 2 / 3; /* 384MHz */
6891 case BXT_CDCLK_CD2X_DIV_SEL_2:
6892 return cdclk / 2; /* 288MHz */
6893 case BXT_CDCLK_CD2X_DIV_SEL_4:
6894 return cdclk / 4; /* 144MHz */
6895 }
6896
6897 /* error case, do as if DE PLL isn't enabled */
6898 return 19200;
6899 }
6900
6901 static int broadwell_get_display_clock_speed(struct drm_device *dev)
6902 {
6903 struct drm_i915_private *dev_priv = dev->dev_private;
6904 uint32_t lcpll = I915_READ(LCPLL_CTL);
6905 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6906
6907 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6908 return 800000;
6909 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6910 return 450000;
6911 else if (freq == LCPLL_CLK_FREQ_450)
6912 return 450000;
6913 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6914 return 540000;
6915 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6916 return 337500;
6917 else
6918 return 675000;
6919 }
6920
6921 static int haswell_get_display_clock_speed(struct drm_device *dev)
6922 {
6923 struct drm_i915_private *dev_priv = dev->dev_private;
6924 uint32_t lcpll = I915_READ(LCPLL_CTL);
6925 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6926
6927 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6928 return 800000;
6929 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6930 return 450000;
6931 else if (freq == LCPLL_CLK_FREQ_450)
6932 return 450000;
6933 else if (IS_HSW_ULT(dev))
6934 return 337500;
6935 else
6936 return 540000;
6937 }
6938
6939 static int valleyview_get_display_clock_speed(struct drm_device *dev)
6940 {
6941 return vlv_get_cck_clock_hpll(to_i915(dev), "cdclk",
6942 CCK_DISPLAY_CLOCK_CONTROL);
6943 }
6944
6945 static int ilk_get_display_clock_speed(struct drm_device *dev)
6946 {
6947 return 450000;
6948 }
6949
6950 static int i945_get_display_clock_speed(struct drm_device *dev)
6951 {
6952 return 400000;
6953 }
6954
6955 static int i915_get_display_clock_speed(struct drm_device *dev)
6956 {
6957 return 333333;
6958 }
6959
6960 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6961 {
6962 return 200000;
6963 }
6964
6965 static int pnv_get_display_clock_speed(struct drm_device *dev)
6966 {
6967 u16 gcfgc = 0;
6968
6969 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6970
6971 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6972 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
6973 return 266667;
6974 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
6975 return 333333;
6976 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
6977 return 444444;
6978 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6979 return 200000;
6980 default:
6981 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6982 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
6983 return 133333;
6984 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
6985 return 166667;
6986 }
6987 }
6988
6989 static int i915gm_get_display_clock_speed(struct drm_device *dev)
6990 {
6991 u16 gcfgc = 0;
6992
6993 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6994
6995 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
6996 return 133333;
6997 else {
6998 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6999 case GC_DISPLAY_CLOCK_333_MHZ:
7000 return 333333;
7001 default:
7002 case GC_DISPLAY_CLOCK_190_200_MHZ:
7003 return 190000;
7004 }
7005 }
7006 }
7007
7008 static int i865_get_display_clock_speed(struct drm_device *dev)
7009 {
7010 return 266667;
7011 }
7012
7013 static int i85x_get_display_clock_speed(struct drm_device *dev)
7014 {
7015 u16 hpllcc = 0;
7016
7017 /*
7018 * 852GM/852GMV only supports 133 MHz and the HPLLCC
7019 * encoding is different :(
7020 * FIXME is this the right way to detect 852GM/852GMV?
7021 */
7022 if (dev->pdev->revision == 0x1)
7023 return 133333;
7024
7025 pci_bus_read_config_word(dev->pdev->bus,
7026 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
7027
7028 /* Assume that the hardware is in the high speed state. This
7029 * should be the default.
7030 */
7031 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
7032 case GC_CLOCK_133_200:
7033 case GC_CLOCK_133_200_2:
7034 case GC_CLOCK_100_200:
7035 return 200000;
7036 case GC_CLOCK_166_250:
7037 return 250000;
7038 case GC_CLOCK_100_133:
7039 return 133333;
7040 case GC_CLOCK_133_266:
7041 case GC_CLOCK_133_266_2:
7042 case GC_CLOCK_166_266:
7043 return 266667;
7044 }
7045
7046 /* Shouldn't happen */
7047 return 0;
7048 }
7049
7050 static int i830_get_display_clock_speed(struct drm_device *dev)
7051 {
7052 return 133333;
7053 }
7054
7055 static unsigned int intel_hpll_vco(struct drm_device *dev)
7056 {
7057 struct drm_i915_private *dev_priv = dev->dev_private;
7058 static const unsigned int blb_vco[8] = {
7059 [0] = 3200000,
7060 [1] = 4000000,
7061 [2] = 5333333,
7062 [3] = 4800000,
7063 [4] = 6400000,
7064 };
7065 static const unsigned int pnv_vco[8] = {
7066 [0] = 3200000,
7067 [1] = 4000000,
7068 [2] = 5333333,
7069 [3] = 4800000,
7070 [4] = 2666667,
7071 };
7072 static const unsigned int cl_vco[8] = {
7073 [0] = 3200000,
7074 [1] = 4000000,
7075 [2] = 5333333,
7076 [3] = 6400000,
7077 [4] = 3333333,
7078 [5] = 3566667,
7079 [6] = 4266667,
7080 };
7081 static const unsigned int elk_vco[8] = {
7082 [0] = 3200000,
7083 [1] = 4000000,
7084 [2] = 5333333,
7085 [3] = 4800000,
7086 };
7087 static const unsigned int ctg_vco[8] = {
7088 [0] = 3200000,
7089 [1] = 4000000,
7090 [2] = 5333333,
7091 [3] = 6400000,
7092 [4] = 2666667,
7093 [5] = 4266667,
7094 };
7095 const unsigned int *vco_table;
7096 unsigned int vco;
7097 uint8_t tmp = 0;
7098
7099 /* FIXME other chipsets? */
7100 if (IS_GM45(dev))
7101 vco_table = ctg_vco;
7102 else if (IS_G4X(dev))
7103 vco_table = elk_vco;
7104 else if (IS_CRESTLINE(dev))
7105 vco_table = cl_vco;
7106 else if (IS_PINEVIEW(dev))
7107 vco_table = pnv_vco;
7108 else if (IS_G33(dev))
7109 vco_table = blb_vco;
7110 else
7111 return 0;
7112
7113 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
7114
7115 vco = vco_table[tmp & 0x7];
7116 if (vco == 0)
7117 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
7118 else
7119 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
7120
7121 return vco;
7122 }
7123
7124 static int gm45_get_display_clock_speed(struct drm_device *dev)
7125 {
7126 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7127 uint16_t tmp = 0;
7128
7129 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7130
7131 cdclk_sel = (tmp >> 12) & 0x1;
7132
7133 switch (vco) {
7134 case 2666667:
7135 case 4000000:
7136 case 5333333:
7137 return cdclk_sel ? 333333 : 222222;
7138 case 3200000:
7139 return cdclk_sel ? 320000 : 228571;
7140 default:
7141 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
7142 return 222222;
7143 }
7144 }
7145
7146 static int i965gm_get_display_clock_speed(struct drm_device *dev)
7147 {
7148 static const uint8_t div_3200[] = { 16, 10, 8 };
7149 static const uint8_t div_4000[] = { 20, 12, 10 };
7150 static const uint8_t div_5333[] = { 24, 16, 14 };
7151 const uint8_t *div_table;
7152 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7153 uint16_t tmp = 0;
7154
7155 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7156
7157 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
7158
7159 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7160 goto fail;
7161
7162 switch (vco) {
7163 case 3200000:
7164 div_table = div_3200;
7165 break;
7166 case 4000000:
7167 div_table = div_4000;
7168 break;
7169 case 5333333:
7170 div_table = div_5333;
7171 break;
7172 default:
7173 goto fail;
7174 }
7175
7176 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7177
7178 fail:
7179 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
7180 return 200000;
7181 }
7182
7183 static int g33_get_display_clock_speed(struct drm_device *dev)
7184 {
7185 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
7186 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
7187 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
7188 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
7189 const uint8_t *div_table;
7190 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7191 uint16_t tmp = 0;
7192
7193 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7194
7195 cdclk_sel = (tmp >> 4) & 0x7;
7196
7197 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7198 goto fail;
7199
7200 switch (vco) {
7201 case 3200000:
7202 div_table = div_3200;
7203 break;
7204 case 4000000:
7205 div_table = div_4000;
7206 break;
7207 case 4800000:
7208 div_table = div_4800;
7209 break;
7210 case 5333333:
7211 div_table = div_5333;
7212 break;
7213 default:
7214 goto fail;
7215 }
7216
7217 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7218
7219 fail:
7220 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7221 return 190476;
7222 }
7223
7224 static void
7225 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
7226 {
7227 while (*num > DATA_LINK_M_N_MASK ||
7228 *den > DATA_LINK_M_N_MASK) {
7229 *num >>= 1;
7230 *den >>= 1;
7231 }
7232 }
7233
7234 static void compute_m_n(unsigned int m, unsigned int n,
7235 uint32_t *ret_m, uint32_t *ret_n)
7236 {
7237 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7238 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7239 intel_reduce_m_n_ratio(ret_m, ret_n);
7240 }
7241
7242 void
7243 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7244 int pixel_clock, int link_clock,
7245 struct intel_link_m_n *m_n)
7246 {
7247 m_n->tu = 64;
7248
7249 compute_m_n(bits_per_pixel * pixel_clock,
7250 link_clock * nlanes * 8,
7251 &m_n->gmch_m, &m_n->gmch_n);
7252
7253 compute_m_n(pixel_clock, link_clock,
7254 &m_n->link_m, &m_n->link_n);
7255 }
7256
7257 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7258 {
7259 if (i915.panel_use_ssc >= 0)
7260 return i915.panel_use_ssc != 0;
7261 return dev_priv->vbt.lvds_use_ssc
7262 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
7263 }
7264
7265 static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7266 int num_connectors)
7267 {
7268 struct drm_device *dev = crtc_state->base.crtc->dev;
7269 struct drm_i915_private *dev_priv = dev->dev_private;
7270 int refclk;
7271
7272 WARN_ON(!crtc_state->base.state);
7273
7274 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || IS_BROXTON(dev)) {
7275 refclk = 100000;
7276 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7277 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
7278 refclk = dev_priv->vbt.lvds_ssc_freq;
7279 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
7280 } else if (!IS_GEN2(dev)) {
7281 refclk = 96000;
7282 } else {
7283 refclk = 48000;
7284 }
7285
7286 return refclk;
7287 }
7288
7289 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
7290 {
7291 return (1 << dpll->n) << 16 | dpll->m2;
7292 }
7293
7294 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7295 {
7296 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
7297 }
7298
7299 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
7300 struct intel_crtc_state *crtc_state,
7301 intel_clock_t *reduced_clock)
7302 {
7303 struct drm_device *dev = crtc->base.dev;
7304 u32 fp, fp2 = 0;
7305
7306 if (IS_PINEVIEW(dev)) {
7307 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
7308 if (reduced_clock)
7309 fp2 = pnv_dpll_compute_fp(reduced_clock);
7310 } else {
7311 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
7312 if (reduced_clock)
7313 fp2 = i9xx_dpll_compute_fp(reduced_clock);
7314 }
7315
7316 crtc_state->dpll_hw_state.fp0 = fp;
7317
7318 crtc->lowfreq_avail = false;
7319 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7320 reduced_clock) {
7321 crtc_state->dpll_hw_state.fp1 = fp2;
7322 crtc->lowfreq_avail = true;
7323 } else {
7324 crtc_state->dpll_hw_state.fp1 = fp;
7325 }
7326 }
7327
7328 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7329 pipe)
7330 {
7331 u32 reg_val;
7332
7333 /*
7334 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7335 * and set it to a reasonable value instead.
7336 */
7337 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7338 reg_val &= 0xffffff00;
7339 reg_val |= 0x00000030;
7340 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7341
7342 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7343 reg_val &= 0x8cffffff;
7344 reg_val = 0x8c000000;
7345 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7346
7347 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
7348 reg_val &= 0xffffff00;
7349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
7350
7351 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
7352 reg_val &= 0x00ffffff;
7353 reg_val |= 0xb0000000;
7354 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
7355 }
7356
7357 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7358 struct intel_link_m_n *m_n)
7359 {
7360 struct drm_device *dev = crtc->base.dev;
7361 struct drm_i915_private *dev_priv = dev->dev_private;
7362 int pipe = crtc->pipe;
7363
7364 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7365 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7366 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7367 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
7368 }
7369
7370 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
7371 struct intel_link_m_n *m_n,
7372 struct intel_link_m_n *m2_n2)
7373 {
7374 struct drm_device *dev = crtc->base.dev;
7375 struct drm_i915_private *dev_priv = dev->dev_private;
7376 int pipe = crtc->pipe;
7377 enum transcoder transcoder = crtc->config->cpu_transcoder;
7378
7379 if (INTEL_INFO(dev)->gen >= 5) {
7380 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7381 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7382 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7383 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
7384 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7385 * for gen < 8) and if DRRS is supported (to make sure the
7386 * registers are not unnecessarily accessed).
7387 */
7388 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
7389 crtc->config->has_drrs) {
7390 I915_WRITE(PIPE_DATA_M2(transcoder),
7391 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7392 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7393 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7394 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7395 }
7396 } else {
7397 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7398 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7399 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7400 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
7401 }
7402 }
7403
7404 void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
7405 {
7406 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7407
7408 if (m_n == M1_N1) {
7409 dp_m_n = &crtc->config->dp_m_n;
7410 dp_m2_n2 = &crtc->config->dp_m2_n2;
7411 } else if (m_n == M2_N2) {
7412
7413 /*
7414 * M2_N2 registers are not supported. Hence m2_n2 divider value
7415 * needs to be programmed into M1_N1.
7416 */
7417 dp_m_n = &crtc->config->dp_m2_n2;
7418 } else {
7419 DRM_ERROR("Unsupported divider value\n");
7420 return;
7421 }
7422
7423 if (crtc->config->has_pch_encoder)
7424 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
7425 else
7426 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
7427 }
7428
7429 static void vlv_compute_dpll(struct intel_crtc *crtc,
7430 struct intel_crtc_state *pipe_config)
7431 {
7432 u32 dpll, dpll_md;
7433
7434 /*
7435 * Enable DPIO clock input. We should never disable the reference
7436 * clock for pipe B, since VGA hotplug / manual detection depends
7437 * on it.
7438 */
7439 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7440 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
7441 /* We should never disable this, set it here for state tracking */
7442 if (crtc->pipe == PIPE_B)
7443 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7444 dpll |= DPLL_VCO_ENABLE;
7445 pipe_config->dpll_hw_state.dpll = dpll;
7446
7447 dpll_md = (pipe_config->pixel_multiplier - 1)
7448 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7449 pipe_config->dpll_hw_state.dpll_md = dpll_md;
7450 }
7451
7452 static void vlv_prepare_pll(struct intel_crtc *crtc,
7453 const struct intel_crtc_state *pipe_config)
7454 {
7455 struct drm_device *dev = crtc->base.dev;
7456 struct drm_i915_private *dev_priv = dev->dev_private;
7457 int pipe = crtc->pipe;
7458 u32 mdiv;
7459 u32 bestn, bestm1, bestm2, bestp1, bestp2;
7460 u32 coreclk, reg_val;
7461
7462 mutex_lock(&dev_priv->sb_lock);
7463
7464 bestn = pipe_config->dpll.n;
7465 bestm1 = pipe_config->dpll.m1;
7466 bestm2 = pipe_config->dpll.m2;
7467 bestp1 = pipe_config->dpll.p1;
7468 bestp2 = pipe_config->dpll.p2;
7469
7470 /* See eDP HDMI DPIO driver vbios notes doc */
7471
7472 /* PLL B needs special handling */
7473 if (pipe == PIPE_B)
7474 vlv_pllb_recal_opamp(dev_priv, pipe);
7475
7476 /* Set up Tx target for periodic Rcomp update */
7477 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
7478
7479 /* Disable target IRef on PLL */
7480 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
7481 reg_val &= 0x00ffffff;
7482 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
7483
7484 /* Disable fast lock */
7485 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
7486
7487 /* Set idtafcrecal before PLL is enabled */
7488 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7489 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7490 mdiv |= ((bestn << DPIO_N_SHIFT));
7491 mdiv |= (1 << DPIO_K_SHIFT);
7492
7493 /*
7494 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7495 * but we don't support that).
7496 * Note: don't use the DAC post divider as it seems unstable.
7497 */
7498 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
7499 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7500
7501 mdiv |= DPIO_ENABLE_CALIBRATION;
7502 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
7503
7504 /* Set HBR and RBR LPF coefficients */
7505 if (pipe_config->port_clock == 162000 ||
7506 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7507 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
7508 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7509 0x009f0003);
7510 else
7511 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
7512 0x00d0000f);
7513
7514 if (pipe_config->has_dp_encoder) {
7515 /* Use SSC source */
7516 if (pipe == PIPE_A)
7517 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7518 0x0df40000);
7519 else
7520 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7521 0x0df70000);
7522 } else { /* HDMI or VGA */
7523 /* Use bend source */
7524 if (pipe == PIPE_A)
7525 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7526 0x0df70000);
7527 else
7528 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
7529 0x0df40000);
7530 }
7531
7532 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
7533 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
7534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7535 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
7536 coreclk |= 0x01000000;
7537 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
7538
7539 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
7540 mutex_unlock(&dev_priv->sb_lock);
7541 }
7542
7543 static void chv_compute_dpll(struct intel_crtc *crtc,
7544 struct intel_crtc_state *pipe_config)
7545 {
7546 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7547 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7548 DPLL_VCO_ENABLE;
7549 if (crtc->pipe != PIPE_A)
7550 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7551
7552 pipe_config->dpll_hw_state.dpll_md =
7553 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7554 }
7555
7556 static void chv_prepare_pll(struct intel_crtc *crtc,
7557 const struct intel_crtc_state *pipe_config)
7558 {
7559 struct drm_device *dev = crtc->base.dev;
7560 struct drm_i915_private *dev_priv = dev->dev_private;
7561 int pipe = crtc->pipe;
7562 i915_reg_t dpll_reg = DPLL(crtc->pipe);
7563 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7564 u32 loopfilter, tribuf_calcntr;
7565 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
7566 u32 dpio_val;
7567 int vco;
7568
7569 bestn = pipe_config->dpll.n;
7570 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7571 bestm1 = pipe_config->dpll.m1;
7572 bestm2 = pipe_config->dpll.m2 >> 22;
7573 bestp1 = pipe_config->dpll.p1;
7574 bestp2 = pipe_config->dpll.p2;
7575 vco = pipe_config->dpll.vco;
7576 dpio_val = 0;
7577 loopfilter = 0;
7578
7579 /*
7580 * Enable Refclk and SSC
7581 */
7582 I915_WRITE(dpll_reg,
7583 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
7584
7585 mutex_lock(&dev_priv->sb_lock);
7586
7587 /* p1 and p2 divider */
7588 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7589 5 << DPIO_CHV_S1_DIV_SHIFT |
7590 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7591 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7592 1 << DPIO_CHV_K_DIV_SHIFT);
7593
7594 /* Feedback post-divider - m2 */
7595 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7596
7597 /* Feedback refclk divider - n and m1 */
7598 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7599 DPIO_CHV_M1_DIV_BY_2 |
7600 1 << DPIO_CHV_N_DIV_SHIFT);
7601
7602 /* M2 fraction division */
7603 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
7604
7605 /* M2 fraction division enable */
7606 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7607 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7608 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7609 if (bestm2_frac)
7610 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7611 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
7612
7613 /* Program digital lock detect threshold */
7614 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7615 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7616 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7617 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7618 if (!bestm2_frac)
7619 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7620 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7621
7622 /* Loop filter */
7623 if (vco == 5400000) {
7624 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7625 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7626 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7627 tribuf_calcntr = 0x9;
7628 } else if (vco <= 6200000) {
7629 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7630 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7631 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7632 tribuf_calcntr = 0x9;
7633 } else if (vco <= 6480000) {
7634 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7635 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7636 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7637 tribuf_calcntr = 0x8;
7638 } else {
7639 /* Not supported. Apply the same limits as in the max case */
7640 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7641 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7642 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7643 tribuf_calcntr = 0;
7644 }
7645 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7646
7647 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
7648 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7649 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7650 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7651
7652 /* AFC Recal */
7653 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7654 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7655 DPIO_AFC_RECAL);
7656
7657 mutex_unlock(&dev_priv->sb_lock);
7658 }
7659
7660 /**
7661 * vlv_force_pll_on - forcibly enable just the PLL
7662 * @dev_priv: i915 private structure
7663 * @pipe: pipe PLL to enable
7664 * @dpll: PLL configuration
7665 *
7666 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7667 * in cases where we need the PLL enabled even when @pipe is not going to
7668 * be enabled.
7669 */
7670 void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7671 const struct dpll *dpll)
7672 {
7673 struct intel_crtc *crtc =
7674 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
7675 struct intel_crtc_state pipe_config = {
7676 .base.crtc = &crtc->base,
7677 .pixel_multiplier = 1,
7678 .dpll = *dpll,
7679 };
7680
7681 if (IS_CHERRYVIEW(dev)) {
7682 chv_compute_dpll(crtc, &pipe_config);
7683 chv_prepare_pll(crtc, &pipe_config);
7684 chv_enable_pll(crtc, &pipe_config);
7685 } else {
7686 vlv_compute_dpll(crtc, &pipe_config);
7687 vlv_prepare_pll(crtc, &pipe_config);
7688 vlv_enable_pll(crtc, &pipe_config);
7689 }
7690 }
7691
7692 /**
7693 * vlv_force_pll_off - forcibly disable just the PLL
7694 * @dev_priv: i915 private structure
7695 * @pipe: pipe PLL to disable
7696 *
7697 * Disable the PLL for @pipe. To be used in cases where we need
7698 * the PLL enabled even when @pipe is not going to be enabled.
7699 */
7700 void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7701 {
7702 if (IS_CHERRYVIEW(dev))
7703 chv_disable_pll(to_i915(dev), pipe);
7704 else
7705 vlv_disable_pll(to_i915(dev), pipe);
7706 }
7707
7708 static void i9xx_compute_dpll(struct intel_crtc *crtc,
7709 struct intel_crtc_state *crtc_state,
7710 intel_clock_t *reduced_clock,
7711 int num_connectors)
7712 {
7713 struct drm_device *dev = crtc->base.dev;
7714 struct drm_i915_private *dev_priv = dev->dev_private;
7715 u32 dpll;
7716 bool is_sdvo;
7717 struct dpll *clock = &crtc_state->dpll;
7718
7719 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7720
7721 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7722 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
7723
7724 dpll = DPLL_VGA_MODE_DIS;
7725
7726 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
7727 dpll |= DPLLB_MODE_LVDS;
7728 else
7729 dpll |= DPLLB_MODE_DAC_SERIAL;
7730
7731 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7732 dpll |= (crtc_state->pixel_multiplier - 1)
7733 << SDVO_MULTIPLIER_SHIFT_HIRES;
7734 }
7735
7736 if (is_sdvo)
7737 dpll |= DPLL_SDVO_HIGH_SPEED;
7738
7739 if (crtc_state->has_dp_encoder)
7740 dpll |= DPLL_SDVO_HIGH_SPEED;
7741
7742 /* compute bitmask from p1 value */
7743 if (IS_PINEVIEW(dev))
7744 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7745 else {
7746 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7747 if (IS_G4X(dev) && reduced_clock)
7748 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7749 }
7750 switch (clock->p2) {
7751 case 5:
7752 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7753 break;
7754 case 7:
7755 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7756 break;
7757 case 10:
7758 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7759 break;
7760 case 14:
7761 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7762 break;
7763 }
7764 if (INTEL_INFO(dev)->gen >= 4)
7765 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7766
7767 if (crtc_state->sdvo_tv_clock)
7768 dpll |= PLL_REF_INPUT_TVCLKINBC;
7769 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7770 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7771 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7772 else
7773 dpll |= PLL_REF_INPUT_DREFCLK;
7774
7775 dpll |= DPLL_VCO_ENABLE;
7776 crtc_state->dpll_hw_state.dpll = dpll;
7777
7778 if (INTEL_INFO(dev)->gen >= 4) {
7779 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
7780 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
7781 crtc_state->dpll_hw_state.dpll_md = dpll_md;
7782 }
7783 }
7784
7785 static void i8xx_compute_dpll(struct intel_crtc *crtc,
7786 struct intel_crtc_state *crtc_state,
7787 intel_clock_t *reduced_clock,
7788 int num_connectors)
7789 {
7790 struct drm_device *dev = crtc->base.dev;
7791 struct drm_i915_private *dev_priv = dev->dev_private;
7792 u32 dpll;
7793 struct dpll *clock = &crtc_state->dpll;
7794
7795 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
7796
7797 dpll = DPLL_VGA_MODE_DIS;
7798
7799 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
7800 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7801 } else {
7802 if (clock->p1 == 2)
7803 dpll |= PLL_P1_DIVIDE_BY_TWO;
7804 else
7805 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7806 if (clock->p2 == 4)
7807 dpll |= PLL_P2_DIVIDE_BY_4;
7808 }
7809
7810 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
7811 dpll |= DPLL_DVO_2X_MODE;
7812
7813 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
7814 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7815 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7816 else
7817 dpll |= PLL_REF_INPUT_DREFCLK;
7818
7819 dpll |= DPLL_VCO_ENABLE;
7820 crtc_state->dpll_hw_state.dpll = dpll;
7821 }
7822
7823 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
7824 {
7825 struct drm_device *dev = intel_crtc->base.dev;
7826 struct drm_i915_private *dev_priv = dev->dev_private;
7827 enum pipe pipe = intel_crtc->pipe;
7828 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
7829 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
7830 uint32_t crtc_vtotal, crtc_vblank_end;
7831 int vsyncshift = 0;
7832
7833 /* We need to be careful not to changed the adjusted mode, for otherwise
7834 * the hw state checker will get angry at the mismatch. */
7835 crtc_vtotal = adjusted_mode->crtc_vtotal;
7836 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
7837
7838 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
7839 /* the chip adds 2 halflines automatically */
7840 crtc_vtotal -= 1;
7841 crtc_vblank_end -= 1;
7842
7843 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7844 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7845 else
7846 vsyncshift = adjusted_mode->crtc_hsync_start -
7847 adjusted_mode->crtc_htotal / 2;
7848 if (vsyncshift < 0)
7849 vsyncshift += adjusted_mode->crtc_htotal;
7850 }
7851
7852 if (INTEL_INFO(dev)->gen > 3)
7853 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
7854
7855 I915_WRITE(HTOTAL(cpu_transcoder),
7856 (adjusted_mode->crtc_hdisplay - 1) |
7857 ((adjusted_mode->crtc_htotal - 1) << 16));
7858 I915_WRITE(HBLANK(cpu_transcoder),
7859 (adjusted_mode->crtc_hblank_start - 1) |
7860 ((adjusted_mode->crtc_hblank_end - 1) << 16));
7861 I915_WRITE(HSYNC(cpu_transcoder),
7862 (adjusted_mode->crtc_hsync_start - 1) |
7863 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7864
7865 I915_WRITE(VTOTAL(cpu_transcoder),
7866 (adjusted_mode->crtc_vdisplay - 1) |
7867 ((crtc_vtotal - 1) << 16));
7868 I915_WRITE(VBLANK(cpu_transcoder),
7869 (adjusted_mode->crtc_vblank_start - 1) |
7870 ((crtc_vblank_end - 1) << 16));
7871 I915_WRITE(VSYNC(cpu_transcoder),
7872 (adjusted_mode->crtc_vsync_start - 1) |
7873 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7874
7875 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7876 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7877 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7878 * bits. */
7879 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7880 (pipe == PIPE_B || pipe == PIPE_C))
7881 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7882
7883 /* pipesrc controls the size that is scaled from, which should
7884 * always be the user's requested size.
7885 */
7886 I915_WRITE(PIPESRC(pipe),
7887 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7888 (intel_crtc->config->pipe_src_h - 1));
7889 }
7890
7891 static void intel_get_pipe_timings(struct intel_crtc *crtc,
7892 struct intel_crtc_state *pipe_config)
7893 {
7894 struct drm_device *dev = crtc->base.dev;
7895 struct drm_i915_private *dev_priv = dev->dev_private;
7896 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7897 uint32_t tmp;
7898
7899 tmp = I915_READ(HTOTAL(cpu_transcoder));
7900 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7901 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
7902 tmp = I915_READ(HBLANK(cpu_transcoder));
7903 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7904 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
7905 tmp = I915_READ(HSYNC(cpu_transcoder));
7906 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7907 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
7908
7909 tmp = I915_READ(VTOTAL(cpu_transcoder));
7910 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7911 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
7912 tmp = I915_READ(VBLANK(cpu_transcoder));
7913 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7914 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
7915 tmp = I915_READ(VSYNC(cpu_transcoder));
7916 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7917 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
7918
7919 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
7920 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7921 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7922 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
7923 }
7924
7925 tmp = I915_READ(PIPESRC(crtc->pipe));
7926 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7927 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7928
7929 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7930 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
7931 }
7932
7933 void intel_mode_from_pipe_config(struct drm_display_mode *mode,
7934 struct intel_crtc_state *pipe_config)
7935 {
7936 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7937 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7938 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7939 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
7940
7941 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7942 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7943 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7944 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
7945
7946 mode->flags = pipe_config->base.adjusted_mode.flags;
7947 mode->type = DRM_MODE_TYPE_DRIVER;
7948
7949 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7950 mode->flags |= pipe_config->base.adjusted_mode.flags;
7951
7952 mode->hsync = drm_mode_hsync(mode);
7953 mode->vrefresh = drm_mode_vrefresh(mode);
7954 drm_mode_set_name(mode);
7955 }
7956
7957 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7958 {
7959 struct drm_device *dev = intel_crtc->base.dev;
7960 struct drm_i915_private *dev_priv = dev->dev_private;
7961 uint32_t pipeconf;
7962
7963 pipeconf = 0;
7964
7965 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7966 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7967 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
7968
7969 if (intel_crtc->config->double_wide)
7970 pipeconf |= PIPECONF_DOUBLE_WIDE;
7971
7972 /* only g4x and later have fancy bpc/dither controls */
7973 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
7974 /* Bspec claims that we can't use dithering for 30bpp pipes. */
7975 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
7976 pipeconf |= PIPECONF_DITHER_EN |
7977 PIPECONF_DITHER_TYPE_SP;
7978
7979 switch (intel_crtc->config->pipe_bpp) {
7980 case 18:
7981 pipeconf |= PIPECONF_6BPC;
7982 break;
7983 case 24:
7984 pipeconf |= PIPECONF_8BPC;
7985 break;
7986 case 30:
7987 pipeconf |= PIPECONF_10BPC;
7988 break;
7989 default:
7990 /* Case prevented by intel_choose_pipe_bpp_dither. */
7991 BUG();
7992 }
7993 }
7994
7995 if (HAS_PIPE_CXSR(dev)) {
7996 if (intel_crtc->lowfreq_avail) {
7997 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7998 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7999 } else {
8000 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
8001 }
8002 }
8003
8004 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
8005 if (INTEL_INFO(dev)->gen < 4 ||
8006 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
8007 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
8008 else
8009 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
8010 } else
8011 pipeconf |= PIPECONF_PROGRESSIVE;
8012
8013 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8014 intel_crtc->config->limited_color_range)
8015 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
8016
8017 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
8018 POSTING_READ(PIPECONF(intel_crtc->pipe));
8019 }
8020
8021 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
8022 struct intel_crtc_state *crtc_state)
8023 {
8024 struct drm_device *dev = crtc->base.dev;
8025 struct drm_i915_private *dev_priv = dev->dev_private;
8026 int refclk, num_connectors = 0;
8027 intel_clock_t clock;
8028 bool ok;
8029 const intel_limit_t *limit;
8030 struct drm_atomic_state *state = crtc_state->base.state;
8031 struct drm_connector *connector;
8032 struct drm_connector_state *connector_state;
8033 int i;
8034
8035 memset(&crtc_state->dpll_hw_state, 0,
8036 sizeof(crtc_state->dpll_hw_state));
8037
8038 if (crtc_state->has_dsi_encoder)
8039 return 0;
8040
8041 for_each_connector_in_state(state, connector, connector_state, i) {
8042 if (connector_state->crtc == &crtc->base)
8043 num_connectors++;
8044 }
8045
8046 if (!crtc_state->clock_set) {
8047 refclk = i9xx_get_refclk(crtc_state, num_connectors);
8048
8049 /*
8050 * Returns a set of divisors for the desired target clock with
8051 * the given refclk, or FALSE. The returned values represent
8052 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
8053 * 2) / p1 / p2.
8054 */
8055 limit = intel_limit(crtc_state, refclk);
8056 ok = dev_priv->display.find_dpll(limit, crtc_state,
8057 crtc_state->port_clock,
8058 refclk, NULL, &clock);
8059 if (!ok) {
8060 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8061 return -EINVAL;
8062 }
8063
8064 /* Compat-code for transition, will disappear. */
8065 crtc_state->dpll.n = clock.n;
8066 crtc_state->dpll.m1 = clock.m1;
8067 crtc_state->dpll.m2 = clock.m2;
8068 crtc_state->dpll.p1 = clock.p1;
8069 crtc_state->dpll.p2 = clock.p2;
8070 }
8071
8072 if (IS_GEN2(dev)) {
8073 i8xx_compute_dpll(crtc, crtc_state, NULL,
8074 num_connectors);
8075 } else if (IS_CHERRYVIEW(dev)) {
8076 chv_compute_dpll(crtc, crtc_state);
8077 } else if (IS_VALLEYVIEW(dev)) {
8078 vlv_compute_dpll(crtc, crtc_state);
8079 } else {
8080 i9xx_compute_dpll(crtc, crtc_state, NULL,
8081 num_connectors);
8082 }
8083
8084 return 0;
8085 }
8086
8087 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
8088 struct intel_crtc_state *pipe_config)
8089 {
8090 struct drm_device *dev = crtc->base.dev;
8091 struct drm_i915_private *dev_priv = dev->dev_private;
8092 uint32_t tmp;
8093
8094 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
8095 return;
8096
8097 tmp = I915_READ(PFIT_CONTROL);
8098 if (!(tmp & PFIT_ENABLE))
8099 return;
8100
8101 /* Check whether the pfit is attached to our pipe. */
8102 if (INTEL_INFO(dev)->gen < 4) {
8103 if (crtc->pipe != PIPE_B)
8104 return;
8105 } else {
8106 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
8107 return;
8108 }
8109
8110 pipe_config->gmch_pfit.control = tmp;
8111 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
8112 if (INTEL_INFO(dev)->gen < 5)
8113 pipe_config->gmch_pfit.lvds_border_bits =
8114 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
8115 }
8116
8117 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
8118 struct intel_crtc_state *pipe_config)
8119 {
8120 struct drm_device *dev = crtc->base.dev;
8121 struct drm_i915_private *dev_priv = dev->dev_private;
8122 int pipe = pipe_config->cpu_transcoder;
8123 intel_clock_t clock;
8124 u32 mdiv;
8125 int refclk = 100000;
8126
8127 /* In case of MIPI DPLL will not even be used */
8128 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
8129 return;
8130
8131 mutex_lock(&dev_priv->sb_lock);
8132 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
8133 mutex_unlock(&dev_priv->sb_lock);
8134
8135 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
8136 clock.m2 = mdiv & DPIO_M2DIV_MASK;
8137 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
8138 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
8139 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
8140
8141 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
8142 }
8143
8144 static void
8145 i9xx_get_initial_plane_config(struct intel_crtc *crtc,
8146 struct intel_initial_plane_config *plane_config)
8147 {
8148 struct drm_device *dev = crtc->base.dev;
8149 struct drm_i915_private *dev_priv = dev->dev_private;
8150 u32 val, base, offset;
8151 int pipe = crtc->pipe, plane = crtc->plane;
8152 int fourcc, pixel_format;
8153 unsigned int aligned_height;
8154 struct drm_framebuffer *fb;
8155 struct intel_framebuffer *intel_fb;
8156
8157 val = I915_READ(DSPCNTR(plane));
8158 if (!(val & DISPLAY_PLANE_ENABLE))
8159 return;
8160
8161 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8162 if (!intel_fb) {
8163 DRM_DEBUG_KMS("failed to alloc fb\n");
8164 return;
8165 }
8166
8167 fb = &intel_fb->base;
8168
8169 if (INTEL_INFO(dev)->gen >= 4) {
8170 if (val & DISPPLANE_TILED) {
8171 plane_config->tiling = I915_TILING_X;
8172 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8173 }
8174 }
8175
8176 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
8177 fourcc = i9xx_format_to_fourcc(pixel_format);
8178 fb->pixel_format = fourcc;
8179 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8180
8181 if (INTEL_INFO(dev)->gen >= 4) {
8182 if (plane_config->tiling)
8183 offset = I915_READ(DSPTILEOFF(plane));
8184 else
8185 offset = I915_READ(DSPLINOFF(plane));
8186 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8187 } else {
8188 base = I915_READ(DSPADDR(plane));
8189 }
8190 plane_config->base = base;
8191
8192 val = I915_READ(PIPESRC(pipe));
8193 fb->width = ((val >> 16) & 0xfff) + 1;
8194 fb->height = ((val >> 0) & 0xfff) + 1;
8195
8196 val = I915_READ(DSPSTRIDE(pipe));
8197 fb->pitches[0] = val & 0xffffffc0;
8198
8199 aligned_height = intel_fb_align_height(dev, fb->height,
8200 fb->pixel_format,
8201 fb->modifier[0]);
8202
8203 plane_config->size = fb->pitches[0] * aligned_height;
8204
8205 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8206 pipe_name(pipe), plane, fb->width, fb->height,
8207 fb->bits_per_pixel, base, fb->pitches[0],
8208 plane_config->size);
8209
8210 plane_config->fb = intel_fb;
8211 }
8212
8213 static void chv_crtc_clock_get(struct intel_crtc *crtc,
8214 struct intel_crtc_state *pipe_config)
8215 {
8216 struct drm_device *dev = crtc->base.dev;
8217 struct drm_i915_private *dev_priv = dev->dev_private;
8218 int pipe = pipe_config->cpu_transcoder;
8219 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8220 intel_clock_t clock;
8221 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
8222 int refclk = 100000;
8223
8224 mutex_lock(&dev_priv->sb_lock);
8225 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8226 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8227 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8228 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
8229 pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
8230 mutex_unlock(&dev_priv->sb_lock);
8231
8232 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8233 clock.m2 = (pll_dw0 & 0xff) << 22;
8234 if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
8235 clock.m2 |= pll_dw2 & 0x3fffff;
8236 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8237 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8238 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8239
8240 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
8241 }
8242
8243 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
8244 struct intel_crtc_state *pipe_config)
8245 {
8246 struct drm_device *dev = crtc->base.dev;
8247 struct drm_i915_private *dev_priv = dev->dev_private;
8248 uint32_t tmp;
8249
8250 if (!intel_display_power_is_enabled(dev_priv,
8251 POWER_DOMAIN_PIPE(crtc->pipe)))
8252 return false;
8253
8254 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
8255 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8256
8257 tmp = I915_READ(PIPECONF(crtc->pipe));
8258 if (!(tmp & PIPECONF_ENABLE))
8259 return false;
8260
8261 if (IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
8262 switch (tmp & PIPECONF_BPC_MASK) {
8263 case PIPECONF_6BPC:
8264 pipe_config->pipe_bpp = 18;
8265 break;
8266 case PIPECONF_8BPC:
8267 pipe_config->pipe_bpp = 24;
8268 break;
8269 case PIPECONF_10BPC:
8270 pipe_config->pipe_bpp = 30;
8271 break;
8272 default:
8273 break;
8274 }
8275 }
8276
8277 if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
8278 (tmp & PIPECONF_COLOR_RANGE_SELECT))
8279 pipe_config->limited_color_range = true;
8280
8281 if (INTEL_INFO(dev)->gen < 4)
8282 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8283
8284 intel_get_pipe_timings(crtc, pipe_config);
8285
8286 i9xx_get_pfit_config(crtc, pipe_config);
8287
8288 if (INTEL_INFO(dev)->gen >= 4) {
8289 tmp = I915_READ(DPLL_MD(crtc->pipe));
8290 pipe_config->pixel_multiplier =
8291 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8292 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8293 pipe_config->dpll_hw_state.dpll_md = tmp;
8294 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8295 tmp = I915_READ(DPLL(crtc->pipe));
8296 pipe_config->pixel_multiplier =
8297 ((tmp & SDVO_MULTIPLIER_MASK)
8298 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8299 } else {
8300 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8301 * port and will be fixed up in the encoder->get_config
8302 * function. */
8303 pipe_config->pixel_multiplier = 1;
8304 }
8305 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8306 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
8307 /*
8308 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8309 * on 830. Filter it out here so that we don't
8310 * report errors due to that.
8311 */
8312 if (IS_I830(dev))
8313 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8314
8315 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8316 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
8317 } else {
8318 /* Mask out read-only status bits. */
8319 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8320 DPLL_PORTC_READY_MASK |
8321 DPLL_PORTB_READY_MASK);
8322 }
8323
8324 if (IS_CHERRYVIEW(dev))
8325 chv_crtc_clock_get(crtc, pipe_config);
8326 else if (IS_VALLEYVIEW(dev))
8327 vlv_crtc_clock_get(crtc, pipe_config);
8328 else
8329 i9xx_crtc_clock_get(crtc, pipe_config);
8330
8331 /*
8332 * Normally the dotclock is filled in by the encoder .get_config()
8333 * but in case the pipe is enabled w/o any ports we need a sane
8334 * default.
8335 */
8336 pipe_config->base.adjusted_mode.crtc_clock =
8337 pipe_config->port_clock / pipe_config->pixel_multiplier;
8338
8339 return true;
8340 }
8341
8342 static void ironlake_init_pch_refclk(struct drm_device *dev)
8343 {
8344 struct drm_i915_private *dev_priv = dev->dev_private;
8345 struct intel_encoder *encoder;
8346 u32 val, final;
8347 bool has_lvds = false;
8348 bool has_cpu_edp = false;
8349 bool has_panel = false;
8350 bool has_ck505 = false;
8351 bool can_ssc = false;
8352
8353 /* We need to take the global config into account */
8354 for_each_intel_encoder(dev, encoder) {
8355 switch (encoder->type) {
8356 case INTEL_OUTPUT_LVDS:
8357 has_panel = true;
8358 has_lvds = true;
8359 break;
8360 case INTEL_OUTPUT_EDP:
8361 has_panel = true;
8362 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
8363 has_cpu_edp = true;
8364 break;
8365 default:
8366 break;
8367 }
8368 }
8369
8370 if (HAS_PCH_IBX(dev)) {
8371 has_ck505 = dev_priv->vbt.display_clock_mode;
8372 can_ssc = has_ck505;
8373 } else {
8374 has_ck505 = false;
8375 can_ssc = true;
8376 }
8377
8378 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8379 has_panel, has_lvds, has_ck505);
8380
8381 /* Ironlake: try to setup display ref clock before DPLL
8382 * enabling. This is only under driver's control after
8383 * PCH B stepping, previous chipset stepping should be
8384 * ignoring this setting.
8385 */
8386 val = I915_READ(PCH_DREF_CONTROL);
8387
8388 /* As we must carefully and slowly disable/enable each source in turn,
8389 * compute the final state we want first and check if we need to
8390 * make any changes at all.
8391 */
8392 final = val;
8393 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8394 if (has_ck505)
8395 final |= DREF_NONSPREAD_CK505_ENABLE;
8396 else
8397 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8398
8399 final &= ~DREF_SSC_SOURCE_MASK;
8400 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8401 final &= ~DREF_SSC1_ENABLE;
8402
8403 if (has_panel) {
8404 final |= DREF_SSC_SOURCE_ENABLE;
8405
8406 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8407 final |= DREF_SSC1_ENABLE;
8408
8409 if (has_cpu_edp) {
8410 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8411 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8412 else
8413 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8414 } else
8415 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8416 } else {
8417 final |= DREF_SSC_SOURCE_DISABLE;
8418 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8419 }
8420
8421 if (final == val)
8422 return;
8423
8424 /* Always enable nonspread source */
8425 val &= ~DREF_NONSPREAD_SOURCE_MASK;
8426
8427 if (has_ck505)
8428 val |= DREF_NONSPREAD_CK505_ENABLE;
8429 else
8430 val |= DREF_NONSPREAD_SOURCE_ENABLE;
8431
8432 if (has_panel) {
8433 val &= ~DREF_SSC_SOURCE_MASK;
8434 val |= DREF_SSC_SOURCE_ENABLE;
8435
8436 /* SSC must be turned on before enabling the CPU output */
8437 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8438 DRM_DEBUG_KMS("Using SSC on panel\n");
8439 val |= DREF_SSC1_ENABLE;
8440 } else
8441 val &= ~DREF_SSC1_ENABLE;
8442
8443 /* Get SSC going before enabling the outputs */
8444 I915_WRITE(PCH_DREF_CONTROL, val);
8445 POSTING_READ(PCH_DREF_CONTROL);
8446 udelay(200);
8447
8448 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8449
8450 /* Enable CPU source on CPU attached eDP */
8451 if (has_cpu_edp) {
8452 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
8453 DRM_DEBUG_KMS("Using SSC on eDP\n");
8454 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8455 } else
8456 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8457 } else
8458 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8459
8460 I915_WRITE(PCH_DREF_CONTROL, val);
8461 POSTING_READ(PCH_DREF_CONTROL);
8462 udelay(200);
8463 } else {
8464 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8465
8466 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8467
8468 /* Turn off CPU output */
8469 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8470
8471 I915_WRITE(PCH_DREF_CONTROL, val);
8472 POSTING_READ(PCH_DREF_CONTROL);
8473 udelay(200);
8474
8475 /* Turn off the SSC source */
8476 val &= ~DREF_SSC_SOURCE_MASK;
8477 val |= DREF_SSC_SOURCE_DISABLE;
8478
8479 /* Turn off SSC1 */
8480 val &= ~DREF_SSC1_ENABLE;
8481
8482 I915_WRITE(PCH_DREF_CONTROL, val);
8483 POSTING_READ(PCH_DREF_CONTROL);
8484 udelay(200);
8485 }
8486
8487 BUG_ON(val != final);
8488 }
8489
8490 static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
8491 {
8492 uint32_t tmp;
8493
8494 tmp = I915_READ(SOUTH_CHICKEN2);
8495 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8496 I915_WRITE(SOUTH_CHICKEN2, tmp);
8497
8498 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8499 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8500 DRM_ERROR("FDI mPHY reset assert timeout\n");
8501
8502 tmp = I915_READ(SOUTH_CHICKEN2);
8503 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8504 I915_WRITE(SOUTH_CHICKEN2, tmp);
8505
8506 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8507 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8508 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
8509 }
8510
8511 /* WaMPhyProgramming:hsw */
8512 static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8513 {
8514 uint32_t tmp;
8515
8516 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8517 tmp &= ~(0xFF << 24);
8518 tmp |= (0x12 << 24);
8519 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8520
8521 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8522 tmp |= (1 << 11);
8523 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8524
8525 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8526 tmp |= (1 << 11);
8527 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8528
8529 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8530 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8531 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8532
8533 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8534 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8535 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8536
8537 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8538 tmp &= ~(7 << 13);
8539 tmp |= (5 << 13);
8540 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
8541
8542 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8543 tmp &= ~(7 << 13);
8544 tmp |= (5 << 13);
8545 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
8546
8547 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8548 tmp &= ~0xFF;
8549 tmp |= 0x1C;
8550 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8551
8552 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8553 tmp &= ~0xFF;
8554 tmp |= 0x1C;
8555 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8556
8557 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8558 tmp &= ~(0xFF << 16);
8559 tmp |= (0x1C << 16);
8560 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8561
8562 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8563 tmp &= ~(0xFF << 16);
8564 tmp |= (0x1C << 16);
8565 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8566
8567 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8568 tmp |= (1 << 27);
8569 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
8570
8571 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8572 tmp |= (1 << 27);
8573 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
8574
8575 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8576 tmp &= ~(0xF << 28);
8577 tmp |= (4 << 28);
8578 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
8579
8580 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8581 tmp &= ~(0xF << 28);
8582 tmp |= (4 << 28);
8583 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
8584 }
8585
8586 /* Implements 3 different sequences from BSpec chapter "Display iCLK
8587 * Programming" based on the parameters passed:
8588 * - Sequence to enable CLKOUT_DP
8589 * - Sequence to enable CLKOUT_DP without spread
8590 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8591 */
8592 static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8593 bool with_fdi)
8594 {
8595 struct drm_i915_private *dev_priv = dev->dev_private;
8596 uint32_t reg, tmp;
8597
8598 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8599 with_spread = true;
8600 if (WARN(HAS_PCH_LPT_LP(dev) && with_fdi, "LP PCH doesn't have FDI\n"))
8601 with_fdi = false;
8602
8603 mutex_lock(&dev_priv->sb_lock);
8604
8605 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8606 tmp &= ~SBI_SSCCTL_DISABLE;
8607 tmp |= SBI_SSCCTL_PATHALT;
8608 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8609
8610 udelay(24);
8611
8612 if (with_spread) {
8613 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8614 tmp &= ~SBI_SSCCTL_PATHALT;
8615 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8616
8617 if (with_fdi) {
8618 lpt_reset_fdi_mphy(dev_priv);
8619 lpt_program_fdi_mphy(dev_priv);
8620 }
8621 }
8622
8623 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8624 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8625 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8626 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8627
8628 mutex_unlock(&dev_priv->sb_lock);
8629 }
8630
8631 /* Sequence to disable CLKOUT_DP */
8632 static void lpt_disable_clkout_dp(struct drm_device *dev)
8633 {
8634 struct drm_i915_private *dev_priv = dev->dev_private;
8635 uint32_t reg, tmp;
8636
8637 mutex_lock(&dev_priv->sb_lock);
8638
8639 reg = HAS_PCH_LPT_LP(dev) ? SBI_GEN0 : SBI_DBUFF0;
8640 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8641 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8642 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8643
8644 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8645 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8646 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8647 tmp |= SBI_SSCCTL_PATHALT;
8648 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8649 udelay(32);
8650 }
8651 tmp |= SBI_SSCCTL_DISABLE;
8652 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8653 }
8654
8655 mutex_unlock(&dev_priv->sb_lock);
8656 }
8657
8658 #define BEND_IDX(steps) ((50 + (steps)) / 5)
8659
8660 static const uint16_t sscdivintphase[] = {
8661 [BEND_IDX( 50)] = 0x3B23,
8662 [BEND_IDX( 45)] = 0x3B23,
8663 [BEND_IDX( 40)] = 0x3C23,
8664 [BEND_IDX( 35)] = 0x3C23,
8665 [BEND_IDX( 30)] = 0x3D23,
8666 [BEND_IDX( 25)] = 0x3D23,
8667 [BEND_IDX( 20)] = 0x3E23,
8668 [BEND_IDX( 15)] = 0x3E23,
8669 [BEND_IDX( 10)] = 0x3F23,
8670 [BEND_IDX( 5)] = 0x3F23,
8671 [BEND_IDX( 0)] = 0x0025,
8672 [BEND_IDX( -5)] = 0x0025,
8673 [BEND_IDX(-10)] = 0x0125,
8674 [BEND_IDX(-15)] = 0x0125,
8675 [BEND_IDX(-20)] = 0x0225,
8676 [BEND_IDX(-25)] = 0x0225,
8677 [BEND_IDX(-30)] = 0x0325,
8678 [BEND_IDX(-35)] = 0x0325,
8679 [BEND_IDX(-40)] = 0x0425,
8680 [BEND_IDX(-45)] = 0x0425,
8681 [BEND_IDX(-50)] = 0x0525,
8682 };
8683
8684 /*
8685 * Bend CLKOUT_DP
8686 * steps -50 to 50 inclusive, in steps of 5
8687 * < 0 slow down the clock, > 0 speed up the clock, 0 == no bend (135MHz)
8688 * change in clock period = -(steps / 10) * 5.787 ps
8689 */
8690 static void lpt_bend_clkout_dp(struct drm_i915_private *dev_priv, int steps)
8691 {
8692 uint32_t tmp;
8693 int idx = BEND_IDX(steps);
8694
8695 if (WARN_ON(steps % 5 != 0))
8696 return;
8697
8698 if (WARN_ON(idx >= ARRAY_SIZE(sscdivintphase)))
8699 return;
8700
8701 mutex_lock(&dev_priv->sb_lock);
8702
8703 if (steps % 10 != 0)
8704 tmp = 0xAAAAAAAB;
8705 else
8706 tmp = 0x00000000;
8707 intel_sbi_write(dev_priv, SBI_SSCDITHPHASE, tmp, SBI_ICLK);
8708
8709 tmp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE, SBI_ICLK);
8710 tmp &= 0xffff0000;
8711 tmp |= sscdivintphase[idx];
8712 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE, tmp, SBI_ICLK);
8713
8714 mutex_unlock(&dev_priv->sb_lock);
8715 }
8716
8717 #undef BEND_IDX
8718
8719 static void lpt_init_pch_refclk(struct drm_device *dev)
8720 {
8721 struct intel_encoder *encoder;
8722 bool has_vga = false;
8723
8724 for_each_intel_encoder(dev, encoder) {
8725 switch (encoder->type) {
8726 case INTEL_OUTPUT_ANALOG:
8727 has_vga = true;
8728 break;
8729 default:
8730 break;
8731 }
8732 }
8733
8734 if (has_vga) {
8735 lpt_bend_clkout_dp(to_i915(dev), 0);
8736 lpt_enable_clkout_dp(dev, true, true);
8737 } else {
8738 lpt_disable_clkout_dp(dev);
8739 }
8740 }
8741
8742 /*
8743 * Initialize reference clocks when the driver loads
8744 */
8745 void intel_init_pch_refclk(struct drm_device *dev)
8746 {
8747 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8748 ironlake_init_pch_refclk(dev);
8749 else if (HAS_PCH_LPT(dev))
8750 lpt_init_pch_refclk(dev);
8751 }
8752
8753 static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
8754 {
8755 struct drm_device *dev = crtc_state->base.crtc->dev;
8756 struct drm_i915_private *dev_priv = dev->dev_private;
8757 struct drm_atomic_state *state = crtc_state->base.state;
8758 struct drm_connector *connector;
8759 struct drm_connector_state *connector_state;
8760 struct intel_encoder *encoder;
8761 int num_connectors = 0, i;
8762 bool is_lvds = false;
8763
8764 for_each_connector_in_state(state, connector, connector_state, i) {
8765 if (connector_state->crtc != crtc_state->base.crtc)
8766 continue;
8767
8768 encoder = to_intel_encoder(connector_state->best_encoder);
8769
8770 switch (encoder->type) {
8771 case INTEL_OUTPUT_LVDS:
8772 is_lvds = true;
8773 break;
8774 default:
8775 break;
8776 }
8777 num_connectors++;
8778 }
8779
8780 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
8781 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
8782 dev_priv->vbt.lvds_ssc_freq);
8783 return dev_priv->vbt.lvds_ssc_freq;
8784 }
8785
8786 return 120000;
8787 }
8788
8789 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
8790 {
8791 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
8792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8793 int pipe = intel_crtc->pipe;
8794 uint32_t val;
8795
8796 val = 0;
8797
8798 switch (intel_crtc->config->pipe_bpp) {
8799 case 18:
8800 val |= PIPECONF_6BPC;
8801 break;
8802 case 24:
8803 val |= PIPECONF_8BPC;
8804 break;
8805 case 30:
8806 val |= PIPECONF_10BPC;
8807 break;
8808 case 36:
8809 val |= PIPECONF_12BPC;
8810 break;
8811 default:
8812 /* Case prevented by intel_choose_pipe_bpp_dither. */
8813 BUG();
8814 }
8815
8816 if (intel_crtc->config->dither)
8817 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8818
8819 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8820 val |= PIPECONF_INTERLACED_ILK;
8821 else
8822 val |= PIPECONF_PROGRESSIVE;
8823
8824 if (intel_crtc->config->limited_color_range)
8825 val |= PIPECONF_COLOR_RANGE_SELECT;
8826
8827 I915_WRITE(PIPECONF(pipe), val);
8828 POSTING_READ(PIPECONF(pipe));
8829 }
8830
8831 /*
8832 * Set up the pipe CSC unit.
8833 *
8834 * Currently only full range RGB to limited range RGB conversion
8835 * is supported, but eventually this should handle various
8836 * RGB<->YCbCr scenarios as well.
8837 */
8838 static void intel_set_pipe_csc(struct drm_crtc *crtc)
8839 {
8840 struct drm_device *dev = crtc->dev;
8841 struct drm_i915_private *dev_priv = dev->dev_private;
8842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8843 int pipe = intel_crtc->pipe;
8844 uint16_t coeff = 0x7800; /* 1.0 */
8845
8846 /*
8847 * TODO: Check what kind of values actually come out of the pipe
8848 * with these coeff/postoff values and adjust to get the best
8849 * accuracy. Perhaps we even need to take the bpc value into
8850 * consideration.
8851 */
8852
8853 if (intel_crtc->config->limited_color_range)
8854 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8855
8856 /*
8857 * GY/GU and RY/RU should be the other way around according
8858 * to BSpec, but reality doesn't agree. Just set them up in
8859 * a way that results in the correct picture.
8860 */
8861 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8862 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8863
8864 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8865 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8866
8867 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8868 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8869
8870 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8871 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8872 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8873
8874 if (INTEL_INFO(dev)->gen > 6) {
8875 uint16_t postoff = 0;
8876
8877 if (intel_crtc->config->limited_color_range)
8878 postoff = (16 * (1 << 12) / 255) & 0x1fff;
8879
8880 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8881 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8882 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8883
8884 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8885 } else {
8886 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8887
8888 if (intel_crtc->config->limited_color_range)
8889 mode |= CSC_BLACK_SCREEN_OFFSET;
8890
8891 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8892 }
8893 }
8894
8895 static void haswell_set_pipeconf(struct drm_crtc *crtc)
8896 {
8897 struct drm_device *dev = crtc->dev;
8898 struct drm_i915_private *dev_priv = dev->dev_private;
8899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8900 enum pipe pipe = intel_crtc->pipe;
8901 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8902 uint32_t val;
8903
8904 val = 0;
8905
8906 if (IS_HASWELL(dev) && intel_crtc->config->dither)
8907 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8908
8909 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
8910 val |= PIPECONF_INTERLACED_ILK;
8911 else
8912 val |= PIPECONF_PROGRESSIVE;
8913
8914 I915_WRITE(PIPECONF(cpu_transcoder), val);
8915 POSTING_READ(PIPECONF(cpu_transcoder));
8916
8917 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8918 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
8919
8920 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
8921 val = 0;
8922
8923 switch (intel_crtc->config->pipe_bpp) {
8924 case 18:
8925 val |= PIPEMISC_DITHER_6_BPC;
8926 break;
8927 case 24:
8928 val |= PIPEMISC_DITHER_8_BPC;
8929 break;
8930 case 30:
8931 val |= PIPEMISC_DITHER_10_BPC;
8932 break;
8933 case 36:
8934 val |= PIPEMISC_DITHER_12_BPC;
8935 break;
8936 default:
8937 /* Case prevented by pipe_config_set_bpp. */
8938 BUG();
8939 }
8940
8941 if (intel_crtc->config->dither)
8942 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8943
8944 I915_WRITE(PIPEMISC(pipe), val);
8945 }
8946 }
8947
8948 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
8949 struct intel_crtc_state *crtc_state,
8950 intel_clock_t *clock,
8951 bool *has_reduced_clock,
8952 intel_clock_t *reduced_clock)
8953 {
8954 struct drm_device *dev = crtc->dev;
8955 struct drm_i915_private *dev_priv = dev->dev_private;
8956 int refclk;
8957 const intel_limit_t *limit;
8958 bool ret;
8959
8960 refclk = ironlake_get_refclk(crtc_state);
8961
8962 /*
8963 * Returns a set of divisors for the desired target clock with the given
8964 * refclk, or FALSE. The returned values represent the clock equation:
8965 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8966 */
8967 limit = intel_limit(crtc_state, refclk);
8968 ret = dev_priv->display.find_dpll(limit, crtc_state,
8969 crtc_state->port_clock,
8970 refclk, NULL, clock);
8971 if (!ret)
8972 return false;
8973
8974 return true;
8975 }
8976
8977 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8978 {
8979 /*
8980 * Account for spread spectrum to avoid
8981 * oversubscribing the link. Max center spread
8982 * is 2.5%; use 5% for safety's sake.
8983 */
8984 u32 bps = target_clock * bpp * 21 / 20;
8985 return DIV_ROUND_UP(bps, link_bw * 8);
8986 }
8987
8988 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
8989 {
8990 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
8991 }
8992
8993 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
8994 struct intel_crtc_state *crtc_state,
8995 u32 *fp,
8996 intel_clock_t *reduced_clock, u32 *fp2)
8997 {
8998 struct drm_crtc *crtc = &intel_crtc->base;
8999 struct drm_device *dev = crtc->dev;
9000 struct drm_i915_private *dev_priv = dev->dev_private;
9001 struct drm_atomic_state *state = crtc_state->base.state;
9002 struct drm_connector *connector;
9003 struct drm_connector_state *connector_state;
9004 struct intel_encoder *encoder;
9005 uint32_t dpll;
9006 int factor, num_connectors = 0, i;
9007 bool is_lvds = false, is_sdvo = false;
9008
9009 for_each_connector_in_state(state, connector, connector_state, i) {
9010 if (connector_state->crtc != crtc_state->base.crtc)
9011 continue;
9012
9013 encoder = to_intel_encoder(connector_state->best_encoder);
9014
9015 switch (encoder->type) {
9016 case INTEL_OUTPUT_LVDS:
9017 is_lvds = true;
9018 break;
9019 case INTEL_OUTPUT_SDVO:
9020 case INTEL_OUTPUT_HDMI:
9021 is_sdvo = true;
9022 break;
9023 default:
9024 break;
9025 }
9026
9027 num_connectors++;
9028 }
9029
9030 /* Enable autotuning of the PLL clock (if permissible) */
9031 factor = 21;
9032 if (is_lvds) {
9033 if ((intel_panel_use_ssc(dev_priv) &&
9034 dev_priv->vbt.lvds_ssc_freq == 100000) ||
9035 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
9036 factor = 25;
9037 } else if (crtc_state->sdvo_tv_clock)
9038 factor = 20;
9039
9040 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
9041 *fp |= FP_CB_TUNE;
9042
9043 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
9044 *fp2 |= FP_CB_TUNE;
9045
9046 dpll = 0;
9047
9048 if (is_lvds)
9049 dpll |= DPLLB_MODE_LVDS;
9050 else
9051 dpll |= DPLLB_MODE_DAC_SERIAL;
9052
9053 dpll |= (crtc_state->pixel_multiplier - 1)
9054 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
9055
9056 if (is_sdvo)
9057 dpll |= DPLL_SDVO_HIGH_SPEED;
9058 if (crtc_state->has_dp_encoder)
9059 dpll |= DPLL_SDVO_HIGH_SPEED;
9060
9061 /* compute bitmask from p1 value */
9062 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
9063 /* also FPA1 */
9064 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
9065
9066 switch (crtc_state->dpll.p2) {
9067 case 5:
9068 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
9069 break;
9070 case 7:
9071 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
9072 break;
9073 case 10:
9074 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
9075 break;
9076 case 14:
9077 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
9078 break;
9079 }
9080
9081 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
9082 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
9083 else
9084 dpll |= PLL_REF_INPUT_DREFCLK;
9085
9086 return dpll | DPLL_VCO_ENABLE;
9087 }
9088
9089 static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
9090 struct intel_crtc_state *crtc_state)
9091 {
9092 struct drm_device *dev = crtc->base.dev;
9093 intel_clock_t clock, reduced_clock;
9094 u32 dpll = 0, fp = 0, fp2 = 0;
9095 bool ok, has_reduced_clock = false;
9096 bool is_lvds = false;
9097 struct intel_shared_dpll *pll;
9098
9099 memset(&crtc_state->dpll_hw_state, 0,
9100 sizeof(crtc_state->dpll_hw_state));
9101
9102 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
9103
9104 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
9105 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
9106
9107 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
9108 &has_reduced_clock, &reduced_clock);
9109 if (!ok && !crtc_state->clock_set) {
9110 DRM_ERROR("Couldn't find PLL settings for mode!\n");
9111 return -EINVAL;
9112 }
9113 /* Compat-code for transition, will disappear. */
9114 if (!crtc_state->clock_set) {
9115 crtc_state->dpll.n = clock.n;
9116 crtc_state->dpll.m1 = clock.m1;
9117 crtc_state->dpll.m2 = clock.m2;
9118 crtc_state->dpll.p1 = clock.p1;
9119 crtc_state->dpll.p2 = clock.p2;
9120 }
9121
9122 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
9123 if (crtc_state->has_pch_encoder) {
9124 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
9125 if (has_reduced_clock)
9126 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
9127
9128 dpll = ironlake_compute_dpll(crtc, crtc_state,
9129 &fp, &reduced_clock,
9130 has_reduced_clock ? &fp2 : NULL);
9131
9132 crtc_state->dpll_hw_state.dpll = dpll;
9133 crtc_state->dpll_hw_state.fp0 = fp;
9134 if (has_reduced_clock)
9135 crtc_state->dpll_hw_state.fp1 = fp2;
9136 else
9137 crtc_state->dpll_hw_state.fp1 = fp;
9138
9139 pll = intel_get_shared_dpll(crtc, crtc_state);
9140 if (pll == NULL) {
9141 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
9142 pipe_name(crtc->pipe));
9143 return -EINVAL;
9144 }
9145 }
9146
9147 if (is_lvds && has_reduced_clock)
9148 crtc->lowfreq_avail = true;
9149 else
9150 crtc->lowfreq_avail = false;
9151
9152 return 0;
9153 }
9154
9155 static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
9156 struct intel_link_m_n *m_n)
9157 {
9158 struct drm_device *dev = crtc->base.dev;
9159 struct drm_i915_private *dev_priv = dev->dev_private;
9160 enum pipe pipe = crtc->pipe;
9161
9162 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
9163 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
9164 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
9165 & ~TU_SIZE_MASK;
9166 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
9167 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
9168 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9169 }
9170
9171 static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
9172 enum transcoder transcoder,
9173 struct intel_link_m_n *m_n,
9174 struct intel_link_m_n *m2_n2)
9175 {
9176 struct drm_device *dev = crtc->base.dev;
9177 struct drm_i915_private *dev_priv = dev->dev_private;
9178 enum pipe pipe = crtc->pipe;
9179
9180 if (INTEL_INFO(dev)->gen >= 5) {
9181 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
9182 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
9183 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
9184 & ~TU_SIZE_MASK;
9185 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
9186 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
9187 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9188 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
9189 * gen < 8) and if DRRS is supported (to make sure the
9190 * registers are not unnecessarily read).
9191 */
9192 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
9193 crtc->config->has_drrs) {
9194 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
9195 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
9196 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
9197 & ~TU_SIZE_MASK;
9198 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
9199 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
9200 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9201 }
9202 } else {
9203 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
9204 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
9205 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
9206 & ~TU_SIZE_MASK;
9207 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
9208 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
9209 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
9210 }
9211 }
9212
9213 void intel_dp_get_m_n(struct intel_crtc *crtc,
9214 struct intel_crtc_state *pipe_config)
9215 {
9216 if (pipe_config->has_pch_encoder)
9217 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
9218 else
9219 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9220 &pipe_config->dp_m_n,
9221 &pipe_config->dp_m2_n2);
9222 }
9223
9224 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
9225 struct intel_crtc_state *pipe_config)
9226 {
9227 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
9228 &pipe_config->fdi_m_n, NULL);
9229 }
9230
9231 static void skylake_get_pfit_config(struct intel_crtc *crtc,
9232 struct intel_crtc_state *pipe_config)
9233 {
9234 struct drm_device *dev = crtc->base.dev;
9235 struct drm_i915_private *dev_priv = dev->dev_private;
9236 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
9237 uint32_t ps_ctrl = 0;
9238 int id = -1;
9239 int i;
9240
9241 /* find scaler attached to this pipe */
9242 for (i = 0; i < crtc->num_scalers; i++) {
9243 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
9244 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
9245 id = i;
9246 pipe_config->pch_pfit.enabled = true;
9247 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
9248 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
9249 break;
9250 }
9251 }
9252
9253 scaler_state->scaler_id = id;
9254 if (id >= 0) {
9255 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9256 } else {
9257 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
9258 }
9259 }
9260
9261 static void
9262 skylake_get_initial_plane_config(struct intel_crtc *crtc,
9263 struct intel_initial_plane_config *plane_config)
9264 {
9265 struct drm_device *dev = crtc->base.dev;
9266 struct drm_i915_private *dev_priv = dev->dev_private;
9267 u32 val, base, offset, stride_mult, tiling;
9268 int pipe = crtc->pipe;
9269 int fourcc, pixel_format;
9270 unsigned int aligned_height;
9271 struct drm_framebuffer *fb;
9272 struct intel_framebuffer *intel_fb;
9273
9274 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9275 if (!intel_fb) {
9276 DRM_DEBUG_KMS("failed to alloc fb\n");
9277 return;
9278 }
9279
9280 fb = &intel_fb->base;
9281
9282 val = I915_READ(PLANE_CTL(pipe, 0));
9283 if (!(val & PLANE_CTL_ENABLE))
9284 goto error;
9285
9286 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9287 fourcc = skl_format_to_fourcc(pixel_format,
9288 val & PLANE_CTL_ORDER_RGBX,
9289 val & PLANE_CTL_ALPHA_MASK);
9290 fb->pixel_format = fourcc;
9291 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9292
9293 tiling = val & PLANE_CTL_TILED_MASK;
9294 switch (tiling) {
9295 case PLANE_CTL_TILED_LINEAR:
9296 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9297 break;
9298 case PLANE_CTL_TILED_X:
9299 plane_config->tiling = I915_TILING_X;
9300 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9301 break;
9302 case PLANE_CTL_TILED_Y:
9303 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9304 break;
9305 case PLANE_CTL_TILED_YF:
9306 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9307 break;
9308 default:
9309 MISSING_CASE(tiling);
9310 goto error;
9311 }
9312
9313 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9314 plane_config->base = base;
9315
9316 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9317
9318 val = I915_READ(PLANE_SIZE(pipe, 0));
9319 fb->height = ((val >> 16) & 0xfff) + 1;
9320 fb->width = ((val >> 0) & 0x1fff) + 1;
9321
9322 val = I915_READ(PLANE_STRIDE(pipe, 0));
9323 stride_mult = intel_fb_stride_alignment(dev_priv, fb->modifier[0],
9324 fb->pixel_format);
9325 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9326
9327 aligned_height = intel_fb_align_height(dev, fb->height,
9328 fb->pixel_format,
9329 fb->modifier[0]);
9330
9331 plane_config->size = fb->pitches[0] * aligned_height;
9332
9333 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9334 pipe_name(pipe), fb->width, fb->height,
9335 fb->bits_per_pixel, base, fb->pitches[0],
9336 plane_config->size);
9337
9338 plane_config->fb = intel_fb;
9339 return;
9340
9341 error:
9342 kfree(fb);
9343 }
9344
9345 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
9346 struct intel_crtc_state *pipe_config)
9347 {
9348 struct drm_device *dev = crtc->base.dev;
9349 struct drm_i915_private *dev_priv = dev->dev_private;
9350 uint32_t tmp;
9351
9352 tmp = I915_READ(PF_CTL(crtc->pipe));
9353
9354 if (tmp & PF_ENABLE) {
9355 pipe_config->pch_pfit.enabled = true;
9356 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9357 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
9358
9359 /* We currently do not free assignements of panel fitters on
9360 * ivb/hsw (since we don't use the higher upscaling modes which
9361 * differentiates them) so just WARN about this case for now. */
9362 if (IS_GEN7(dev)) {
9363 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9364 PF_PIPE_SEL_IVB(crtc->pipe));
9365 }
9366 }
9367 }
9368
9369 static void
9370 ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9371 struct intel_initial_plane_config *plane_config)
9372 {
9373 struct drm_device *dev = crtc->base.dev;
9374 struct drm_i915_private *dev_priv = dev->dev_private;
9375 u32 val, base, offset;
9376 int pipe = crtc->pipe;
9377 int fourcc, pixel_format;
9378 unsigned int aligned_height;
9379 struct drm_framebuffer *fb;
9380 struct intel_framebuffer *intel_fb;
9381
9382 val = I915_READ(DSPCNTR(pipe));
9383 if (!(val & DISPLAY_PLANE_ENABLE))
9384 return;
9385
9386 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9387 if (!intel_fb) {
9388 DRM_DEBUG_KMS("failed to alloc fb\n");
9389 return;
9390 }
9391
9392 fb = &intel_fb->base;
9393
9394 if (INTEL_INFO(dev)->gen >= 4) {
9395 if (val & DISPPLANE_TILED) {
9396 plane_config->tiling = I915_TILING_X;
9397 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9398 }
9399 }
9400
9401 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
9402 fourcc = i9xx_format_to_fourcc(pixel_format);
9403 fb->pixel_format = fourcc;
9404 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9405
9406 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
9407 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
9408 offset = I915_READ(DSPOFFSET(pipe));
9409 } else {
9410 if (plane_config->tiling)
9411 offset = I915_READ(DSPTILEOFF(pipe));
9412 else
9413 offset = I915_READ(DSPLINOFF(pipe));
9414 }
9415 plane_config->base = base;
9416
9417 val = I915_READ(PIPESRC(pipe));
9418 fb->width = ((val >> 16) & 0xfff) + 1;
9419 fb->height = ((val >> 0) & 0xfff) + 1;
9420
9421 val = I915_READ(DSPSTRIDE(pipe));
9422 fb->pitches[0] = val & 0xffffffc0;
9423
9424 aligned_height = intel_fb_align_height(dev, fb->height,
9425 fb->pixel_format,
9426 fb->modifier[0]);
9427
9428 plane_config->size = fb->pitches[0] * aligned_height;
9429
9430 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9431 pipe_name(pipe), fb->width, fb->height,
9432 fb->bits_per_pixel, base, fb->pitches[0],
9433 plane_config->size);
9434
9435 plane_config->fb = intel_fb;
9436 }
9437
9438 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
9439 struct intel_crtc_state *pipe_config)
9440 {
9441 struct drm_device *dev = crtc->base.dev;
9442 struct drm_i915_private *dev_priv = dev->dev_private;
9443 uint32_t tmp;
9444
9445 if (!intel_display_power_is_enabled(dev_priv,
9446 POWER_DOMAIN_PIPE(crtc->pipe)))
9447 return false;
9448
9449 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
9450 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9451
9452 tmp = I915_READ(PIPECONF(crtc->pipe));
9453 if (!(tmp & PIPECONF_ENABLE))
9454 return false;
9455
9456 switch (tmp & PIPECONF_BPC_MASK) {
9457 case PIPECONF_6BPC:
9458 pipe_config->pipe_bpp = 18;
9459 break;
9460 case PIPECONF_8BPC:
9461 pipe_config->pipe_bpp = 24;
9462 break;
9463 case PIPECONF_10BPC:
9464 pipe_config->pipe_bpp = 30;
9465 break;
9466 case PIPECONF_12BPC:
9467 pipe_config->pipe_bpp = 36;
9468 break;
9469 default:
9470 break;
9471 }
9472
9473 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9474 pipe_config->limited_color_range = true;
9475
9476 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
9477 struct intel_shared_dpll *pll;
9478
9479 pipe_config->has_pch_encoder = true;
9480
9481 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9482 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9483 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9484
9485 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9486
9487 if (HAS_PCH_IBX(dev_priv->dev)) {
9488 pipe_config->shared_dpll =
9489 (enum intel_dpll_id) crtc->pipe;
9490 } else {
9491 tmp = I915_READ(PCH_DPLL_SEL);
9492 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9493 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9494 else
9495 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9496 }
9497
9498 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9499
9500 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9501 &pipe_config->dpll_hw_state));
9502
9503 tmp = pipe_config->dpll_hw_state.dpll;
9504 pipe_config->pixel_multiplier =
9505 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9506 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
9507
9508 ironlake_pch_clock_get(crtc, pipe_config);
9509 } else {
9510 pipe_config->pixel_multiplier = 1;
9511 }
9512
9513 intel_get_pipe_timings(crtc, pipe_config);
9514
9515 ironlake_get_pfit_config(crtc, pipe_config);
9516
9517 return true;
9518 }
9519
9520 static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9521 {
9522 struct drm_device *dev = dev_priv->dev;
9523 struct intel_crtc *crtc;
9524
9525 for_each_intel_crtc(dev, crtc)
9526 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
9527 pipe_name(crtc->pipe));
9528
9529 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9530 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9531 I915_STATE_WARN(I915_READ(WRPLL_CTL(0)) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9532 I915_STATE_WARN(I915_READ(WRPLL_CTL(1)) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9533 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9534 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
9535 "CPU PWM1 enabled\n");
9536 if (IS_HASWELL(dev))
9537 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
9538 "CPU PWM2 enabled\n");
9539 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
9540 "PCH PWM1 enabled\n");
9541 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
9542 "Utility pin enabled\n");
9543 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
9544
9545 /*
9546 * In theory we can still leave IRQs enabled, as long as only the HPD
9547 * interrupts remain enabled. We used to check for that, but since it's
9548 * gen-specific and since we only disable LCPLL after we fully disable
9549 * the interrupts, the check below should be enough.
9550 */
9551 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
9552 }
9553
9554 static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9555 {
9556 struct drm_device *dev = dev_priv->dev;
9557
9558 if (IS_HASWELL(dev))
9559 return I915_READ(D_COMP_HSW);
9560 else
9561 return I915_READ(D_COMP_BDW);
9562 }
9563
9564 static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9565 {
9566 struct drm_device *dev = dev_priv->dev;
9567
9568 if (IS_HASWELL(dev)) {
9569 mutex_lock(&dev_priv->rps.hw_lock);
9570 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9571 val))
9572 DRM_ERROR("Failed to write to D_COMP\n");
9573 mutex_unlock(&dev_priv->rps.hw_lock);
9574 } else {
9575 I915_WRITE(D_COMP_BDW, val);
9576 POSTING_READ(D_COMP_BDW);
9577 }
9578 }
9579
9580 /*
9581 * This function implements pieces of two sequences from BSpec:
9582 * - Sequence for display software to disable LCPLL
9583 * - Sequence for display software to allow package C8+
9584 * The steps implemented here are just the steps that actually touch the LCPLL
9585 * register. Callers should take care of disabling all the display engine
9586 * functions, doing the mode unset, fixing interrupts, etc.
9587 */
9588 static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9589 bool switch_to_fclk, bool allow_power_down)
9590 {
9591 uint32_t val;
9592
9593 assert_can_disable_lcpll(dev_priv);
9594
9595 val = I915_READ(LCPLL_CTL);
9596
9597 if (switch_to_fclk) {
9598 val |= LCPLL_CD_SOURCE_FCLK;
9599 I915_WRITE(LCPLL_CTL, val);
9600
9601 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9602 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9603 DRM_ERROR("Switching to FCLK failed\n");
9604
9605 val = I915_READ(LCPLL_CTL);
9606 }
9607
9608 val |= LCPLL_PLL_DISABLE;
9609 I915_WRITE(LCPLL_CTL, val);
9610 POSTING_READ(LCPLL_CTL);
9611
9612 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9613 DRM_ERROR("LCPLL still locked\n");
9614
9615 val = hsw_read_dcomp(dev_priv);
9616 val |= D_COMP_COMP_DISABLE;
9617 hsw_write_dcomp(dev_priv, val);
9618 ndelay(100);
9619
9620 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9621 1))
9622 DRM_ERROR("D_COMP RCOMP still in progress\n");
9623
9624 if (allow_power_down) {
9625 val = I915_READ(LCPLL_CTL);
9626 val |= LCPLL_POWER_DOWN_ALLOW;
9627 I915_WRITE(LCPLL_CTL, val);
9628 POSTING_READ(LCPLL_CTL);
9629 }
9630 }
9631
9632 /*
9633 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9634 * source.
9635 */
9636 static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
9637 {
9638 uint32_t val;
9639
9640 val = I915_READ(LCPLL_CTL);
9641
9642 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9643 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9644 return;
9645
9646 /*
9647 * Make sure we're not on PC8 state before disabling PC8, otherwise
9648 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
9649 */
9650 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
9651
9652 if (val & LCPLL_POWER_DOWN_ALLOW) {
9653 val &= ~LCPLL_POWER_DOWN_ALLOW;
9654 I915_WRITE(LCPLL_CTL, val);
9655 POSTING_READ(LCPLL_CTL);
9656 }
9657
9658 val = hsw_read_dcomp(dev_priv);
9659 val |= D_COMP_COMP_FORCE;
9660 val &= ~D_COMP_COMP_DISABLE;
9661 hsw_write_dcomp(dev_priv, val);
9662
9663 val = I915_READ(LCPLL_CTL);
9664 val &= ~LCPLL_PLL_DISABLE;
9665 I915_WRITE(LCPLL_CTL, val);
9666
9667 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9668 DRM_ERROR("LCPLL not locked yet\n");
9669
9670 if (val & LCPLL_CD_SOURCE_FCLK) {
9671 val = I915_READ(LCPLL_CTL);
9672 val &= ~LCPLL_CD_SOURCE_FCLK;
9673 I915_WRITE(LCPLL_CTL, val);
9674
9675 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9676 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9677 DRM_ERROR("Switching back to LCPLL failed\n");
9678 }
9679
9680 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
9681 intel_update_cdclk(dev_priv->dev);
9682 }
9683
9684 /*
9685 * Package states C8 and deeper are really deep PC states that can only be
9686 * reached when all the devices on the system allow it, so even if the graphics
9687 * device allows PC8+, it doesn't mean the system will actually get to these
9688 * states. Our driver only allows PC8+ when going into runtime PM.
9689 *
9690 * The requirements for PC8+ are that all the outputs are disabled, the power
9691 * well is disabled and most interrupts are disabled, and these are also
9692 * requirements for runtime PM. When these conditions are met, we manually do
9693 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9694 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9695 * hang the machine.
9696 *
9697 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9698 * the state of some registers, so when we come back from PC8+ we need to
9699 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9700 * need to take care of the registers kept by RC6. Notice that this happens even
9701 * if we don't put the device in PCI D3 state (which is what currently happens
9702 * because of the runtime PM support).
9703 *
9704 * For more, read "Display Sequences for Package C8" on the hardware
9705 * documentation.
9706 */
9707 void hsw_enable_pc8(struct drm_i915_private *dev_priv)
9708 {
9709 struct drm_device *dev = dev_priv->dev;
9710 uint32_t val;
9711
9712 DRM_DEBUG_KMS("Enabling package C8+\n");
9713
9714 if (HAS_PCH_LPT_LP(dev)) {
9715 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9716 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9717 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9718 }
9719
9720 lpt_disable_clkout_dp(dev);
9721 hsw_disable_lcpll(dev_priv, true, true);
9722 }
9723
9724 void hsw_disable_pc8(struct drm_i915_private *dev_priv)
9725 {
9726 struct drm_device *dev = dev_priv->dev;
9727 uint32_t val;
9728
9729 DRM_DEBUG_KMS("Disabling package C8+\n");
9730
9731 hsw_restore_lcpll(dev_priv);
9732 lpt_init_pch_refclk(dev);
9733
9734 if (HAS_PCH_LPT_LP(dev)) {
9735 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9736 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9737 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9738 }
9739 }
9740
9741 static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9742 {
9743 struct drm_device *dev = old_state->dev;
9744 struct intel_atomic_state *old_intel_state =
9745 to_intel_atomic_state(old_state);
9746 unsigned int req_cdclk = old_intel_state->dev_cdclk;
9747
9748 broxton_set_cdclk(dev, req_cdclk);
9749 }
9750
9751 /* compute the max rate for new configuration */
9752 static int ilk_max_pixel_rate(struct drm_atomic_state *state)
9753 {
9754 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9755 struct drm_i915_private *dev_priv = state->dev->dev_private;
9756 struct drm_crtc *crtc;
9757 struct drm_crtc_state *cstate;
9758 struct intel_crtc_state *crtc_state;
9759 unsigned max_pixel_rate = 0, i;
9760 enum pipe pipe;
9761
9762 memcpy(intel_state->min_pixclk, dev_priv->min_pixclk,
9763 sizeof(intel_state->min_pixclk));
9764
9765 for_each_crtc_in_state(state, crtc, cstate, i) {
9766 int pixel_rate;
9767
9768 crtc_state = to_intel_crtc_state(cstate);
9769 if (!crtc_state->base.enable) {
9770 intel_state->min_pixclk[i] = 0;
9771 continue;
9772 }
9773
9774 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
9775
9776 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
9777 if (IS_BROADWELL(dev_priv) && crtc_state->ips_enabled)
9778 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9779
9780 intel_state->min_pixclk[i] = pixel_rate;
9781 }
9782
9783 if (!intel_state->active_crtcs)
9784 return 0;
9785
9786 for_each_pipe(dev_priv, pipe)
9787 max_pixel_rate = max(intel_state->min_pixclk[pipe], max_pixel_rate);
9788
9789 return max_pixel_rate;
9790 }
9791
9792 static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9793 {
9794 struct drm_i915_private *dev_priv = dev->dev_private;
9795 uint32_t val, data;
9796 int ret;
9797
9798 if (WARN((I915_READ(LCPLL_CTL) &
9799 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9800 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9801 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9802 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9803 "trying to change cdclk frequency with cdclk not enabled\n"))
9804 return;
9805
9806 mutex_lock(&dev_priv->rps.hw_lock);
9807 ret = sandybridge_pcode_write(dev_priv,
9808 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9809 mutex_unlock(&dev_priv->rps.hw_lock);
9810 if (ret) {
9811 DRM_ERROR("failed to inform pcode about cdclk change\n");
9812 return;
9813 }
9814
9815 val = I915_READ(LCPLL_CTL);
9816 val |= LCPLL_CD_SOURCE_FCLK;
9817 I915_WRITE(LCPLL_CTL, val);
9818
9819 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9820 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9821 DRM_ERROR("Switching to FCLK failed\n");
9822
9823 val = I915_READ(LCPLL_CTL);
9824 val &= ~LCPLL_CLK_FREQ_MASK;
9825
9826 switch (cdclk) {
9827 case 450000:
9828 val |= LCPLL_CLK_FREQ_450;
9829 data = 0;
9830 break;
9831 case 540000:
9832 val |= LCPLL_CLK_FREQ_54O_BDW;
9833 data = 1;
9834 break;
9835 case 337500:
9836 val |= LCPLL_CLK_FREQ_337_5_BDW;
9837 data = 2;
9838 break;
9839 case 675000:
9840 val |= LCPLL_CLK_FREQ_675_BDW;
9841 data = 3;
9842 break;
9843 default:
9844 WARN(1, "invalid cdclk frequency\n");
9845 return;
9846 }
9847
9848 I915_WRITE(LCPLL_CTL, val);
9849
9850 val = I915_READ(LCPLL_CTL);
9851 val &= ~LCPLL_CD_SOURCE_FCLK;
9852 I915_WRITE(LCPLL_CTL, val);
9853
9854 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9855 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9856 DRM_ERROR("Switching back to LCPLL failed\n");
9857
9858 mutex_lock(&dev_priv->rps.hw_lock);
9859 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9860 mutex_unlock(&dev_priv->rps.hw_lock);
9861
9862 intel_update_cdclk(dev);
9863
9864 WARN(cdclk != dev_priv->cdclk_freq,
9865 "cdclk requested %d kHz but got %d kHz\n",
9866 cdclk, dev_priv->cdclk_freq);
9867 }
9868
9869 static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
9870 {
9871 struct drm_i915_private *dev_priv = to_i915(state->dev);
9872 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
9873 int max_pixclk = ilk_max_pixel_rate(state);
9874 int cdclk;
9875
9876 /*
9877 * FIXME should also account for plane ratio
9878 * once 64bpp pixel formats are supported.
9879 */
9880 if (max_pixclk > 540000)
9881 cdclk = 675000;
9882 else if (max_pixclk > 450000)
9883 cdclk = 540000;
9884 else if (max_pixclk > 337500)
9885 cdclk = 450000;
9886 else
9887 cdclk = 337500;
9888
9889 if (cdclk > dev_priv->max_cdclk_freq) {
9890 DRM_DEBUG_KMS("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9891 cdclk, dev_priv->max_cdclk_freq);
9892 return -EINVAL;
9893 }
9894
9895 intel_state->cdclk = intel_state->dev_cdclk = cdclk;
9896 if (!intel_state->active_crtcs)
9897 intel_state->dev_cdclk = 337500;
9898
9899 return 0;
9900 }
9901
9902 static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
9903 {
9904 struct drm_device *dev = old_state->dev;
9905 struct intel_atomic_state *old_intel_state =
9906 to_intel_atomic_state(old_state);
9907 unsigned req_cdclk = old_intel_state->dev_cdclk;
9908
9909 broadwell_set_cdclk(dev, req_cdclk);
9910 }
9911
9912 static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9913 struct intel_crtc_state *crtc_state)
9914 {
9915 if (!intel_ddi_pll_select(crtc, crtc_state))
9916 return -EINVAL;
9917
9918 crtc->lowfreq_avail = false;
9919
9920 return 0;
9921 }
9922
9923 static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9924 enum port port,
9925 struct intel_crtc_state *pipe_config)
9926 {
9927 switch (port) {
9928 case PORT_A:
9929 pipe_config->ddi_pll_sel = SKL_DPLL0;
9930 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9931 break;
9932 case PORT_B:
9933 pipe_config->ddi_pll_sel = SKL_DPLL1;
9934 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9935 break;
9936 case PORT_C:
9937 pipe_config->ddi_pll_sel = SKL_DPLL2;
9938 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9939 break;
9940 default:
9941 DRM_ERROR("Incorrect port type\n");
9942 }
9943 }
9944
9945 static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9946 enum port port,
9947 struct intel_crtc_state *pipe_config)
9948 {
9949 u32 temp, dpll_ctl1;
9950
9951 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9952 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9953
9954 switch (pipe_config->ddi_pll_sel) {
9955 case SKL_DPLL0:
9956 /*
9957 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9958 * of the shared DPLL framework and thus needs to be read out
9959 * separately
9960 */
9961 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9962 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9963 break;
9964 case SKL_DPLL1:
9965 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9966 break;
9967 case SKL_DPLL2:
9968 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9969 break;
9970 case SKL_DPLL3:
9971 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9972 break;
9973 }
9974 }
9975
9976 static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9977 enum port port,
9978 struct intel_crtc_state *pipe_config)
9979 {
9980 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9981
9982 switch (pipe_config->ddi_pll_sel) {
9983 case PORT_CLK_SEL_WRPLL1:
9984 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9985 break;
9986 case PORT_CLK_SEL_WRPLL2:
9987 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9988 break;
9989 case PORT_CLK_SEL_SPLL:
9990 pipe_config->shared_dpll = DPLL_ID_SPLL;
9991 break;
9992 }
9993 }
9994
9995 static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
9996 struct intel_crtc_state *pipe_config)
9997 {
9998 struct drm_device *dev = crtc->base.dev;
9999 struct drm_i915_private *dev_priv = dev->dev_private;
10000 struct intel_shared_dpll *pll;
10001 enum port port;
10002 uint32_t tmp;
10003
10004 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
10005
10006 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
10007
10008 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
10009 skylake_get_ddi_pll(dev_priv, port, pipe_config);
10010 else if (IS_BROXTON(dev))
10011 bxt_get_ddi_pll(dev_priv, port, pipe_config);
10012 else
10013 haswell_get_ddi_pll(dev_priv, port, pipe_config);
10014
10015 if (pipe_config->shared_dpll >= 0) {
10016 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
10017
10018 WARN_ON(!pll->get_hw_state(dev_priv, pll,
10019 &pipe_config->dpll_hw_state));
10020 }
10021
10022 /*
10023 * Haswell has only FDI/PCH transcoder A. It is which is connected to
10024 * DDI E. So just check whether this pipe is wired to DDI E and whether
10025 * the PCH transcoder is on.
10026 */
10027 if (INTEL_INFO(dev)->gen < 9 &&
10028 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
10029 pipe_config->has_pch_encoder = true;
10030
10031 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
10032 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
10033 FDI_DP_PORT_WIDTH_SHIFT) + 1;
10034
10035 ironlake_get_fdi_m_n_config(crtc, pipe_config);
10036 }
10037 }
10038
10039 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
10040 struct intel_crtc_state *pipe_config)
10041 {
10042 struct drm_device *dev = crtc->base.dev;
10043 struct drm_i915_private *dev_priv = dev->dev_private;
10044 enum intel_display_power_domain pfit_domain;
10045 uint32_t tmp;
10046
10047 if (!intel_display_power_is_enabled(dev_priv,
10048 POWER_DOMAIN_PIPE(crtc->pipe)))
10049 return false;
10050
10051 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
10052 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
10053
10054 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
10055 if (tmp & TRANS_DDI_FUNC_ENABLE) {
10056 enum pipe trans_edp_pipe;
10057 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
10058 default:
10059 WARN(1, "unknown pipe linked to edp transcoder\n");
10060 case TRANS_DDI_EDP_INPUT_A_ONOFF:
10061 case TRANS_DDI_EDP_INPUT_A_ON:
10062 trans_edp_pipe = PIPE_A;
10063 break;
10064 case TRANS_DDI_EDP_INPUT_B_ONOFF:
10065 trans_edp_pipe = PIPE_B;
10066 break;
10067 case TRANS_DDI_EDP_INPUT_C_ONOFF:
10068 trans_edp_pipe = PIPE_C;
10069 break;
10070 }
10071
10072 if (trans_edp_pipe == crtc->pipe)
10073 pipe_config->cpu_transcoder = TRANSCODER_EDP;
10074 }
10075
10076 if (!intel_display_power_is_enabled(dev_priv,
10077 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
10078 return false;
10079
10080 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
10081 if (!(tmp & PIPECONF_ENABLE))
10082 return false;
10083
10084 haswell_get_ddi_port_state(crtc, pipe_config);
10085
10086 intel_get_pipe_timings(crtc, pipe_config);
10087
10088 if (INTEL_INFO(dev)->gen >= 9) {
10089 skl_init_scalers(dev, crtc, pipe_config);
10090 }
10091
10092 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
10093
10094 if (INTEL_INFO(dev)->gen >= 9) {
10095 pipe_config->scaler_state.scaler_id = -1;
10096 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
10097 }
10098
10099 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
10100 if (INTEL_INFO(dev)->gen >= 9)
10101 skylake_get_pfit_config(crtc, pipe_config);
10102 else
10103 ironlake_get_pfit_config(crtc, pipe_config);
10104 }
10105
10106 if (IS_HASWELL(dev))
10107 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
10108 (I915_READ(IPS_CTL) & IPS_ENABLE);
10109
10110 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
10111 pipe_config->pixel_multiplier =
10112 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
10113 } else {
10114 pipe_config->pixel_multiplier = 1;
10115 }
10116
10117 return true;
10118 }
10119
10120 static void i845_update_cursor(struct drm_crtc *crtc, u32 base,
10121 const struct intel_plane_state *plane_state)
10122 {
10123 struct drm_device *dev = crtc->dev;
10124 struct drm_i915_private *dev_priv = dev->dev_private;
10125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10126 uint32_t cntl = 0, size = 0;
10127
10128 if (plane_state && plane_state->visible) {
10129 unsigned int width = plane_state->base.crtc_w;
10130 unsigned int height = plane_state->base.crtc_h;
10131 unsigned int stride = roundup_pow_of_two(width) * 4;
10132
10133 switch (stride) {
10134 default:
10135 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
10136 width, stride);
10137 stride = 256;
10138 /* fallthrough */
10139 case 256:
10140 case 512:
10141 case 1024:
10142 case 2048:
10143 break;
10144 }
10145
10146 cntl |= CURSOR_ENABLE |
10147 CURSOR_GAMMA_ENABLE |
10148 CURSOR_FORMAT_ARGB |
10149 CURSOR_STRIDE(stride);
10150
10151 size = (height << 12) | width;
10152 }
10153
10154 if (intel_crtc->cursor_cntl != 0 &&
10155 (intel_crtc->cursor_base != base ||
10156 intel_crtc->cursor_size != size ||
10157 intel_crtc->cursor_cntl != cntl)) {
10158 /* On these chipsets we can only modify the base/size/stride
10159 * whilst the cursor is disabled.
10160 */
10161 I915_WRITE(CURCNTR(PIPE_A), 0);
10162 POSTING_READ(CURCNTR(PIPE_A));
10163 intel_crtc->cursor_cntl = 0;
10164 }
10165
10166 if (intel_crtc->cursor_base != base) {
10167 I915_WRITE(CURBASE(PIPE_A), base);
10168 intel_crtc->cursor_base = base;
10169 }
10170
10171 if (intel_crtc->cursor_size != size) {
10172 I915_WRITE(CURSIZE, size);
10173 intel_crtc->cursor_size = size;
10174 }
10175
10176 if (intel_crtc->cursor_cntl != cntl) {
10177 I915_WRITE(CURCNTR(PIPE_A), cntl);
10178 POSTING_READ(CURCNTR(PIPE_A));
10179 intel_crtc->cursor_cntl = cntl;
10180 }
10181 }
10182
10183 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base,
10184 const struct intel_plane_state *plane_state)
10185 {
10186 struct drm_device *dev = crtc->dev;
10187 struct drm_i915_private *dev_priv = dev->dev_private;
10188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10189 int pipe = intel_crtc->pipe;
10190 uint32_t cntl = 0;
10191
10192 if (plane_state && plane_state->visible) {
10193 cntl = MCURSOR_GAMMA_ENABLE;
10194 switch (plane_state->base.crtc_w) {
10195 case 64:
10196 cntl |= CURSOR_MODE_64_ARGB_AX;
10197 break;
10198 case 128:
10199 cntl |= CURSOR_MODE_128_ARGB_AX;
10200 break;
10201 case 256:
10202 cntl |= CURSOR_MODE_256_ARGB_AX;
10203 break;
10204 default:
10205 MISSING_CASE(plane_state->base.crtc_w);
10206 return;
10207 }
10208 cntl |= pipe << 28; /* Connect to correct pipe */
10209
10210 if (HAS_DDI(dev))
10211 cntl |= CURSOR_PIPE_CSC_ENABLE;
10212
10213 if (plane_state->base.rotation == BIT(DRM_ROTATE_180))
10214 cntl |= CURSOR_ROTATE_180;
10215 }
10216
10217 if (intel_crtc->cursor_cntl != cntl) {
10218 I915_WRITE(CURCNTR(pipe), cntl);
10219 POSTING_READ(CURCNTR(pipe));
10220 intel_crtc->cursor_cntl = cntl;
10221 }
10222
10223 /* and commit changes on next vblank */
10224 I915_WRITE(CURBASE(pipe), base);
10225 POSTING_READ(CURBASE(pipe));
10226
10227 intel_crtc->cursor_base = base;
10228 }
10229
10230 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
10231 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
10232 const struct intel_plane_state *plane_state)
10233 {
10234 struct drm_device *dev = crtc->dev;
10235 struct drm_i915_private *dev_priv = dev->dev_private;
10236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10237 int pipe = intel_crtc->pipe;
10238 u32 base = intel_crtc->cursor_addr;
10239 u32 pos = 0;
10240
10241 if (plane_state) {
10242 int x = plane_state->base.crtc_x;
10243 int y = plane_state->base.crtc_y;
10244
10245 if (x < 0) {
10246 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
10247 x = -x;
10248 }
10249 pos |= x << CURSOR_X_SHIFT;
10250
10251 if (y < 0) {
10252 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
10253 y = -y;
10254 }
10255 pos |= y << CURSOR_Y_SHIFT;
10256
10257 /* ILK+ do this automagically */
10258 if (HAS_GMCH_DISPLAY(dev) &&
10259 plane_state->base.rotation == BIT(DRM_ROTATE_180)) {
10260 base += (plane_state->base.crtc_h *
10261 plane_state->base.crtc_w - 1) * 4;
10262 }
10263 }
10264
10265 I915_WRITE(CURPOS(pipe), pos);
10266
10267 if (IS_845G(dev) || IS_I865G(dev))
10268 i845_update_cursor(crtc, base, plane_state);
10269 else
10270 i9xx_update_cursor(crtc, base, plane_state);
10271 }
10272
10273 static bool cursor_size_ok(struct drm_device *dev,
10274 uint32_t width, uint32_t height)
10275 {
10276 if (width == 0 || height == 0)
10277 return false;
10278
10279 /*
10280 * 845g/865g are special in that they are only limited by
10281 * the width of their cursors, the height is arbitrary up to
10282 * the precision of the register. Everything else requires
10283 * square cursors, limited to a few power-of-two sizes.
10284 */
10285 if (IS_845G(dev) || IS_I865G(dev)) {
10286 if ((width & 63) != 0)
10287 return false;
10288
10289 if (width > (IS_845G(dev) ? 64 : 512))
10290 return false;
10291
10292 if (height > 1023)
10293 return false;
10294 } else {
10295 switch (width | height) {
10296 case 256:
10297 case 128:
10298 if (IS_GEN2(dev))
10299 return false;
10300 case 64:
10301 break;
10302 default:
10303 return false;
10304 }
10305 }
10306
10307 return true;
10308 }
10309
10310 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
10311 u16 *blue, uint32_t start, uint32_t size)
10312 {
10313 int end = (start + size > 256) ? 256 : start + size, i;
10314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10315
10316 for (i = start; i < end; i++) {
10317 intel_crtc->lut_r[i] = red[i] >> 8;
10318 intel_crtc->lut_g[i] = green[i] >> 8;
10319 intel_crtc->lut_b[i] = blue[i] >> 8;
10320 }
10321
10322 intel_crtc_load_lut(crtc);
10323 }
10324
10325 /* VESA 640x480x72Hz mode to set on the pipe */
10326 static struct drm_display_mode load_detect_mode = {
10327 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10328 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10329 };
10330
10331 struct drm_framebuffer *
10332 __intel_framebuffer_create(struct drm_device *dev,
10333 struct drm_mode_fb_cmd2 *mode_cmd,
10334 struct drm_i915_gem_object *obj)
10335 {
10336 struct intel_framebuffer *intel_fb;
10337 int ret;
10338
10339 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10340 if (!intel_fb)
10341 return ERR_PTR(-ENOMEM);
10342
10343 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
10344 if (ret)
10345 goto err;
10346
10347 return &intel_fb->base;
10348
10349 err:
10350 kfree(intel_fb);
10351 return ERR_PTR(ret);
10352 }
10353
10354 static struct drm_framebuffer *
10355 intel_framebuffer_create(struct drm_device *dev,
10356 struct drm_mode_fb_cmd2 *mode_cmd,
10357 struct drm_i915_gem_object *obj)
10358 {
10359 struct drm_framebuffer *fb;
10360 int ret;
10361
10362 ret = i915_mutex_lock_interruptible(dev);
10363 if (ret)
10364 return ERR_PTR(ret);
10365 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10366 mutex_unlock(&dev->struct_mutex);
10367
10368 return fb;
10369 }
10370
10371 static u32
10372 intel_framebuffer_pitch_for_width(int width, int bpp)
10373 {
10374 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10375 return ALIGN(pitch, 64);
10376 }
10377
10378 static u32
10379 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10380 {
10381 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
10382 return PAGE_ALIGN(pitch * mode->vdisplay);
10383 }
10384
10385 static struct drm_framebuffer *
10386 intel_framebuffer_create_for_mode(struct drm_device *dev,
10387 struct drm_display_mode *mode,
10388 int depth, int bpp)
10389 {
10390 struct drm_framebuffer *fb;
10391 struct drm_i915_gem_object *obj;
10392 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
10393
10394 obj = i915_gem_alloc_object(dev,
10395 intel_framebuffer_size_for_mode(mode, bpp));
10396 if (obj == NULL)
10397 return ERR_PTR(-ENOMEM);
10398
10399 mode_cmd.width = mode->hdisplay;
10400 mode_cmd.height = mode->vdisplay;
10401 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10402 bpp);
10403 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
10404
10405 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
10406 if (IS_ERR(fb))
10407 drm_gem_object_unreference_unlocked(&obj->base);
10408
10409 return fb;
10410 }
10411
10412 static struct drm_framebuffer *
10413 mode_fits_in_fbdev(struct drm_device *dev,
10414 struct drm_display_mode *mode)
10415 {
10416 #ifdef CONFIG_DRM_FBDEV_EMULATION
10417 struct drm_i915_private *dev_priv = dev->dev_private;
10418 struct drm_i915_gem_object *obj;
10419 struct drm_framebuffer *fb;
10420
10421 if (!dev_priv->fbdev)
10422 return NULL;
10423
10424 if (!dev_priv->fbdev->fb)
10425 return NULL;
10426
10427 obj = dev_priv->fbdev->fb->obj;
10428 BUG_ON(!obj);
10429
10430 fb = &dev_priv->fbdev->fb->base;
10431 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10432 fb->bits_per_pixel))
10433 return NULL;
10434
10435 if (obj->base.size < mode->vdisplay * fb->pitches[0])
10436 return NULL;
10437
10438 return fb;
10439 #else
10440 return NULL;
10441 #endif
10442 }
10443
10444 static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10445 struct drm_crtc *crtc,
10446 struct drm_display_mode *mode,
10447 struct drm_framebuffer *fb,
10448 int x, int y)
10449 {
10450 struct drm_plane_state *plane_state;
10451 int hdisplay, vdisplay;
10452 int ret;
10453
10454 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10455 if (IS_ERR(plane_state))
10456 return PTR_ERR(plane_state);
10457
10458 if (mode)
10459 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10460 else
10461 hdisplay = vdisplay = 0;
10462
10463 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10464 if (ret)
10465 return ret;
10466 drm_atomic_set_fb_for_plane(plane_state, fb);
10467 plane_state->crtc_x = 0;
10468 plane_state->crtc_y = 0;
10469 plane_state->crtc_w = hdisplay;
10470 plane_state->crtc_h = vdisplay;
10471 plane_state->src_x = x << 16;
10472 plane_state->src_y = y << 16;
10473 plane_state->src_w = hdisplay << 16;
10474 plane_state->src_h = vdisplay << 16;
10475
10476 return 0;
10477 }
10478
10479 bool intel_get_load_detect_pipe(struct drm_connector *connector,
10480 struct drm_display_mode *mode,
10481 struct intel_load_detect_pipe *old,
10482 struct drm_modeset_acquire_ctx *ctx)
10483 {
10484 struct intel_crtc *intel_crtc;
10485 struct intel_encoder *intel_encoder =
10486 intel_attached_encoder(connector);
10487 struct drm_crtc *possible_crtc;
10488 struct drm_encoder *encoder = &intel_encoder->base;
10489 struct drm_crtc *crtc = NULL;
10490 struct drm_device *dev = encoder->dev;
10491 struct drm_framebuffer *fb;
10492 struct drm_mode_config *config = &dev->mode_config;
10493 struct drm_atomic_state *state = NULL;
10494 struct drm_connector_state *connector_state;
10495 struct intel_crtc_state *crtc_state;
10496 int ret, i = -1;
10497
10498 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10499 connector->base.id, connector->name,
10500 encoder->base.id, encoder->name);
10501
10502 retry:
10503 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10504 if (ret)
10505 goto fail;
10506
10507 /*
10508 * Algorithm gets a little messy:
10509 *
10510 * - if the connector already has an assigned crtc, use it (but make
10511 * sure it's on first)
10512 *
10513 * - try to find the first unused crtc that can drive this connector,
10514 * and use that if we find one
10515 */
10516
10517 /* See if we already have a CRTC for this connector */
10518 if (encoder->crtc) {
10519 crtc = encoder->crtc;
10520
10521 ret = drm_modeset_lock(&crtc->mutex, ctx);
10522 if (ret)
10523 goto fail;
10524 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10525 if (ret)
10526 goto fail;
10527
10528 old->dpms_mode = connector->dpms;
10529 old->load_detect_temp = false;
10530
10531 /* Make sure the crtc and connector are running */
10532 if (connector->dpms != DRM_MODE_DPMS_ON)
10533 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
10534
10535 return true;
10536 }
10537
10538 /* Find an unused one (if possible) */
10539 for_each_crtc(dev, possible_crtc) {
10540 i++;
10541 if (!(encoder->possible_crtcs & (1 << i)))
10542 continue;
10543 if (possible_crtc->state->enable)
10544 continue;
10545
10546 crtc = possible_crtc;
10547 break;
10548 }
10549
10550 /*
10551 * If we didn't find an unused CRTC, don't use any.
10552 */
10553 if (!crtc) {
10554 DRM_DEBUG_KMS("no pipe available for load-detect\n");
10555 goto fail;
10556 }
10557
10558 ret = drm_modeset_lock(&crtc->mutex, ctx);
10559 if (ret)
10560 goto fail;
10561 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10562 if (ret)
10563 goto fail;
10564
10565 intel_crtc = to_intel_crtc(crtc);
10566 old->dpms_mode = connector->dpms;
10567 old->load_detect_temp = true;
10568 old->release_fb = NULL;
10569
10570 state = drm_atomic_state_alloc(dev);
10571 if (!state)
10572 return false;
10573
10574 state->acquire_ctx = ctx;
10575
10576 connector_state = drm_atomic_get_connector_state(state, connector);
10577 if (IS_ERR(connector_state)) {
10578 ret = PTR_ERR(connector_state);
10579 goto fail;
10580 }
10581
10582 connector_state->crtc = crtc;
10583 connector_state->best_encoder = &intel_encoder->base;
10584
10585 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10586 if (IS_ERR(crtc_state)) {
10587 ret = PTR_ERR(crtc_state);
10588 goto fail;
10589 }
10590
10591 crtc_state->base.active = crtc_state->base.enable = true;
10592
10593 if (!mode)
10594 mode = &load_detect_mode;
10595
10596 /* We need a framebuffer large enough to accommodate all accesses
10597 * that the plane may generate whilst we perform load detection.
10598 * We can not rely on the fbcon either being present (we get called
10599 * during its initialisation to detect all boot displays, or it may
10600 * not even exist) or that it is large enough to satisfy the
10601 * requested mode.
10602 */
10603 fb = mode_fits_in_fbdev(dev, mode);
10604 if (fb == NULL) {
10605 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
10606 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10607 old->release_fb = fb;
10608 } else
10609 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
10610 if (IS_ERR(fb)) {
10611 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
10612 goto fail;
10613 }
10614
10615 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10616 if (ret)
10617 goto fail;
10618
10619 drm_mode_copy(&crtc_state->base.mode, mode);
10620
10621 if (drm_atomic_commit(state)) {
10622 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
10623 if (old->release_fb)
10624 old->release_fb->funcs->destroy(old->release_fb);
10625 goto fail;
10626 }
10627 crtc->primary->crtc = crtc;
10628
10629 /* let the connector get through one full cycle before testing */
10630 intel_wait_for_vblank(dev, intel_crtc->pipe);
10631 return true;
10632
10633 fail:
10634 drm_atomic_state_free(state);
10635 state = NULL;
10636
10637 if (ret == -EDEADLK) {
10638 drm_modeset_backoff(ctx);
10639 goto retry;
10640 }
10641
10642 return false;
10643 }
10644
10645 void intel_release_load_detect_pipe(struct drm_connector *connector,
10646 struct intel_load_detect_pipe *old,
10647 struct drm_modeset_acquire_ctx *ctx)
10648 {
10649 struct drm_device *dev = connector->dev;
10650 struct intel_encoder *intel_encoder =
10651 intel_attached_encoder(connector);
10652 struct drm_encoder *encoder = &intel_encoder->base;
10653 struct drm_crtc *crtc = encoder->crtc;
10654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10655 struct drm_atomic_state *state;
10656 struct drm_connector_state *connector_state;
10657 struct intel_crtc_state *crtc_state;
10658 int ret;
10659
10660 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
10661 connector->base.id, connector->name,
10662 encoder->base.id, encoder->name);
10663
10664 if (old->load_detect_temp) {
10665 state = drm_atomic_state_alloc(dev);
10666 if (!state)
10667 goto fail;
10668
10669 state->acquire_ctx = ctx;
10670
10671 connector_state = drm_atomic_get_connector_state(state, connector);
10672 if (IS_ERR(connector_state))
10673 goto fail;
10674
10675 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10676 if (IS_ERR(crtc_state))
10677 goto fail;
10678
10679 connector_state->best_encoder = NULL;
10680 connector_state->crtc = NULL;
10681
10682 crtc_state->base.enable = crtc_state->base.active = false;
10683
10684 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10685 0, 0);
10686 if (ret)
10687 goto fail;
10688
10689 ret = drm_atomic_commit(state);
10690 if (ret)
10691 goto fail;
10692
10693 if (old->release_fb) {
10694 drm_framebuffer_unregister_private(old->release_fb);
10695 drm_framebuffer_unreference(old->release_fb);
10696 }
10697
10698 return;
10699 }
10700
10701 /* Switch crtc and encoder back off if necessary */
10702 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10703 connector->funcs->dpms(connector, old->dpms_mode);
10704
10705 return;
10706 fail:
10707 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10708 drm_atomic_state_free(state);
10709 }
10710
10711 static int i9xx_pll_refclk(struct drm_device *dev,
10712 const struct intel_crtc_state *pipe_config)
10713 {
10714 struct drm_i915_private *dev_priv = dev->dev_private;
10715 u32 dpll = pipe_config->dpll_hw_state.dpll;
10716
10717 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
10718 return dev_priv->vbt.lvds_ssc_freq;
10719 else if (HAS_PCH_SPLIT(dev))
10720 return 120000;
10721 else if (!IS_GEN2(dev))
10722 return 96000;
10723 else
10724 return 48000;
10725 }
10726
10727 /* Returns the clock of the currently programmed mode of the given pipe. */
10728 static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
10729 struct intel_crtc_state *pipe_config)
10730 {
10731 struct drm_device *dev = crtc->base.dev;
10732 struct drm_i915_private *dev_priv = dev->dev_private;
10733 int pipe = pipe_config->cpu_transcoder;
10734 u32 dpll = pipe_config->dpll_hw_state.dpll;
10735 u32 fp;
10736 intel_clock_t clock;
10737 int port_clock;
10738 int refclk = i9xx_pll_refclk(dev, pipe_config);
10739
10740 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
10741 fp = pipe_config->dpll_hw_state.fp0;
10742 else
10743 fp = pipe_config->dpll_hw_state.fp1;
10744
10745 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
10746 if (IS_PINEVIEW(dev)) {
10747 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10748 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
10749 } else {
10750 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10751 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10752 }
10753
10754 if (!IS_GEN2(dev)) {
10755 if (IS_PINEVIEW(dev))
10756 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10757 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
10758 else
10759 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
10760 DPLL_FPA01_P1_POST_DIV_SHIFT);
10761
10762 switch (dpll & DPLL_MODE_MASK) {
10763 case DPLLB_MODE_DAC_SERIAL:
10764 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10765 5 : 10;
10766 break;
10767 case DPLLB_MODE_LVDS:
10768 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10769 7 : 14;
10770 break;
10771 default:
10772 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
10773 "mode\n", (int)(dpll & DPLL_MODE_MASK));
10774 return;
10775 }
10776
10777 if (IS_PINEVIEW(dev))
10778 port_clock = pnv_calc_dpll_params(refclk, &clock);
10779 else
10780 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10781 } else {
10782 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
10783 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
10784
10785 if (is_lvds) {
10786 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10787 DPLL_FPA01_P1_POST_DIV_SHIFT);
10788
10789 if (lvds & LVDS_CLKB_POWER_UP)
10790 clock.p2 = 7;
10791 else
10792 clock.p2 = 14;
10793 } else {
10794 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10795 clock.p1 = 2;
10796 else {
10797 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10798 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10799 }
10800 if (dpll & PLL_P2_DIVIDE_BY_4)
10801 clock.p2 = 4;
10802 else
10803 clock.p2 = 2;
10804 }
10805
10806 port_clock = i9xx_calc_dpll_params(refclk, &clock);
10807 }
10808
10809 /*
10810 * This value includes pixel_multiplier. We will use
10811 * port_clock to compute adjusted_mode.crtc_clock in the
10812 * encoder's get_config() function.
10813 */
10814 pipe_config->port_clock = port_clock;
10815 }
10816
10817 int intel_dotclock_calculate(int link_freq,
10818 const struct intel_link_m_n *m_n)
10819 {
10820 /*
10821 * The calculation for the data clock is:
10822 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
10823 * But we want to avoid losing precison if possible, so:
10824 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
10825 *
10826 * and the link clock is simpler:
10827 * link_clock = (m * link_clock) / n
10828 */
10829
10830 if (!m_n->link_n)
10831 return 0;
10832
10833 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10834 }
10835
10836 static void ironlake_pch_clock_get(struct intel_crtc *crtc,
10837 struct intel_crtc_state *pipe_config)
10838 {
10839 struct drm_device *dev = crtc->base.dev;
10840
10841 /* read out port_clock from the DPLL */
10842 i9xx_crtc_clock_get(crtc, pipe_config);
10843
10844 /*
10845 * This value does not include pixel_multiplier.
10846 * We will check that port_clock and adjusted_mode.crtc_clock
10847 * agree once we know their relationship in the encoder's
10848 * get_config() function.
10849 */
10850 pipe_config->base.adjusted_mode.crtc_clock =
10851 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10852 &pipe_config->fdi_m_n);
10853 }
10854
10855 /** Returns the currently programmed mode of the given pipe. */
10856 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10857 struct drm_crtc *crtc)
10858 {
10859 struct drm_i915_private *dev_priv = dev->dev_private;
10860 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10861 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
10862 struct drm_display_mode *mode;
10863 struct intel_crtc_state pipe_config;
10864 int htot = I915_READ(HTOTAL(cpu_transcoder));
10865 int hsync = I915_READ(HSYNC(cpu_transcoder));
10866 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10867 int vsync = I915_READ(VSYNC(cpu_transcoder));
10868 enum pipe pipe = intel_crtc->pipe;
10869
10870 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10871 if (!mode)
10872 return NULL;
10873
10874 /*
10875 * Construct a pipe_config sufficient for getting the clock info
10876 * back out of crtc_clock_get.
10877 *
10878 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10879 * to use a real value here instead.
10880 */
10881 pipe_config.cpu_transcoder = (enum transcoder) pipe;
10882 pipe_config.pixel_multiplier = 1;
10883 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10884 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10885 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
10886 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10887
10888 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
10889 mode->hdisplay = (htot & 0xffff) + 1;
10890 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10891 mode->hsync_start = (hsync & 0xffff) + 1;
10892 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10893 mode->vdisplay = (vtot & 0xffff) + 1;
10894 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10895 mode->vsync_start = (vsync & 0xffff) + 1;
10896 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10897
10898 drm_mode_set_name(mode);
10899
10900 return mode;
10901 }
10902
10903 void intel_mark_busy(struct drm_device *dev)
10904 {
10905 struct drm_i915_private *dev_priv = dev->dev_private;
10906
10907 if (dev_priv->mm.busy)
10908 return;
10909
10910 intel_runtime_pm_get(dev_priv);
10911 i915_update_gfx_val(dev_priv);
10912 if (INTEL_INFO(dev)->gen >= 6)
10913 gen6_rps_busy(dev_priv);
10914 dev_priv->mm.busy = true;
10915 }
10916
10917 void intel_mark_idle(struct drm_device *dev)
10918 {
10919 struct drm_i915_private *dev_priv = dev->dev_private;
10920
10921 if (!dev_priv->mm.busy)
10922 return;
10923
10924 dev_priv->mm.busy = false;
10925
10926 if (INTEL_INFO(dev)->gen >= 6)
10927 gen6_rps_idle(dev->dev_private);
10928
10929 intel_runtime_pm_put(dev_priv);
10930 }
10931
10932 static void intel_crtc_destroy(struct drm_crtc *crtc)
10933 {
10934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10935 struct drm_device *dev = crtc->dev;
10936 struct intel_unpin_work *work;
10937
10938 spin_lock_irq(&dev->event_lock);
10939 work = intel_crtc->unpin_work;
10940 intel_crtc->unpin_work = NULL;
10941 spin_unlock_irq(&dev->event_lock);
10942
10943 if (work) {
10944 cancel_work_sync(&work->work);
10945 kfree(work);
10946 }
10947
10948 drm_crtc_cleanup(crtc);
10949
10950 kfree(intel_crtc);
10951 }
10952
10953 static void intel_unpin_work_fn(struct work_struct *__work)
10954 {
10955 struct intel_unpin_work *work =
10956 container_of(__work, struct intel_unpin_work, work);
10957 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10958 struct drm_device *dev = crtc->base.dev;
10959 struct drm_plane *primary = crtc->base.primary;
10960
10961 mutex_lock(&dev->struct_mutex);
10962 intel_unpin_fb_obj(work->old_fb, primary->state);
10963 drm_gem_object_unreference(&work->pending_flip_obj->base);
10964
10965 if (work->flip_queued_req)
10966 i915_gem_request_assign(&work->flip_queued_req, NULL);
10967 mutex_unlock(&dev->struct_mutex);
10968
10969 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
10970 drm_framebuffer_unreference(work->old_fb);
10971
10972 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10973 atomic_dec(&crtc->unpin_work_count);
10974
10975 kfree(work);
10976 }
10977
10978 static void do_intel_finish_page_flip(struct drm_device *dev,
10979 struct drm_crtc *crtc)
10980 {
10981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10982 struct intel_unpin_work *work;
10983 unsigned long flags;
10984
10985 /* Ignore early vblank irqs */
10986 if (intel_crtc == NULL)
10987 return;
10988
10989 /*
10990 * This is called both by irq handlers and the reset code (to complete
10991 * lost pageflips) so needs the full irqsave spinlocks.
10992 */
10993 spin_lock_irqsave(&dev->event_lock, flags);
10994 work = intel_crtc->unpin_work;
10995
10996 /* Ensure we don't miss a work->pending update ... */
10997 smp_rmb();
10998
10999 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
11000 spin_unlock_irqrestore(&dev->event_lock, flags);
11001 return;
11002 }
11003
11004 page_flip_completed(intel_crtc);
11005
11006 spin_unlock_irqrestore(&dev->event_lock, flags);
11007 }
11008
11009 void intel_finish_page_flip(struct drm_device *dev, int pipe)
11010 {
11011 struct drm_i915_private *dev_priv = dev->dev_private;
11012 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11013
11014 do_intel_finish_page_flip(dev, crtc);
11015 }
11016
11017 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
11018 {
11019 struct drm_i915_private *dev_priv = dev->dev_private;
11020 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
11021
11022 do_intel_finish_page_flip(dev, crtc);
11023 }
11024
11025 /* Is 'a' after or equal to 'b'? */
11026 static bool g4x_flip_count_after_eq(u32 a, u32 b)
11027 {
11028 return !((a - b) & 0x80000000);
11029 }
11030
11031 static bool page_flip_finished(struct intel_crtc *crtc)
11032 {
11033 struct drm_device *dev = crtc->base.dev;
11034 struct drm_i915_private *dev_priv = dev->dev_private;
11035
11036 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
11037 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
11038 return true;
11039
11040 /*
11041 * The relevant registers doen't exist on pre-ctg.
11042 * As the flip done interrupt doesn't trigger for mmio
11043 * flips on gmch platforms, a flip count check isn't
11044 * really needed there. But since ctg has the registers,
11045 * include it in the check anyway.
11046 */
11047 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
11048 return true;
11049
11050 /*
11051 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
11052 * used the same base address. In that case the mmio flip might
11053 * have completed, but the CS hasn't even executed the flip yet.
11054 *
11055 * A flip count check isn't enough as the CS might have updated
11056 * the base address just after start of vblank, but before we
11057 * managed to process the interrupt. This means we'd complete the
11058 * CS flip too soon.
11059 *
11060 * Combining both checks should get us a good enough result. It may
11061 * still happen that the CS flip has been executed, but has not
11062 * yet actually completed. But in case the base address is the same
11063 * anyway, we don't really care.
11064 */
11065 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
11066 crtc->unpin_work->gtt_offset &&
11067 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_G4X(crtc->pipe)),
11068 crtc->unpin_work->flip_count);
11069 }
11070
11071 void intel_prepare_page_flip(struct drm_device *dev, int plane)
11072 {
11073 struct drm_i915_private *dev_priv = dev->dev_private;
11074 struct intel_crtc *intel_crtc =
11075 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
11076 unsigned long flags;
11077
11078
11079 /*
11080 * This is called both by irq handlers and the reset code (to complete
11081 * lost pageflips) so needs the full irqsave spinlocks.
11082 *
11083 * NB: An MMIO update of the plane base pointer will also
11084 * generate a page-flip completion irq, i.e. every modeset
11085 * is also accompanied by a spurious intel_prepare_page_flip().
11086 */
11087 spin_lock_irqsave(&dev->event_lock, flags);
11088 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
11089 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
11090 spin_unlock_irqrestore(&dev->event_lock, flags);
11091 }
11092
11093 static inline void intel_mark_page_flip_active(struct intel_unpin_work *work)
11094 {
11095 /* Ensure that the work item is consistent when activating it ... */
11096 smp_wmb();
11097 atomic_set(&work->pending, INTEL_FLIP_PENDING);
11098 /* and that it is marked active as soon as the irq could fire. */
11099 smp_wmb();
11100 }
11101
11102 static int intel_gen2_queue_flip(struct drm_device *dev,
11103 struct drm_crtc *crtc,
11104 struct drm_framebuffer *fb,
11105 struct drm_i915_gem_object *obj,
11106 struct drm_i915_gem_request *req,
11107 uint32_t flags)
11108 {
11109 struct intel_engine_cs *ring = req->ring;
11110 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11111 u32 flip_mask;
11112 int ret;
11113
11114 ret = intel_ring_begin(req, 6);
11115 if (ret)
11116 return ret;
11117
11118 /* Can't queue multiple flips, so wait for the previous
11119 * one to finish before executing the next.
11120 */
11121 if (intel_crtc->plane)
11122 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11123 else
11124 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11125 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11126 intel_ring_emit(ring, MI_NOOP);
11127 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11128 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11129 intel_ring_emit(ring, fb->pitches[0]);
11130 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11131 intel_ring_emit(ring, 0); /* aux display base address, unused */
11132
11133 intel_mark_page_flip_active(intel_crtc->unpin_work);
11134 return 0;
11135 }
11136
11137 static int intel_gen3_queue_flip(struct drm_device *dev,
11138 struct drm_crtc *crtc,
11139 struct drm_framebuffer *fb,
11140 struct drm_i915_gem_object *obj,
11141 struct drm_i915_gem_request *req,
11142 uint32_t flags)
11143 {
11144 struct intel_engine_cs *ring = req->ring;
11145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11146 u32 flip_mask;
11147 int ret;
11148
11149 ret = intel_ring_begin(req, 6);
11150 if (ret)
11151 return ret;
11152
11153 if (intel_crtc->plane)
11154 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
11155 else
11156 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
11157 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
11158 intel_ring_emit(ring, MI_NOOP);
11159 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
11160 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11161 intel_ring_emit(ring, fb->pitches[0]);
11162 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11163 intel_ring_emit(ring, MI_NOOP);
11164
11165 intel_mark_page_flip_active(intel_crtc->unpin_work);
11166 return 0;
11167 }
11168
11169 static int intel_gen4_queue_flip(struct drm_device *dev,
11170 struct drm_crtc *crtc,
11171 struct drm_framebuffer *fb,
11172 struct drm_i915_gem_object *obj,
11173 struct drm_i915_gem_request *req,
11174 uint32_t flags)
11175 {
11176 struct intel_engine_cs *ring = req->ring;
11177 struct drm_i915_private *dev_priv = dev->dev_private;
11178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11179 uint32_t pf, pipesrc;
11180 int ret;
11181
11182 ret = intel_ring_begin(req, 4);
11183 if (ret)
11184 return ret;
11185
11186 /* i965+ uses the linear or tiled offsets from the
11187 * Display Registers (which do not change across a page-flip)
11188 * so we need only reprogram the base address.
11189 */
11190 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11191 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11192 intel_ring_emit(ring, fb->pitches[0]);
11193 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
11194 obj->tiling_mode);
11195
11196 /* XXX Enabling the panel-fitter across page-flip is so far
11197 * untested on non-native modes, so ignore it for now.
11198 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
11199 */
11200 pf = 0;
11201 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11202 intel_ring_emit(ring, pf | pipesrc);
11203
11204 intel_mark_page_flip_active(intel_crtc->unpin_work);
11205 return 0;
11206 }
11207
11208 static int intel_gen6_queue_flip(struct drm_device *dev,
11209 struct drm_crtc *crtc,
11210 struct drm_framebuffer *fb,
11211 struct drm_i915_gem_object *obj,
11212 struct drm_i915_gem_request *req,
11213 uint32_t flags)
11214 {
11215 struct intel_engine_cs *ring = req->ring;
11216 struct drm_i915_private *dev_priv = dev->dev_private;
11217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11218 uint32_t pf, pipesrc;
11219 int ret;
11220
11221 ret = intel_ring_begin(req, 4);
11222 if (ret)
11223 return ret;
11224
11225 intel_ring_emit(ring, MI_DISPLAY_FLIP |
11226 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
11227 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
11228 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11229
11230 /* Contrary to the suggestions in the documentation,
11231 * "Enable Panel Fitter" does not seem to be required when page
11232 * flipping with a non-native mode, and worse causes a normal
11233 * modeset to fail.
11234 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
11235 */
11236 pf = 0;
11237 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
11238 intel_ring_emit(ring, pf | pipesrc);
11239
11240 intel_mark_page_flip_active(intel_crtc->unpin_work);
11241 return 0;
11242 }
11243
11244 static int intel_gen7_queue_flip(struct drm_device *dev,
11245 struct drm_crtc *crtc,
11246 struct drm_framebuffer *fb,
11247 struct drm_i915_gem_object *obj,
11248 struct drm_i915_gem_request *req,
11249 uint32_t flags)
11250 {
11251 struct intel_engine_cs *ring = req->ring;
11252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11253 uint32_t plane_bit = 0;
11254 int len, ret;
11255
11256 switch (intel_crtc->plane) {
11257 case PLANE_A:
11258 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11259 break;
11260 case PLANE_B:
11261 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11262 break;
11263 case PLANE_C:
11264 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11265 break;
11266 default:
11267 WARN_ONCE(1, "unknown plane in flip command\n");
11268 return -ENODEV;
11269 }
11270
11271 len = 4;
11272 if (ring->id == RCS) {
11273 len += 6;
11274 /*
11275 * On Gen 8, SRM is now taking an extra dword to accommodate
11276 * 48bits addresses, and we need a NOOP for the batch size to
11277 * stay even.
11278 */
11279 if (IS_GEN8(dev))
11280 len += 2;
11281 }
11282
11283 /*
11284 * BSpec MI_DISPLAY_FLIP for IVB:
11285 * "The full packet must be contained within the same cache line."
11286 *
11287 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11288 * cacheline, if we ever start emitting more commands before
11289 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11290 * then do the cacheline alignment, and finally emit the
11291 * MI_DISPLAY_FLIP.
11292 */
11293 ret = intel_ring_cacheline_align(req);
11294 if (ret)
11295 return ret;
11296
11297 ret = intel_ring_begin(req, len);
11298 if (ret)
11299 return ret;
11300
11301 /* Unmask the flip-done completion message. Note that the bspec says that
11302 * we should do this for both the BCS and RCS, and that we must not unmask
11303 * more than one flip event at any time (or ensure that one flip message
11304 * can be sent by waiting for flip-done prior to queueing new flips).
11305 * Experimentation says that BCS works despite DERRMR masking all
11306 * flip-done completion events and that unmasking all planes at once
11307 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11308 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11309 */
11310 if (ring->id == RCS) {
11311 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11312 intel_ring_emit_reg(ring, DERRMR);
11313 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11314 DERRMR_PIPEB_PRI_FLIP_DONE |
11315 DERRMR_PIPEC_PRI_FLIP_DONE));
11316 if (IS_GEN8(dev))
11317 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8 |
11318 MI_SRM_LRM_GLOBAL_GTT);
11319 else
11320 intel_ring_emit(ring, MI_STORE_REGISTER_MEM |
11321 MI_SRM_LRM_GLOBAL_GTT);
11322 intel_ring_emit_reg(ring, DERRMR);
11323 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
11324 if (IS_GEN8(dev)) {
11325 intel_ring_emit(ring, 0);
11326 intel_ring_emit(ring, MI_NOOP);
11327 }
11328 }
11329
11330 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
11331 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
11332 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
11333 intel_ring_emit(ring, (MI_NOOP));
11334
11335 intel_mark_page_flip_active(intel_crtc->unpin_work);
11336 return 0;
11337 }
11338
11339 static bool use_mmio_flip(struct intel_engine_cs *ring,
11340 struct drm_i915_gem_object *obj)
11341 {
11342 /*
11343 * This is not being used for older platforms, because
11344 * non-availability of flip done interrupt forces us to use
11345 * CS flips. Older platforms derive flip done using some clever
11346 * tricks involving the flip_pending status bits and vblank irqs.
11347 * So using MMIO flips there would disrupt this mechanism.
11348 */
11349
11350 if (ring == NULL)
11351 return true;
11352
11353 if (INTEL_INFO(ring->dev)->gen < 5)
11354 return false;
11355
11356 if (i915.use_mmio_flip < 0)
11357 return false;
11358 else if (i915.use_mmio_flip > 0)
11359 return true;
11360 else if (i915.enable_execlists)
11361 return true;
11362 else if (obj->base.dma_buf &&
11363 !reservation_object_test_signaled_rcu(obj->base.dma_buf->resv,
11364 false))
11365 return true;
11366 else
11367 return ring != i915_gem_request_get_ring(obj->last_write_req);
11368 }
11369
11370 static void skl_do_mmio_flip(struct intel_crtc *intel_crtc,
11371 unsigned int rotation,
11372 struct intel_unpin_work *work)
11373 {
11374 struct drm_device *dev = intel_crtc->base.dev;
11375 struct drm_i915_private *dev_priv = dev->dev_private;
11376 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
11377 const enum pipe pipe = intel_crtc->pipe;
11378 u32 ctl, stride, tile_height;
11379
11380 ctl = I915_READ(PLANE_CTL(pipe, 0));
11381 ctl &= ~PLANE_CTL_TILED_MASK;
11382 switch (fb->modifier[0]) {
11383 case DRM_FORMAT_MOD_NONE:
11384 break;
11385 case I915_FORMAT_MOD_X_TILED:
11386 ctl |= PLANE_CTL_TILED_X;
11387 break;
11388 case I915_FORMAT_MOD_Y_TILED:
11389 ctl |= PLANE_CTL_TILED_Y;
11390 break;
11391 case I915_FORMAT_MOD_Yf_TILED:
11392 ctl |= PLANE_CTL_TILED_YF;
11393 break;
11394 default:
11395 MISSING_CASE(fb->modifier[0]);
11396 }
11397
11398 /*
11399 * The stride is either expressed as a multiple of 64 bytes chunks for
11400 * linear buffers or in number of tiles for tiled buffers.
11401 */
11402 if (intel_rotation_90_or_270(rotation)) {
11403 /* stride = Surface height in tiles */
11404 tile_height = intel_tile_height(dev, fb->pixel_format,
11405 fb->modifier[0], 0);
11406 stride = DIV_ROUND_UP(fb->height, tile_height);
11407 } else {
11408 stride = fb->pitches[0] /
11409 intel_fb_stride_alignment(dev_priv, fb->modifier[0],
11410 fb->pixel_format);
11411 }
11412
11413 /*
11414 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11415 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11416 */
11417 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11418 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11419
11420 I915_WRITE(PLANE_SURF(pipe, 0), work->gtt_offset);
11421 POSTING_READ(PLANE_SURF(pipe, 0));
11422 }
11423
11424 static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc,
11425 struct intel_unpin_work *work)
11426 {
11427 struct drm_device *dev = intel_crtc->base.dev;
11428 struct drm_i915_private *dev_priv = dev->dev_private;
11429 struct intel_framebuffer *intel_fb =
11430 to_intel_framebuffer(intel_crtc->base.primary->fb);
11431 struct drm_i915_gem_object *obj = intel_fb->obj;
11432 i915_reg_t reg = DSPCNTR(intel_crtc->plane);
11433 u32 dspcntr;
11434
11435 dspcntr = I915_READ(reg);
11436
11437 if (obj->tiling_mode != I915_TILING_NONE)
11438 dspcntr |= DISPPLANE_TILED;
11439 else
11440 dspcntr &= ~DISPPLANE_TILED;
11441
11442 I915_WRITE(reg, dspcntr);
11443
11444 I915_WRITE(DSPSURF(intel_crtc->plane), work->gtt_offset);
11445 POSTING_READ(DSPSURF(intel_crtc->plane));
11446 }
11447
11448 /*
11449 * XXX: This is the temporary way to update the plane registers until we get
11450 * around to using the usual plane update functions for MMIO flips
11451 */
11452 static void intel_do_mmio_flip(struct intel_mmio_flip *mmio_flip)
11453 {
11454 struct intel_crtc *crtc = mmio_flip->crtc;
11455 struct intel_unpin_work *work;
11456
11457 spin_lock_irq(&crtc->base.dev->event_lock);
11458 work = crtc->unpin_work;
11459 spin_unlock_irq(&crtc->base.dev->event_lock);
11460 if (work == NULL)
11461 return;
11462
11463 intel_mark_page_flip_active(work);
11464
11465 intel_pipe_update_start(crtc);
11466
11467 if (INTEL_INFO(mmio_flip->i915)->gen >= 9)
11468 skl_do_mmio_flip(crtc, mmio_flip->rotation, work);
11469 else
11470 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11471 ilk_do_mmio_flip(crtc, work);
11472
11473 intel_pipe_update_end(crtc);
11474 }
11475
11476 static void intel_mmio_flip_work_func(struct work_struct *work)
11477 {
11478 struct intel_mmio_flip *mmio_flip =
11479 container_of(work, struct intel_mmio_flip, work);
11480 struct intel_framebuffer *intel_fb =
11481 to_intel_framebuffer(mmio_flip->crtc->base.primary->fb);
11482 struct drm_i915_gem_object *obj = intel_fb->obj;
11483
11484 if (mmio_flip->req) {
11485 WARN_ON(__i915_wait_request(mmio_flip->req,
11486 mmio_flip->crtc->reset_counter,
11487 false, NULL,
11488 &mmio_flip->i915->rps.mmioflips));
11489 i915_gem_request_unreference__unlocked(mmio_flip->req);
11490 }
11491
11492 /* For framebuffer backed by dmabuf, wait for fence */
11493 if (obj->base.dma_buf)
11494 WARN_ON(reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
11495 false, false,
11496 MAX_SCHEDULE_TIMEOUT) < 0);
11497
11498 intel_do_mmio_flip(mmio_flip);
11499 kfree(mmio_flip);
11500 }
11501
11502 static int intel_queue_mmio_flip(struct drm_device *dev,
11503 struct drm_crtc *crtc,
11504 struct drm_i915_gem_object *obj)
11505 {
11506 struct intel_mmio_flip *mmio_flip;
11507
11508 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11509 if (mmio_flip == NULL)
11510 return -ENOMEM;
11511
11512 mmio_flip->i915 = to_i915(dev);
11513 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
11514 mmio_flip->crtc = to_intel_crtc(crtc);
11515 mmio_flip->rotation = crtc->primary->state->rotation;
11516
11517 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11518 schedule_work(&mmio_flip->work);
11519
11520 return 0;
11521 }
11522
11523 static int intel_default_queue_flip(struct drm_device *dev,
11524 struct drm_crtc *crtc,
11525 struct drm_framebuffer *fb,
11526 struct drm_i915_gem_object *obj,
11527 struct drm_i915_gem_request *req,
11528 uint32_t flags)
11529 {
11530 return -ENODEV;
11531 }
11532
11533 static bool __intel_pageflip_stall_check(struct drm_device *dev,
11534 struct drm_crtc *crtc)
11535 {
11536 struct drm_i915_private *dev_priv = dev->dev_private;
11537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11538 struct intel_unpin_work *work = intel_crtc->unpin_work;
11539 u32 addr;
11540
11541 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11542 return true;
11543
11544 if (atomic_read(&work->pending) < INTEL_FLIP_PENDING)
11545 return false;
11546
11547 if (!work->enable_stall_check)
11548 return false;
11549
11550 if (work->flip_ready_vblank == 0) {
11551 if (work->flip_queued_req &&
11552 !i915_gem_request_completed(work->flip_queued_req, true))
11553 return false;
11554
11555 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
11556 }
11557
11558 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
11559 return false;
11560
11561 /* Potential stall - if we see that the flip has happened,
11562 * assume a missed interrupt. */
11563 if (INTEL_INFO(dev)->gen >= 4)
11564 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11565 else
11566 addr = I915_READ(DSPADDR(intel_crtc->plane));
11567
11568 /* There is a potential issue here with a false positive after a flip
11569 * to the same address. We could address this by checking for a
11570 * non-incrementing frame counter.
11571 */
11572 return addr == work->gtt_offset;
11573 }
11574
11575 void intel_check_page_flip(struct drm_device *dev, int pipe)
11576 {
11577 struct drm_i915_private *dev_priv = dev->dev_private;
11578 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11580 struct intel_unpin_work *work;
11581
11582 WARN_ON(!in_interrupt());
11583
11584 if (crtc == NULL)
11585 return;
11586
11587 spin_lock(&dev->event_lock);
11588 work = intel_crtc->unpin_work;
11589 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
11590 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
11591 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
11592 page_flip_completed(intel_crtc);
11593 work = NULL;
11594 }
11595 if (work != NULL &&
11596 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11597 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
11598 spin_unlock(&dev->event_lock);
11599 }
11600
11601 static int intel_crtc_page_flip(struct drm_crtc *crtc,
11602 struct drm_framebuffer *fb,
11603 struct drm_pending_vblank_event *event,
11604 uint32_t page_flip_flags)
11605 {
11606 struct drm_device *dev = crtc->dev;
11607 struct drm_i915_private *dev_priv = dev->dev_private;
11608 struct drm_framebuffer *old_fb = crtc->primary->fb;
11609 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
11610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11611 struct drm_plane *primary = crtc->primary;
11612 enum pipe pipe = intel_crtc->pipe;
11613 struct intel_unpin_work *work;
11614 struct intel_engine_cs *ring;
11615 bool mmio_flip;
11616 struct drm_i915_gem_request *request = NULL;
11617 int ret;
11618
11619 /*
11620 * drm_mode_page_flip_ioctl() should already catch this, but double
11621 * check to be safe. In the future we may enable pageflipping from
11622 * a disabled primary plane.
11623 */
11624 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11625 return -EBUSY;
11626
11627 /* Can't change pixel format via MI display flips. */
11628 if (fb->pixel_format != crtc->primary->fb->pixel_format)
11629 return -EINVAL;
11630
11631 /*
11632 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11633 * Note that pitch changes could also affect these register.
11634 */
11635 if (INTEL_INFO(dev)->gen > 3 &&
11636 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11637 fb->pitches[0] != crtc->primary->fb->pitches[0]))
11638 return -EINVAL;
11639
11640 if (i915_terminally_wedged(&dev_priv->gpu_error))
11641 goto out_hang;
11642
11643 work = kzalloc(sizeof(*work), GFP_KERNEL);
11644 if (work == NULL)
11645 return -ENOMEM;
11646
11647 work->event = event;
11648 work->crtc = crtc;
11649 work->old_fb = old_fb;
11650 INIT_WORK(&work->work, intel_unpin_work_fn);
11651
11652 ret = drm_crtc_vblank_get(crtc);
11653 if (ret)
11654 goto free_work;
11655
11656 /* We borrow the event spin lock for protecting unpin_work */
11657 spin_lock_irq(&dev->event_lock);
11658 if (intel_crtc->unpin_work) {
11659 /* Before declaring the flip queue wedged, check if
11660 * the hardware completed the operation behind our backs.
11661 */
11662 if (__intel_pageflip_stall_check(dev, crtc)) {
11663 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11664 page_flip_completed(intel_crtc);
11665 } else {
11666 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
11667 spin_unlock_irq(&dev->event_lock);
11668
11669 drm_crtc_vblank_put(crtc);
11670 kfree(work);
11671 return -EBUSY;
11672 }
11673 }
11674 intel_crtc->unpin_work = work;
11675 spin_unlock_irq(&dev->event_lock);
11676
11677 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11678 flush_workqueue(dev_priv->wq);
11679
11680 /* Reference the objects for the scheduled work. */
11681 drm_framebuffer_reference(work->old_fb);
11682 drm_gem_object_reference(&obj->base);
11683
11684 crtc->primary->fb = fb;
11685 update_state_fb(crtc->primary);
11686
11687 work->pending_flip_obj = obj;
11688
11689 ret = i915_mutex_lock_interruptible(dev);
11690 if (ret)
11691 goto cleanup;
11692
11693 atomic_inc(&intel_crtc->unpin_work_count);
11694 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
11695
11696 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
11697 work->flip_count = I915_READ(PIPE_FLIPCOUNT_G4X(pipe)) + 1;
11698
11699 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
11700 ring = &dev_priv->ring[BCS];
11701 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
11702 /* vlv: DISPLAY_FLIP fails to change tiling */
11703 ring = NULL;
11704 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
11705 ring = &dev_priv->ring[BCS];
11706 } else if (INTEL_INFO(dev)->gen >= 7) {
11707 ring = i915_gem_request_get_ring(obj->last_write_req);
11708 if (ring == NULL || ring->id != RCS)
11709 ring = &dev_priv->ring[BCS];
11710 } else {
11711 ring = &dev_priv->ring[RCS];
11712 }
11713
11714 mmio_flip = use_mmio_flip(ring, obj);
11715
11716 /* When using CS flips, we want to emit semaphores between rings.
11717 * However, when using mmio flips we will create a task to do the
11718 * synchronisation, so all we want here is to pin the framebuffer
11719 * into the display plane and skip any waits.
11720 */
11721 if (!mmio_flip) {
11722 ret = i915_gem_object_sync(obj, ring, &request);
11723 if (ret)
11724 goto cleanup_pending;
11725 }
11726
11727 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
11728 crtc->primary->state);
11729 if (ret)
11730 goto cleanup_pending;
11731
11732 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary),
11733 obj, 0);
11734 work->gtt_offset += intel_crtc->dspaddr_offset;
11735
11736 if (mmio_flip) {
11737 ret = intel_queue_mmio_flip(dev, crtc, obj);
11738 if (ret)
11739 goto cleanup_unpin;
11740
11741 i915_gem_request_assign(&work->flip_queued_req,
11742 obj->last_write_req);
11743 } else {
11744 if (!request) {
11745 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11746 if (ret)
11747 goto cleanup_unpin;
11748 }
11749
11750 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
11751 page_flip_flags);
11752 if (ret)
11753 goto cleanup_unpin;
11754
11755 i915_gem_request_assign(&work->flip_queued_req, request);
11756 }
11757
11758 if (request)
11759 i915_add_request_no_flush(request);
11760
11761 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
11762 work->enable_stall_check = true;
11763
11764 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
11765 to_intel_plane(primary)->frontbuffer_bit);
11766 mutex_unlock(&dev->struct_mutex);
11767
11768 intel_fbc_deactivate(intel_crtc);
11769 intel_frontbuffer_flip_prepare(dev,
11770 to_intel_plane(primary)->frontbuffer_bit);
11771
11772 trace_i915_flip_request(intel_crtc->plane, obj);
11773
11774 return 0;
11775
11776 cleanup_unpin:
11777 intel_unpin_fb_obj(fb, crtc->primary->state);
11778 cleanup_pending:
11779 if (request)
11780 i915_gem_request_cancel(request);
11781 atomic_dec(&intel_crtc->unpin_work_count);
11782 mutex_unlock(&dev->struct_mutex);
11783 cleanup:
11784 crtc->primary->fb = old_fb;
11785 update_state_fb(crtc->primary);
11786
11787 drm_gem_object_unreference_unlocked(&obj->base);
11788 drm_framebuffer_unreference(work->old_fb);
11789
11790 spin_lock_irq(&dev->event_lock);
11791 intel_crtc->unpin_work = NULL;
11792 spin_unlock_irq(&dev->event_lock);
11793
11794 drm_crtc_vblank_put(crtc);
11795 free_work:
11796 kfree(work);
11797
11798 if (ret == -EIO) {
11799 struct drm_atomic_state *state;
11800 struct drm_plane_state *plane_state;
11801
11802 out_hang:
11803 state = drm_atomic_state_alloc(dev);
11804 if (!state)
11805 return -ENOMEM;
11806 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11807
11808 retry:
11809 plane_state = drm_atomic_get_plane_state(state, primary);
11810 ret = PTR_ERR_OR_ZERO(plane_state);
11811 if (!ret) {
11812 drm_atomic_set_fb_for_plane(plane_state, fb);
11813
11814 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11815 if (!ret)
11816 ret = drm_atomic_commit(state);
11817 }
11818
11819 if (ret == -EDEADLK) {
11820 drm_modeset_backoff(state->acquire_ctx);
11821 drm_atomic_state_clear(state);
11822 goto retry;
11823 }
11824
11825 if (ret)
11826 drm_atomic_state_free(state);
11827
11828 if (ret == 0 && event) {
11829 spin_lock_irq(&dev->event_lock);
11830 drm_send_vblank_event(dev, pipe, event);
11831 spin_unlock_irq(&dev->event_lock);
11832 }
11833 }
11834 return ret;
11835 }
11836
11837
11838 /**
11839 * intel_wm_need_update - Check whether watermarks need updating
11840 * @plane: drm plane
11841 * @state: new plane state
11842 *
11843 * Check current plane state versus the new one to determine whether
11844 * watermarks need to be recalculated.
11845 *
11846 * Returns true or false.
11847 */
11848 static bool intel_wm_need_update(struct drm_plane *plane,
11849 struct drm_plane_state *state)
11850 {
11851 struct intel_plane_state *new = to_intel_plane_state(state);
11852 struct intel_plane_state *cur = to_intel_plane_state(plane->state);
11853
11854 /* Update watermarks on tiling or size changes. */
11855 if (new->visible != cur->visible)
11856 return true;
11857
11858 if (!cur->base.fb || !new->base.fb)
11859 return false;
11860
11861 if (cur->base.fb->modifier[0] != new->base.fb->modifier[0] ||
11862 cur->base.rotation != new->base.rotation ||
11863 drm_rect_width(&new->src) != drm_rect_width(&cur->src) ||
11864 drm_rect_height(&new->src) != drm_rect_height(&cur->src) ||
11865 drm_rect_width(&new->dst) != drm_rect_width(&cur->dst) ||
11866 drm_rect_height(&new->dst) != drm_rect_height(&cur->dst))
11867 return true;
11868
11869 return false;
11870 }
11871
11872 static bool needs_scaling(struct intel_plane_state *state)
11873 {
11874 int src_w = drm_rect_width(&state->src) >> 16;
11875 int src_h = drm_rect_height(&state->src) >> 16;
11876 int dst_w = drm_rect_width(&state->dst);
11877 int dst_h = drm_rect_height(&state->dst);
11878
11879 return (src_w != dst_w || src_h != dst_h);
11880 }
11881
11882 int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11883 struct drm_plane_state *plane_state)
11884 {
11885 struct intel_crtc_state *pipe_config = to_intel_crtc_state(crtc_state);
11886 struct drm_crtc *crtc = crtc_state->crtc;
11887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11888 struct drm_plane *plane = plane_state->plane;
11889 struct drm_device *dev = crtc->dev;
11890 struct drm_i915_private *dev_priv = dev->dev_private;
11891 struct intel_plane_state *old_plane_state =
11892 to_intel_plane_state(plane->state);
11893 int idx = intel_crtc->base.base.id, ret;
11894 int i = drm_plane_index(plane);
11895 bool mode_changed = needs_modeset(crtc_state);
11896 bool was_crtc_enabled = crtc->state->active;
11897 bool is_crtc_enabled = crtc_state->active;
11898 bool turn_off, turn_on, visible, was_visible;
11899 struct drm_framebuffer *fb = plane_state->fb;
11900
11901 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11902 plane->type != DRM_PLANE_TYPE_CURSOR) {
11903 ret = skl_update_scaler_plane(
11904 to_intel_crtc_state(crtc_state),
11905 to_intel_plane_state(plane_state));
11906 if (ret)
11907 return ret;
11908 }
11909
11910 was_visible = old_plane_state->visible;
11911 visible = to_intel_plane_state(plane_state)->visible;
11912
11913 if (!was_crtc_enabled && WARN_ON(was_visible))
11914 was_visible = false;
11915
11916 /*
11917 * Visibility is calculated as if the crtc was on, but
11918 * after scaler setup everything depends on it being off
11919 * when the crtc isn't active.
11920 */
11921 if (!is_crtc_enabled)
11922 to_intel_plane_state(plane_state)->visible = visible = false;
11923
11924 if (!was_visible && !visible)
11925 return 0;
11926
11927 turn_off = was_visible && (!visible || mode_changed);
11928 turn_on = visible && (!was_visible || mode_changed);
11929
11930 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11931 plane->base.id, fb ? fb->base.id : -1);
11932
11933 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11934 plane->base.id, was_visible, visible,
11935 turn_off, turn_on, mode_changed);
11936
11937 if (turn_on || turn_off) {
11938 pipe_config->wm_changed = true;
11939
11940 /* must disable cxsr around plane enable/disable */
11941 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11942 if (is_crtc_enabled)
11943 intel_crtc->atomic.wait_vblank = true;
11944 pipe_config->disable_cxsr = true;
11945 }
11946 } else if (intel_wm_need_update(plane, plane_state)) {
11947 pipe_config->wm_changed = true;
11948 }
11949
11950 /* Pre-gen9 platforms need two-step watermark updates */
11951 if (pipe_config->wm_changed && INTEL_INFO(dev)->gen < 9 &&
11952 dev_priv->display.optimize_watermarks)
11953 to_intel_crtc_state(crtc_state)->wm.need_postvbl_update = true;
11954
11955 if (visible || was_visible)
11956 intel_crtc->atomic.fb_bits |=
11957 to_intel_plane(plane)->frontbuffer_bit;
11958
11959 switch (plane->type) {
11960 case DRM_PLANE_TYPE_PRIMARY:
11961 intel_crtc->atomic.pre_disable_primary = turn_off;
11962 intel_crtc->atomic.post_enable_primary = turn_on;
11963
11964 if (turn_off) {
11965 /*
11966 * FIXME: Actually if we will still have any other
11967 * plane enabled on the pipe we could let IPS enabled
11968 * still, but for now lets consider that when we make
11969 * primary invisible by setting DSPCNTR to 0 on
11970 * update_primary_plane function IPS needs to be
11971 * disable.
11972 */
11973 intel_crtc->atomic.disable_ips = true;
11974
11975 intel_crtc->atomic.disable_fbc = true;
11976 }
11977
11978 /*
11979 * FBC does not work on some platforms for rotated
11980 * planes, so disable it when rotation is not 0 and
11981 * update it when rotation is set back to 0.
11982 *
11983 * FIXME: This is redundant with the fbc update done in
11984 * the primary plane enable function except that that
11985 * one is done too late. We eventually need to unify
11986 * this.
11987 */
11988
11989 if (visible &&
11990 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11991 dev_priv->fbc.crtc == intel_crtc &&
11992 plane_state->rotation != BIT(DRM_ROTATE_0))
11993 intel_crtc->atomic.disable_fbc = true;
11994
11995 /*
11996 * BDW signals flip done immediately if the plane
11997 * is disabled, even if the plane enable is already
11998 * armed to occur at the next vblank :(
11999 */
12000 if (turn_on && IS_BROADWELL(dev))
12001 intel_crtc->atomic.wait_vblank = true;
12002
12003 intel_crtc->atomic.update_fbc |= visible || mode_changed;
12004 break;
12005 case DRM_PLANE_TYPE_CURSOR:
12006 break;
12007 case DRM_PLANE_TYPE_OVERLAY:
12008 /*
12009 * WaCxSRDisabledForSpriteScaling:ivb
12010 *
12011 * cstate->update_wm was already set above, so this flag will
12012 * take effect when we commit and program watermarks.
12013 */
12014 if (IS_IVYBRIDGE(dev) &&
12015 needs_scaling(to_intel_plane_state(plane_state)) &&
12016 !needs_scaling(old_plane_state)) {
12017 to_intel_crtc_state(crtc_state)->disable_lp_wm = true;
12018 } else if (turn_off && !mode_changed) {
12019 intel_crtc->atomic.wait_vblank = true;
12020 intel_crtc->atomic.update_sprite_watermarks |=
12021 1 << i;
12022 }
12023
12024 break;
12025 }
12026 return 0;
12027 }
12028
12029 static bool encoders_cloneable(const struct intel_encoder *a,
12030 const struct intel_encoder *b)
12031 {
12032 /* masks could be asymmetric, so check both ways */
12033 return a == b || (a->cloneable & (1 << b->type) &&
12034 b->cloneable & (1 << a->type));
12035 }
12036
12037 static bool check_single_encoder_cloning(struct drm_atomic_state *state,
12038 struct intel_crtc *crtc,
12039 struct intel_encoder *encoder)
12040 {
12041 struct intel_encoder *source_encoder;
12042 struct drm_connector *connector;
12043 struct drm_connector_state *connector_state;
12044 int i;
12045
12046 for_each_connector_in_state(state, connector, connector_state, i) {
12047 if (connector_state->crtc != &crtc->base)
12048 continue;
12049
12050 source_encoder =
12051 to_intel_encoder(connector_state->best_encoder);
12052 if (!encoders_cloneable(encoder, source_encoder))
12053 return false;
12054 }
12055
12056 return true;
12057 }
12058
12059 static bool check_encoder_cloning(struct drm_atomic_state *state,
12060 struct intel_crtc *crtc)
12061 {
12062 struct intel_encoder *encoder;
12063 struct drm_connector *connector;
12064 struct drm_connector_state *connector_state;
12065 int i;
12066
12067 for_each_connector_in_state(state, connector, connector_state, i) {
12068 if (connector_state->crtc != &crtc->base)
12069 continue;
12070
12071 encoder = to_intel_encoder(connector_state->best_encoder);
12072 if (!check_single_encoder_cloning(state, crtc, encoder))
12073 return false;
12074 }
12075
12076 return true;
12077 }
12078
12079 static int intel_crtc_atomic_check(struct drm_crtc *crtc,
12080 struct drm_crtc_state *crtc_state)
12081 {
12082 struct drm_device *dev = crtc->dev;
12083 struct drm_i915_private *dev_priv = dev->dev_private;
12084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12085 struct intel_crtc_state *pipe_config =
12086 to_intel_crtc_state(crtc_state);
12087 struct drm_atomic_state *state = crtc_state->state;
12088 int ret;
12089 bool mode_changed = needs_modeset(crtc_state);
12090
12091 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
12092 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
12093 return -EINVAL;
12094 }
12095
12096 if (mode_changed && !crtc_state->active)
12097 pipe_config->wm_changed = true;
12098
12099 if (mode_changed && crtc_state->enable &&
12100 dev_priv->display.crtc_compute_clock &&
12101 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
12102 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
12103 pipe_config);
12104 if (ret)
12105 return ret;
12106 }
12107
12108 ret = 0;
12109 if (dev_priv->display.compute_pipe_wm) {
12110 ret = dev_priv->display.compute_pipe_wm(intel_crtc, state);
12111 if (ret) {
12112 DRM_DEBUG_KMS("Target pipe watermarks are invalid\n");
12113 return ret;
12114 }
12115 }
12116
12117 if (dev_priv->display.compute_intermediate_wm &&
12118 !to_intel_atomic_state(state)->skip_intermediate_wm) {
12119 if (WARN_ON(!dev_priv->display.compute_pipe_wm))
12120 return 0;
12121
12122 /*
12123 * Calculate 'intermediate' watermarks that satisfy both the
12124 * old state and the new state. We can program these
12125 * immediately.
12126 */
12127 ret = dev_priv->display.compute_intermediate_wm(crtc->dev,
12128 intel_crtc,
12129 pipe_config);
12130 if (ret) {
12131 DRM_DEBUG_KMS("No valid intermediate pipe watermarks are possible\n");
12132 return ret;
12133 }
12134 }
12135
12136 if (INTEL_INFO(dev)->gen >= 9) {
12137 if (mode_changed)
12138 ret = skl_update_scaler_crtc(pipe_config);
12139
12140 if (!ret)
12141 ret = intel_atomic_setup_scalers(dev, intel_crtc,
12142 pipe_config);
12143 }
12144
12145 return ret;
12146 }
12147
12148 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
12149 .mode_set_base_atomic = intel_pipe_set_base_atomic,
12150 .load_lut = intel_crtc_load_lut,
12151 .atomic_begin = intel_begin_crtc_commit,
12152 .atomic_flush = intel_finish_crtc_commit,
12153 .atomic_check = intel_crtc_atomic_check,
12154 };
12155
12156 static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
12157 {
12158 struct intel_connector *connector;
12159
12160 for_each_intel_connector(dev, connector) {
12161 if (connector->base.encoder) {
12162 connector->base.state->best_encoder =
12163 connector->base.encoder;
12164 connector->base.state->crtc =
12165 connector->base.encoder->crtc;
12166 } else {
12167 connector->base.state->best_encoder = NULL;
12168 connector->base.state->crtc = NULL;
12169 }
12170 }
12171 }
12172
12173 static void
12174 connected_sink_compute_bpp(struct intel_connector *connector,
12175 struct intel_crtc_state *pipe_config)
12176 {
12177 int bpp = pipe_config->pipe_bpp;
12178
12179 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
12180 connector->base.base.id,
12181 connector->base.name);
12182
12183 /* Don't use an invalid EDID bpc value */
12184 if (connector->base.display_info.bpc &&
12185 connector->base.display_info.bpc * 3 < bpp) {
12186 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
12187 bpp, connector->base.display_info.bpc*3);
12188 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
12189 }
12190
12191 /* Clamp bpp to 8 on screens without EDID 1.4 */
12192 if (connector->base.display_info.bpc == 0 && bpp > 24) {
12193 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
12194 bpp);
12195 pipe_config->pipe_bpp = 24;
12196 }
12197 }
12198
12199 static int
12200 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
12201 struct intel_crtc_state *pipe_config)
12202 {
12203 struct drm_device *dev = crtc->base.dev;
12204 struct drm_atomic_state *state;
12205 struct drm_connector *connector;
12206 struct drm_connector_state *connector_state;
12207 int bpp, i;
12208
12209 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
12210 bpp = 10*3;
12211 else if (INTEL_INFO(dev)->gen >= 5)
12212 bpp = 12*3;
12213 else
12214 bpp = 8*3;
12215
12216
12217 pipe_config->pipe_bpp = bpp;
12218
12219 state = pipe_config->base.state;
12220
12221 /* Clamp display bpp to EDID value */
12222 for_each_connector_in_state(state, connector, connector_state, i) {
12223 if (connector_state->crtc != &crtc->base)
12224 continue;
12225
12226 connected_sink_compute_bpp(to_intel_connector(connector),
12227 pipe_config);
12228 }
12229
12230 return bpp;
12231 }
12232
12233 static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
12234 {
12235 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
12236 "type: 0x%x flags: 0x%x\n",
12237 mode->crtc_clock,
12238 mode->crtc_hdisplay, mode->crtc_hsync_start,
12239 mode->crtc_hsync_end, mode->crtc_htotal,
12240 mode->crtc_vdisplay, mode->crtc_vsync_start,
12241 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
12242 }
12243
12244 static void intel_dump_pipe_config(struct intel_crtc *crtc,
12245 struct intel_crtc_state *pipe_config,
12246 const char *context)
12247 {
12248 struct drm_device *dev = crtc->base.dev;
12249 struct drm_plane *plane;
12250 struct intel_plane *intel_plane;
12251 struct intel_plane_state *state;
12252 struct drm_framebuffer *fb;
12253
12254 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
12255 context, pipe_config, pipe_name(crtc->pipe));
12256
12257 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
12258 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
12259 pipe_config->pipe_bpp, pipe_config->dither);
12260 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12261 pipe_config->has_pch_encoder,
12262 pipe_config->fdi_lanes,
12263 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
12264 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
12265 pipe_config->fdi_m_n.tu);
12266 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
12267 pipe_config->has_dp_encoder,
12268 pipe_config->lane_count,
12269 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
12270 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
12271 pipe_config->dp_m_n.tu);
12272
12273 DRM_DEBUG_KMS("dp: %i, lanes: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
12274 pipe_config->has_dp_encoder,
12275 pipe_config->lane_count,
12276 pipe_config->dp_m2_n2.gmch_m,
12277 pipe_config->dp_m2_n2.gmch_n,
12278 pipe_config->dp_m2_n2.link_m,
12279 pipe_config->dp_m2_n2.link_n,
12280 pipe_config->dp_m2_n2.tu);
12281
12282 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
12283 pipe_config->has_audio,
12284 pipe_config->has_infoframe);
12285
12286 DRM_DEBUG_KMS("requested mode:\n");
12287 drm_mode_debug_printmodeline(&pipe_config->base.mode);
12288 DRM_DEBUG_KMS("adjusted mode:\n");
12289 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12290 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
12291 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
12292 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12293 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
12294 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12295 crtc->num_scalers,
12296 pipe_config->scaler_state.scaler_users,
12297 pipe_config->scaler_state.scaler_id);
12298 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12299 pipe_config->gmch_pfit.control,
12300 pipe_config->gmch_pfit.pgm_ratios,
12301 pipe_config->gmch_pfit.lvds_border_bits);
12302 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
12303 pipe_config->pch_pfit.pos,
12304 pipe_config->pch_pfit.size,
12305 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
12306 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
12307 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
12308
12309 if (IS_BROXTON(dev)) {
12310 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
12311 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
12312 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
12313 pipe_config->ddi_pll_sel,
12314 pipe_config->dpll_hw_state.ebb0,
12315 pipe_config->dpll_hw_state.ebb4,
12316 pipe_config->dpll_hw_state.pll0,
12317 pipe_config->dpll_hw_state.pll1,
12318 pipe_config->dpll_hw_state.pll2,
12319 pipe_config->dpll_hw_state.pll3,
12320 pipe_config->dpll_hw_state.pll6,
12321 pipe_config->dpll_hw_state.pll8,
12322 pipe_config->dpll_hw_state.pll9,
12323 pipe_config->dpll_hw_state.pll10,
12324 pipe_config->dpll_hw_state.pcsdw12);
12325 } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
12326 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12327 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12328 pipe_config->ddi_pll_sel,
12329 pipe_config->dpll_hw_state.ctrl1,
12330 pipe_config->dpll_hw_state.cfgcr1,
12331 pipe_config->dpll_hw_state.cfgcr2);
12332 } else if (HAS_DDI(dev)) {
12333 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
12334 pipe_config->ddi_pll_sel,
12335 pipe_config->dpll_hw_state.wrpll,
12336 pipe_config->dpll_hw_state.spll);
12337 } else {
12338 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12339 "fp0: 0x%x, fp1: 0x%x\n",
12340 pipe_config->dpll_hw_state.dpll,
12341 pipe_config->dpll_hw_state.dpll_md,
12342 pipe_config->dpll_hw_state.fp0,
12343 pipe_config->dpll_hw_state.fp1);
12344 }
12345
12346 DRM_DEBUG_KMS("planes on this crtc\n");
12347 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12348 intel_plane = to_intel_plane(plane);
12349 if (intel_plane->pipe != crtc->pipe)
12350 continue;
12351
12352 state = to_intel_plane_state(plane->state);
12353 fb = state->base.fb;
12354 if (!fb) {
12355 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12356 "disabled, scaler_id = %d\n",
12357 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12358 plane->base.id, intel_plane->pipe,
12359 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12360 drm_plane_index(plane), state->scaler_id);
12361 continue;
12362 }
12363
12364 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12365 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12366 plane->base.id, intel_plane->pipe,
12367 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12368 drm_plane_index(plane));
12369 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12370 fb->base.id, fb->width, fb->height, fb->pixel_format);
12371 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12372 state->scaler_id,
12373 state->src.x1 >> 16, state->src.y1 >> 16,
12374 drm_rect_width(&state->src) >> 16,
12375 drm_rect_height(&state->src) >> 16,
12376 state->dst.x1, state->dst.y1,
12377 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12378 }
12379 }
12380
12381 static bool check_digital_port_conflicts(struct drm_atomic_state *state)
12382 {
12383 struct drm_device *dev = state->dev;
12384 struct drm_connector *connector;
12385 unsigned int used_ports = 0;
12386
12387 /*
12388 * Walk the connector list instead of the encoder
12389 * list to detect the problem on ddi platforms
12390 * where there's just one encoder per digital port.
12391 */
12392 drm_for_each_connector(connector, dev) {
12393 struct drm_connector_state *connector_state;
12394 struct intel_encoder *encoder;
12395
12396 connector_state = drm_atomic_get_existing_connector_state(state, connector);
12397 if (!connector_state)
12398 connector_state = connector->state;
12399
12400 if (!connector_state->best_encoder)
12401 continue;
12402
12403 encoder = to_intel_encoder(connector_state->best_encoder);
12404
12405 WARN_ON(!connector_state->crtc);
12406
12407 switch (encoder->type) {
12408 unsigned int port_mask;
12409 case INTEL_OUTPUT_UNKNOWN:
12410 if (WARN_ON(!HAS_DDI(dev)))
12411 break;
12412 case INTEL_OUTPUT_DISPLAYPORT:
12413 case INTEL_OUTPUT_HDMI:
12414 case INTEL_OUTPUT_EDP:
12415 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12416
12417 /* the same port mustn't appear more than once */
12418 if (used_ports & port_mask)
12419 return false;
12420
12421 used_ports |= port_mask;
12422 default:
12423 break;
12424 }
12425 }
12426
12427 return true;
12428 }
12429
12430 static void
12431 clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12432 {
12433 struct drm_crtc_state tmp_state;
12434 struct intel_crtc_scaler_state scaler_state;
12435 struct intel_dpll_hw_state dpll_hw_state;
12436 enum intel_dpll_id shared_dpll;
12437 uint32_t ddi_pll_sel;
12438 bool force_thru;
12439
12440 /* FIXME: before the switch to atomic started, a new pipe_config was
12441 * kzalloc'd. Code that depends on any field being zero should be
12442 * fixed, so that the crtc_state can be safely duplicated. For now,
12443 * only fields that are know to not cause problems are preserved. */
12444
12445 tmp_state = crtc_state->base;
12446 scaler_state = crtc_state->scaler_state;
12447 shared_dpll = crtc_state->shared_dpll;
12448 dpll_hw_state = crtc_state->dpll_hw_state;
12449 ddi_pll_sel = crtc_state->ddi_pll_sel;
12450 force_thru = crtc_state->pch_pfit.force_thru;
12451
12452 memset(crtc_state, 0, sizeof *crtc_state);
12453
12454 crtc_state->base = tmp_state;
12455 crtc_state->scaler_state = scaler_state;
12456 crtc_state->shared_dpll = shared_dpll;
12457 crtc_state->dpll_hw_state = dpll_hw_state;
12458 crtc_state->ddi_pll_sel = ddi_pll_sel;
12459 crtc_state->pch_pfit.force_thru = force_thru;
12460 }
12461
12462 static int
12463 intel_modeset_pipe_config(struct drm_crtc *crtc,
12464 struct intel_crtc_state *pipe_config)
12465 {
12466 struct drm_atomic_state *state = pipe_config->base.state;
12467 struct intel_encoder *encoder;
12468 struct drm_connector *connector;
12469 struct drm_connector_state *connector_state;
12470 int base_bpp, ret = -EINVAL;
12471 int i;
12472 bool retry = true;
12473
12474 clear_intel_crtc_state(pipe_config);
12475
12476 pipe_config->cpu_transcoder =
12477 (enum transcoder) to_intel_crtc(crtc)->pipe;
12478
12479 /*
12480 * Sanitize sync polarity flags based on requested ones. If neither
12481 * positive or negative polarity is requested, treat this as meaning
12482 * negative polarity.
12483 */
12484 if (!(pipe_config->base.adjusted_mode.flags &
12485 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
12486 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
12487
12488 if (!(pipe_config->base.adjusted_mode.flags &
12489 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
12490 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
12491
12492 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12493 pipe_config);
12494 if (base_bpp < 0)
12495 goto fail;
12496
12497 /*
12498 * Determine the real pipe dimensions. Note that stereo modes can
12499 * increase the actual pipe size due to the frame doubling and
12500 * insertion of additional space for blanks between the frame. This
12501 * is stored in the crtc timings. We use the requested mode to do this
12502 * computation to clearly distinguish it from the adjusted mode, which
12503 * can be changed by the connectors in the below retry loop.
12504 */
12505 drm_crtc_get_hv_timing(&pipe_config->base.mode,
12506 &pipe_config->pipe_src_w,
12507 &pipe_config->pipe_src_h);
12508
12509 encoder_retry:
12510 /* Ensure the port clock defaults are reset when retrying. */
12511 pipe_config->port_clock = 0;
12512 pipe_config->pixel_multiplier = 1;
12513
12514 /* Fill in default crtc timings, allow encoders to overwrite them. */
12515 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12516 CRTC_STEREO_DOUBLE);
12517
12518 /* Pass our mode to the connectors and the CRTC to give them a chance to
12519 * adjust it according to limitations or connector properties, and also
12520 * a chance to reject the mode entirely.
12521 */
12522 for_each_connector_in_state(state, connector, connector_state, i) {
12523 if (connector_state->crtc != crtc)
12524 continue;
12525
12526 encoder = to_intel_encoder(connector_state->best_encoder);
12527
12528 if (!(encoder->compute_config(encoder, pipe_config))) {
12529 DRM_DEBUG_KMS("Encoder config failure\n");
12530 goto fail;
12531 }
12532 }
12533
12534 /* Set default port clock if not overwritten by the encoder. Needs to be
12535 * done afterwards in case the encoder adjusts the mode. */
12536 if (!pipe_config->port_clock)
12537 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
12538 * pipe_config->pixel_multiplier;
12539
12540 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
12541 if (ret < 0) {
12542 DRM_DEBUG_KMS("CRTC fixup failed\n");
12543 goto fail;
12544 }
12545
12546 if (ret == RETRY) {
12547 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12548 ret = -EINVAL;
12549 goto fail;
12550 }
12551
12552 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12553 retry = false;
12554 goto encoder_retry;
12555 }
12556
12557 /* Dithering seems to not pass-through bits correctly when it should, so
12558 * only enable it on 6bpc panels. */
12559 pipe_config->dither = pipe_config->pipe_bpp == 6*3;
12560 DRM_DEBUG_KMS("hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
12561 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
12562
12563 fail:
12564 return ret;
12565 }
12566
12567 static void
12568 intel_modeset_update_crtc_state(struct drm_atomic_state *state)
12569 {
12570 struct drm_crtc *crtc;
12571 struct drm_crtc_state *crtc_state;
12572 int i;
12573
12574 /* Double check state. */
12575 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12576 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
12577
12578 /* Update hwmode for vblank functions */
12579 if (crtc->state->active)
12580 crtc->hwmode = crtc->state->adjusted_mode;
12581 else
12582 crtc->hwmode.crtc_clock = 0;
12583
12584 /*
12585 * Update legacy state to satisfy fbc code. This can
12586 * be removed when fbc uses the atomic state.
12587 */
12588 if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
12589 struct drm_plane_state *plane_state = crtc->primary->state;
12590
12591 crtc->primary->fb = plane_state->fb;
12592 crtc->x = plane_state->src_x >> 16;
12593 crtc->y = plane_state->src_y >> 16;
12594 }
12595 }
12596 }
12597
12598 static bool intel_fuzzy_clock_check(int clock1, int clock2)
12599 {
12600 int diff;
12601
12602 if (clock1 == clock2)
12603 return true;
12604
12605 if (!clock1 || !clock2)
12606 return false;
12607
12608 diff = abs(clock1 - clock2);
12609
12610 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12611 return true;
12612
12613 return false;
12614 }
12615
12616 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12617 list_for_each_entry((intel_crtc), \
12618 &(dev)->mode_config.crtc_list, \
12619 base.head) \
12620 for_each_if (mask & (1 <<(intel_crtc)->pipe))
12621
12622 static bool
12623 intel_compare_m_n(unsigned int m, unsigned int n,
12624 unsigned int m2, unsigned int n2,
12625 bool exact)
12626 {
12627 if (m == m2 && n == n2)
12628 return true;
12629
12630 if (exact || !m || !n || !m2 || !n2)
12631 return false;
12632
12633 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12634
12635 if (n > n2) {
12636 while (n > n2) {
12637 m2 <<= 1;
12638 n2 <<= 1;
12639 }
12640 } else if (n < n2) {
12641 while (n < n2) {
12642 m <<= 1;
12643 n <<= 1;
12644 }
12645 }
12646
12647 if (n != n2)
12648 return false;
12649
12650 return intel_fuzzy_clock_check(m, m2);
12651 }
12652
12653 static bool
12654 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12655 struct intel_link_m_n *m2_n2,
12656 bool adjust)
12657 {
12658 if (m_n->tu == m2_n2->tu &&
12659 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12660 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12661 intel_compare_m_n(m_n->link_m, m_n->link_n,
12662 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12663 if (adjust)
12664 *m2_n2 = *m_n;
12665
12666 return true;
12667 }
12668
12669 return false;
12670 }
12671
12672 static bool
12673 intel_pipe_config_compare(struct drm_device *dev,
12674 struct intel_crtc_state *current_config,
12675 struct intel_crtc_state *pipe_config,
12676 bool adjust)
12677 {
12678 bool ret = true;
12679
12680 #define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12681 do { \
12682 if (!adjust) \
12683 DRM_ERROR(fmt, ##__VA_ARGS__); \
12684 else \
12685 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12686 } while (0)
12687
12688 #define PIPE_CONF_CHECK_X(name) \
12689 if (current_config->name != pipe_config->name) { \
12690 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12691 "(expected 0x%08x, found 0x%08x)\n", \
12692 current_config->name, \
12693 pipe_config->name); \
12694 ret = false; \
12695 }
12696
12697 #define PIPE_CONF_CHECK_I(name) \
12698 if (current_config->name != pipe_config->name) { \
12699 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12700 "(expected %i, found %i)\n", \
12701 current_config->name, \
12702 pipe_config->name); \
12703 ret = false; \
12704 }
12705
12706 #define PIPE_CONF_CHECK_M_N(name) \
12707 if (!intel_compare_link_m_n(&current_config->name, \
12708 &pipe_config->name,\
12709 adjust)) { \
12710 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12711 "(expected tu %i gmch %i/%i link %i/%i, " \
12712 "found tu %i, gmch %i/%i link %i/%i)\n", \
12713 current_config->name.tu, \
12714 current_config->name.gmch_m, \
12715 current_config->name.gmch_n, \
12716 current_config->name.link_m, \
12717 current_config->name.link_n, \
12718 pipe_config->name.tu, \
12719 pipe_config->name.gmch_m, \
12720 pipe_config->name.gmch_n, \
12721 pipe_config->name.link_m, \
12722 pipe_config->name.link_n); \
12723 ret = false; \
12724 }
12725
12726 #define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12727 if (!intel_compare_link_m_n(&current_config->name, \
12728 &pipe_config->name, adjust) && \
12729 !intel_compare_link_m_n(&current_config->alt_name, \
12730 &pipe_config->name, adjust)) { \
12731 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12732 "(expected tu %i gmch %i/%i link %i/%i, " \
12733 "or tu %i gmch %i/%i link %i/%i, " \
12734 "found tu %i, gmch %i/%i link %i/%i)\n", \
12735 current_config->name.tu, \
12736 current_config->name.gmch_m, \
12737 current_config->name.gmch_n, \
12738 current_config->name.link_m, \
12739 current_config->name.link_n, \
12740 current_config->alt_name.tu, \
12741 current_config->alt_name.gmch_m, \
12742 current_config->alt_name.gmch_n, \
12743 current_config->alt_name.link_m, \
12744 current_config->alt_name.link_n, \
12745 pipe_config->name.tu, \
12746 pipe_config->name.gmch_m, \
12747 pipe_config->name.gmch_n, \
12748 pipe_config->name.link_m, \
12749 pipe_config->name.link_n); \
12750 ret = false; \
12751 }
12752
12753 /* This is required for BDW+ where there is only one set of registers for
12754 * switching between high and low RR.
12755 * This macro can be used whenever a comparison has to be made between one
12756 * hw state and multiple sw state variables.
12757 */
12758 #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12759 if ((current_config->name != pipe_config->name) && \
12760 (current_config->alt_name != pipe_config->name)) { \
12761 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12762 "(expected %i or %i, found %i)\n", \
12763 current_config->name, \
12764 current_config->alt_name, \
12765 pipe_config->name); \
12766 ret = false; \
12767 }
12768
12769 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
12770 if ((current_config->name ^ pipe_config->name) & (mask)) { \
12771 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
12772 "(expected %i, found %i)\n", \
12773 current_config->name & (mask), \
12774 pipe_config->name & (mask)); \
12775 ret = false; \
12776 }
12777
12778 #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12779 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
12780 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12781 "(expected %i, found %i)\n", \
12782 current_config->name, \
12783 pipe_config->name); \
12784 ret = false; \
12785 }
12786
12787 #define PIPE_CONF_QUIRK(quirk) \
12788 ((current_config->quirks | pipe_config->quirks) & (quirk))
12789
12790 PIPE_CONF_CHECK_I(cpu_transcoder);
12791
12792 PIPE_CONF_CHECK_I(has_pch_encoder);
12793 PIPE_CONF_CHECK_I(fdi_lanes);
12794 PIPE_CONF_CHECK_M_N(fdi_m_n);
12795
12796 PIPE_CONF_CHECK_I(has_dp_encoder);
12797 PIPE_CONF_CHECK_I(lane_count);
12798
12799 if (INTEL_INFO(dev)->gen < 8) {
12800 PIPE_CONF_CHECK_M_N(dp_m_n);
12801
12802 if (current_config->has_drrs)
12803 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12804 } else
12805 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
12806
12807 PIPE_CONF_CHECK_I(has_dsi_encoder);
12808
12809 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12810 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12811 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12812 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12813 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12814 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
12815
12816 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12817 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12818 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12819 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12820 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12821 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
12822
12823 PIPE_CONF_CHECK_I(pixel_multiplier);
12824 PIPE_CONF_CHECK_I(has_hdmi_sink);
12825 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12826 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
12827 PIPE_CONF_CHECK_I(limited_color_range);
12828 PIPE_CONF_CHECK_I(has_infoframe);
12829
12830 PIPE_CONF_CHECK_I(has_audio);
12831
12832 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12833 DRM_MODE_FLAG_INTERLACE);
12834
12835 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
12836 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12837 DRM_MODE_FLAG_PHSYNC);
12838 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12839 DRM_MODE_FLAG_NHSYNC);
12840 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12841 DRM_MODE_FLAG_PVSYNC);
12842 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
12843 DRM_MODE_FLAG_NVSYNC);
12844 }
12845
12846 PIPE_CONF_CHECK_X(gmch_pfit.control);
12847 /* pfit ratios are autocomputed by the hw on gen4+ */
12848 if (INTEL_INFO(dev)->gen < 4)
12849 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12850 PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
12851
12852 if (!adjust) {
12853 PIPE_CONF_CHECK_I(pipe_src_w);
12854 PIPE_CONF_CHECK_I(pipe_src_h);
12855
12856 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12857 if (current_config->pch_pfit.enabled) {
12858 PIPE_CONF_CHECK_X(pch_pfit.pos);
12859 PIPE_CONF_CHECK_X(pch_pfit.size);
12860 }
12861
12862 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12863 }
12864
12865 /* BDW+ don't expose a synchronous way to read the state */
12866 if (IS_HASWELL(dev))
12867 PIPE_CONF_CHECK_I(ips_enabled);
12868
12869 PIPE_CONF_CHECK_I(double_wide);
12870
12871 PIPE_CONF_CHECK_X(ddi_pll_sel);
12872
12873 PIPE_CONF_CHECK_I(shared_dpll);
12874 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
12875 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
12876 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12877 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
12878 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
12879 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
12880 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12881 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12882 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
12883
12884 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12885 PIPE_CONF_CHECK_I(pipe_bpp);
12886
12887 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
12888 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
12889
12890 #undef PIPE_CONF_CHECK_X
12891 #undef PIPE_CONF_CHECK_I
12892 #undef PIPE_CONF_CHECK_I_ALT
12893 #undef PIPE_CONF_CHECK_FLAGS
12894 #undef PIPE_CONF_CHECK_CLOCK_FUZZY
12895 #undef PIPE_CONF_QUIRK
12896 #undef INTEL_ERR_OR_DBG_KMS
12897
12898 return ret;
12899 }
12900
12901 static void check_wm_state(struct drm_device *dev)
12902 {
12903 struct drm_i915_private *dev_priv = dev->dev_private;
12904 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12905 struct intel_crtc *intel_crtc;
12906 int plane;
12907
12908 if (INTEL_INFO(dev)->gen < 9)
12909 return;
12910
12911 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12912 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12913
12914 for_each_intel_crtc(dev, intel_crtc) {
12915 struct skl_ddb_entry *hw_entry, *sw_entry;
12916 const enum pipe pipe = intel_crtc->pipe;
12917
12918 if (!intel_crtc->active)
12919 continue;
12920
12921 /* planes */
12922 for_each_plane(dev_priv, pipe, plane) {
12923 hw_entry = &hw_ddb.plane[pipe][plane];
12924 sw_entry = &sw_ddb->plane[pipe][plane];
12925
12926 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12927 continue;
12928
12929 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12930 "(expected (%u,%u), found (%u,%u))\n",
12931 pipe_name(pipe), plane + 1,
12932 sw_entry->start, sw_entry->end,
12933 hw_entry->start, hw_entry->end);
12934 }
12935
12936 /* cursor */
12937 hw_entry = &hw_ddb.plane[pipe][PLANE_CURSOR];
12938 sw_entry = &sw_ddb->plane[pipe][PLANE_CURSOR];
12939
12940 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12941 continue;
12942
12943 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12944 "(expected (%u,%u), found (%u,%u))\n",
12945 pipe_name(pipe),
12946 sw_entry->start, sw_entry->end,
12947 hw_entry->start, hw_entry->end);
12948 }
12949 }
12950
12951 static void
12952 check_connector_state(struct drm_device *dev,
12953 struct drm_atomic_state *old_state)
12954 {
12955 struct drm_connector_state *old_conn_state;
12956 struct drm_connector *connector;
12957 int i;
12958
12959 for_each_connector_in_state(old_state, connector, old_conn_state, i) {
12960 struct drm_encoder *encoder = connector->encoder;
12961 struct drm_connector_state *state = connector->state;
12962
12963 /* This also checks the encoder/connector hw state with the
12964 * ->get_hw_state callbacks. */
12965 intel_connector_check_state(to_intel_connector(connector));
12966
12967 I915_STATE_WARN(state->best_encoder != encoder,
12968 "connector's atomic encoder doesn't match legacy encoder\n");
12969 }
12970 }
12971
12972 static void
12973 check_encoder_state(struct drm_device *dev)
12974 {
12975 struct intel_encoder *encoder;
12976 struct intel_connector *connector;
12977
12978 for_each_intel_encoder(dev, encoder) {
12979 bool enabled = false;
12980 enum pipe pipe;
12981
12982 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12983 encoder->base.base.id,
12984 encoder->base.name);
12985
12986 for_each_intel_connector(dev, connector) {
12987 if (connector->base.state->best_encoder != &encoder->base)
12988 continue;
12989 enabled = true;
12990
12991 I915_STATE_WARN(connector->base.state->crtc !=
12992 encoder->base.crtc,
12993 "connector's crtc doesn't match encoder crtc\n");
12994 }
12995
12996 I915_STATE_WARN(!!encoder->base.crtc != enabled,
12997 "encoder's enabled state mismatch "
12998 "(expected %i, found %i)\n",
12999 !!encoder->base.crtc, enabled);
13000
13001 if (!encoder->base.crtc) {
13002 bool active;
13003
13004 active = encoder->get_hw_state(encoder, &pipe);
13005 I915_STATE_WARN(active,
13006 "encoder detached but still enabled on pipe %c.\n",
13007 pipe_name(pipe));
13008 }
13009 }
13010 }
13011
13012 static void
13013 check_crtc_state(struct drm_device *dev, struct drm_atomic_state *old_state)
13014 {
13015 struct drm_i915_private *dev_priv = dev->dev_private;
13016 struct intel_encoder *encoder;
13017 struct drm_crtc_state *old_crtc_state;
13018 struct drm_crtc *crtc;
13019 int i;
13020
13021 for_each_crtc_in_state(old_state, crtc, old_crtc_state, i) {
13022 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13023 struct intel_crtc_state *pipe_config, *sw_config;
13024 bool active;
13025
13026 if (!needs_modeset(crtc->state) &&
13027 !to_intel_crtc_state(crtc->state)->update_pipe)
13028 continue;
13029
13030 __drm_atomic_helper_crtc_destroy_state(crtc, old_crtc_state);
13031 pipe_config = to_intel_crtc_state(old_crtc_state);
13032 memset(pipe_config, 0, sizeof(*pipe_config));
13033 pipe_config->base.crtc = crtc;
13034 pipe_config->base.state = old_state;
13035
13036 DRM_DEBUG_KMS("[CRTC:%d]\n",
13037 crtc->base.id);
13038
13039 active = dev_priv->display.get_pipe_config(intel_crtc,
13040 pipe_config);
13041
13042 /* hw state is inconsistent with the pipe quirk */
13043 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
13044 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
13045 active = crtc->state->active;
13046
13047 I915_STATE_WARN(crtc->state->active != active,
13048 "crtc active state doesn't match with hw state "
13049 "(expected %i, found %i)\n", crtc->state->active, active);
13050
13051 I915_STATE_WARN(intel_crtc->active != crtc->state->active,
13052 "transitional active state does not match atomic hw state "
13053 "(expected %i, found %i)\n", crtc->state->active, intel_crtc->active);
13054
13055 for_each_encoder_on_crtc(dev, crtc, encoder) {
13056 enum pipe pipe;
13057
13058 active = encoder->get_hw_state(encoder, &pipe);
13059 I915_STATE_WARN(active != crtc->state->active,
13060 "[ENCODER:%i] active %i with crtc active %i\n",
13061 encoder->base.base.id, active, crtc->state->active);
13062
13063 I915_STATE_WARN(active && intel_crtc->pipe != pipe,
13064 "Encoder connected to wrong pipe %c\n",
13065 pipe_name(pipe));
13066
13067 if (active)
13068 encoder->get_config(encoder, pipe_config);
13069 }
13070
13071 if (!crtc->state->active)
13072 continue;
13073
13074 sw_config = to_intel_crtc_state(crtc->state);
13075 if (!intel_pipe_config_compare(dev, sw_config,
13076 pipe_config, false)) {
13077 I915_STATE_WARN(1, "pipe state doesn't match!\n");
13078 intel_dump_pipe_config(intel_crtc, pipe_config,
13079 "[hw state]");
13080 intel_dump_pipe_config(intel_crtc, sw_config,
13081 "[sw state]");
13082 }
13083 }
13084 }
13085
13086 static void
13087 check_shared_dpll_state(struct drm_device *dev)
13088 {
13089 struct drm_i915_private *dev_priv = dev->dev_private;
13090 struct intel_crtc *crtc;
13091 struct intel_dpll_hw_state dpll_hw_state;
13092 int i;
13093
13094 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13095 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13096 int enabled_crtcs = 0, active_crtcs = 0;
13097 bool active;
13098
13099 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
13100
13101 DRM_DEBUG_KMS("%s\n", pll->name);
13102
13103 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
13104
13105 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
13106 "more active pll users than references: %i vs %i\n",
13107 pll->active, hweight32(pll->config.crtc_mask));
13108 I915_STATE_WARN(pll->active && !pll->on,
13109 "pll in active use but not on in sw tracking\n");
13110 I915_STATE_WARN(pll->on && !pll->active,
13111 "pll in on but not on in use in sw tracking\n");
13112 I915_STATE_WARN(pll->on != active,
13113 "pll on state mismatch (expected %i, found %i)\n",
13114 pll->on, active);
13115
13116 for_each_intel_crtc(dev, crtc) {
13117 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
13118 enabled_crtcs++;
13119 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
13120 active_crtcs++;
13121 }
13122 I915_STATE_WARN(pll->active != active_crtcs,
13123 "pll active crtcs mismatch (expected %i, found %i)\n",
13124 pll->active, active_crtcs);
13125 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
13126 "pll enabled crtcs mismatch (expected %i, found %i)\n",
13127 hweight32(pll->config.crtc_mask), enabled_crtcs);
13128
13129 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
13130 sizeof(dpll_hw_state)),
13131 "pll hw state mismatch\n");
13132 }
13133 }
13134
13135 static void
13136 intel_modeset_check_state(struct drm_device *dev,
13137 struct drm_atomic_state *old_state)
13138 {
13139 check_wm_state(dev);
13140 check_connector_state(dev, old_state);
13141 check_encoder_state(dev);
13142 check_crtc_state(dev, old_state);
13143 check_shared_dpll_state(dev);
13144 }
13145
13146 void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
13147 int dotclock)
13148 {
13149 /*
13150 * FDI already provided one idea for the dotclock.
13151 * Yell if the encoder disagrees.
13152 */
13153 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
13154 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
13155 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
13156 }
13157
13158 static void update_scanline_offset(struct intel_crtc *crtc)
13159 {
13160 struct drm_device *dev = crtc->base.dev;
13161
13162 /*
13163 * The scanline counter increments at the leading edge of hsync.
13164 *
13165 * On most platforms it starts counting from vtotal-1 on the
13166 * first active line. That means the scanline counter value is
13167 * always one less than what we would expect. Ie. just after
13168 * start of vblank, which also occurs at start of hsync (on the
13169 * last active line), the scanline counter will read vblank_start-1.
13170 *
13171 * On gen2 the scanline counter starts counting from 1 instead
13172 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
13173 * to keep the value positive), instead of adding one.
13174 *
13175 * On HSW+ the behaviour of the scanline counter depends on the output
13176 * type. For DP ports it behaves like most other platforms, but on HDMI
13177 * there's an extra 1 line difference. So we need to add two instead of
13178 * one to the value.
13179 */
13180 if (IS_GEN2(dev)) {
13181 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
13182 int vtotal;
13183
13184 vtotal = adjusted_mode->crtc_vtotal;
13185 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
13186 vtotal /= 2;
13187
13188 crtc->scanline_offset = vtotal - 1;
13189 } else if (HAS_DDI(dev) &&
13190 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
13191 crtc->scanline_offset = 2;
13192 } else
13193 crtc->scanline_offset = 1;
13194 }
13195
13196 static void intel_modeset_clear_plls(struct drm_atomic_state *state)
13197 {
13198 struct drm_device *dev = state->dev;
13199 struct drm_i915_private *dev_priv = to_i915(dev);
13200 struct intel_shared_dpll_config *shared_dpll = NULL;
13201 struct intel_crtc *intel_crtc;
13202 struct intel_crtc_state *intel_crtc_state;
13203 struct drm_crtc *crtc;
13204 struct drm_crtc_state *crtc_state;
13205 int i;
13206
13207 if (!dev_priv->display.crtc_compute_clock)
13208 return;
13209
13210 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13211 int dpll;
13212
13213 intel_crtc = to_intel_crtc(crtc);
13214 intel_crtc_state = to_intel_crtc_state(crtc_state);
13215 dpll = intel_crtc_state->shared_dpll;
13216
13217 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
13218 continue;
13219
13220 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
13221
13222 if (!shared_dpll)
13223 shared_dpll = intel_atomic_get_shared_dpll_state(state);
13224
13225 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
13226 }
13227 }
13228
13229 /*
13230 * This implements the workaround described in the "notes" section of the mode
13231 * set sequence documentation. When going from no pipes or single pipe to
13232 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13233 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13234 */
13235 static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13236 {
13237 struct drm_crtc_state *crtc_state;
13238 struct intel_crtc *intel_crtc;
13239 struct drm_crtc *crtc;
13240 struct intel_crtc_state *first_crtc_state = NULL;
13241 struct intel_crtc_state *other_crtc_state = NULL;
13242 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13243 int i;
13244
13245 /* look at all crtc's that are going to be enabled in during modeset */
13246 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13247 intel_crtc = to_intel_crtc(crtc);
13248
13249 if (!crtc_state->active || !needs_modeset(crtc_state))
13250 continue;
13251
13252 if (first_crtc_state) {
13253 other_crtc_state = to_intel_crtc_state(crtc_state);
13254 break;
13255 } else {
13256 first_crtc_state = to_intel_crtc_state(crtc_state);
13257 first_pipe = intel_crtc->pipe;
13258 }
13259 }
13260
13261 /* No workaround needed? */
13262 if (!first_crtc_state)
13263 return 0;
13264
13265 /* w/a possibly needed, check how many crtc's are already enabled. */
13266 for_each_intel_crtc(state->dev, intel_crtc) {
13267 struct intel_crtc_state *pipe_config;
13268
13269 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13270 if (IS_ERR(pipe_config))
13271 return PTR_ERR(pipe_config);
13272
13273 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13274
13275 if (!pipe_config->base.active ||
13276 needs_modeset(&pipe_config->base))
13277 continue;
13278
13279 /* 2 or more enabled crtcs means no need for w/a */
13280 if (enabled_pipe != INVALID_PIPE)
13281 return 0;
13282
13283 enabled_pipe = intel_crtc->pipe;
13284 }
13285
13286 if (enabled_pipe != INVALID_PIPE)
13287 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13288 else if (other_crtc_state)
13289 other_crtc_state->hsw_workaround_pipe = first_pipe;
13290
13291 return 0;
13292 }
13293
13294 static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13295 {
13296 struct drm_crtc *crtc;
13297 struct drm_crtc_state *crtc_state;
13298 int ret = 0;
13299
13300 /* add all active pipes to the state */
13301 for_each_crtc(state->dev, crtc) {
13302 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13303 if (IS_ERR(crtc_state))
13304 return PTR_ERR(crtc_state);
13305
13306 if (!crtc_state->active || needs_modeset(crtc_state))
13307 continue;
13308
13309 crtc_state->mode_changed = true;
13310
13311 ret = drm_atomic_add_affected_connectors(state, crtc);
13312 if (ret)
13313 break;
13314
13315 ret = drm_atomic_add_affected_planes(state, crtc);
13316 if (ret)
13317 break;
13318 }
13319
13320 return ret;
13321 }
13322
13323 static int intel_modeset_checks(struct drm_atomic_state *state)
13324 {
13325 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13326 struct drm_i915_private *dev_priv = state->dev->dev_private;
13327 struct drm_crtc *crtc;
13328 struct drm_crtc_state *crtc_state;
13329 int ret = 0, i;
13330
13331 if (!check_digital_port_conflicts(state)) {
13332 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13333 return -EINVAL;
13334 }
13335
13336 intel_state->modeset = true;
13337 intel_state->active_crtcs = dev_priv->active_crtcs;
13338
13339 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13340 if (crtc_state->active)
13341 intel_state->active_crtcs |= 1 << i;
13342 else
13343 intel_state->active_crtcs &= ~(1 << i);
13344 }
13345
13346 /*
13347 * See if the config requires any additional preparation, e.g.
13348 * to adjust global state with pipes off. We need to do this
13349 * here so we can get the modeset_pipe updated config for the new
13350 * mode set on this crtc. For other crtcs we need to use the
13351 * adjusted_mode bits in the crtc directly.
13352 */
13353 if (dev_priv->display.modeset_calc_cdclk) {
13354 ret = dev_priv->display.modeset_calc_cdclk(state);
13355
13356 if (!ret && intel_state->dev_cdclk != dev_priv->cdclk_freq)
13357 ret = intel_modeset_all_pipes(state);
13358
13359 if (ret < 0)
13360 return ret;
13361 } else
13362 to_intel_atomic_state(state)->cdclk = dev_priv->atomic_cdclk_freq;
13363
13364 intel_modeset_clear_plls(state);
13365
13366 if (IS_HASWELL(dev_priv))
13367 return haswell_mode_set_planes_workaround(state);
13368
13369 return 0;
13370 }
13371
13372 /*
13373 * Handle calculation of various watermark data at the end of the atomic check
13374 * phase. The code here should be run after the per-crtc and per-plane 'check'
13375 * handlers to ensure that all derived state has been updated.
13376 */
13377 static void calc_watermark_data(struct drm_atomic_state *state)
13378 {
13379 struct drm_device *dev = state->dev;
13380 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13381 struct drm_crtc *crtc;
13382 struct drm_crtc_state *cstate;
13383 struct drm_plane *plane;
13384 struct drm_plane_state *pstate;
13385
13386 /*
13387 * Calculate watermark configuration details now that derived
13388 * plane/crtc state is all properly updated.
13389 */
13390 drm_for_each_crtc(crtc, dev) {
13391 cstate = drm_atomic_get_existing_crtc_state(state, crtc) ?:
13392 crtc->state;
13393
13394 if (cstate->active)
13395 intel_state->wm_config.num_pipes_active++;
13396 }
13397 drm_for_each_legacy_plane(plane, dev) {
13398 pstate = drm_atomic_get_existing_plane_state(state, plane) ?:
13399 plane->state;
13400
13401 if (!to_intel_plane_state(pstate)->visible)
13402 continue;
13403
13404 intel_state->wm_config.sprites_enabled = true;
13405 if (pstate->crtc_w != pstate->src_w >> 16 ||
13406 pstate->crtc_h != pstate->src_h >> 16)
13407 intel_state->wm_config.sprites_scaled = true;
13408 }
13409 }
13410
13411 /**
13412 * intel_atomic_check - validate state object
13413 * @dev: drm device
13414 * @state: state to validate
13415 */
13416 static int intel_atomic_check(struct drm_device *dev,
13417 struct drm_atomic_state *state)
13418 {
13419 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13420 struct drm_crtc *crtc;
13421 struct drm_crtc_state *crtc_state;
13422 int ret, i;
13423 bool any_ms = false;
13424
13425 ret = drm_atomic_helper_check_modeset(dev, state);
13426 if (ret)
13427 return ret;
13428
13429 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13430 struct intel_crtc_state *pipe_config =
13431 to_intel_crtc_state(crtc_state);
13432
13433 memset(&to_intel_crtc(crtc)->atomic, 0,
13434 sizeof(struct intel_crtc_atomic_commit));
13435
13436 /* Catch I915_MODE_FLAG_INHERITED */
13437 if (crtc_state->mode.private_flags != crtc->state->mode.private_flags)
13438 crtc_state->mode_changed = true;
13439
13440 if (!crtc_state->enable) {
13441 if (needs_modeset(crtc_state))
13442 any_ms = true;
13443 continue;
13444 }
13445
13446 if (!needs_modeset(crtc_state))
13447 continue;
13448
13449 /* FIXME: For only active_changed we shouldn't need to do any
13450 * state recomputation at all. */
13451
13452 ret = drm_atomic_add_affected_connectors(state, crtc);
13453 if (ret)
13454 return ret;
13455
13456 ret = intel_modeset_pipe_config(crtc, pipe_config);
13457 if (ret)
13458 return ret;
13459
13460 if (i915.fastboot &&
13461 intel_pipe_config_compare(state->dev,
13462 to_intel_crtc_state(crtc->state),
13463 pipe_config, true)) {
13464 crtc_state->mode_changed = false;
13465 to_intel_crtc_state(crtc_state)->update_pipe = true;
13466 }
13467
13468 if (needs_modeset(crtc_state)) {
13469 any_ms = true;
13470
13471 ret = drm_atomic_add_affected_planes(state, crtc);
13472 if (ret)
13473 return ret;
13474 }
13475
13476 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
13477 needs_modeset(crtc_state) ?
13478 "[modeset]" : "[fastset]");
13479 }
13480
13481 if (any_ms) {
13482 ret = intel_modeset_checks(state);
13483
13484 if (ret)
13485 return ret;
13486 } else
13487 intel_state->cdclk = to_i915(state->dev)->cdclk_freq;
13488
13489 ret = drm_atomic_helper_check_planes(state->dev, state);
13490 if (ret)
13491 return ret;
13492
13493 calc_watermark_data(state);
13494
13495 return 0;
13496 }
13497
13498 static int intel_atomic_prepare_commit(struct drm_device *dev,
13499 struct drm_atomic_state *state,
13500 bool async)
13501 {
13502 struct drm_i915_private *dev_priv = dev->dev_private;
13503 struct drm_plane_state *plane_state;
13504 struct drm_crtc_state *crtc_state;
13505 struct drm_plane *plane;
13506 struct drm_crtc *crtc;
13507 int i, ret;
13508
13509 if (async) {
13510 DRM_DEBUG_KMS("i915 does not yet support async commit\n");
13511 return -EINVAL;
13512 }
13513
13514 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13515 ret = intel_crtc_wait_for_pending_flips(crtc);
13516 if (ret)
13517 return ret;
13518
13519 if (atomic_read(&to_intel_crtc(crtc)->unpin_work_count) >= 2)
13520 flush_workqueue(dev_priv->wq);
13521 }
13522
13523 ret = mutex_lock_interruptible(&dev->struct_mutex);
13524 if (ret)
13525 return ret;
13526
13527 ret = drm_atomic_helper_prepare_planes(dev, state);
13528 if (!ret && !async && !i915_reset_in_progress(&dev_priv->gpu_error)) {
13529 u32 reset_counter;
13530
13531 reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
13532 mutex_unlock(&dev->struct_mutex);
13533
13534 for_each_plane_in_state(state, plane, plane_state, i) {
13535 struct intel_plane_state *intel_plane_state =
13536 to_intel_plane_state(plane_state);
13537
13538 if (!intel_plane_state->wait_req)
13539 continue;
13540
13541 ret = __i915_wait_request(intel_plane_state->wait_req,
13542 reset_counter, true,
13543 NULL, NULL);
13544
13545 /* Swallow -EIO errors to allow updates during hw lockup. */
13546 if (ret == -EIO)
13547 ret = 0;
13548
13549 if (ret)
13550 break;
13551 }
13552
13553 if (!ret)
13554 return 0;
13555
13556 mutex_lock(&dev->struct_mutex);
13557 drm_atomic_helper_cleanup_planes(dev, state);
13558 }
13559
13560 mutex_unlock(&dev->struct_mutex);
13561 return ret;
13562 }
13563
13564 /**
13565 * intel_atomic_commit - commit validated state object
13566 * @dev: DRM device
13567 * @state: the top-level driver state object
13568 * @async: asynchronous commit
13569 *
13570 * This function commits a top-level state object that has been validated
13571 * with drm_atomic_helper_check().
13572 *
13573 * FIXME: Atomic modeset support for i915 is not yet complete. At the moment
13574 * we can only handle plane-related operations and do not yet support
13575 * asynchronous commit.
13576 *
13577 * RETURNS
13578 * Zero for success or -errno.
13579 */
13580 static int intel_atomic_commit(struct drm_device *dev,
13581 struct drm_atomic_state *state,
13582 bool async)
13583 {
13584 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
13585 struct drm_i915_private *dev_priv = dev->dev_private;
13586 struct drm_crtc_state *crtc_state;
13587 struct drm_crtc *crtc;
13588 struct intel_crtc_state *intel_cstate;
13589 int ret = 0, i;
13590 bool hw_check = intel_state->modeset;
13591
13592 ret = intel_atomic_prepare_commit(dev, state, async);
13593 if (ret) {
13594 DRM_DEBUG_ATOMIC("Preparing state failed with %i\n", ret);
13595 return ret;
13596 }
13597
13598 drm_atomic_helper_swap_state(dev, state);
13599 dev_priv->wm.config = to_intel_atomic_state(state)->wm_config;
13600
13601 if (intel_state->modeset) {
13602 memcpy(dev_priv->min_pixclk, intel_state->min_pixclk,
13603 sizeof(intel_state->min_pixclk));
13604 dev_priv->active_crtcs = intel_state->active_crtcs;
13605 dev_priv->atomic_cdclk_freq = intel_state->cdclk;
13606 }
13607
13608 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13609 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13610
13611 if (!needs_modeset(crtc->state))
13612 continue;
13613
13614 intel_pre_plane_update(intel_crtc);
13615
13616 if (crtc_state->active) {
13617 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13618 dev_priv->display.crtc_disable(crtc);
13619 intel_crtc->active = false;
13620 intel_disable_shared_dpll(intel_crtc);
13621
13622 /*
13623 * Underruns don't always raise
13624 * interrupts, so check manually.
13625 */
13626 intel_check_cpu_fifo_underruns(dev_priv);
13627 intel_check_pch_fifo_underruns(dev_priv);
13628
13629 if (!crtc->state->active)
13630 intel_update_watermarks(crtc);
13631 }
13632 }
13633
13634 /* Only after disabling all output pipelines that will be changed can we
13635 * update the the output configuration. */
13636 intel_modeset_update_crtc_state(state);
13637
13638 if (intel_state->modeset) {
13639 intel_shared_dpll_commit(state);
13640
13641 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
13642 modeset_update_crtc_power_domains(state);
13643 }
13644
13645 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
13646 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13648 bool modeset = needs_modeset(crtc->state);
13649 bool update_pipe = !modeset &&
13650 to_intel_crtc_state(crtc->state)->update_pipe;
13651 unsigned long put_domains = 0;
13652
13653 if (modeset)
13654 intel_display_power_get(dev_priv, POWER_DOMAIN_MODESET);
13655
13656 if (modeset && crtc->state->active) {
13657 update_scanline_offset(to_intel_crtc(crtc));
13658 dev_priv->display.crtc_enable(crtc);
13659 }
13660
13661 if (update_pipe) {
13662 put_domains = modeset_get_crtc_power_domains(crtc);
13663
13664 /* make sure intel_modeset_check_state runs */
13665 hw_check = true;
13666 }
13667
13668 if (!modeset)
13669 intel_pre_plane_update(intel_crtc);
13670
13671 if (crtc->state->active &&
13672 (crtc->state->planes_changed || update_pipe))
13673 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
13674
13675 if (put_domains)
13676 modeset_put_power_domains(dev_priv, put_domains);
13677
13678 intel_post_plane_update(intel_crtc);
13679
13680 if (modeset)
13681 intel_display_power_put(dev_priv, POWER_DOMAIN_MODESET);
13682 }
13683
13684 /* FIXME: add subpixel order */
13685
13686 drm_atomic_helper_wait_for_vblanks(dev, state);
13687
13688 /*
13689 * Now that the vblank has passed, we can go ahead and program the
13690 * optimal watermarks on platforms that need two-step watermark
13691 * programming.
13692 *
13693 * TODO: Move this (and other cleanup) to an async worker eventually.
13694 */
13695 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13696 intel_cstate = to_intel_crtc_state(crtc->state);
13697
13698 if (dev_priv->display.optimize_watermarks)
13699 dev_priv->display.optimize_watermarks(intel_cstate);
13700 }
13701
13702 mutex_lock(&dev->struct_mutex);
13703 drm_atomic_helper_cleanup_planes(dev, state);
13704 mutex_unlock(&dev->struct_mutex);
13705
13706 if (hw_check)
13707 intel_modeset_check_state(dev, state);
13708
13709 drm_atomic_state_free(state);
13710
13711 /* As one of the primary mmio accessors, KMS has a high likelihood
13712 * of triggering bugs in unclaimed access. After we finish
13713 * modesetting, see if an error has been flagged, and if so
13714 * enable debugging for the next modeset - and hope we catch
13715 * the culprit.
13716 *
13717 * XXX note that we assume display power is on at this point.
13718 * This might hold true now but we need to add pm helper to check
13719 * unclaimed only when the hardware is on, as atomic commits
13720 * can happen also when the device is completely off.
13721 */
13722 intel_uncore_arm_unclaimed_mmio_detection(dev_priv);
13723
13724 return 0;
13725 }
13726
13727 void intel_crtc_restore_mode(struct drm_crtc *crtc)
13728 {
13729 struct drm_device *dev = crtc->dev;
13730 struct drm_atomic_state *state;
13731 struct drm_crtc_state *crtc_state;
13732 int ret;
13733
13734 state = drm_atomic_state_alloc(dev);
13735 if (!state) {
13736 DRM_DEBUG_KMS("[CRTC:%d] crtc restore failed, out of memory",
13737 crtc->base.id);
13738 return;
13739 }
13740
13741 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
13742
13743 retry:
13744 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13745 ret = PTR_ERR_OR_ZERO(crtc_state);
13746 if (!ret) {
13747 if (!crtc_state->active)
13748 goto out;
13749
13750 crtc_state->mode_changed = true;
13751 ret = drm_atomic_commit(state);
13752 }
13753
13754 if (ret == -EDEADLK) {
13755 drm_atomic_state_clear(state);
13756 drm_modeset_backoff(state->acquire_ctx);
13757 goto retry;
13758 }
13759
13760 if (ret)
13761 out:
13762 drm_atomic_state_free(state);
13763 }
13764
13765 #undef for_each_intel_crtc_masked
13766
13767 static const struct drm_crtc_funcs intel_crtc_funcs = {
13768 .gamma_set = intel_crtc_gamma_set,
13769 .set_config = drm_atomic_helper_set_config,
13770 .destroy = intel_crtc_destroy,
13771 .page_flip = intel_crtc_page_flip,
13772 .atomic_duplicate_state = intel_crtc_duplicate_state,
13773 .atomic_destroy_state = intel_crtc_destroy_state,
13774 };
13775
13776 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13777 struct intel_shared_dpll *pll,
13778 struct intel_dpll_hw_state *hw_state)
13779 {
13780 uint32_t val;
13781
13782 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
13783 return false;
13784
13785 val = I915_READ(PCH_DPLL(pll->id));
13786 hw_state->dpll = val;
13787 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13788 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
13789
13790 return val & DPLL_VCO_ENABLE;
13791 }
13792
13793 static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13794 struct intel_shared_dpll *pll)
13795 {
13796 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13797 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
13798 }
13799
13800 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13801 struct intel_shared_dpll *pll)
13802 {
13803 /* PCH refclock must be enabled first */
13804 ibx_assert_pch_refclk_enabled(dev_priv);
13805
13806 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13807
13808 /* Wait for the clocks to stabilize. */
13809 POSTING_READ(PCH_DPLL(pll->id));
13810 udelay(150);
13811
13812 /* The pixel multiplier can only be updated once the
13813 * DPLL is enabled and the clocks are stable.
13814 *
13815 * So write it again.
13816 */
13817 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
13818 POSTING_READ(PCH_DPLL(pll->id));
13819 udelay(200);
13820 }
13821
13822 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13823 struct intel_shared_dpll *pll)
13824 {
13825 struct drm_device *dev = dev_priv->dev;
13826 struct intel_crtc *crtc;
13827
13828 /* Make sure no transcoder isn't still depending on us. */
13829 for_each_intel_crtc(dev, crtc) {
13830 if (intel_crtc_to_shared_dpll(crtc) == pll)
13831 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
13832 }
13833
13834 I915_WRITE(PCH_DPLL(pll->id), 0);
13835 POSTING_READ(PCH_DPLL(pll->id));
13836 udelay(200);
13837 }
13838
13839 static char *ibx_pch_dpll_names[] = {
13840 "PCH DPLL A",
13841 "PCH DPLL B",
13842 };
13843
13844 static void ibx_pch_dpll_init(struct drm_device *dev)
13845 {
13846 struct drm_i915_private *dev_priv = dev->dev_private;
13847 int i;
13848
13849 dev_priv->num_shared_dpll = 2;
13850
13851 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13852 dev_priv->shared_dplls[i].id = i;
13853 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
13854 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
13855 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13856 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
13857 dev_priv->shared_dplls[i].get_hw_state =
13858 ibx_pch_dpll_get_hw_state;
13859 }
13860 }
13861
13862 static void intel_shared_dpll_init(struct drm_device *dev)
13863 {
13864 struct drm_i915_private *dev_priv = dev->dev_private;
13865
13866 if (HAS_DDI(dev))
13867 intel_ddi_pll_init(dev);
13868 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
13869 ibx_pch_dpll_init(dev);
13870 else
13871 dev_priv->num_shared_dpll = 0;
13872
13873 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
13874 }
13875
13876 /**
13877 * intel_prepare_plane_fb - Prepare fb for usage on plane
13878 * @plane: drm plane to prepare for
13879 * @fb: framebuffer to prepare for presentation
13880 *
13881 * Prepares a framebuffer for usage on a display plane. Generally this
13882 * involves pinning the underlying object and updating the frontbuffer tracking
13883 * bits. Some older platforms need special physical address handling for
13884 * cursor planes.
13885 *
13886 * Must be called with struct_mutex held.
13887 *
13888 * Returns 0 on success, negative error code on failure.
13889 */
13890 int
13891 intel_prepare_plane_fb(struct drm_plane *plane,
13892 const struct drm_plane_state *new_state)
13893 {
13894 struct drm_device *dev = plane->dev;
13895 struct drm_framebuffer *fb = new_state->fb;
13896 struct intel_plane *intel_plane = to_intel_plane(plane);
13897 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13898 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb);
13899 int ret = 0;
13900
13901 if (!obj && !old_obj)
13902 return 0;
13903
13904 if (old_obj) {
13905 struct drm_crtc_state *crtc_state =
13906 drm_atomic_get_existing_crtc_state(new_state->state, plane->state->crtc);
13907
13908 /* Big Hammer, we also need to ensure that any pending
13909 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
13910 * current scanout is retired before unpinning the old
13911 * framebuffer. Note that we rely on userspace rendering
13912 * into the buffer attached to the pipe they are waiting
13913 * on. If not, userspace generates a GPU hang with IPEHR
13914 * point to the MI_WAIT_FOR_EVENT.
13915 *
13916 * This should only fail upon a hung GPU, in which case we
13917 * can safely continue.
13918 */
13919 if (needs_modeset(crtc_state))
13920 ret = i915_gem_object_wait_rendering(old_obj, true);
13921
13922 /* Swallow -EIO errors to allow updates during hw lockup. */
13923 if (ret && ret != -EIO)
13924 return ret;
13925 }
13926
13927 /* For framebuffer backed by dmabuf, wait for fence */
13928 if (obj && obj->base.dma_buf) {
13929 long lret;
13930
13931 lret = reservation_object_wait_timeout_rcu(obj->base.dma_buf->resv,
13932 false, true,
13933 MAX_SCHEDULE_TIMEOUT);
13934 if (lret == -ERESTARTSYS)
13935 return lret;
13936
13937 WARN(lret < 0, "waiting returns %li\n", lret);
13938 }
13939
13940 if (!obj) {
13941 ret = 0;
13942 } else if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13943 INTEL_INFO(dev)->cursor_needs_physical) {
13944 int align = IS_I830(dev) ? 16 * 1024 : 256;
13945 ret = i915_gem_object_attach_phys(obj, align);
13946 if (ret)
13947 DRM_DEBUG_KMS("failed to attach phys object\n");
13948 } else {
13949 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state);
13950 }
13951
13952 if (ret == 0) {
13953 if (obj) {
13954 struct intel_plane_state *plane_state =
13955 to_intel_plane_state(new_state);
13956
13957 i915_gem_request_assign(&plane_state->wait_req,
13958 obj->last_write_req);
13959 }
13960
13961 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13962 }
13963
13964 return ret;
13965 }
13966
13967 /**
13968 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13969 * @plane: drm plane to clean up for
13970 * @fb: old framebuffer that was on plane
13971 *
13972 * Cleans up a framebuffer that has just been removed from a plane.
13973 *
13974 * Must be called with struct_mutex held.
13975 */
13976 void
13977 intel_cleanup_plane_fb(struct drm_plane *plane,
13978 const struct drm_plane_state *old_state)
13979 {
13980 struct drm_device *dev = plane->dev;
13981 struct intel_plane *intel_plane = to_intel_plane(plane);
13982 struct intel_plane_state *old_intel_state;
13983 struct drm_i915_gem_object *old_obj = intel_fb_obj(old_state->fb);
13984 struct drm_i915_gem_object *obj = intel_fb_obj(plane->state->fb);
13985
13986 old_intel_state = to_intel_plane_state(old_state);
13987
13988 if (!obj && !old_obj)
13989 return;
13990
13991 if (old_obj && (plane->type != DRM_PLANE_TYPE_CURSOR ||
13992 !INTEL_INFO(dev)->cursor_needs_physical))
13993 intel_unpin_fb_obj(old_state->fb, old_state);
13994
13995 /* prepare_fb aborted? */
13996 if ((old_obj && (old_obj->frontbuffer_bits & intel_plane->frontbuffer_bit)) ||
13997 (obj && !(obj->frontbuffer_bits & intel_plane->frontbuffer_bit)))
13998 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
13999
14000 i915_gem_request_assign(&old_intel_state->wait_req, NULL);
14001
14002 }
14003
14004 int
14005 skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
14006 {
14007 int max_scale;
14008 struct drm_device *dev;
14009 struct drm_i915_private *dev_priv;
14010 int crtc_clock, cdclk;
14011
14012 if (!intel_crtc || !crtc_state->base.enable)
14013 return DRM_PLANE_HELPER_NO_SCALING;
14014
14015 dev = intel_crtc->base.dev;
14016 dev_priv = dev->dev_private;
14017 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
14018 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
14019
14020 if (WARN_ON_ONCE(!crtc_clock || cdclk < crtc_clock))
14021 return DRM_PLANE_HELPER_NO_SCALING;
14022
14023 /*
14024 * skl max scale is lower of:
14025 * close to 3 but not 3, -1 is for that purpose
14026 * or
14027 * cdclk/crtc_clock
14028 */
14029 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
14030
14031 return max_scale;
14032 }
14033
14034 static int
14035 intel_check_primary_plane(struct drm_plane *plane,
14036 struct intel_crtc_state *crtc_state,
14037 struct intel_plane_state *state)
14038 {
14039 struct drm_crtc *crtc = state->base.crtc;
14040 struct drm_framebuffer *fb = state->base.fb;
14041 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
14042 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
14043 bool can_position = false;
14044
14045 /* use scaler when colorkey is not required */
14046 if (INTEL_INFO(plane->dev)->gen >= 9 &&
14047 state->ckey.flags == I915_SET_COLORKEY_NONE) {
14048 min_scale = 1;
14049 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
14050 can_position = true;
14051 }
14052
14053 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14054 &state->dst, &state->clip,
14055 min_scale, max_scale,
14056 can_position, true,
14057 &state->visible);
14058 }
14059
14060 static void intel_begin_crtc_commit(struct drm_crtc *crtc,
14061 struct drm_crtc_state *old_crtc_state)
14062 {
14063 struct drm_device *dev = crtc->dev;
14064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14065 struct intel_crtc_state *old_intel_state =
14066 to_intel_crtc_state(old_crtc_state);
14067 bool modeset = needs_modeset(crtc->state);
14068
14069 /* Perform vblank evasion around commit operation */
14070 intel_pipe_update_start(intel_crtc);
14071
14072 if (modeset)
14073 return;
14074
14075 if (to_intel_crtc_state(crtc->state)->update_pipe)
14076 intel_update_pipe_config(intel_crtc, old_intel_state);
14077 else if (INTEL_INFO(dev)->gen >= 9)
14078 skl_detach_scalers(intel_crtc);
14079 }
14080
14081 static void intel_finish_crtc_commit(struct drm_crtc *crtc,
14082 struct drm_crtc_state *old_crtc_state)
14083 {
14084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14085
14086 intel_pipe_update_end(intel_crtc);
14087 }
14088
14089 /**
14090 * intel_plane_destroy - destroy a plane
14091 * @plane: plane to destroy
14092 *
14093 * Common destruction function for all types of planes (primary, cursor,
14094 * sprite).
14095 */
14096 void intel_plane_destroy(struct drm_plane *plane)
14097 {
14098 struct intel_plane *intel_plane = to_intel_plane(plane);
14099 drm_plane_cleanup(plane);
14100 kfree(intel_plane);
14101 }
14102
14103 const struct drm_plane_funcs intel_plane_funcs = {
14104 .update_plane = drm_atomic_helper_update_plane,
14105 .disable_plane = drm_atomic_helper_disable_plane,
14106 .destroy = intel_plane_destroy,
14107 .set_property = drm_atomic_helper_plane_set_property,
14108 .atomic_get_property = intel_plane_atomic_get_property,
14109 .atomic_set_property = intel_plane_atomic_set_property,
14110 .atomic_duplicate_state = intel_plane_duplicate_state,
14111 .atomic_destroy_state = intel_plane_destroy_state,
14112
14113 };
14114
14115 static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
14116 int pipe)
14117 {
14118 struct intel_plane *primary;
14119 struct intel_plane_state *state;
14120 const uint32_t *intel_primary_formats;
14121 unsigned int num_formats;
14122
14123 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
14124 if (primary == NULL)
14125 return NULL;
14126
14127 state = intel_create_plane_state(&primary->base);
14128 if (!state) {
14129 kfree(primary);
14130 return NULL;
14131 }
14132 primary->base.state = &state->base;
14133
14134 primary->can_scale = false;
14135 primary->max_downscale = 1;
14136 if (INTEL_INFO(dev)->gen >= 9) {
14137 primary->can_scale = true;
14138 state->scaler_id = -1;
14139 }
14140 primary->pipe = pipe;
14141 primary->plane = pipe;
14142 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
14143 primary->check_plane = intel_check_primary_plane;
14144 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
14145 primary->plane = !pipe;
14146
14147 if (INTEL_INFO(dev)->gen >= 9) {
14148 intel_primary_formats = skl_primary_formats;
14149 num_formats = ARRAY_SIZE(skl_primary_formats);
14150
14151 primary->update_plane = skylake_update_primary_plane;
14152 primary->disable_plane = skylake_disable_primary_plane;
14153 } else if (HAS_PCH_SPLIT(dev)) {
14154 intel_primary_formats = i965_primary_formats;
14155 num_formats = ARRAY_SIZE(i965_primary_formats);
14156
14157 primary->update_plane = ironlake_update_primary_plane;
14158 primary->disable_plane = i9xx_disable_primary_plane;
14159 } else if (INTEL_INFO(dev)->gen >= 4) {
14160 intel_primary_formats = i965_primary_formats;
14161 num_formats = ARRAY_SIZE(i965_primary_formats);
14162
14163 primary->update_plane = i9xx_update_primary_plane;
14164 primary->disable_plane = i9xx_disable_primary_plane;
14165 } else {
14166 intel_primary_formats = i8xx_primary_formats;
14167 num_formats = ARRAY_SIZE(i8xx_primary_formats);
14168
14169 primary->update_plane = i9xx_update_primary_plane;
14170 primary->disable_plane = i9xx_disable_primary_plane;
14171 }
14172
14173 drm_universal_plane_init(dev, &primary->base, 0,
14174 &intel_plane_funcs,
14175 intel_primary_formats, num_formats,
14176 DRM_PLANE_TYPE_PRIMARY);
14177
14178 if (INTEL_INFO(dev)->gen >= 4)
14179 intel_create_rotation_property(dev, primary);
14180
14181 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
14182
14183 return &primary->base;
14184 }
14185
14186 void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
14187 {
14188 if (!dev->mode_config.rotation_property) {
14189 unsigned long flags = BIT(DRM_ROTATE_0) |
14190 BIT(DRM_ROTATE_180);
14191
14192 if (INTEL_INFO(dev)->gen >= 9)
14193 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
14194
14195 dev->mode_config.rotation_property =
14196 drm_mode_create_rotation_property(dev, flags);
14197 }
14198 if (dev->mode_config.rotation_property)
14199 drm_object_attach_property(&plane->base.base,
14200 dev->mode_config.rotation_property,
14201 plane->base.state->rotation);
14202 }
14203
14204 static int
14205 intel_check_cursor_plane(struct drm_plane *plane,
14206 struct intel_crtc_state *crtc_state,
14207 struct intel_plane_state *state)
14208 {
14209 struct drm_crtc *crtc = crtc_state->base.crtc;
14210 struct drm_framebuffer *fb = state->base.fb;
14211 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
14212 enum pipe pipe = to_intel_plane(plane)->pipe;
14213 unsigned stride;
14214 int ret;
14215
14216 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
14217 &state->dst, &state->clip,
14218 DRM_PLANE_HELPER_NO_SCALING,
14219 DRM_PLANE_HELPER_NO_SCALING,
14220 true, true, &state->visible);
14221 if (ret)
14222 return ret;
14223
14224 /* if we want to turn off the cursor ignore width and height */
14225 if (!obj)
14226 return 0;
14227
14228 /* Check for which cursor types we support */
14229 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
14230 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
14231 state->base.crtc_w, state->base.crtc_h);
14232 return -EINVAL;
14233 }
14234
14235 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14236 if (obj->base.size < stride * state->base.crtc_h) {
14237 DRM_DEBUG_KMS("buffer is too small\n");
14238 return -ENOMEM;
14239 }
14240
14241 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
14242 DRM_DEBUG_KMS("cursor cannot be tiled\n");
14243 return -EINVAL;
14244 }
14245
14246 /*
14247 * There's something wrong with the cursor on CHV pipe C.
14248 * If it straddles the left edge of the screen then
14249 * moving it away from the edge or disabling it often
14250 * results in a pipe underrun, and often that can lead to
14251 * dead pipe (constant underrun reported, and it scans
14252 * out just a solid color). To recover from that, the
14253 * display power well must be turned off and on again.
14254 * Refuse the put the cursor into that compromised position.
14255 */
14256 if (IS_CHERRYVIEW(plane->dev) && pipe == PIPE_C &&
14257 state->visible && state->base.crtc_x < 0) {
14258 DRM_DEBUG_KMS("CHV cursor C not allowed to straddle the left screen edge\n");
14259 return -EINVAL;
14260 }
14261
14262 return 0;
14263 }
14264
14265 static void
14266 intel_disable_cursor_plane(struct drm_plane *plane,
14267 struct drm_crtc *crtc)
14268 {
14269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14270
14271 intel_crtc->cursor_addr = 0;
14272 intel_crtc_update_cursor(crtc, NULL);
14273 }
14274
14275 static void
14276 intel_update_cursor_plane(struct drm_plane *plane,
14277 const struct intel_crtc_state *crtc_state,
14278 const struct intel_plane_state *state)
14279 {
14280 struct drm_crtc *crtc = crtc_state->base.crtc;
14281 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
14282 struct drm_device *dev = plane->dev;
14283 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
14284 uint32_t addr;
14285
14286 if (!obj)
14287 addr = 0;
14288 else if (!INTEL_INFO(dev)->cursor_needs_physical)
14289 addr = i915_gem_obj_ggtt_offset(obj);
14290 else
14291 addr = obj->phys_handle->busaddr;
14292
14293 intel_crtc->cursor_addr = addr;
14294 intel_crtc_update_cursor(crtc, state);
14295 }
14296
14297 static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14298 int pipe)
14299 {
14300 struct intel_plane *cursor;
14301 struct intel_plane_state *state;
14302
14303 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14304 if (cursor == NULL)
14305 return NULL;
14306
14307 state = intel_create_plane_state(&cursor->base);
14308 if (!state) {
14309 kfree(cursor);
14310 return NULL;
14311 }
14312 cursor->base.state = &state->base;
14313
14314 cursor->can_scale = false;
14315 cursor->max_downscale = 1;
14316 cursor->pipe = pipe;
14317 cursor->plane = pipe;
14318 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
14319 cursor->check_plane = intel_check_cursor_plane;
14320 cursor->update_plane = intel_update_cursor_plane;
14321 cursor->disable_plane = intel_disable_cursor_plane;
14322
14323 drm_universal_plane_init(dev, &cursor->base, 0,
14324 &intel_plane_funcs,
14325 intel_cursor_formats,
14326 ARRAY_SIZE(intel_cursor_formats),
14327 DRM_PLANE_TYPE_CURSOR);
14328
14329 if (INTEL_INFO(dev)->gen >= 4) {
14330 if (!dev->mode_config.rotation_property)
14331 dev->mode_config.rotation_property =
14332 drm_mode_create_rotation_property(dev,
14333 BIT(DRM_ROTATE_0) |
14334 BIT(DRM_ROTATE_180));
14335 if (dev->mode_config.rotation_property)
14336 drm_object_attach_property(&cursor->base.base,
14337 dev->mode_config.rotation_property,
14338 state->base.rotation);
14339 }
14340
14341 if (INTEL_INFO(dev)->gen >=9)
14342 state->scaler_id = -1;
14343
14344 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14345
14346 return &cursor->base;
14347 }
14348
14349 static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14350 struct intel_crtc_state *crtc_state)
14351 {
14352 int i;
14353 struct intel_scaler *intel_scaler;
14354 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14355
14356 for (i = 0; i < intel_crtc->num_scalers; i++) {
14357 intel_scaler = &scaler_state->scalers[i];
14358 intel_scaler->in_use = 0;
14359 intel_scaler->mode = PS_SCALER_MODE_DYN;
14360 }
14361
14362 scaler_state->scaler_id = -1;
14363 }
14364
14365 static void intel_crtc_init(struct drm_device *dev, int pipe)
14366 {
14367 struct drm_i915_private *dev_priv = dev->dev_private;
14368 struct intel_crtc *intel_crtc;
14369 struct intel_crtc_state *crtc_state = NULL;
14370 struct drm_plane *primary = NULL;
14371 struct drm_plane *cursor = NULL;
14372 int i, ret;
14373
14374 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
14375 if (intel_crtc == NULL)
14376 return;
14377
14378 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14379 if (!crtc_state)
14380 goto fail;
14381 intel_crtc->config = crtc_state;
14382 intel_crtc->base.state = &crtc_state->base;
14383 crtc_state->base.crtc = &intel_crtc->base;
14384
14385 /* initialize shared scalers */
14386 if (INTEL_INFO(dev)->gen >= 9) {
14387 if (pipe == PIPE_C)
14388 intel_crtc->num_scalers = 1;
14389 else
14390 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14391
14392 skl_init_scalers(dev, intel_crtc, crtc_state);
14393 }
14394
14395 primary = intel_primary_plane_create(dev, pipe);
14396 if (!primary)
14397 goto fail;
14398
14399 cursor = intel_cursor_plane_create(dev, pipe);
14400 if (!cursor)
14401 goto fail;
14402
14403 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
14404 cursor, &intel_crtc_funcs);
14405 if (ret)
14406 goto fail;
14407
14408 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
14409 for (i = 0; i < 256; i++) {
14410 intel_crtc->lut_r[i] = i;
14411 intel_crtc->lut_g[i] = i;
14412 intel_crtc->lut_b[i] = i;
14413 }
14414
14415 /*
14416 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
14417 * is hooked to pipe B. Hence we want plane A feeding pipe B.
14418 */
14419 intel_crtc->pipe = pipe;
14420 intel_crtc->plane = pipe;
14421 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
14422 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
14423 intel_crtc->plane = !pipe;
14424 }
14425
14426 intel_crtc->cursor_base = ~0;
14427 intel_crtc->cursor_cntl = ~0;
14428 intel_crtc->cursor_size = ~0;
14429
14430 intel_crtc->wm.cxsr_allowed = true;
14431
14432 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14433 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14434 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14435 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14436
14437 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
14438
14439 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
14440 return;
14441
14442 fail:
14443 if (primary)
14444 drm_plane_cleanup(primary);
14445 if (cursor)
14446 drm_plane_cleanup(cursor);
14447 kfree(crtc_state);
14448 kfree(intel_crtc);
14449 }
14450
14451 enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14452 {
14453 struct drm_encoder *encoder = connector->base.encoder;
14454 struct drm_device *dev = connector->base.dev;
14455
14456 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
14457
14458 if (!encoder || WARN_ON(!encoder->crtc))
14459 return INVALID_PIPE;
14460
14461 return to_intel_crtc(encoder->crtc)->pipe;
14462 }
14463
14464 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
14465 struct drm_file *file)
14466 {
14467 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
14468 struct drm_crtc *drmmode_crtc;
14469 struct intel_crtc *crtc;
14470
14471 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
14472
14473 if (!drmmode_crtc) {
14474 DRM_ERROR("no such CRTC id\n");
14475 return -ENOENT;
14476 }
14477
14478 crtc = to_intel_crtc(drmmode_crtc);
14479 pipe_from_crtc_id->pipe = crtc->pipe;
14480
14481 return 0;
14482 }
14483
14484 static int intel_encoder_clones(struct intel_encoder *encoder)
14485 {
14486 struct drm_device *dev = encoder->base.dev;
14487 struct intel_encoder *source_encoder;
14488 int index_mask = 0;
14489 int entry = 0;
14490
14491 for_each_intel_encoder(dev, source_encoder) {
14492 if (encoders_cloneable(encoder, source_encoder))
14493 index_mask |= (1 << entry);
14494
14495 entry++;
14496 }
14497
14498 return index_mask;
14499 }
14500
14501 static bool has_edp_a(struct drm_device *dev)
14502 {
14503 struct drm_i915_private *dev_priv = dev->dev_private;
14504
14505 if (!IS_MOBILE(dev))
14506 return false;
14507
14508 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14509 return false;
14510
14511 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
14512 return false;
14513
14514 return true;
14515 }
14516
14517 static bool intel_crt_present(struct drm_device *dev)
14518 {
14519 struct drm_i915_private *dev_priv = dev->dev_private;
14520
14521 if (INTEL_INFO(dev)->gen >= 9)
14522 return false;
14523
14524 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
14525 return false;
14526
14527 if (IS_CHERRYVIEW(dev))
14528 return false;
14529
14530 if (HAS_PCH_LPT_H(dev) && I915_READ(SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
14531 return false;
14532
14533 /* DDI E can't be used if DDI A requires 4 lanes */
14534 if (HAS_DDI(dev) && I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
14535 return false;
14536
14537 if (!dev_priv->vbt.int_crt_support)
14538 return false;
14539
14540 return true;
14541 }
14542
14543 static void intel_setup_outputs(struct drm_device *dev)
14544 {
14545 struct drm_i915_private *dev_priv = dev->dev_private;
14546 struct intel_encoder *encoder;
14547 bool dpd_is_edp = false;
14548
14549 intel_lvds_init(dev);
14550
14551 if (intel_crt_present(dev))
14552 intel_crt_init(dev);
14553
14554 if (IS_BROXTON(dev)) {
14555 /*
14556 * FIXME: Broxton doesn't support port detection via the
14557 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14558 * detect the ports.
14559 */
14560 intel_ddi_init(dev, PORT_A);
14561 intel_ddi_init(dev, PORT_B);
14562 intel_ddi_init(dev, PORT_C);
14563 } else if (HAS_DDI(dev)) {
14564 int found;
14565
14566 /*
14567 * Haswell uses DDI functions to detect digital outputs.
14568 * On SKL pre-D0 the strap isn't connected, so we assume
14569 * it's there.
14570 */
14571 found = I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
14572 /* WaIgnoreDDIAStrap: skl */
14573 if (found || IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
14574 intel_ddi_init(dev, PORT_A);
14575
14576 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14577 * register */
14578 found = I915_READ(SFUSE_STRAP);
14579
14580 if (found & SFUSE_STRAP_DDIB_DETECTED)
14581 intel_ddi_init(dev, PORT_B);
14582 if (found & SFUSE_STRAP_DDIC_DETECTED)
14583 intel_ddi_init(dev, PORT_C);
14584 if (found & SFUSE_STRAP_DDID_DETECTED)
14585 intel_ddi_init(dev, PORT_D);
14586 /*
14587 * On SKL we don't have a way to detect DDI-E so we rely on VBT.
14588 */
14589 if ((IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) &&
14590 (dev_priv->vbt.ddi_port_info[PORT_E].supports_dp ||
14591 dev_priv->vbt.ddi_port_info[PORT_E].supports_dvi ||
14592 dev_priv->vbt.ddi_port_info[PORT_E].supports_hdmi))
14593 intel_ddi_init(dev, PORT_E);
14594
14595 } else if (HAS_PCH_SPLIT(dev)) {
14596 int found;
14597 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
14598
14599 if (has_edp_a(dev))
14600 intel_dp_init(dev, DP_A, PORT_A);
14601
14602 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
14603 /* PCH SDVOB multiplex with HDMIB */
14604 found = intel_sdvo_init(dev, PCH_SDVOB, PORT_B);
14605 if (!found)
14606 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
14607 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
14608 intel_dp_init(dev, PCH_DP_B, PORT_B);
14609 }
14610
14611 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
14612 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
14613
14614 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
14615 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
14616
14617 if (I915_READ(PCH_DP_C) & DP_DETECTED)
14618 intel_dp_init(dev, PCH_DP_C, PORT_C);
14619
14620 if (I915_READ(PCH_DP_D) & DP_DETECTED)
14621 intel_dp_init(dev, PCH_DP_D, PORT_D);
14622 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
14623 /*
14624 * The DP_DETECTED bit is the latched state of the DDC
14625 * SDA pin at boot. However since eDP doesn't require DDC
14626 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14627 * eDP ports may have been muxed to an alternate function.
14628 * Thus we can't rely on the DP_DETECTED bit alone to detect
14629 * eDP ports. Consult the VBT as well as DP_DETECTED to
14630 * detect eDP ports.
14631 */
14632 if (I915_READ(VLV_HDMIB) & SDVO_DETECTED &&
14633 !intel_dp_is_edp(dev, PORT_B))
14634 intel_hdmi_init(dev, VLV_HDMIB, PORT_B);
14635 if (I915_READ(VLV_DP_B) & DP_DETECTED ||
14636 intel_dp_is_edp(dev, PORT_B))
14637 intel_dp_init(dev, VLV_DP_B, PORT_B);
14638
14639 if (I915_READ(VLV_HDMIC) & SDVO_DETECTED &&
14640 !intel_dp_is_edp(dev, PORT_C))
14641 intel_hdmi_init(dev, VLV_HDMIC, PORT_C);
14642 if (I915_READ(VLV_DP_C) & DP_DETECTED ||
14643 intel_dp_is_edp(dev, PORT_C))
14644 intel_dp_init(dev, VLV_DP_C, PORT_C);
14645
14646 if (IS_CHERRYVIEW(dev)) {
14647 /* eDP not supported on port D, so don't check VBT */
14648 if (I915_READ(CHV_HDMID) & SDVO_DETECTED)
14649 intel_hdmi_init(dev, CHV_HDMID, PORT_D);
14650 if (I915_READ(CHV_DP_D) & DP_DETECTED)
14651 intel_dp_init(dev, CHV_DP_D, PORT_D);
14652 }
14653
14654 intel_dsi_init(dev);
14655 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
14656 bool found = false;
14657
14658 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14659 DRM_DEBUG_KMS("probing SDVOB\n");
14660 found = intel_sdvo_init(dev, GEN3_SDVOB, PORT_B);
14661 if (!found && IS_G4X(dev)) {
14662 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
14663 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
14664 }
14665
14666 if (!found && IS_G4X(dev))
14667 intel_dp_init(dev, DP_B, PORT_B);
14668 }
14669
14670 /* Before G4X SDVOC doesn't have its own detect register */
14671
14672 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
14673 DRM_DEBUG_KMS("probing SDVOC\n");
14674 found = intel_sdvo_init(dev, GEN3_SDVOC, PORT_C);
14675 }
14676
14677 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
14678
14679 if (IS_G4X(dev)) {
14680 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
14681 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
14682 }
14683 if (IS_G4X(dev))
14684 intel_dp_init(dev, DP_C, PORT_C);
14685 }
14686
14687 if (IS_G4X(dev) &&
14688 (I915_READ(DP_D) & DP_DETECTED))
14689 intel_dp_init(dev, DP_D, PORT_D);
14690 } else if (IS_GEN2(dev))
14691 intel_dvo_init(dev);
14692
14693 if (SUPPORTS_TV(dev))
14694 intel_tv_init(dev);
14695
14696 intel_psr_init(dev);
14697
14698 for_each_intel_encoder(dev, encoder) {
14699 encoder->base.possible_crtcs = encoder->crtc_mask;
14700 encoder->base.possible_clones =
14701 intel_encoder_clones(encoder);
14702 }
14703
14704 intel_init_pch_refclk(dev);
14705
14706 drm_helper_move_panel_connectors_to_head(dev);
14707 }
14708
14709 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14710 {
14711 struct drm_device *dev = fb->dev;
14712 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14713
14714 drm_framebuffer_cleanup(fb);
14715 mutex_lock(&dev->struct_mutex);
14716 WARN_ON(!intel_fb->obj->framebuffer_references--);
14717 drm_gem_object_unreference(&intel_fb->obj->base);
14718 mutex_unlock(&dev->struct_mutex);
14719 kfree(intel_fb);
14720 }
14721
14722 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
14723 struct drm_file *file,
14724 unsigned int *handle)
14725 {
14726 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14727 struct drm_i915_gem_object *obj = intel_fb->obj;
14728
14729 if (obj->userptr.mm) {
14730 DRM_DEBUG("attempting to use a userptr for a framebuffer, denied\n");
14731 return -EINVAL;
14732 }
14733
14734 return drm_gem_handle_create(file, &obj->base, handle);
14735 }
14736
14737 static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14738 struct drm_file *file,
14739 unsigned flags, unsigned color,
14740 struct drm_clip_rect *clips,
14741 unsigned num_clips)
14742 {
14743 struct drm_device *dev = fb->dev;
14744 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14745 struct drm_i915_gem_object *obj = intel_fb->obj;
14746
14747 mutex_lock(&dev->struct_mutex);
14748 intel_fb_obj_flush(obj, false, ORIGIN_DIRTYFB);
14749 mutex_unlock(&dev->struct_mutex);
14750
14751 return 0;
14752 }
14753
14754 static const struct drm_framebuffer_funcs intel_fb_funcs = {
14755 .destroy = intel_user_framebuffer_destroy,
14756 .create_handle = intel_user_framebuffer_create_handle,
14757 .dirty = intel_user_framebuffer_dirty,
14758 };
14759
14760 static
14761 u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14762 uint32_t pixel_format)
14763 {
14764 u32 gen = INTEL_INFO(dev)->gen;
14765
14766 if (gen >= 9) {
14767 /* "The stride in bytes must not exceed the of the size of 8K
14768 * pixels and 32K bytes."
14769 */
14770 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14771 } else if (gen >= 5 && !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14772 return 32*1024;
14773 } else if (gen >= 4) {
14774 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14775 return 16*1024;
14776 else
14777 return 32*1024;
14778 } else if (gen >= 3) {
14779 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14780 return 8*1024;
14781 else
14782 return 16*1024;
14783 } else {
14784 /* XXX DSPC is limited to 4k tiled */
14785 return 8*1024;
14786 }
14787 }
14788
14789 static int intel_framebuffer_init(struct drm_device *dev,
14790 struct intel_framebuffer *intel_fb,
14791 struct drm_mode_fb_cmd2 *mode_cmd,
14792 struct drm_i915_gem_object *obj)
14793 {
14794 struct drm_i915_private *dev_priv = to_i915(dev);
14795 unsigned int aligned_height;
14796 int ret;
14797 u32 pitch_limit, stride_alignment;
14798
14799 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14800
14801 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14802 /* Enforce that fb modifier and tiling mode match, but only for
14803 * X-tiled. This is needed for FBC. */
14804 if (!!(obj->tiling_mode == I915_TILING_X) !=
14805 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14806 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14807 return -EINVAL;
14808 }
14809 } else {
14810 if (obj->tiling_mode == I915_TILING_X)
14811 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14812 else if (obj->tiling_mode == I915_TILING_Y) {
14813 DRM_DEBUG("No Y tiling for legacy addfb\n");
14814 return -EINVAL;
14815 }
14816 }
14817
14818 /* Passed in modifier sanity checking. */
14819 switch (mode_cmd->modifier[0]) {
14820 case I915_FORMAT_MOD_Y_TILED:
14821 case I915_FORMAT_MOD_Yf_TILED:
14822 if (INTEL_INFO(dev)->gen < 9) {
14823 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14824 mode_cmd->modifier[0]);
14825 return -EINVAL;
14826 }
14827 case DRM_FORMAT_MOD_NONE:
14828 case I915_FORMAT_MOD_X_TILED:
14829 break;
14830 default:
14831 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14832 mode_cmd->modifier[0]);
14833 return -EINVAL;
14834 }
14835
14836 stride_alignment = intel_fb_stride_alignment(dev_priv,
14837 mode_cmd->modifier[0],
14838 mode_cmd->pixel_format);
14839 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14840 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14841 mode_cmd->pitches[0], stride_alignment);
14842 return -EINVAL;
14843 }
14844
14845 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14846 mode_cmd->pixel_format);
14847 if (mode_cmd->pitches[0] > pitch_limit) {
14848 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14849 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
14850 "tiled" : "linear",
14851 mode_cmd->pitches[0], pitch_limit);
14852 return -EINVAL;
14853 }
14854
14855 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
14856 mode_cmd->pitches[0] != obj->stride) {
14857 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14858 mode_cmd->pitches[0], obj->stride);
14859 return -EINVAL;
14860 }
14861
14862 /* Reject formats not supported by any plane early. */
14863 switch (mode_cmd->pixel_format) {
14864 case DRM_FORMAT_C8:
14865 case DRM_FORMAT_RGB565:
14866 case DRM_FORMAT_XRGB8888:
14867 case DRM_FORMAT_ARGB8888:
14868 break;
14869 case DRM_FORMAT_XRGB1555:
14870 if (INTEL_INFO(dev)->gen > 3) {
14871 DRM_DEBUG("unsupported pixel format: %s\n",
14872 drm_get_format_name(mode_cmd->pixel_format));
14873 return -EINVAL;
14874 }
14875 break;
14876 case DRM_FORMAT_ABGR8888:
14877 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) &&
14878 INTEL_INFO(dev)->gen < 9) {
14879 DRM_DEBUG("unsupported pixel format: %s\n",
14880 drm_get_format_name(mode_cmd->pixel_format));
14881 return -EINVAL;
14882 }
14883 break;
14884 case DRM_FORMAT_XBGR8888:
14885 case DRM_FORMAT_XRGB2101010:
14886 case DRM_FORMAT_XBGR2101010:
14887 if (INTEL_INFO(dev)->gen < 4) {
14888 DRM_DEBUG("unsupported pixel format: %s\n",
14889 drm_get_format_name(mode_cmd->pixel_format));
14890 return -EINVAL;
14891 }
14892 break;
14893 case DRM_FORMAT_ABGR2101010:
14894 if (!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) {
14895 DRM_DEBUG("unsupported pixel format: %s\n",
14896 drm_get_format_name(mode_cmd->pixel_format));
14897 return -EINVAL;
14898 }
14899 break;
14900 case DRM_FORMAT_YUYV:
14901 case DRM_FORMAT_UYVY:
14902 case DRM_FORMAT_YVYU:
14903 case DRM_FORMAT_VYUY:
14904 if (INTEL_INFO(dev)->gen < 5) {
14905 DRM_DEBUG("unsupported pixel format: %s\n",
14906 drm_get_format_name(mode_cmd->pixel_format));
14907 return -EINVAL;
14908 }
14909 break;
14910 default:
14911 DRM_DEBUG("unsupported pixel format: %s\n",
14912 drm_get_format_name(mode_cmd->pixel_format));
14913 return -EINVAL;
14914 }
14915
14916 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14917 if (mode_cmd->offsets[0] != 0)
14918 return -EINVAL;
14919
14920 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
14921 mode_cmd->pixel_format,
14922 mode_cmd->modifier[0]);
14923 /* FIXME drm helper for size checks (especially planar formats)? */
14924 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14925 return -EINVAL;
14926
14927 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14928 intel_fb->obj = obj;
14929 intel_fb->obj->framebuffer_references++;
14930
14931 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14932 if (ret) {
14933 DRM_ERROR("framebuffer init failed %d\n", ret);
14934 return ret;
14935 }
14936
14937 return 0;
14938 }
14939
14940 static struct drm_framebuffer *
14941 intel_user_framebuffer_create(struct drm_device *dev,
14942 struct drm_file *filp,
14943 const struct drm_mode_fb_cmd2 *user_mode_cmd)
14944 {
14945 struct drm_framebuffer *fb;
14946 struct drm_i915_gem_object *obj;
14947 struct drm_mode_fb_cmd2 mode_cmd = *user_mode_cmd;
14948
14949 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14950 mode_cmd.handles[0]));
14951 if (&obj->base == NULL)
14952 return ERR_PTR(-ENOENT);
14953
14954 fb = intel_framebuffer_create(dev, &mode_cmd, obj);
14955 if (IS_ERR(fb))
14956 drm_gem_object_unreference_unlocked(&obj->base);
14957
14958 return fb;
14959 }
14960
14961 #ifndef CONFIG_DRM_FBDEV_EMULATION
14962 static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
14963 {
14964 }
14965 #endif
14966
14967 static const struct drm_mode_config_funcs intel_mode_funcs = {
14968 .fb_create = intel_user_framebuffer_create,
14969 .output_poll_changed = intel_fbdev_output_poll_changed,
14970 .atomic_check = intel_atomic_check,
14971 .atomic_commit = intel_atomic_commit,
14972 .atomic_state_alloc = intel_atomic_state_alloc,
14973 .atomic_state_clear = intel_atomic_state_clear,
14974 };
14975
14976 /* Set up chip specific display functions */
14977 static void intel_init_display(struct drm_device *dev)
14978 {
14979 struct drm_i915_private *dev_priv = dev->dev_private;
14980
14981 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14982 dev_priv->display.find_dpll = g4x_find_best_dpll;
14983 else if (IS_CHERRYVIEW(dev))
14984 dev_priv->display.find_dpll = chv_find_best_dpll;
14985 else if (IS_VALLEYVIEW(dev))
14986 dev_priv->display.find_dpll = vlv_find_best_dpll;
14987 else if (IS_PINEVIEW(dev))
14988 dev_priv->display.find_dpll = pnv_find_best_dpll;
14989 else
14990 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14991
14992 if (INTEL_INFO(dev)->gen >= 9) {
14993 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
14994 dev_priv->display.get_initial_plane_config =
14995 skylake_get_initial_plane_config;
14996 dev_priv->display.crtc_compute_clock =
14997 haswell_crtc_compute_clock;
14998 dev_priv->display.crtc_enable = haswell_crtc_enable;
14999 dev_priv->display.crtc_disable = haswell_crtc_disable;
15000 } else if (HAS_DDI(dev)) {
15001 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
15002 dev_priv->display.get_initial_plane_config =
15003 ironlake_get_initial_plane_config;
15004 dev_priv->display.crtc_compute_clock =
15005 haswell_crtc_compute_clock;
15006 dev_priv->display.crtc_enable = haswell_crtc_enable;
15007 dev_priv->display.crtc_disable = haswell_crtc_disable;
15008 } else if (HAS_PCH_SPLIT(dev)) {
15009 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
15010 dev_priv->display.get_initial_plane_config =
15011 ironlake_get_initial_plane_config;
15012 dev_priv->display.crtc_compute_clock =
15013 ironlake_crtc_compute_clock;
15014 dev_priv->display.crtc_enable = ironlake_crtc_enable;
15015 dev_priv->display.crtc_disable = ironlake_crtc_disable;
15016 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15017 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15018 dev_priv->display.get_initial_plane_config =
15019 i9xx_get_initial_plane_config;
15020 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15021 dev_priv->display.crtc_enable = valleyview_crtc_enable;
15022 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15023 } else {
15024 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
15025 dev_priv->display.get_initial_plane_config =
15026 i9xx_get_initial_plane_config;
15027 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
15028 dev_priv->display.crtc_enable = i9xx_crtc_enable;
15029 dev_priv->display.crtc_disable = i9xx_crtc_disable;
15030 }
15031
15032 /* Returns the core display clock speed */
15033 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
15034 dev_priv->display.get_display_clock_speed =
15035 skylake_get_display_clock_speed;
15036 else if (IS_BROXTON(dev))
15037 dev_priv->display.get_display_clock_speed =
15038 broxton_get_display_clock_speed;
15039 else if (IS_BROADWELL(dev))
15040 dev_priv->display.get_display_clock_speed =
15041 broadwell_get_display_clock_speed;
15042 else if (IS_HASWELL(dev))
15043 dev_priv->display.get_display_clock_speed =
15044 haswell_get_display_clock_speed;
15045 else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15046 dev_priv->display.get_display_clock_speed =
15047 valleyview_get_display_clock_speed;
15048 else if (IS_GEN5(dev))
15049 dev_priv->display.get_display_clock_speed =
15050 ilk_get_display_clock_speed;
15051 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
15052 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
15053 dev_priv->display.get_display_clock_speed =
15054 i945_get_display_clock_speed;
15055 else if (IS_GM45(dev))
15056 dev_priv->display.get_display_clock_speed =
15057 gm45_get_display_clock_speed;
15058 else if (IS_CRESTLINE(dev))
15059 dev_priv->display.get_display_clock_speed =
15060 i965gm_get_display_clock_speed;
15061 else if (IS_PINEVIEW(dev))
15062 dev_priv->display.get_display_clock_speed =
15063 pnv_get_display_clock_speed;
15064 else if (IS_G33(dev) || IS_G4X(dev))
15065 dev_priv->display.get_display_clock_speed =
15066 g33_get_display_clock_speed;
15067 else if (IS_I915G(dev))
15068 dev_priv->display.get_display_clock_speed =
15069 i915_get_display_clock_speed;
15070 else if (IS_I945GM(dev) || IS_845G(dev))
15071 dev_priv->display.get_display_clock_speed =
15072 i9xx_misc_get_display_clock_speed;
15073 else if (IS_I915GM(dev))
15074 dev_priv->display.get_display_clock_speed =
15075 i915gm_get_display_clock_speed;
15076 else if (IS_I865G(dev))
15077 dev_priv->display.get_display_clock_speed =
15078 i865_get_display_clock_speed;
15079 else if (IS_I85X(dev))
15080 dev_priv->display.get_display_clock_speed =
15081 i85x_get_display_clock_speed;
15082 else { /* 830 */
15083 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
15084 dev_priv->display.get_display_clock_speed =
15085 i830_get_display_clock_speed;
15086 }
15087
15088 if (IS_GEN5(dev)) {
15089 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
15090 } else if (IS_GEN6(dev)) {
15091 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
15092 } else if (IS_IVYBRIDGE(dev)) {
15093 /* FIXME: detect B0+ stepping and use auto training */
15094 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
15095 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
15096 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
15097 if (IS_BROADWELL(dev)) {
15098 dev_priv->display.modeset_commit_cdclk =
15099 broadwell_modeset_commit_cdclk;
15100 dev_priv->display.modeset_calc_cdclk =
15101 broadwell_modeset_calc_cdclk;
15102 }
15103 } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
15104 dev_priv->display.modeset_commit_cdclk =
15105 valleyview_modeset_commit_cdclk;
15106 dev_priv->display.modeset_calc_cdclk =
15107 valleyview_modeset_calc_cdclk;
15108 } else if (IS_BROXTON(dev)) {
15109 dev_priv->display.modeset_commit_cdclk =
15110 broxton_modeset_commit_cdclk;
15111 dev_priv->display.modeset_calc_cdclk =
15112 broxton_modeset_calc_cdclk;
15113 }
15114
15115 switch (INTEL_INFO(dev)->gen) {
15116 case 2:
15117 dev_priv->display.queue_flip = intel_gen2_queue_flip;
15118 break;
15119
15120 case 3:
15121 dev_priv->display.queue_flip = intel_gen3_queue_flip;
15122 break;
15123
15124 case 4:
15125 case 5:
15126 dev_priv->display.queue_flip = intel_gen4_queue_flip;
15127 break;
15128
15129 case 6:
15130 dev_priv->display.queue_flip = intel_gen6_queue_flip;
15131 break;
15132 case 7:
15133 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
15134 dev_priv->display.queue_flip = intel_gen7_queue_flip;
15135 break;
15136 case 9:
15137 /* Drop through - unsupported since execlist only. */
15138 default:
15139 /* Default just returns -ENODEV to indicate unsupported */
15140 dev_priv->display.queue_flip = intel_default_queue_flip;
15141 }
15142
15143 mutex_init(&dev_priv->pps_mutex);
15144 }
15145
15146 /*
15147 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
15148 * resume, or other times. This quirk makes sure that's the case for
15149 * affected systems.
15150 */
15151 static void quirk_pipea_force(struct drm_device *dev)
15152 {
15153 struct drm_i915_private *dev_priv = dev->dev_private;
15154
15155 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
15156 DRM_INFO("applying pipe a force quirk\n");
15157 }
15158
15159 static void quirk_pipeb_force(struct drm_device *dev)
15160 {
15161 struct drm_i915_private *dev_priv = dev->dev_private;
15162
15163 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
15164 DRM_INFO("applying pipe b force quirk\n");
15165 }
15166
15167 /*
15168 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
15169 */
15170 static void quirk_ssc_force_disable(struct drm_device *dev)
15171 {
15172 struct drm_i915_private *dev_priv = dev->dev_private;
15173 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
15174 DRM_INFO("applying lvds SSC disable quirk\n");
15175 }
15176
15177 /*
15178 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
15179 * brightness value
15180 */
15181 static void quirk_invert_brightness(struct drm_device *dev)
15182 {
15183 struct drm_i915_private *dev_priv = dev->dev_private;
15184 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
15185 DRM_INFO("applying inverted panel brightness quirk\n");
15186 }
15187
15188 /* Some VBT's incorrectly indicate no backlight is present */
15189 static void quirk_backlight_present(struct drm_device *dev)
15190 {
15191 struct drm_i915_private *dev_priv = dev->dev_private;
15192 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
15193 DRM_INFO("applying backlight present quirk\n");
15194 }
15195
15196 struct intel_quirk {
15197 int device;
15198 int subsystem_vendor;
15199 int subsystem_device;
15200 void (*hook)(struct drm_device *dev);
15201 };
15202
15203 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
15204 struct intel_dmi_quirk {
15205 void (*hook)(struct drm_device *dev);
15206 const struct dmi_system_id (*dmi_id_list)[];
15207 };
15208
15209 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
15210 {
15211 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
15212 return 1;
15213 }
15214
15215 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
15216 {
15217 .dmi_id_list = &(const struct dmi_system_id[]) {
15218 {
15219 .callback = intel_dmi_reverse_brightness,
15220 .ident = "NCR Corporation",
15221 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
15222 DMI_MATCH(DMI_PRODUCT_NAME, ""),
15223 },
15224 },
15225 { } /* terminating entry */
15226 },
15227 .hook = quirk_invert_brightness,
15228 },
15229 };
15230
15231 static struct intel_quirk intel_quirks[] = {
15232 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
15233 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
15234
15235 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
15236 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
15237
15238 /* 830 needs to leave pipe A & dpll A up */
15239 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
15240
15241 /* 830 needs to leave pipe B & dpll B up */
15242 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
15243
15244 /* Lenovo U160 cannot use SSC on LVDS */
15245 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
15246
15247 /* Sony Vaio Y cannot use SSC on LVDS */
15248 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
15249
15250 /* Acer Aspire 5734Z must invert backlight brightness */
15251 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
15252
15253 /* Acer/eMachines G725 */
15254 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15255
15256 /* Acer/eMachines e725 */
15257 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15258
15259 /* Acer/Packard Bell NCL20 */
15260 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15261
15262 /* Acer Aspire 4736Z */
15263 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
15264
15265 /* Acer Aspire 5336 */
15266 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
15267
15268 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15269 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
15270
15271 /* Acer C720 Chromebook (Core i3 4005U) */
15272 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15273
15274 /* Apple Macbook 2,1 (Core 2 T7400) */
15275 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15276
15277 /* Apple Macbook 4,1 */
15278 { 0x2a02, 0x106b, 0x00a1, quirk_backlight_present },
15279
15280 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15281 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
15282
15283 /* HP Chromebook 14 (Celeron 2955U) */
15284 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
15285
15286 /* Dell Chromebook 11 */
15287 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
15288
15289 /* Dell Chromebook 11 (2015 version) */
15290 { 0x0a16, 0x1028, 0x0a35, quirk_backlight_present },
15291 };
15292
15293 static void intel_init_quirks(struct drm_device *dev)
15294 {
15295 struct pci_dev *d = dev->pdev;
15296 int i;
15297
15298 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15299 struct intel_quirk *q = &intel_quirks[i];
15300
15301 if (d->device == q->device &&
15302 (d->subsystem_vendor == q->subsystem_vendor ||
15303 q->subsystem_vendor == PCI_ANY_ID) &&
15304 (d->subsystem_device == q->subsystem_device ||
15305 q->subsystem_device == PCI_ANY_ID))
15306 q->hook(dev);
15307 }
15308 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15309 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15310 intel_dmi_quirks[i].hook(dev);
15311 }
15312 }
15313
15314 /* Disable the VGA plane that we never use */
15315 static void i915_disable_vga(struct drm_device *dev)
15316 {
15317 struct drm_i915_private *dev_priv = dev->dev_private;
15318 u8 sr1;
15319 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15320
15321 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
15322 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
15323 outb(SR01, VGA_SR_INDEX);
15324 sr1 = inb(VGA_SR_DATA);
15325 outb(sr1 | 1<<5, VGA_SR_DATA);
15326 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15327 udelay(300);
15328
15329 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
15330 POSTING_READ(vga_reg);
15331 }
15332
15333 void intel_modeset_init_hw(struct drm_device *dev)
15334 {
15335 struct drm_i915_private *dev_priv = dev->dev_private;
15336
15337 intel_update_cdclk(dev);
15338
15339 dev_priv->atomic_cdclk_freq = dev_priv->cdclk_freq;
15340
15341 intel_init_clock_gating(dev);
15342 intel_enable_gt_powersave(dev);
15343 }
15344
15345 /*
15346 * Calculate what we think the watermarks should be for the state we've read
15347 * out of the hardware and then immediately program those watermarks so that
15348 * we ensure the hardware settings match our internal state.
15349 *
15350 * We can calculate what we think WM's should be by creating a duplicate of the
15351 * current state (which was constructed during hardware readout) and running it
15352 * through the atomic check code to calculate new watermark values in the
15353 * state object.
15354 */
15355 static void sanitize_watermarks(struct drm_device *dev)
15356 {
15357 struct drm_i915_private *dev_priv = to_i915(dev);
15358 struct drm_atomic_state *state;
15359 struct drm_crtc *crtc;
15360 struct drm_crtc_state *cstate;
15361 struct drm_modeset_acquire_ctx ctx;
15362 int ret;
15363 int i;
15364
15365 /* Only supported on platforms that use atomic watermark design */
15366 if (!dev_priv->display.optimize_watermarks)
15367 return;
15368
15369 /*
15370 * We need to hold connection_mutex before calling duplicate_state so
15371 * that the connector loop is protected.
15372 */
15373 drm_modeset_acquire_init(&ctx, 0);
15374 retry:
15375 ret = drm_modeset_lock_all_ctx(dev, &ctx);
15376 if (ret == -EDEADLK) {
15377 drm_modeset_backoff(&ctx);
15378 goto retry;
15379 } else if (WARN_ON(ret)) {
15380 goto fail;
15381 }
15382
15383 state = drm_atomic_helper_duplicate_state(dev, &ctx);
15384 if (WARN_ON(IS_ERR(state)))
15385 goto fail;
15386
15387 /*
15388 * Hardware readout is the only time we don't want to calculate
15389 * intermediate watermarks (since we don't trust the current
15390 * watermarks).
15391 */
15392 to_intel_atomic_state(state)->skip_intermediate_wm = true;
15393
15394 ret = intel_atomic_check(dev, state);
15395 if (ret) {
15396 /*
15397 * If we fail here, it means that the hardware appears to be
15398 * programmed in a way that shouldn't be possible, given our
15399 * understanding of watermark requirements. This might mean a
15400 * mistake in the hardware readout code or a mistake in the
15401 * watermark calculations for a given platform. Raise a WARN
15402 * so that this is noticeable.
15403 *
15404 * If this actually happens, we'll have to just leave the
15405 * BIOS-programmed watermarks untouched and hope for the best.
15406 */
15407 WARN(true, "Could not determine valid watermarks for inherited state\n");
15408 goto fail;
15409 }
15410
15411 /* Write calculated watermark values back */
15412 to_i915(dev)->wm.config = to_intel_atomic_state(state)->wm_config;
15413 for_each_crtc_in_state(state, crtc, cstate, i) {
15414 struct intel_crtc_state *cs = to_intel_crtc_state(cstate);
15415
15416 cs->wm.need_postvbl_update = true;
15417 dev_priv->display.optimize_watermarks(cs);
15418 }
15419
15420 drm_atomic_state_free(state);
15421 fail:
15422 drm_modeset_drop_locks(&ctx);
15423 drm_modeset_acquire_fini(&ctx);
15424 }
15425
15426 void intel_modeset_init(struct drm_device *dev)
15427 {
15428 struct drm_i915_private *dev_priv = dev->dev_private;
15429 int sprite, ret;
15430 enum pipe pipe;
15431 struct intel_crtc *crtc;
15432
15433 drm_mode_config_init(dev);
15434
15435 dev->mode_config.min_width = 0;
15436 dev->mode_config.min_height = 0;
15437
15438 dev->mode_config.preferred_depth = 24;
15439 dev->mode_config.prefer_shadow = 1;
15440
15441 dev->mode_config.allow_fb_modifiers = true;
15442
15443 dev->mode_config.funcs = &intel_mode_funcs;
15444
15445 intel_init_quirks(dev);
15446
15447 intel_init_pm(dev);
15448
15449 if (INTEL_INFO(dev)->num_pipes == 0)
15450 return;
15451
15452 /*
15453 * There may be no VBT; and if the BIOS enabled SSC we can
15454 * just keep using it to avoid unnecessary flicker. Whereas if the
15455 * BIOS isn't using it, don't assume it will work even if the VBT
15456 * indicates as much.
15457 */
15458 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
15459 bool bios_lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15460 DREF_SSC1_ENABLE);
15461
15462 if (dev_priv->vbt.lvds_use_ssc != bios_lvds_use_ssc) {
15463 DRM_DEBUG_KMS("SSC %sabled by BIOS, overriding VBT which says %sabled\n",
15464 bios_lvds_use_ssc ? "en" : "dis",
15465 dev_priv->vbt.lvds_use_ssc ? "en" : "dis");
15466 dev_priv->vbt.lvds_use_ssc = bios_lvds_use_ssc;
15467 }
15468 }
15469
15470 intel_init_display(dev);
15471 intel_init_audio(dev);
15472
15473 if (IS_GEN2(dev)) {
15474 dev->mode_config.max_width = 2048;
15475 dev->mode_config.max_height = 2048;
15476 } else if (IS_GEN3(dev)) {
15477 dev->mode_config.max_width = 4096;
15478 dev->mode_config.max_height = 4096;
15479 } else {
15480 dev->mode_config.max_width = 8192;
15481 dev->mode_config.max_height = 8192;
15482 }
15483
15484 if (IS_845G(dev) || IS_I865G(dev)) {
15485 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15486 dev->mode_config.cursor_height = 1023;
15487 } else if (IS_GEN2(dev)) {
15488 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15489 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15490 } else {
15491 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15492 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15493 }
15494
15495 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
15496
15497 DRM_DEBUG_KMS("%d display pipe%s available.\n",
15498 INTEL_INFO(dev)->num_pipes,
15499 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
15500
15501 for_each_pipe(dev_priv, pipe) {
15502 intel_crtc_init(dev, pipe);
15503 for_each_sprite(dev_priv, pipe, sprite) {
15504 ret = intel_plane_init(dev, pipe, sprite);
15505 if (ret)
15506 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
15507 pipe_name(pipe), sprite_name(pipe, sprite), ret);
15508 }
15509 }
15510
15511 intel_update_czclk(dev_priv);
15512 intel_update_cdclk(dev);
15513
15514 intel_shared_dpll_init(dev);
15515
15516 /* Just disable it once at startup */
15517 i915_disable_vga(dev);
15518 intel_setup_outputs(dev);
15519
15520 drm_modeset_lock_all(dev);
15521 intel_modeset_setup_hw_state(dev);
15522 drm_modeset_unlock_all(dev);
15523
15524 for_each_intel_crtc(dev, crtc) {
15525 struct intel_initial_plane_config plane_config = {};
15526
15527 if (!crtc->active)
15528 continue;
15529
15530 /*
15531 * Note that reserving the BIOS fb up front prevents us
15532 * from stuffing other stolen allocations like the ring
15533 * on top. This prevents some ugliness at boot time, and
15534 * can even allow for smooth boot transitions if the BIOS
15535 * fb is large enough for the active pipe configuration.
15536 */
15537 dev_priv->display.get_initial_plane_config(crtc,
15538 &plane_config);
15539
15540 /*
15541 * If the fb is shared between multiple heads, we'll
15542 * just get the first one.
15543 */
15544 intel_find_initial_plane_obj(crtc, &plane_config);
15545 }
15546
15547 /*
15548 * Make sure hardware watermarks really match the state we read out.
15549 * Note that we need to do this after reconstructing the BIOS fb's
15550 * since the watermark calculation done here will use pstate->fb.
15551 */
15552 sanitize_watermarks(dev);
15553 }
15554
15555 static void intel_enable_pipe_a(struct drm_device *dev)
15556 {
15557 struct intel_connector *connector;
15558 struct drm_connector *crt = NULL;
15559 struct intel_load_detect_pipe load_detect_temp;
15560 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
15561
15562 /* We can't just switch on the pipe A, we need to set things up with a
15563 * proper mode and output configuration. As a gross hack, enable pipe A
15564 * by enabling the load detect pipe once. */
15565 for_each_intel_connector(dev, connector) {
15566 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15567 crt = &connector->base;
15568 break;
15569 }
15570 }
15571
15572 if (!crt)
15573 return;
15574
15575 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
15576 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
15577 }
15578
15579 static bool
15580 intel_check_plane_mapping(struct intel_crtc *crtc)
15581 {
15582 struct drm_device *dev = crtc->base.dev;
15583 struct drm_i915_private *dev_priv = dev->dev_private;
15584 u32 val;
15585
15586 if (INTEL_INFO(dev)->num_pipes == 1)
15587 return true;
15588
15589 val = I915_READ(DSPCNTR(!crtc->plane));
15590
15591 if ((val & DISPLAY_PLANE_ENABLE) &&
15592 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15593 return false;
15594
15595 return true;
15596 }
15597
15598 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
15599 {
15600 struct drm_device *dev = crtc->base.dev;
15601 struct intel_encoder *encoder;
15602
15603 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15604 return true;
15605
15606 return false;
15607 }
15608
15609 static void intel_sanitize_crtc(struct intel_crtc *crtc)
15610 {
15611 struct drm_device *dev = crtc->base.dev;
15612 struct drm_i915_private *dev_priv = dev->dev_private;
15613 i915_reg_t reg = PIPECONF(crtc->config->cpu_transcoder);
15614
15615 /* Clear any frame start delays used for debugging left by the BIOS */
15616 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15617
15618 /* restore vblank interrupts to correct state */
15619 drm_crtc_vblank_reset(&crtc->base);
15620 if (crtc->active) {
15621 struct intel_plane *plane;
15622
15623 drm_crtc_vblank_on(&crtc->base);
15624
15625 /* Disable everything but the primary plane */
15626 for_each_intel_plane_on_crtc(dev, crtc, plane) {
15627 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
15628 continue;
15629
15630 plane->disable_plane(&plane->base, &crtc->base);
15631 }
15632 }
15633
15634 /* We need to sanitize the plane -> pipe mapping first because this will
15635 * disable the crtc (and hence change the state) if it is wrong. Note
15636 * that gen4+ has a fixed plane -> pipe mapping. */
15637 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
15638 bool plane;
15639
15640 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15641 crtc->base.base.id);
15642
15643 /* Pipe has the wrong plane attached and the plane is active.
15644 * Temporarily change the plane mapping and disable everything
15645 * ... */
15646 plane = crtc->plane;
15647 to_intel_plane_state(crtc->base.primary->state)->visible = true;
15648 crtc->plane = !plane;
15649 intel_crtc_disable_noatomic(&crtc->base);
15650 crtc->plane = plane;
15651 }
15652
15653 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15654 crtc->pipe == PIPE_A && !crtc->active) {
15655 /* BIOS forgot to enable pipe A, this mostly happens after
15656 * resume. Force-enable the pipe to fix this, the update_dpms
15657 * call below we restore the pipe to the right state, but leave
15658 * the required bits on. */
15659 intel_enable_pipe_a(dev);
15660 }
15661
15662 /* Adjust the state of the output pipe according to whether we
15663 * have active connectors/encoders. */
15664 if (!intel_crtc_has_encoders(crtc))
15665 intel_crtc_disable_noatomic(&crtc->base);
15666
15667 if (crtc->active != crtc->base.state->active) {
15668 struct intel_encoder *encoder;
15669
15670 /* This can happen either due to bugs in the get_hw_state
15671 * functions or because of calls to intel_crtc_disable_noatomic,
15672 * or because the pipe is force-enabled due to the
15673 * pipe A quirk. */
15674 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15675 crtc->base.base.id,
15676 crtc->base.state->enable ? "enabled" : "disabled",
15677 crtc->active ? "enabled" : "disabled");
15678
15679 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
15680 crtc->base.state->active = crtc->active;
15681 crtc->base.enabled = crtc->active;
15682
15683 /* Because we only establish the connector -> encoder ->
15684 * crtc links if something is active, this means the
15685 * crtc is now deactivated. Break the links. connector
15686 * -> encoder links are only establish when things are
15687 * actually up, hence no need to break them. */
15688 WARN_ON(crtc->active);
15689
15690 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15691 encoder->base.crtc = NULL;
15692 }
15693
15694 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
15695 /*
15696 * We start out with underrun reporting disabled to avoid races.
15697 * For correct bookkeeping mark this on active crtcs.
15698 *
15699 * Also on gmch platforms we dont have any hardware bits to
15700 * disable the underrun reporting. Which means we need to start
15701 * out with underrun reporting disabled also on inactive pipes,
15702 * since otherwise we'll complain about the garbage we read when
15703 * e.g. coming up after runtime pm.
15704 *
15705 * No protection against concurrent access is required - at
15706 * worst a fifo underrun happens which also sets this to false.
15707 */
15708 crtc->cpu_fifo_underrun_disabled = true;
15709 crtc->pch_fifo_underrun_disabled = true;
15710 }
15711 }
15712
15713 static void intel_sanitize_encoder(struct intel_encoder *encoder)
15714 {
15715 struct intel_connector *connector;
15716 struct drm_device *dev = encoder->base.dev;
15717 bool active = false;
15718
15719 /* We need to check both for a crtc link (meaning that the
15720 * encoder is active and trying to read from a pipe) and the
15721 * pipe itself being active. */
15722 bool has_active_crtc = encoder->base.crtc &&
15723 to_intel_crtc(encoder->base.crtc)->active;
15724
15725 for_each_intel_connector(dev, connector) {
15726 if (connector->base.encoder != &encoder->base)
15727 continue;
15728
15729 active = true;
15730 break;
15731 }
15732
15733 if (active && !has_active_crtc) {
15734 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15735 encoder->base.base.id,
15736 encoder->base.name);
15737
15738 /* Connector is active, but has no active pipe. This is
15739 * fallout from our resume register restoring. Disable
15740 * the encoder manually again. */
15741 if (encoder->base.crtc) {
15742 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15743 encoder->base.base.id,
15744 encoder->base.name);
15745 encoder->disable(encoder);
15746 if (encoder->post_disable)
15747 encoder->post_disable(encoder);
15748 }
15749 encoder->base.crtc = NULL;
15750
15751 /* Inconsistent output/port/pipe state happens presumably due to
15752 * a bug in one of the get_hw_state functions. Or someplace else
15753 * in our code, like the register restore mess on resume. Clamp
15754 * things to off as a safer default. */
15755 for_each_intel_connector(dev, connector) {
15756 if (connector->encoder != encoder)
15757 continue;
15758 connector->base.dpms = DRM_MODE_DPMS_OFF;
15759 connector->base.encoder = NULL;
15760 }
15761 }
15762 /* Enabled encoders without active connectors will be fixed in
15763 * the crtc fixup. */
15764 }
15765
15766 void i915_redisable_vga_power_on(struct drm_device *dev)
15767 {
15768 struct drm_i915_private *dev_priv = dev->dev_private;
15769 i915_reg_t vga_reg = i915_vgacntrl_reg(dev);
15770
15771 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15772 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15773 i915_disable_vga(dev);
15774 }
15775 }
15776
15777 void i915_redisable_vga(struct drm_device *dev)
15778 {
15779 struct drm_i915_private *dev_priv = dev->dev_private;
15780
15781 /* This function can be called both from intel_modeset_setup_hw_state or
15782 * at a very early point in our resume sequence, where the power well
15783 * structures are not yet restored. Since this function is at a very
15784 * paranoid "someone might have enabled VGA while we were not looking"
15785 * level, just check if the power well is enabled instead of trying to
15786 * follow the "don't touch the power well if we don't need it" policy
15787 * the rest of the driver uses. */
15788 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
15789 return;
15790
15791 i915_redisable_vga_power_on(dev);
15792 }
15793
15794 static bool primary_get_hw_state(struct intel_plane *plane)
15795 {
15796 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
15797
15798 return I915_READ(DSPCNTR(plane->plane)) & DISPLAY_PLANE_ENABLE;
15799 }
15800
15801 /* FIXME read out full plane state for all planes */
15802 static void readout_plane_state(struct intel_crtc *crtc)
15803 {
15804 struct drm_plane *primary = crtc->base.primary;
15805 struct intel_plane_state *plane_state =
15806 to_intel_plane_state(primary->state);
15807
15808 plane_state->visible = crtc->active &&
15809 primary_get_hw_state(to_intel_plane(primary));
15810
15811 if (plane_state->visible)
15812 crtc->base.state->plane_mask |= 1 << drm_plane_index(primary);
15813 }
15814
15815 static void intel_modeset_readout_hw_state(struct drm_device *dev)
15816 {
15817 struct drm_i915_private *dev_priv = dev->dev_private;
15818 enum pipe pipe;
15819 struct intel_crtc *crtc;
15820 struct intel_encoder *encoder;
15821 struct intel_connector *connector;
15822 int i;
15823
15824 dev_priv->active_crtcs = 0;
15825
15826 for_each_intel_crtc(dev, crtc) {
15827 struct intel_crtc_state *crtc_state = crtc->config;
15828 int pixclk = 0;
15829
15830 __drm_atomic_helper_crtc_destroy_state(&crtc->base, &crtc_state->base);
15831 memset(crtc_state, 0, sizeof(*crtc_state));
15832 crtc_state->base.crtc = &crtc->base;
15833
15834 crtc_state->base.active = crtc_state->base.enable =
15835 dev_priv->display.get_pipe_config(crtc, crtc_state);
15836
15837 crtc->base.enabled = crtc_state->base.enable;
15838 crtc->active = crtc_state->base.active;
15839
15840 if (crtc_state->base.active) {
15841 dev_priv->active_crtcs |= 1 << crtc->pipe;
15842
15843 if (IS_BROADWELL(dev_priv)) {
15844 pixclk = ilk_pipe_pixel_rate(crtc_state);
15845
15846 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
15847 if (crtc_state->ips_enabled)
15848 pixclk = DIV_ROUND_UP(pixclk * 100, 95);
15849 } else if (IS_VALLEYVIEW(dev_priv) ||
15850 IS_CHERRYVIEW(dev_priv) ||
15851 IS_BROXTON(dev_priv))
15852 pixclk = crtc_state->base.adjusted_mode.crtc_clock;
15853 else
15854 WARN_ON(dev_priv->display.modeset_calc_cdclk);
15855 }
15856
15857 dev_priv->min_pixclk[crtc->pipe] = pixclk;
15858
15859 readout_plane_state(crtc);
15860
15861 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15862 crtc->base.base.id,
15863 crtc->active ? "enabled" : "disabled");
15864 }
15865
15866 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15867 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15868
15869 pll->on = pll->get_hw_state(dev_priv, pll,
15870 &pll->config.hw_state);
15871 pll->active = 0;
15872 pll->config.crtc_mask = 0;
15873 for_each_intel_crtc(dev, crtc) {
15874 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
15875 pll->active++;
15876 pll->config.crtc_mask |= 1 << crtc->pipe;
15877 }
15878 }
15879
15880 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
15881 pll->name, pll->config.crtc_mask, pll->on);
15882
15883 if (pll->config.crtc_mask)
15884 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
15885 }
15886
15887 for_each_intel_encoder(dev, encoder) {
15888 pipe = 0;
15889
15890 if (encoder->get_hw_state(encoder, &pipe)) {
15891 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15892 encoder->base.crtc = &crtc->base;
15893 encoder->get_config(encoder, crtc->config);
15894 } else {
15895 encoder->base.crtc = NULL;
15896 }
15897
15898 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
15899 encoder->base.base.id,
15900 encoder->base.name,
15901 encoder->base.crtc ? "enabled" : "disabled",
15902 pipe_name(pipe));
15903 }
15904
15905 for_each_intel_connector(dev, connector) {
15906 if (connector->get_hw_state(connector)) {
15907 connector->base.dpms = DRM_MODE_DPMS_ON;
15908 connector->base.encoder = &connector->encoder->base;
15909 } else {
15910 connector->base.dpms = DRM_MODE_DPMS_OFF;
15911 connector->base.encoder = NULL;
15912 }
15913 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15914 connector->base.base.id,
15915 connector->base.name,
15916 connector->base.encoder ? "enabled" : "disabled");
15917 }
15918
15919 for_each_intel_crtc(dev, crtc) {
15920 crtc->base.hwmode = crtc->config->base.adjusted_mode;
15921
15922 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15923 if (crtc->base.state->active) {
15924 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15925 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15926 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15927
15928 /*
15929 * The initial mode needs to be set in order to keep
15930 * the atomic core happy. It wants a valid mode if the
15931 * crtc's enabled, so we do the above call.
15932 *
15933 * At this point some state updated by the connectors
15934 * in their ->detect() callback has not run yet, so
15935 * no recalculation can be done yet.
15936 *
15937 * Even if we could do a recalculation and modeset
15938 * right now it would cause a double modeset if
15939 * fbdev or userspace chooses a different initial mode.
15940 *
15941 * If that happens, someone indicated they wanted a
15942 * mode change, which means it's safe to do a full
15943 * recalculation.
15944 */
15945 crtc->base.state->mode.private_flags = I915_MODE_FLAG_INHERITED;
15946
15947 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
15948 update_scanline_offset(crtc);
15949 }
15950 }
15951 }
15952
15953 /* Scan out the current hw modeset state,
15954 * and sanitizes it to the current state
15955 */
15956 static void
15957 intel_modeset_setup_hw_state(struct drm_device *dev)
15958 {
15959 struct drm_i915_private *dev_priv = dev->dev_private;
15960 enum pipe pipe;
15961 struct intel_crtc *crtc;
15962 struct intel_encoder *encoder;
15963 int i;
15964
15965 intel_modeset_readout_hw_state(dev);
15966
15967 /* HW state is read out, now we need to sanitize this mess. */
15968 for_each_intel_encoder(dev, encoder) {
15969 intel_sanitize_encoder(encoder);
15970 }
15971
15972 for_each_pipe(dev_priv, pipe) {
15973 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15974 intel_sanitize_crtc(crtc);
15975 intel_dump_pipe_config(crtc, crtc->config,
15976 "[setup_hw_state]");
15977 }
15978
15979 intel_modeset_update_connector_atomic_state(dev);
15980
15981 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15982 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15983
15984 if (!pll->on || pll->active)
15985 continue;
15986
15987 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15988
15989 pll->disable(dev_priv, pll);
15990 pll->on = false;
15991 }
15992
15993 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
15994 vlv_wm_get_hw_state(dev);
15995 else if (IS_GEN9(dev))
15996 skl_wm_get_hw_state(dev);
15997 else if (HAS_PCH_SPLIT(dev))
15998 ilk_wm_get_hw_state(dev);
15999
16000 for_each_intel_crtc(dev, crtc) {
16001 unsigned long put_domains;
16002
16003 put_domains = modeset_get_crtc_power_domains(&crtc->base);
16004 if (WARN_ON(put_domains))
16005 modeset_put_power_domains(dev_priv, put_domains);
16006 }
16007 intel_display_set_init_power(dev_priv, false);
16008 }
16009
16010 void intel_display_resume(struct drm_device *dev)
16011 {
16012 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
16013 struct intel_connector *conn;
16014 struct intel_plane *plane;
16015 struct drm_crtc *crtc;
16016 int ret;
16017
16018 if (!state)
16019 return;
16020
16021 state->acquire_ctx = dev->mode_config.acquire_ctx;
16022
16023 /* preserve complete old state, including dpll */
16024 intel_atomic_get_shared_dpll_state(state);
16025
16026 for_each_crtc(dev, crtc) {
16027 struct drm_crtc_state *crtc_state =
16028 drm_atomic_get_crtc_state(state, crtc);
16029
16030 ret = PTR_ERR_OR_ZERO(crtc_state);
16031 if (ret)
16032 goto err;
16033
16034 /* force a restore */
16035 crtc_state->mode_changed = true;
16036 }
16037
16038 for_each_intel_plane(dev, plane) {
16039 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
16040 if (ret)
16041 goto err;
16042 }
16043
16044 for_each_intel_connector(dev, conn) {
16045 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
16046 if (ret)
16047 goto err;
16048 }
16049
16050 intel_modeset_setup_hw_state(dev);
16051
16052 i915_redisable_vga(dev);
16053 ret = drm_atomic_commit(state);
16054 if (!ret)
16055 return;
16056
16057 err:
16058 DRM_ERROR("Restoring old state failed with %i\n", ret);
16059 drm_atomic_state_free(state);
16060 }
16061
16062 void intel_modeset_gem_init(struct drm_device *dev)
16063 {
16064 struct drm_crtc *c;
16065 struct drm_i915_gem_object *obj;
16066 int ret;
16067
16068 mutex_lock(&dev->struct_mutex);
16069 intel_init_gt_powersave(dev);
16070 mutex_unlock(&dev->struct_mutex);
16071
16072 intel_modeset_init_hw(dev);
16073
16074 intel_setup_overlay(dev);
16075
16076 /*
16077 * Make sure any fbs we allocated at startup are properly
16078 * pinned & fenced. When we do the allocation it's too early
16079 * for this.
16080 */
16081 for_each_crtc(dev, c) {
16082 obj = intel_fb_obj(c->primary->fb);
16083 if (obj == NULL)
16084 continue;
16085
16086 mutex_lock(&dev->struct_mutex);
16087 ret = intel_pin_and_fence_fb_obj(c->primary,
16088 c->primary->fb,
16089 c->primary->state);
16090 mutex_unlock(&dev->struct_mutex);
16091 if (ret) {
16092 DRM_ERROR("failed to pin boot fb on pipe %d\n",
16093 to_intel_crtc(c)->pipe);
16094 drm_framebuffer_unreference(c->primary->fb);
16095 c->primary->fb = NULL;
16096 c->primary->crtc = c->primary->state->crtc = NULL;
16097 update_state_fb(c->primary);
16098 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
16099 }
16100 }
16101
16102 intel_backlight_register(dev);
16103 }
16104
16105 void intel_connector_unregister(struct intel_connector *intel_connector)
16106 {
16107 struct drm_connector *connector = &intel_connector->base;
16108
16109 intel_panel_destroy_backlight(connector);
16110 drm_connector_unregister(connector);
16111 }
16112
16113 void intel_modeset_cleanup(struct drm_device *dev)
16114 {
16115 struct drm_i915_private *dev_priv = dev->dev_private;
16116 struct intel_connector *connector;
16117
16118 intel_disable_gt_powersave(dev);
16119
16120 intel_backlight_unregister(dev);
16121
16122 /*
16123 * Interrupts and polling as the first thing to avoid creating havoc.
16124 * Too much stuff here (turning of connectors, ...) would
16125 * experience fancy races otherwise.
16126 */
16127 intel_irq_uninstall(dev_priv);
16128
16129 /*
16130 * Due to the hpd irq storm handling the hotplug work can re-arm the
16131 * poll handlers. Hence disable polling after hpd handling is shut down.
16132 */
16133 drm_kms_helper_poll_fini(dev);
16134
16135 intel_unregister_dsm_handler();
16136
16137 intel_fbc_disable(dev_priv);
16138
16139 /* flush any delayed tasks or pending work */
16140 flush_scheduled_work();
16141
16142 /* destroy the backlight and sysfs files before encoders/connectors */
16143 for_each_intel_connector(dev, connector)
16144 connector->unregister(connector);
16145
16146 drm_mode_config_cleanup(dev);
16147
16148 intel_cleanup_overlay(dev);
16149
16150 mutex_lock(&dev->struct_mutex);
16151 intel_cleanup_gt_powersave(dev);
16152 mutex_unlock(&dev->struct_mutex);
16153 }
16154
16155 /*
16156 * Return which encoder is currently attached for connector.
16157 */
16158 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
16159 {
16160 return &intel_attached_encoder(connector)->base;
16161 }
16162
16163 void intel_connector_attach_encoder(struct intel_connector *connector,
16164 struct intel_encoder *encoder)
16165 {
16166 connector->encoder = encoder;
16167 drm_mode_connector_attach_encoder(&connector->base,
16168 &encoder->base);
16169 }
16170
16171 /*
16172 * set vga decode state - true == enable VGA decode
16173 */
16174 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
16175 {
16176 struct drm_i915_private *dev_priv = dev->dev_private;
16177 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
16178 u16 gmch_ctrl;
16179
16180 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
16181 DRM_ERROR("failed to read control word\n");
16182 return -EIO;
16183 }
16184
16185 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
16186 return 0;
16187
16188 if (state)
16189 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
16190 else
16191 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
16192
16193 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
16194 DRM_ERROR("failed to write control word\n");
16195 return -EIO;
16196 }
16197
16198 return 0;
16199 }
16200
16201 struct intel_display_error_state {
16202
16203 u32 power_well_driver;
16204
16205 int num_transcoders;
16206
16207 struct intel_cursor_error_state {
16208 u32 control;
16209 u32 position;
16210 u32 base;
16211 u32 size;
16212 } cursor[I915_MAX_PIPES];
16213
16214 struct intel_pipe_error_state {
16215 bool power_domain_on;
16216 u32 source;
16217 u32 stat;
16218 } pipe[I915_MAX_PIPES];
16219
16220 struct intel_plane_error_state {
16221 u32 control;
16222 u32 stride;
16223 u32 size;
16224 u32 pos;
16225 u32 addr;
16226 u32 surface;
16227 u32 tile_offset;
16228 } plane[I915_MAX_PIPES];
16229
16230 struct intel_transcoder_error_state {
16231 bool power_domain_on;
16232 enum transcoder cpu_transcoder;
16233
16234 u32 conf;
16235
16236 u32 htotal;
16237 u32 hblank;
16238 u32 hsync;
16239 u32 vtotal;
16240 u32 vblank;
16241 u32 vsync;
16242 } transcoder[4];
16243 };
16244
16245 struct intel_display_error_state *
16246 intel_display_capture_error_state(struct drm_device *dev)
16247 {
16248 struct drm_i915_private *dev_priv = dev->dev_private;
16249 struct intel_display_error_state *error;
16250 int transcoders[] = {
16251 TRANSCODER_A,
16252 TRANSCODER_B,
16253 TRANSCODER_C,
16254 TRANSCODER_EDP,
16255 };
16256 int i;
16257
16258 if (INTEL_INFO(dev)->num_pipes == 0)
16259 return NULL;
16260
16261 error = kzalloc(sizeof(*error), GFP_ATOMIC);
16262 if (error == NULL)
16263 return NULL;
16264
16265 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16266 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
16267
16268 for_each_pipe(dev_priv, i) {
16269 error->pipe[i].power_domain_on =
16270 __intel_display_power_is_enabled(dev_priv,
16271 POWER_DOMAIN_PIPE(i));
16272 if (!error->pipe[i].power_domain_on)
16273 continue;
16274
16275 error->cursor[i].control = I915_READ(CURCNTR(i));
16276 error->cursor[i].position = I915_READ(CURPOS(i));
16277 error->cursor[i].base = I915_READ(CURBASE(i));
16278
16279 error->plane[i].control = I915_READ(DSPCNTR(i));
16280 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
16281 if (INTEL_INFO(dev)->gen <= 3) {
16282 error->plane[i].size = I915_READ(DSPSIZE(i));
16283 error->plane[i].pos = I915_READ(DSPPOS(i));
16284 }
16285 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16286 error->plane[i].addr = I915_READ(DSPADDR(i));
16287 if (INTEL_INFO(dev)->gen >= 4) {
16288 error->plane[i].surface = I915_READ(DSPSURF(i));
16289 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
16290 }
16291
16292 error->pipe[i].source = I915_READ(PIPESRC(i));
16293
16294 if (HAS_GMCH_DISPLAY(dev))
16295 error->pipe[i].stat = I915_READ(PIPESTAT(i));
16296 }
16297
16298 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
16299 if (HAS_DDI(dev_priv->dev))
16300 error->num_transcoders++; /* Account for eDP. */
16301
16302 for (i = 0; i < error->num_transcoders; i++) {
16303 enum transcoder cpu_transcoder = transcoders[i];
16304
16305 error->transcoder[i].power_domain_on =
16306 __intel_display_power_is_enabled(dev_priv,
16307 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
16308 if (!error->transcoder[i].power_domain_on)
16309 continue;
16310
16311 error->transcoder[i].cpu_transcoder = cpu_transcoder;
16312
16313 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
16314 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
16315 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
16316 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
16317 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
16318 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
16319 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
16320 }
16321
16322 return error;
16323 }
16324
16325 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
16326
16327 void
16328 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
16329 struct drm_device *dev,
16330 struct intel_display_error_state *error)
16331 {
16332 struct drm_i915_private *dev_priv = dev->dev_private;
16333 int i;
16334
16335 if (!error)
16336 return;
16337
16338 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
16339 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
16340 err_printf(m, "PWR_WELL_CTL2: %08x\n",
16341 error->power_well_driver);
16342 for_each_pipe(dev_priv, i) {
16343 err_printf(m, "Pipe [%d]:\n", i);
16344 err_printf(m, " Power: %s\n",
16345 error->pipe[i].power_domain_on ? "on" : "off");
16346 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
16347 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
16348
16349 err_printf(m, "Plane [%d]:\n", i);
16350 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
16351 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
16352 if (INTEL_INFO(dev)->gen <= 3) {
16353 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
16354 err_printf(m, " POS: %08x\n", error->plane[i].pos);
16355 }
16356 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
16357 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
16358 if (INTEL_INFO(dev)->gen >= 4) {
16359 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
16360 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
16361 }
16362
16363 err_printf(m, "Cursor [%d]:\n", i);
16364 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
16365 err_printf(m, " POS: %08x\n", error->cursor[i].position);
16366 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
16367 }
16368
16369 for (i = 0; i < error->num_transcoders; i++) {
16370 err_printf(m, "CPU transcoder: %c\n",
16371 transcoder_name(error->transcoder[i].cpu_transcoder));
16372 err_printf(m, " Power: %s\n",
16373 error->transcoder[i].power_domain_on ? "on" : "off");
16374 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
16375 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
16376 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
16377 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
16378 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
16379 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
16380 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
16381 }
16382 }
16383
16384 void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
16385 {
16386 struct intel_crtc *crtc;
16387
16388 for_each_intel_crtc(dev, crtc) {
16389 struct intel_unpin_work *work;
16390
16391 spin_lock_irq(&dev->event_lock);
16392
16393 work = crtc->unpin_work;
16394
16395 if (work && work->event &&
16396 work->event->base.file_priv == file) {
16397 kfree(work->event);
16398 work->event = NULL;
16399 }
16400
16401 spin_unlock_irq(&dev->event_lock);
16402 }
16403 }
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