2 * Copyright © 2006-2007 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
24 * Eric Anholt <eric@anholt.net>
27 #include <linux/dmi.h>
28 #include <linux/module.h>
29 #include <linux/input.h>
30 #include <linux/i2c.h>
31 #include <linux/kernel.h>
32 #include <linux/slab.h>
33 #include <linux/vgaarb.h>
34 #include <drm/drm_edid.h>
36 #include "intel_drv.h"
39 #include "i915_trace.h"
40 #include "drm_dp_helper.h"
41 #include "drm_crtc_helper.h"
42 #include <linux/dma_remapping.h>
44 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
46 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
);
47 static void intel_increase_pllclock(struct drm_crtc
*crtc
);
48 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
, bool on
);
71 #define INTEL_P2_NUM 2
72 typedef struct intel_limit intel_limit_t
;
74 intel_range_t dot
, vco
, n
, m
, m1
, m2
, p
, p1
;
76 bool (* find_pll
)(const intel_limit_t
*, struct drm_crtc
*,
77 int, int, intel_clock_t
*, intel_clock_t
*);
81 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
85 int target
, int refclk
, intel_clock_t
*match_clock
,
86 intel_clock_t
*best_clock
);
88 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
89 int target
, int refclk
, intel_clock_t
*match_clock
,
90 intel_clock_t
*best_clock
);
93 intel_find_pll_g4x_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
94 int target
, int refclk
, intel_clock_t
*match_clock
,
95 intel_clock_t
*best_clock
);
97 intel_find_pll_ironlake_dp(const intel_limit_t
*, struct drm_crtc
*crtc
,
98 int target
, int refclk
, intel_clock_t
*match_clock
,
99 intel_clock_t
*best_clock
);
102 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
103 int target
, int refclk
, intel_clock_t
*match_clock
,
104 intel_clock_t
*best_clock
);
106 static inline u32
/* units of 100MHz */
107 intel_fdi_link_freq(struct drm_device
*dev
)
110 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
111 return (I915_READ(FDI_PLL_BIOS_0
) & FDI_PLL_FB_CLOCK_MASK
) + 2;
116 static const intel_limit_t intel_limits_i8xx_dvo
= {
117 .dot
= { .min
= 25000, .max
= 350000 },
118 .vco
= { .min
= 930000, .max
= 1400000 },
119 .n
= { .min
= 3, .max
= 16 },
120 .m
= { .min
= 96, .max
= 140 },
121 .m1
= { .min
= 18, .max
= 26 },
122 .m2
= { .min
= 6, .max
= 16 },
123 .p
= { .min
= 4, .max
= 128 },
124 .p1
= { .min
= 2, .max
= 33 },
125 .p2
= { .dot_limit
= 165000,
126 .p2_slow
= 4, .p2_fast
= 2 },
127 .find_pll
= intel_find_best_PLL
,
130 static const intel_limit_t intel_limits_i8xx_lvds
= {
131 .dot
= { .min
= 25000, .max
= 350000 },
132 .vco
= { .min
= 930000, .max
= 1400000 },
133 .n
= { .min
= 3, .max
= 16 },
134 .m
= { .min
= 96, .max
= 140 },
135 .m1
= { .min
= 18, .max
= 26 },
136 .m2
= { .min
= 6, .max
= 16 },
137 .p
= { .min
= 4, .max
= 128 },
138 .p1
= { .min
= 1, .max
= 6 },
139 .p2
= { .dot_limit
= 165000,
140 .p2_slow
= 14, .p2_fast
= 7 },
141 .find_pll
= intel_find_best_PLL
,
144 static const intel_limit_t intel_limits_i9xx_sdvo
= {
145 .dot
= { .min
= 20000, .max
= 400000 },
146 .vco
= { .min
= 1400000, .max
= 2800000 },
147 .n
= { .min
= 1, .max
= 6 },
148 .m
= { .min
= 70, .max
= 120 },
149 .m1
= { .min
= 10, .max
= 22 },
150 .m2
= { .min
= 5, .max
= 9 },
151 .p
= { .min
= 5, .max
= 80 },
152 .p1
= { .min
= 1, .max
= 8 },
153 .p2
= { .dot_limit
= 200000,
154 .p2_slow
= 10, .p2_fast
= 5 },
155 .find_pll
= intel_find_best_PLL
,
158 static const intel_limit_t intel_limits_i9xx_lvds
= {
159 .dot
= { .min
= 20000, .max
= 400000 },
160 .vco
= { .min
= 1400000, .max
= 2800000 },
161 .n
= { .min
= 1, .max
= 6 },
162 .m
= { .min
= 70, .max
= 120 },
163 .m1
= { .min
= 10, .max
= 22 },
164 .m2
= { .min
= 5, .max
= 9 },
165 .p
= { .min
= 7, .max
= 98 },
166 .p1
= { .min
= 1, .max
= 8 },
167 .p2
= { .dot_limit
= 112000,
168 .p2_slow
= 14, .p2_fast
= 7 },
169 .find_pll
= intel_find_best_PLL
,
173 static const intel_limit_t intel_limits_g4x_sdvo
= {
174 .dot
= { .min
= 25000, .max
= 270000 },
175 .vco
= { .min
= 1750000, .max
= 3500000},
176 .n
= { .min
= 1, .max
= 4 },
177 .m
= { .min
= 104, .max
= 138 },
178 .m1
= { .min
= 17, .max
= 23 },
179 .m2
= { .min
= 5, .max
= 11 },
180 .p
= { .min
= 10, .max
= 30 },
181 .p1
= { .min
= 1, .max
= 3},
182 .p2
= { .dot_limit
= 270000,
186 .find_pll
= intel_g4x_find_best_PLL
,
189 static const intel_limit_t intel_limits_g4x_hdmi
= {
190 .dot
= { .min
= 22000, .max
= 400000 },
191 .vco
= { .min
= 1750000, .max
= 3500000},
192 .n
= { .min
= 1, .max
= 4 },
193 .m
= { .min
= 104, .max
= 138 },
194 .m1
= { .min
= 16, .max
= 23 },
195 .m2
= { .min
= 5, .max
= 11 },
196 .p
= { .min
= 5, .max
= 80 },
197 .p1
= { .min
= 1, .max
= 8},
198 .p2
= { .dot_limit
= 165000,
199 .p2_slow
= 10, .p2_fast
= 5 },
200 .find_pll
= intel_g4x_find_best_PLL
,
203 static const intel_limit_t intel_limits_g4x_single_channel_lvds
= {
204 .dot
= { .min
= 20000, .max
= 115000 },
205 .vco
= { .min
= 1750000, .max
= 3500000 },
206 .n
= { .min
= 1, .max
= 3 },
207 .m
= { .min
= 104, .max
= 138 },
208 .m1
= { .min
= 17, .max
= 23 },
209 .m2
= { .min
= 5, .max
= 11 },
210 .p
= { .min
= 28, .max
= 112 },
211 .p1
= { .min
= 2, .max
= 8 },
212 .p2
= { .dot_limit
= 0,
213 .p2_slow
= 14, .p2_fast
= 14
215 .find_pll
= intel_g4x_find_best_PLL
,
218 static const intel_limit_t intel_limits_g4x_dual_channel_lvds
= {
219 .dot
= { .min
= 80000, .max
= 224000 },
220 .vco
= { .min
= 1750000, .max
= 3500000 },
221 .n
= { .min
= 1, .max
= 3 },
222 .m
= { .min
= 104, .max
= 138 },
223 .m1
= { .min
= 17, .max
= 23 },
224 .m2
= { .min
= 5, .max
= 11 },
225 .p
= { .min
= 14, .max
= 42 },
226 .p1
= { .min
= 2, .max
= 6 },
227 .p2
= { .dot_limit
= 0,
228 .p2_slow
= 7, .p2_fast
= 7
230 .find_pll
= intel_g4x_find_best_PLL
,
233 static const intel_limit_t intel_limits_g4x_display_port
= {
234 .dot
= { .min
= 161670, .max
= 227000 },
235 .vco
= { .min
= 1750000, .max
= 3500000},
236 .n
= { .min
= 1, .max
= 2 },
237 .m
= { .min
= 97, .max
= 108 },
238 .m1
= { .min
= 0x10, .max
= 0x12 },
239 .m2
= { .min
= 0x05, .max
= 0x06 },
240 .p
= { .min
= 10, .max
= 20 },
241 .p1
= { .min
= 1, .max
= 2},
242 .p2
= { .dot_limit
= 0,
243 .p2_slow
= 10, .p2_fast
= 10 },
244 .find_pll
= intel_find_pll_g4x_dp
,
247 static const intel_limit_t intel_limits_pineview_sdvo
= {
248 .dot
= { .min
= 20000, .max
= 400000},
249 .vco
= { .min
= 1700000, .max
= 3500000 },
250 /* Pineview's Ncounter is a ring counter */
251 .n
= { .min
= 3, .max
= 6 },
252 .m
= { .min
= 2, .max
= 256 },
253 /* Pineview only has one combined m divider, which we treat as m2. */
254 .m1
= { .min
= 0, .max
= 0 },
255 .m2
= { .min
= 0, .max
= 254 },
256 .p
= { .min
= 5, .max
= 80 },
257 .p1
= { .min
= 1, .max
= 8 },
258 .p2
= { .dot_limit
= 200000,
259 .p2_slow
= 10, .p2_fast
= 5 },
260 .find_pll
= intel_find_best_PLL
,
263 static const intel_limit_t intel_limits_pineview_lvds
= {
264 .dot
= { .min
= 20000, .max
= 400000 },
265 .vco
= { .min
= 1700000, .max
= 3500000 },
266 .n
= { .min
= 3, .max
= 6 },
267 .m
= { .min
= 2, .max
= 256 },
268 .m1
= { .min
= 0, .max
= 0 },
269 .m2
= { .min
= 0, .max
= 254 },
270 .p
= { .min
= 7, .max
= 112 },
271 .p1
= { .min
= 1, .max
= 8 },
272 .p2
= { .dot_limit
= 112000,
273 .p2_slow
= 14, .p2_fast
= 14 },
274 .find_pll
= intel_find_best_PLL
,
277 /* Ironlake / Sandybridge
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
282 static const intel_limit_t intel_limits_ironlake_dac
= {
283 .dot
= { .min
= 25000, .max
= 350000 },
284 .vco
= { .min
= 1760000, .max
= 3510000 },
285 .n
= { .min
= 1, .max
= 5 },
286 .m
= { .min
= 79, .max
= 127 },
287 .m1
= { .min
= 12, .max
= 22 },
288 .m2
= { .min
= 5, .max
= 9 },
289 .p
= { .min
= 5, .max
= 80 },
290 .p1
= { .min
= 1, .max
= 8 },
291 .p2
= { .dot_limit
= 225000,
292 .p2_slow
= 10, .p2_fast
= 5 },
293 .find_pll
= intel_g4x_find_best_PLL
,
296 static const intel_limit_t intel_limits_ironlake_single_lvds
= {
297 .dot
= { .min
= 25000, .max
= 350000 },
298 .vco
= { .min
= 1760000, .max
= 3510000 },
299 .n
= { .min
= 1, .max
= 3 },
300 .m
= { .min
= 79, .max
= 118 },
301 .m1
= { .min
= 12, .max
= 22 },
302 .m2
= { .min
= 5, .max
= 9 },
303 .p
= { .min
= 28, .max
= 112 },
304 .p1
= { .min
= 2, .max
= 8 },
305 .p2
= { .dot_limit
= 225000,
306 .p2_slow
= 14, .p2_fast
= 14 },
307 .find_pll
= intel_g4x_find_best_PLL
,
310 static const intel_limit_t intel_limits_ironlake_dual_lvds
= {
311 .dot
= { .min
= 25000, .max
= 350000 },
312 .vco
= { .min
= 1760000, .max
= 3510000 },
313 .n
= { .min
= 1, .max
= 3 },
314 .m
= { .min
= 79, .max
= 127 },
315 .m1
= { .min
= 12, .max
= 22 },
316 .m2
= { .min
= 5, .max
= 9 },
317 .p
= { .min
= 14, .max
= 56 },
318 .p1
= { .min
= 2, .max
= 8 },
319 .p2
= { .dot_limit
= 225000,
320 .p2_slow
= 7, .p2_fast
= 7 },
321 .find_pll
= intel_g4x_find_best_PLL
,
324 /* LVDS 100mhz refclk limits. */
325 static const intel_limit_t intel_limits_ironlake_single_lvds_100m
= {
326 .dot
= { .min
= 25000, .max
= 350000 },
327 .vco
= { .min
= 1760000, .max
= 3510000 },
328 .n
= { .min
= 1, .max
= 2 },
329 .m
= { .min
= 79, .max
= 126 },
330 .m1
= { .min
= 12, .max
= 22 },
331 .m2
= { .min
= 5, .max
= 9 },
332 .p
= { .min
= 28, .max
= 112 },
333 .p1
= { .min
= 2, .max
= 8 },
334 .p2
= { .dot_limit
= 225000,
335 .p2_slow
= 14, .p2_fast
= 14 },
336 .find_pll
= intel_g4x_find_best_PLL
,
339 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m
= {
340 .dot
= { .min
= 25000, .max
= 350000 },
341 .vco
= { .min
= 1760000, .max
= 3510000 },
342 .n
= { .min
= 1, .max
= 3 },
343 .m
= { .min
= 79, .max
= 126 },
344 .m1
= { .min
= 12, .max
= 22 },
345 .m2
= { .min
= 5, .max
= 9 },
346 .p
= { .min
= 14, .max
= 42 },
347 .p1
= { .min
= 2, .max
= 6 },
348 .p2
= { .dot_limit
= 225000,
349 .p2_slow
= 7, .p2_fast
= 7 },
350 .find_pll
= intel_g4x_find_best_PLL
,
353 static const intel_limit_t intel_limits_ironlake_display_port
= {
354 .dot
= { .min
= 25000, .max
= 350000 },
355 .vco
= { .min
= 1760000, .max
= 3510000},
356 .n
= { .min
= 1, .max
= 2 },
357 .m
= { .min
= 81, .max
= 90 },
358 .m1
= { .min
= 12, .max
= 22 },
359 .m2
= { .min
= 5, .max
= 9 },
360 .p
= { .min
= 10, .max
= 20 },
361 .p1
= { .min
= 1, .max
= 2},
362 .p2
= { .dot_limit
= 0,
363 .p2_slow
= 10, .p2_fast
= 10 },
364 .find_pll
= intel_find_pll_ironlake_dp
,
367 static const intel_limit_t intel_limits_vlv_dac
= {
368 .dot
= { .min
= 25000, .max
= 270000 },
369 .vco
= { .min
= 4000000, .max
= 6000000 },
370 .n
= { .min
= 1, .max
= 7 },
371 .m
= { .min
= 22, .max
= 450 }, /* guess */
372 .m1
= { .min
= 2, .max
= 3 },
373 .m2
= { .min
= 11, .max
= 156 },
374 .p
= { .min
= 10, .max
= 30 },
375 .p1
= { .min
= 2, .max
= 3 },
376 .p2
= { .dot_limit
= 270000,
377 .p2_slow
= 2, .p2_fast
= 20 },
378 .find_pll
= intel_vlv_find_best_pll
,
381 static const intel_limit_t intel_limits_vlv_hdmi
= {
382 .dot
= { .min
= 20000, .max
= 165000 },
383 .vco
= { .min
= 5994000, .max
= 4000000 },
384 .n
= { .min
= 1, .max
= 7 },
385 .m
= { .min
= 60, .max
= 300 }, /* guess */
386 .m1
= { .min
= 2, .max
= 3 },
387 .m2
= { .min
= 11, .max
= 156 },
388 .p
= { .min
= 10, .max
= 30 },
389 .p1
= { .min
= 2, .max
= 3 },
390 .p2
= { .dot_limit
= 270000,
391 .p2_slow
= 2, .p2_fast
= 20 },
392 .find_pll
= intel_vlv_find_best_pll
,
395 static const intel_limit_t intel_limits_vlv_dp
= {
396 .dot
= { .min
= 162000, .max
= 270000 },
397 .vco
= { .min
= 5994000, .max
= 4000000 },
398 .n
= { .min
= 1, .max
= 7 },
399 .m
= { .min
= 60, .max
= 300 }, /* guess */
400 .m1
= { .min
= 2, .max
= 3 },
401 .m2
= { .min
= 11, .max
= 156 },
402 .p
= { .min
= 10, .max
= 30 },
403 .p1
= { .min
= 2, .max
= 3 },
404 .p2
= { .dot_limit
= 270000,
405 .p2_slow
= 2, .p2_fast
= 20 },
406 .find_pll
= intel_vlv_find_best_pll
,
409 u32
intel_dpio_read(struct drm_i915_private
*dev_priv
, int reg
)
414 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
420 I915_WRITE(DPIO_REG
, reg
);
421 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_READ
| DPIO_PORTID
|
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
427 val
= I915_READ(DPIO_DATA
);
430 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
434 static void intel_dpio_write(struct drm_i915_private
*dev_priv
, int reg
,
439 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
445 I915_WRITE(DPIO_DATA
, val
);
446 I915_WRITE(DPIO_REG
, reg
);
447 I915_WRITE(DPIO_PKT
, DPIO_RID
| DPIO_OP_WRITE
| DPIO_PORTID
|
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT
) & DPIO_BUSY
) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
453 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
456 static void vlv_init_dpio(struct drm_device
*dev
)
458 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL
, 0);
462 POSTING_READ(DPIO_CTL
);
463 I915_WRITE(DPIO_CTL
, 1);
464 POSTING_READ(DPIO_CTL
);
467 static int intel_dual_link_lvds_callback(const struct dmi_system_id
*id
)
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id
->ident
);
473 static const struct dmi_system_id intel_dual_link_lvds
[] = {
475 .callback
= intel_dual_link_lvds_callback
,
476 .ident
= "Apple MacBook Pro (Core i5/i7 Series)",
478 DMI_MATCH(DMI_SYS_VENDOR
, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME
, "MacBookPro8,2"),
482 { } /* terminating entry */
485 static bool is_dual_link_lvds(struct drm_i915_private
*dev_priv
,
490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode
> 0)
492 return i915_lvds_channel_mode
== 2;
494 if (dmi_check_system(intel_dual_link_lvds
))
497 if (dev_priv
->lvds_val
)
498 val
= dev_priv
->lvds_val
;
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
505 val
= I915_READ(reg
);
506 if (!(val
& ~(LVDS_PIPE_MASK
| LVDS_DETECTED
)))
507 val
= dev_priv
->bios_lvds_val
;
508 dev_priv
->lvds_val
= val
;
510 return (val
& LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
;
513 static const intel_limit_t
*intel_ironlake_limit(struct drm_crtc
*crtc
,
516 struct drm_device
*dev
= crtc
->dev
;
517 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 const intel_limit_t
*limit
;
520 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
521 if (is_dual_link_lvds(dev_priv
, PCH_LVDS
)) {
522 /* LVDS dual channel */
523 if (refclk
== 100000)
524 limit
= &intel_limits_ironlake_dual_lvds_100m
;
526 limit
= &intel_limits_ironlake_dual_lvds
;
528 if (refclk
== 100000)
529 limit
= &intel_limits_ironlake_single_lvds_100m
;
531 limit
= &intel_limits_ironlake_single_lvds
;
533 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
535 limit
= &intel_limits_ironlake_display_port
;
537 limit
= &intel_limits_ironlake_dac
;
542 static const intel_limit_t
*intel_g4x_limit(struct drm_crtc
*crtc
)
544 struct drm_device
*dev
= crtc
->dev
;
545 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
546 const intel_limit_t
*limit
;
548 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
549 if (is_dual_link_lvds(dev_priv
, LVDS
))
550 /* LVDS with dual channel */
551 limit
= &intel_limits_g4x_dual_channel_lvds
;
553 /* LVDS with dual channel */
554 limit
= &intel_limits_g4x_single_channel_lvds
;
555 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
) ||
556 intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
557 limit
= &intel_limits_g4x_hdmi
;
558 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
)) {
559 limit
= &intel_limits_g4x_sdvo
;
560 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
561 limit
= &intel_limits_g4x_display_port
;
562 } else /* The option is for other outputs */
563 limit
= &intel_limits_i9xx_sdvo
;
568 static const intel_limit_t
*intel_limit(struct drm_crtc
*crtc
, int refclk
)
570 struct drm_device
*dev
= crtc
->dev
;
571 const intel_limit_t
*limit
;
573 if (HAS_PCH_SPLIT(dev
))
574 limit
= intel_ironlake_limit(crtc
, refclk
);
575 else if (IS_G4X(dev
)) {
576 limit
= intel_g4x_limit(crtc
);
577 } else if (IS_PINEVIEW(dev
)) {
578 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
579 limit
= &intel_limits_pineview_lvds
;
581 limit
= &intel_limits_pineview_sdvo
;
582 } else if (IS_VALLEYVIEW(dev
)) {
583 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
))
584 limit
= &intel_limits_vlv_dac
;
585 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
))
586 limit
= &intel_limits_vlv_hdmi
;
588 limit
= &intel_limits_vlv_dp
;
589 } else if (!IS_GEN2(dev
)) {
590 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
591 limit
= &intel_limits_i9xx_lvds
;
593 limit
= &intel_limits_i9xx_sdvo
;
595 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
596 limit
= &intel_limits_i8xx_lvds
;
598 limit
= &intel_limits_i8xx_dvo
;
603 /* m1 is reserved as 0 in Pineview, n is a ring counter */
604 static void pineview_clock(int refclk
, intel_clock_t
*clock
)
606 clock
->m
= clock
->m2
+ 2;
607 clock
->p
= clock
->p1
* clock
->p2
;
608 clock
->vco
= refclk
* clock
->m
/ clock
->n
;
609 clock
->dot
= clock
->vco
/ clock
->p
;
612 static void intel_clock(struct drm_device
*dev
, int refclk
, intel_clock_t
*clock
)
614 if (IS_PINEVIEW(dev
)) {
615 pineview_clock(refclk
, clock
);
618 clock
->m
= 5 * (clock
->m1
+ 2) + (clock
->m2
+ 2);
619 clock
->p
= clock
->p1
* clock
->p2
;
620 clock
->vco
= refclk
* clock
->m
/ (clock
->n
+ 2);
621 clock
->dot
= clock
->vco
/ clock
->p
;
625 * Returns whether any output on the specified pipe is of the specified type
627 bool intel_pipe_has_type(struct drm_crtc
*crtc
, int type
)
629 struct drm_device
*dev
= crtc
->dev
;
630 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
631 struct intel_encoder
*encoder
;
633 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
634 if (encoder
->base
.crtc
== crtc
&& encoder
->type
== type
)
640 #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
642 * Returns whether the given set of divisors are valid for a given refclk with
643 * the given connectors.
646 static bool intel_PLL_is_valid(struct drm_device
*dev
,
647 const intel_limit_t
*limit
,
648 const intel_clock_t
*clock
)
650 if (clock
->p1
< limit
->p1
.min
|| limit
->p1
.max
< clock
->p1
)
651 INTELPllInvalid("p1 out of range\n");
652 if (clock
->p
< limit
->p
.min
|| limit
->p
.max
< clock
->p
)
653 INTELPllInvalid("p out of range\n");
654 if (clock
->m2
< limit
->m2
.min
|| limit
->m2
.max
< clock
->m2
)
655 INTELPllInvalid("m2 out of range\n");
656 if (clock
->m1
< limit
->m1
.min
|| limit
->m1
.max
< clock
->m1
)
657 INTELPllInvalid("m1 out of range\n");
658 if (clock
->m1
<= clock
->m2
&& !IS_PINEVIEW(dev
))
659 INTELPllInvalid("m1 <= m2\n");
660 if (clock
->m
< limit
->m
.min
|| limit
->m
.max
< clock
->m
)
661 INTELPllInvalid("m out of range\n");
662 if (clock
->n
< limit
->n
.min
|| limit
->n
.max
< clock
->n
)
663 INTELPllInvalid("n out of range\n");
664 if (clock
->vco
< limit
->vco
.min
|| limit
->vco
.max
< clock
->vco
)
665 INTELPllInvalid("vco out of range\n");
666 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
667 * connector, etc., rather than just a single range.
669 if (clock
->dot
< limit
->dot
.min
|| limit
->dot
.max
< clock
->dot
)
670 INTELPllInvalid("dot out of range\n");
676 intel_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
677 int target
, int refclk
, intel_clock_t
*match_clock
,
678 intel_clock_t
*best_clock
)
681 struct drm_device
*dev
= crtc
->dev
;
682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
686 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
687 (I915_READ(LVDS
)) != 0) {
689 * For LVDS, if the panel is on, just rely on its current
690 * settings for dual-channel. We haven't figured out how to
691 * reliably set up different single/dual channel state, if we
694 if (is_dual_link_lvds(dev_priv
, LVDS
))
695 clock
.p2
= limit
->p2
.p2_fast
;
697 clock
.p2
= limit
->p2
.p2_slow
;
699 if (target
< limit
->p2
.dot_limit
)
700 clock
.p2
= limit
->p2
.p2_slow
;
702 clock
.p2
= limit
->p2
.p2_fast
;
705 memset(best_clock
, 0, sizeof(*best_clock
));
707 for (clock
.m1
= limit
->m1
.min
; clock
.m1
<= limit
->m1
.max
;
709 for (clock
.m2
= limit
->m2
.min
;
710 clock
.m2
<= limit
->m2
.max
; clock
.m2
++) {
711 /* m1 is always 0 in Pineview */
712 if (clock
.m2
>= clock
.m1
&& !IS_PINEVIEW(dev
))
714 for (clock
.n
= limit
->n
.min
;
715 clock
.n
<= limit
->n
.max
; clock
.n
++) {
716 for (clock
.p1
= limit
->p1
.min
;
717 clock
.p1
<= limit
->p1
.max
; clock
.p1
++) {
720 intel_clock(dev
, refclk
, &clock
);
721 if (!intel_PLL_is_valid(dev
, limit
,
725 clock
.p
!= match_clock
->p
)
728 this_err
= abs(clock
.dot
- target
);
729 if (this_err
< err
) {
738 return (err
!= target
);
742 intel_g4x_find_best_PLL(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
743 int target
, int refclk
, intel_clock_t
*match_clock
,
744 intel_clock_t
*best_clock
)
746 struct drm_device
*dev
= crtc
->dev
;
747 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
751 /* approximately equals target * 0.00585 */
752 int err_most
= (target
>> 8) + (target
>> 9);
755 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
758 if (HAS_PCH_SPLIT(dev
))
762 if ((I915_READ(lvds_reg
) & LVDS_CLKB_POWER_MASK
) ==
764 clock
.p2
= limit
->p2
.p2_fast
;
766 clock
.p2
= limit
->p2
.p2_slow
;
768 if (target
< limit
->p2
.dot_limit
)
769 clock
.p2
= limit
->p2
.p2_slow
;
771 clock
.p2
= limit
->p2
.p2_fast
;
774 memset(best_clock
, 0, sizeof(*best_clock
));
775 max_n
= limit
->n
.max
;
776 /* based on hardware requirement, prefer smaller n to precision */
777 for (clock
.n
= limit
->n
.min
; clock
.n
<= max_n
; clock
.n
++) {
778 /* based on hardware requirement, prefere larger m1,m2 */
779 for (clock
.m1
= limit
->m1
.max
;
780 clock
.m1
>= limit
->m1
.min
; clock
.m1
--) {
781 for (clock
.m2
= limit
->m2
.max
;
782 clock
.m2
>= limit
->m2
.min
; clock
.m2
--) {
783 for (clock
.p1
= limit
->p1
.max
;
784 clock
.p1
>= limit
->p1
.min
; clock
.p1
--) {
787 intel_clock(dev
, refclk
, &clock
);
788 if (!intel_PLL_is_valid(dev
, limit
,
792 clock
.p
!= match_clock
->p
)
795 this_err
= abs(clock
.dot
- target
);
796 if (this_err
< err_most
) {
810 intel_find_pll_ironlake_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
811 int target
, int refclk
, intel_clock_t
*match_clock
,
812 intel_clock_t
*best_clock
)
814 struct drm_device
*dev
= crtc
->dev
;
817 if (target
< 200000) {
830 intel_clock(dev
, refclk
, &clock
);
831 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
835 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
837 intel_find_pll_g4x_dp(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
838 int target
, int refclk
, intel_clock_t
*match_clock
,
839 intel_clock_t
*best_clock
)
842 if (target
< 200000) {
855 clock
.m
= 5 * (clock
.m1
+ 2) + (clock
.m2
+ 2);
856 clock
.p
= (clock
.p1
* clock
.p2
);
857 clock
.dot
= 96000 * clock
.m
/ (clock
.n
+ 2) / clock
.p
;
859 memcpy(best_clock
, &clock
, sizeof(intel_clock_t
));
863 intel_vlv_find_best_pll(const intel_limit_t
*limit
, struct drm_crtc
*crtc
,
864 int target
, int refclk
, intel_clock_t
*match_clock
,
865 intel_clock_t
*best_clock
)
867 u32 p1
, p2
, m1
, m2
, vco
, bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
869 u32 updrate
, minupdate
, fracbits
, p
;
870 unsigned long bestppm
, ppm
, absppm
;
873 dotclk
= target
* 1000;
876 fastclk
= dotclk
/ (2*100);
880 n
= p
= p1
= p2
= m
= m1
= m2
= vco
= bestn
= 0;
881 bestm1
= bestm2
= bestp1
= bestp2
= 0;
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n
= limit
->n
.min
; n
<= ((refclk
) / minupdate
); n
++) {
885 updrate
= refclk
/ n
;
886 for (p1
= limit
->p1
.max
; p1
> limit
->p1
.min
; p1
--) {
887 for (p2
= limit
->p2
.p2_fast
+1; p2
> 0; p2
--) {
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1
= limit
->m1
.min
; m1
<= limit
->m1
.max
; m1
++) {
893 m2
= (((2*(fastclk
* p
* n
/ m1
)) +
894 refclk
) / (2*refclk
));
897 if (vco
>= limit
->vco
.min
&& vco
< limit
->vco
.max
) {
898 ppm
= 1000000 * ((vco
/ p
) - fastclk
) / fastclk
;
899 absppm
= (ppm
> 0) ? ppm
: (-ppm
);
900 if (absppm
< 100 && ((p1
* p2
) > (bestp1
* bestp2
))) {
904 if (absppm
< bestppm
- 10) {
921 best_clock
->n
= bestn
;
922 best_clock
->m1
= bestm1
;
923 best_clock
->m2
= bestm2
;
924 best_clock
->p1
= bestp1
;
925 best_clock
->p2
= bestp2
;
930 static void ironlake_wait_for_vblank(struct drm_device
*dev
, int pipe
)
932 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
933 u32 frame
, frame_reg
= PIPEFRAME(pipe
);
935 frame
= I915_READ(frame_reg
);
937 if (wait_for(I915_READ_NOTRACE(frame_reg
) != frame
, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
942 * intel_wait_for_vblank - wait for vblank on a given pipe
944 * @pipe: pipe to wait for
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
949 void intel_wait_for_vblank(struct drm_device
*dev
, int pipe
)
951 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
952 int pipestat_reg
= PIPESTAT(pipe
);
954 if (INTEL_INFO(dev
)->gen
>= 5) {
955 ironlake_wait_for_vblank(dev
, pipe
);
959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
972 I915_WRITE(pipestat_reg
,
973 I915_READ(pipestat_reg
) | PIPE_VBLANK_INTERRUPT_STATUS
);
975 /* Wait for vblank interrupt bit to set */
976 if (wait_for(I915_READ(pipestat_reg
) &
977 PIPE_VBLANK_INTERRUPT_STATUS
,
979 DRM_DEBUG_KMS("vblank wait timed out\n");
983 * intel_wait_for_pipe_off - wait for pipe to turn off
985 * @pipe: pipe to wait for
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
992 * wait for the pipe register state bit to turn off
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
999 void intel_wait_for_pipe_off(struct drm_device
*dev
, int pipe
)
1001 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1003 if (INTEL_INFO(dev
)->gen
>= 4) {
1004 int reg
= PIPECONF(pipe
);
1006 /* Wait for the Pipe State to go off */
1007 if (wait_for((I915_READ(reg
) & I965_PIPECONF_ACTIVE
) == 0,
1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1011 u32 last_line
, line_mask
;
1012 int reg
= PIPEDSL(pipe
);
1013 unsigned long timeout
= jiffies
+ msecs_to_jiffies(100);
1016 line_mask
= DSL_LINEMASK_GEN2
;
1018 line_mask
= DSL_LINEMASK_GEN3
;
1020 /* Wait for the display line to settle */
1022 last_line
= I915_READ(reg
) & line_mask
;
1024 } while (((I915_READ(reg
) & line_mask
) != last_line
) &&
1025 time_after(timeout
, jiffies
));
1026 if (time_after(jiffies
, timeout
))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1031 static const char *state_string(bool enabled
)
1033 return enabled
? "on" : "off";
1036 /* Only for pre-ILK configs */
1037 static void assert_pll(struct drm_i915_private
*dev_priv
,
1038 enum pipe pipe
, bool state
)
1045 val
= I915_READ(reg
);
1046 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1047 WARN(cur_state
!= state
,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state
), state_string(cur_state
));
1051 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055 static void assert_pch_pll(struct drm_i915_private
*dev_priv
,
1056 struct intel_pch_pll
*pll
,
1057 struct intel_crtc
*crtc
,
1063 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1069 "asserting PCH PLL %s with no PLL\n", state_string(state
)))
1072 val
= I915_READ(pll
->pll_reg
);
1073 cur_state
= !!(val
& DPLL_VCO_ENABLE
);
1074 WARN(cur_state
!= state
,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll
->pll_reg
, state_string(state
), state_string(cur_state
), val
);
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc
&& HAS_PCH_CPT(dev_priv
->dev
)) {
1082 pch_dpll
= I915_READ(PCH_DPLL_SEL
);
1083 cur_state
= pll
->pll_reg
== _PCH_DPLL_B
;
1084 if (!WARN(((pch_dpll
>> (4 * crtc
->pipe
)) & 1) != cur_state
,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state
, crtc
->pipe
, pch_dpll
)) {
1087 cur_state
= !!(val
>> (4*crtc
->pipe
+ 3));
1088 WARN(cur_state
!= state
,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll
->pll_reg
== _PCH_DPLL_B
,
1091 state_string(state
),
1097 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1100 static void assert_fdi_tx(struct drm_i915_private
*dev_priv
,
1101 enum pipe pipe
, bool state
)
1107 if (IS_HASWELL(dev_priv
->dev
)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg
= DDI_FUNC_CTL(pipe
);
1110 val
= I915_READ(reg
);
1111 cur_state
= !!(val
& PIPE_DDI_FUNC_ENABLE
);
1113 reg
= FDI_TX_CTL(pipe
);
1114 val
= I915_READ(reg
);
1115 cur_state
= !!(val
& FDI_TX_ENABLE
);
1117 WARN(cur_state
!= state
,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state
), state_string(cur_state
));
1121 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1124 static void assert_fdi_rx(struct drm_i915_private
*dev_priv
,
1125 enum pipe pipe
, bool state
)
1131 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1135 reg
= FDI_RX_CTL(pipe
);
1136 val
= I915_READ(reg
);
1137 cur_state
= !!(val
& FDI_RX_ENABLE
);
1139 WARN(cur_state
!= state
,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state
), state_string(cur_state
));
1143 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1146 static void assert_fdi_tx_pll_enabled(struct drm_i915_private
*dev_priv
,
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv
->info
->gen
== 5)
1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv
->dev
))
1160 reg
= FDI_TX_CTL(pipe
);
1161 val
= I915_READ(reg
);
1162 WARN(!(val
& FDI_TX_PLL_ENABLE
), "FDI TX PLL assertion failure, should be active but is disabled\n");
1165 static void assert_fdi_rx_pll_enabled(struct drm_i915_private
*dev_priv
,
1171 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1175 reg
= FDI_RX_CTL(pipe
);
1176 val
= I915_READ(reg
);
1177 WARN(!(val
& FDI_RX_PLL_ENABLE
), "FDI RX PLL assertion failure, should be active but is disabled\n");
1180 static void assert_panel_unlocked(struct drm_i915_private
*dev_priv
,
1183 int pp_reg
, lvds_reg
;
1185 enum pipe panel_pipe
= PIPE_A
;
1188 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1189 pp_reg
= PCH_PP_CONTROL
;
1190 lvds_reg
= PCH_LVDS
;
1192 pp_reg
= PP_CONTROL
;
1196 val
= I915_READ(pp_reg
);
1197 if (!(val
& PANEL_POWER_ON
) ||
1198 ((val
& PANEL_UNLOCK_REGS
) == PANEL_UNLOCK_REGS
))
1201 if (I915_READ(lvds_reg
) & LVDS_PIPEB_SELECT
)
1202 panel_pipe
= PIPE_B
;
1204 WARN(panel_pipe
== pipe
&& locked
,
1205 "panel assertion failure, pipe %c regs locked\n",
1209 void assert_pipe(struct drm_i915_private
*dev_priv
,
1210 enum pipe pipe
, bool state
)
1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe
== PIPE_A
&& dev_priv
->quirks
& QUIRK_PIPEA_FORCE
)
1220 reg
= PIPECONF(pipe
);
1221 val
= I915_READ(reg
);
1222 cur_state
= !!(val
& PIPECONF_ENABLE
);
1223 WARN(cur_state
!= state
,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
1225 pipe_name(pipe
), state_string(state
), state_string(cur_state
));
1228 static void assert_plane(struct drm_i915_private
*dev_priv
,
1229 enum plane plane
, bool state
)
1235 reg
= DSPCNTR(plane
);
1236 val
= I915_READ(reg
);
1237 cur_state
= !!(val
& DISPLAY_PLANE_ENABLE
);
1238 WARN(cur_state
!= state
,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane
), state_string(state
), state_string(cur_state
));
1243 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1246 static void assert_planes_disabled(struct drm_i915_private
*dev_priv
,
1253 /* Planes are fixed to pipes on ILK+ */
1254 if (HAS_PCH_SPLIT(dev_priv
->dev
)) {
1255 reg
= DSPCNTR(pipe
);
1256 val
= I915_READ(reg
);
1257 WARN((val
& DISPLAY_PLANE_ENABLE
),
1258 "plane %c assertion failure, should be disabled but not\n",
1263 /* Need to check both planes against the pipe */
1264 for (i
= 0; i
< 2; i
++) {
1266 val
= I915_READ(reg
);
1267 cur_pipe
= (val
& DISPPLANE_SEL_PIPE_MASK
) >>
1268 DISPPLANE_SEL_PIPE_SHIFT
;
1269 WARN((val
& DISPLAY_PLANE_ENABLE
) && pipe
== cur_pipe
,
1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i
), pipe_name(pipe
));
1275 static void assert_pch_refclk_enabled(struct drm_i915_private
*dev_priv
)
1280 if (HAS_PCH_LPT(dev_priv
->dev
)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 val
= I915_READ(PCH_DREF_CONTROL
);
1286 enabled
= !!(val
& (DREF_SSC_SOURCE_MASK
| DREF_NONSPREAD_SOURCE_MASK
|
1287 DREF_SUPERSPREAD_SOURCE_MASK
));
1288 WARN(!enabled
, "PCH refclk assertion failure, should be active but is disabled\n");
1291 static void assert_transcoder_disabled(struct drm_i915_private
*dev_priv
,
1298 reg
= TRANSCONF(pipe
);
1299 val
= I915_READ(reg
);
1300 enabled
= !!(val
& TRANS_ENABLE
);
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 static bool dp_pipe_enabled(struct drm_i915_private
*dev_priv
,
1307 enum pipe pipe
, u32 port_sel
, u32 val
)
1309 if ((val
& DP_PORT_EN
) == 0)
1312 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1313 u32 trans_dp_ctl_reg
= TRANS_DP_CTL(pipe
);
1314 u32 trans_dp_ctl
= I915_READ(trans_dp_ctl_reg
);
1315 if ((trans_dp_ctl
& TRANS_DP_PORT_SEL_MASK
) != port_sel
)
1318 if ((val
& DP_PIPE_MASK
) != (pipe
<< 30))
1324 static bool hdmi_pipe_enabled(struct drm_i915_private
*dev_priv
,
1325 enum pipe pipe
, u32 val
)
1327 if ((val
& PORT_ENABLE
) == 0)
1330 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1331 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1334 if ((val
& TRANSCODER_MASK
) != TRANSCODER(pipe
))
1340 static bool lvds_pipe_enabled(struct drm_i915_private
*dev_priv
,
1341 enum pipe pipe
, u32 val
)
1343 if ((val
& LVDS_PORT_EN
) == 0)
1346 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1347 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1350 if ((val
& LVDS_PIPE_MASK
) != LVDS_PIPE(pipe
))
1356 static bool adpa_pipe_enabled(struct drm_i915_private
*dev_priv
,
1357 enum pipe pipe
, u32 val
)
1359 if ((val
& ADPA_DAC_ENABLE
) == 0)
1361 if (HAS_PCH_CPT(dev_priv
->dev
)) {
1362 if ((val
& PORT_TRANS_SEL_MASK
) != PORT_TRANS_SEL_CPT(pipe
))
1365 if ((val
& ADPA_PIPE_SELECT_MASK
) != ADPA_PIPE_SELECT(pipe
))
1371 static void assert_pch_dp_disabled(struct drm_i915_private
*dev_priv
,
1372 enum pipe pipe
, int reg
, u32 port_sel
)
1374 u32 val
= I915_READ(reg
);
1375 WARN(dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
),
1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1377 reg
, pipe_name(pipe
));
1379 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_PIPE_B_SELECT
),
1380 "IBX PCH dp port still using transcoder B\n");
1383 static void assert_pch_hdmi_disabled(struct drm_i915_private
*dev_priv
,
1384 enum pipe pipe
, int reg
)
1386 u32 val
= I915_READ(reg
);
1387 WARN(hdmi_pipe_enabled(dev_priv
, val
, pipe
),
1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1389 reg
, pipe_name(pipe
));
1391 WARN(HAS_PCH_IBX(dev_priv
->dev
) && (val
& SDVO_PIPE_B_SELECT
),
1392 "IBX PCH hdmi port still using transcoder B\n");
1395 static void assert_pch_ports_disabled(struct drm_i915_private
*dev_priv
,
1401 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1402 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1403 assert_pch_dp_disabled(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1406 val
= I915_READ(reg
);
1407 WARN(adpa_pipe_enabled(dev_priv
, val
, pipe
),
1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
1412 val
= I915_READ(reg
);
1413 WARN(lvds_pipe_enabled(dev_priv
, val
, pipe
),
1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
1417 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIB
);
1418 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMIC
);
1419 assert_pch_hdmi_disabled(dev_priv
, pipe
, HDMID
);
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1431 * Note! This is for pre-ILK only.
1433 static void intel_enable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1438 /* No really, not for ILK+ */
1439 BUG_ON(!IS_VALLEYVIEW(dev_priv
->dev
) && dev_priv
->info
->gen
>= 5);
1441 /* PLL is protected by panel, make sure we can write it */
1442 if (IS_MOBILE(dev_priv
->dev
) && !IS_I830(dev_priv
->dev
))
1443 assert_panel_unlocked(dev_priv
, pipe
);
1446 val
= I915_READ(reg
);
1447 val
|= DPLL_VCO_ENABLE
;
1449 /* We do this three times for luck */
1450 I915_WRITE(reg
, val
);
1452 udelay(150); /* wait for warmup */
1453 I915_WRITE(reg
, val
);
1455 udelay(150); /* wait for warmup */
1456 I915_WRITE(reg
, val
);
1458 udelay(150); /* wait for warmup */
1462 * intel_disable_pll - disable a PLL
1463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1468 * Note! This is for pre-ILK only.
1470 static void intel_disable_pll(struct drm_i915_private
*dev_priv
, enum pipe pipe
)
1475 /* Don't disable pipe A or pipe A PLLs if needed */
1476 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1479 /* Make sure the pipe isn't still relying on us */
1480 assert_pipe_disabled(dev_priv
, pipe
);
1483 val
= I915_READ(reg
);
1484 val
&= ~DPLL_VCO_ENABLE
;
1485 I915_WRITE(reg
, val
);
1491 intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
)
1493 unsigned long flags
;
1495 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1496 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1498 DRM_ERROR("timeout waiting for SBI to become ready\n");
1502 I915_WRITE(SBI_ADDR
,
1504 I915_WRITE(SBI_DATA
,
1506 I915_WRITE(SBI_CTL_STAT
,
1510 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1512 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1517 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1521 intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
)
1523 unsigned long flags
;
1526 spin_lock_irqsave(&dev_priv
->dpio_lock
, flags
);
1527 if (wait_for((I915_READ(SBI_CTL_STAT
) & SBI_BUSY
) == 0,
1529 DRM_ERROR("timeout waiting for SBI to become ready\n");
1533 I915_WRITE(SBI_ADDR
,
1535 I915_WRITE(SBI_CTL_STAT
,
1539 if (wait_for((I915_READ(SBI_CTL_STAT
) & (SBI_BUSY
| SBI_RESPONSE_FAIL
)) == 0,
1541 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1545 value
= I915_READ(SBI_DATA
);
1548 spin_unlock_irqrestore(&dev_priv
->dpio_lock
, flags
);
1553 * intel_enable_pch_pll - enable PCH PLL
1554 * @dev_priv: i915 private structure
1555 * @pipe: pipe PLL to enable
1557 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1558 * drives the transcoder clock.
1560 static void intel_enable_pch_pll(struct intel_crtc
*intel_crtc
)
1562 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1563 struct intel_pch_pll
*pll
;
1567 /* PCH PLLs only available on ILK, SNB and IVB */
1568 BUG_ON(dev_priv
->info
->gen
< 5);
1569 pll
= intel_crtc
->pch_pll
;
1573 if (WARN_ON(pll
->refcount
== 0))
1576 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1577 pll
->pll_reg
, pll
->active
, pll
->on
,
1578 intel_crtc
->base
.base
.id
);
1580 /* PCH refclock must be enabled first */
1581 assert_pch_refclk_enabled(dev_priv
);
1583 if (pll
->active
++ && pll
->on
) {
1584 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1588 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll
->pll_reg
);
1591 val
= I915_READ(reg
);
1592 val
|= DPLL_VCO_ENABLE
;
1593 I915_WRITE(reg
, val
);
1600 static void intel_disable_pch_pll(struct intel_crtc
*intel_crtc
)
1602 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
1603 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
1607 /* PCH only available on ILK+ */
1608 BUG_ON(dev_priv
->info
->gen
< 5);
1612 if (WARN_ON(pll
->refcount
== 0))
1615 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1616 pll
->pll_reg
, pll
->active
, pll
->on
,
1617 intel_crtc
->base
.base
.id
);
1619 if (WARN_ON(pll
->active
== 0)) {
1620 assert_pch_pll_disabled(dev_priv
, pll
, NULL
);
1624 if (--pll
->active
) {
1625 assert_pch_pll_enabled(dev_priv
, pll
, NULL
);
1629 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll
->pll_reg
);
1631 /* Make sure transcoder isn't still depending on us */
1632 assert_transcoder_disabled(dev_priv
, intel_crtc
->pipe
);
1635 val
= I915_READ(reg
);
1636 val
&= ~DPLL_VCO_ENABLE
;
1637 I915_WRITE(reg
, val
);
1644 static void intel_enable_transcoder(struct drm_i915_private
*dev_priv
,
1648 u32 val
, pipeconf_val
;
1649 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
1651 /* PCH only available on ILK+ */
1652 BUG_ON(dev_priv
->info
->gen
< 5);
1654 /* Make sure PCH DPLL is enabled */
1655 assert_pch_pll_enabled(dev_priv
,
1656 to_intel_crtc(crtc
)->pch_pll
,
1657 to_intel_crtc(crtc
));
1659 /* FDI must be feeding us bits for PCH ports */
1660 assert_fdi_tx_enabled(dev_priv
, pipe
);
1661 assert_fdi_rx_enabled(dev_priv
, pipe
);
1663 if (IS_HASWELL(dev_priv
->dev
) && pipe
> 0) {
1664 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 reg
= TRANSCONF(pipe
);
1668 val
= I915_READ(reg
);
1669 pipeconf_val
= I915_READ(PIPECONF(pipe
));
1671 if (HAS_PCH_IBX(dev_priv
->dev
)) {
1673 * make the BPC in transcoder be consistent with
1674 * that in pipeconf reg.
1676 val
&= ~PIPE_BPC_MASK
;
1677 val
|= pipeconf_val
& PIPE_BPC_MASK
;
1680 val
&= ~TRANS_INTERLACE_MASK
;
1681 if ((pipeconf_val
& PIPECONF_INTERLACE_MASK
) == PIPECONF_INTERLACED_ILK
)
1682 if (HAS_PCH_IBX(dev_priv
->dev
) &&
1683 intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
))
1684 val
|= TRANS_LEGACY_INTERLACED_ILK
;
1686 val
|= TRANS_INTERLACED
;
1688 val
|= TRANS_PROGRESSIVE
;
1690 I915_WRITE(reg
, val
| TRANS_ENABLE
);
1691 if (wait_for(I915_READ(reg
) & TRANS_STATE_ENABLE
, 100))
1692 DRM_ERROR("failed to enable transcoder %d\n", pipe
);
1695 static void intel_disable_transcoder(struct drm_i915_private
*dev_priv
,
1701 /* FDI relies on the transcoder */
1702 assert_fdi_tx_disabled(dev_priv
, pipe
);
1703 assert_fdi_rx_disabled(dev_priv
, pipe
);
1705 /* Ports must be off as well */
1706 assert_pch_ports_disabled(dev_priv
, pipe
);
1708 reg
= TRANSCONF(pipe
);
1709 val
= I915_READ(reg
);
1710 val
&= ~TRANS_ENABLE
;
1711 I915_WRITE(reg
, val
);
1712 /* wait for PCH transcoder off, transcoder state */
1713 if (wait_for((I915_READ(reg
) & TRANS_STATE_ENABLE
) == 0, 50))
1714 DRM_ERROR("failed to disable transcoder %d\n", pipe
);
1718 * intel_enable_pipe - enable a pipe, asserting requirements
1719 * @dev_priv: i915 private structure
1720 * @pipe: pipe to enable
1721 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1723 * Enable @pipe, making sure that various hardware specific requirements
1724 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1726 * @pipe should be %PIPE_A or %PIPE_B.
1728 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 static void intel_enable_pipe(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
1738 * A pipe without a PLL won't actually be able to drive bits from
1739 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 if (!HAS_PCH_SPLIT(dev_priv
->dev
))
1743 assert_pll_enabled(dev_priv
, pipe
);
1746 /* if driving the PCH, we need FDI enabled */
1747 assert_fdi_rx_pll_enabled(dev_priv
, pipe
);
1748 assert_fdi_tx_pll_enabled(dev_priv
, pipe
);
1750 /* FIXME: assert CPU port conditions for SNB+ */
1753 reg
= PIPECONF(pipe
);
1754 val
= I915_READ(reg
);
1755 if (val
& PIPECONF_ENABLE
)
1758 I915_WRITE(reg
, val
| PIPECONF_ENABLE
);
1759 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1763 * intel_disable_pipe - disable a pipe, asserting requirements
1764 * @dev_priv: i915 private structure
1765 * @pipe: pipe to disable
1767 * Disable @pipe, making sure that various hardware specific requirements
1768 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1770 * @pipe should be %PIPE_A or %PIPE_B.
1772 * Will wait until the pipe has shut down before returning.
1774 static void intel_disable_pipe(struct drm_i915_private
*dev_priv
,
1781 * Make sure planes won't keep trying to pump pixels to us,
1782 * or we might hang the display.
1784 assert_planes_disabled(dev_priv
, pipe
);
1786 /* Don't disable pipe A or pipe A PLLs if needed */
1787 if (pipe
== PIPE_A
&& (dev_priv
->quirks
& QUIRK_PIPEA_FORCE
))
1790 reg
= PIPECONF(pipe
);
1791 val
= I915_READ(reg
);
1792 if ((val
& PIPECONF_ENABLE
) == 0)
1795 I915_WRITE(reg
, val
& ~PIPECONF_ENABLE
);
1796 intel_wait_for_pipe_off(dev_priv
->dev
, pipe
);
1800 * Plane regs are double buffered, going from enabled->disabled needs a
1801 * trigger in order to latch. The display address reg provides this.
1803 void intel_flush_display_plane(struct drm_i915_private
*dev_priv
,
1806 I915_WRITE(DSPADDR(plane
), I915_READ(DSPADDR(plane
)));
1807 I915_WRITE(DSPSURF(plane
), I915_READ(DSPSURF(plane
)));
1811 * intel_enable_plane - enable a display plane on a given pipe
1812 * @dev_priv: i915 private structure
1813 * @plane: plane to enable
1814 * @pipe: pipe being fed
1816 * Enable @plane on @pipe, making sure that @pipe is running first.
1818 static void intel_enable_plane(struct drm_i915_private
*dev_priv
,
1819 enum plane plane
, enum pipe pipe
)
1824 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1825 assert_pipe_enabled(dev_priv
, pipe
);
1827 reg
= DSPCNTR(plane
);
1828 val
= I915_READ(reg
);
1829 if (val
& DISPLAY_PLANE_ENABLE
)
1832 I915_WRITE(reg
, val
| DISPLAY_PLANE_ENABLE
);
1833 intel_flush_display_plane(dev_priv
, plane
);
1834 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1838 * intel_disable_plane - disable a display plane
1839 * @dev_priv: i915 private structure
1840 * @plane: plane to disable
1841 * @pipe: pipe consuming the data
1843 * Disable @plane; should be an independent operation.
1845 static void intel_disable_plane(struct drm_i915_private
*dev_priv
,
1846 enum plane plane
, enum pipe pipe
)
1851 reg
= DSPCNTR(plane
);
1852 val
= I915_READ(reg
);
1853 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
1856 I915_WRITE(reg
, val
& ~DISPLAY_PLANE_ENABLE
);
1857 intel_flush_display_plane(dev_priv
, plane
);
1858 intel_wait_for_vblank(dev_priv
->dev
, pipe
);
1861 static void disable_pch_dp(struct drm_i915_private
*dev_priv
,
1862 enum pipe pipe
, int reg
, u32 port_sel
)
1864 u32 val
= I915_READ(reg
);
1865 if (dp_pipe_enabled(dev_priv
, pipe
, port_sel
, val
)) {
1866 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg
, pipe
);
1867 I915_WRITE(reg
, val
& ~DP_PORT_EN
);
1871 static void disable_pch_hdmi(struct drm_i915_private
*dev_priv
,
1872 enum pipe pipe
, int reg
)
1874 u32 val
= I915_READ(reg
);
1875 if (hdmi_pipe_enabled(dev_priv
, val
, pipe
)) {
1876 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1878 I915_WRITE(reg
, val
& ~PORT_ENABLE
);
1882 /* Disable any ports connected to this transcoder */
1883 static void intel_disable_pch_ports(struct drm_i915_private
*dev_priv
,
1888 val
= I915_READ(PCH_PP_CONTROL
);
1889 I915_WRITE(PCH_PP_CONTROL
, val
| PANEL_UNLOCK_REGS
);
1891 disable_pch_dp(dev_priv
, pipe
, PCH_DP_B
, TRANS_DP_PORT_SEL_B
);
1892 disable_pch_dp(dev_priv
, pipe
, PCH_DP_C
, TRANS_DP_PORT_SEL_C
);
1893 disable_pch_dp(dev_priv
, pipe
, PCH_DP_D
, TRANS_DP_PORT_SEL_D
);
1896 val
= I915_READ(reg
);
1897 if (adpa_pipe_enabled(dev_priv
, val
, pipe
))
1898 I915_WRITE(reg
, val
& ~ADPA_DAC_ENABLE
);
1901 val
= I915_READ(reg
);
1902 if (lvds_pipe_enabled(dev_priv
, val
, pipe
)) {
1903 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe
, val
);
1904 I915_WRITE(reg
, val
& ~LVDS_PORT_EN
);
1909 disable_pch_hdmi(dev_priv
, pipe
, HDMIB
);
1910 disable_pch_hdmi(dev_priv
, pipe
, HDMIC
);
1911 disable_pch_hdmi(dev_priv
, pipe
, HDMID
);
1915 intel_pin_and_fence_fb_obj(struct drm_device
*dev
,
1916 struct drm_i915_gem_object
*obj
,
1917 struct intel_ring_buffer
*pipelined
)
1919 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1923 switch (obj
->tiling_mode
) {
1924 case I915_TILING_NONE
:
1925 if (IS_BROADWATER(dev
) || IS_CRESTLINE(dev
))
1926 alignment
= 128 * 1024;
1927 else if (INTEL_INFO(dev
)->gen
>= 4)
1928 alignment
= 4 * 1024;
1930 alignment
= 64 * 1024;
1933 /* pin() will align the object as required by fence */
1937 /* FIXME: Is this true? */
1938 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1944 dev_priv
->mm
.interruptible
= false;
1945 ret
= i915_gem_object_pin_to_display_plane(obj
, alignment
, pipelined
);
1947 goto err_interruptible
;
1949 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1950 * fence, whereas 965+ only requires a fence if using
1951 * framebuffer compression. For simplicity, we always install
1952 * a fence as the cost is not that onerous.
1954 ret
= i915_gem_object_get_fence(obj
);
1958 i915_gem_object_pin_fence(obj
);
1960 dev_priv
->mm
.interruptible
= true;
1964 i915_gem_object_unpin(obj
);
1966 dev_priv
->mm
.interruptible
= true;
1970 void intel_unpin_fb_obj(struct drm_i915_gem_object
*obj
)
1972 i915_gem_object_unpin_fence(obj
);
1973 i915_gem_object_unpin(obj
);
1976 static int i9xx_update_plane(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
1979 struct drm_device
*dev
= crtc
->dev
;
1980 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1981 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
1982 struct intel_framebuffer
*intel_fb
;
1983 struct drm_i915_gem_object
*obj
;
1984 int plane
= intel_crtc
->plane
;
1985 unsigned long Start
, Offset
;
1994 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
1998 intel_fb
= to_intel_framebuffer(fb
);
1999 obj
= intel_fb
->obj
;
2001 reg
= DSPCNTR(plane
);
2002 dspcntr
= I915_READ(reg
);
2003 /* Mask out pixel format bits in case we change it */
2004 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2005 switch (fb
->bits_per_pixel
) {
2007 dspcntr
|= DISPPLANE_8BPP
;
2010 if (fb
->depth
== 15)
2011 dspcntr
|= DISPPLANE_15_16BPP
;
2013 dspcntr
|= DISPPLANE_16BPP
;
2017 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2020 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2023 if (INTEL_INFO(dev
)->gen
>= 4) {
2024 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2025 dspcntr
|= DISPPLANE_TILED
;
2027 dspcntr
&= ~DISPPLANE_TILED
;
2030 I915_WRITE(reg
, dspcntr
);
2032 Start
= obj
->gtt_offset
;
2033 Offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2035 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2036 Start
, Offset
, x
, y
, fb
->pitches
[0]);
2037 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2038 if (INTEL_INFO(dev
)->gen
>= 4) {
2039 I915_MODIFY_DISPBASE(DSPSURF(plane
), Start
);
2040 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2041 I915_WRITE(DSPADDR(plane
), Offset
);
2043 I915_WRITE(DSPADDR(plane
), Start
+ Offset
);
2049 static int ironlake_update_plane(struct drm_crtc
*crtc
,
2050 struct drm_framebuffer
*fb
, int x
, int y
)
2052 struct drm_device
*dev
= crtc
->dev
;
2053 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2054 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2055 struct intel_framebuffer
*intel_fb
;
2056 struct drm_i915_gem_object
*obj
;
2057 int plane
= intel_crtc
->plane
;
2058 unsigned long Start
, Offset
;
2068 DRM_ERROR("Can't update plane %d in SAREA\n", plane
);
2072 intel_fb
= to_intel_framebuffer(fb
);
2073 obj
= intel_fb
->obj
;
2075 reg
= DSPCNTR(plane
);
2076 dspcntr
= I915_READ(reg
);
2077 /* Mask out pixel format bits in case we change it */
2078 dspcntr
&= ~DISPPLANE_PIXFORMAT_MASK
;
2079 switch (fb
->bits_per_pixel
) {
2081 dspcntr
|= DISPPLANE_8BPP
;
2084 if (fb
->depth
!= 16)
2087 dspcntr
|= DISPPLANE_16BPP
;
2091 if (fb
->depth
== 24)
2092 dspcntr
|= DISPPLANE_32BPP_NO_ALPHA
;
2093 else if (fb
->depth
== 30)
2094 dspcntr
|= DISPPLANE_32BPP_30BIT_NO_ALPHA
;
2099 DRM_ERROR("Unknown color depth %d\n", fb
->bits_per_pixel
);
2103 if (obj
->tiling_mode
!= I915_TILING_NONE
)
2104 dspcntr
|= DISPPLANE_TILED
;
2106 dspcntr
&= ~DISPPLANE_TILED
;
2109 dspcntr
|= DISPPLANE_TRICKLE_FEED_DISABLE
;
2111 I915_WRITE(reg
, dspcntr
);
2113 Start
= obj
->gtt_offset
;
2114 Offset
= y
* fb
->pitches
[0] + x
* (fb
->bits_per_pixel
/ 8);
2116 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2117 Start
, Offset
, x
, y
, fb
->pitches
[0]);
2118 I915_WRITE(DSPSTRIDE(plane
), fb
->pitches
[0]);
2119 I915_MODIFY_DISPBASE(DSPSURF(plane
), Start
);
2120 I915_WRITE(DSPTILEOFF(plane
), (y
<< 16) | x
);
2121 I915_WRITE(DSPADDR(plane
), Offset
);
2127 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2129 intel_pipe_set_base_atomic(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
2130 int x
, int y
, enum mode_set_atomic state
)
2132 struct drm_device
*dev
= crtc
->dev
;
2133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2135 if (dev_priv
->display
.disable_fbc
)
2136 dev_priv
->display
.disable_fbc(dev
);
2137 intel_increase_pllclock(crtc
);
2139 return dev_priv
->display
.update_plane(crtc
, fb
, x
, y
);
2143 intel_finish_fb(struct drm_framebuffer
*old_fb
)
2145 struct drm_i915_gem_object
*obj
= to_intel_framebuffer(old_fb
)->obj
;
2146 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2147 bool was_interruptible
= dev_priv
->mm
.interruptible
;
2150 wait_event(dev_priv
->pending_flip_queue
,
2151 atomic_read(&dev_priv
->mm
.wedged
) ||
2152 atomic_read(&obj
->pending_flip
) == 0);
2154 /* Big Hammer, we also need to ensure that any pending
2155 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2156 * current scanout is retired before unpinning the old
2159 * This should only fail upon a hung GPU, in which case we
2160 * can safely continue.
2162 dev_priv
->mm
.interruptible
= false;
2163 ret
= i915_gem_object_finish_gpu(obj
);
2164 dev_priv
->mm
.interruptible
= was_interruptible
;
2170 intel_pipe_set_base(struct drm_crtc
*crtc
, int x
, int y
,
2171 struct drm_framebuffer
*old_fb
)
2173 struct drm_device
*dev
= crtc
->dev
;
2174 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2175 struct drm_i915_master_private
*master_priv
;
2176 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2181 DRM_ERROR("No FB bound\n");
2185 if(intel_crtc
->plane
> dev_priv
->num_pipe
) {
2186 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2188 dev_priv
->num_pipe
);
2192 mutex_lock(&dev
->struct_mutex
);
2193 ret
= intel_pin_and_fence_fb_obj(dev
,
2194 to_intel_framebuffer(crtc
->fb
)->obj
,
2197 mutex_unlock(&dev
->struct_mutex
);
2198 DRM_ERROR("pin & fence failed\n");
2203 intel_finish_fb(old_fb
);
2205 ret
= dev_priv
->display
.update_plane(crtc
, crtc
->fb
, x
, y
);
2207 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
2208 mutex_unlock(&dev
->struct_mutex
);
2209 DRM_ERROR("failed to update base address\n");
2214 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
2215 intel_unpin_fb_obj(to_intel_framebuffer(old_fb
)->obj
);
2218 intel_update_fbc(dev
);
2219 mutex_unlock(&dev
->struct_mutex
);
2221 if (!dev
->primary
->master
)
2224 master_priv
= dev
->primary
->master
->driver_priv
;
2225 if (!master_priv
->sarea_priv
)
2228 if (intel_crtc
->pipe
) {
2229 master_priv
->sarea_priv
->pipeB_x
= x
;
2230 master_priv
->sarea_priv
->pipeB_y
= y
;
2232 master_priv
->sarea_priv
->pipeA_x
= x
;
2233 master_priv
->sarea_priv
->pipeA_y
= y
;
2239 static void ironlake_set_pll_edp(struct drm_crtc
*crtc
, int clock
)
2241 struct drm_device
*dev
= crtc
->dev
;
2242 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2245 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock
);
2246 dpa_ctl
= I915_READ(DP_A
);
2247 dpa_ctl
&= ~DP_PLL_FREQ_MASK
;
2249 if (clock
< 200000) {
2251 dpa_ctl
|= DP_PLL_FREQ_160MHZ
;
2252 /* workaround for 160Mhz:
2253 1) program 0x4600c bits 15:0 = 0x8124
2254 2) program 0x46010 bit 0 = 1
2255 3) program 0x46034 bit 24 = 1
2256 4) program 0x64000 bit 14 = 1
2258 temp
= I915_READ(0x4600c);
2260 I915_WRITE(0x4600c, temp
| 0x8124);
2262 temp
= I915_READ(0x46010);
2263 I915_WRITE(0x46010, temp
| 1);
2265 temp
= I915_READ(0x46034);
2266 I915_WRITE(0x46034, temp
| (1 << 24));
2268 dpa_ctl
|= DP_PLL_FREQ_270MHZ
;
2270 I915_WRITE(DP_A
, dpa_ctl
);
2276 static void intel_fdi_normal_train(struct drm_crtc
*crtc
)
2278 struct drm_device
*dev
= crtc
->dev
;
2279 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2280 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2281 int pipe
= intel_crtc
->pipe
;
2284 /* enable normal train */
2285 reg
= FDI_TX_CTL(pipe
);
2286 temp
= I915_READ(reg
);
2287 if (IS_IVYBRIDGE(dev
)) {
2288 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2289 temp
|= FDI_LINK_TRAIN_NONE_IVB
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2291 temp
&= ~FDI_LINK_TRAIN_NONE
;
2292 temp
|= FDI_LINK_TRAIN_NONE
| FDI_TX_ENHANCE_FRAME_ENABLE
;
2294 I915_WRITE(reg
, temp
);
2296 reg
= FDI_RX_CTL(pipe
);
2297 temp
= I915_READ(reg
);
2298 if (HAS_PCH_CPT(dev
)) {
2299 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2300 temp
|= FDI_LINK_TRAIN_NORMAL_CPT
;
2302 temp
&= ~FDI_LINK_TRAIN_NONE
;
2303 temp
|= FDI_LINK_TRAIN_NONE
;
2305 I915_WRITE(reg
, temp
| FDI_RX_ENHANCE_FRAME_ENABLE
);
2307 /* wait one idle pattern time */
2311 /* IVB wants error correction enabled */
2312 if (IS_IVYBRIDGE(dev
))
2313 I915_WRITE(reg
, I915_READ(reg
) | FDI_FS_ERRC_ENABLE
|
2314 FDI_FE_ERRC_ENABLE
);
2317 static void cpt_phase_pointer_enable(struct drm_device
*dev
, int pipe
)
2319 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2320 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2322 flags
|= FDI_PHASE_SYNC_OVR(pipe
);
2323 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to unlock... */
2324 flags
|= FDI_PHASE_SYNC_EN(pipe
);
2325 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to enable */
2326 POSTING_READ(SOUTH_CHICKEN1
);
2329 /* The FDI link training functions for ILK/Ibexpeak. */
2330 static void ironlake_fdi_link_train(struct drm_crtc
*crtc
)
2332 struct drm_device
*dev
= crtc
->dev
;
2333 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2334 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2335 int pipe
= intel_crtc
->pipe
;
2336 int plane
= intel_crtc
->plane
;
2337 u32 reg
, temp
, tries
;
2339 /* FDI needs bits from pipe & plane first */
2340 assert_pipe_enabled(dev_priv
, pipe
);
2341 assert_plane_enabled(dev_priv
, plane
);
2343 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2345 reg
= FDI_RX_IMR(pipe
);
2346 temp
= I915_READ(reg
);
2347 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2348 temp
&= ~FDI_RX_BIT_LOCK
;
2349 I915_WRITE(reg
, temp
);
2353 /* enable CPU FDI TX and PCH FDI RX */
2354 reg
= FDI_TX_CTL(pipe
);
2355 temp
= I915_READ(reg
);
2357 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2358 temp
&= ~FDI_LINK_TRAIN_NONE
;
2359 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2360 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2362 reg
= FDI_RX_CTL(pipe
);
2363 temp
= I915_READ(reg
);
2364 temp
&= ~FDI_LINK_TRAIN_NONE
;
2365 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2366 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2371 /* Ironlake workaround, enable clock pointer after FDI enable*/
2372 if (HAS_PCH_IBX(dev
)) {
2373 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2374 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
|
2375 FDI_RX_PHASE_SYNC_POINTER_EN
);
2378 reg
= FDI_RX_IIR(pipe
);
2379 for (tries
= 0; tries
< 5; tries
++) {
2380 temp
= I915_READ(reg
);
2381 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2383 if ((temp
& FDI_RX_BIT_LOCK
)) {
2384 DRM_DEBUG_KMS("FDI train 1 done.\n");
2385 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2390 DRM_ERROR("FDI train 1 fail!\n");
2393 reg
= FDI_TX_CTL(pipe
);
2394 temp
= I915_READ(reg
);
2395 temp
&= ~FDI_LINK_TRAIN_NONE
;
2396 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2397 I915_WRITE(reg
, temp
);
2399 reg
= FDI_RX_CTL(pipe
);
2400 temp
= I915_READ(reg
);
2401 temp
&= ~FDI_LINK_TRAIN_NONE
;
2402 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2403 I915_WRITE(reg
, temp
);
2408 reg
= FDI_RX_IIR(pipe
);
2409 for (tries
= 0; tries
< 5; tries
++) {
2410 temp
= I915_READ(reg
);
2411 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2413 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2414 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2415 DRM_DEBUG_KMS("FDI train 2 done.\n");
2420 DRM_ERROR("FDI train 2 fail!\n");
2422 DRM_DEBUG_KMS("FDI train done\n");
2426 static const int snb_b_fdi_train_param
[] = {
2427 FDI_LINK_TRAIN_400MV_0DB_SNB_B
,
2428 FDI_LINK_TRAIN_400MV_6DB_SNB_B
,
2429 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B
,
2430 FDI_LINK_TRAIN_800MV_0DB_SNB_B
,
2433 /* The FDI link training functions for SNB/Cougarpoint. */
2434 static void gen6_fdi_link_train(struct drm_crtc
*crtc
)
2436 struct drm_device
*dev
= crtc
->dev
;
2437 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2438 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2439 int pipe
= intel_crtc
->pipe
;
2440 u32 reg
, temp
, i
, retry
;
2442 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2444 reg
= FDI_RX_IMR(pipe
);
2445 temp
= I915_READ(reg
);
2446 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2447 temp
&= ~FDI_RX_BIT_LOCK
;
2448 I915_WRITE(reg
, temp
);
2453 /* enable CPU FDI TX and PCH FDI RX */
2454 reg
= FDI_TX_CTL(pipe
);
2455 temp
= I915_READ(reg
);
2457 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2458 temp
&= ~FDI_LINK_TRAIN_NONE
;
2459 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2460 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2462 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2463 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2465 reg
= FDI_RX_CTL(pipe
);
2466 temp
= I915_READ(reg
);
2467 if (HAS_PCH_CPT(dev
)) {
2468 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2469 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2471 temp
&= ~FDI_LINK_TRAIN_NONE
;
2472 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2474 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2479 if (HAS_PCH_CPT(dev
))
2480 cpt_phase_pointer_enable(dev
, pipe
);
2482 for (i
= 0; i
< 4; i
++) {
2483 reg
= FDI_TX_CTL(pipe
);
2484 temp
= I915_READ(reg
);
2485 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2486 temp
|= snb_b_fdi_train_param
[i
];
2487 I915_WRITE(reg
, temp
);
2492 for (retry
= 0; retry
< 5; retry
++) {
2493 reg
= FDI_RX_IIR(pipe
);
2494 temp
= I915_READ(reg
);
2495 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2496 if (temp
& FDI_RX_BIT_LOCK
) {
2497 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2498 DRM_DEBUG_KMS("FDI train 1 done.\n");
2507 DRM_ERROR("FDI train 1 fail!\n");
2510 reg
= FDI_TX_CTL(pipe
);
2511 temp
= I915_READ(reg
);
2512 temp
&= ~FDI_LINK_TRAIN_NONE
;
2513 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2515 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2517 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2519 I915_WRITE(reg
, temp
);
2521 reg
= FDI_RX_CTL(pipe
);
2522 temp
= I915_READ(reg
);
2523 if (HAS_PCH_CPT(dev
)) {
2524 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2525 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2527 temp
&= ~FDI_LINK_TRAIN_NONE
;
2528 temp
|= FDI_LINK_TRAIN_PATTERN_2
;
2530 I915_WRITE(reg
, temp
);
2535 for (i
= 0; i
< 4; i
++) {
2536 reg
= FDI_TX_CTL(pipe
);
2537 temp
= I915_READ(reg
);
2538 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2539 temp
|= snb_b_fdi_train_param
[i
];
2540 I915_WRITE(reg
, temp
);
2545 for (retry
= 0; retry
< 5; retry
++) {
2546 reg
= FDI_RX_IIR(pipe
);
2547 temp
= I915_READ(reg
);
2548 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2549 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2550 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2551 DRM_DEBUG_KMS("FDI train 2 done.\n");
2560 DRM_ERROR("FDI train 2 fail!\n");
2562 DRM_DEBUG_KMS("FDI train done.\n");
2565 /* Manual link training for Ivy Bridge A0 parts */
2566 static void ivb_manual_fdi_link_train(struct drm_crtc
*crtc
)
2568 struct drm_device
*dev
= crtc
->dev
;
2569 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2570 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2571 int pipe
= intel_crtc
->pipe
;
2574 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2576 reg
= FDI_RX_IMR(pipe
);
2577 temp
= I915_READ(reg
);
2578 temp
&= ~FDI_RX_SYMBOL_LOCK
;
2579 temp
&= ~FDI_RX_BIT_LOCK
;
2580 I915_WRITE(reg
, temp
);
2585 /* enable CPU FDI TX and PCH FDI RX */
2586 reg
= FDI_TX_CTL(pipe
);
2587 temp
= I915_READ(reg
);
2589 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2590 temp
&= ~(FDI_LINK_TRAIN_AUTO
| FDI_LINK_TRAIN_NONE_IVB
);
2591 temp
|= FDI_LINK_TRAIN_PATTERN_1_IVB
;
2592 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2593 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2594 temp
|= FDI_COMPOSITE_SYNC
;
2595 I915_WRITE(reg
, temp
| FDI_TX_ENABLE
);
2597 reg
= FDI_RX_CTL(pipe
);
2598 temp
= I915_READ(reg
);
2599 temp
&= ~FDI_LINK_TRAIN_AUTO
;
2600 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2601 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2602 temp
|= FDI_COMPOSITE_SYNC
;
2603 I915_WRITE(reg
, temp
| FDI_RX_ENABLE
);
2608 if (HAS_PCH_CPT(dev
))
2609 cpt_phase_pointer_enable(dev
, pipe
);
2611 for (i
= 0; i
< 4; i
++) {
2612 reg
= FDI_TX_CTL(pipe
);
2613 temp
= I915_READ(reg
);
2614 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2615 temp
|= snb_b_fdi_train_param
[i
];
2616 I915_WRITE(reg
, temp
);
2621 reg
= FDI_RX_IIR(pipe
);
2622 temp
= I915_READ(reg
);
2623 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2625 if (temp
& FDI_RX_BIT_LOCK
||
2626 (I915_READ(reg
) & FDI_RX_BIT_LOCK
)) {
2627 I915_WRITE(reg
, temp
| FDI_RX_BIT_LOCK
);
2628 DRM_DEBUG_KMS("FDI train 1 done.\n");
2633 DRM_ERROR("FDI train 1 fail!\n");
2636 reg
= FDI_TX_CTL(pipe
);
2637 temp
= I915_READ(reg
);
2638 temp
&= ~FDI_LINK_TRAIN_NONE_IVB
;
2639 temp
|= FDI_LINK_TRAIN_PATTERN_2_IVB
;
2640 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2641 temp
|= FDI_LINK_TRAIN_400MV_0DB_SNB_B
;
2642 I915_WRITE(reg
, temp
);
2644 reg
= FDI_RX_CTL(pipe
);
2645 temp
= I915_READ(reg
);
2646 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2647 temp
|= FDI_LINK_TRAIN_PATTERN_2_CPT
;
2648 I915_WRITE(reg
, temp
);
2653 for (i
= 0; i
< 4; i
++) {
2654 reg
= FDI_TX_CTL(pipe
);
2655 temp
= I915_READ(reg
);
2656 temp
&= ~FDI_LINK_TRAIN_VOL_EMP_MASK
;
2657 temp
|= snb_b_fdi_train_param
[i
];
2658 I915_WRITE(reg
, temp
);
2663 reg
= FDI_RX_IIR(pipe
);
2664 temp
= I915_READ(reg
);
2665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp
);
2667 if (temp
& FDI_RX_SYMBOL_LOCK
) {
2668 I915_WRITE(reg
, temp
| FDI_RX_SYMBOL_LOCK
);
2669 DRM_DEBUG_KMS("FDI train 2 done.\n");
2674 DRM_ERROR("FDI train 2 fail!\n");
2676 DRM_DEBUG_KMS("FDI train done.\n");
2679 static void ironlake_fdi_pll_enable(struct drm_crtc
*crtc
)
2681 struct drm_device
*dev
= crtc
->dev
;
2682 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2683 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2684 int pipe
= intel_crtc
->pipe
;
2687 /* Write the TU size bits so error detection works */
2688 I915_WRITE(FDI_RX_TUSIZE1(pipe
),
2689 I915_READ(PIPE_DATA_M1(pipe
)) & TU_SIZE_MASK
);
2691 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2692 reg
= FDI_RX_CTL(pipe
);
2693 temp
= I915_READ(reg
);
2694 temp
&= ~((0x7 << 19) | (0x7 << 16));
2695 temp
|= (intel_crtc
->fdi_lanes
- 1) << 19;
2696 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2697 I915_WRITE(reg
, temp
| FDI_RX_PLL_ENABLE
);
2702 /* Switch from Rawclk to PCDclk */
2703 temp
= I915_READ(reg
);
2704 I915_WRITE(reg
, temp
| FDI_PCDCLK
);
2709 /* On Haswell, the PLL configuration for ports and pipes is handled
2710 * separately, as part of DDI setup */
2711 if (!IS_HASWELL(dev
)) {
2712 /* Enable CPU FDI TX PLL, always on for Ironlake */
2713 reg
= FDI_TX_CTL(pipe
);
2714 temp
= I915_READ(reg
);
2715 if ((temp
& FDI_TX_PLL_ENABLE
) == 0) {
2716 I915_WRITE(reg
, temp
| FDI_TX_PLL_ENABLE
);
2724 static void cpt_phase_pointer_disable(struct drm_device
*dev
, int pipe
)
2726 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2727 u32 flags
= I915_READ(SOUTH_CHICKEN1
);
2729 flags
&= ~(FDI_PHASE_SYNC_EN(pipe
));
2730 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* once to disable... */
2731 flags
&= ~(FDI_PHASE_SYNC_OVR(pipe
));
2732 I915_WRITE(SOUTH_CHICKEN1
, flags
); /* then again to lock */
2733 POSTING_READ(SOUTH_CHICKEN1
);
2735 static void ironlake_fdi_disable(struct drm_crtc
*crtc
)
2737 struct drm_device
*dev
= crtc
->dev
;
2738 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2739 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2740 int pipe
= intel_crtc
->pipe
;
2743 /* disable CPU FDI tx and PCH FDI rx */
2744 reg
= FDI_TX_CTL(pipe
);
2745 temp
= I915_READ(reg
);
2746 I915_WRITE(reg
, temp
& ~FDI_TX_ENABLE
);
2749 reg
= FDI_RX_CTL(pipe
);
2750 temp
= I915_READ(reg
);
2751 temp
&= ~(0x7 << 16);
2752 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2753 I915_WRITE(reg
, temp
& ~FDI_RX_ENABLE
);
2758 /* Ironlake workaround, disable clock pointer after downing FDI */
2759 if (HAS_PCH_IBX(dev
)) {
2760 I915_WRITE(FDI_RX_CHICKEN(pipe
), FDI_RX_PHASE_SYNC_POINTER_OVR
);
2761 I915_WRITE(FDI_RX_CHICKEN(pipe
),
2762 I915_READ(FDI_RX_CHICKEN(pipe
) &
2763 ~FDI_RX_PHASE_SYNC_POINTER_EN
));
2764 } else if (HAS_PCH_CPT(dev
)) {
2765 cpt_phase_pointer_disable(dev
, pipe
);
2768 /* still set train pattern 1 */
2769 reg
= FDI_TX_CTL(pipe
);
2770 temp
= I915_READ(reg
);
2771 temp
&= ~FDI_LINK_TRAIN_NONE
;
2772 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2773 I915_WRITE(reg
, temp
);
2775 reg
= FDI_RX_CTL(pipe
);
2776 temp
= I915_READ(reg
);
2777 if (HAS_PCH_CPT(dev
)) {
2778 temp
&= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT
;
2779 temp
|= FDI_LINK_TRAIN_PATTERN_1_CPT
;
2781 temp
&= ~FDI_LINK_TRAIN_NONE
;
2782 temp
|= FDI_LINK_TRAIN_PATTERN_1
;
2784 /* BPC in FDI rx is consistent with that in PIPECONF */
2785 temp
&= ~(0x07 << 16);
2786 temp
|= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) << 11;
2787 I915_WRITE(reg
, temp
);
2793 static void intel_crtc_wait_for_pending_flips(struct drm_crtc
*crtc
)
2795 struct drm_device
*dev
= crtc
->dev
;
2797 if (crtc
->fb
== NULL
)
2800 mutex_lock(&dev
->struct_mutex
);
2801 intel_finish_fb(crtc
->fb
);
2802 mutex_unlock(&dev
->struct_mutex
);
2805 static bool intel_crtc_driving_pch(struct drm_crtc
*crtc
)
2807 struct drm_device
*dev
= crtc
->dev
;
2808 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
2809 struct intel_encoder
*encoder
;
2812 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2813 * must be driven by its own crtc; no sharing is possible.
2815 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
2816 if (encoder
->base
.crtc
!= crtc
)
2819 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2820 * CPU handles all others */
2821 if (IS_HASWELL(dev
)) {
2822 /* It is still unclear how this will work on PPT, so throw up a warning */
2823 WARN_ON(!HAS_PCH_LPT(dev
));
2825 if (encoder
->type
== DRM_MODE_ENCODER_DAC
) {
2826 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2829 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2835 switch (encoder
->type
) {
2836 case INTEL_OUTPUT_EDP
:
2837 if (!intel_encoder_is_pch_edp(&encoder
->base
))
2846 /* Program iCLKIP clock to the desired frequency */
2847 static void lpt_program_iclkip(struct drm_crtc
*crtc
)
2849 struct drm_device
*dev
= crtc
->dev
;
2850 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2851 u32 divsel
, phaseinc
, auxdiv
, phasedir
= 0;
2854 /* It is necessary to ungate the pixclk gate prior to programming
2855 * the divisors, and gate it back when it is done.
2857 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_GATE
);
2859 /* Disable SSCCTL */
2860 intel_sbi_write(dev_priv
, SBI_SSCCTL6
,
2861 intel_sbi_read(dev_priv
, SBI_SSCCTL6
) |
2862 SBI_SSCCTL_DISABLE
);
2864 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2865 if (crtc
->mode
.clock
== 20000) {
2870 /* The iCLK virtual clock root frequency is in MHz,
2871 * but the crtc->mode.clock in in KHz. To get the divisors,
2872 * it is necessary to divide one by another, so we
2873 * convert the virtual clock precision to KHz here for higher
2876 u32 iclk_virtual_root_freq
= 172800 * 1000;
2877 u32 iclk_pi_range
= 64;
2878 u32 desired_divisor
, msb_divisor_value
, pi_value
;
2880 desired_divisor
= (iclk_virtual_root_freq
/ crtc
->mode
.clock
);
2881 msb_divisor_value
= desired_divisor
/ iclk_pi_range
;
2882 pi_value
= desired_divisor
% iclk_pi_range
;
2885 divsel
= msb_divisor_value
- 2;
2886 phaseinc
= pi_value
;
2889 /* This should not happen with any sane values */
2890 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel
) &
2891 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
);
2892 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir
) &
2893 ~SBI_SSCDIVINTPHASE_INCVAL_MASK
);
2895 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2902 /* Program SSCDIVINTPHASE6 */
2903 temp
= intel_sbi_read(dev_priv
, SBI_SSCDIVINTPHASE6
);
2904 temp
&= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK
;
2905 temp
|= SBI_SSCDIVINTPHASE_DIVSEL(divsel
);
2906 temp
&= ~SBI_SSCDIVINTPHASE_INCVAL_MASK
;
2907 temp
|= SBI_SSCDIVINTPHASE_INCVAL(phaseinc
);
2908 temp
|= SBI_SSCDIVINTPHASE_DIR(phasedir
);
2909 temp
|= SBI_SSCDIVINTPHASE_PROPAGATE
;
2911 intel_sbi_write(dev_priv
,
2912 SBI_SSCDIVINTPHASE6
,
2915 /* Program SSCAUXDIV */
2916 temp
= intel_sbi_read(dev_priv
, SBI_SSCAUXDIV6
);
2917 temp
&= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2918 temp
|= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv
);
2919 intel_sbi_write(dev_priv
,
2924 /* Enable modulator and associated divider */
2925 temp
= intel_sbi_read(dev_priv
, SBI_SSCCTL6
);
2926 temp
&= ~SBI_SSCCTL_DISABLE
;
2927 intel_sbi_write(dev_priv
,
2931 /* Wait for initialization time */
2934 I915_WRITE(PIXCLK_GATE
, PIXCLK_GATE_UNGATE
);
2938 * Enable PCH resources required for PCH ports:
2940 * - FDI training & RX/TX
2941 * - update transcoder timings
2942 * - DP transcoding bits
2945 static void ironlake_pch_enable(struct drm_crtc
*crtc
)
2947 struct drm_device
*dev
= crtc
->dev
;
2948 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
2949 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
2950 int pipe
= intel_crtc
->pipe
;
2953 assert_transcoder_disabled(dev_priv
, pipe
);
2955 /* For PCH output, training FDI link */
2956 dev_priv
->display
.fdi_link_train(crtc
);
2958 intel_enable_pch_pll(intel_crtc
);
2960 if (HAS_PCH_LPT(dev
)) {
2961 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2962 lpt_program_iclkip(crtc
);
2963 } else if (HAS_PCH_CPT(dev
)) {
2966 temp
= I915_READ(PCH_DPLL_SEL
);
2970 temp
|= TRANSA_DPLL_ENABLE
;
2971 sel
= TRANSA_DPLLB_SEL
;
2974 temp
|= TRANSB_DPLL_ENABLE
;
2975 sel
= TRANSB_DPLLB_SEL
;
2978 temp
|= TRANSC_DPLL_ENABLE
;
2979 sel
= TRANSC_DPLLB_SEL
;
2982 if (intel_crtc
->pch_pll
->pll_reg
== _PCH_DPLL_B
)
2986 I915_WRITE(PCH_DPLL_SEL
, temp
);
2989 /* set transcoder timing, panel must allow it */
2990 assert_panel_unlocked(dev_priv
, pipe
);
2991 I915_WRITE(TRANS_HTOTAL(pipe
), I915_READ(HTOTAL(pipe
)));
2992 I915_WRITE(TRANS_HBLANK(pipe
), I915_READ(HBLANK(pipe
)));
2993 I915_WRITE(TRANS_HSYNC(pipe
), I915_READ(HSYNC(pipe
)));
2995 I915_WRITE(TRANS_VTOTAL(pipe
), I915_READ(VTOTAL(pipe
)));
2996 I915_WRITE(TRANS_VBLANK(pipe
), I915_READ(VBLANK(pipe
)));
2997 I915_WRITE(TRANS_VSYNC(pipe
), I915_READ(VSYNC(pipe
)));
2998 I915_WRITE(TRANS_VSYNCSHIFT(pipe
), I915_READ(VSYNCSHIFT(pipe
)));
3000 if (!IS_HASWELL(dev
))
3001 intel_fdi_normal_train(crtc
);
3003 /* For PCH DP, enable TRANS_DP_CTL */
3004 if (HAS_PCH_CPT(dev
) &&
3005 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
) ||
3006 intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
))) {
3007 u32 bpc
= (I915_READ(PIPECONF(pipe
)) & PIPE_BPC_MASK
) >> 5;
3008 reg
= TRANS_DP_CTL(pipe
);
3009 temp
= I915_READ(reg
);
3010 temp
&= ~(TRANS_DP_PORT_SEL_MASK
|
3011 TRANS_DP_SYNC_MASK
|
3013 temp
|= (TRANS_DP_OUTPUT_ENABLE
|
3014 TRANS_DP_ENH_FRAMING
);
3015 temp
|= bpc
<< 9; /* same format but at 11:9 */
3017 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PHSYNC
)
3018 temp
|= TRANS_DP_HSYNC_ACTIVE_HIGH
;
3019 if (crtc
->mode
.flags
& DRM_MODE_FLAG_PVSYNC
)
3020 temp
|= TRANS_DP_VSYNC_ACTIVE_HIGH
;
3022 switch (intel_trans_dp_port_sel(crtc
)) {
3024 temp
|= TRANS_DP_PORT_SEL_B
;
3027 temp
|= TRANS_DP_PORT_SEL_C
;
3030 temp
|= TRANS_DP_PORT_SEL_D
;
3033 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
3034 temp
|= TRANS_DP_PORT_SEL_B
;
3038 I915_WRITE(reg
, temp
);
3041 intel_enable_transcoder(dev_priv
, pipe
);
3044 static void intel_put_pch_pll(struct intel_crtc
*intel_crtc
)
3046 struct intel_pch_pll
*pll
= intel_crtc
->pch_pll
;
3051 if (pll
->refcount
== 0) {
3052 WARN(1, "bad PCH PLL refcount\n");
3057 intel_crtc
->pch_pll
= NULL
;
3060 static struct intel_pch_pll
*intel_get_pch_pll(struct intel_crtc
*intel_crtc
, u32 dpll
, u32 fp
)
3062 struct drm_i915_private
*dev_priv
= intel_crtc
->base
.dev
->dev_private
;
3063 struct intel_pch_pll
*pll
;
3066 pll
= intel_crtc
->pch_pll
;
3068 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3069 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3073 if (HAS_PCH_IBX(dev_priv
->dev
)) {
3074 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3075 i
= intel_crtc
->pipe
;
3076 pll
= &dev_priv
->pch_plls
[i
];
3078 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3079 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3084 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3085 pll
= &dev_priv
->pch_plls
[i
];
3087 /* Only want to check enabled timings first */
3088 if (pll
->refcount
== 0)
3091 if (dpll
== (I915_READ(pll
->pll_reg
) & 0x7fffffff) &&
3092 fp
== I915_READ(pll
->fp0_reg
)) {
3093 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3094 intel_crtc
->base
.base
.id
,
3095 pll
->pll_reg
, pll
->refcount
, pll
->active
);
3101 /* Ok no matching timings, maybe there's a free one? */
3102 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
3103 pll
= &dev_priv
->pch_plls
[i
];
3104 if (pll
->refcount
== 0) {
3105 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3106 intel_crtc
->base
.base
.id
, pll
->pll_reg
);
3114 intel_crtc
->pch_pll
= pll
;
3116 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i
, intel_crtc
->pipe
);
3117 prepare
: /* separate function? */
3118 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll
->pll_reg
);
3120 /* Wait for the clocks to stabilize before rewriting the regs */
3121 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3122 POSTING_READ(pll
->pll_reg
);
3125 I915_WRITE(pll
->fp0_reg
, fp
);
3126 I915_WRITE(pll
->pll_reg
, dpll
& ~DPLL_VCO_ENABLE
);
3131 void intel_cpt_verify_modeset(struct drm_device
*dev
, int pipe
)
3133 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3134 int dslreg
= PIPEDSL(pipe
), tc2reg
= TRANS_CHICKEN2(pipe
);
3137 temp
= I915_READ(dslreg
);
3139 if (wait_for(I915_READ(dslreg
) != temp
, 5)) {
3140 /* Without this, mode sets may fail silently on FDI */
3141 I915_WRITE(tc2reg
, TRANS_AUTOTRAIN_GEN_STALL_DIS
);
3143 I915_WRITE(tc2reg
, 0);
3144 if (wait_for(I915_READ(dslreg
) != temp
, 5))
3145 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe
);
3149 static void ironlake_crtc_enable(struct drm_crtc
*crtc
)
3151 struct drm_device
*dev
= crtc
->dev
;
3152 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3153 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3154 int pipe
= intel_crtc
->pipe
;
3155 int plane
= intel_crtc
->plane
;
3159 if (intel_crtc
->active
)
3162 intel_crtc
->active
= true;
3163 intel_update_watermarks(dev
);
3165 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3166 temp
= I915_READ(PCH_LVDS
);
3167 if ((temp
& LVDS_PORT_EN
) == 0)
3168 I915_WRITE(PCH_LVDS
, temp
| LVDS_PORT_EN
);
3171 is_pch_port
= intel_crtc_driving_pch(crtc
);
3174 ironlake_fdi_pll_enable(crtc
);
3176 ironlake_fdi_disable(crtc
);
3178 /* Enable panel fitting for LVDS */
3179 if (dev_priv
->pch_pf_size
&&
3180 (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) || HAS_eDP
)) {
3181 /* Force use of hard-coded filter coefficients
3182 * as some pre-programmed values are broken,
3185 I915_WRITE(PF_CTL(pipe
), PF_ENABLE
| PF_FILTER_MED_3x3
);
3186 I915_WRITE(PF_WIN_POS(pipe
), dev_priv
->pch_pf_pos
);
3187 I915_WRITE(PF_WIN_SZ(pipe
), dev_priv
->pch_pf_size
);
3191 * On ILK+ LUT must be loaded before the pipe is running but with
3194 intel_crtc_load_lut(crtc
);
3196 intel_enable_pipe(dev_priv
, pipe
, is_pch_port
);
3197 intel_enable_plane(dev_priv
, plane
, pipe
);
3200 ironlake_pch_enable(crtc
);
3202 mutex_lock(&dev
->struct_mutex
);
3203 intel_update_fbc(dev
);
3204 mutex_unlock(&dev
->struct_mutex
);
3206 intel_crtc_update_cursor(crtc
, true);
3209 static void ironlake_crtc_disable(struct drm_crtc
*crtc
)
3211 struct drm_device
*dev
= crtc
->dev
;
3212 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3213 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3214 int pipe
= intel_crtc
->pipe
;
3215 int plane
= intel_crtc
->plane
;
3218 if (!intel_crtc
->active
)
3221 intel_crtc_wait_for_pending_flips(crtc
);
3222 drm_vblank_off(dev
, pipe
);
3223 intel_crtc_update_cursor(crtc
, false);
3225 intel_disable_plane(dev_priv
, plane
, pipe
);
3227 if (dev_priv
->cfb_plane
== plane
)
3228 intel_disable_fbc(dev
);
3230 intel_disable_pipe(dev_priv
, pipe
);
3233 I915_WRITE(PF_CTL(pipe
), 0);
3234 I915_WRITE(PF_WIN_SZ(pipe
), 0);
3236 ironlake_fdi_disable(crtc
);
3238 /* This is a horrible layering violation; we should be doing this in
3239 * the connector/encoder ->prepare instead, but we don't always have
3240 * enough information there about the config to know whether it will
3241 * actually be necessary or just cause undesired flicker.
3243 intel_disable_pch_ports(dev_priv
, pipe
);
3245 intel_disable_transcoder(dev_priv
, pipe
);
3247 if (HAS_PCH_CPT(dev
)) {
3248 /* disable TRANS_DP_CTL */
3249 reg
= TRANS_DP_CTL(pipe
);
3250 temp
= I915_READ(reg
);
3251 temp
&= ~(TRANS_DP_OUTPUT_ENABLE
| TRANS_DP_PORT_SEL_MASK
);
3252 temp
|= TRANS_DP_PORT_SEL_NONE
;
3253 I915_WRITE(reg
, temp
);
3255 /* disable DPLL_SEL */
3256 temp
= I915_READ(PCH_DPLL_SEL
);
3259 temp
&= ~(TRANSA_DPLL_ENABLE
| TRANSA_DPLLB_SEL
);
3262 temp
&= ~(TRANSB_DPLL_ENABLE
| TRANSB_DPLLB_SEL
);
3265 /* C shares PLL A or B */
3266 temp
&= ~(TRANSC_DPLL_ENABLE
| TRANSC_DPLLB_SEL
);
3271 I915_WRITE(PCH_DPLL_SEL
, temp
);
3274 /* disable PCH DPLL */
3275 intel_disable_pch_pll(intel_crtc
);
3277 /* Switch from PCDclk to Rawclk */
3278 reg
= FDI_RX_CTL(pipe
);
3279 temp
= I915_READ(reg
);
3280 I915_WRITE(reg
, temp
& ~FDI_PCDCLK
);
3282 /* Disable CPU FDI TX PLL */
3283 reg
= FDI_TX_CTL(pipe
);
3284 temp
= I915_READ(reg
);
3285 I915_WRITE(reg
, temp
& ~FDI_TX_PLL_ENABLE
);
3290 reg
= FDI_RX_CTL(pipe
);
3291 temp
= I915_READ(reg
);
3292 I915_WRITE(reg
, temp
& ~FDI_RX_PLL_ENABLE
);
3294 /* Wait for the clocks to turn off. */
3298 intel_crtc
->active
= false;
3299 intel_update_watermarks(dev
);
3301 mutex_lock(&dev
->struct_mutex
);
3302 intel_update_fbc(dev
);
3303 mutex_unlock(&dev
->struct_mutex
);
3306 static void ironlake_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3308 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3309 int pipe
= intel_crtc
->pipe
;
3310 int plane
= intel_crtc
->plane
;
3312 /* XXX: When our outputs are all unaware of DPMS modes other than off
3313 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3316 case DRM_MODE_DPMS_ON
:
3317 case DRM_MODE_DPMS_STANDBY
:
3318 case DRM_MODE_DPMS_SUSPEND
:
3319 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe
, plane
);
3320 ironlake_crtc_enable(crtc
);
3323 case DRM_MODE_DPMS_OFF
:
3324 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe
, plane
);
3325 ironlake_crtc_disable(crtc
);
3330 static void ironlake_crtc_off(struct drm_crtc
*crtc
)
3332 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3333 intel_put_pch_pll(intel_crtc
);
3336 static void intel_crtc_dpms_overlay(struct intel_crtc
*intel_crtc
, bool enable
)
3338 if (!enable
&& intel_crtc
->overlay
) {
3339 struct drm_device
*dev
= intel_crtc
->base
.dev
;
3340 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3342 mutex_lock(&dev
->struct_mutex
);
3343 dev_priv
->mm
.interruptible
= false;
3344 (void) intel_overlay_switch_off(intel_crtc
->overlay
);
3345 dev_priv
->mm
.interruptible
= true;
3346 mutex_unlock(&dev
->struct_mutex
);
3349 /* Let userspace switch the overlay on again. In most cases userspace
3350 * has to recompute where to put it anyway.
3354 static void i9xx_crtc_enable(struct drm_crtc
*crtc
)
3356 struct drm_device
*dev
= crtc
->dev
;
3357 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3358 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3359 int pipe
= intel_crtc
->pipe
;
3360 int plane
= intel_crtc
->plane
;
3362 if (intel_crtc
->active
)
3365 intel_crtc
->active
= true;
3366 intel_update_watermarks(dev
);
3368 intel_enable_pll(dev_priv
, pipe
);
3369 intel_enable_pipe(dev_priv
, pipe
, false);
3370 intel_enable_plane(dev_priv
, plane
, pipe
);
3372 intel_crtc_load_lut(crtc
);
3373 intel_update_fbc(dev
);
3375 /* Give the overlay scaler a chance to enable if it's on this pipe */
3376 intel_crtc_dpms_overlay(intel_crtc
, true);
3377 intel_crtc_update_cursor(crtc
, true);
3380 static void i9xx_crtc_disable(struct drm_crtc
*crtc
)
3382 struct drm_device
*dev
= crtc
->dev
;
3383 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3384 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3385 int pipe
= intel_crtc
->pipe
;
3386 int plane
= intel_crtc
->plane
;
3388 if (!intel_crtc
->active
)
3391 /* Give the overlay scaler a chance to disable if it's on this pipe */
3392 intel_crtc_wait_for_pending_flips(crtc
);
3393 drm_vblank_off(dev
, pipe
);
3394 intel_crtc_dpms_overlay(intel_crtc
, false);
3395 intel_crtc_update_cursor(crtc
, false);
3397 if (dev_priv
->cfb_plane
== plane
)
3398 intel_disable_fbc(dev
);
3400 intel_disable_plane(dev_priv
, plane
, pipe
);
3401 intel_disable_pipe(dev_priv
, pipe
);
3402 intel_disable_pll(dev_priv
, pipe
);
3404 intel_crtc
->active
= false;
3405 intel_update_fbc(dev
);
3406 intel_update_watermarks(dev
);
3409 static void i9xx_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3411 /* XXX: When our outputs are all unaware of DPMS modes other than off
3412 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3415 case DRM_MODE_DPMS_ON
:
3416 case DRM_MODE_DPMS_STANDBY
:
3417 case DRM_MODE_DPMS_SUSPEND
:
3418 i9xx_crtc_enable(crtc
);
3420 case DRM_MODE_DPMS_OFF
:
3421 i9xx_crtc_disable(crtc
);
3426 static void i9xx_crtc_off(struct drm_crtc
*crtc
)
3431 * Sets the power management mode of the pipe and plane.
3433 static void intel_crtc_dpms(struct drm_crtc
*crtc
, int mode
)
3435 struct drm_device
*dev
= crtc
->dev
;
3436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3437 struct drm_i915_master_private
*master_priv
;
3438 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3439 int pipe
= intel_crtc
->pipe
;
3442 if (intel_crtc
->dpms_mode
== mode
)
3445 intel_crtc
->dpms_mode
= mode
;
3447 dev_priv
->display
.dpms(crtc
, mode
);
3449 if (!dev
->primary
->master
)
3452 master_priv
= dev
->primary
->master
->driver_priv
;
3453 if (!master_priv
->sarea_priv
)
3456 enabled
= crtc
->enabled
&& mode
!= DRM_MODE_DPMS_OFF
;
3460 master_priv
->sarea_priv
->pipeA_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3461 master_priv
->sarea_priv
->pipeA_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3464 master_priv
->sarea_priv
->pipeB_w
= enabled
? crtc
->mode
.hdisplay
: 0;
3465 master_priv
->sarea_priv
->pipeB_h
= enabled
? crtc
->mode
.vdisplay
: 0;
3468 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe
));
3473 static void intel_crtc_disable(struct drm_crtc
*crtc
)
3475 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
3476 struct drm_device
*dev
= crtc
->dev
;
3477 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3479 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_OFF
);
3480 dev_priv
->display
.off(crtc
);
3482 assert_plane_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->plane
);
3483 assert_pipe_disabled(dev
->dev_private
, to_intel_crtc(crtc
)->pipe
);
3486 mutex_lock(&dev
->struct_mutex
);
3487 intel_unpin_fb_obj(to_intel_framebuffer(crtc
->fb
)->obj
);
3488 mutex_unlock(&dev
->struct_mutex
);
3492 /* Prepare for a mode set.
3494 * Note we could be a lot smarter here. We need to figure out which outputs
3495 * will be enabled, which disabled (in short, how the config will changes)
3496 * and perform the minimum necessary steps to accomplish that, e.g. updating
3497 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3498 * panel fitting is in the proper state, etc.
3500 static void i9xx_crtc_prepare(struct drm_crtc
*crtc
)
3502 i9xx_crtc_disable(crtc
);
3505 static void i9xx_crtc_commit(struct drm_crtc
*crtc
)
3507 i9xx_crtc_enable(crtc
);
3510 static void ironlake_crtc_prepare(struct drm_crtc
*crtc
)
3512 ironlake_crtc_disable(crtc
);
3515 static void ironlake_crtc_commit(struct drm_crtc
*crtc
)
3517 ironlake_crtc_enable(crtc
);
3520 void intel_encoder_prepare(struct drm_encoder
*encoder
)
3522 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3523 /* lvds has its own version of prepare see intel_lvds_prepare */
3524 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_OFF
);
3527 void intel_encoder_commit(struct drm_encoder
*encoder
)
3529 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
3530 struct drm_device
*dev
= encoder
->dev
;
3531 struct intel_crtc
*intel_crtc
= to_intel_crtc(encoder
->crtc
);
3533 /* lvds has its own version of commit see intel_lvds_commit */
3534 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
3536 if (HAS_PCH_CPT(dev
))
3537 intel_cpt_verify_modeset(dev
, intel_crtc
->pipe
);
3540 void intel_encoder_destroy(struct drm_encoder
*encoder
)
3542 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3544 drm_encoder_cleanup(encoder
);
3545 kfree(intel_encoder
);
3548 static bool intel_crtc_mode_fixup(struct drm_crtc
*crtc
,
3549 struct drm_display_mode
*mode
,
3550 struct drm_display_mode
*adjusted_mode
)
3552 struct drm_device
*dev
= crtc
->dev
;
3554 if (HAS_PCH_SPLIT(dev
)) {
3555 /* FDI link clock is fixed at 2.7G */
3556 if (mode
->clock
* 3 > IRONLAKE_FDI_FREQ
* 4)
3560 /* All interlaced capable intel hw wants timings in frames. Note though
3561 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3562 * timings, so we need to be careful not to clobber these.*/
3563 if (!(adjusted_mode
->private_flags
& INTEL_MODE_CRTC_TIMINGS_SET
))
3564 drm_mode_set_crtcinfo(adjusted_mode
, 0);
3569 static int valleyview_get_display_clock_speed(struct drm_device
*dev
)
3571 return 400000; /* FIXME */
3574 static int i945_get_display_clock_speed(struct drm_device
*dev
)
3579 static int i915_get_display_clock_speed(struct drm_device
*dev
)
3584 static int i9xx_misc_get_display_clock_speed(struct drm_device
*dev
)
3589 static int i915gm_get_display_clock_speed(struct drm_device
*dev
)
3593 pci_read_config_word(dev
->pdev
, GCFGC
, &gcfgc
);
3595 if (gcfgc
& GC_LOW_FREQUENCY_ENABLE
)
3598 switch (gcfgc
& GC_DISPLAY_CLOCK_MASK
) {
3599 case GC_DISPLAY_CLOCK_333_MHZ
:
3602 case GC_DISPLAY_CLOCK_190_200_MHZ
:
3608 static int i865_get_display_clock_speed(struct drm_device
*dev
)
3613 static int i855_get_display_clock_speed(struct drm_device
*dev
)
3616 /* Assume that the hardware is in the high speed state. This
3617 * should be the default.
3619 switch (hpllcc
& GC_CLOCK_CONTROL_MASK
) {
3620 case GC_CLOCK_133_200
:
3621 case GC_CLOCK_100_200
:
3623 case GC_CLOCK_166_250
:
3625 case GC_CLOCK_100_133
:
3629 /* Shouldn't happen */
3633 static int i830_get_display_clock_speed(struct drm_device
*dev
)
3647 fdi_reduce_ratio(u32
*num
, u32
*den
)
3649 while (*num
> 0xffffff || *den
> 0xffffff) {
3656 ironlake_compute_m_n(int bits_per_pixel
, int nlanes
, int pixel_clock
,
3657 int link_clock
, struct fdi_m_n
*m_n
)
3659 m_n
->tu
= 64; /* default size */
3661 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3662 m_n
->gmch_m
= bits_per_pixel
* pixel_clock
;
3663 m_n
->gmch_n
= link_clock
* nlanes
* 8;
3664 fdi_reduce_ratio(&m_n
->gmch_m
, &m_n
->gmch_n
);
3666 m_n
->link_m
= pixel_clock
;
3667 m_n
->link_n
= link_clock
;
3668 fdi_reduce_ratio(&m_n
->link_m
, &m_n
->link_n
);
3671 static inline bool intel_panel_use_ssc(struct drm_i915_private
*dev_priv
)
3673 if (i915_panel_use_ssc
>= 0)
3674 return i915_panel_use_ssc
!= 0;
3675 return dev_priv
->lvds_use_ssc
3676 && !(dev_priv
->quirks
& QUIRK_LVDS_SSC_DISABLE
);
3680 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3681 * @crtc: CRTC structure
3682 * @mode: requested mode
3684 * A pipe may be connected to one or more outputs. Based on the depth of the
3685 * attached framebuffer, choose a good color depth to use on the pipe.
3687 * If possible, match the pipe depth to the fb depth. In some cases, this
3688 * isn't ideal, because the connected output supports a lesser or restricted
3689 * set of depths. Resolve that here:
3690 * LVDS typically supports only 6bpc, so clamp down in that case
3691 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3692 * Displays may support a restricted set as well, check EDID and clamp as
3694 * DP may want to dither down to 6bpc to fit larger modes
3697 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3698 * true if they don't match).
3700 static bool intel_choose_pipe_bpp_dither(struct drm_crtc
*crtc
,
3701 unsigned int *pipe_bpp
,
3702 struct drm_display_mode
*mode
)
3704 struct drm_device
*dev
= crtc
->dev
;
3705 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3706 struct drm_encoder
*encoder
;
3707 struct drm_connector
*connector
;
3708 unsigned int display_bpc
= UINT_MAX
, bpc
;
3710 /* Walk the encoders & connectors on this crtc, get min bpc */
3711 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
3712 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
3714 if (encoder
->crtc
!= crtc
)
3717 if (intel_encoder
->type
== INTEL_OUTPUT_LVDS
) {
3718 unsigned int lvds_bpc
;
3720 if ((I915_READ(PCH_LVDS
) & LVDS_A3_POWER_MASK
) ==
3726 if (lvds_bpc
< display_bpc
) {
3727 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc
, lvds_bpc
);
3728 display_bpc
= lvds_bpc
;
3733 if (intel_encoder
->type
== INTEL_OUTPUT_EDP
) {
3734 /* Use VBT settings if we have an eDP panel */
3735 unsigned int edp_bpc
= dev_priv
->edp
.bpp
/ 3;
3737 if (edp_bpc
< display_bpc
) {
3738 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc
, edp_bpc
);
3739 display_bpc
= edp_bpc
;
3744 /* Not one of the known troublemakers, check the EDID */
3745 list_for_each_entry(connector
, &dev
->mode_config
.connector_list
,
3747 if (connector
->encoder
!= encoder
)
3750 /* Don't use an invalid EDID bpc value */
3751 if (connector
->display_info
.bpc
&&
3752 connector
->display_info
.bpc
< display_bpc
) {
3753 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc
, connector
->display_info
.bpc
);
3754 display_bpc
= connector
->display_info
.bpc
;
3759 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3760 * through, clamp it down. (Note: >12bpc will be caught below.)
3762 if (intel_encoder
->type
== INTEL_OUTPUT_HDMI
) {
3763 if (display_bpc
> 8 && display_bpc
< 12) {
3764 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
3767 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
3773 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
3774 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3779 * We could just drive the pipe at the highest bpc all the time and
3780 * enable dithering as needed, but that costs bandwidth. So choose
3781 * the minimum value that expresses the full color range of the fb but
3782 * also stays within the max display bpc discovered above.
3785 switch (crtc
->fb
->depth
) {
3787 bpc
= 8; /* since we go through a colormap */
3791 bpc
= 6; /* min is 18bpp */
3803 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3804 bpc
= min((unsigned int)8, display_bpc
);
3808 display_bpc
= min(display_bpc
, bpc
);
3810 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3813 *pipe_bpp
= display_bpc
* 3;
3815 return display_bpc
!= bpc
;
3818 static int vlv_get_refclk(struct drm_crtc
*crtc
)
3820 struct drm_device
*dev
= crtc
->dev
;
3821 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3822 int refclk
= 27000; /* for DP & HDMI */
3824 return 100000; /* only one validated so far */
3826 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_ANALOG
)) {
3828 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
3829 if (intel_panel_use_ssc(dev_priv
))
3833 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_EDP
)) {
3840 static int i9xx_get_refclk(struct drm_crtc
*crtc
, int num_connectors
)
3842 struct drm_device
*dev
= crtc
->dev
;
3843 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3846 if (IS_VALLEYVIEW(dev
)) {
3847 refclk
= vlv_get_refclk(crtc
);
3848 } else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3849 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
3850 refclk
= dev_priv
->lvds_ssc_freq
* 1000;
3851 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3853 } else if (!IS_GEN2(dev
)) {
3862 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode
*adjusted_mode
,
3863 intel_clock_t
*clock
)
3865 /* SDVO TV has fixed PLL values depend on its clock range,
3866 this mirrors vbios setting. */
3867 if (adjusted_mode
->clock
>= 100000
3868 && adjusted_mode
->clock
< 140500) {
3874 } else if (adjusted_mode
->clock
>= 140500
3875 && adjusted_mode
->clock
<= 200000) {
3884 static void i9xx_update_pll_dividers(struct drm_crtc
*crtc
,
3885 intel_clock_t
*clock
,
3886 intel_clock_t
*reduced_clock
)
3888 struct drm_device
*dev
= crtc
->dev
;
3889 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3890 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3891 int pipe
= intel_crtc
->pipe
;
3894 if (IS_PINEVIEW(dev
)) {
3895 fp
= (1 << clock
->n
) << 16 | clock
->m1
<< 8 | clock
->m2
;
3897 fp2
= (1 << reduced_clock
->n
) << 16 |
3898 reduced_clock
->m1
<< 8 | reduced_clock
->m2
;
3900 fp
= clock
->n
<< 16 | clock
->m1
<< 8 | clock
->m2
;
3902 fp2
= reduced_clock
->n
<< 16 | reduced_clock
->m1
<< 8 |
3906 I915_WRITE(FP0(pipe
), fp
);
3908 intel_crtc
->lowfreq_avail
= false;
3909 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
3910 reduced_clock
&& i915_powersave
) {
3911 I915_WRITE(FP1(pipe
), fp2
);
3912 intel_crtc
->lowfreq_avail
= true;
3914 I915_WRITE(FP1(pipe
), fp
);
3918 static void intel_update_lvds(struct drm_crtc
*crtc
, intel_clock_t
*clock
,
3919 struct drm_display_mode
*adjusted_mode
)
3921 struct drm_device
*dev
= crtc
->dev
;
3922 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3923 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3924 int pipe
= intel_crtc
->pipe
;
3927 temp
= I915_READ(LVDS
);
3928 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
3930 temp
|= LVDS_PIPEB_SELECT
;
3932 temp
&= ~LVDS_PIPEB_SELECT
;
3934 /* set the corresponsding LVDS_BORDER bit */
3935 temp
|= dev_priv
->lvds_border_bits
;
3936 /* Set the B0-B3 data pairs corresponding to whether we're going to
3937 * set the DPLLs for dual-channel mode or not.
3940 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
3942 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
3944 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3945 * appropriately here, but we need to look more thoroughly into how
3946 * panels behave in the two modes.
3948 /* set the dithering flag on LVDS as needed */
3949 if (INTEL_INFO(dev
)->gen
>= 4) {
3950 if (dev_priv
->lvds_dither
)
3951 temp
|= LVDS_ENABLE_DITHER
;
3953 temp
&= ~LVDS_ENABLE_DITHER
;
3955 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
3956 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
3957 temp
|= LVDS_HSYNC_POLARITY
;
3958 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
3959 temp
|= LVDS_VSYNC_POLARITY
;
3960 I915_WRITE(LVDS
, temp
);
3963 static void vlv_update_pll(struct drm_crtc
*crtc
,
3964 struct drm_display_mode
*mode
,
3965 struct drm_display_mode
*adjusted_mode
,
3966 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
3967 int refclk
, int num_connectors
)
3969 struct drm_device
*dev
= crtc
->dev
;
3970 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
3971 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
3972 int pipe
= intel_crtc
->pipe
;
3973 u32 dpll
, mdiv
, pdiv
;
3974 u32 bestn
, bestm1
, bestm2
, bestp1
, bestp2
;
3977 is_hdmi
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
3985 /* Enable DPIO clock input */
3986 dpll
= DPLL_EXT_BUFFER_ENABLE_VLV
| DPLL_REFA_CLK_ENABLE_VLV
|
3987 DPLL_VGA_MODE_DIS
| DPLL_INTEGRATED_CLOCK_VLV
;
3988 I915_WRITE(DPLL(pipe
), dpll
);
3989 POSTING_READ(DPLL(pipe
));
3991 mdiv
= ((bestm1
<< DPIO_M1DIV_SHIFT
) | (bestm2
& DPIO_M2DIV_MASK
));
3992 mdiv
|= ((bestp1
<< DPIO_P1_SHIFT
) | (bestp2
<< DPIO_P2_SHIFT
));
3993 mdiv
|= ((bestn
<< DPIO_N_SHIFT
));
3994 mdiv
|= (1 << DPIO_POST_DIV_SHIFT
);
3995 mdiv
|= (1 << DPIO_K_SHIFT
);
3996 mdiv
|= DPIO_ENABLE_CALIBRATION
;
3997 intel_dpio_write(dev_priv
, DPIO_DIV(pipe
), mdiv
);
3999 intel_dpio_write(dev_priv
, DPIO_CORE_CLK(pipe
), 0x01000000);
4001 pdiv
= DPIO_REFSEL_OVERRIDE
| (5 << DPIO_PLL_MODESEL_SHIFT
) |
4002 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT
) | (1<<20) |
4003 (8 << DPIO_DRIVER_CTL_SHIFT
) | (5 << DPIO_CLK_BIAS_CTL_SHIFT
);
4004 intel_dpio_write(dev_priv
, DPIO_REFSFR(pipe
), pdiv
);
4006 intel_dpio_write(dev_priv
, DPIO_LFP_COEFF(pipe
), 0x009f0051);
4008 dpll
|= DPLL_VCO_ENABLE
;
4009 I915_WRITE(DPLL(pipe
), dpll
);
4010 POSTING_READ(DPLL(pipe
));
4011 if (wait_for(((I915_READ(DPLL(pipe
)) & DPLL_LOCK_VLV
) == DPLL_LOCK_VLV
), 1))
4012 DRM_ERROR("DPLL %d failed to lock\n", pipe
);
4015 u32 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4018 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4022 I915_WRITE(DPLL_MD(pipe
), temp
);
4023 POSTING_READ(DPLL_MD(pipe
));
4026 intel_dpio_write(dev_priv
, DPIO_FASTCLK_DISABLE
, 0x641); /* ??? */
4029 static void i9xx_update_pll(struct drm_crtc
*crtc
,
4030 struct drm_display_mode
*mode
,
4031 struct drm_display_mode
*adjusted_mode
,
4032 intel_clock_t
*clock
, intel_clock_t
*reduced_clock
,
4035 struct drm_device
*dev
= crtc
->dev
;
4036 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4037 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4038 int pipe
= intel_crtc
->pipe
;
4042 is_sdvo
= intel_pipe_has_type(crtc
, INTEL_OUTPUT_SDVO
) ||
4043 intel_pipe_has_type(crtc
, INTEL_OUTPUT_HDMI
);
4045 dpll
= DPLL_VGA_MODE_DIS
;
4047 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4048 dpll
|= DPLLB_MODE_LVDS
;
4050 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4052 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4053 if (pixel_multiplier
> 1) {
4054 if (IS_I945G(dev
) || IS_I945GM(dev
) || IS_G33(dev
))
4055 dpll
|= (pixel_multiplier
- 1) << SDVO_MULTIPLIER_SHIFT_HIRES
;
4057 dpll
|= DPLL_DVO_HIGH_SPEED
;
4059 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4060 dpll
|= DPLL_DVO_HIGH_SPEED
;
4062 /* compute bitmask from p1 value */
4063 if (IS_PINEVIEW(dev
))
4064 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
;
4066 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4067 if (IS_G4X(dev
) && reduced_clock
)
4068 dpll
|= (1 << (reduced_clock
->p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4070 switch (clock
->p2
) {
4072 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4075 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4078 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4081 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4084 if (INTEL_INFO(dev
)->gen
>= 4)
4085 dpll
|= (6 << PLL_LOAD_PULSE_PHASE_SHIFT
);
4087 if (is_sdvo
&& intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4088 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4089 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4090 /* XXX: just matching BIOS for now */
4091 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4093 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4094 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4095 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4097 dpll
|= PLL_REF_INPUT_DREFCLK
;
4099 dpll
|= DPLL_VCO_ENABLE
;
4100 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4101 POSTING_READ(DPLL(pipe
));
4104 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4105 * This is an exception to the general rule that mode_set doesn't turn
4108 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4109 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4111 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
))
4112 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4114 I915_WRITE(DPLL(pipe
), dpll
);
4116 /* Wait for the clocks to stabilize. */
4117 POSTING_READ(DPLL(pipe
));
4120 if (INTEL_INFO(dev
)->gen
>= 4) {
4123 temp
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4125 temp
= (temp
- 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT
;
4129 I915_WRITE(DPLL_MD(pipe
), temp
);
4131 /* The pixel multiplier can only be updated once the
4132 * DPLL is enabled and the clocks are stable.
4134 * So write it again.
4136 I915_WRITE(DPLL(pipe
), dpll
);
4140 static void i8xx_update_pll(struct drm_crtc
*crtc
,
4141 struct drm_display_mode
*adjusted_mode
,
4142 intel_clock_t
*clock
,
4145 struct drm_device
*dev
= crtc
->dev
;
4146 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4147 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4148 int pipe
= intel_crtc
->pipe
;
4151 dpll
= DPLL_VGA_MODE_DIS
;
4153 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
)) {
4154 dpll
|= (1 << (clock
->p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4157 dpll
|= PLL_P1_DIVIDE_BY_TWO
;
4159 dpll
|= (clock
->p1
- 2) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4161 dpll
|= PLL_P2_DIVIDE_BY_4
;
4164 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_TVOUT
))
4165 /* XXX: just matching BIOS for now */
4166 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4168 else if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
) &&
4169 intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4170 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4172 dpll
|= PLL_REF_INPUT_DREFCLK
;
4174 dpll
|= DPLL_VCO_ENABLE
;
4175 I915_WRITE(DPLL(pipe
), dpll
& ~DPLL_VCO_ENABLE
);
4176 POSTING_READ(DPLL(pipe
));
4179 I915_WRITE(DPLL(pipe
), dpll
);
4181 /* Wait for the clocks to stabilize. */
4182 POSTING_READ(DPLL(pipe
));
4185 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4186 * This is an exception to the general rule that mode_set doesn't turn
4189 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_LVDS
))
4190 intel_update_lvds(crtc
, clock
, adjusted_mode
);
4192 /* The pixel multiplier can only be updated once the
4193 * DPLL is enabled and the clocks are stable.
4195 * So write it again.
4197 I915_WRITE(DPLL(pipe
), dpll
);
4200 static int i9xx_crtc_mode_set(struct drm_crtc
*crtc
,
4201 struct drm_display_mode
*mode
,
4202 struct drm_display_mode
*adjusted_mode
,
4204 struct drm_framebuffer
*old_fb
)
4206 struct drm_device
*dev
= crtc
->dev
;
4207 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4208 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4209 int pipe
= intel_crtc
->pipe
;
4210 int plane
= intel_crtc
->plane
;
4211 int refclk
, num_connectors
= 0;
4212 intel_clock_t clock
, reduced_clock
;
4213 u32 dspcntr
, pipeconf
, vsyncshift
;
4214 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4215 bool is_lvds
= false, is_tv
= false, is_dp
= false;
4216 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4217 struct intel_encoder
*encoder
;
4218 const intel_limit_t
*limit
;
4221 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4222 if (encoder
->base
.crtc
!= crtc
)
4225 switch (encoder
->type
) {
4226 case INTEL_OUTPUT_LVDS
:
4229 case INTEL_OUTPUT_SDVO
:
4230 case INTEL_OUTPUT_HDMI
:
4232 if (encoder
->needs_tv_clock
)
4235 case INTEL_OUTPUT_TVOUT
:
4238 case INTEL_OUTPUT_DISPLAYPORT
:
4246 refclk
= i9xx_get_refclk(crtc
, num_connectors
);
4249 * Returns a set of divisors for the desired target clock with the given
4250 * refclk, or FALSE. The returned values represent the clock equation:
4251 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4253 limit
= intel_limit(crtc
, refclk
);
4254 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4257 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4261 /* Ensure that the cursor is valid for the new mode before changing... */
4262 intel_crtc_update_cursor(crtc
, true);
4264 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4266 * Ensure we match the reduced clock's P to the target clock.
4267 * If the clocks don't match, we can't switch the display clock
4268 * by using the FP0/FP1. In such case we will disable the LVDS
4269 * downclock feature.
4271 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4272 dev_priv
->lvds_downclock
,
4278 if (is_sdvo
&& is_tv
)
4279 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4281 i9xx_update_pll_dividers(crtc
, &clock
, has_reduced_clock
?
4282 &reduced_clock
: NULL
);
4285 i8xx_update_pll(crtc
, adjusted_mode
, &clock
, num_connectors
);
4286 else if (IS_VALLEYVIEW(dev
))
4287 vlv_update_pll(crtc
, mode
,adjusted_mode
, &clock
, NULL
,
4288 refclk
, num_connectors
);
4290 i9xx_update_pll(crtc
, mode
, adjusted_mode
, &clock
,
4291 has_reduced_clock
? &reduced_clock
: NULL
,
4294 /* setup pipeconf */
4295 pipeconf
= I915_READ(PIPECONF(pipe
));
4297 /* Set up the display plane register */
4298 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4301 dspcntr
&= ~DISPPLANE_SEL_PIPE_MASK
;
4303 dspcntr
|= DISPPLANE_SEL_PIPE_B
;
4305 if (pipe
== 0 && INTEL_INFO(dev
)->gen
< 4) {
4306 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4309 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4313 dev_priv
->display
.get_display_clock_speed(dev
) * 9 / 10)
4314 pipeconf
|= PIPECONF_DOUBLE_WIDE
;
4316 pipeconf
&= ~PIPECONF_DOUBLE_WIDE
;
4319 /* default to 8bpc */
4320 pipeconf
&= ~(PIPECONF_BPP_MASK
| PIPECONF_DITHER_EN
);
4322 if (mode
->private_flags
& INTEL_MODE_DP_FORCE_6BPC
) {
4323 pipeconf
|= PIPECONF_BPP_6
|
4324 PIPECONF_DITHER_EN
|
4325 PIPECONF_DITHER_TYPE_SP
;
4329 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe
== 0 ? 'A' : 'B');
4330 drm_mode_debug_printmodeline(mode
);
4332 if (HAS_PIPE_CXSR(dev
)) {
4333 if (intel_crtc
->lowfreq_avail
) {
4334 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4335 pipeconf
|= PIPECONF_CXSR_DOWNCLOCK
;
4337 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4338 pipeconf
&= ~PIPECONF_CXSR_DOWNCLOCK
;
4342 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4343 if (!IS_GEN2(dev
) &&
4344 adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4345 pipeconf
|= PIPECONF_INTERLACE_W_FIELD_INDICATION
;
4346 /* the chip adds 2 halflines automatically */
4347 adjusted_mode
->crtc_vtotal
-= 1;
4348 adjusted_mode
->crtc_vblank_end
-= 1;
4349 vsyncshift
= adjusted_mode
->crtc_hsync_start
4350 - adjusted_mode
->crtc_htotal
/2;
4352 pipeconf
|= PIPECONF_PROGRESSIVE
;
4357 I915_WRITE(VSYNCSHIFT(pipe
), vsyncshift
);
4359 I915_WRITE(HTOTAL(pipe
),
4360 (adjusted_mode
->crtc_hdisplay
- 1) |
4361 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4362 I915_WRITE(HBLANK(pipe
),
4363 (adjusted_mode
->crtc_hblank_start
- 1) |
4364 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4365 I915_WRITE(HSYNC(pipe
),
4366 (adjusted_mode
->crtc_hsync_start
- 1) |
4367 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4369 I915_WRITE(VTOTAL(pipe
),
4370 (adjusted_mode
->crtc_vdisplay
- 1) |
4371 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4372 I915_WRITE(VBLANK(pipe
),
4373 (adjusted_mode
->crtc_vblank_start
- 1) |
4374 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4375 I915_WRITE(VSYNC(pipe
),
4376 (adjusted_mode
->crtc_vsync_start
- 1) |
4377 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4379 /* pipesrc and dspsize control the size that is scaled from,
4380 * which should always be the user's requested size.
4382 I915_WRITE(DSPSIZE(plane
),
4383 ((mode
->vdisplay
- 1) << 16) |
4384 (mode
->hdisplay
- 1));
4385 I915_WRITE(DSPPOS(plane
), 0);
4386 I915_WRITE(PIPESRC(pipe
),
4387 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4389 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4390 POSTING_READ(PIPECONF(pipe
));
4391 intel_enable_pipe(dev_priv
, pipe
, false);
4393 intel_wait_for_vblank(dev
, pipe
);
4395 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4396 POSTING_READ(DSPCNTR(plane
));
4398 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4400 intel_update_watermarks(dev
);
4406 * Initialize reference clocks when the driver loads
4408 void ironlake_init_pch_refclk(struct drm_device
*dev
)
4410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4411 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4412 struct intel_encoder
*encoder
;
4414 bool has_lvds
= false;
4415 bool has_cpu_edp
= false;
4416 bool has_pch_edp
= false;
4417 bool has_panel
= false;
4418 bool has_ck505
= false;
4419 bool can_ssc
= false;
4421 /* We need to take the global config into account */
4422 list_for_each_entry(encoder
, &mode_config
->encoder_list
,
4424 switch (encoder
->type
) {
4425 case INTEL_OUTPUT_LVDS
:
4429 case INTEL_OUTPUT_EDP
:
4431 if (intel_encoder_is_pch_edp(&encoder
->base
))
4439 if (HAS_PCH_IBX(dev
)) {
4440 has_ck505
= dev_priv
->display_clock_mode
;
4441 can_ssc
= has_ck505
;
4447 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4448 has_panel
, has_lvds
, has_pch_edp
, has_cpu_edp
,
4451 /* Ironlake: try to setup display ref clock before DPLL
4452 * enabling. This is only under driver's control after
4453 * PCH B stepping, previous chipset stepping should be
4454 * ignoring this setting.
4456 temp
= I915_READ(PCH_DREF_CONTROL
);
4457 /* Always enable nonspread source */
4458 temp
&= ~DREF_NONSPREAD_SOURCE_MASK
;
4461 temp
|= DREF_NONSPREAD_CK505_ENABLE
;
4463 temp
|= DREF_NONSPREAD_SOURCE_ENABLE
;
4466 temp
&= ~DREF_SSC_SOURCE_MASK
;
4467 temp
|= DREF_SSC_SOURCE_ENABLE
;
4469 /* SSC must be turned on before enabling the CPU output */
4470 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4471 DRM_DEBUG_KMS("Using SSC on panel\n");
4472 temp
|= DREF_SSC1_ENABLE
;
4474 temp
&= ~DREF_SSC1_ENABLE
;
4476 /* Get SSC going before enabling the outputs */
4477 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4478 POSTING_READ(PCH_DREF_CONTROL
);
4481 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4483 /* Enable CPU source on CPU attached eDP */
4485 if (intel_panel_use_ssc(dev_priv
) && can_ssc
) {
4486 DRM_DEBUG_KMS("Using SSC on eDP\n");
4487 temp
|= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD
;
4490 temp
|= DREF_CPU_SOURCE_OUTPUT_NONSPREAD
;
4492 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4494 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4495 POSTING_READ(PCH_DREF_CONTROL
);
4498 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4500 temp
&= ~DREF_CPU_SOURCE_OUTPUT_MASK
;
4502 /* Turn off CPU output */
4503 temp
|= DREF_CPU_SOURCE_OUTPUT_DISABLE
;
4505 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4506 POSTING_READ(PCH_DREF_CONTROL
);
4509 /* Turn off the SSC source */
4510 temp
&= ~DREF_SSC_SOURCE_MASK
;
4511 temp
|= DREF_SSC_SOURCE_DISABLE
;
4514 temp
&= ~ DREF_SSC1_ENABLE
;
4516 I915_WRITE(PCH_DREF_CONTROL
, temp
);
4517 POSTING_READ(PCH_DREF_CONTROL
);
4522 static int ironlake_get_refclk(struct drm_crtc
*crtc
)
4524 struct drm_device
*dev
= crtc
->dev
;
4525 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4526 struct intel_encoder
*encoder
;
4527 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4528 struct intel_encoder
*edp_encoder
= NULL
;
4529 int num_connectors
= 0;
4530 bool is_lvds
= false;
4532 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4533 if (encoder
->base
.crtc
!= crtc
)
4536 switch (encoder
->type
) {
4537 case INTEL_OUTPUT_LVDS
:
4540 case INTEL_OUTPUT_EDP
:
4541 edp_encoder
= encoder
;
4547 if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2) {
4548 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4549 dev_priv
->lvds_ssc_freq
);
4550 return dev_priv
->lvds_ssc_freq
* 1000;
4556 static int ironlake_crtc_mode_set(struct drm_crtc
*crtc
,
4557 struct drm_display_mode
*mode
,
4558 struct drm_display_mode
*adjusted_mode
,
4560 struct drm_framebuffer
*old_fb
)
4562 struct drm_device
*dev
= crtc
->dev
;
4563 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4564 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4565 int pipe
= intel_crtc
->pipe
;
4566 int plane
= intel_crtc
->plane
;
4567 int refclk
, num_connectors
= 0;
4568 intel_clock_t clock
, reduced_clock
;
4569 u32 dpll
, fp
= 0, fp2
= 0, dspcntr
, pipeconf
;
4570 bool ok
, has_reduced_clock
= false, is_sdvo
= false;
4571 bool is_crt
= false, is_lvds
= false, is_tv
= false, is_dp
= false;
4572 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
4573 struct intel_encoder
*encoder
, *edp_encoder
= NULL
;
4574 const intel_limit_t
*limit
;
4576 struct fdi_m_n m_n
= {0};
4578 int target_clock
, pixel_multiplier
, lane
, link_bw
, factor
;
4579 unsigned int pipe_bpp
;
4581 bool is_cpu_edp
= false, is_pch_edp
= false;
4583 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
) {
4584 if (encoder
->base
.crtc
!= crtc
)
4587 switch (encoder
->type
) {
4588 case INTEL_OUTPUT_LVDS
:
4591 case INTEL_OUTPUT_SDVO
:
4592 case INTEL_OUTPUT_HDMI
:
4594 if (encoder
->needs_tv_clock
)
4597 case INTEL_OUTPUT_TVOUT
:
4600 case INTEL_OUTPUT_ANALOG
:
4603 case INTEL_OUTPUT_DISPLAYPORT
:
4606 case INTEL_OUTPUT_EDP
:
4608 if (intel_encoder_is_pch_edp(&encoder
->base
))
4612 edp_encoder
= encoder
;
4619 refclk
= ironlake_get_refclk(crtc
);
4622 * Returns a set of divisors for the desired target clock with the given
4623 * refclk, or FALSE. The returned values represent the clock equation:
4624 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4626 limit
= intel_limit(crtc
, refclk
);
4627 ok
= limit
->find_pll(limit
, crtc
, adjusted_mode
->clock
, refclk
, NULL
,
4630 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4634 /* Ensure that the cursor is valid for the new mode before changing... */
4635 intel_crtc_update_cursor(crtc
, true);
4637 if (is_lvds
&& dev_priv
->lvds_downclock_avail
) {
4639 * Ensure we match the reduced clock's P to the target clock.
4640 * If the clocks don't match, we can't switch the display clock
4641 * by using the FP0/FP1. In such case we will disable the LVDS
4642 * downclock feature.
4644 has_reduced_clock
= limit
->find_pll(limit
, crtc
,
4645 dev_priv
->lvds_downclock
,
4651 if (is_sdvo
&& is_tv
)
4652 i9xx_adjust_sdvo_tv_clock(adjusted_mode
, &clock
);
4656 pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4658 /* CPU eDP doesn't require FDI link, so just set DP M/N
4659 according to current link config */
4661 intel_edp_link_config(edp_encoder
, &lane
, &link_bw
);
4663 /* FDI is a binary signal running at ~2.7GHz, encoding
4664 * each output octet as 10 bits. The actual frequency
4665 * is stored as a divider into a 100MHz clock, and the
4666 * mode pixel clock is stored in units of 1KHz.
4667 * Hence the bw of each lane in terms of the mode signal
4670 link_bw
= intel_fdi_link_freq(dev
) * MHz(100)/KHz(1)/10;
4673 /* [e]DP over FDI requires target mode clock instead of link clock. */
4675 target_clock
= intel_edp_target_clock(edp_encoder
, mode
);
4677 target_clock
= mode
->clock
;
4679 target_clock
= adjusted_mode
->clock
;
4681 /* determine panel color depth */
4682 temp
= I915_READ(PIPECONF(pipe
));
4683 temp
&= ~PIPE_BPC_MASK
;
4684 dither
= intel_choose_pipe_bpp_dither(crtc
, &pipe_bpp
, mode
);
4699 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4706 intel_crtc
->bpp
= pipe_bpp
;
4707 I915_WRITE(PIPECONF(pipe
), temp
);
4711 * Account for spread spectrum to avoid
4712 * oversubscribing the link. Max center spread
4713 * is 2.5%; use 5% for safety's sake.
4715 u32 bps
= target_clock
* intel_crtc
->bpp
* 21 / 20;
4716 lane
= bps
/ (link_bw
* 8) + 1;
4719 intel_crtc
->fdi_lanes
= lane
;
4721 if (pixel_multiplier
> 1)
4722 link_bw
*= pixel_multiplier
;
4723 ironlake_compute_m_n(intel_crtc
->bpp
, lane
, target_clock
, link_bw
,
4726 fp
= clock
.n
<< 16 | clock
.m1
<< 8 | clock
.m2
;
4727 if (has_reduced_clock
)
4728 fp2
= reduced_clock
.n
<< 16 | reduced_clock
.m1
<< 8 |
4731 /* Enable autotuning of the PLL clock (if permissible) */
4734 if ((intel_panel_use_ssc(dev_priv
) &&
4735 dev_priv
->lvds_ssc_freq
== 100) ||
4736 (I915_READ(PCH_LVDS
) & LVDS_CLKB_POWER_MASK
) == LVDS_CLKB_POWER_UP
)
4738 } else if (is_sdvo
&& is_tv
)
4741 if (clock
.m
< factor
* clock
.n
)
4747 dpll
|= DPLLB_MODE_LVDS
;
4749 dpll
|= DPLLB_MODE_DAC_SERIAL
;
4751 int pixel_multiplier
= intel_mode_get_pixel_multiplier(adjusted_mode
);
4752 if (pixel_multiplier
> 1) {
4753 dpll
|= (pixel_multiplier
- 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT
;
4755 dpll
|= DPLL_DVO_HIGH_SPEED
;
4757 if (is_dp
&& !is_cpu_edp
)
4758 dpll
|= DPLL_DVO_HIGH_SPEED
;
4760 /* compute bitmask from p1 value */
4761 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT
;
4763 dpll
|= (1 << (clock
.p1
- 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT
;
4767 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
;
4770 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_7
;
4773 dpll
|= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10
;
4776 dpll
|= DPLLB_LVDS_P2_CLOCK_DIV_14
;
4780 if (is_sdvo
&& is_tv
)
4781 dpll
|= PLL_REF_INPUT_TVCLKINBC
;
4783 /* XXX: just matching BIOS for now */
4784 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4786 else if (is_lvds
&& intel_panel_use_ssc(dev_priv
) && num_connectors
< 2)
4787 dpll
|= PLLB_REF_INPUT_SPREADSPECTRUMIN
;
4789 dpll
|= PLL_REF_INPUT_DREFCLK
;
4791 /* setup pipeconf */
4792 pipeconf
= I915_READ(PIPECONF(pipe
));
4794 /* Set up the display plane register */
4795 dspcntr
= DISPPLANE_GAMMA_ENABLE
;
4797 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe
);
4798 drm_mode_debug_printmodeline(mode
);
4800 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4801 * pre-Haswell/LPT generation */
4802 if (HAS_PCH_LPT(dev
)) {
4803 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4805 } else if (!is_cpu_edp
) {
4806 struct intel_pch_pll
*pll
;
4808 pll
= intel_get_pch_pll(intel_crtc
, dpll
, fp
);
4810 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4815 intel_put_pch_pll(intel_crtc
);
4817 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4818 * This is an exception to the general rule that mode_set doesn't turn
4822 temp
= I915_READ(PCH_LVDS
);
4823 temp
|= LVDS_PORT_EN
| LVDS_A0A2_CLKA_POWER_UP
;
4824 if (HAS_PCH_CPT(dev
)) {
4825 temp
&= ~PORT_TRANS_SEL_MASK
;
4826 temp
|= PORT_TRANS_SEL_CPT(pipe
);
4829 temp
|= LVDS_PIPEB_SELECT
;
4831 temp
&= ~LVDS_PIPEB_SELECT
;
4834 /* set the corresponsding LVDS_BORDER bit */
4835 temp
|= dev_priv
->lvds_border_bits
;
4836 /* Set the B0-B3 data pairs corresponding to whether we're going to
4837 * set the DPLLs for dual-channel mode or not.
4840 temp
|= LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
;
4842 temp
&= ~(LVDS_B0B3_POWER_UP
| LVDS_CLKB_POWER_UP
);
4844 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4845 * appropriately here, but we need to look more thoroughly into how
4846 * panels behave in the two modes.
4848 temp
&= ~(LVDS_HSYNC_POLARITY
| LVDS_VSYNC_POLARITY
);
4849 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NHSYNC
)
4850 temp
|= LVDS_HSYNC_POLARITY
;
4851 if (adjusted_mode
->flags
& DRM_MODE_FLAG_NVSYNC
)
4852 temp
|= LVDS_VSYNC_POLARITY
;
4853 I915_WRITE(PCH_LVDS
, temp
);
4856 pipeconf
&= ~PIPECONF_DITHER_EN
;
4857 pipeconf
&= ~PIPECONF_DITHER_TYPE_MASK
;
4858 if ((is_lvds
&& dev_priv
->lvds_dither
) || dither
) {
4859 pipeconf
|= PIPECONF_DITHER_EN
;
4860 pipeconf
|= PIPECONF_DITHER_TYPE_SP
;
4862 if (is_dp
&& !is_cpu_edp
) {
4863 intel_dp_set_m_n(crtc
, mode
, adjusted_mode
);
4865 /* For non-DP output, clear any trans DP clock recovery setting.*/
4866 I915_WRITE(TRANSDATA_M1(pipe
), 0);
4867 I915_WRITE(TRANSDATA_N1(pipe
), 0);
4868 I915_WRITE(TRANSDPLINK_M1(pipe
), 0);
4869 I915_WRITE(TRANSDPLINK_N1(pipe
), 0);
4872 if (intel_crtc
->pch_pll
) {
4873 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4875 /* Wait for the clocks to stabilize. */
4876 POSTING_READ(intel_crtc
->pch_pll
->pll_reg
);
4879 /* The pixel multiplier can only be updated once the
4880 * DPLL is enabled and the clocks are stable.
4882 * So write it again.
4884 I915_WRITE(intel_crtc
->pch_pll
->pll_reg
, dpll
);
4887 intel_crtc
->lowfreq_avail
= false;
4888 if (intel_crtc
->pch_pll
) {
4889 if (is_lvds
&& has_reduced_clock
&& i915_powersave
) {
4890 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp2
);
4891 intel_crtc
->lowfreq_avail
= true;
4893 I915_WRITE(intel_crtc
->pch_pll
->fp1_reg
, fp
);
4897 pipeconf
&= ~PIPECONF_INTERLACE_MASK
;
4898 if (adjusted_mode
->flags
& DRM_MODE_FLAG_INTERLACE
) {
4899 pipeconf
|= PIPECONF_INTERLACED_ILK
;
4900 /* the chip adds 2 halflines automatically */
4901 adjusted_mode
->crtc_vtotal
-= 1;
4902 adjusted_mode
->crtc_vblank_end
-= 1;
4903 I915_WRITE(VSYNCSHIFT(pipe
),
4904 adjusted_mode
->crtc_hsync_start
4905 - adjusted_mode
->crtc_htotal
/2);
4907 pipeconf
|= PIPECONF_PROGRESSIVE
;
4908 I915_WRITE(VSYNCSHIFT(pipe
), 0);
4911 I915_WRITE(HTOTAL(pipe
),
4912 (adjusted_mode
->crtc_hdisplay
- 1) |
4913 ((adjusted_mode
->crtc_htotal
- 1) << 16));
4914 I915_WRITE(HBLANK(pipe
),
4915 (adjusted_mode
->crtc_hblank_start
- 1) |
4916 ((adjusted_mode
->crtc_hblank_end
- 1) << 16));
4917 I915_WRITE(HSYNC(pipe
),
4918 (adjusted_mode
->crtc_hsync_start
- 1) |
4919 ((adjusted_mode
->crtc_hsync_end
- 1) << 16));
4921 I915_WRITE(VTOTAL(pipe
),
4922 (adjusted_mode
->crtc_vdisplay
- 1) |
4923 ((adjusted_mode
->crtc_vtotal
- 1) << 16));
4924 I915_WRITE(VBLANK(pipe
),
4925 (adjusted_mode
->crtc_vblank_start
- 1) |
4926 ((adjusted_mode
->crtc_vblank_end
- 1) << 16));
4927 I915_WRITE(VSYNC(pipe
),
4928 (adjusted_mode
->crtc_vsync_start
- 1) |
4929 ((adjusted_mode
->crtc_vsync_end
- 1) << 16));
4931 /* pipesrc controls the size that is scaled from, which should
4932 * always be the user's requested size.
4934 I915_WRITE(PIPESRC(pipe
),
4935 ((mode
->hdisplay
- 1) << 16) | (mode
->vdisplay
- 1));
4937 I915_WRITE(PIPE_DATA_M1(pipe
), TU_SIZE(m_n
.tu
) | m_n
.gmch_m
);
4938 I915_WRITE(PIPE_DATA_N1(pipe
), m_n
.gmch_n
);
4939 I915_WRITE(PIPE_LINK_M1(pipe
), m_n
.link_m
);
4940 I915_WRITE(PIPE_LINK_N1(pipe
), m_n
.link_n
);
4943 ironlake_set_pll_edp(crtc
, adjusted_mode
->clock
);
4945 I915_WRITE(PIPECONF(pipe
), pipeconf
);
4946 POSTING_READ(PIPECONF(pipe
));
4948 intel_wait_for_vblank(dev
, pipe
);
4950 I915_WRITE(DSPCNTR(plane
), dspcntr
);
4951 POSTING_READ(DSPCNTR(plane
));
4953 ret
= intel_pipe_set_base(crtc
, x
, y
, old_fb
);
4955 intel_update_watermarks(dev
);
4957 intel_update_linetime_watermarks(dev
, pipe
, adjusted_mode
);
4962 static int intel_crtc_mode_set(struct drm_crtc
*crtc
,
4963 struct drm_display_mode
*mode
,
4964 struct drm_display_mode
*adjusted_mode
,
4966 struct drm_framebuffer
*old_fb
)
4968 struct drm_device
*dev
= crtc
->dev
;
4969 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
4970 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
4971 int pipe
= intel_crtc
->pipe
;
4974 drm_vblank_pre_modeset(dev
, pipe
);
4976 ret
= dev_priv
->display
.crtc_mode_set(crtc
, mode
, adjusted_mode
,
4978 drm_vblank_post_modeset(dev
, pipe
);
4981 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_OFF
;
4983 intel_crtc
->dpms_mode
= DRM_MODE_DPMS_ON
;
4988 static bool intel_eld_uptodate(struct drm_connector
*connector
,
4989 int reg_eldv
, uint32_t bits_eldv
,
4990 int reg_elda
, uint32_t bits_elda
,
4993 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
4994 uint8_t *eld
= connector
->eld
;
4997 i
= I915_READ(reg_eldv
);
5006 i
= I915_READ(reg_elda
);
5008 I915_WRITE(reg_elda
, i
);
5010 for (i
= 0; i
< eld
[2]; i
++)
5011 if (I915_READ(reg_edid
) != *((uint32_t *)eld
+ i
))
5017 static void g4x_write_eld(struct drm_connector
*connector
,
5018 struct drm_crtc
*crtc
)
5020 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5021 uint8_t *eld
= connector
->eld
;
5026 i
= I915_READ(G4X_AUD_VID_DID
);
5028 if (i
== INTEL_AUDIO_DEVBLC
|| i
== INTEL_AUDIO_DEVCL
)
5029 eldv
= G4X_ELDV_DEVCL_DEVBLC
;
5031 eldv
= G4X_ELDV_DEVCTG
;
5033 if (intel_eld_uptodate(connector
,
5034 G4X_AUD_CNTL_ST
, eldv
,
5035 G4X_AUD_CNTL_ST
, G4X_ELD_ADDR
,
5036 G4X_HDMIW_HDMIEDID
))
5039 i
= I915_READ(G4X_AUD_CNTL_ST
);
5040 i
&= ~(eldv
| G4X_ELD_ADDR
);
5041 len
= (i
>> 9) & 0x1f; /* ELD buffer size */
5042 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5047 len
= min_t(uint8_t, eld
[2], len
);
5048 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5049 for (i
= 0; i
< len
; i
++)
5050 I915_WRITE(G4X_HDMIW_HDMIEDID
, *((uint32_t *)eld
+ i
));
5052 i
= I915_READ(G4X_AUD_CNTL_ST
);
5054 I915_WRITE(G4X_AUD_CNTL_ST
, i
);
5057 static void ironlake_write_eld(struct drm_connector
*connector
,
5058 struct drm_crtc
*crtc
)
5060 struct drm_i915_private
*dev_priv
= connector
->dev
->dev_private
;
5061 uint8_t *eld
= connector
->eld
;
5070 if (HAS_PCH_IBX(connector
->dev
)) {
5071 hdmiw_hdmiedid
= IBX_HDMIW_HDMIEDID_A
;
5072 aud_config
= IBX_AUD_CONFIG_A
;
5073 aud_cntl_st
= IBX_AUD_CNTL_ST_A
;
5074 aud_cntrl_st2
= IBX_AUD_CNTL_ST2
;
5076 hdmiw_hdmiedid
= CPT_HDMIW_HDMIEDID_A
;
5077 aud_config
= CPT_AUD_CONFIG_A
;
5078 aud_cntl_st
= CPT_AUD_CNTL_ST_A
;
5079 aud_cntrl_st2
= CPT_AUD_CNTRL_ST2
;
5082 i
= to_intel_crtc(crtc
)->pipe
;
5083 hdmiw_hdmiedid
+= i
* 0x100;
5084 aud_cntl_st
+= i
* 0x100;
5085 aud_config
+= i
* 0x100;
5087 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i
));
5089 i
= I915_READ(aud_cntl_st
);
5090 i
= (i
>> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5092 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5093 /* operate blindly on all ports */
5094 eldv
= IBX_ELD_VALIDB
;
5095 eldv
|= IBX_ELD_VALIDB
<< 4;
5096 eldv
|= IBX_ELD_VALIDB
<< 8;
5098 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i
);
5099 eldv
= IBX_ELD_VALIDB
<< ((i
- 1) * 4);
5102 if (intel_pipe_has_type(crtc
, INTEL_OUTPUT_DISPLAYPORT
)) {
5103 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5104 eld
[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5105 I915_WRITE(aud_config
, AUD_CONFIG_N_VALUE_INDEX
); /* 0x1 = DP */
5107 I915_WRITE(aud_config
, 0);
5109 if (intel_eld_uptodate(connector
,
5110 aud_cntrl_st2
, eldv
,
5111 aud_cntl_st
, IBX_ELD_ADDRESS
,
5115 i
= I915_READ(aud_cntrl_st2
);
5117 I915_WRITE(aud_cntrl_st2
, i
);
5122 i
= I915_READ(aud_cntl_st
);
5123 i
&= ~IBX_ELD_ADDRESS
;
5124 I915_WRITE(aud_cntl_st
, i
);
5126 len
= min_t(uint8_t, eld
[2], 21); /* 84 bytes of hw ELD buffer */
5127 DRM_DEBUG_DRIVER("ELD size %d\n", len
);
5128 for (i
= 0; i
< len
; i
++)
5129 I915_WRITE(hdmiw_hdmiedid
, *((uint32_t *)eld
+ i
));
5131 i
= I915_READ(aud_cntrl_st2
);
5133 I915_WRITE(aud_cntrl_st2
, i
);
5136 void intel_write_eld(struct drm_encoder
*encoder
,
5137 struct drm_display_mode
*mode
)
5139 struct drm_crtc
*crtc
= encoder
->crtc
;
5140 struct drm_connector
*connector
;
5141 struct drm_device
*dev
= encoder
->dev
;
5142 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5144 connector
= drm_select_eld(encoder
, mode
);
5148 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5150 drm_get_connector_name(connector
),
5151 connector
->encoder
->base
.id
,
5152 drm_get_encoder_name(connector
->encoder
));
5154 connector
->eld
[6] = drm_av_sync_delay(connector
, mode
) / 2;
5156 if (dev_priv
->display
.write_eld
)
5157 dev_priv
->display
.write_eld(connector
, crtc
);
5160 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5161 void intel_crtc_load_lut(struct drm_crtc
*crtc
)
5163 struct drm_device
*dev
= crtc
->dev
;
5164 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5165 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5166 int palreg
= PALETTE(intel_crtc
->pipe
);
5169 /* The clocks have to be on to load the palette. */
5170 if (!crtc
->enabled
|| !intel_crtc
->active
)
5173 /* use legacy palette for Ironlake */
5174 if (HAS_PCH_SPLIT(dev
))
5175 palreg
= LGC_PALETTE(intel_crtc
->pipe
);
5177 for (i
= 0; i
< 256; i
++) {
5178 I915_WRITE(palreg
+ 4 * i
,
5179 (intel_crtc
->lut_r
[i
] << 16) |
5180 (intel_crtc
->lut_g
[i
] << 8) |
5181 intel_crtc
->lut_b
[i
]);
5185 static void i845_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5187 struct drm_device
*dev
= crtc
->dev
;
5188 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5189 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5190 bool visible
= base
!= 0;
5193 if (intel_crtc
->cursor_visible
== visible
)
5196 cntl
= I915_READ(_CURACNTR
);
5198 /* On these chipsets we can only modify the base whilst
5199 * the cursor is disabled.
5201 I915_WRITE(_CURABASE
, base
);
5203 cntl
&= ~(CURSOR_FORMAT_MASK
);
5204 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5205 cntl
|= CURSOR_ENABLE
|
5206 CURSOR_GAMMA_ENABLE
|
5209 cntl
&= ~(CURSOR_ENABLE
| CURSOR_GAMMA_ENABLE
);
5210 I915_WRITE(_CURACNTR
, cntl
);
5212 intel_crtc
->cursor_visible
= visible
;
5215 static void i9xx_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5217 struct drm_device
*dev
= crtc
->dev
;
5218 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5219 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5220 int pipe
= intel_crtc
->pipe
;
5221 bool visible
= base
!= 0;
5223 if (intel_crtc
->cursor_visible
!= visible
) {
5224 uint32_t cntl
= I915_READ(CURCNTR(pipe
));
5226 cntl
&= ~(CURSOR_MODE
| MCURSOR_PIPE_SELECT
);
5227 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5228 cntl
|= pipe
<< 28; /* Connect to correct pipe */
5230 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5231 cntl
|= CURSOR_MODE_DISABLE
;
5233 I915_WRITE(CURCNTR(pipe
), cntl
);
5235 intel_crtc
->cursor_visible
= visible
;
5237 /* and commit changes on next vblank */
5238 I915_WRITE(CURBASE(pipe
), base
);
5241 static void ivb_update_cursor(struct drm_crtc
*crtc
, u32 base
)
5243 struct drm_device
*dev
= crtc
->dev
;
5244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5245 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5246 int pipe
= intel_crtc
->pipe
;
5247 bool visible
= base
!= 0;
5249 if (intel_crtc
->cursor_visible
!= visible
) {
5250 uint32_t cntl
= I915_READ(CURCNTR_IVB(pipe
));
5252 cntl
&= ~CURSOR_MODE
;
5253 cntl
|= CURSOR_MODE_64_ARGB_AX
| MCURSOR_GAMMA_ENABLE
;
5255 cntl
&= ~(CURSOR_MODE
| MCURSOR_GAMMA_ENABLE
);
5256 cntl
|= CURSOR_MODE_DISABLE
;
5258 I915_WRITE(CURCNTR_IVB(pipe
), cntl
);
5260 intel_crtc
->cursor_visible
= visible
;
5262 /* and commit changes on next vblank */
5263 I915_WRITE(CURBASE_IVB(pipe
), base
);
5266 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
5267 static void intel_crtc_update_cursor(struct drm_crtc
*crtc
,
5270 struct drm_device
*dev
= crtc
->dev
;
5271 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5272 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5273 int pipe
= intel_crtc
->pipe
;
5274 int x
= intel_crtc
->cursor_x
;
5275 int y
= intel_crtc
->cursor_y
;
5281 if (on
&& crtc
->enabled
&& crtc
->fb
) {
5282 base
= intel_crtc
->cursor_addr
;
5283 if (x
> (int) crtc
->fb
->width
)
5286 if (y
> (int) crtc
->fb
->height
)
5292 if (x
+ intel_crtc
->cursor_width
< 0)
5295 pos
|= CURSOR_POS_SIGN
<< CURSOR_X_SHIFT
;
5298 pos
|= x
<< CURSOR_X_SHIFT
;
5301 if (y
+ intel_crtc
->cursor_height
< 0)
5304 pos
|= CURSOR_POS_SIGN
<< CURSOR_Y_SHIFT
;
5307 pos
|= y
<< CURSOR_Y_SHIFT
;
5309 visible
= base
!= 0;
5310 if (!visible
&& !intel_crtc
->cursor_visible
)
5313 if (IS_IVYBRIDGE(dev
) || IS_HASWELL(dev
)) {
5314 I915_WRITE(CURPOS_IVB(pipe
), pos
);
5315 ivb_update_cursor(crtc
, base
);
5317 I915_WRITE(CURPOS(pipe
), pos
);
5318 if (IS_845G(dev
) || IS_I865G(dev
))
5319 i845_update_cursor(crtc
, base
);
5321 i9xx_update_cursor(crtc
, base
);
5325 static int intel_crtc_cursor_set(struct drm_crtc
*crtc
,
5326 struct drm_file
*file
,
5328 uint32_t width
, uint32_t height
)
5330 struct drm_device
*dev
= crtc
->dev
;
5331 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5332 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5333 struct drm_i915_gem_object
*obj
;
5337 DRM_DEBUG_KMS("\n");
5339 /* if we want to turn off the cursor ignore width and height */
5341 DRM_DEBUG_KMS("cursor off\n");
5344 mutex_lock(&dev
->struct_mutex
);
5348 /* Currently we only support 64x64 cursors */
5349 if (width
!= 64 || height
!= 64) {
5350 DRM_ERROR("we currently only support 64x64 cursors\n");
5354 obj
= to_intel_bo(drm_gem_object_lookup(dev
, file
, handle
));
5355 if (&obj
->base
== NULL
)
5358 if (obj
->base
.size
< width
* height
* 4) {
5359 DRM_ERROR("buffer is to small\n");
5364 /* we only need to pin inside GTT if cursor is non-phy */
5365 mutex_lock(&dev
->struct_mutex
);
5366 if (!dev_priv
->info
->cursor_needs_physical
) {
5367 if (obj
->tiling_mode
) {
5368 DRM_ERROR("cursor cannot be tiled\n");
5373 ret
= i915_gem_object_pin_to_display_plane(obj
, 0, NULL
);
5375 DRM_ERROR("failed to move cursor bo into the GTT\n");
5379 ret
= i915_gem_object_put_fence(obj
);
5381 DRM_ERROR("failed to release fence for cursor");
5385 addr
= obj
->gtt_offset
;
5387 int align
= IS_I830(dev
) ? 16 * 1024 : 256;
5388 ret
= i915_gem_attach_phys_object(dev
, obj
,
5389 (intel_crtc
->pipe
== 0) ? I915_GEM_PHYS_CURSOR_0
: I915_GEM_PHYS_CURSOR_1
,
5392 DRM_ERROR("failed to attach phys object\n");
5395 addr
= obj
->phys_obj
->handle
->busaddr
;
5399 I915_WRITE(CURSIZE
, (height
<< 12) | width
);
5402 if (intel_crtc
->cursor_bo
) {
5403 if (dev_priv
->info
->cursor_needs_physical
) {
5404 if (intel_crtc
->cursor_bo
!= obj
)
5405 i915_gem_detach_phys_object(dev
, intel_crtc
->cursor_bo
);
5407 i915_gem_object_unpin(intel_crtc
->cursor_bo
);
5408 drm_gem_object_unreference(&intel_crtc
->cursor_bo
->base
);
5411 mutex_unlock(&dev
->struct_mutex
);
5413 intel_crtc
->cursor_addr
= addr
;
5414 intel_crtc
->cursor_bo
= obj
;
5415 intel_crtc
->cursor_width
= width
;
5416 intel_crtc
->cursor_height
= height
;
5418 intel_crtc_update_cursor(crtc
, true);
5422 i915_gem_object_unpin(obj
);
5424 mutex_unlock(&dev
->struct_mutex
);
5426 drm_gem_object_unreference_unlocked(&obj
->base
);
5430 static int intel_crtc_cursor_move(struct drm_crtc
*crtc
, int x
, int y
)
5432 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5434 intel_crtc
->cursor_x
= x
;
5435 intel_crtc
->cursor_y
= y
;
5437 intel_crtc_update_cursor(crtc
, true);
5442 /** Sets the color ramps on behalf of RandR */
5443 void intel_crtc_fb_gamma_set(struct drm_crtc
*crtc
, u16 red
, u16 green
,
5444 u16 blue
, int regno
)
5446 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5448 intel_crtc
->lut_r
[regno
] = red
>> 8;
5449 intel_crtc
->lut_g
[regno
] = green
>> 8;
5450 intel_crtc
->lut_b
[regno
] = blue
>> 8;
5453 void intel_crtc_fb_gamma_get(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5454 u16
*blue
, int regno
)
5456 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5458 *red
= intel_crtc
->lut_r
[regno
] << 8;
5459 *green
= intel_crtc
->lut_g
[regno
] << 8;
5460 *blue
= intel_crtc
->lut_b
[regno
] << 8;
5463 static void intel_crtc_gamma_set(struct drm_crtc
*crtc
, u16
*red
, u16
*green
,
5464 u16
*blue
, uint32_t start
, uint32_t size
)
5466 int end
= (start
+ size
> 256) ? 256 : start
+ size
, i
;
5467 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5469 for (i
= start
; i
< end
; i
++) {
5470 intel_crtc
->lut_r
[i
] = red
[i
] >> 8;
5471 intel_crtc
->lut_g
[i
] = green
[i
] >> 8;
5472 intel_crtc
->lut_b
[i
] = blue
[i
] >> 8;
5475 intel_crtc_load_lut(crtc
);
5479 * Get a pipe with a simple mode set on it for doing load-based monitor
5482 * It will be up to the load-detect code to adjust the pipe as appropriate for
5483 * its requirements. The pipe will be connected to no other encoders.
5485 * Currently this code will only succeed if there is a pipe with no encoders
5486 * configured for it. In the future, it could choose to temporarily disable
5487 * some outputs to free up a pipe for its use.
5489 * \return crtc, or NULL if no pipes are available.
5492 /* VESA 640x480x72Hz mode to set on the pipe */
5493 static struct drm_display_mode load_detect_mode
= {
5494 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT
, 31500, 640, 664,
5495 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC
| DRM_MODE_FLAG_NVSYNC
),
5498 static struct drm_framebuffer
*
5499 intel_framebuffer_create(struct drm_device
*dev
,
5500 struct drm_mode_fb_cmd2
*mode_cmd
,
5501 struct drm_i915_gem_object
*obj
)
5503 struct intel_framebuffer
*intel_fb
;
5506 intel_fb
= kzalloc(sizeof(*intel_fb
), GFP_KERNEL
);
5508 drm_gem_object_unreference_unlocked(&obj
->base
);
5509 return ERR_PTR(-ENOMEM
);
5512 ret
= intel_framebuffer_init(dev
, intel_fb
, mode_cmd
, obj
);
5514 drm_gem_object_unreference_unlocked(&obj
->base
);
5516 return ERR_PTR(ret
);
5519 return &intel_fb
->base
;
5523 intel_framebuffer_pitch_for_width(int width
, int bpp
)
5525 u32 pitch
= DIV_ROUND_UP(width
* bpp
, 8);
5526 return ALIGN(pitch
, 64);
5530 intel_framebuffer_size_for_mode(struct drm_display_mode
*mode
, int bpp
)
5532 u32 pitch
= intel_framebuffer_pitch_for_width(mode
->hdisplay
, bpp
);
5533 return ALIGN(pitch
* mode
->vdisplay
, PAGE_SIZE
);
5536 static struct drm_framebuffer
*
5537 intel_framebuffer_create_for_mode(struct drm_device
*dev
,
5538 struct drm_display_mode
*mode
,
5541 struct drm_i915_gem_object
*obj
;
5542 struct drm_mode_fb_cmd2 mode_cmd
;
5544 obj
= i915_gem_alloc_object(dev
,
5545 intel_framebuffer_size_for_mode(mode
, bpp
));
5547 return ERR_PTR(-ENOMEM
);
5549 mode_cmd
.width
= mode
->hdisplay
;
5550 mode_cmd
.height
= mode
->vdisplay
;
5551 mode_cmd
.pitches
[0] = intel_framebuffer_pitch_for_width(mode_cmd
.width
,
5553 mode_cmd
.pixel_format
= drm_mode_legacy_fb_format(bpp
, depth
);
5555 return intel_framebuffer_create(dev
, &mode_cmd
, obj
);
5558 static struct drm_framebuffer
*
5559 mode_fits_in_fbdev(struct drm_device
*dev
,
5560 struct drm_display_mode
*mode
)
5562 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5563 struct drm_i915_gem_object
*obj
;
5564 struct drm_framebuffer
*fb
;
5566 if (dev_priv
->fbdev
== NULL
)
5569 obj
= dev_priv
->fbdev
->ifb
.obj
;
5573 fb
= &dev_priv
->fbdev
->ifb
.base
;
5574 if (fb
->pitches
[0] < intel_framebuffer_pitch_for_width(mode
->hdisplay
,
5575 fb
->bits_per_pixel
))
5578 if (obj
->base
.size
< mode
->vdisplay
* fb
->pitches
[0])
5584 bool intel_get_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5585 struct drm_connector
*connector
,
5586 struct drm_display_mode
*mode
,
5587 struct intel_load_detect_pipe
*old
)
5589 struct intel_crtc
*intel_crtc
;
5590 struct drm_crtc
*possible_crtc
;
5591 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5592 struct drm_crtc
*crtc
= NULL
;
5593 struct drm_device
*dev
= encoder
->dev
;
5594 struct drm_framebuffer
*old_fb
;
5597 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5598 connector
->base
.id
, drm_get_connector_name(connector
),
5599 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5602 * Algorithm gets a little messy:
5604 * - if the connector already has an assigned crtc, use it (but make
5605 * sure it's on first)
5607 * - try to find the first unused crtc that can drive this connector,
5608 * and use that if we find one
5611 /* See if we already have a CRTC for this connector */
5612 if (encoder
->crtc
) {
5613 crtc
= encoder
->crtc
;
5615 intel_crtc
= to_intel_crtc(crtc
);
5616 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5617 old
->load_detect_temp
= false;
5619 /* Make sure the crtc and connector are running */
5620 if (intel_crtc
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5621 struct drm_encoder_helper_funcs
*encoder_funcs
;
5622 struct drm_crtc_helper_funcs
*crtc_funcs
;
5624 crtc_funcs
= crtc
->helper_private
;
5625 crtc_funcs
->dpms(crtc
, DRM_MODE_DPMS_ON
);
5627 encoder_funcs
= encoder
->helper_private
;
5628 encoder_funcs
->dpms(encoder
, DRM_MODE_DPMS_ON
);
5634 /* Find an unused one (if possible) */
5635 list_for_each_entry(possible_crtc
, &dev
->mode_config
.crtc_list
, head
) {
5637 if (!(encoder
->possible_crtcs
& (1 << i
)))
5639 if (!possible_crtc
->enabled
) {
5640 crtc
= possible_crtc
;
5646 * If we didn't find an unused CRTC, don't use any.
5649 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5653 encoder
->crtc
= crtc
;
5654 connector
->encoder
= encoder
;
5656 intel_crtc
= to_intel_crtc(crtc
);
5657 old
->dpms_mode
= intel_crtc
->dpms_mode
;
5658 old
->load_detect_temp
= true;
5659 old
->release_fb
= NULL
;
5662 mode
= &load_detect_mode
;
5666 /* We need a framebuffer large enough to accommodate all accesses
5667 * that the plane may generate whilst we perform load detection.
5668 * We can not rely on the fbcon either being present (we get called
5669 * during its initialisation to detect all boot displays, or it may
5670 * not even exist) or that it is large enough to satisfy the
5673 crtc
->fb
= mode_fits_in_fbdev(dev
, mode
);
5674 if (crtc
->fb
== NULL
) {
5675 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5676 crtc
->fb
= intel_framebuffer_create_for_mode(dev
, mode
, 24, 32);
5677 old
->release_fb
= crtc
->fb
;
5679 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5680 if (IS_ERR(crtc
->fb
)) {
5681 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5686 if (!drm_crtc_helper_set_mode(crtc
, mode
, 0, 0, old_fb
)) {
5687 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
5688 if (old
->release_fb
)
5689 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5694 /* let the connector get through one full cycle before testing */
5695 intel_wait_for_vblank(dev
, intel_crtc
->pipe
);
5700 void intel_release_load_detect_pipe(struct intel_encoder
*intel_encoder
,
5701 struct drm_connector
*connector
,
5702 struct intel_load_detect_pipe
*old
)
5704 struct drm_encoder
*encoder
= &intel_encoder
->base
;
5705 struct drm_device
*dev
= encoder
->dev
;
5706 struct drm_crtc
*crtc
= encoder
->crtc
;
5707 struct drm_encoder_helper_funcs
*encoder_funcs
= encoder
->helper_private
;
5708 struct drm_crtc_helper_funcs
*crtc_funcs
= crtc
->helper_private
;
5710 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5711 connector
->base
.id
, drm_get_connector_name(connector
),
5712 encoder
->base
.id
, drm_get_encoder_name(encoder
));
5714 if (old
->load_detect_temp
) {
5715 connector
->encoder
= NULL
;
5716 drm_helper_disable_unused_functions(dev
);
5718 if (old
->release_fb
)
5719 old
->release_fb
->funcs
->destroy(old
->release_fb
);
5724 /* Switch crtc and encoder back off if necessary */
5725 if (old
->dpms_mode
!= DRM_MODE_DPMS_ON
) {
5726 encoder_funcs
->dpms(encoder
, old
->dpms_mode
);
5727 crtc_funcs
->dpms(crtc
, old
->dpms_mode
);
5731 /* Returns the clock of the currently programmed mode of the given pipe. */
5732 static int intel_crtc_clock_get(struct drm_device
*dev
, struct drm_crtc
*crtc
)
5734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5735 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5736 int pipe
= intel_crtc
->pipe
;
5737 u32 dpll
= I915_READ(DPLL(pipe
));
5739 intel_clock_t clock
;
5741 if ((dpll
& DISPLAY_RATE_SELECT_FPA1
) == 0)
5742 fp
= I915_READ(FP0(pipe
));
5744 fp
= I915_READ(FP1(pipe
));
5746 clock
.m1
= (fp
& FP_M1_DIV_MASK
) >> FP_M1_DIV_SHIFT
;
5747 if (IS_PINEVIEW(dev
)) {
5748 clock
.n
= ffs((fp
& FP_N_PINEVIEW_DIV_MASK
) >> FP_N_DIV_SHIFT
) - 1;
5749 clock
.m2
= (fp
& FP_M2_PINEVIEW_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5751 clock
.n
= (fp
& FP_N_DIV_MASK
) >> FP_N_DIV_SHIFT
;
5752 clock
.m2
= (fp
& FP_M2_DIV_MASK
) >> FP_M2_DIV_SHIFT
;
5755 if (!IS_GEN2(dev
)) {
5756 if (IS_PINEVIEW(dev
))
5757 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW
) >>
5758 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW
);
5760 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK
) >>
5761 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5763 switch (dpll
& DPLL_MODE_MASK
) {
5764 case DPLLB_MODE_DAC_SERIAL
:
5765 clock
.p2
= dpll
& DPLL_DAC_SERIAL_P2_CLOCK_DIV_5
?
5768 case DPLLB_MODE_LVDS
:
5769 clock
.p2
= dpll
& DPLLB_LVDS_P2_CLOCK_DIV_7
?
5773 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
5774 "mode\n", (int)(dpll
& DPLL_MODE_MASK
));
5778 /* XXX: Handle the 100Mhz refclk */
5779 intel_clock(dev
, 96000, &clock
);
5781 bool is_lvds
= (pipe
== 1) && (I915_READ(LVDS
) & LVDS_PORT_EN
);
5784 clock
.p1
= ffs((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS
) >>
5785 DPLL_FPA01_P1_POST_DIV_SHIFT
);
5788 if ((dpll
& PLL_REF_INPUT_MASK
) ==
5789 PLLB_REF_INPUT_SPREADSPECTRUMIN
) {
5790 /* XXX: might not be 66MHz */
5791 intel_clock(dev
, 66000, &clock
);
5793 intel_clock(dev
, 48000, &clock
);
5795 if (dpll
& PLL_P1_DIVIDE_BY_TWO
)
5798 clock
.p1
= ((dpll
& DPLL_FPA01_P1_POST_DIV_MASK_I830
) >>
5799 DPLL_FPA01_P1_POST_DIV_SHIFT
) + 2;
5801 if (dpll
& PLL_P2_DIVIDE_BY_4
)
5806 intel_clock(dev
, 48000, &clock
);
5810 /* XXX: It would be nice to validate the clocks, but we can't reuse
5811 * i830PllIsValid() because it relies on the xf86_config connector
5812 * configuration being accurate, which it isn't necessarily.
5818 /** Returns the currently programmed mode of the given pipe. */
5819 struct drm_display_mode
*intel_crtc_mode_get(struct drm_device
*dev
,
5820 struct drm_crtc
*crtc
)
5822 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
5823 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5824 int pipe
= intel_crtc
->pipe
;
5825 struct drm_display_mode
*mode
;
5826 int htot
= I915_READ(HTOTAL(pipe
));
5827 int hsync
= I915_READ(HSYNC(pipe
));
5828 int vtot
= I915_READ(VTOTAL(pipe
));
5829 int vsync
= I915_READ(VSYNC(pipe
));
5831 mode
= kzalloc(sizeof(*mode
), GFP_KERNEL
);
5835 mode
->clock
= intel_crtc_clock_get(dev
, crtc
);
5836 mode
->hdisplay
= (htot
& 0xffff) + 1;
5837 mode
->htotal
= ((htot
& 0xffff0000) >> 16) + 1;
5838 mode
->hsync_start
= (hsync
& 0xffff) + 1;
5839 mode
->hsync_end
= ((hsync
& 0xffff0000) >> 16) + 1;
5840 mode
->vdisplay
= (vtot
& 0xffff) + 1;
5841 mode
->vtotal
= ((vtot
& 0xffff0000) >> 16) + 1;
5842 mode
->vsync_start
= (vsync
& 0xffff) + 1;
5843 mode
->vsync_end
= ((vsync
& 0xffff0000) >> 16) + 1;
5845 drm_mode_set_name(mode
);
5850 #define GPU_IDLE_TIMEOUT 500 /* ms */
5852 /* When this timer fires, we've been idle for awhile */
5853 static void intel_gpu_idle_timer(unsigned long arg
)
5855 struct drm_device
*dev
= (struct drm_device
*)arg
;
5856 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5858 if (!list_empty(&dev_priv
->mm
.active_list
)) {
5859 /* Still processing requests, so just re-arm the timer. */
5860 mod_timer(&dev_priv
->idle_timer
, jiffies
+
5861 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
5865 dev_priv
->busy
= false;
5866 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5869 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
5871 static void intel_crtc_idle_timer(unsigned long arg
)
5873 struct intel_crtc
*intel_crtc
= (struct intel_crtc
*)arg
;
5874 struct drm_crtc
*crtc
= &intel_crtc
->base
;
5875 drm_i915_private_t
*dev_priv
= crtc
->dev
->dev_private
;
5876 struct intel_framebuffer
*intel_fb
;
5878 intel_fb
= to_intel_framebuffer(crtc
->fb
);
5879 if (intel_fb
&& intel_fb
->obj
->active
) {
5880 /* The framebuffer is still being accessed by the GPU. */
5881 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5882 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5886 intel_crtc
->busy
= false;
5887 queue_work(dev_priv
->wq
, &dev_priv
->idle_work
);
5890 static void intel_increase_pllclock(struct drm_crtc
*crtc
)
5892 struct drm_device
*dev
= crtc
->dev
;
5893 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5894 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5895 int pipe
= intel_crtc
->pipe
;
5896 int dpll_reg
= DPLL(pipe
);
5899 if (HAS_PCH_SPLIT(dev
))
5902 if (!dev_priv
->lvds_downclock_avail
)
5905 dpll
= I915_READ(dpll_reg
);
5906 if (!HAS_PIPE_CXSR(dev
) && (dpll
& DISPLAY_RATE_SELECT_FPA1
)) {
5907 DRM_DEBUG_DRIVER("upclocking LVDS\n");
5909 assert_panel_unlocked(dev_priv
, pipe
);
5911 dpll
&= ~DISPLAY_RATE_SELECT_FPA1
;
5912 I915_WRITE(dpll_reg
, dpll
);
5913 intel_wait_for_vblank(dev
, pipe
);
5915 dpll
= I915_READ(dpll_reg
);
5916 if (dpll
& DISPLAY_RATE_SELECT_FPA1
)
5917 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
5920 /* Schedule downclock */
5921 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
5922 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
5925 static void intel_decrease_pllclock(struct drm_crtc
*crtc
)
5927 struct drm_device
*dev
= crtc
->dev
;
5928 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
5929 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
5931 if (HAS_PCH_SPLIT(dev
))
5934 if (!dev_priv
->lvds_downclock_avail
)
5938 * Since this is called by a timer, we should never get here in
5941 if (!HAS_PIPE_CXSR(dev
) && intel_crtc
->lowfreq_avail
) {
5942 int pipe
= intel_crtc
->pipe
;
5943 int dpll_reg
= DPLL(pipe
);
5946 DRM_DEBUG_DRIVER("downclocking LVDS\n");
5948 assert_panel_unlocked(dev_priv
, pipe
);
5950 dpll
= I915_READ(dpll_reg
);
5951 dpll
|= DISPLAY_RATE_SELECT_FPA1
;
5952 I915_WRITE(dpll_reg
, dpll
);
5953 intel_wait_for_vblank(dev
, pipe
);
5954 dpll
= I915_READ(dpll_reg
);
5955 if (!(dpll
& DISPLAY_RATE_SELECT_FPA1
))
5956 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
5962 * intel_idle_update - adjust clocks for idleness
5963 * @work: work struct
5965 * Either the GPU or display (or both) went idle. Check the busy status
5966 * here and adjust the CRTC and GPU clocks as necessary.
5968 static void intel_idle_update(struct work_struct
*work
)
5970 drm_i915_private_t
*dev_priv
= container_of(work
, drm_i915_private_t
,
5972 struct drm_device
*dev
= dev_priv
->dev
;
5973 struct drm_crtc
*crtc
;
5974 struct intel_crtc
*intel_crtc
;
5976 if (!i915_powersave
)
5979 mutex_lock(&dev
->struct_mutex
);
5981 i915_update_gfx_val(dev_priv
);
5983 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
5984 /* Skip inactive CRTCs */
5988 intel_crtc
= to_intel_crtc(crtc
);
5989 if (!intel_crtc
->busy
)
5990 intel_decrease_pllclock(crtc
);
5994 mutex_unlock(&dev
->struct_mutex
);
5998 * intel_mark_busy - mark the GPU and possibly the display busy
6000 * @obj: object we're operating on
6002 * Callers can use this function to indicate that the GPU is busy processing
6003 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6004 * buffer), we'll also mark the display as busy, so we know to increase its
6007 void intel_mark_busy(struct drm_device
*dev
, struct drm_i915_gem_object
*obj
)
6009 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6010 struct drm_crtc
*crtc
= NULL
;
6011 struct intel_framebuffer
*intel_fb
;
6012 struct intel_crtc
*intel_crtc
;
6014 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
6017 if (!dev_priv
->busy
) {
6018 intel_sanitize_pm(dev
);
6019 dev_priv
->busy
= true;
6021 mod_timer(&dev_priv
->idle_timer
, jiffies
+
6022 msecs_to_jiffies(GPU_IDLE_TIMEOUT
));
6027 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
6031 intel_crtc
= to_intel_crtc(crtc
);
6032 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6033 if (intel_fb
->obj
== obj
) {
6034 if (!intel_crtc
->busy
) {
6035 /* Non-busy -> busy, upclock */
6036 intel_increase_pllclock(crtc
);
6037 intel_crtc
->busy
= true;
6039 /* Busy -> busy, put off timer */
6040 mod_timer(&intel_crtc
->idle_timer
, jiffies
+
6041 msecs_to_jiffies(CRTC_IDLE_TIMEOUT
));
6047 static void intel_crtc_destroy(struct drm_crtc
*crtc
)
6049 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6050 struct drm_device
*dev
= crtc
->dev
;
6051 struct intel_unpin_work
*work
;
6052 unsigned long flags
;
6054 spin_lock_irqsave(&dev
->event_lock
, flags
);
6055 work
= intel_crtc
->unpin_work
;
6056 intel_crtc
->unpin_work
= NULL
;
6057 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6060 cancel_work_sync(&work
->work
);
6064 drm_crtc_cleanup(crtc
);
6069 static void intel_unpin_work_fn(struct work_struct
*__work
)
6071 struct intel_unpin_work
*work
=
6072 container_of(__work
, struct intel_unpin_work
, work
);
6074 mutex_lock(&work
->dev
->struct_mutex
);
6075 intel_unpin_fb_obj(work
->old_fb_obj
);
6076 drm_gem_object_unreference(&work
->pending_flip_obj
->base
);
6077 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6079 intel_update_fbc(work
->dev
);
6080 mutex_unlock(&work
->dev
->struct_mutex
);
6084 static void do_intel_finish_page_flip(struct drm_device
*dev
,
6085 struct drm_crtc
*crtc
)
6087 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6088 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6089 struct intel_unpin_work
*work
;
6090 struct drm_i915_gem_object
*obj
;
6091 struct drm_pending_vblank_event
*e
;
6092 struct timeval tnow
, tvbl
;
6093 unsigned long flags
;
6095 /* Ignore early vblank irqs */
6096 if (intel_crtc
== NULL
)
6099 do_gettimeofday(&tnow
);
6101 spin_lock_irqsave(&dev
->event_lock
, flags
);
6102 work
= intel_crtc
->unpin_work
;
6103 if (work
== NULL
|| !work
->pending
) {
6104 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6108 intel_crtc
->unpin_work
= NULL
;
6112 e
->event
.sequence
= drm_vblank_count_and_time(dev
, intel_crtc
->pipe
, &tvbl
);
6114 /* Called before vblank count and timestamps have
6115 * been updated for the vblank interval of flip
6116 * completion? Need to increment vblank count and
6117 * add one videorefresh duration to returned timestamp
6118 * to account for this. We assume this happened if we
6119 * get called over 0.9 frame durations after the last
6120 * timestamped vblank.
6122 * This calculation can not be used with vrefresh rates
6123 * below 5Hz (10Hz to be on the safe side) without
6124 * promoting to 64 integers.
6126 if (10 * (timeval_to_ns(&tnow
) - timeval_to_ns(&tvbl
)) >
6127 9 * crtc
->framedur_ns
) {
6128 e
->event
.sequence
++;
6129 tvbl
= ns_to_timeval(timeval_to_ns(&tvbl
) +
6133 e
->event
.tv_sec
= tvbl
.tv_sec
;
6134 e
->event
.tv_usec
= tvbl
.tv_usec
;
6136 list_add_tail(&e
->base
.link
,
6137 &e
->base
.file_priv
->event_list
);
6138 wake_up_interruptible(&e
->base
.file_priv
->event_wait
);
6141 drm_vblank_put(dev
, intel_crtc
->pipe
);
6143 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6145 obj
= work
->old_fb_obj
;
6147 atomic_clear_mask(1 << intel_crtc
->plane
,
6148 &obj
->pending_flip
.counter
);
6149 if (atomic_read(&obj
->pending_flip
) == 0)
6150 wake_up(&dev_priv
->pending_flip_queue
);
6152 schedule_work(&work
->work
);
6154 trace_i915_flip_complete(intel_crtc
->plane
, work
->pending_flip_obj
);
6157 void intel_finish_page_flip(struct drm_device
*dev
, int pipe
)
6159 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6160 struct drm_crtc
*crtc
= dev_priv
->pipe_to_crtc_mapping
[pipe
];
6162 do_intel_finish_page_flip(dev
, crtc
);
6165 void intel_finish_page_flip_plane(struct drm_device
*dev
, int plane
)
6167 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6168 struct drm_crtc
*crtc
= dev_priv
->plane_to_crtc_mapping
[plane
];
6170 do_intel_finish_page_flip(dev
, crtc
);
6173 void intel_prepare_page_flip(struct drm_device
*dev
, int plane
)
6175 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6176 struct intel_crtc
*intel_crtc
=
6177 to_intel_crtc(dev_priv
->plane_to_crtc_mapping
[plane
]);
6178 unsigned long flags
;
6180 spin_lock_irqsave(&dev
->event_lock
, flags
);
6181 if (intel_crtc
->unpin_work
) {
6182 if ((++intel_crtc
->unpin_work
->pending
) > 1)
6183 DRM_ERROR("Prepared flip multiple times\n");
6185 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6187 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6190 static int intel_gen2_queue_flip(struct drm_device
*dev
,
6191 struct drm_crtc
*crtc
,
6192 struct drm_framebuffer
*fb
,
6193 struct drm_i915_gem_object
*obj
)
6195 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6196 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6197 unsigned long offset
;
6199 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6202 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6206 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6207 offset
= crtc
->y
* fb
->pitches
[0] + crtc
->x
* fb
->bits_per_pixel
/8;
6209 ret
= intel_ring_begin(ring
, 6);
6213 /* Can't queue multiple flips, so wait for the previous
6214 * one to finish before executing the next.
6216 if (intel_crtc
->plane
)
6217 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6219 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6220 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6221 intel_ring_emit(ring
, MI_NOOP
);
6222 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6223 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6224 intel_ring_emit(ring
, fb
->pitches
[0]);
6225 intel_ring_emit(ring
, obj
->gtt_offset
+ offset
);
6226 intel_ring_emit(ring
, 0); /* aux display base address, unused */
6227 intel_ring_advance(ring
);
6231 intel_unpin_fb_obj(obj
);
6236 static int intel_gen3_queue_flip(struct drm_device
*dev
,
6237 struct drm_crtc
*crtc
,
6238 struct drm_framebuffer
*fb
,
6239 struct drm_i915_gem_object
*obj
)
6241 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6242 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6243 unsigned long offset
;
6245 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6248 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6252 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6253 offset
= crtc
->y
* fb
->pitches
[0] + crtc
->x
* fb
->bits_per_pixel
/8;
6255 ret
= intel_ring_begin(ring
, 6);
6259 if (intel_crtc
->plane
)
6260 flip_mask
= MI_WAIT_FOR_PLANE_B_FLIP
;
6262 flip_mask
= MI_WAIT_FOR_PLANE_A_FLIP
;
6263 intel_ring_emit(ring
, MI_WAIT_FOR_EVENT
| flip_mask
);
6264 intel_ring_emit(ring
, MI_NOOP
);
6265 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
|
6266 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6267 intel_ring_emit(ring
, fb
->pitches
[0]);
6268 intel_ring_emit(ring
, obj
->gtt_offset
+ offset
);
6269 intel_ring_emit(ring
, MI_NOOP
);
6271 intel_ring_advance(ring
);
6275 intel_unpin_fb_obj(obj
);
6280 static int intel_gen4_queue_flip(struct drm_device
*dev
,
6281 struct drm_crtc
*crtc
,
6282 struct drm_framebuffer
*fb
,
6283 struct drm_i915_gem_object
*obj
)
6285 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6286 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6287 uint32_t pf
, pipesrc
;
6288 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6291 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6295 ret
= intel_ring_begin(ring
, 4);
6299 /* i965+ uses the linear or tiled offsets from the
6300 * Display Registers (which do not change across a page-flip)
6301 * so we need only reprogram the base address.
6303 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6304 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6305 intel_ring_emit(ring
, fb
->pitches
[0]);
6306 intel_ring_emit(ring
, obj
->gtt_offset
| obj
->tiling_mode
);
6308 /* XXX Enabling the panel-fitter across page-flip is so far
6309 * untested on non-native modes, so ignore it for now.
6310 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6313 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6314 intel_ring_emit(ring
, pf
| pipesrc
);
6315 intel_ring_advance(ring
);
6319 intel_unpin_fb_obj(obj
);
6324 static int intel_gen6_queue_flip(struct drm_device
*dev
,
6325 struct drm_crtc
*crtc
,
6326 struct drm_framebuffer
*fb
,
6327 struct drm_i915_gem_object
*obj
)
6329 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6330 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6331 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[RCS
];
6332 uint32_t pf
, pipesrc
;
6335 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6339 ret
= intel_ring_begin(ring
, 4);
6343 intel_ring_emit(ring
, MI_DISPLAY_FLIP
|
6344 MI_DISPLAY_FLIP_PLANE(intel_crtc
->plane
));
6345 intel_ring_emit(ring
, fb
->pitches
[0] | obj
->tiling_mode
);
6346 intel_ring_emit(ring
, obj
->gtt_offset
);
6348 /* Contrary to the suggestions in the documentation,
6349 * "Enable Panel Fitter" does not seem to be required when page
6350 * flipping with a non-native mode, and worse causes a normal
6352 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6355 pipesrc
= I915_READ(PIPESRC(intel_crtc
->pipe
)) & 0x0fff0fff;
6356 intel_ring_emit(ring
, pf
| pipesrc
);
6357 intel_ring_advance(ring
);
6361 intel_unpin_fb_obj(obj
);
6367 * On gen7 we currently use the blit ring because (in early silicon at least)
6368 * the render ring doesn't give us interrpts for page flip completion, which
6369 * means clients will hang after the first flip is queued. Fortunately the
6370 * blit ring generates interrupts properly, so use it instead.
6372 static int intel_gen7_queue_flip(struct drm_device
*dev
,
6373 struct drm_crtc
*crtc
,
6374 struct drm_framebuffer
*fb
,
6375 struct drm_i915_gem_object
*obj
)
6377 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6378 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6379 struct intel_ring_buffer
*ring
= &dev_priv
->ring
[BCS
];
6380 uint32_t plane_bit
= 0;
6383 ret
= intel_pin_and_fence_fb_obj(dev
, obj
, ring
);
6387 switch(intel_crtc
->plane
) {
6389 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_A
;
6392 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_B
;
6395 plane_bit
= MI_DISPLAY_FLIP_IVB_PLANE_C
;
6398 WARN_ONCE(1, "unknown plane in flip command\n");
6403 ret
= intel_ring_begin(ring
, 4);
6407 intel_ring_emit(ring
, MI_DISPLAY_FLIP_I915
| plane_bit
);
6408 intel_ring_emit(ring
, (fb
->pitches
[0] | obj
->tiling_mode
));
6409 intel_ring_emit(ring
, (obj
->gtt_offset
));
6410 intel_ring_emit(ring
, (MI_NOOP
));
6411 intel_ring_advance(ring
);
6415 intel_unpin_fb_obj(obj
);
6420 static int intel_default_queue_flip(struct drm_device
*dev
,
6421 struct drm_crtc
*crtc
,
6422 struct drm_framebuffer
*fb
,
6423 struct drm_i915_gem_object
*obj
)
6428 static int intel_crtc_page_flip(struct drm_crtc
*crtc
,
6429 struct drm_framebuffer
*fb
,
6430 struct drm_pending_vblank_event
*event
)
6432 struct drm_device
*dev
= crtc
->dev
;
6433 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6434 struct intel_framebuffer
*intel_fb
;
6435 struct drm_i915_gem_object
*obj
;
6436 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6437 struct intel_unpin_work
*work
;
6438 unsigned long flags
;
6441 work
= kzalloc(sizeof *work
, GFP_KERNEL
);
6445 work
->event
= event
;
6446 work
->dev
= crtc
->dev
;
6447 intel_fb
= to_intel_framebuffer(crtc
->fb
);
6448 work
->old_fb_obj
= intel_fb
->obj
;
6449 INIT_WORK(&work
->work
, intel_unpin_work_fn
);
6451 ret
= drm_vblank_get(dev
, intel_crtc
->pipe
);
6455 /* We borrow the event spin lock for protecting unpin_work */
6456 spin_lock_irqsave(&dev
->event_lock
, flags
);
6457 if (intel_crtc
->unpin_work
) {
6458 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6460 drm_vblank_put(dev
, intel_crtc
->pipe
);
6462 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6465 intel_crtc
->unpin_work
= work
;
6466 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6468 intel_fb
= to_intel_framebuffer(fb
);
6469 obj
= intel_fb
->obj
;
6471 mutex_lock(&dev
->struct_mutex
);
6473 /* Reference the objects for the scheduled work. */
6474 drm_gem_object_reference(&work
->old_fb_obj
->base
);
6475 drm_gem_object_reference(&obj
->base
);
6479 work
->pending_flip_obj
= obj
;
6481 work
->enable_stall_check
= true;
6483 /* Block clients from rendering to the new back buffer until
6484 * the flip occurs and the object is no longer visible.
6486 atomic_add(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6488 ret
= dev_priv
->display
.queue_flip(dev
, crtc
, fb
, obj
);
6490 goto cleanup_pending
;
6492 intel_disable_fbc(dev
);
6493 intel_mark_busy(dev
, obj
);
6494 mutex_unlock(&dev
->struct_mutex
);
6496 trace_i915_flip_request(intel_crtc
->plane
, obj
);
6501 atomic_sub(1 << intel_crtc
->plane
, &work
->old_fb_obj
->pending_flip
);
6502 drm_gem_object_unreference(&work
->old_fb_obj
->base
);
6503 drm_gem_object_unreference(&obj
->base
);
6504 mutex_unlock(&dev
->struct_mutex
);
6506 spin_lock_irqsave(&dev
->event_lock
, flags
);
6507 intel_crtc
->unpin_work
= NULL
;
6508 spin_unlock_irqrestore(&dev
->event_lock
, flags
);
6510 drm_vblank_put(dev
, intel_crtc
->pipe
);
6517 static void intel_sanitize_modesetting(struct drm_device
*dev
,
6518 int pipe
, int plane
)
6520 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6524 /* Clear any frame start delays used for debugging left by the BIOS */
6527 I915_WRITE(reg
, I915_READ(reg
) & ~PIPECONF_FRAME_START_DELAY_MASK
);
6530 if (HAS_PCH_SPLIT(dev
))
6533 /* Who knows what state these registers were left in by the BIOS or
6536 * If we leave the registers in a conflicting state (e.g. with the
6537 * display plane reading from the other pipe than the one we intend
6538 * to use) then when we attempt to teardown the active mode, we will
6539 * not disable the pipes and planes in the correct order -- leaving
6540 * a plane reading from a disabled pipe and possibly leading to
6541 * undefined behaviour.
6544 reg
= DSPCNTR(plane
);
6545 val
= I915_READ(reg
);
6547 if ((val
& DISPLAY_PLANE_ENABLE
) == 0)
6549 if (!!(val
& DISPPLANE_SEL_PIPE_MASK
) == pipe
)
6552 /* This display plane is active and attached to the other CPU pipe. */
6555 /* Disable the plane and wait for it to stop reading from the pipe. */
6556 intel_disable_plane(dev_priv
, plane
, pipe
);
6557 intel_disable_pipe(dev_priv
, pipe
);
6560 static void intel_crtc_reset(struct drm_crtc
*crtc
)
6562 struct drm_device
*dev
= crtc
->dev
;
6563 struct intel_crtc
*intel_crtc
= to_intel_crtc(crtc
);
6565 /* Reset flags back to the 'unknown' status so that they
6566 * will be correctly set on the initial modeset.
6568 intel_crtc
->dpms_mode
= -1;
6570 /* We need to fix up any BIOS configuration that conflicts with
6573 intel_sanitize_modesetting(dev
, intel_crtc
->pipe
, intel_crtc
->plane
);
6576 static struct drm_crtc_helper_funcs intel_helper_funcs
= {
6577 .dpms
= intel_crtc_dpms
,
6578 .mode_fixup
= intel_crtc_mode_fixup
,
6579 .mode_set
= intel_crtc_mode_set
,
6580 .mode_set_base
= intel_pipe_set_base
,
6581 .mode_set_base_atomic
= intel_pipe_set_base_atomic
,
6582 .load_lut
= intel_crtc_load_lut
,
6583 .disable
= intel_crtc_disable
,
6586 static const struct drm_crtc_funcs intel_crtc_funcs
= {
6587 .reset
= intel_crtc_reset
,
6588 .cursor_set
= intel_crtc_cursor_set
,
6589 .cursor_move
= intel_crtc_cursor_move
,
6590 .gamma_set
= intel_crtc_gamma_set
,
6591 .set_config
= drm_crtc_helper_set_config
,
6592 .destroy
= intel_crtc_destroy
,
6593 .page_flip
= intel_crtc_page_flip
,
6596 static void intel_pch_pll_init(struct drm_device
*dev
)
6598 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6601 if (dev_priv
->num_pch_pll
== 0) {
6602 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6606 for (i
= 0; i
< dev_priv
->num_pch_pll
; i
++) {
6607 dev_priv
->pch_plls
[i
].pll_reg
= _PCH_DPLL(i
);
6608 dev_priv
->pch_plls
[i
].fp0_reg
= _PCH_FP0(i
);
6609 dev_priv
->pch_plls
[i
].fp1_reg
= _PCH_FP1(i
);
6613 static void intel_crtc_init(struct drm_device
*dev
, int pipe
)
6615 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
6616 struct intel_crtc
*intel_crtc
;
6619 intel_crtc
= kzalloc(sizeof(struct intel_crtc
) + (INTELFB_CONN_LIMIT
* sizeof(struct drm_connector
*)), GFP_KERNEL
);
6620 if (intel_crtc
== NULL
)
6623 drm_crtc_init(dev
, &intel_crtc
->base
, &intel_crtc_funcs
);
6625 drm_mode_crtc_set_gamma_size(&intel_crtc
->base
, 256);
6626 for (i
= 0; i
< 256; i
++) {
6627 intel_crtc
->lut_r
[i
] = i
;
6628 intel_crtc
->lut_g
[i
] = i
;
6629 intel_crtc
->lut_b
[i
] = i
;
6632 /* Swap pipes & planes for FBC on pre-965 */
6633 intel_crtc
->pipe
= pipe
;
6634 intel_crtc
->plane
= pipe
;
6635 if (IS_MOBILE(dev
) && IS_GEN3(dev
)) {
6636 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
6637 intel_crtc
->plane
= !pipe
;
6640 BUG_ON(pipe
>= ARRAY_SIZE(dev_priv
->plane_to_crtc_mapping
) ||
6641 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] != NULL
);
6642 dev_priv
->plane_to_crtc_mapping
[intel_crtc
->plane
] = &intel_crtc
->base
;
6643 dev_priv
->pipe_to_crtc_mapping
[intel_crtc
->pipe
] = &intel_crtc
->base
;
6645 intel_crtc_reset(&intel_crtc
->base
);
6646 intel_crtc
->active
= true; /* force the pipe off on setup_init_config */
6647 intel_crtc
->bpp
= 24; /* default for pre-Ironlake */
6649 if (HAS_PCH_SPLIT(dev
)) {
6650 intel_helper_funcs
.prepare
= ironlake_crtc_prepare
;
6651 intel_helper_funcs
.commit
= ironlake_crtc_commit
;
6653 intel_helper_funcs
.prepare
= i9xx_crtc_prepare
;
6654 intel_helper_funcs
.commit
= i9xx_crtc_commit
;
6657 drm_crtc_helper_add(&intel_crtc
->base
, &intel_helper_funcs
);
6659 intel_crtc
->busy
= false;
6661 setup_timer(&intel_crtc
->idle_timer
, intel_crtc_idle_timer
,
6662 (unsigned long)intel_crtc
);
6665 int intel_get_pipe_from_crtc_id(struct drm_device
*dev
, void *data
,
6666 struct drm_file
*file
)
6668 struct drm_i915_get_pipe_from_crtc_id
*pipe_from_crtc_id
= data
;
6669 struct drm_mode_object
*drmmode_obj
;
6670 struct intel_crtc
*crtc
;
6672 if (!drm_core_check_feature(dev
, DRIVER_MODESET
))
6675 drmmode_obj
= drm_mode_object_find(dev
, pipe_from_crtc_id
->crtc_id
,
6676 DRM_MODE_OBJECT_CRTC
);
6679 DRM_ERROR("no such CRTC id\n");
6683 crtc
= to_intel_crtc(obj_to_crtc(drmmode_obj
));
6684 pipe_from_crtc_id
->pipe
= crtc
->pipe
;
6689 static int intel_encoder_clones(struct drm_device
*dev
, int type_mask
)
6691 struct intel_encoder
*encoder
;
6695 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6696 if (type_mask
& encoder
->clone_mask
)
6697 index_mask
|= (1 << entry
);
6704 static bool has_edp_a(struct drm_device
*dev
)
6706 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6708 if (!IS_MOBILE(dev
))
6711 if ((I915_READ(DP_A
) & DP_DETECTED
) == 0)
6715 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES
) & ILK_eDP_A_DISABLE
))
6721 static void intel_setup_outputs(struct drm_device
*dev
)
6723 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6724 struct intel_encoder
*encoder
;
6725 bool dpd_is_edp
= false;
6728 has_lvds
= intel_lvds_init(dev
);
6729 if (!has_lvds
&& !HAS_PCH_SPLIT(dev
)) {
6730 /* disable the panel fitter on everything but LVDS */
6731 I915_WRITE(PFIT_CONTROL
, 0);
6734 if (HAS_PCH_SPLIT(dev
)) {
6735 dpd_is_edp
= intel_dpd_is_edp(dev
);
6738 intel_dp_init(dev
, DP_A
);
6740 if (dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6741 intel_dp_init(dev
, PCH_DP_D
);
6744 intel_crt_init(dev
);
6746 if (IS_HASWELL(dev
)) {
6749 /* Haswell uses DDI functions to detect digital outputs */
6750 found
= I915_READ(DDI_BUF_CTL_A
) & DDI_INIT_DISPLAY_DETECTED
;
6751 /* DDI A only supports eDP */
6753 intel_ddi_init(dev
, PORT_A
);
6755 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6757 found
= I915_READ(SFUSE_STRAP
);
6759 if (found
& SFUSE_STRAP_DDIB_DETECTED
)
6760 intel_ddi_init(dev
, PORT_B
);
6761 if (found
& SFUSE_STRAP_DDIC_DETECTED
)
6762 intel_ddi_init(dev
, PORT_C
);
6763 if (found
& SFUSE_STRAP_DDID_DETECTED
)
6764 intel_ddi_init(dev
, PORT_D
);
6765 } else if (HAS_PCH_SPLIT(dev
)) {
6768 if (I915_READ(HDMIB
) & PORT_DETECTED
) {
6769 /* PCH SDVOB multiplex with HDMIB */
6770 found
= intel_sdvo_init(dev
, PCH_SDVOB
, true);
6772 intel_hdmi_init(dev
, HDMIB
);
6773 if (!found
&& (I915_READ(PCH_DP_B
) & DP_DETECTED
))
6774 intel_dp_init(dev
, PCH_DP_B
);
6777 if (I915_READ(HDMIC
) & PORT_DETECTED
)
6778 intel_hdmi_init(dev
, HDMIC
);
6780 if (!dpd_is_edp
&& I915_READ(HDMID
) & PORT_DETECTED
)
6781 intel_hdmi_init(dev
, HDMID
);
6783 if (I915_READ(PCH_DP_C
) & DP_DETECTED
)
6784 intel_dp_init(dev
, PCH_DP_C
);
6786 if (!dpd_is_edp
&& (I915_READ(PCH_DP_D
) & DP_DETECTED
))
6787 intel_dp_init(dev
, PCH_DP_D
);
6788 } else if (IS_VALLEYVIEW(dev
)) {
6791 if (I915_READ(SDVOB
) & PORT_DETECTED
) {
6792 /* SDVOB multiplex with HDMIB */
6793 found
= intel_sdvo_init(dev
, SDVOB
, true);
6795 intel_hdmi_init(dev
, SDVOB
);
6796 if (!found
&& (I915_READ(DP_B
) & DP_DETECTED
))
6797 intel_dp_init(dev
, DP_B
);
6800 if (I915_READ(SDVOC
) & PORT_DETECTED
)
6801 intel_hdmi_init(dev
, SDVOC
);
6803 /* Shares lanes with HDMI on SDVOC */
6804 if (I915_READ(DP_C
) & DP_DETECTED
)
6805 intel_dp_init(dev
, DP_C
);
6806 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev
)) {
6809 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6810 DRM_DEBUG_KMS("probing SDVOB\n");
6811 found
= intel_sdvo_init(dev
, SDVOB
, true);
6812 if (!found
&& SUPPORTS_INTEGRATED_HDMI(dev
)) {
6813 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
6814 intel_hdmi_init(dev
, SDVOB
);
6817 if (!found
&& SUPPORTS_INTEGRATED_DP(dev
)) {
6818 DRM_DEBUG_KMS("probing DP_B\n");
6819 intel_dp_init(dev
, DP_B
);
6823 /* Before G4X SDVOC doesn't have its own detect register */
6825 if (I915_READ(SDVOB
) & SDVO_DETECTED
) {
6826 DRM_DEBUG_KMS("probing SDVOC\n");
6827 found
= intel_sdvo_init(dev
, SDVOC
, false);
6830 if (!found
&& (I915_READ(SDVOC
) & SDVO_DETECTED
)) {
6832 if (SUPPORTS_INTEGRATED_HDMI(dev
)) {
6833 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
6834 intel_hdmi_init(dev
, SDVOC
);
6836 if (SUPPORTS_INTEGRATED_DP(dev
)) {
6837 DRM_DEBUG_KMS("probing DP_C\n");
6838 intel_dp_init(dev
, DP_C
);
6842 if (SUPPORTS_INTEGRATED_DP(dev
) &&
6843 (I915_READ(DP_D
) & DP_DETECTED
)) {
6844 DRM_DEBUG_KMS("probing DP_D\n");
6845 intel_dp_init(dev
, DP_D
);
6847 } else if (IS_GEN2(dev
))
6848 intel_dvo_init(dev
);
6850 if (SUPPORTS_TV(dev
))
6853 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, base
.head
) {
6854 encoder
->base
.possible_crtcs
= encoder
->crtc_mask
;
6855 encoder
->base
.possible_clones
=
6856 intel_encoder_clones(dev
, encoder
->clone_mask
);
6859 /* disable all the possible outputs/crtcs before entering KMS mode */
6860 drm_helper_disable_unused_functions(dev
);
6862 if (HAS_PCH_SPLIT(dev
))
6863 ironlake_init_pch_refclk(dev
);
6866 static void intel_user_framebuffer_destroy(struct drm_framebuffer
*fb
)
6868 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6870 drm_framebuffer_cleanup(fb
);
6871 drm_gem_object_unreference_unlocked(&intel_fb
->obj
->base
);
6876 static int intel_user_framebuffer_create_handle(struct drm_framebuffer
*fb
,
6877 struct drm_file
*file
,
6878 unsigned int *handle
)
6880 struct intel_framebuffer
*intel_fb
= to_intel_framebuffer(fb
);
6881 struct drm_i915_gem_object
*obj
= intel_fb
->obj
;
6883 return drm_gem_handle_create(file
, &obj
->base
, handle
);
6886 static const struct drm_framebuffer_funcs intel_fb_funcs
= {
6887 .destroy
= intel_user_framebuffer_destroy
,
6888 .create_handle
= intel_user_framebuffer_create_handle
,
6891 int intel_framebuffer_init(struct drm_device
*dev
,
6892 struct intel_framebuffer
*intel_fb
,
6893 struct drm_mode_fb_cmd2
*mode_cmd
,
6894 struct drm_i915_gem_object
*obj
)
6898 if (obj
->tiling_mode
== I915_TILING_Y
)
6901 if (mode_cmd
->pitches
[0] & 63)
6904 switch (mode_cmd
->pixel_format
) {
6905 case DRM_FORMAT_RGB332
:
6906 case DRM_FORMAT_RGB565
:
6907 case DRM_FORMAT_XRGB8888
:
6908 case DRM_FORMAT_XBGR8888
:
6909 case DRM_FORMAT_ARGB8888
:
6910 case DRM_FORMAT_XRGB2101010
:
6911 case DRM_FORMAT_ARGB2101010
:
6912 /* RGB formats are common across chipsets */
6914 case DRM_FORMAT_YUYV
:
6915 case DRM_FORMAT_UYVY
:
6916 case DRM_FORMAT_YVYU
:
6917 case DRM_FORMAT_VYUY
:
6920 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6921 mode_cmd
->pixel_format
);
6925 ret
= drm_framebuffer_init(dev
, &intel_fb
->base
, &intel_fb_funcs
);
6927 DRM_ERROR("framebuffer init failed %d\n", ret
);
6931 drm_helper_mode_fill_fb_struct(&intel_fb
->base
, mode_cmd
);
6932 intel_fb
->obj
= obj
;
6936 static struct drm_framebuffer
*
6937 intel_user_framebuffer_create(struct drm_device
*dev
,
6938 struct drm_file
*filp
,
6939 struct drm_mode_fb_cmd2
*mode_cmd
)
6941 struct drm_i915_gem_object
*obj
;
6943 obj
= to_intel_bo(drm_gem_object_lookup(dev
, filp
,
6944 mode_cmd
->handles
[0]));
6945 if (&obj
->base
== NULL
)
6946 return ERR_PTR(-ENOENT
);
6948 return intel_framebuffer_create(dev
, mode_cmd
, obj
);
6951 static const struct drm_mode_config_funcs intel_mode_funcs
= {
6952 .fb_create
= intel_user_framebuffer_create
,
6953 .output_poll_changed
= intel_fb_output_poll_changed
,
6956 /* Set up chip specific display functions */
6957 static void intel_init_display(struct drm_device
*dev
)
6959 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
6961 /* We always want a DPMS function */
6962 if (HAS_PCH_SPLIT(dev
)) {
6963 dev_priv
->display
.dpms
= ironlake_crtc_dpms
;
6964 dev_priv
->display
.crtc_mode_set
= ironlake_crtc_mode_set
;
6965 dev_priv
->display
.off
= ironlake_crtc_off
;
6966 dev_priv
->display
.update_plane
= ironlake_update_plane
;
6968 dev_priv
->display
.dpms
= i9xx_crtc_dpms
;
6969 dev_priv
->display
.crtc_mode_set
= i9xx_crtc_mode_set
;
6970 dev_priv
->display
.off
= i9xx_crtc_off
;
6971 dev_priv
->display
.update_plane
= i9xx_update_plane
;
6974 /* Returns the core display clock speed */
6975 if (IS_VALLEYVIEW(dev
))
6976 dev_priv
->display
.get_display_clock_speed
=
6977 valleyview_get_display_clock_speed
;
6978 else if (IS_I945G(dev
) || (IS_G33(dev
) && !IS_PINEVIEW_M(dev
)))
6979 dev_priv
->display
.get_display_clock_speed
=
6980 i945_get_display_clock_speed
;
6981 else if (IS_I915G(dev
))
6982 dev_priv
->display
.get_display_clock_speed
=
6983 i915_get_display_clock_speed
;
6984 else if (IS_I945GM(dev
) || IS_845G(dev
) || IS_PINEVIEW_M(dev
))
6985 dev_priv
->display
.get_display_clock_speed
=
6986 i9xx_misc_get_display_clock_speed
;
6987 else if (IS_I915GM(dev
))
6988 dev_priv
->display
.get_display_clock_speed
=
6989 i915gm_get_display_clock_speed
;
6990 else if (IS_I865G(dev
))
6991 dev_priv
->display
.get_display_clock_speed
=
6992 i865_get_display_clock_speed
;
6993 else if (IS_I85X(dev
))
6994 dev_priv
->display
.get_display_clock_speed
=
6995 i855_get_display_clock_speed
;
6997 dev_priv
->display
.get_display_clock_speed
=
6998 i830_get_display_clock_speed
;
7000 if (HAS_PCH_SPLIT(dev
)) {
7002 dev_priv
->display
.fdi_link_train
= ironlake_fdi_link_train
;
7003 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7004 } else if (IS_GEN6(dev
)) {
7005 dev_priv
->display
.fdi_link_train
= gen6_fdi_link_train
;
7006 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7007 } else if (IS_IVYBRIDGE(dev
)) {
7008 /* FIXME: detect B0+ stepping and use auto training */
7009 dev_priv
->display
.fdi_link_train
= ivb_manual_fdi_link_train
;
7010 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7011 } else if (IS_HASWELL(dev
)) {
7012 dev_priv
->display
.fdi_link_train
= hsw_fdi_link_train
;
7013 dev_priv
->display
.write_eld
= ironlake_write_eld
;
7015 dev_priv
->display
.update_wm
= NULL
;
7016 } else if (IS_VALLEYVIEW(dev
)) {
7017 dev_priv
->display
.force_wake_get
= vlv_force_wake_get
;
7018 dev_priv
->display
.force_wake_put
= vlv_force_wake_put
;
7019 } else if (IS_G4X(dev
)) {
7020 dev_priv
->display
.write_eld
= g4x_write_eld
;
7023 /* Default just returns -ENODEV to indicate unsupported */
7024 dev_priv
->display
.queue_flip
= intel_default_queue_flip
;
7026 switch (INTEL_INFO(dev
)->gen
) {
7028 dev_priv
->display
.queue_flip
= intel_gen2_queue_flip
;
7032 dev_priv
->display
.queue_flip
= intel_gen3_queue_flip
;
7037 dev_priv
->display
.queue_flip
= intel_gen4_queue_flip
;
7041 dev_priv
->display
.queue_flip
= intel_gen6_queue_flip
;
7044 dev_priv
->display
.queue_flip
= intel_gen7_queue_flip
;
7050 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7051 * resume, or other times. This quirk makes sure that's the case for
7054 static void quirk_pipea_force(struct drm_device
*dev
)
7056 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7058 dev_priv
->quirks
|= QUIRK_PIPEA_FORCE
;
7059 DRM_INFO("applying pipe a force quirk\n");
7063 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7065 static void quirk_ssc_force_disable(struct drm_device
*dev
)
7067 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7068 dev_priv
->quirks
|= QUIRK_LVDS_SSC_DISABLE
;
7069 DRM_INFO("applying lvds SSC disable quirk\n");
7073 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7076 static void quirk_invert_brightness(struct drm_device
*dev
)
7078 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7079 dev_priv
->quirks
|= QUIRK_INVERT_BRIGHTNESS
;
7080 DRM_INFO("applying inverted panel brightness quirk\n");
7083 struct intel_quirk
{
7085 int subsystem_vendor
;
7086 int subsystem_device
;
7087 void (*hook
)(struct drm_device
*dev
);
7090 static struct intel_quirk intel_quirks
[] = {
7091 /* HP Mini needs pipe A force quirk (LP: #322104) */
7092 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force
},
7094 /* Thinkpad R31 needs pipe A force quirk */
7095 { 0x3577, 0x1014, 0x0505, quirk_pipea_force
},
7096 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7097 { 0x2592, 0x1179, 0x0001, quirk_pipea_force
},
7099 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7100 { 0x3577, 0x1014, 0x0513, quirk_pipea_force
},
7101 /* ThinkPad X40 needs pipe A force quirk */
7103 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7104 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force
},
7106 /* 855 & before need to leave pipe A & dpll A up */
7107 { 0x3582, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7108 { 0x2562, PCI_ANY_ID
, PCI_ANY_ID
, quirk_pipea_force
},
7110 /* Lenovo U160 cannot use SSC on LVDS */
7111 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable
},
7113 /* Sony Vaio Y cannot use SSC on LVDS */
7114 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable
},
7116 /* Acer Aspire 5734Z must invert backlight brightness */
7117 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness
},
7120 static void intel_init_quirks(struct drm_device
*dev
)
7122 struct pci_dev
*d
= dev
->pdev
;
7125 for (i
= 0; i
< ARRAY_SIZE(intel_quirks
); i
++) {
7126 struct intel_quirk
*q
= &intel_quirks
[i
];
7128 if (d
->device
== q
->device
&&
7129 (d
->subsystem_vendor
== q
->subsystem_vendor
||
7130 q
->subsystem_vendor
== PCI_ANY_ID
) &&
7131 (d
->subsystem_device
== q
->subsystem_device
||
7132 q
->subsystem_device
== PCI_ANY_ID
))
7137 /* Disable the VGA plane that we never use */
7138 static void i915_disable_vga(struct drm_device
*dev
)
7140 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7144 if (HAS_PCH_SPLIT(dev
))
7145 vga_reg
= CPU_VGACNTRL
;
7149 vga_get_uninterruptible(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7150 outb(SR01
, VGA_SR_INDEX
);
7151 sr1
= inb(VGA_SR_DATA
);
7152 outb(sr1
| 1<<5, VGA_SR_DATA
);
7153 vga_put(dev
->pdev
, VGA_RSRC_LEGACY_IO
);
7156 I915_WRITE(vga_reg
, VGA_DISP_DISABLE
);
7157 POSTING_READ(vga_reg
);
7160 static void ivb_pch_pwm_override(struct drm_device
*dev
)
7162 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7165 * IVB has CPU eDP backlight regs too, set things up to let the
7166 * PCH regs control the backlight
7168 I915_WRITE(BLC_PWM_CPU_CTL2
, BLM_PWM_ENABLE
);
7169 I915_WRITE(BLC_PWM_CPU_CTL
, 0);
7170 I915_WRITE(BLC_PWM_PCH_CTL1
, BLM_PCH_PWM_ENABLE
| BLM_PCH_OVERRIDE_ENABLE
);
7173 void intel_modeset_init_hw(struct drm_device
*dev
)
7175 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7177 intel_init_clock_gating(dev
);
7179 if (IS_IRONLAKE_M(dev
)) {
7180 ironlake_enable_drps(dev
);
7181 ironlake_enable_rc6(dev
);
7182 intel_init_emon(dev
);
7185 if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
)) {
7186 gen6_enable_rps(dev_priv
);
7187 gen6_update_ring_freq(dev_priv
);
7190 if (IS_IVYBRIDGE(dev
))
7191 ivb_pch_pwm_override(dev
);
7194 void intel_modeset_init(struct drm_device
*dev
)
7196 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7199 drm_mode_config_init(dev
);
7201 dev
->mode_config
.min_width
= 0;
7202 dev
->mode_config
.min_height
= 0;
7204 dev
->mode_config
.preferred_depth
= 24;
7205 dev
->mode_config
.prefer_shadow
= 1;
7207 dev
->mode_config
.funcs
= &intel_mode_funcs
;
7209 intel_init_quirks(dev
);
7213 intel_prepare_ddi(dev
);
7215 intel_init_display(dev
);
7218 dev
->mode_config
.max_width
= 2048;
7219 dev
->mode_config
.max_height
= 2048;
7220 } else if (IS_GEN3(dev
)) {
7221 dev
->mode_config
.max_width
= 4096;
7222 dev
->mode_config
.max_height
= 4096;
7224 dev
->mode_config
.max_width
= 8192;
7225 dev
->mode_config
.max_height
= 8192;
7227 dev
->mode_config
.fb_base
= dev_priv
->mm
.gtt_base_addr
;
7229 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7230 dev_priv
->num_pipe
, dev_priv
->num_pipe
> 1 ? "s" : "");
7232 for (i
= 0; i
< dev_priv
->num_pipe
; i
++) {
7233 intel_crtc_init(dev
, i
);
7234 ret
= intel_plane_init(dev
, i
);
7236 DRM_DEBUG_KMS("plane %d init failed: %d\n", i
, ret
);
7239 intel_pch_pll_init(dev
);
7241 /* Just disable it once at startup */
7242 i915_disable_vga(dev
);
7243 intel_setup_outputs(dev
);
7245 INIT_WORK(&dev_priv
->idle_work
, intel_idle_update
);
7246 setup_timer(&dev_priv
->idle_timer
, intel_gpu_idle_timer
,
7247 (unsigned long)dev
);
7250 void intel_modeset_gem_init(struct drm_device
*dev
)
7252 intel_modeset_init_hw(dev
);
7254 intel_setup_overlay(dev
);
7257 void intel_modeset_cleanup(struct drm_device
*dev
)
7259 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7260 struct drm_crtc
*crtc
;
7261 struct intel_crtc
*intel_crtc
;
7263 drm_kms_helper_poll_fini(dev
);
7264 mutex_lock(&dev
->struct_mutex
);
7266 intel_unregister_dsm_handler();
7269 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7270 /* Skip inactive CRTCs */
7274 intel_crtc
= to_intel_crtc(crtc
);
7275 intel_increase_pllclock(crtc
);
7278 intel_disable_fbc(dev
);
7280 if (IS_IRONLAKE_M(dev
))
7281 ironlake_disable_drps(dev
);
7282 if ((IS_GEN6(dev
) || IS_GEN7(dev
)) && !IS_VALLEYVIEW(dev
))
7283 gen6_disable_rps(dev
);
7285 if (IS_IRONLAKE_M(dev
))
7286 ironlake_disable_rc6(dev
);
7288 if (IS_VALLEYVIEW(dev
))
7291 mutex_unlock(&dev
->struct_mutex
);
7293 /* Disable the irq before mode object teardown, for the irq might
7294 * enqueue unpin/hotplug work. */
7295 drm_irq_uninstall(dev
);
7296 cancel_work_sync(&dev_priv
->hotplug_work
);
7297 cancel_work_sync(&dev_priv
->rps_work
);
7299 /* flush any delayed tasks or pending work */
7300 flush_scheduled_work();
7302 /* Shut off idle work before the crtcs get freed. */
7303 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
) {
7304 intel_crtc
= to_intel_crtc(crtc
);
7305 del_timer_sync(&intel_crtc
->idle_timer
);
7307 del_timer_sync(&dev_priv
->idle_timer
);
7308 cancel_work_sync(&dev_priv
->idle_work
);
7310 drm_mode_config_cleanup(dev
);
7314 * Return which encoder is currently attached for connector.
7316 struct drm_encoder
*intel_best_encoder(struct drm_connector
*connector
)
7318 return &intel_attached_encoder(connector
)->base
;
7321 void intel_connector_attach_encoder(struct intel_connector
*connector
,
7322 struct intel_encoder
*encoder
)
7324 connector
->encoder
= encoder
;
7325 drm_mode_connector_attach_encoder(&connector
->base
,
7330 * set vga decode state - true == enable VGA decode
7332 int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
)
7334 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
7337 pci_read_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, &gmch_ctrl
);
7339 gmch_ctrl
&= ~INTEL_GMCH_VGA_DISABLE
;
7341 gmch_ctrl
|= INTEL_GMCH_VGA_DISABLE
;
7342 pci_write_config_word(dev_priv
->bridge_dev
, INTEL_GMCH_CTRL
, gmch_ctrl
);
7346 #ifdef CONFIG_DEBUG_FS
7347 #include <linux/seq_file.h>
7349 struct intel_display_error_state
{
7350 struct intel_cursor_error_state
{
7357 struct intel_pipe_error_state
{
7369 struct intel_plane_error_state
{
7380 struct intel_display_error_state
*
7381 intel_display_capture_error_state(struct drm_device
*dev
)
7383 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
7384 struct intel_display_error_state
*error
;
7387 error
= kmalloc(sizeof(*error
), GFP_ATOMIC
);
7391 for (i
= 0; i
< 2; i
++) {
7392 error
->cursor
[i
].control
= I915_READ(CURCNTR(i
));
7393 error
->cursor
[i
].position
= I915_READ(CURPOS(i
));
7394 error
->cursor
[i
].base
= I915_READ(CURBASE(i
));
7396 error
->plane
[i
].control
= I915_READ(DSPCNTR(i
));
7397 error
->plane
[i
].stride
= I915_READ(DSPSTRIDE(i
));
7398 error
->plane
[i
].size
= I915_READ(DSPSIZE(i
));
7399 error
->plane
[i
].pos
= I915_READ(DSPPOS(i
));
7400 error
->plane
[i
].addr
= I915_READ(DSPADDR(i
));
7401 if (INTEL_INFO(dev
)->gen
>= 4) {
7402 error
->plane
[i
].surface
= I915_READ(DSPSURF(i
));
7403 error
->plane
[i
].tile_offset
= I915_READ(DSPTILEOFF(i
));
7406 error
->pipe
[i
].conf
= I915_READ(PIPECONF(i
));
7407 error
->pipe
[i
].source
= I915_READ(PIPESRC(i
));
7408 error
->pipe
[i
].htotal
= I915_READ(HTOTAL(i
));
7409 error
->pipe
[i
].hblank
= I915_READ(HBLANK(i
));
7410 error
->pipe
[i
].hsync
= I915_READ(HSYNC(i
));
7411 error
->pipe
[i
].vtotal
= I915_READ(VTOTAL(i
));
7412 error
->pipe
[i
].vblank
= I915_READ(VBLANK(i
));
7413 error
->pipe
[i
].vsync
= I915_READ(VSYNC(i
));
7420 intel_display_print_error_state(struct seq_file
*m
,
7421 struct drm_device
*dev
,
7422 struct intel_display_error_state
*error
)
7426 for (i
= 0; i
< 2; i
++) {
7427 seq_printf(m
, "Pipe [%d]:\n", i
);
7428 seq_printf(m
, " CONF: %08x\n", error
->pipe
[i
].conf
);
7429 seq_printf(m
, " SRC: %08x\n", error
->pipe
[i
].source
);
7430 seq_printf(m
, " HTOTAL: %08x\n", error
->pipe
[i
].htotal
);
7431 seq_printf(m
, " HBLANK: %08x\n", error
->pipe
[i
].hblank
);
7432 seq_printf(m
, " HSYNC: %08x\n", error
->pipe
[i
].hsync
);
7433 seq_printf(m
, " VTOTAL: %08x\n", error
->pipe
[i
].vtotal
);
7434 seq_printf(m
, " VBLANK: %08x\n", error
->pipe
[i
].vblank
);
7435 seq_printf(m
, " VSYNC: %08x\n", error
->pipe
[i
].vsync
);
7437 seq_printf(m
, "Plane [%d]:\n", i
);
7438 seq_printf(m
, " CNTR: %08x\n", error
->plane
[i
].control
);
7439 seq_printf(m
, " STRIDE: %08x\n", error
->plane
[i
].stride
);
7440 seq_printf(m
, " SIZE: %08x\n", error
->plane
[i
].size
);
7441 seq_printf(m
, " POS: %08x\n", error
->plane
[i
].pos
);
7442 seq_printf(m
, " ADDR: %08x\n", error
->plane
[i
].addr
);
7443 if (INTEL_INFO(dev
)->gen
>= 4) {
7444 seq_printf(m
, " SURF: %08x\n", error
->plane
[i
].surface
);
7445 seq_printf(m
, " TILEOFF: %08x\n", error
->plane
[i
].tile_offset
);
7448 seq_printf(m
, "Cursor [%d]:\n", i
);
7449 seq_printf(m
, " CNTR: %08x\n", error
->cursor
[i
].control
);
7450 seq_printf(m
, " POS: %08x\n", error
->cursor
[i
].position
);
7451 seq_printf(m
, " BASE: %08x\n", error
->cursor
[i
].base
);