arch/arm/mach-s3c2410/s3c2410-clock.c

   1 /* linux/arch/arm/mach-s3c2410/s3c2410-clock.c
   2  *
   3  * Copyright (c) 2006 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410,S3C2440,S3C2442 Clock control support
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  21 */
  22
  23 #include <linux/init.h>
  24 #include <linux/module.h>
  25 #include <linux/kernel.h>
  26 #include <linux/list.h>
  27 #include <linux/errno.h>
  28 #include <linux/err.h>
  29 #include <linux/sysdev.h>
  30 #include <linux/clk.h>
  31 #include <linux/mutex.h>
  32 #include <linux/delay.h>
  33
  34 #include <asm/mach/map.h>
  35
  36 #include <asm/hardware.h>
  37 #include <asm/io.h>
  38
  39 #include <asm/arch/regs-serial.h>
  40 #include <asm/arch/regs-clock.h>
  41 #include <asm/arch/regs-gpio.h>
  42
  43 #include "s3c2410.h"
  44 #include "clock.h"
  45 #include "cpu.h"
  46
  47 int s3c2410_clkcon_enable(struct clk *clk, int enable)
  48 {
  49         unsigned int clocks = clk->ctrlbit;
  50         unsigned long clkcon;
  51
  52         clkcon = __raw_readl(S3C2410_CLKCON);
  53
  54         if (enable)
  55                 clkcon |= clocks;
  56         else
  57                 clkcon &= ~clocks;
  58
  59         /* ensure none of the special function bits set */
  60         clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
  61
  62         __raw_writel(clkcon, S3C2410_CLKCON);
  63
  64         return 0;
  65 }
  66
  67 static int s3c2410_upll_enable(struct clk *clk, int enable)
  68 {
  69         unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
  70         unsigned long orig = clkslow;
  71
  72         if (enable)
  73                 clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
  74         else
  75                 clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
  76
  77         __raw_writel(clkslow, S3C2410_CLKSLOW);
  78
  79         /* if we started the UPLL, then allow to settle */
  80
  81         if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
  82                 udelay(200);
  83
  84         return 0;
  85 }
  86
  87 /* standard clock definitions */
  88
  89 static struct clk init_clocks_disable[] = {
  90         {
  91                 .name           = "nand",
  92                 .id             = -1,
  93                 .parent         = &clk_h,
  94                 .enable         = s3c2410_clkcon_enable,
  95                 .ctrlbit        = S3C2410_CLKCON_NAND,
  96         }, {
  97                 .name           = "sdi",
  98                 .id             = -1,
  99                 .parent         = &clk_p,
 100                 .enable         = s3c2410_clkcon_enable,
 101                 .ctrlbit        = S3C2410_CLKCON_SDI,
 102         }, {
 103                 .name           = "adc",
 104                 .id             = -1,
 105                 .parent         = &clk_p,
 106                 .enable         = s3c2410_clkcon_enable,
 107                 .ctrlbit        = S3C2410_CLKCON_ADC,
 108         }, {
 109                 .name           = "i2c",
 110                 .id             = -1,
 111                 .parent         = &clk_p,
 112                 .enable         = s3c2410_clkcon_enable,
 113                 .ctrlbit        = S3C2410_CLKCON_IIC,
 114         }, {
 115                 .name           = "iis",
 116                 .id             = -1,
 117                 .parent         = &clk_p,
 118                 .enable         = s3c2410_clkcon_enable,
 119                 .ctrlbit        = S3C2410_CLKCON_IIS,
 120         }, {
 121                 .name           = "spi",
 122                 .id             = -1,
 123                 .parent         = &clk_p,
 124                 .enable         = s3c2410_clkcon_enable,
 125                 .ctrlbit        = S3C2410_CLKCON_SPI,
 126         }
 127 };
 128
 129 static struct clk init_clocks[] = {
 130         {
 131                 .name           = "lcd",
 132                 .id             = -1,
 133                 .parent         = &clk_h,
 134                 .enable         = s3c2410_clkcon_enable,
 135                 .ctrlbit        = S3C2410_CLKCON_LCDC,
 136         }, {
 137                 .name           = "gpio",
 138                 .id             = -1,
 139                 .parent         = &clk_p,
 140                 .enable         = s3c2410_clkcon_enable,
 141                 .ctrlbit        = S3C2410_CLKCON_GPIO,
 142         }, {
 143                 .name           = "usb-host",
 144                 .id             = -1,
 145                 .parent         = &clk_h,
 146                 .enable         = s3c2410_clkcon_enable,
 147                 .ctrlbit        = S3C2410_CLKCON_USBH,
 148         }, {
 149                 .name           = "usb-device",
 150                 .id             = -1,
 151                 .parent         = &clk_h,
 152                 .enable         = s3c2410_clkcon_enable,
 153                 .ctrlbit        = S3C2410_CLKCON_USBD,
 154         }, {
 155                 .name           = "timers",
 156                 .id             = -1,
 157                 .parent         = &clk_p,
 158                 .enable         = s3c2410_clkcon_enable,
 159                 .ctrlbit        = S3C2410_CLKCON_PWMT,
 160         }, {
 161                 .name           = "uart",
 162                 .id             = 0,
 163                 .parent         = &clk_p,
 164                 .enable         = s3c2410_clkcon_enable,
 165                 .ctrlbit        = S3C2410_CLKCON_UART0,
 166         }, {
 167                 .name           = "uart",
 168                 .id             = 1,
 169                 .parent         = &clk_p,
 170                 .enable         = s3c2410_clkcon_enable,
 171                 .ctrlbit        = S3C2410_CLKCON_UART1,
 172         }, {
 173                 .name           = "uart",
 174                 .id             = 2,
 175                 .parent         = &clk_p,
 176                 .enable         = s3c2410_clkcon_enable,
 177                 .ctrlbit        = S3C2410_CLKCON_UART2,
 178         }, {
 179                 .name           = "rtc",
 180                 .id             = -1,
 181                 .parent         = &clk_p,
 182                 .enable         = s3c2410_clkcon_enable,
 183                 .ctrlbit        = S3C2410_CLKCON_RTC,
 184         }, {
 185                 .name           = "watchdog",
 186                 .id             = -1,
 187                 .parent         = &clk_p,
 188                 .ctrlbit        = 0,
 189         }, {
 190                 .name           = "usb-bus-host",
 191                 .id             = -1,
 192                 .parent         = &clk_usb_bus,
 193         }, {
 194                 .name           = "usb-bus-gadget",
 195                 .id             = -1,
 196                 .parent         = &clk_usb_bus,
 197         },
 198 };
 199
 200 /* s3c2410_baseclk_add()
 201  *
 202  * Add all the clocks used by the s3c2410 or compatible CPUs
 203  * such as the S3C2440 and S3C2442.
 204  *
 205  * We cannot use a system device as we are needed before any
 206  * of the init-calls that initialise the devices are actually
 207  * done.
 208 */
 209
 210 int __init s3c2410_baseclk_add(void)
 211 {
 212         unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
 213         unsigned long clkcon  = __raw_readl(S3C2410_CLKCON);
 214         struct clk *clkp;
 215         struct clk *xtal;
 216         int ret;
 217         int ptr;
 218
 219         clk_upll.enable = s3c2410_upll_enable;
 220
 221         if (s3c24xx_register_clock(&clk_usb_bus) < 0)
 222                 printk(KERN_ERR "failed to register usb bus clock\n");
 223
 224         /* register clocks from clock array */
 225
 226         clkp = init_clocks;
 227         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++, clkp++) {
 228                 /* ensure that we note the clock state */
 229
 230                 clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
 231
 232                 ret = s3c24xx_register_clock(clkp);
 233                 if (ret < 0) {
 234                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 235                                clkp->name, ret);
 236                 }
 237         }
 238
 239         /* We must be careful disabling the clocks we are not intending to
 240          * be using at boot time, as subsytems such as the LCD which do
 241          * their own DMA requests to the bus can cause the system to lockup
 242          * if they where in the middle of requesting bus access.
 243          *
 244          * Disabling the LCD clock if the LCD is active is very dangerous,
 245          * and therefore the bootloader should be careful to not enable
 246          * the LCD clock if it is not needed.
 247         */
 248
 249         /* install (and disable) the clocks we do not need immediately */
 250
 251         clkp = init_clocks_disable;
 252         for (ptr = 0; ptr < ARRAY_SIZE(init_clocks_disable); ptr++, clkp++) {
 253
 254                 ret = s3c24xx_register_clock(clkp);
 255                 if (ret < 0) {
 256                         printk(KERN_ERR "Failed to register clock %s (%d)\n",
 257                                clkp->name, ret);
 258                 }
 259
 260                 s3c2410_clkcon_enable(clkp, 0);
 261         }
 262
 263         /* show the clock-slow value */
 264
 265         xtal = clk_get(NULL, "xtal");
 266
 267         printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
 268                print_mhz(clk_get_rate(xtal) /
 269                          ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
 270                (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
 271                (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
 272                (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
 273
 274         return 0;
 275 }