2 * Performance events x86 architecture code
4 * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
5 * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
6 * Copyright (C) 2009 Jaswinder Singh Rajput
7 * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
8 * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
9 * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
10 * Copyright (C) 2009 Google, Inc., Stephane Eranian
12 * For licencing details see kernel-base/COPYING
15 #include <linux/perf_event.h>
16 #include <linux/capability.h>
17 #include <linux/notifier.h>
18 #include <linux/hardirq.h>
19 #include <linux/kprobes.h>
20 #include <linux/module.h>
21 #include <linux/kdebug.h>
22 #include <linux/sched.h>
23 #include <linux/uaccess.h>
24 #include <linux/slab.h>
25 #include <linux/highmem.h>
26 #include <linux/cpu.h>
27 #include <linux/bitops.h>
30 #include <asm/stacktrace.h>
32 #include <asm/compat.h>
36 #define wrmsrl(msr, val) \
38 trace_printk("wrmsrl(%lx, %lx)\n", (unsigned long)(msr),\
39 (unsigned long)(val)); \
40 native_write_msr((msr), (u32)((u64)(val)), \
41 (u32)((u64)(val) >> 32)); \
46 * best effort, GUP based copy_from_user() that assumes IRQ or NMI context
49 copy_from_user_nmi(void *to
, const void __user
*from
, unsigned long n
)
51 unsigned long offset
, addr
= (unsigned long)from
;
52 unsigned long size
, len
= 0;
58 ret
= __get_user_pages_fast(addr
, 1, 0, &page
);
62 offset
= addr
& (PAGE_SIZE
- 1);
63 size
= min(PAGE_SIZE
- offset
, n
- len
);
65 map
= kmap_atomic(page
);
66 memcpy(to
, map
+offset
, size
);
79 struct event_constraint
{
81 unsigned long idxmsk
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
90 int nb_id
; /* NorthBridge id */
91 int refcnt
; /* reference count */
92 struct perf_event
*owners
[X86_PMC_IDX_MAX
];
93 struct event_constraint event_constraints
[X86_PMC_IDX_MAX
];
96 #define MAX_LBR_ENTRIES 16
98 struct cpu_hw_events
{
100 * Generic x86 PMC bits
102 struct perf_event
*events
[X86_PMC_IDX_MAX
]; /* in counter order */
103 unsigned long active_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
104 unsigned long running
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
110 int assign
[X86_PMC_IDX_MAX
]; /* event to counter assignment */
111 u64 tags
[X86_PMC_IDX_MAX
];
112 struct perf_event
*event_list
[X86_PMC_IDX_MAX
]; /* in enabled order */
114 unsigned int group_flag
;
117 * Intel DebugStore bits
119 struct debug_store
*ds
;
127 struct perf_branch_stack lbr_stack
;
128 struct perf_branch_entry lbr_entries
[MAX_LBR_ENTRIES
];
133 struct amd_nb
*amd_nb
;
136 #define __EVENT_CONSTRAINT(c, n, m, w) {\
137 { .idxmsk64 = (n) }, \
143 #define EVENT_CONSTRAINT(c, n, m) \
144 __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n))
147 * Constraint on the Event code.
149 #define INTEL_EVENT_CONSTRAINT(c, n) \
150 EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
153 * Constraint on the Event code + UMask + fixed-mask
155 * filter mask to validate fixed counter events.
156 * the following filters disqualify for fixed counters:
160 * The other filters are supported by fixed counters.
161 * The any-thread option is supported starting with v3.
163 #define FIXED_EVENT_CONSTRAINT(c, n) \
164 EVENT_CONSTRAINT(c, (1ULL << (32+n)), X86_RAW_EVENT_MASK)
167 * Constraint on the Event code + UMask
169 #define PEBS_EVENT_CONSTRAINT(c, n) \
170 EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
172 #define EVENT_CONSTRAINT_END \
173 EVENT_CONSTRAINT(0, 0, 0)
175 #define for_each_event_constraint(e, c) \
176 for ((e) = (c); (e)->weight; (e)++)
178 union perf_capabilities
{
182 u64 pebs_arch_reg
: 1;
190 * struct x86_pmu - generic x86 pmu
194 * Generic x86 PMC bits
198 int (*handle_irq
)(struct pt_regs
*);
199 void (*disable_all
)(void);
200 void (*enable_all
)(int added
);
201 void (*enable
)(struct perf_event
*);
202 void (*disable
)(struct perf_event
*);
203 int (*hw_config
)(struct perf_event
*event
);
204 int (*schedule_events
)(struct cpu_hw_events
*cpuc
, int n
, int *assign
);
207 u64 (*event_map
)(int);
210 int num_counters_fixed
;
215 struct event_constraint
*
216 (*get_event_constraints
)(struct cpu_hw_events
*cpuc
,
217 struct perf_event
*event
);
219 void (*put_event_constraints
)(struct cpu_hw_events
*cpuc
,
220 struct perf_event
*event
);
221 struct event_constraint
*event_constraints
;
222 void (*quirks
)(void);
223 int perfctr_second_write
;
225 int (*cpu_prepare
)(int cpu
);
226 void (*cpu_starting
)(int cpu
);
227 void (*cpu_dying
)(int cpu
);
228 void (*cpu_dead
)(int cpu
);
231 * Intel Arch Perfmon v2+
234 union perf_capabilities intel_cap
;
237 * Intel DebugStore bits
240 int pebs_record_size
;
241 void (*drain_pebs
)(struct pt_regs
*regs
);
242 struct event_constraint
*pebs_constraints
;
247 unsigned long lbr_tos
, lbr_from
, lbr_to
; /* MSR base regs */
248 int lbr_nr
; /* hardware stack size */
251 static struct x86_pmu x86_pmu __read_mostly
;
253 static DEFINE_PER_CPU(struct cpu_hw_events
, cpu_hw_events
) = {
257 static int x86_perf_event_set_period(struct perf_event
*event
);
260 * Generalized hw caching related hw_event table, filled
261 * in on a per model basis. A value of 0 means
262 * 'not supported', -1 means 'hw_event makes no sense on
263 * this CPU', any other value means the raw hw_event
267 #define C(x) PERF_COUNT_HW_CACHE_##x
269 static u64 __read_mostly hw_cache_event_ids
270 [PERF_COUNT_HW_CACHE_MAX
]
271 [PERF_COUNT_HW_CACHE_OP_MAX
]
272 [PERF_COUNT_HW_CACHE_RESULT_MAX
];
275 * Propagate event elapsed time into the generic event.
276 * Can only be executed on the CPU where the event is active.
277 * Returns the delta events processed.
280 x86_perf_event_update(struct perf_event
*event
)
282 struct hw_perf_event
*hwc
= &event
->hw
;
283 int shift
= 64 - x86_pmu
.cntval_bits
;
284 u64 prev_raw_count
, new_raw_count
;
288 if (idx
== X86_PMC_IDX_FIXED_BTS
)
292 * Careful: an NMI might modify the previous event value.
294 * Our tactic to handle this is to first atomically read and
295 * exchange a new raw count - then add that new-prev delta
296 * count to the generic event atomically:
299 prev_raw_count
= local64_read(&hwc
->prev_count
);
300 rdmsrl(hwc
->event_base
+ idx
, new_raw_count
);
302 if (local64_cmpxchg(&hwc
->prev_count
, prev_raw_count
,
303 new_raw_count
) != prev_raw_count
)
307 * Now we have the new raw value and have updated the prev
308 * timestamp already. We can now calculate the elapsed delta
309 * (event-)time and add that to the generic event.
311 * Careful, not all hw sign-extends above the physical width
314 delta
= (new_raw_count
<< shift
) - (prev_raw_count
<< shift
);
317 local64_add(delta
, &event
->count
);
318 local64_sub(delta
, &hwc
->period_left
);
320 return new_raw_count
;
323 static atomic_t active_events
;
324 static DEFINE_MUTEX(pmc_reserve_mutex
);
326 #ifdef CONFIG_X86_LOCAL_APIC
328 static bool reserve_pmc_hardware(void)
332 if (nmi_watchdog
== NMI_LOCAL_APIC
)
333 disable_lapic_nmi_watchdog();
335 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
336 if (!reserve_perfctr_nmi(x86_pmu
.perfctr
+ i
))
340 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
341 if (!reserve_evntsel_nmi(x86_pmu
.eventsel
+ i
))
348 for (i
--; i
>= 0; i
--)
349 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
351 i
= x86_pmu
.num_counters
;
354 for (i
--; i
>= 0; i
--)
355 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
357 if (nmi_watchdog
== NMI_LOCAL_APIC
)
358 enable_lapic_nmi_watchdog();
363 static void release_pmc_hardware(void)
367 for (i
= 0; i
< x86_pmu
.num_counters
; i
++) {
368 release_perfctr_nmi(x86_pmu
.perfctr
+ i
);
369 release_evntsel_nmi(x86_pmu
.eventsel
+ i
);
372 if (nmi_watchdog
== NMI_LOCAL_APIC
)
373 enable_lapic_nmi_watchdog();
378 static bool reserve_pmc_hardware(void) { return true; }
379 static void release_pmc_hardware(void) {}
383 static int reserve_ds_buffers(void);
384 static void release_ds_buffers(void);
386 static void hw_perf_event_destroy(struct perf_event
*event
)
388 if (atomic_dec_and_mutex_lock(&active_events
, &pmc_reserve_mutex
)) {
389 release_pmc_hardware();
390 release_ds_buffers();
391 mutex_unlock(&pmc_reserve_mutex
);
395 static inline int x86_pmu_initialized(void)
397 return x86_pmu
.handle_irq
!= NULL
;
401 set_ext_hw_attr(struct hw_perf_event
*hwc
, struct perf_event_attr
*attr
)
403 unsigned int cache_type
, cache_op
, cache_result
;
406 config
= attr
->config
;
408 cache_type
= (config
>> 0) & 0xff;
409 if (cache_type
>= PERF_COUNT_HW_CACHE_MAX
)
412 cache_op
= (config
>> 8) & 0xff;
413 if (cache_op
>= PERF_COUNT_HW_CACHE_OP_MAX
)
416 cache_result
= (config
>> 16) & 0xff;
417 if (cache_result
>= PERF_COUNT_HW_CACHE_RESULT_MAX
)
420 val
= hw_cache_event_ids
[cache_type
][cache_op
][cache_result
];
433 static int x86_setup_perfctr(struct perf_event
*event
)
435 struct perf_event_attr
*attr
= &event
->attr
;
436 struct hw_perf_event
*hwc
= &event
->hw
;
439 if (!hwc
->sample_period
) {
440 hwc
->sample_period
= x86_pmu
.max_period
;
441 hwc
->last_period
= hwc
->sample_period
;
442 local64_set(&hwc
->period_left
, hwc
->sample_period
);
445 * If we have a PMU initialized but no APIC
446 * interrupts, we cannot sample hardware
447 * events (user-space has to fall back and
448 * sample via a hrtimer based software event):
454 if (attr
->type
== PERF_TYPE_RAW
)
457 if (attr
->type
== PERF_TYPE_HW_CACHE
)
458 return set_ext_hw_attr(hwc
, attr
);
460 if (attr
->config
>= x86_pmu
.max_events
)
466 config
= x86_pmu
.event_map(attr
->config
);
477 if ((attr
->config
== PERF_COUNT_HW_BRANCH_INSTRUCTIONS
) &&
478 (hwc
->sample_period
== 1)) {
479 /* BTS is not supported by this architecture. */
483 /* BTS is currently only allowed for user-mode. */
484 if (!attr
->exclude_kernel
)
488 hwc
->config
|= config
;
493 static int x86_pmu_hw_config(struct perf_event
*event
)
495 if (event
->attr
.precise_ip
) {
498 /* Support for constant skid */
502 /* Support for IP fixup */
506 if (event
->attr
.precise_ip
> precise
)
512 * (keep 'enabled' bit clear for now)
514 event
->hw
.config
= ARCH_PERFMON_EVENTSEL_INT
;
517 * Count user and OS events unless requested not to
519 if (!event
->attr
.exclude_user
)
520 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_USR
;
521 if (!event
->attr
.exclude_kernel
)
522 event
->hw
.config
|= ARCH_PERFMON_EVENTSEL_OS
;
524 if (event
->attr
.type
== PERF_TYPE_RAW
)
525 event
->hw
.config
|= event
->attr
.config
& X86_RAW_EVENT_MASK
;
527 return x86_setup_perfctr(event
);
531 * Setup the hardware configuration for a given attr_type
533 static int __x86_pmu_event_init(struct perf_event
*event
)
537 if (!x86_pmu_initialized())
541 if (!atomic_inc_not_zero(&active_events
)) {
542 mutex_lock(&pmc_reserve_mutex
);
543 if (atomic_read(&active_events
) == 0) {
544 if (!reserve_pmc_hardware())
547 err
= reserve_ds_buffers();
549 release_pmc_hardware();
553 atomic_inc(&active_events
);
554 mutex_unlock(&pmc_reserve_mutex
);
559 event
->destroy
= hw_perf_event_destroy
;
562 event
->hw
.last_cpu
= -1;
563 event
->hw
.last_tag
= ~0ULL;
565 return x86_pmu
.hw_config(event
);
568 static void x86_pmu_disable_all(void)
570 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
573 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
576 if (!test_bit(idx
, cpuc
->active_mask
))
578 rdmsrl(x86_pmu
.eventsel
+ idx
, val
);
579 if (!(val
& ARCH_PERFMON_EVENTSEL_ENABLE
))
581 val
&= ~ARCH_PERFMON_EVENTSEL_ENABLE
;
582 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
586 static void x86_pmu_disable(struct pmu
*pmu
)
588 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
590 if (!x86_pmu_initialized())
600 x86_pmu
.disable_all();
603 static void x86_pmu_enable_all(int added
)
605 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
608 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
609 struct perf_event
*event
= cpuc
->events
[idx
];
612 if (!test_bit(idx
, cpuc
->active_mask
))
615 val
= event
->hw
.config
;
616 val
|= ARCH_PERFMON_EVENTSEL_ENABLE
;
617 wrmsrl(x86_pmu
.eventsel
+ idx
, val
);
621 static struct pmu pmu
;
623 static inline int is_x86_event(struct perf_event
*event
)
625 return event
->pmu
== &pmu
;
628 static int x86_schedule_events(struct cpu_hw_events
*cpuc
, int n
, int *assign
)
630 struct event_constraint
*c
, *constraints
[X86_PMC_IDX_MAX
];
631 unsigned long used_mask
[BITS_TO_LONGS(X86_PMC_IDX_MAX
)];
632 int i
, j
, w
, wmax
, num
= 0;
633 struct hw_perf_event
*hwc
;
635 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
637 for (i
= 0; i
< n
; i
++) {
638 c
= x86_pmu
.get_event_constraints(cpuc
, cpuc
->event_list
[i
]);
643 * fastpath, try to reuse previous register
645 for (i
= 0; i
< n
; i
++) {
646 hwc
= &cpuc
->event_list
[i
]->hw
;
653 /* constraint still honored */
654 if (!test_bit(hwc
->idx
, c
->idxmsk
))
657 /* not already used */
658 if (test_bit(hwc
->idx
, used_mask
))
661 __set_bit(hwc
->idx
, used_mask
);
663 assign
[i
] = hwc
->idx
;
672 bitmap_zero(used_mask
, X86_PMC_IDX_MAX
);
675 * weight = number of possible counters
677 * 1 = most constrained, only works on one counter
678 * wmax = least constrained, works on any counter
680 * assign events to counters starting with most
681 * constrained events.
683 wmax
= x86_pmu
.num_counters
;
686 * when fixed event counters are present,
687 * wmax is incremented by 1 to account
688 * for one more choice
690 if (x86_pmu
.num_counters_fixed
)
693 for (w
= 1, num
= n
; num
&& w
<= wmax
; w
++) {
695 for (i
= 0; num
&& i
< n
; i
++) {
697 hwc
= &cpuc
->event_list
[i
]->hw
;
702 for_each_set_bit(j
, c
->idxmsk
, X86_PMC_IDX_MAX
) {
703 if (!test_bit(j
, used_mask
))
707 if (j
== X86_PMC_IDX_MAX
)
710 __set_bit(j
, used_mask
);
719 * scheduling failed or is just a simulation,
720 * free resources if necessary
722 if (!assign
|| num
) {
723 for (i
= 0; i
< n
; i
++) {
724 if (x86_pmu
.put_event_constraints
)
725 x86_pmu
.put_event_constraints(cpuc
, cpuc
->event_list
[i
]);
728 return num
? -ENOSPC
: 0;
732 * dogrp: true if must collect siblings events (group)
733 * returns total number of events and error code
735 static int collect_events(struct cpu_hw_events
*cpuc
, struct perf_event
*leader
, bool dogrp
)
737 struct perf_event
*event
;
740 max_count
= x86_pmu
.num_counters
+ x86_pmu
.num_counters_fixed
;
742 /* current number of events already accepted */
745 if (is_x86_event(leader
)) {
748 cpuc
->event_list
[n
] = leader
;
754 list_for_each_entry(event
, &leader
->sibling_list
, group_entry
) {
755 if (!is_x86_event(event
) ||
756 event
->state
<= PERF_EVENT_STATE_OFF
)
762 cpuc
->event_list
[n
] = event
;
768 static inline void x86_assign_hw_event(struct perf_event
*event
,
769 struct cpu_hw_events
*cpuc
, int i
)
771 struct hw_perf_event
*hwc
= &event
->hw
;
773 hwc
->idx
= cpuc
->assign
[i
];
774 hwc
->last_cpu
= smp_processor_id();
775 hwc
->last_tag
= ++cpuc
->tags
[i
];
777 if (hwc
->idx
== X86_PMC_IDX_FIXED_BTS
) {
778 hwc
->config_base
= 0;
780 } else if (hwc
->idx
>= X86_PMC_IDX_FIXED
) {
781 hwc
->config_base
= MSR_ARCH_PERFMON_FIXED_CTR_CTRL
;
783 * We set it so that event_base + idx in wrmsr/rdmsr maps to
784 * MSR_ARCH_PERFMON_FIXED_CTR0 ... CTR2:
787 MSR_ARCH_PERFMON_FIXED_CTR0
- X86_PMC_IDX_FIXED
;
789 hwc
->config_base
= x86_pmu
.eventsel
;
790 hwc
->event_base
= x86_pmu
.perfctr
;
794 static inline int match_prev_assignment(struct hw_perf_event
*hwc
,
795 struct cpu_hw_events
*cpuc
,
798 return hwc
->idx
== cpuc
->assign
[i
] &&
799 hwc
->last_cpu
== smp_processor_id() &&
800 hwc
->last_tag
== cpuc
->tags
[i
];
803 static void x86_pmu_start(struct perf_event
*event
, int flags
);
804 static void x86_pmu_stop(struct perf_event
*event
, int flags
);
806 static void x86_pmu_enable(struct pmu
*pmu
)
808 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
809 struct perf_event
*event
;
810 struct hw_perf_event
*hwc
;
811 int i
, added
= cpuc
->n_added
;
813 if (!x86_pmu_initialized())
820 int n_running
= cpuc
->n_events
- cpuc
->n_added
;
822 * apply assignment obtained either from
823 * hw_perf_group_sched_in() or x86_pmu_enable()
825 * step1: save events moving to new counters
826 * step2: reprogram moved events into new counters
828 for (i
= 0; i
< n_running
; i
++) {
829 event
= cpuc
->event_list
[i
];
833 * we can avoid reprogramming counter if:
834 * - assigned same counter as last time
835 * - running on same CPU as last time
836 * - no other event has used the counter since
838 if (hwc
->idx
== -1 ||
839 match_prev_assignment(hwc
, cpuc
, i
))
843 * Ensure we don't accidentally enable a stopped
844 * counter simply because we rescheduled.
846 if (hwc
->state
& PERF_HES_STOPPED
)
847 hwc
->state
|= PERF_HES_ARCH
;
849 x86_pmu_stop(event
, PERF_EF_UPDATE
);
852 for (i
= 0; i
< cpuc
->n_events
; i
++) {
853 event
= cpuc
->event_list
[i
];
856 if (!match_prev_assignment(hwc
, cpuc
, i
))
857 x86_assign_hw_event(event
, cpuc
, i
);
858 else if (i
< n_running
)
861 if (hwc
->state
& PERF_HES_ARCH
)
864 x86_pmu_start(event
, PERF_EF_RELOAD
);
867 perf_events_lapic_init();
873 x86_pmu
.enable_all(added
);
876 static inline void __x86_pmu_enable_event(struct hw_perf_event
*hwc
,
879 wrmsrl(hwc
->config_base
+ hwc
->idx
, hwc
->config
| enable_mask
);
882 static inline void x86_pmu_disable_event(struct perf_event
*event
)
884 struct hw_perf_event
*hwc
= &event
->hw
;
886 wrmsrl(hwc
->config_base
+ hwc
->idx
, hwc
->config
);
889 static DEFINE_PER_CPU(u64
[X86_PMC_IDX_MAX
], pmc_prev_left
);
892 * Set the next IRQ period, based on the hwc->period_left value.
893 * To be called with the event disabled in hw:
896 x86_perf_event_set_period(struct perf_event
*event
)
898 struct hw_perf_event
*hwc
= &event
->hw
;
899 s64 left
= local64_read(&hwc
->period_left
);
900 s64 period
= hwc
->sample_period
;
901 int ret
= 0, idx
= hwc
->idx
;
903 if (idx
== X86_PMC_IDX_FIXED_BTS
)
907 * If we are way outside a reasonable range then just skip forward:
909 if (unlikely(left
<= -period
)) {
911 local64_set(&hwc
->period_left
, left
);
912 hwc
->last_period
= period
;
916 if (unlikely(left
<= 0)) {
918 local64_set(&hwc
->period_left
, left
);
919 hwc
->last_period
= period
;
923 * Quirk: certain CPUs dont like it if just 1 hw_event is left:
925 if (unlikely(left
< 2))
928 if (left
> x86_pmu
.max_period
)
929 left
= x86_pmu
.max_period
;
931 per_cpu(pmc_prev_left
[idx
], smp_processor_id()) = left
;
934 * The hw event starts counting from this event offset,
935 * mark it to be able to extra future deltas:
937 local64_set(&hwc
->prev_count
, (u64
)-left
);
939 wrmsrl(hwc
->event_base
+ idx
, (u64
)(-left
) & x86_pmu
.cntval_mask
);
942 * Due to erratum on certan cpu we need
943 * a second write to be sure the register
944 * is updated properly
946 if (x86_pmu
.perfctr_second_write
) {
947 wrmsrl(hwc
->event_base
+ idx
,
948 (u64
)(-left
) & x86_pmu
.cntval_mask
);
951 perf_event_update_userpage(event
);
956 static void x86_pmu_enable_event(struct perf_event
*event
)
958 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
960 __x86_pmu_enable_event(&event
->hw
,
961 ARCH_PERFMON_EVENTSEL_ENABLE
);
965 * Add a single event to the PMU.
967 * The event is added to the group of enabled events
968 * but only if it can be scehduled with existing events.
970 static int x86_pmu_add(struct perf_event
*event
, int flags
)
972 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
973 struct hw_perf_event
*hwc
;
974 int assign
[X86_PMC_IDX_MAX
];
979 perf_pmu_disable(event
->pmu
);
981 ret
= n
= collect_events(cpuc
, event
, false);
985 hwc
->state
= PERF_HES_UPTODATE
| PERF_HES_STOPPED
;
986 if (!(flags
& PERF_EF_START
))
987 hwc
->state
|= PERF_HES_ARCH
;
990 * If group events scheduling transaction was started,
991 * skip the schedulability test here, it will be peformed
992 * at commit time (->commit_txn) as a whole
994 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
997 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1001 * copy new assignment, now we know it is possible
1002 * will be used by hw_perf_enable()
1004 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1008 cpuc
->n_added
+= n
- n0
;
1009 cpuc
->n_txn
+= n
- n0
;
1013 perf_pmu_enable(event
->pmu
);
1017 static void x86_pmu_start(struct perf_event
*event
, int flags
)
1019 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1020 int idx
= event
->hw
.idx
;
1022 if (WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_STOPPED
)))
1025 if (WARN_ON_ONCE(idx
== -1))
1028 if (flags
& PERF_EF_RELOAD
) {
1029 WARN_ON_ONCE(!(event
->hw
.state
& PERF_HES_UPTODATE
));
1030 x86_perf_event_set_period(event
);
1033 event
->hw
.state
= 0;
1035 cpuc
->events
[idx
] = event
;
1036 __set_bit(idx
, cpuc
->active_mask
);
1037 __set_bit(idx
, cpuc
->running
);
1038 x86_pmu
.enable(event
);
1039 perf_event_update_userpage(event
);
1042 void perf_event_print_debug(void)
1044 u64 ctrl
, status
, overflow
, pmc_ctrl
, pmc_count
, prev_left
, fixed
;
1046 struct cpu_hw_events
*cpuc
;
1047 unsigned long flags
;
1050 if (!x86_pmu
.num_counters
)
1053 local_irq_save(flags
);
1055 cpu
= smp_processor_id();
1056 cpuc
= &per_cpu(cpu_hw_events
, cpu
);
1058 if (x86_pmu
.version
>= 2) {
1059 rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL
, ctrl
);
1060 rdmsrl(MSR_CORE_PERF_GLOBAL_STATUS
, status
);
1061 rdmsrl(MSR_CORE_PERF_GLOBAL_OVF_CTRL
, overflow
);
1062 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR_CTRL
, fixed
);
1063 rdmsrl(MSR_IA32_PEBS_ENABLE
, pebs
);
1066 pr_info("CPU#%d: ctrl: %016llx\n", cpu
, ctrl
);
1067 pr_info("CPU#%d: status: %016llx\n", cpu
, status
);
1068 pr_info("CPU#%d: overflow: %016llx\n", cpu
, overflow
);
1069 pr_info("CPU#%d: fixed: %016llx\n", cpu
, fixed
);
1070 pr_info("CPU#%d: pebs: %016llx\n", cpu
, pebs
);
1072 pr_info("CPU#%d: active: %016llx\n", cpu
, *(u64
*)cpuc
->active_mask
);
1074 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1075 rdmsrl(x86_pmu
.eventsel
+ idx
, pmc_ctrl
);
1076 rdmsrl(x86_pmu
.perfctr
+ idx
, pmc_count
);
1078 prev_left
= per_cpu(pmc_prev_left
[idx
], cpu
);
1080 pr_info("CPU#%d: gen-PMC%d ctrl: %016llx\n",
1081 cpu
, idx
, pmc_ctrl
);
1082 pr_info("CPU#%d: gen-PMC%d count: %016llx\n",
1083 cpu
, idx
, pmc_count
);
1084 pr_info("CPU#%d: gen-PMC%d left: %016llx\n",
1085 cpu
, idx
, prev_left
);
1087 for (idx
= 0; idx
< x86_pmu
.num_counters_fixed
; idx
++) {
1088 rdmsrl(MSR_ARCH_PERFMON_FIXED_CTR0
+ idx
, pmc_count
);
1090 pr_info("CPU#%d: fixed-PMC%d count: %016llx\n",
1091 cpu
, idx
, pmc_count
);
1093 local_irq_restore(flags
);
1096 static void x86_pmu_stop(struct perf_event
*event
, int flags
)
1098 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1099 struct hw_perf_event
*hwc
= &event
->hw
;
1101 if (__test_and_clear_bit(hwc
->idx
, cpuc
->active_mask
)) {
1102 x86_pmu
.disable(event
);
1103 cpuc
->events
[hwc
->idx
] = NULL
;
1104 WARN_ON_ONCE(hwc
->state
& PERF_HES_STOPPED
);
1105 hwc
->state
|= PERF_HES_STOPPED
;
1108 if ((flags
& PERF_EF_UPDATE
) && !(hwc
->state
& PERF_HES_UPTODATE
)) {
1110 * Drain the remaining delta count out of a event
1111 * that we are disabling:
1113 x86_perf_event_update(event
);
1114 hwc
->state
|= PERF_HES_UPTODATE
;
1118 static void x86_pmu_del(struct perf_event
*event
, int flags
)
1120 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1124 * If we're called during a txn, we don't need to do anything.
1125 * The events never got scheduled and ->cancel_txn will truncate
1128 if (cpuc
->group_flag
& PERF_EVENT_TXN
)
1131 x86_pmu_stop(event
, PERF_EF_UPDATE
);
1133 for (i
= 0; i
< cpuc
->n_events
; i
++) {
1134 if (event
== cpuc
->event_list
[i
]) {
1136 if (x86_pmu
.put_event_constraints
)
1137 x86_pmu
.put_event_constraints(cpuc
, event
);
1139 while (++i
< cpuc
->n_events
)
1140 cpuc
->event_list
[i
-1] = cpuc
->event_list
[i
];
1146 perf_event_update_userpage(event
);
1149 static int x86_pmu_handle_irq(struct pt_regs
*regs
)
1151 struct perf_sample_data data
;
1152 struct cpu_hw_events
*cpuc
;
1153 struct perf_event
*event
;
1154 int idx
, handled
= 0;
1157 perf_sample_data_init(&data
, 0);
1159 cpuc
= &__get_cpu_var(cpu_hw_events
);
1161 for (idx
= 0; idx
< x86_pmu
.num_counters
; idx
++) {
1162 if (!test_bit(idx
, cpuc
->active_mask
)) {
1164 * Though we deactivated the counter some cpus
1165 * might still deliver spurious interrupts still
1166 * in flight. Catch them:
1168 if (__test_and_clear_bit(idx
, cpuc
->running
))
1173 event
= cpuc
->events
[idx
];
1175 val
= x86_perf_event_update(event
);
1176 if (val
& (1ULL << (x86_pmu
.cntval_bits
- 1)))
1183 data
.period
= event
->hw
.last_period
;
1185 if (!x86_perf_event_set_period(event
))
1188 if (perf_event_overflow(event
, 1, &data
, regs
))
1189 x86_pmu_stop(event
, 0);
1193 inc_irq_stat(apic_perf_irqs
);
1198 void perf_events_lapic_init(void)
1200 if (!x86_pmu
.apic
|| !x86_pmu_initialized())
1204 * Always use NMI for PMU
1206 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1209 struct pmu_nmi_state
{
1210 unsigned int marked
;
1214 static DEFINE_PER_CPU(struct pmu_nmi_state
, pmu_nmi
);
1216 static int __kprobes
1217 perf_event_nmi_handler(struct notifier_block
*self
,
1218 unsigned long cmd
, void *__args
)
1220 struct die_args
*args
= __args
;
1221 unsigned int this_nmi
;
1224 if (!atomic_read(&active_events
))
1231 case DIE_NMIUNKNOWN
:
1232 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1233 if (this_nmi
!= __get_cpu_var(pmu_nmi
).marked
)
1234 /* let the kernel handle the unknown nmi */
1237 * This one is a PMU back-to-back nmi. Two events
1238 * trigger 'simultaneously' raising two back-to-back
1239 * NMIs. If the first NMI handles both, the latter
1240 * will be empty and daze the CPU. So, we drop it to
1241 * avoid false-positive 'unknown nmi' messages.
1248 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
1250 handled
= x86_pmu
.handle_irq(args
->regs
);
1254 this_nmi
= percpu_read(irq_stat
.__nmi_count
);
1255 if ((handled
> 1) ||
1256 /* the next nmi could be a back-to-back nmi */
1257 ((__get_cpu_var(pmu_nmi
).marked
== this_nmi
) &&
1258 (__get_cpu_var(pmu_nmi
).handled
> 1))) {
1260 * We could have two subsequent back-to-back nmis: The
1261 * first handles more than one counter, the 2nd
1262 * handles only one counter and the 3rd handles no
1265 * This is the 2nd nmi because the previous was
1266 * handling more than one counter. We will mark the
1267 * next (3rd) and then drop it if unhandled.
1269 __get_cpu_var(pmu_nmi
).marked
= this_nmi
+ 1;
1270 __get_cpu_var(pmu_nmi
).handled
= handled
;
1276 static __read_mostly
struct notifier_block perf_event_nmi_notifier
= {
1277 .notifier_call
= perf_event_nmi_handler
,
1282 static struct event_constraint unconstrained
;
1283 static struct event_constraint emptyconstraint
;
1285 static struct event_constraint
*
1286 x86_get_event_constraints(struct cpu_hw_events
*cpuc
, struct perf_event
*event
)
1288 struct event_constraint
*c
;
1290 if (x86_pmu
.event_constraints
) {
1291 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1292 if ((event
->hw
.config
& c
->cmask
) == c
->code
)
1297 return &unconstrained
;
1300 #include "perf_event_amd.c"
1301 #include "perf_event_p6.c"
1302 #include "perf_event_p4.c"
1303 #include "perf_event_intel_lbr.c"
1304 #include "perf_event_intel_ds.c"
1305 #include "perf_event_intel.c"
1307 static int __cpuinit
1308 x86_pmu_notifier(struct notifier_block
*self
, unsigned long action
, void *hcpu
)
1310 unsigned int cpu
= (long)hcpu
;
1311 int ret
= NOTIFY_OK
;
1313 switch (action
& ~CPU_TASKS_FROZEN
) {
1314 case CPU_UP_PREPARE
:
1315 if (x86_pmu
.cpu_prepare
)
1316 ret
= x86_pmu
.cpu_prepare(cpu
);
1320 if (x86_pmu
.cpu_starting
)
1321 x86_pmu
.cpu_starting(cpu
);
1325 if (x86_pmu
.cpu_dying
)
1326 x86_pmu
.cpu_dying(cpu
);
1329 case CPU_UP_CANCELED
:
1331 if (x86_pmu
.cpu_dead
)
1332 x86_pmu
.cpu_dead(cpu
);
1342 static void __init
pmu_check_apic(void)
1348 pr_info("no APIC, boot with the \"lapic\" boot parameter to force-enable it.\n");
1349 pr_info("no hardware sampling interrupt available.\n");
1352 void __init
init_hw_perf_events(void)
1354 struct event_constraint
*c
;
1357 pr_info("Performance Events: ");
1359 switch (boot_cpu_data
.x86_vendor
) {
1360 case X86_VENDOR_INTEL
:
1361 err
= intel_pmu_init();
1363 case X86_VENDOR_AMD
:
1364 err
= amd_pmu_init();
1370 pr_cont("no PMU driver, software events only.\n");
1376 pr_cont("%s PMU driver.\n", x86_pmu
.name
);
1381 if (x86_pmu
.num_counters
> X86_PMC_MAX_GENERIC
) {
1382 WARN(1, KERN_ERR
"hw perf events %d > max(%d), clipping!",
1383 x86_pmu
.num_counters
, X86_PMC_MAX_GENERIC
);
1384 x86_pmu
.num_counters
= X86_PMC_MAX_GENERIC
;
1386 x86_pmu
.intel_ctrl
= (1 << x86_pmu
.num_counters
) - 1;
1388 if (x86_pmu
.num_counters_fixed
> X86_PMC_MAX_FIXED
) {
1389 WARN(1, KERN_ERR
"hw perf events fixed %d > max(%d), clipping!",
1390 x86_pmu
.num_counters_fixed
, X86_PMC_MAX_FIXED
);
1391 x86_pmu
.num_counters_fixed
= X86_PMC_MAX_FIXED
;
1394 x86_pmu
.intel_ctrl
|=
1395 ((1LL << x86_pmu
.num_counters_fixed
)-1) << X86_PMC_IDX_FIXED
;
1397 perf_events_lapic_init();
1398 register_die_notifier(&perf_event_nmi_notifier
);
1400 unconstrained
= (struct event_constraint
)
1401 __EVENT_CONSTRAINT(0, (1ULL << x86_pmu
.num_counters
) - 1,
1402 0, x86_pmu
.num_counters
);
1404 if (x86_pmu
.event_constraints
) {
1405 for_each_event_constraint(c
, x86_pmu
.event_constraints
) {
1406 if (c
->cmask
!= X86_RAW_EVENT_MASK
)
1409 c
->idxmsk64
|= (1ULL << x86_pmu
.num_counters
) - 1;
1410 c
->weight
+= x86_pmu
.num_counters
;
1414 pr_info("... version: %d\n", x86_pmu
.version
);
1415 pr_info("... bit width: %d\n", x86_pmu
.cntval_bits
);
1416 pr_info("... generic registers: %d\n", x86_pmu
.num_counters
);
1417 pr_info("... value mask: %016Lx\n", x86_pmu
.cntval_mask
);
1418 pr_info("... max period: %016Lx\n", x86_pmu
.max_period
);
1419 pr_info("... fixed-purpose events: %d\n", x86_pmu
.num_counters_fixed
);
1420 pr_info("... event mask: %016Lx\n", x86_pmu
.intel_ctrl
);
1422 perf_pmu_register(&pmu
);
1423 perf_cpu_notifier(x86_pmu_notifier
);
1426 static inline void x86_pmu_read(struct perf_event
*event
)
1428 x86_perf_event_update(event
);
1432 * Start group events scheduling transaction
1433 * Set the flag to make pmu::enable() not perform the
1434 * schedulability test, it will be performed at commit time
1436 static void x86_pmu_start_txn(struct pmu
*pmu
)
1438 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1440 perf_pmu_disable(pmu
);
1441 cpuc
->group_flag
|= PERF_EVENT_TXN
;
1446 * Stop group events scheduling transaction
1447 * Clear the flag and pmu::enable() will perform the
1448 * schedulability test.
1450 static void x86_pmu_cancel_txn(struct pmu
*pmu
)
1452 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1454 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1456 * Truncate the collected events.
1458 cpuc
->n_added
-= cpuc
->n_txn
;
1459 cpuc
->n_events
-= cpuc
->n_txn
;
1460 perf_pmu_enable(pmu
);
1464 * Commit group events scheduling transaction
1465 * Perform the group schedulability test as a whole
1466 * Return 0 if success
1468 static int x86_pmu_commit_txn(struct pmu
*pmu
)
1470 struct cpu_hw_events
*cpuc
= &__get_cpu_var(cpu_hw_events
);
1471 int assign
[X86_PMC_IDX_MAX
];
1476 if (!x86_pmu_initialized())
1479 ret
= x86_pmu
.schedule_events(cpuc
, n
, assign
);
1484 * copy new assignment, now we know it is possible
1485 * will be used by hw_perf_enable()
1487 memcpy(cpuc
->assign
, assign
, n
*sizeof(int));
1489 cpuc
->group_flag
&= ~PERF_EVENT_TXN
;
1490 perf_pmu_enable(pmu
);
1495 * validate that we can schedule this event
1497 static int validate_event(struct perf_event
*event
)
1499 struct cpu_hw_events
*fake_cpuc
;
1500 struct event_constraint
*c
;
1503 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1507 c
= x86_pmu
.get_event_constraints(fake_cpuc
, event
);
1509 if (!c
|| !c
->weight
)
1512 if (x86_pmu
.put_event_constraints
)
1513 x86_pmu
.put_event_constraints(fake_cpuc
, event
);
1521 * validate a single event group
1523 * validation include:
1524 * - check events are compatible which each other
1525 * - events do not compete for the same counter
1526 * - number of events <= number of counters
1528 * validation ensures the group can be loaded onto the
1529 * PMU if it was the only group available.
1531 static int validate_group(struct perf_event
*event
)
1533 struct perf_event
*leader
= event
->group_leader
;
1534 struct cpu_hw_events
*fake_cpuc
;
1538 fake_cpuc
= kmalloc(sizeof(*fake_cpuc
), GFP_KERNEL
| __GFP_ZERO
);
1543 * the event is not yet connected with its
1544 * siblings therefore we must first collect
1545 * existing siblings, then add the new event
1546 * before we can simulate the scheduling
1549 n
= collect_events(fake_cpuc
, leader
, true);
1553 fake_cpuc
->n_events
= n
;
1554 n
= collect_events(fake_cpuc
, event
, false);
1558 fake_cpuc
->n_events
= n
;
1560 ret
= x86_pmu
.schedule_events(fake_cpuc
, n
, NULL
);
1568 int x86_pmu_event_init(struct perf_event
*event
)
1573 switch (event
->attr
.type
) {
1575 case PERF_TYPE_HARDWARE
:
1576 case PERF_TYPE_HW_CACHE
:
1583 err
= __x86_pmu_event_init(event
);
1586 * we temporarily connect event to its pmu
1587 * such that validate_group() can classify
1588 * it as an x86 event using is_x86_event()
1593 if (event
->group_leader
!= event
)
1594 err
= validate_group(event
);
1596 err
= validate_event(event
);
1602 event
->destroy(event
);
1608 static struct pmu pmu
= {
1609 .pmu_enable
= x86_pmu_enable
,
1610 .pmu_disable
= x86_pmu_disable
,
1612 .event_init
= x86_pmu_event_init
,
1616 .start
= x86_pmu_start
,
1617 .stop
= x86_pmu_stop
,
1618 .read
= x86_pmu_read
,
1620 .start_txn
= x86_pmu_start_txn
,
1621 .cancel_txn
= x86_pmu_cancel_txn
,
1622 .commit_txn
= x86_pmu_commit_txn
,
1630 backtrace_warning_symbol(void *data
, char *msg
, unsigned long symbol
)
1632 /* Ignore warnings */
1635 static void backtrace_warning(void *data
, char *msg
)
1637 /* Ignore warnings */
1640 static int backtrace_stack(void *data
, char *name
)
1645 static void backtrace_address(void *data
, unsigned long addr
, int reliable
)
1647 struct perf_callchain_entry
*entry
= data
;
1649 perf_callchain_store(entry
, addr
);
1652 static const struct stacktrace_ops backtrace_ops
= {
1653 .warning
= backtrace_warning
,
1654 .warning_symbol
= backtrace_warning_symbol
,
1655 .stack
= backtrace_stack
,
1656 .address
= backtrace_address
,
1657 .walk_stack
= print_context_stack_bp
,
1661 perf_callchain_kernel(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1663 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1664 /* TODO: We don't support guest os callchain now */
1668 perf_callchain_store(entry
, regs
->ip
);
1670 dump_trace(NULL
, regs
, NULL
, regs
->bp
, &backtrace_ops
, entry
);
1673 #ifdef CONFIG_COMPAT
1675 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1677 /* 32-bit process in 64-bit kernel. */
1678 struct stack_frame_ia32 frame
;
1679 const void __user
*fp
;
1681 if (!test_thread_flag(TIF_IA32
))
1684 fp
= compat_ptr(regs
->bp
);
1685 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1686 unsigned long bytes
;
1687 frame
.next_frame
= 0;
1688 frame
.return_address
= 0;
1690 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1691 if (bytes
!= sizeof(frame
))
1694 if (fp
< compat_ptr(regs
->sp
))
1697 perf_callchain_store(entry
, frame
.return_address
);
1698 fp
= compat_ptr(frame
.next_frame
);
1704 perf_callchain_user32(struct pt_regs
*regs
, struct perf_callchain_entry
*entry
)
1711 perf_callchain_user(struct perf_callchain_entry
*entry
, struct pt_regs
*regs
)
1713 struct stack_frame frame
;
1714 const void __user
*fp
;
1716 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1717 /* TODO: We don't support guest os callchain now */
1721 fp
= (void __user
*)regs
->bp
;
1723 perf_callchain_store(entry
, regs
->ip
);
1725 if (perf_callchain_user32(regs
, entry
))
1728 while (entry
->nr
< PERF_MAX_STACK_DEPTH
) {
1729 unsigned long bytes
;
1730 frame
.next_frame
= NULL
;
1731 frame
.return_address
= 0;
1733 bytes
= copy_from_user_nmi(&frame
, fp
, sizeof(frame
));
1734 if (bytes
!= sizeof(frame
))
1737 if ((unsigned long)fp
< regs
->sp
)
1740 perf_callchain_store(entry
, frame
.return_address
);
1741 fp
= frame
.next_frame
;
1745 unsigned long perf_instruction_pointer(struct pt_regs
*regs
)
1749 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest())
1750 ip
= perf_guest_cbs
->get_guest_ip();
1752 ip
= instruction_pointer(regs
);
1757 unsigned long perf_misc_flags(struct pt_regs
*regs
)
1761 if (perf_guest_cbs
&& perf_guest_cbs
->is_in_guest()) {
1762 if (perf_guest_cbs
->is_user_mode())
1763 misc
|= PERF_RECORD_MISC_GUEST_USER
;
1765 misc
|= PERF_RECORD_MISC_GUEST_KERNEL
;
1767 if (user_mode(regs
))
1768 misc
|= PERF_RECORD_MISC_USER
;
1770 misc
|= PERF_RECORD_MISC_KERNEL
;
1773 if (regs
->flags
& PERF_EFLAGS_EXACT
)
1774 misc
|= PERF_RECORD_MISC_EXACT_IP
;