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drm/nouveau/instmem: namespace + nvidia gpu names (no binary change)
[linux-2.6/btrfs-unstable.git] / drivers / gpu / drm / nouveau / nouveau_bo.c
blob902d93fd72cc3864b1a38b0e289373a20f57a6de
1 /*
2 * Copyright 2007 Dave Airlied
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 */
24 /*
25 * Authors: Dave Airlied <airlied@linux.ie>
26 * Ben Skeggs <darktama@iinet.net.au>
27 * Jeremy Kolb <jkolb@brandeis.edu>
28 */
29
30 #include <linux/dma-mapping.h>
31 #include <linux/swiotlb.h>
32
33 #include "nouveau_drm.h"
34 #include "nouveau_dma.h"
35 #include "nouveau_fence.h"
36
37 #include "nouveau_bo.h"
38 #include "nouveau_ttm.h"
39 #include "nouveau_gem.h"
40
41 /*
42 * NV10-NV40 tiling helpers
43 */
44
45 static void
46 nv10_bo_update_tile_region(struct drm_device *dev, struct nouveau_drm_tile *reg,
47 u32 addr, u32 size, u32 pitch, u32 flags)
48 {
49 struct nouveau_drm *drm = nouveau_drm(dev);
50 int i = reg - drm->tile.reg;
51 struct nouveau_fb *pfb = nvxx_fb(&drm->device);
52 struct nouveau_fb_tile *tile = &pfb->tile.region[i];
53 struct nouveau_engine *engine;
54
55 nouveau_fence_unref(&reg->fence);
56
57 if (tile->pitch)
58 pfb->tile.fini(pfb, i, tile);
59
60 if (pitch)
61 pfb->tile.init(pfb, i, addr, size, pitch, flags, tile);
62
63 pfb->tile.prog(pfb, i, tile);
64
65 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_GR)))
66 engine->tile_prog(engine, i);
67 if ((engine = nouveau_engine(pfb, NVDEV_ENGINE_MPEG)))
68 engine->tile_prog(engine, i);
69 }
70
71 static struct nouveau_drm_tile *
72 nv10_bo_get_tile_region(struct drm_device *dev, int i)
73 {
74 struct nouveau_drm *drm = nouveau_drm(dev);
75 struct nouveau_drm_tile *tile = &drm->tile.reg[i];
76
77 spin_lock(&drm->tile.lock);
78
79 if (!tile->used &&
80 (!tile->fence || nouveau_fence_done(tile->fence)))
81 tile->used = true;
82 else
83 tile = NULL;
84
85 spin_unlock(&drm->tile.lock);
86 return tile;
87 }
88
89 static void
90 nv10_bo_put_tile_region(struct drm_device *dev, struct nouveau_drm_tile *tile,
91 struct fence *fence)
92 {
93 struct nouveau_drm *drm = nouveau_drm(dev);
94
95 if (tile) {
96 spin_lock(&drm->tile.lock);
97 tile->fence = (struct nouveau_fence *)fence_get(fence);
98 tile->used = false;
99 spin_unlock(&drm->tile.lock);
100 }
101 }
102
103 static struct nouveau_drm_tile *
104 nv10_bo_set_tiling(struct drm_device *dev, u32 addr,
105 u32 size, u32 pitch, u32 flags)
106 {
107 struct nouveau_drm *drm = nouveau_drm(dev);
108 struct nouveau_fb *pfb = nvxx_fb(&drm->device);
109 struct nouveau_drm_tile *tile, *found = NULL;
110 int i;
111
112 for (i = 0; i < pfb->tile.regions; i++) {
113 tile = nv10_bo_get_tile_region(dev, i);
114
115 if (pitch && !found) {
116 found = tile;
117 continue;
118
119 } else if (tile && pfb->tile.region[i].pitch) {
120 /* Kill an unused tile region. */
121 nv10_bo_update_tile_region(dev, tile, 0, 0, 0, 0);
122 }
123
124 nv10_bo_put_tile_region(dev, tile, NULL);
125 }
126
127 if (found)
128 nv10_bo_update_tile_region(dev, found, addr, size,
129 pitch, flags);
130 return found;
131 }
132
133 static void
134 nouveau_bo_del_ttm(struct ttm_buffer_object *bo)
135 {
136 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
137 struct drm_device *dev = drm->dev;
138 struct nouveau_bo *nvbo = nouveau_bo(bo);
139
140 if (unlikely(nvbo->gem.filp))
141 DRM_ERROR("bo %p still attached to GEM object\n", bo);
142 WARN_ON(nvbo->pin_refcnt > 0);
143 nv10_bo_put_tile_region(dev, nvbo->tile, NULL);
144 kfree(nvbo);
145 }
146
147 static void
148 nouveau_bo_fixup_align(struct nouveau_bo *nvbo, u32 flags,
149 int *align, int *size)
150 {
151 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
152 struct nvif_device *device = &drm->device;
153
154 if (device->info.family < NV_DEVICE_INFO_V0_TESLA) {
155 if (nvbo->tile_mode) {
156 if (device->info.chipset >= 0x40) {
157 *align = 65536;
158 *size = roundup(*size, 64 * nvbo->tile_mode);
159
160 } else if (device->info.chipset >= 0x30) {
161 *align = 32768;
162 *size = roundup(*size, 64 * nvbo->tile_mode);
163
164 } else if (device->info.chipset >= 0x20) {
165 *align = 16384;
166 *size = roundup(*size, 64 * nvbo->tile_mode);
167
168 } else if (device->info.chipset >= 0x10) {
169 *align = 16384;
170 *size = roundup(*size, 32 * nvbo->tile_mode);
171 }
172 }
173 } else {
174 *size = roundup(*size, (1 << nvbo->page_shift));
175 *align = max((1 << nvbo->page_shift), *align);
176 }
177
178 *size = roundup(*size, PAGE_SIZE);
179 }
180
181 int
182 nouveau_bo_new(struct drm_device *dev, int size, int align,
183 uint32_t flags, uint32_t tile_mode, uint32_t tile_flags,
184 struct sg_table *sg, struct reservation_object *robj,
185 struct nouveau_bo **pnvbo)
186 {
187 struct nouveau_drm *drm = nouveau_drm(dev);
188 struct nouveau_bo *nvbo;
189 size_t acc_size;
190 int ret;
191 int type = ttm_bo_type_device;
192 int lpg_shift = 12;
193 int max_size;
194
195 if (drm->client.vm)
196 lpg_shift = drm->client.vm->mmu->lpg_shift;
197 max_size = INT_MAX & ~((1 << lpg_shift) - 1);
198
199 if (size <= 0 || size > max_size) {
200 NV_WARN(drm, "skipped size %x\n", (u32)size);
201 return -EINVAL;
202 }
203
204 if (sg)
205 type = ttm_bo_type_sg;
206
207 nvbo = kzalloc(sizeof(struct nouveau_bo), GFP_KERNEL);
208 if (!nvbo)
209 return -ENOMEM;
210 INIT_LIST_HEAD(&nvbo->head);
211 INIT_LIST_HEAD(&nvbo->entry);
212 INIT_LIST_HEAD(&nvbo->vma_list);
213 nvbo->tile_mode = tile_mode;
214 nvbo->tile_flags = tile_flags;
215 nvbo->bo.bdev = &drm->ttm.bdev;
216
217 if (!nv_device_is_cpu_coherent(nvxx_device(&drm->device)))
218 nvbo->force_coherent = flags & TTM_PL_FLAG_UNCACHED;
219
220 nvbo->page_shift = 12;
221 if (drm->client.vm) {
222 if (!(flags & TTM_PL_FLAG_TT) && size > 256 * 1024)
223 nvbo->page_shift = drm->client.vm->mmu->lpg_shift;
224 }
225
226 nouveau_bo_fixup_align(nvbo, flags, &align, &size);
227 nvbo->bo.mem.num_pages = size >> PAGE_SHIFT;
228 nouveau_bo_placement_set(nvbo, flags, 0);
229
230 acc_size = ttm_bo_dma_acc_size(&drm->ttm.bdev, size,
231 sizeof(struct nouveau_bo));
232
233 ret = ttm_bo_init(&drm->ttm.bdev, &nvbo->bo, size,
234 type, &nvbo->placement,
235 align >> PAGE_SHIFT, false, NULL, acc_size, sg,
236 robj, nouveau_bo_del_ttm);
237 if (ret) {
238 /* ttm will call nouveau_bo_del_ttm if it fails.. */
239 return ret;
240 }
241
242 *pnvbo = nvbo;
243 return 0;
244 }
245
246 static void
247 set_placement_list(struct ttm_place *pl, unsigned *n, uint32_t type, uint32_t flags)
248 {
249 *n = 0;
250
251 if (type & TTM_PL_FLAG_VRAM)
252 pl[(*n)++].flags = TTM_PL_FLAG_VRAM | flags;
253 if (type & TTM_PL_FLAG_TT)
254 pl[(*n)++].flags = TTM_PL_FLAG_TT | flags;
255 if (type & TTM_PL_FLAG_SYSTEM)
256 pl[(*n)++].flags = TTM_PL_FLAG_SYSTEM | flags;
257 }
258
259 static void
260 set_placement_range(struct nouveau_bo *nvbo, uint32_t type)
261 {
262 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
263 u32 vram_pages = drm->device.info.ram_size >> PAGE_SHIFT;
264 unsigned i, fpfn, lpfn;
265
266 if (drm->device.info.family == NV_DEVICE_INFO_V0_CELSIUS &&
267 nvbo->tile_mode && (type & TTM_PL_FLAG_VRAM) &&
268 nvbo->bo.mem.num_pages < vram_pages / 4) {
269 /*
270 * Make sure that the color and depth buffers are handled
271 * by independent memory controller units. Up to a 9x
272 * speed up when alpha-blending and depth-test are enabled
273 * at the same time.
274 */
275 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_ZETA) {
276 fpfn = vram_pages / 2;
277 lpfn = ~0;
278 } else {
279 fpfn = 0;
280 lpfn = vram_pages / 2;
281 }
282 for (i = 0; i < nvbo->placement.num_placement; ++i) {
283 nvbo->placements[i].fpfn = fpfn;
284 nvbo->placements[i].lpfn = lpfn;
285 }
286 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
287 nvbo->busy_placements[i].fpfn = fpfn;
288 nvbo->busy_placements[i].lpfn = lpfn;
289 }
290 }
291 }
292
293 void
294 nouveau_bo_placement_set(struct nouveau_bo *nvbo, uint32_t type, uint32_t busy)
295 {
296 struct ttm_placement *pl = &nvbo->placement;
297 uint32_t flags = (nvbo->force_coherent ? TTM_PL_FLAG_UNCACHED :
298 TTM_PL_MASK_CACHING) |
299 (nvbo->pin_refcnt ? TTM_PL_FLAG_NO_EVICT : 0);
300
301 pl->placement = nvbo->placements;
302 set_placement_list(nvbo->placements, &pl->num_placement,
303 type, flags);
304
305 pl->busy_placement = nvbo->busy_placements;
306 set_placement_list(nvbo->busy_placements, &pl->num_busy_placement,
307 type | busy, flags);
308
309 set_placement_range(nvbo, type);
310 }
311
312 int
313 nouveau_bo_pin(struct nouveau_bo *nvbo, uint32_t memtype, bool contig)
314 {
315 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
316 struct ttm_buffer_object *bo = &nvbo->bo;
317 bool force = false, evict = false;
318 int ret;
319
320 ret = ttm_bo_reserve(bo, false, false, false, NULL);
321 if (ret)
322 return ret;
323
324 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA &&
325 memtype == TTM_PL_FLAG_VRAM && contig) {
326 if (nvbo->tile_flags & NOUVEAU_GEM_TILE_NONCONTIG) {
327 if (bo->mem.mem_type == TTM_PL_VRAM) {
328 struct nouveau_mem *mem = bo->mem.mm_node;
329 if (!list_is_singular(&mem->regions))
330 evict = true;
331 }
332 nvbo->tile_flags &= ~NOUVEAU_GEM_TILE_NONCONTIG;
333 force = true;
334 }
335 }
336
337 if (nvbo->pin_refcnt) {
338 if (!(memtype & (1 << bo->mem.mem_type)) || evict) {
339 NV_ERROR(drm, "bo %p pinned elsewhere: "
340 "0x%08x vs 0x%08x\n", bo,
341 1 << bo->mem.mem_type, memtype);
342 ret = -EBUSY;
343 }
344 nvbo->pin_refcnt++;
345 goto out;
346 }
347
348 if (evict) {
349 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT, 0);
350 ret = nouveau_bo_validate(nvbo, false, false);
351 if (ret)
352 goto out;
353 }
354
355 nvbo->pin_refcnt++;
356 nouveau_bo_placement_set(nvbo, memtype, 0);
357
358 /* drop pin_refcnt temporarily, so we don't trip the assertion
359 * in nouveau_bo_move() that makes sure we're not trying to
360 * move a pinned buffer
361 */
362 nvbo->pin_refcnt--;
363 ret = nouveau_bo_validate(nvbo, false, false);
364 if (ret)
365 goto out;
366 nvbo->pin_refcnt++;
367
368 switch (bo->mem.mem_type) {
369 case TTM_PL_VRAM:
370 drm->gem.vram_available -= bo->mem.size;
371 break;
372 case TTM_PL_TT:
373 drm->gem.gart_available -= bo->mem.size;
374 break;
375 default:
376 break;
377 }
378
379 out:
380 if (force && ret)
381 nvbo->tile_flags |= NOUVEAU_GEM_TILE_NONCONTIG;
382 ttm_bo_unreserve(bo);
383 return ret;
384 }
385
386 int
387 nouveau_bo_unpin(struct nouveau_bo *nvbo)
388 {
389 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
390 struct ttm_buffer_object *bo = &nvbo->bo;
391 int ret, ref;
392
393 ret = ttm_bo_reserve(bo, false, false, false, NULL);
394 if (ret)
395 return ret;
396
397 ref = --nvbo->pin_refcnt;
398 WARN_ON_ONCE(ref < 0);
399 if (ref)
400 goto out;
401
402 nouveau_bo_placement_set(nvbo, bo->mem.placement, 0);
403
404 ret = nouveau_bo_validate(nvbo, false, false);
405 if (ret == 0) {
406 switch (bo->mem.mem_type) {
407 case TTM_PL_VRAM:
408 drm->gem.vram_available += bo->mem.size;
409 break;
410 case TTM_PL_TT:
411 drm->gem.gart_available += bo->mem.size;
412 break;
413 default:
414 break;
415 }
416 }
417
418 out:
419 ttm_bo_unreserve(bo);
420 return ret;
421 }
422
423 int
424 nouveau_bo_map(struct nouveau_bo *nvbo)
425 {
426 int ret;
427
428 ret = ttm_bo_reserve(&nvbo->bo, false, false, false, NULL);
429 if (ret)
430 return ret;
431
432 /*
433 * TTM buffers allocated using the DMA API already have a mapping, let's
434 * use it instead.
435 */
436 if (!nvbo->force_coherent)
437 ret = ttm_bo_kmap(&nvbo->bo, 0, nvbo->bo.mem.num_pages,
438 &nvbo->kmap);
439
440 ttm_bo_unreserve(&nvbo->bo);
441 return ret;
442 }
443
444 void
445 nouveau_bo_unmap(struct nouveau_bo *nvbo)
446 {
447 if (!nvbo)
448 return;
449
450 /*
451 * TTM buffers allocated using the DMA API already had a coherent
452 * mapping which we used, no need to unmap.
453 */
454 if (!nvbo->force_coherent)
455 ttm_bo_kunmap(&nvbo->kmap);
456 }
457
458 void
459 nouveau_bo_sync_for_device(struct nouveau_bo *nvbo)
460 {
461 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
462 struct nouveau_device *device = nvxx_device(&drm->device);
463 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
464 int i;
465
466 if (!ttm_dma)
467 return;
468
469 /* Don't waste time looping if the object is coherent */
470 if (nvbo->force_coherent)
471 return;
472
473 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
474 dma_sync_single_for_device(nv_device_base(device),
475 ttm_dma->dma_address[i], PAGE_SIZE, DMA_TO_DEVICE);
476 }
477
478 void
479 nouveau_bo_sync_for_cpu(struct nouveau_bo *nvbo)
480 {
481 struct nouveau_drm *drm = nouveau_bdev(nvbo->bo.bdev);
482 struct nouveau_device *device = nvxx_device(&drm->device);
483 struct ttm_dma_tt *ttm_dma = (struct ttm_dma_tt *)nvbo->bo.ttm;
484 int i;
485
486 if (!ttm_dma)
487 return;
488
489 /* Don't waste time looping if the object is coherent */
490 if (nvbo->force_coherent)
491 return;
492
493 for (i = 0; i < ttm_dma->ttm.num_pages; i++)
494 dma_sync_single_for_cpu(nv_device_base(device),
495 ttm_dma->dma_address[i], PAGE_SIZE, DMA_FROM_DEVICE);
496 }
497
498 int
499 nouveau_bo_validate(struct nouveau_bo *nvbo, bool interruptible,
500 bool no_wait_gpu)
501 {
502 int ret;
503
504 ret = ttm_bo_validate(&nvbo->bo, &nvbo->placement,
505 interruptible, no_wait_gpu);
506 if (ret)
507 return ret;
508
509 nouveau_bo_sync_for_device(nvbo);
510
511 return 0;
512 }
513
514 static inline void *
515 _nouveau_bo_mem_index(struct nouveau_bo *nvbo, unsigned index, void *mem, u8 sz)
516 {
517 struct ttm_dma_tt *dma_tt;
518 u8 *m = mem;
519
520 index *= sz;
521
522 if (m) {
523 /* kmap'd address, return the corresponding offset */
524 m += index;
525 } else {
526 /* DMA-API mapping, lookup the right address */
527 dma_tt = (struct ttm_dma_tt *)nvbo->bo.ttm;
528 m = dma_tt->cpu_address[index / PAGE_SIZE];
529 m += index % PAGE_SIZE;
530 }
531
532 return m;
533 }
534 #define nouveau_bo_mem_index(o, i, m) _nouveau_bo_mem_index(o, i, m, sizeof(*m))
535
536 void
537 nouveau_bo_wr16(struct nouveau_bo *nvbo, unsigned index, u16 val)
538 {
539 bool is_iomem;
540 u16 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
541
542 mem = nouveau_bo_mem_index(nvbo, index, mem);
543
544 if (is_iomem)
545 iowrite16_native(val, (void __force __iomem *)mem);
546 else
547 *mem = val;
548 }
549
550 u32
551 nouveau_bo_rd32(struct nouveau_bo *nvbo, unsigned index)
552 {
553 bool is_iomem;
554 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
555
556 mem = nouveau_bo_mem_index(nvbo, index, mem);
557
558 if (is_iomem)
559 return ioread32_native((void __force __iomem *)mem);
560 else
561 return *mem;
562 }
563
564 void
565 nouveau_bo_wr32(struct nouveau_bo *nvbo, unsigned index, u32 val)
566 {
567 bool is_iomem;
568 u32 *mem = ttm_kmap_obj_virtual(&nvbo->kmap, &is_iomem);
569
570 mem = nouveau_bo_mem_index(nvbo, index, mem);
571
572 if (is_iomem)
573 iowrite32_native(val, (void __force __iomem *)mem);
574 else
575 *mem = val;
576 }
577
578 static struct ttm_tt *
579 nouveau_ttm_tt_create(struct ttm_bo_device *bdev, unsigned long size,
580 uint32_t page_flags, struct page *dummy_read)
581 {
582 #if __OS_HAS_AGP
583 struct nouveau_drm *drm = nouveau_bdev(bdev);
584 struct drm_device *dev = drm->dev;
585
586 if (drm->agp.stat == ENABLED) {
587 return ttm_agp_tt_create(bdev, dev->agp->bridge, size,
588 page_flags, dummy_read);
589 }
590 #endif
591
592 return nouveau_sgdma_create_ttm(bdev, size, page_flags, dummy_read);
593 }
594
595 static int
596 nouveau_bo_invalidate_caches(struct ttm_bo_device *bdev, uint32_t flags)
597 {
598 /* We'll do this from user space. */
599 return 0;
600 }
601
602 static int
603 nouveau_bo_init_mem_type(struct ttm_bo_device *bdev, uint32_t type,
604 struct ttm_mem_type_manager *man)
605 {
606 struct nouveau_drm *drm = nouveau_bdev(bdev);
607
608 switch (type) {
609 case TTM_PL_SYSTEM:
610 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
611 man->available_caching = TTM_PL_MASK_CACHING;
612 man->default_caching = TTM_PL_FLAG_CACHED;
613 break;
614 case TTM_PL_VRAM:
615 man->flags = TTM_MEMTYPE_FLAG_FIXED |
616 TTM_MEMTYPE_FLAG_MAPPABLE;
617 man->available_caching = TTM_PL_FLAG_UNCACHED |
618 TTM_PL_FLAG_WC;
619 man->default_caching = TTM_PL_FLAG_WC;
620
621 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
622 /* Some BARs do not support being ioremapped WC */
623 if (nvxx_bar(&drm->device)->iomap_uncached) {
624 man->available_caching = TTM_PL_FLAG_UNCACHED;
625 man->default_caching = TTM_PL_FLAG_UNCACHED;
626 }
627
628 man->func = &nouveau_vram_manager;
629 man->io_reserve_fastpath = false;
630 man->use_io_reserve_lru = true;
631 } else {
632 man->func = &ttm_bo_manager_func;
633 }
634 break;
635 case TTM_PL_TT:
636 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA)
637 man->func = &nouveau_gart_manager;
638 else
639 if (drm->agp.stat != ENABLED)
640 man->func = &nv04_gart_manager;
641 else
642 man->func = &ttm_bo_manager_func;
643
644 if (drm->agp.stat == ENABLED) {
645 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE;
646 man->available_caching = TTM_PL_FLAG_UNCACHED |
647 TTM_PL_FLAG_WC;
648 man->default_caching = TTM_PL_FLAG_WC;
649 } else {
650 man->flags = TTM_MEMTYPE_FLAG_MAPPABLE |
651 TTM_MEMTYPE_FLAG_CMA;
652 man->available_caching = TTM_PL_MASK_CACHING;
653 man->default_caching = TTM_PL_FLAG_CACHED;
654 }
655
656 break;
657 default:
658 return -EINVAL;
659 }
660 return 0;
661 }
662
663 static void
664 nouveau_bo_evict_flags(struct ttm_buffer_object *bo, struct ttm_placement *pl)
665 {
666 struct nouveau_bo *nvbo = nouveau_bo(bo);
667
668 switch (bo->mem.mem_type) {
669 case TTM_PL_VRAM:
670 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_TT,
671 TTM_PL_FLAG_SYSTEM);
672 break;
673 default:
674 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_SYSTEM, 0);
675 break;
676 }
677
678 *pl = nvbo->placement;
679 }
680
681
682 static int
683 nve0_bo_move_init(struct nouveau_channel *chan, u32 handle)
684 {
685 int ret = RING_SPACE(chan, 2);
686 if (ret == 0) {
687 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
688 OUT_RING (chan, handle & 0x0000ffff);
689 FIRE_RING (chan);
690 }
691 return ret;
692 }
693
694 static int
695 nve0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
696 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
697 {
698 struct nouveau_mem *node = old_mem->mm_node;
699 int ret = RING_SPACE(chan, 10);
700 if (ret == 0) {
701 BEGIN_NVC0(chan, NvSubCopy, 0x0400, 8);
702 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
703 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
704 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
705 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
706 OUT_RING (chan, PAGE_SIZE);
707 OUT_RING (chan, PAGE_SIZE);
708 OUT_RING (chan, PAGE_SIZE);
709 OUT_RING (chan, new_mem->num_pages);
710 BEGIN_IMC0(chan, NvSubCopy, 0x0300, 0x0386);
711 }
712 return ret;
713 }
714
715 static int
716 nvc0_bo_move_init(struct nouveau_channel *chan, u32 handle)
717 {
718 int ret = RING_SPACE(chan, 2);
719 if (ret == 0) {
720 BEGIN_NVC0(chan, NvSubCopy, 0x0000, 1);
721 OUT_RING (chan, handle);
722 }
723 return ret;
724 }
725
726 static int
727 nvc0_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
728 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
729 {
730 struct nouveau_mem *node = old_mem->mm_node;
731 u64 src_offset = node->vma[0].offset;
732 u64 dst_offset = node->vma[1].offset;
733 u32 page_count = new_mem->num_pages;
734 int ret;
735
736 page_count = new_mem->num_pages;
737 while (page_count) {
738 int line_count = (page_count > 8191) ? 8191 : page_count;
739
740 ret = RING_SPACE(chan, 11);
741 if (ret)
742 return ret;
743
744 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 8);
745 OUT_RING (chan, upper_32_bits(src_offset));
746 OUT_RING (chan, lower_32_bits(src_offset));
747 OUT_RING (chan, upper_32_bits(dst_offset));
748 OUT_RING (chan, lower_32_bits(dst_offset));
749 OUT_RING (chan, PAGE_SIZE);
750 OUT_RING (chan, PAGE_SIZE);
751 OUT_RING (chan, PAGE_SIZE);
752 OUT_RING (chan, line_count);
753 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
754 OUT_RING (chan, 0x00000110);
755
756 page_count -= line_count;
757 src_offset += (PAGE_SIZE * line_count);
758 dst_offset += (PAGE_SIZE * line_count);
759 }
760
761 return 0;
762 }
763
764 static int
765 nvc0_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
766 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
767 {
768 struct nouveau_mem *node = old_mem->mm_node;
769 u64 src_offset = node->vma[0].offset;
770 u64 dst_offset = node->vma[1].offset;
771 u32 page_count = new_mem->num_pages;
772 int ret;
773
774 page_count = new_mem->num_pages;
775 while (page_count) {
776 int line_count = (page_count > 2047) ? 2047 : page_count;
777
778 ret = RING_SPACE(chan, 12);
779 if (ret)
780 return ret;
781
782 BEGIN_NVC0(chan, NvSubCopy, 0x0238, 2);
783 OUT_RING (chan, upper_32_bits(dst_offset));
784 OUT_RING (chan, lower_32_bits(dst_offset));
785 BEGIN_NVC0(chan, NvSubCopy, 0x030c, 6);
786 OUT_RING (chan, upper_32_bits(src_offset));
787 OUT_RING (chan, lower_32_bits(src_offset));
788 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
789 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
790 OUT_RING (chan, PAGE_SIZE); /* line_length */
791 OUT_RING (chan, line_count);
792 BEGIN_NVC0(chan, NvSubCopy, 0x0300, 1);
793 OUT_RING (chan, 0x00100110);
794
795 page_count -= line_count;
796 src_offset += (PAGE_SIZE * line_count);
797 dst_offset += (PAGE_SIZE * line_count);
798 }
799
800 return 0;
801 }
802
803 static int
804 nva3_bo_move_copy(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
805 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
806 {
807 struct nouveau_mem *node = old_mem->mm_node;
808 u64 src_offset = node->vma[0].offset;
809 u64 dst_offset = node->vma[1].offset;
810 u32 page_count = new_mem->num_pages;
811 int ret;
812
813 page_count = new_mem->num_pages;
814 while (page_count) {
815 int line_count = (page_count > 8191) ? 8191 : page_count;
816
817 ret = RING_SPACE(chan, 11);
818 if (ret)
819 return ret;
820
821 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
822 OUT_RING (chan, upper_32_bits(src_offset));
823 OUT_RING (chan, lower_32_bits(src_offset));
824 OUT_RING (chan, upper_32_bits(dst_offset));
825 OUT_RING (chan, lower_32_bits(dst_offset));
826 OUT_RING (chan, PAGE_SIZE);
827 OUT_RING (chan, PAGE_SIZE);
828 OUT_RING (chan, PAGE_SIZE);
829 OUT_RING (chan, line_count);
830 BEGIN_NV04(chan, NvSubCopy, 0x0300, 1);
831 OUT_RING (chan, 0x00000110);
832
833 page_count -= line_count;
834 src_offset += (PAGE_SIZE * line_count);
835 dst_offset += (PAGE_SIZE * line_count);
836 }
837
838 return 0;
839 }
840
841 static int
842 nv98_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
843 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
844 {
845 struct nouveau_mem *node = old_mem->mm_node;
846 int ret = RING_SPACE(chan, 7);
847 if (ret == 0) {
848 BEGIN_NV04(chan, NvSubCopy, 0x0320, 6);
849 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
850 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
851 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
852 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
853 OUT_RING (chan, 0x00000000 /* COPY */);
854 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
855 }
856 return ret;
857 }
858
859 static int
860 nv84_bo_move_exec(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
861 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
862 {
863 struct nouveau_mem *node = old_mem->mm_node;
864 int ret = RING_SPACE(chan, 7);
865 if (ret == 0) {
866 BEGIN_NV04(chan, NvSubCopy, 0x0304, 6);
867 OUT_RING (chan, new_mem->num_pages << PAGE_SHIFT);
868 OUT_RING (chan, upper_32_bits(node->vma[0].offset));
869 OUT_RING (chan, lower_32_bits(node->vma[0].offset));
870 OUT_RING (chan, upper_32_bits(node->vma[1].offset));
871 OUT_RING (chan, lower_32_bits(node->vma[1].offset));
872 OUT_RING (chan, 0x00000000 /* MODE_COPY, QUERY_NONE */);
873 }
874 return ret;
875 }
876
877 static int
878 nv50_bo_move_init(struct nouveau_channel *chan, u32 handle)
879 {
880 int ret = RING_SPACE(chan, 6);
881 if (ret == 0) {
882 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
883 OUT_RING (chan, handle);
884 BEGIN_NV04(chan, NvSubCopy, 0x0180, 3);
885 OUT_RING (chan, chan->drm->ntfy.handle);
886 OUT_RING (chan, chan->vram.handle);
887 OUT_RING (chan, chan->vram.handle);
888 }
889
890 return ret;
891 }
892
893 static int
894 nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
895 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
896 {
897 struct nouveau_mem *node = old_mem->mm_node;
898 u64 length = (new_mem->num_pages << PAGE_SHIFT);
899 u64 src_offset = node->vma[0].offset;
900 u64 dst_offset = node->vma[1].offset;
901 int src_tiled = !!node->memtype;
902 int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype;
903 int ret;
904
905 while (length) {
906 u32 amount, stride, height;
907
908 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
909 if (ret)
910 return ret;
911
912 amount = min(length, (u64)(4 * 1024 * 1024));
913 stride = 16 * 4;
914 height = amount / stride;
915
916 if (src_tiled) {
917 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
918 OUT_RING (chan, 0);
919 OUT_RING (chan, 0);
920 OUT_RING (chan, stride);
921 OUT_RING (chan, height);
922 OUT_RING (chan, 1);
923 OUT_RING (chan, 0);
924 OUT_RING (chan, 0);
925 } else {
926 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
927 OUT_RING (chan, 1);
928 }
929 if (dst_tiled) {
930 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
931 OUT_RING (chan, 0);
932 OUT_RING (chan, 0);
933 OUT_RING (chan, stride);
934 OUT_RING (chan, height);
935 OUT_RING (chan, 1);
936 OUT_RING (chan, 0);
937 OUT_RING (chan, 0);
938 } else {
939 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
940 OUT_RING (chan, 1);
941 }
942
943 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
944 OUT_RING (chan, upper_32_bits(src_offset));
945 OUT_RING (chan, upper_32_bits(dst_offset));
946 BEGIN_NV04(chan, NvSubCopy, 0x030c, 8);
947 OUT_RING (chan, lower_32_bits(src_offset));
948 OUT_RING (chan, lower_32_bits(dst_offset));
949 OUT_RING (chan, stride);
950 OUT_RING (chan, stride);
951 OUT_RING (chan, stride);
952 OUT_RING (chan, height);
953 OUT_RING (chan, 0x00000101);
954 OUT_RING (chan, 0x00000000);
955 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
956 OUT_RING (chan, 0);
957
958 length -= amount;
959 src_offset += amount;
960 dst_offset += amount;
961 }
962
963 return 0;
964 }
965
966 static int
967 nv04_bo_move_init(struct nouveau_channel *chan, u32 handle)
968 {
969 int ret = RING_SPACE(chan, 4);
970 if (ret == 0) {
971 BEGIN_NV04(chan, NvSubCopy, 0x0000, 1);
972 OUT_RING (chan, handle);
973 BEGIN_NV04(chan, NvSubCopy, 0x0180, 1);
974 OUT_RING (chan, chan->drm->ntfy.handle);
975 }
976
977 return ret;
978 }
979
980 static inline uint32_t
981 nouveau_bo_mem_ctxdma(struct ttm_buffer_object *bo,
982 struct nouveau_channel *chan, struct ttm_mem_reg *mem)
983 {
984 if (mem->mem_type == TTM_PL_TT)
985 return NvDmaTT;
986 return chan->vram.handle;
987 }
988
989 static int
990 nv04_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
991 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
992 {
993 u32 src_offset = old_mem->start << PAGE_SHIFT;
994 u32 dst_offset = new_mem->start << PAGE_SHIFT;
995 u32 page_count = new_mem->num_pages;
996 int ret;
997
998 ret = RING_SPACE(chan, 3);
999 if (ret)
1000 return ret;
1001
1002 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_DMA_SOURCE, 2);
1003 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, old_mem));
1004 OUT_RING (chan, nouveau_bo_mem_ctxdma(bo, chan, new_mem));
1005
1006 page_count = new_mem->num_pages;
1007 while (page_count) {
1008 int line_count = (page_count > 2047) ? 2047 : page_count;
1009
1010 ret = RING_SPACE(chan, 11);
1011 if (ret)
1012 return ret;
1013
1014 BEGIN_NV04(chan, NvSubCopy,
1015 NV_MEMORY_TO_MEMORY_FORMAT_OFFSET_IN, 8);
1016 OUT_RING (chan, src_offset);
1017 OUT_RING (chan, dst_offset);
1018 OUT_RING (chan, PAGE_SIZE); /* src_pitch */
1019 OUT_RING (chan, PAGE_SIZE); /* dst_pitch */
1020 OUT_RING (chan, PAGE_SIZE); /* line_length */
1021 OUT_RING (chan, line_count);
1022 OUT_RING (chan, 0x00000101);
1023 OUT_RING (chan, 0x00000000);
1024 BEGIN_NV04(chan, NvSubCopy, NV_MEMORY_TO_MEMORY_FORMAT_NOP, 1);
1025 OUT_RING (chan, 0);
1026
1027 page_count -= line_count;
1028 src_offset += (PAGE_SIZE * line_count);
1029 dst_offset += (PAGE_SIZE * line_count);
1030 }
1031
1032 return 0;
1033 }
1034
1035 static int
1036 nouveau_bo_move_prep(struct nouveau_drm *drm, struct ttm_buffer_object *bo,
1037 struct ttm_mem_reg *mem)
1038 {
1039 struct nouveau_mem *old_node = bo->mem.mm_node;
1040 struct nouveau_mem *new_node = mem->mm_node;
1041 u64 size = (u64)mem->num_pages << PAGE_SHIFT;
1042 int ret;
1043
1044 ret = nouveau_vm_get(drm->client.vm, size, old_node->page_shift,
1045 NV_MEM_ACCESS_RW, &old_node->vma[0]);
1046 if (ret)
1047 return ret;
1048
1049 ret = nouveau_vm_get(drm->client.vm, size, new_node->page_shift,
1050 NV_MEM_ACCESS_RW, &old_node->vma[1]);
1051 if (ret) {
1052 nouveau_vm_put(&old_node->vma[0]);
1053 return ret;
1054 }
1055
1056 nouveau_vm_map(&old_node->vma[0], old_node);
1057 nouveau_vm_map(&old_node->vma[1], new_node);
1058 return 0;
1059 }
1060
1061 static int
1062 nouveau_bo_move_m2mf(struct ttm_buffer_object *bo, int evict, bool intr,
1063 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1064 {
1065 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1066 struct nouveau_channel *chan = drm->ttm.chan;
1067 struct nouveau_cli *cli = (void *)nvif_client(&chan->device->base);
1068 struct nouveau_fence *fence;
1069 int ret;
1070
1071 /* create temporary vmas for the transfer and attach them to the
1072 * old nouveau_mem node, these will get cleaned up after ttm has
1073 * destroyed the ttm_mem_reg
1074 */
1075 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1076 ret = nouveau_bo_move_prep(drm, bo, new_mem);
1077 if (ret)
1078 return ret;
1079 }
1080
1081 mutex_lock_nested(&cli->mutex, SINGLE_DEPTH_NESTING);
1082 ret = nouveau_fence_sync(nouveau_bo(bo), chan, true, intr);
1083 if (ret == 0) {
1084 ret = drm->ttm.move(chan, bo, &bo->mem, new_mem);
1085 if (ret == 0) {
1086 ret = nouveau_fence_new(chan, false, &fence);
1087 if (ret == 0) {
1088 ret = ttm_bo_move_accel_cleanup(bo,
1089 &fence->base,
1090 evict,
1091 no_wait_gpu,
1092 new_mem);
1093 nouveau_fence_unref(&fence);
1094 }
1095 }
1096 }
1097 mutex_unlock(&cli->mutex);
1098 return ret;
1099 }
1100
1101 void
1102 nouveau_bo_move_init(struct nouveau_drm *drm)
1103 {
1104 static const struct {
1105 const char *name;
1106 int engine;
1107 u32 oclass;
1108 int (*exec)(struct nouveau_channel *,
1109 struct ttm_buffer_object *,
1110 struct ttm_mem_reg *, struct ttm_mem_reg *);
1111 int (*init)(struct nouveau_channel *, u32 handle);
1112 } _methods[] = {
1113 { "COPY", 4, 0xa0b5, nve0_bo_move_copy, nve0_bo_move_init },
1114 { "GRCE", 0, 0xa0b5, nve0_bo_move_copy, nvc0_bo_move_init },
1115 { "COPY1", 5, 0x90b8, nvc0_bo_move_copy, nvc0_bo_move_init },
1116 { "COPY0", 4, 0x90b5, nvc0_bo_move_copy, nvc0_bo_move_init },
1117 { "COPY", 0, 0x85b5, nva3_bo_move_copy, nv50_bo_move_init },
1118 { "CRYPT", 0, 0x74c1, nv84_bo_move_exec, nv50_bo_move_init },
1119 { "M2MF", 0, 0x9039, nvc0_bo_move_m2mf, nvc0_bo_move_init },
1120 { "M2MF", 0, 0x5039, nv50_bo_move_m2mf, nv50_bo_move_init },
1121 { "M2MF", 0, 0x0039, nv04_bo_move_m2mf, nv04_bo_move_init },
1122 {},
1123 { "CRYPT", 0, 0x88b4, nv98_bo_move_exec, nv50_bo_move_init },
1124 }, *mthd = _methods;
1125 const char *name = "CPU";
1126 int ret;
1127
1128 do {
1129 struct nouveau_channel *chan;
1130
1131 if (mthd->engine)
1132 chan = drm->cechan;
1133 else
1134 chan = drm->channel;
1135 if (chan == NULL)
1136 continue;
1137
1138 ret = nvif_object_init(chan->object, NULL,
1139 mthd->oclass | (mthd->engine << 16),
1140 mthd->oclass, NULL, 0,
1141 &drm->ttm.copy);
1142 if (ret == 0) {
1143 ret = mthd->init(chan, drm->ttm.copy.handle);
1144 if (ret) {
1145 nvif_object_fini(&drm->ttm.copy);
1146 continue;
1147 }
1148
1149 drm->ttm.move = mthd->exec;
1150 drm->ttm.chan = chan;
1151 name = mthd->name;
1152 break;
1153 }
1154 } while ((++mthd)->exec);
1155
1156 NV_INFO(drm, "MM: using %s for buffer copies\n", name);
1157 }
1158
1159 static int
1160 nouveau_bo_move_flipd(struct ttm_buffer_object *bo, bool evict, bool intr,
1161 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1162 {
1163 struct ttm_place placement_memtype = {
1164 .fpfn = 0,
1165 .lpfn = 0,
1166 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1167 };
1168 struct ttm_placement placement;
1169 struct ttm_mem_reg tmp_mem;
1170 int ret;
1171
1172 placement.num_placement = placement.num_busy_placement = 1;
1173 placement.placement = placement.busy_placement = &placement_memtype;
1174
1175 tmp_mem = *new_mem;
1176 tmp_mem.mm_node = NULL;
1177 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1178 if (ret)
1179 return ret;
1180
1181 ret = ttm_tt_bind(bo->ttm, &tmp_mem);
1182 if (ret)
1183 goto out;
1184
1185 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, &tmp_mem);
1186 if (ret)
1187 goto out;
1188
1189 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, new_mem);
1190 out:
1191 ttm_bo_mem_put(bo, &tmp_mem);
1192 return ret;
1193 }
1194
1195 static int
1196 nouveau_bo_move_flips(struct ttm_buffer_object *bo, bool evict, bool intr,
1197 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1198 {
1199 struct ttm_place placement_memtype = {
1200 .fpfn = 0,
1201 .lpfn = 0,
1202 .flags = TTM_PL_FLAG_TT | TTM_PL_MASK_CACHING
1203 };
1204 struct ttm_placement placement;
1205 struct ttm_mem_reg tmp_mem;
1206 int ret;
1207
1208 placement.num_placement = placement.num_busy_placement = 1;
1209 placement.placement = placement.busy_placement = &placement_memtype;
1210
1211 tmp_mem = *new_mem;
1212 tmp_mem.mm_node = NULL;
1213 ret = ttm_bo_mem_space(bo, &placement, &tmp_mem, intr, no_wait_gpu);
1214 if (ret)
1215 return ret;
1216
1217 ret = ttm_bo_move_ttm(bo, true, no_wait_gpu, &tmp_mem);
1218 if (ret)
1219 goto out;
1220
1221 ret = nouveau_bo_move_m2mf(bo, true, intr, no_wait_gpu, new_mem);
1222 if (ret)
1223 goto out;
1224
1225 out:
1226 ttm_bo_mem_put(bo, &tmp_mem);
1227 return ret;
1228 }
1229
1230 static void
1231 nouveau_bo_move_ntfy(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem)
1232 {
1233 struct nouveau_bo *nvbo = nouveau_bo(bo);
1234 struct nouveau_vma *vma;
1235
1236 /* ttm can now (stupidly) pass the driver bos it didn't create... */
1237 if (bo->destroy != nouveau_bo_del_ttm)
1238 return;
1239
1240 list_for_each_entry(vma, &nvbo->vma_list, head) {
1241 if (new_mem && new_mem->mem_type != TTM_PL_SYSTEM &&
1242 (new_mem->mem_type == TTM_PL_VRAM ||
1243 nvbo->page_shift != vma->vm->mmu->lpg_shift)) {
1244 nouveau_vm_map(vma, new_mem->mm_node);
1245 } else {
1246 nouveau_vm_unmap(vma);
1247 }
1248 }
1249 }
1250
1251 static int
1252 nouveau_bo_vm_bind(struct ttm_buffer_object *bo, struct ttm_mem_reg *new_mem,
1253 struct nouveau_drm_tile **new_tile)
1254 {
1255 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1256 struct drm_device *dev = drm->dev;
1257 struct nouveau_bo *nvbo = nouveau_bo(bo);
1258 u64 offset = new_mem->start << PAGE_SHIFT;
1259
1260 *new_tile = NULL;
1261 if (new_mem->mem_type != TTM_PL_VRAM)
1262 return 0;
1263
1264 if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
1265 *new_tile = nv10_bo_set_tiling(dev, offset, new_mem->size,
1266 nvbo->tile_mode,
1267 nvbo->tile_flags);
1268 }
1269
1270 return 0;
1271 }
1272
1273 static void
1274 nouveau_bo_vm_cleanup(struct ttm_buffer_object *bo,
1275 struct nouveau_drm_tile *new_tile,
1276 struct nouveau_drm_tile **old_tile)
1277 {
1278 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1279 struct drm_device *dev = drm->dev;
1280 struct fence *fence = reservation_object_get_excl(bo->resv);
1281
1282 nv10_bo_put_tile_region(dev, *old_tile, fence);
1283 *old_tile = new_tile;
1284 }
1285
1286 static int
1287 nouveau_bo_move(struct ttm_buffer_object *bo, bool evict, bool intr,
1288 bool no_wait_gpu, struct ttm_mem_reg *new_mem)
1289 {
1290 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1291 struct nouveau_bo *nvbo = nouveau_bo(bo);
1292 struct ttm_mem_reg *old_mem = &bo->mem;
1293 struct nouveau_drm_tile *new_tile = NULL;
1294 int ret = 0;
1295
1296 if (nvbo->pin_refcnt)
1297 NV_WARN(drm, "Moving pinned object %p!\n", nvbo);
1298
1299 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1300 ret = nouveau_bo_vm_bind(bo, new_mem, &new_tile);
1301 if (ret)
1302 return ret;
1303 }
1304
1305 /* Fake bo copy. */
1306 if (old_mem->mem_type == TTM_PL_SYSTEM && !bo->ttm) {
1307 BUG_ON(bo->mem.mm_node != NULL);
1308 bo->mem = *new_mem;
1309 new_mem->mm_node = NULL;
1310 goto out;
1311 }
1312
1313 /* Hardware assisted copy. */
1314 if (drm->ttm.move) {
1315 if (new_mem->mem_type == TTM_PL_SYSTEM)
1316 ret = nouveau_bo_move_flipd(bo, evict, intr,
1317 no_wait_gpu, new_mem);
1318 else if (old_mem->mem_type == TTM_PL_SYSTEM)
1319 ret = nouveau_bo_move_flips(bo, evict, intr,
1320 no_wait_gpu, new_mem);
1321 else
1322 ret = nouveau_bo_move_m2mf(bo, evict, intr,
1323 no_wait_gpu, new_mem);
1324 if (!ret)
1325 goto out;
1326 }
1327
1328 /* Fallback to software copy. */
1329 ret = ttm_bo_wait(bo, true, intr, no_wait_gpu);
1330 if (ret == 0)
1331 ret = ttm_bo_move_memcpy(bo, evict, no_wait_gpu, new_mem);
1332
1333 out:
1334 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA) {
1335 if (ret)
1336 nouveau_bo_vm_cleanup(bo, NULL, &new_tile);
1337 else
1338 nouveau_bo_vm_cleanup(bo, new_tile, &nvbo->tile);
1339 }
1340
1341 return ret;
1342 }
1343
1344 static int
1345 nouveau_bo_verify_access(struct ttm_buffer_object *bo, struct file *filp)
1346 {
1347 struct nouveau_bo *nvbo = nouveau_bo(bo);
1348
1349 return drm_vma_node_verify_access(&nvbo->gem.vma_node, filp);
1350 }
1351
1352 static int
1353 nouveau_ttm_io_mem_reserve(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1354 {
1355 struct ttm_mem_type_manager *man = &bdev->man[mem->mem_type];
1356 struct nouveau_drm *drm = nouveau_bdev(bdev);
1357 struct nouveau_mem *node = mem->mm_node;
1358 int ret;
1359
1360 mem->bus.addr = NULL;
1361 mem->bus.offset = 0;
1362 mem->bus.size = mem->num_pages << PAGE_SHIFT;
1363 mem->bus.base = 0;
1364 mem->bus.is_iomem = false;
1365 if (!(man->flags & TTM_MEMTYPE_FLAG_MAPPABLE))
1366 return -EINVAL;
1367 switch (mem->mem_type) {
1368 case TTM_PL_SYSTEM:
1369 /* System memory */
1370 return 0;
1371 case TTM_PL_TT:
1372 #if __OS_HAS_AGP
1373 if (drm->agp.stat == ENABLED) {
1374 mem->bus.offset = mem->start << PAGE_SHIFT;
1375 mem->bus.base = drm->agp.base;
1376 mem->bus.is_iomem = !drm->dev->agp->cant_use_aperture;
1377 }
1378 #endif
1379 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA || !node->memtype)
1380 /* untiled */
1381 break;
1382 /* fallthrough, tiled memory */
1383 case TTM_PL_VRAM:
1384 mem->bus.offset = mem->start << PAGE_SHIFT;
1385 mem->bus.base = nv_device_resource_start(nvxx_device(&drm->device), 1);
1386 mem->bus.is_iomem = true;
1387 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) {
1388 struct nouveau_bar *bar = nvxx_bar(&drm->device);
1389
1390 ret = bar->umap(bar, node, NV_MEM_ACCESS_RW,
1391 &node->bar_vma);
1392 if (ret)
1393 return ret;
1394
1395 mem->bus.offset = node->bar_vma.offset;
1396 }
1397 break;
1398 default:
1399 return -EINVAL;
1400 }
1401 return 0;
1402 }
1403
1404 static void
1405 nouveau_ttm_io_mem_free(struct ttm_bo_device *bdev, struct ttm_mem_reg *mem)
1406 {
1407 struct nouveau_drm *drm = nouveau_bdev(bdev);
1408 struct nouveau_bar *bar = nvxx_bar(&drm->device);
1409 struct nouveau_mem *node = mem->mm_node;
1410
1411 if (!node->bar_vma.node)
1412 return;
1413
1414 bar->unmap(bar, &node->bar_vma);
1415 }
1416
1417 static int
1418 nouveau_ttm_fault_reserve_notify(struct ttm_buffer_object *bo)
1419 {
1420 struct nouveau_drm *drm = nouveau_bdev(bo->bdev);
1421 struct nouveau_bo *nvbo = nouveau_bo(bo);
1422 struct nvif_device *device = &drm->device;
1423 u32 mappable = nv_device_resource_len(nvxx_device(device), 1) >> PAGE_SHIFT;
1424 int i, ret;
1425
1426 /* as long as the bo isn't in vram, and isn't tiled, we've got
1427 * nothing to do here.
1428 */
1429 if (bo->mem.mem_type != TTM_PL_VRAM) {
1430 if (drm->device.info.family < NV_DEVICE_INFO_V0_TESLA ||
1431 !nouveau_bo_tile_layout(nvbo))
1432 return 0;
1433
1434 if (bo->mem.mem_type == TTM_PL_SYSTEM) {
1435 nouveau_bo_placement_set(nvbo, TTM_PL_TT, 0);
1436
1437 ret = nouveau_bo_validate(nvbo, false, false);
1438 if (ret)
1439 return ret;
1440 }
1441 return 0;
1442 }
1443
1444 /* make sure bo is in mappable vram */
1445 if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA ||
1446 bo->mem.start + bo->mem.num_pages < mappable)
1447 return 0;
1448
1449 for (i = 0; i < nvbo->placement.num_placement; ++i) {
1450 nvbo->placements[i].fpfn = 0;
1451 nvbo->placements[i].lpfn = mappable;
1452 }
1453
1454 for (i = 0; i < nvbo->placement.num_busy_placement; ++i) {
1455 nvbo->busy_placements[i].fpfn = 0;
1456 nvbo->busy_placements[i].lpfn = mappable;
1457 }
1458
1459 nouveau_bo_placement_set(nvbo, TTM_PL_FLAG_VRAM, 0);
1460 return nouveau_bo_validate(nvbo, false, false);
1461 }
1462
1463 static int
1464 nouveau_ttm_tt_populate(struct ttm_tt *ttm)
1465 {
1466 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1467 struct nouveau_drm *drm;
1468 struct nouveau_device *device;
1469 struct drm_device *dev;
1470 struct device *pdev;
1471 unsigned i;
1472 int r;
1473 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1474
1475 if (ttm->state != tt_unpopulated)
1476 return 0;
1477
1478 if (slave && ttm->sg) {
1479 /* make userspace faulting work */
1480 drm_prime_sg_to_page_addr_arrays(ttm->sg, ttm->pages,
1481 ttm_dma->dma_address, ttm->num_pages);
1482 ttm->state = tt_unbound;
1483 return 0;
1484 }
1485
1486 drm = nouveau_bdev(ttm->bdev);
1487 device = nvxx_device(&drm->device);
1488 dev = drm->dev;
1489 pdev = nv_device_base(device);
1490
1491 /*
1492 * Objects matching this condition have been marked as force_coherent,
1493 * so use the DMA API for them.
1494 */
1495 if (!nv_device_is_cpu_coherent(device) &&
1496 ttm->caching_state == tt_uncached)
1497 return ttm_dma_populate(ttm_dma, dev->dev);
1498
1499 #if __OS_HAS_AGP
1500 if (drm->agp.stat == ENABLED) {
1501 return ttm_agp_tt_populate(ttm);
1502 }
1503 #endif
1504
1505 #ifdef CONFIG_SWIOTLB
1506 if (swiotlb_nr_tbl()) {
1507 return ttm_dma_populate((void *)ttm, dev->dev);
1508 }
1509 #endif
1510
1511 r = ttm_pool_populate(ttm);
1512 if (r) {
1513 return r;
1514 }
1515
1516 for (i = 0; i < ttm->num_pages; i++) {
1517 dma_addr_t addr;
1518
1519 addr = dma_map_page(pdev, ttm->pages[i], 0, PAGE_SIZE,
1520 DMA_BIDIRECTIONAL);
1521
1522 if (dma_mapping_error(pdev, addr)) {
1523 while (--i) {
1524 dma_unmap_page(pdev, ttm_dma->dma_address[i],
1525 PAGE_SIZE, DMA_BIDIRECTIONAL);
1526 ttm_dma->dma_address[i] = 0;
1527 }
1528 ttm_pool_unpopulate(ttm);
1529 return -EFAULT;
1530 }
1531
1532 ttm_dma->dma_address[i] = addr;
1533 }
1534 return 0;
1535 }
1536
1537 static void
1538 nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm)
1539 {
1540 struct ttm_dma_tt *ttm_dma = (void *)ttm;
1541 struct nouveau_drm *drm;
1542 struct nouveau_device *device;
1543 struct drm_device *dev;
1544 struct device *pdev;
1545 unsigned i;
1546 bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
1547
1548 if (slave)
1549 return;
1550
1551 drm = nouveau_bdev(ttm->bdev);
1552 device = nvxx_device(&drm->device);
1553 dev = drm->dev;
1554 pdev = nv_device_base(device);
1555
1556 /*
1557 * Objects matching this condition have been marked as force_coherent,
1558 * so use the DMA API for them.
1559 */
1560 if (!nv_device_is_cpu_coherent(device) &&
1561 ttm->caching_state == tt_uncached) {
1562 ttm_dma_unpopulate(ttm_dma, dev->dev);
1563 return;
1564 }
1565
1566 #if __OS_HAS_AGP
1567 if (drm->agp.stat == ENABLED) {
1568 ttm_agp_tt_unpopulate(ttm);
1569 return;
1570 }
1571 #endif
1572
1573 #ifdef CONFIG_SWIOTLB
1574 if (swiotlb_nr_tbl()) {
1575 ttm_dma_unpopulate((void *)ttm, dev->dev);
1576 return;
1577 }
1578 #endif
1579
1580 for (i = 0; i < ttm->num_pages; i++) {
1581 if (ttm_dma->dma_address[i]) {
1582 dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE,
1583 DMA_BIDIRECTIONAL);
1584 }
1585 }
1586
1587 ttm_pool_unpopulate(ttm);
1588 }
1589
1590 void
1591 nouveau_bo_fence(struct nouveau_bo *nvbo, struct nouveau_fence *fence, bool exclusive)
1592 {
1593 struct reservation_object *resv = nvbo->bo.resv;
1594
1595 if (exclusive)
1596 reservation_object_add_excl_fence(resv, &fence->base);
1597 else if (fence)
1598 reservation_object_add_shared_fence(resv, &fence->base);
1599 }
1600
1601 struct ttm_bo_driver nouveau_bo_driver = {
1602 .ttm_tt_create = &nouveau_ttm_tt_create,
1603 .ttm_tt_populate = &nouveau_ttm_tt_populate,
1604 .ttm_tt_unpopulate = &nouveau_ttm_tt_unpopulate,
1605 .invalidate_caches = nouveau_bo_invalidate_caches,
1606 .init_mem_type = nouveau_bo_init_mem_type,
1607 .evict_flags = nouveau_bo_evict_flags,
1608 .move_notify = nouveau_bo_move_ntfy,
1609 .move = nouveau_bo_move,
1610 .verify_access = nouveau_bo_verify_access,
1611 .fault_reserve_notify = &nouveau_ttm_fault_reserve_notify,
1612 .io_mem_reserve = &nouveau_ttm_io_mem_reserve,
1613 .io_mem_free = &nouveau_ttm_io_mem_free,
1614 };
1615
1616 struct nouveau_vma *
1617 nouveau_bo_vma_find(struct nouveau_bo *nvbo, struct nouveau_vm *vm)
1618 {
1619 struct nouveau_vma *vma;
1620 list_for_each_entry(vma, &nvbo->vma_list, head) {
1621 if (vma->vm == vm)
1622 return vma;
1623 }
1624
1625 return NULL;
1626 }
1627
1628 int
1629 nouveau_bo_vma_add(struct nouveau_bo *nvbo, struct nouveau_vm *vm,
1630 struct nouveau_vma *vma)
1631 {
1632 const u32 size = nvbo->bo.mem.num_pages << PAGE_SHIFT;
1633 int ret;
1634
1635 ret = nouveau_vm_get(vm, size, nvbo->page_shift,
1636 NV_MEM_ACCESS_RW, vma);
1637 if (ret)
1638 return ret;
1639
1640 if ( nvbo->bo.mem.mem_type != TTM_PL_SYSTEM &&
1641 (nvbo->bo.mem.mem_type == TTM_PL_VRAM ||
1642 nvbo->page_shift != vma->vm->mmu->lpg_shift))
1643 nouveau_vm_map(vma, nvbo->bo.mem.mm_node);
1644
1645 list_add_tail(&vma->head, &nvbo->vma_list);
1646 vma->refcount = 1;
1647 return 0;
1648 }
1649
1650 void
1651 nouveau_bo_vma_del(struct nouveau_bo *nvbo, struct nouveau_vma *vma)
1652 {
1653 if (vma->node) {
1654 if (nvbo->bo.mem.mem_type != TTM_PL_SYSTEM)
1655 nouveau_vm_unmap(vma);
1656 nouveau_vm_put(vma);
1657 list_del(&vma->head);
1658 }
1659 }
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