arch/arm/mach-shmobile/setup-rcar-gen2.c

   1 /*
   2  * R-Car Generation 2 support
   3  *
   4  * Copyright (C) 2013  Renesas Solutions Corp.
   5  * Copyright (C) 2013  Magnus Damm
   6  * Copyright (C) 2014  Ulrich Hecht
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; version 2 of the License.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  20  */
  21
  22 #include <linux/clk/shmobile.h>
  23 #include <linux/clocksource.h>
  24 #include <linux/device.h>
  25 #include <linux/dma-contiguous.h>
  26 #include <linux/io.h>
  27 #include <linux/kernel.h>
  28 #include <linux/of.h>
  29 #include <linux/of_fdt.h>
  30 #include <asm/mach/arch.h>
  31 #include "common.h"
  32 #include "rcar-gen2.h"
  33
  34 #define MODEMR 0xe6160060
  35
  36 u32 rcar_gen2_read_mode_pins(void)
  37 {
  38         static u32 mode;
  39         static bool mode_valid;
  40
  41         if (!mode_valid) {
  42                 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
  43                 BUG_ON(!modemr);
  44                 mode = ioread32(modemr);
  45                 iounmap(modemr);
  46                 mode_valid = true;
  47         }
  48
  49         return mode;
  50 }
  51
  52 #define CNTCR 0
  53 #define CNTFID0 0x20
  54
  55 void __init rcar_gen2_timer_init(void)
  56 {
  57 #if defined(CONFIG_ARM_ARCH_TIMER) || defined(CONFIG_COMMON_CLK)
  58         u32 mode = rcar_gen2_read_mode_pins();
  59         bool is_e2 = (bool)of_find_compatible_node(NULL, NULL,
  60                 "renesas,r8a7794");
  61 #endif
  62 #ifdef CONFIG_ARM_ARCH_TIMER
  63         void __iomem *base;
  64         int extal_mhz = 0;
  65         u32 freq;
  66
  67         if (is_e2) {
  68                 freq = 260000000 / 8;   /* ZS / 8 */
  69                 /* CNTVOFF has to be initialized either from non-secure
  70                  * Hypervisor mode or secure Monitor mode with SCR.NS==1.
  71                  * If TrustZone is enabled then it should be handled by the
  72                  * secure code.
  73                  */
  74                 asm volatile(
  75                 "       cps     0x16\n"
  76                 "       mrc     p15, 0, r1, c1, c1, 0\n"
  77                 "       orr     r0, r1, #1\n"
  78                 "       mcr     p15, 0, r0, c1, c1, 0\n"
  79                 "       isb\n"
  80                 "       mov     r0, #0\n"
  81                 "       mcrr    p15, 4, r0, r0, c14\n"
  82                 "       isb\n"
  83                 "       mcr     p15, 0, r1, c1, c1, 0\n"
  84                 "       isb\n"
  85                 "       cps     0x13\n"
  86                         : : : "r0", "r1");
  87         } else {
  88                 /* At Linux boot time the r8a7790 arch timer comes up
  89                  * with the counter disabled. Moreover, it may also report
  90                  * a potentially incorrect fixed 13 MHz frequency. To be
  91                  * correct these registers need to be updated to use the
  92                  * frequency EXTAL / 2 which can be determined by the MD pins.
  93                  */
  94
  95                 switch (mode & (MD(14) | MD(13))) {
  96                 case 0:
  97                         extal_mhz = 15;
  98                         break;
  99                 case MD(13):
 100                         extal_mhz = 20;
 101                         break;
 102                 case MD(14):
 103                         extal_mhz = 26;
 104                         break;
 105                 case MD(13) | MD(14):
 106                         extal_mhz = 30;
 107                         break;
 108                 }
 109
 110                 /* The arch timer frequency equals EXTAL / 2 */
 111                 freq = extal_mhz * (1000000 / 2);
 112         }
 113
 114         /* Remap "armgcnt address map" space */
 115         base = ioremap(0xe6080000, PAGE_SIZE);
 116
 117         /*
 118          * Update the timer if it is either not running, or is not at the
 119          * right frequency. The timer is only configurable in secure mode
 120          * so this avoids an abort if the loader started the timer and
 121          * entered the kernel in non-secure mode.
 122          */
 123
 124         if ((ioread32(base + CNTCR) & 1) == 0 ||
 125             ioread32(base + CNTFID0) != freq) {
 126                 /* Update registers with correct frequency */
 127                 iowrite32(freq, base + CNTFID0);
 128                 asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r" (freq));
 129
 130                 /* make sure arch timer is started by setting bit 0 of CNTCR */
 131                 iowrite32(1, base + CNTCR);
 132         }
 133
 134         iounmap(base);
 135 #endif /* CONFIG_ARM_ARCH_TIMER */
 136
 137 #ifdef CONFIG_COMMON_CLK
 138         rcar_gen2_clocks_init(mode);
 139 #endif
 140 #ifdef CONFIG_ARCH_SHMOBILE_MULTI
 141         clocksource_of_init();
 142 #endif
 143 }
 144
 145 struct memory_reserve_config {
 146         u64 reserved;
 147         u64 base, size;
 148 };
 149
 150 static int __init rcar_gen2_scan_mem(unsigned long node, const char *uname,
 151                                      int depth, void *data)
 152 {
 153         const char *type = of_get_flat_dt_prop(node, "device_type", NULL);
 154         const __be32 *reg, *endp;
 155         int l;
 156         struct memory_reserve_config *mrc = data;
 157         u64 lpae_start = 1ULL << 32;
 158
 159         /* We are scanning "memory" nodes only */
 160         if (type == NULL || strcmp(type, "memory"))
 161                 return 0;
 162
 163         reg = of_get_flat_dt_prop(node, "linux,usable-memory", &l);
 164         if (reg == NULL)
 165                 reg = of_get_flat_dt_prop(node, "reg", &l);
 166         if (reg == NULL)
 167                 return 0;
 168
 169         endp = reg + (l / sizeof(__be32));
 170         while ((endp - reg) >= (dt_root_addr_cells + dt_root_size_cells)) {
 171                 u64 base, size;
 172
 173                 base = dt_mem_next_cell(dt_root_addr_cells, &reg);
 174                 size = dt_mem_next_cell(dt_root_size_cells, &reg);
 175
 176                 if (base >= lpae_start)
 177                         continue;
 178
 179                 if ((base + size) >= lpae_start)
 180                         size = lpae_start - base;
 181
 182                 if (size < mrc->reserved)
 183                         continue;
 184
 185                 if (base < mrc->base)
 186                         continue;
 187
 188                 /* keep the area at top near the 32-bit legacy limit */
 189                 mrc->base = base + size - mrc->reserved;
 190                 mrc->size = mrc->reserved;
 191         }
 192
 193         return 0;
 194 }
 195
 196 struct cma *rcar_gen2_dma_contiguous;
 197
 198 void __init rcar_gen2_reserve(void)
 199 {
 200         struct memory_reserve_config mrc;
 201
 202         /* reserve 256 MiB at the top of the physical legacy 32-bit space */
 203         memset(&mrc, 0, sizeof(mrc));
 204         mrc.reserved = SZ_256M;
 205
 206         of_scan_flat_dt(rcar_gen2_scan_mem, &mrc);
 207 #ifdef CONFIG_DMA_CMA
 208         if (mrc.size)
 209                 dma_contiguous_reserve_area(mrc.size, mrc.base, 0,
 210                                             &rcar_gen2_dma_contiguous, true);
 211 #endif
 212 }