2 * Freescale eSDHC controller driver.
4 * Copyright (c) 2007, 2010, 2012 Freescale Semiconductor, Inc.
5 * Copyright (c) 2009 MontaVista Software, Inc.
7 * Authors: Xiaobo Xie <X.Xie@freescale.com>
8 * Anton Vorontsov <avorontsov@ru.mvista.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/err.h>
19 #include <linux/delay.h>
20 #include <linux/module.h>
21 #include <linux/mmc/host.h>
22 #include "sdhci-pltfm.h"
23 #include "sdhci-esdhc.h"
25 #define VENDOR_V_22 0x12
26 #define VENDOR_V_23 0x13
27 static u32
esdhc_readl(struct sdhci_host
*host
, int reg
)
31 ret
= in_be32(host
->ioaddr
+ reg
);
33 * The bit of ADMA flag in eSDHC is not compatible with standard
34 * SDHC register, so set fake flag SDHCI_CAN_DO_ADMA2 when ADMA is
36 * And for many FSL eSDHC controller, the reset value of field
37 * SDHCI_CAN_DO_ADMA1 is one, but some of them can't support ADMA,
38 * only these vendor version is greater than 2.2/0x12 support ADMA.
39 * For FSL eSDHC, must aligned 4-byte, so use 0xFC to read the
40 * the verdor version number, oxFE is SDHCI_HOST_VERSION.
42 if ((reg
== SDHCI_CAPABILITIES
) && (ret
& SDHCI_CAN_DO_ADMA1
)) {
43 u32 tmp
= in_be32(host
->ioaddr
+ SDHCI_SLOT_INT_STATUS
);
44 tmp
= (tmp
& SDHCI_VENDOR_VER_MASK
) >> SDHCI_VENDOR_VER_SHIFT
;
45 if (tmp
> VENDOR_V_22
)
46 ret
|= SDHCI_CAN_DO_ADMA2
;
52 static u16
esdhc_readw(struct sdhci_host
*host
, int reg
)
55 int base
= reg
& ~0x3;
56 int shift
= (reg
& 0x2) * 8;
58 if (unlikely(reg
== SDHCI_HOST_VERSION
))
59 ret
= in_be32(host
->ioaddr
+ base
) & 0xffff;
61 ret
= (in_be32(host
->ioaddr
+ base
) >> shift
) & 0xffff;
65 static u8
esdhc_readb(struct sdhci_host
*host
, int reg
)
67 int base
= reg
& ~0x3;
68 int shift
= (reg
& 0x3) * 8;
69 u8 ret
= (in_be32(host
->ioaddr
+ base
) >> shift
) & 0xff;
72 * "DMA select" locates at offset 0x28 in SD specification, but on
73 * P5020 or P3041, it locates at 0x29.
75 if (reg
== SDHCI_HOST_CONTROL
) {
78 dma_bits
= in_be32(host
->ioaddr
+ reg
);
79 /* DMA select is 22,23 bits in Protocol Control Register */
80 dma_bits
= (dma_bits
>> 5) & SDHCI_CTRL_DMA_MASK
;
82 /* fixup the result */
83 ret
&= ~SDHCI_CTRL_DMA_MASK
;
90 static void esdhc_writel(struct sdhci_host
*host
, u32 val
, int reg
)
93 * Enable IRQSTATEN[BGESEN] is just to set IRQSTAT[BGE]
94 * when SYSCTL[RSTD]) is set for some special operations.
95 * No any impact other operation.
97 if (reg
== SDHCI_INT_ENABLE
)
98 val
|= SDHCI_INT_BLK_GAP
;
99 sdhci_be32bs_writel(host
, val
, reg
);
102 static void esdhc_writew(struct sdhci_host
*host
, u16 val
, int reg
)
104 if (reg
== SDHCI_BLOCK_SIZE
) {
106 * Two last DMA bits are reserved, and first one is used for
107 * non-standard blksz of 4096 bytes that we don't support
108 * yet. So clear the DMA boundary bits.
110 val
&= ~SDHCI_MAKE_BLKSZ(0x7, 0);
112 sdhci_be32bs_writew(host
, val
, reg
);
115 static void esdhc_writeb(struct sdhci_host
*host
, u8 val
, int reg
)
118 * "DMA select" location is offset 0x28 in SD specification, but on
119 * P5020 or P3041, it's located at 0x29.
121 if (reg
== SDHCI_HOST_CONTROL
) {
125 * If host control register is not standard, exit
128 if (host
->quirks2
& SDHCI_QUIRK2_BROKEN_HOST_CONTROL
)
131 /* DMA select is 22,23 bits in Protocol Control Register */
132 dma_bits
= (val
& SDHCI_CTRL_DMA_MASK
) << 5;
133 clrsetbits_be32(host
->ioaddr
+ reg
, SDHCI_CTRL_DMA_MASK
<< 5,
135 val
&= ~SDHCI_CTRL_DMA_MASK
;
136 val
|= in_be32(host
->ioaddr
+ reg
) & SDHCI_CTRL_DMA_MASK
;
139 /* Prevent SDHCI core from writing reserved bits (e.g. HISPD). */
140 if (reg
== SDHCI_HOST_CONTROL
)
141 val
&= ~ESDHC_HOST_CONTROL_RES
;
142 sdhci_be32bs_writeb(host
, val
, reg
);
146 * For Abort or Suspend after Stop at Block Gap, ignore the ADMA
147 * error(IRQSTAT[ADMAE]) if both Transfer Complete(IRQSTAT[TC])
148 * and Block Gap Event(IRQSTAT[BGE]) are also set.
149 * For Continue, apply soft reset for data(SYSCTL[RSTD]);
150 * and re-issue the entire read transaction from beginning.
152 static void esdhci_of_adma_workaround(struct sdhci_host
*host
, u32 intmask
)
159 tmp
= in_be32(host
->ioaddr
+ SDHCI_SLOT_INT_STATUS
);
160 tmp
= (tmp
& SDHCI_VENDOR_VER_MASK
) >> SDHCI_VENDOR_VER_SHIFT
;
162 applicable
= (intmask
& SDHCI_INT_DATA_END
) &&
163 (intmask
& SDHCI_INT_BLK_GAP
) &&
164 (tmp
== VENDOR_V_23
);
168 host
->data
->error
= 0;
169 dmastart
= sg_dma_address(host
->data
->sg
);
170 dmanow
= dmastart
+ host
->data
->bytes_xfered
;
172 * Force update to the next DMA block boundary.
174 dmanow
= (dmanow
& ~(SDHCI_DEFAULT_BOUNDARY_SIZE
- 1)) +
175 SDHCI_DEFAULT_BOUNDARY_SIZE
;
176 host
->data
->bytes_xfered
= dmanow
- dmastart
;
177 sdhci_writel(host
, dmanow
, SDHCI_DMA_ADDRESS
);
180 static int esdhc_of_enable_dma(struct sdhci_host
*host
)
182 setbits32(host
->ioaddr
+ ESDHC_DMA_SYSCTL
, ESDHC_DMA_SNOOP
);
186 static unsigned int esdhc_of_get_max_clock(struct sdhci_host
*host
)
188 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
190 return pltfm_host
->clock
;
193 static unsigned int esdhc_of_get_min_clock(struct sdhci_host
*host
)
195 struct sdhci_pltfm_host
*pltfm_host
= sdhci_priv(host
);
197 return pltfm_host
->clock
/ 256 / 16;
200 static void esdhc_of_set_clock(struct sdhci_host
*host
, unsigned int clock
)
206 host
->mmc
->actual_clock
= 0;
211 /* Workaround to start pre_div at 2 for VNN < VENDOR_V_23 */
212 temp
= esdhc_readw(host
, SDHCI_HOST_VERSION
);
213 temp
= (temp
& SDHCI_VENDOR_VER_MASK
) >> SDHCI_VENDOR_VER_SHIFT
;
214 if (temp
< VENDOR_V_23
)
217 /* Workaround to reduce the clock frequency for p1010 esdhc */
218 if (of_find_compatible_node(NULL
, NULL
, "fsl,p1010-esdhc")) {
219 if (clock
> 20000000)
221 if (clock
> 40000000)
225 temp
= sdhci_readl(host
, ESDHC_SYSTEM_CONTROL
);
226 temp
&= ~(ESDHC_CLOCK_IPGEN
| ESDHC_CLOCK_HCKEN
| ESDHC_CLOCK_PEREN
228 sdhci_writel(host
, temp
, ESDHC_SYSTEM_CONTROL
);
230 while (host
->max_clk
/ pre_div
/ 16 > clock
&& pre_div
< 256)
233 while (host
->max_clk
/ pre_div
/ div
> clock
&& div
< 16)
236 dev_dbg(mmc_dev(host
->mmc
), "desired SD clock: %d, actual: %d\n",
237 clock
, host
->max_clk
/ pre_div
/ div
);
238 host
->mmc
->actual_clock
= host
->max_clk
/ pre_div
/ div
;
242 temp
= sdhci_readl(host
, ESDHC_SYSTEM_CONTROL
);
243 temp
|= (ESDHC_CLOCK_IPGEN
| ESDHC_CLOCK_HCKEN
| ESDHC_CLOCK_PEREN
244 | (div
<< ESDHC_DIVIDER_SHIFT
)
245 | (pre_div
<< ESDHC_PREDIV_SHIFT
));
246 sdhci_writel(host
, temp
, ESDHC_SYSTEM_CONTROL
);
250 static void esdhc_of_platform_init(struct sdhci_host
*host
)
254 vvn
= in_be32(host
->ioaddr
+ SDHCI_SLOT_INT_STATUS
);
255 vvn
= (vvn
& SDHCI_VENDOR_VER_MASK
) >> SDHCI_VENDOR_VER_SHIFT
;
256 if (vvn
== VENDOR_V_22
)
257 host
->quirks2
|= SDHCI_QUIRK2_HOST_NO_CMD23
;
259 if (vvn
> VENDOR_V_22
)
260 host
->quirks
&= ~SDHCI_QUIRK_NO_BUSY_IRQ
;
263 static void esdhc_pltfm_set_bus_width(struct sdhci_host
*host
, int width
)
268 case MMC_BUS_WIDTH_8
:
269 ctrl
= ESDHC_CTRL_8BITBUS
;
272 case MMC_BUS_WIDTH_4
:
273 ctrl
= ESDHC_CTRL_4BITBUS
;
281 clrsetbits_be32(host
->ioaddr
+ SDHCI_HOST_CONTROL
,
282 ESDHC_CTRL_BUSWIDTH_MASK
, ctrl
);
285 static void esdhc_reset(struct sdhci_host
*host
, u8 mask
)
287 sdhci_reset(host
, mask
);
289 sdhci_writel(host
, host
->ier
, SDHCI_INT_ENABLE
);
290 sdhci_writel(host
, host
->ier
, SDHCI_SIGNAL_ENABLE
);
293 static const struct sdhci_ops sdhci_esdhc_ops
= {
294 .read_l
= esdhc_readl
,
295 .read_w
= esdhc_readw
,
296 .read_b
= esdhc_readb
,
297 .write_l
= esdhc_writel
,
298 .write_w
= esdhc_writew
,
299 .write_b
= esdhc_writeb
,
300 .set_clock
= esdhc_of_set_clock
,
301 .enable_dma
= esdhc_of_enable_dma
,
302 .get_max_clock
= esdhc_of_get_max_clock
,
303 .get_min_clock
= esdhc_of_get_min_clock
,
304 .platform_init
= esdhc_of_platform_init
,
305 .adma_workaround
= esdhci_of_adma_workaround
,
306 .set_bus_width
= esdhc_pltfm_set_bus_width
,
307 .reset
= esdhc_reset
,
308 .set_uhs_signaling
= sdhci_set_uhs_signaling
,
313 static u32 esdhc_proctl
;
314 static int esdhc_of_suspend(struct device
*dev
)
316 struct sdhci_host
*host
= dev_get_drvdata(dev
);
318 esdhc_proctl
= sdhci_be32bs_readl(host
, SDHCI_HOST_CONTROL
);
320 return sdhci_suspend_host(host
);
323 static int esdhc_of_resume(struct device
*dev
)
325 struct sdhci_host
*host
= dev_get_drvdata(dev
);
326 int ret
= sdhci_resume_host(host
);
329 /* Isn't this already done by sdhci_resume_host() ? --rmk */
330 esdhc_of_enable_dma(host
);
331 sdhci_be32bs_writel(host
, esdhc_proctl
, SDHCI_HOST_CONTROL
);
337 static const struct dev_pm_ops esdhc_pmops
= {
338 .suspend
= esdhc_of_suspend
,
339 .resume
= esdhc_of_resume
,
341 #define ESDHC_PMOPS (&esdhc_pmops)
343 #define ESDHC_PMOPS NULL
346 static const struct sdhci_pltfm_data sdhci_esdhc_pdata
= {
348 * card detection could be handled via GPIO
349 * eSDHC cannot support End Attribute in NOP ADMA descriptor
351 .quirks
= ESDHC_DEFAULT_QUIRKS
| SDHCI_QUIRK_BROKEN_CARD_DETECTION
352 | SDHCI_QUIRK_NO_CARD_NO_RESET
353 | SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC
,
354 .ops
= &sdhci_esdhc_ops
,
357 static int sdhci_esdhc_probe(struct platform_device
*pdev
)
359 struct sdhci_host
*host
;
360 struct device_node
*np
;
363 host
= sdhci_pltfm_init(pdev
, &sdhci_esdhc_pdata
, 0);
365 return PTR_ERR(host
);
367 sdhci_get_of_property(pdev
);
369 np
= pdev
->dev
.of_node
;
370 if (of_device_is_compatible(np
, "fsl,p5040-esdhc") ||
371 of_device_is_compatible(np
, "fsl,p5020-esdhc") ||
372 of_device_is_compatible(np
, "fsl,p4080-esdhc") ||
373 of_device_is_compatible(np
, "fsl,p1020-esdhc") ||
374 of_device_is_compatible(np
, "fsl,t1040-esdhc"))
375 host
->quirks
&= ~SDHCI_QUIRK_BROKEN_CARD_DETECTION
;
377 if (of_device_is_compatible(np
, "fsl,p2020-esdhc")) {
379 * Freescale messed up with P2020 as it has a non-standard
380 * host control register
382 host
->quirks2
|= SDHCI_QUIRK2_BROKEN_HOST_CONTROL
;
385 /* call to generic mmc_of_parse to support additional capabilities */
386 ret
= mmc_of_parse(host
->mmc
);
390 mmc_of_parse_voltage(np
, &host
->ocr_mask
);
392 ret
= sdhci_add_host(host
);
398 sdhci_pltfm_free(pdev
);
402 static const struct of_device_id sdhci_esdhc_of_match
[] = {
403 { .compatible
= "fsl,mpc8379-esdhc" },
404 { .compatible
= "fsl,mpc8536-esdhc" },
405 { .compatible
= "fsl,esdhc" },
408 MODULE_DEVICE_TABLE(of
, sdhci_esdhc_of_match
);
410 static struct platform_driver sdhci_esdhc_driver
= {
412 .name
= "sdhci-esdhc",
413 .of_match_table
= sdhci_esdhc_of_match
,
416 .probe
= sdhci_esdhc_probe
,
417 .remove
= sdhci_pltfm_unregister
,
420 module_platform_driver(sdhci_esdhc_driver
);
422 MODULE_DESCRIPTION("SDHCI OF driver for Freescale MPC eSDHC");
423 MODULE_AUTHOR("Xiaobo Xie <X.Xie@freescale.com>, "
424 "Anton Vorontsov <avorontsov@ru.mvista.com>");
425 MODULE_LICENSE("GPL v2");