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video: Kconfig: move drm and fb into separate menus
[linux-2.6/btrfs-unstable.git] / drivers / staging / rtl8187se / r8185b_init.c
blobcc6f100814f333b56a7e0740c3ee568856116fb6
1 /*
2 * Copyright (c) Realtek Semiconductor Corp. All rights reserved.
3 *
4 * Module Name:
5 * r8185b_init.c
6 *
7 * Abstract:
8 * Hardware Initialization and Hardware IO for RTL8185B
9 *
10 * Major Change History:
11 * When Who What
12 * ---------- --------------- -------------------------------
13 * 2006-11-15 Xiong Created
14 *
15 * Notes:
16 * This file is ported from RTL8185B Windows driver.
17 *
18 *
19 */
20
21 /*--------------------------Include File------------------------------------*/
22 #include <linux/spinlock.h>
23 #include "r8180_hw.h"
24 #include "r8180.h"
25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
26 #include "r8180_93cx6.h" /* Card EEPROM */
27 #include "r8180_wx.h"
28 #include "ieee80211/dot11d.h"
29 /* #define CONFIG_RTL8180_IO_MAP */
30 #define TC_3W_POLL_MAX_TRY_CNT 5
31
32 static u8 MAC_REG_TABLE[][2] = {
33 /*
34 * PAGE 0:
35 * 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in
36 * HwConfigureRTL8185()
37 * 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
38 * 0x1F0~0x1F8 set in MacConfig_85BASIC()
39 */
40 {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
41 {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
42 {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
43 {0x94, 0x0F}, {0x95, 0x32},
44 {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
45 {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
46 {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
47 {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
48 {0xff, 0x00},
49
50 /*
51 * PAGE 1:
52 * For Flextronics system Logo PCIHCT failure:
53 * 0x1C4~0x1CD set no-zero value to avoid PCI configuration
54 * space 0x45[7]=1
55 */
56 {0x5e, 0x01},
57 {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
58 {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
59 {0x82, 0xFF}, {0x83, 0x03},
60 /* lzm add 080826 */
61 {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22},
62 /* lzm add 080826 */
63 {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},
64 {0xe2, 0x00},
65
66
67 /* PAGE 2: */
68 {0x5e, 0x02},
69 {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
70 {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
71 {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
72 {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
73 {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
74 {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
75 {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
76
77 /* PAGE 0: */
78 {0x5e, 0x00}, {0x9f, 0x03}
79 };
80
81
82 static u8 ZEBRA_AGC[] = {
83 0,
84 0x7E, 0x7E, 0x7E, 0x7E, 0x7D, 0x7C, 0x7B, 0x7A, 0x79, 0x78, 0x77, 0x76,
85 0x75, 0x74, 0x73, 0x72, 0x71, 0x70, 0x6F, 0x6E, 0x6D, 0x6C, 0x6B, 0x6A,
86 0x69, 0x68, 0x67, 0x66, 0x65, 0x64, 0x63, 0x62, 0x48, 0x47, 0x46, 0x45,
87 0x44, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24, 0x23, 0x22, 0x21, 0x08, 0x07,
88 0x06, 0x05, 0x04, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
89 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f, 0x0f,
90 0x0f, 0x0f, 0x10, 0x11, 0x12, 0x13, 0x15, 0x16, 0x17, 0x17, 0x18, 0x18,
91 0x19, 0x1a, 0x1a, 0x1b, 0x1b, 0x1c, 0x1c, 0x1d, 0x1d, 0x1d, 0x1e, 0x1e,
92 0x1f, 0x1f, 0x1f, 0x20, 0x20, 0x20, 0x20, 0x21, 0x21, 0x21, 0x22, 0x22,
93 0x22, 0x23, 0x23, 0x24, 0x24, 0x25, 0x25, 0x25, 0x26, 0x26, 0x27, 0x27,
94 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F, 0x2F
95 };
96
97 static u32 ZEBRA_RF_RX_GAIN_TABLE[] = {
98 0x0096, 0x0076, 0x0056, 0x0036, 0x0016, 0x01f6, 0x01d6, 0x01b6,
99 0x0196, 0x0176, 0x00F7, 0x00D7, 0x00B7, 0x0097, 0x0077, 0x0057,
100 0x0037, 0x00FB, 0x00DB, 0x00BB, 0x00FF, 0x00E3, 0x00C3, 0x00A3,
101 0x0083, 0x0063, 0x0043, 0x0023, 0x0003, 0x01E3, 0x01C3, 0x01A3,
102 0x0183, 0x0163, 0x0143, 0x0123, 0x0103
103 };
104
105 static u8 OFDM_CONFIG[] = {
106 /* OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX */
107 /* OFDM reg0x3C[4]=1'b1: Enable RX power saving mode */
108 /* ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test */
109 /* 0x00 */
110 0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
111 0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
112 /* 0x10 */
113 0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
114 0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
115 /* 0x20 */
116 0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
117 0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
118 /* 0x30 */
119 0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
120 0xD8, 0x3C, 0x7B, 0x10, 0x10
121 };
122
123 /*---------------------------------------------------------------
124 * Hardware IO
125 * the code is ported from Windows source code
126 *---------------------------------------------------------------
127 */
128
129 static u8 PlatformIORead1Byte(struct net_device *dev, u32 offset)
130 {
131 return read_nic_byte(dev, offset);
132 }
133
134 static void PlatformIOWrite1Byte(struct net_device *dev, u32 offset, u8 data)
135 {
136 write_nic_byte(dev, offset, data);
137 /*
138 * To make sure write operation is completed,
139 * 2005.11.09, by rcnjko.
140 */
141 read_nic_byte(dev, offset);
142 }
143
144 static void PlatformIOWrite2Byte(struct net_device *dev, u32 offset, u16 data)
145 {
146 write_nic_word(dev, offset, data);
147 /*
148 * To make sure write operation is completed,
149 * 2005.11.09, by rcnjko.
150 */
151 read_nic_word(dev, offset);
152 }
153
154 static void PlatformIOWrite4Byte(struct net_device *dev, u32 offset, u32 data)
155 {
156 if (offset == PhyAddr) {
157 /* For Base Band configuration. */
158 unsigned char cmdByte;
159 unsigned long dataBytes;
160 unsigned char idx;
161 u8 u1bTmp;
162
163 cmdByte = (u8)(data & 0x000000ff);
164 dataBytes = data>>8;
165
166 /*
167 * 071010, rcnjko:
168 * The critical section is only BB read/write race
169 * condition. Assumption:
170 * 1. We assume NO one will access BB at DIRQL, otherwise,
171 * system will crash for
172 * acquiring the spinlock in such context.
173 * 2. PlatformIOWrite4Byte() MUST NOT be recursive.
174 */
175 /* NdisAcquireSpinLock( &(pDevice->IoSpinLock) ); */
176
177 for (idx = 0; idx < 30; idx++) {
178 /* Make sure command bit is clear before access it. */
179 u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
180 if ((u1bTmp & BIT7) == 0)
181 break;
182 else
183 mdelay(10);
184 }
185
186 for (idx = 0; idx < 3; idx++)
187 PlatformIOWrite1Byte(dev, offset+1+idx,
188 ((u8 *)&dataBytes)[idx]);
189
190 write_nic_byte(dev, offset, cmdByte);
191
192 /* NdisReleaseSpinLock( &(pDevice->IoSpinLock) ); */
193 } else {
194 write_nic_dword(dev, offset, data);
195 /*
196 * To make sure write operation is completed, 2005.11.09,
197 * by rcnjko.
198 */
199 read_nic_dword(dev, offset);
200 }
201 }
202
203 static void SetOutputEnableOfRfPins(struct net_device *dev)
204 {
205 write_nic_word(dev, RFPinsEnable, 0x1bff);
206 }
207
208 static bool HwHSSIThreeWire(struct net_device *dev,
209 u8 *pDataBuf,
210 bool write)
211 {
212 u8 TryCnt;
213 u8 u1bTmp;
214
215 /* Check if WE and RE are cleared. */
216 for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
217 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
218 if ((u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0)
219 break;
220
221 udelay(10);
222 }
223 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT) {
224 netdev_err(dev,
225 "HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n",
226 u1bTmp);
227 return false;
228 }
229
230 /* RTL8187S HSSI Read/Write Function */
231 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
232 u1bTmp |= RF_SW_CFG_SI; /* reg08[1]=1 Serial Interface(SI) */
233 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
234
235 /* jong: HW SI read must set reg84[3]=0. */
236 u1bTmp = read_nic_byte(dev, RFPinsSelect);
237 u1bTmp &= ~BIT3;
238 write_nic_byte(dev, RFPinsSelect, u1bTmp);
239 /* Fill up data buffer for write operation. */
240
241 /* SI - reg274[3:0] : RF register's Address */
242 if (write)
243 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
244 else
245 write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
246
247 /* Set up command: WE or RE. */
248 if (write)
249 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
250 else
251 write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
252
253
254 /* Check if DONE is set. */
255 for (TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++) {
256 u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
257 if (u1bTmp & SW_3W_CMD1_DONE)
258 break;
259
260 udelay(10);
261 }
262
263 write_nic_byte(dev, SW_3W_CMD1, 0);
264
265 /* Read back data for read operation. */
266 if (!write) {
267 /* Serial Interface : reg363_362[11:0] */
268 *((u16 *)pDataBuf) = read_nic_word(dev, SI_DATA_READ);
269 *((u16 *)pDataBuf) &= 0x0FFF;
270 }
271
272 return true;
273 }
274
275 void RF_WriteReg(struct net_device *dev, u8 offset, u16 data)
276 {
277 u16 reg = (data << 4) | (offset & 0x0f);
278 HwHSSIThreeWire(dev, (u8 *)&reg, true);
279 }
280
281 u16 RF_ReadReg(struct net_device *dev, u8 offset)
282 {
283 u16 reg = offset & 0x0f;
284 HwHSSIThreeWire(dev, (u8 *)&reg, false);
285 return reg;
286 }
287
288 static u8 ReadBBPortUchar(struct net_device *dev, u32 addr)
289 {
290 PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
291 return PlatformIORead1Byte(dev, PhyDataR);
292 }
293
294 /* by Owen on 04/07/14 for writing BB register successfully */
295 static void WriteBBPortUchar(struct net_device *dev, u32 Data)
296 {
297 PlatformIOWrite4Byte(dev, PhyAddr, Data);
298 ReadBBPortUchar(dev, Data);
299 }
300
301 /*
302 * Description:
303 * Perform Antenna settings with antenna diversity on 87SE.
304 * Created by Roger, 2008.01.25.
305 */
306 bool SetAntennaConfig87SE(struct net_device *dev,
307 u8 DefaultAnt, /* 0: Main, 1: Aux. */
308 bool bAntDiversity) /* 1:Enable, 0: Disable. */
309 {
310 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
311 bool bAntennaSwitched = true;
312 /* 0x00 = disabled, 0x80 = enabled */
313 u8 ant_diversity_offset = 0x00;
314
315 /*
316 * printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n",
317 * DefaultAnt, bAntDiversity);
318 */
319
320 /* Threshold for antenna diversity. */
321 write_phy_cck(dev, 0x0c, 0x09); /* Reg0c : 09 */
322
323 if (bAntDiversity) /* Enable Antenna Diversity. */
324 ant_diversity_offset = 0x80;
325
326 if (DefaultAnt == 1) { /* aux Antenna */
327 /* Mac register, aux antenna */
328 write_nic_byte(dev, ANTSEL, 0x00);
329
330 /* Config CCK RX antenna. */
331 write_phy_cck(dev, 0x11, 0xbb); /* Reg11 : bb */
332
333 /* Reg01 : 47 | ant_diversity_offset */
334 write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset);
335
336 /* Config OFDM RX antenna. */
337 write_phy_ofdm(dev, 0x0D, 0x54); /* Reg0d : 54 */
338 /* Reg18 : 32 */
339 write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset);
340 } else { /* main Antenna */
341 /* Mac register, main antenna */
342 write_nic_byte(dev, ANTSEL, 0x03);
343
344 /* Config CCK RX antenna. */
345 write_phy_cck(dev, 0x11, 0x9b); /* Reg11 : 9b */
346 /* Reg01 : 47 */
347 write_phy_cck(dev, 0x01, 0x47|ant_diversity_offset);
348
349 /* Config OFDM RX antenna. */
350 write_phy_ofdm(dev, 0x0D, 0x5c); /* Reg0d : 5c */
351 /*Reg18 : 32 */
352 write_phy_ofdm(dev, 0x18, 0x32|ant_diversity_offset);
353 }
354 priv->CurrAntennaIndex = DefaultAnt; /* Update default settings. */
355 return bAntennaSwitched;
356 }
357 /*
358 *--------------------------------------------------------------
359 * Hardware Initialization.
360 * the code is ported from Windows source code
361 *--------------------------------------------------------------
362 */
363
364 static void ZEBRA_Config_85BASIC_HardCode(struct net_device *dev)
365 {
366
367 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
368 u32 i;
369 u32 addr, data;
370 u32 u4bRegOffset, u4bRegValue;
371 u16 u4bRF23, u4bRF24;
372 u8 u1b24E;
373 int d_cut = 0;
374
375
376 /*
377 *===========================================================================
378 * 87S_PCIE :: RADIOCFG.TXT
379 *===========================================================================
380 */
381
382
383 /* Page1 : reg16-reg30 */
384 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1); /* switch to page1 */
385 u4bRF23 = RF_ReadReg(dev, 0x08); mdelay(1);
386 u4bRF24 = RF_ReadReg(dev, 0x09); mdelay(1);
387
388 if (u4bRF23 == 0x818 && u4bRF24 == 0x70C) {
389 d_cut = 1;
390 netdev_info(dev, "card type changed from C- to D-cut\n");
391 }
392
393 /* Page0 : reg0-reg15 */
394
395 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);/* 1 */
396 RF_WriteReg(dev, 0x01, 0x06e0); mdelay(1);
397 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);/* 2 */
398 RF_WriteReg(dev, 0x03, 0x07f1); mdelay(1);/* 3 */
399 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1);
400 RF_WriteReg(dev, 0x05, 0x0c72); mdelay(1);
401 RF_WriteReg(dev, 0x06, 0x0ae6); mdelay(1);
402 RF_WriteReg(dev, 0x07, 0x00ca); mdelay(1);
403 RF_WriteReg(dev, 0x08, 0x0e1c); mdelay(1);
404 RF_WriteReg(dev, 0x09, 0x02f0); mdelay(1);
405 RF_WriteReg(dev, 0x0a, 0x09d0); mdelay(1);
406 RF_WriteReg(dev, 0x0b, 0x01ba); mdelay(1);
407 RF_WriteReg(dev, 0x0c, 0x0640); mdelay(1);
408 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
409 RF_WriteReg(dev, 0x0e, 0x0020); mdelay(1);
410 RF_WriteReg(dev, 0x0f, 0x0990); mdelay(1);
411
412 /* Page1 : reg16-reg30 */
413 RF_WriteReg(dev, 0x00, 0x013f); mdelay(1);
414 RF_WriteReg(dev, 0x03, 0x0806); mdelay(1);
415 RF_WriteReg(dev, 0x04, 0x03a7); mdelay(1);
416 RF_WriteReg(dev, 0x05, 0x059b); mdelay(1);
417 RF_WriteReg(dev, 0x06, 0x0081); mdelay(1);
418 RF_WriteReg(dev, 0x07, 0x01A0); mdelay(1);
419 /*
420 * Don't write RF23/RF24 to make a difference between 87S C cut and D cut.
421 * asked by SD3 stevenl.
422 */
423 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
424 RF_WriteReg(dev, 0x0b, 0x0418); mdelay(1);
425
426 if (d_cut) {
427 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
428 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
429 /* RX LO buffer */
430 RF_WriteReg(dev, 0x0e, 0x0807); mdelay(1);
431 } else {
432 RF_WriteReg(dev, 0x0c, 0x0fbe); mdelay(1);
433 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
434 /* RX LO buffer */
435 RF_WriteReg(dev, 0x0e, 0x0806); mdelay(1);
436 }
437
438 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
439 RF_WriteReg(dev, 0x00, 0x01d7); mdelay(1); /* 6 */
440 RF_WriteReg(dev, 0x03, 0x0e00); mdelay(1);
441 RF_WriteReg(dev, 0x04, 0x0e50); mdelay(1);
442
443 for (i = 0; i <= 36; i++) {
444 RF_WriteReg(dev, 0x01, i); mdelay(1);
445 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
446 }
447
448 RF_WriteReg(dev, 0x05, 0x0203); mdelay(1); /* 203, 343 */
449 RF_WriteReg(dev, 0x06, 0x0200); mdelay(1); /* 400 */
450 /* switch to reg16-reg30, and HSSI disable 137 */
451 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1);
452 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
453
454 /* Z4 synthesizer loop filter setting, 392 */
455 RF_WriteReg(dev, 0x0d, 0x0008); mdelay(1);
456 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
457
458 /* switch to reg0-reg15, and HSSI disable */
459 RF_WriteReg(dev, 0x00, 0x0037); mdelay(1);
460 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
461
462 /* CBC on, Tx Rx disable, High gain */
463 RF_WriteReg(dev, 0x04, 0x0160); mdelay(1);
464 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
465
466 /* Z4 setted channel 1 */
467 RF_WriteReg(dev, 0x07, 0x0080); mdelay(1);
468 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
469
470 RF_WriteReg(dev, 0x02, 0x088D); mdelay(1); /* LC calibration */
471 mdelay(200); /* Deay 200 ms. */ /* 0xfd */
472 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
473 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
474
475 /* switch to reg16-reg30 137, and HSSI disable 137 */
476 RF_WriteReg(dev, 0x00, 0x0137); mdelay(1);
477 mdelay(10); /* Deay 10 ms. */ /* 0xfd */
478
479 RF_WriteReg(dev, 0x07, 0x0000); mdelay(1);
480 RF_WriteReg(dev, 0x07, 0x0180); mdelay(1);
481 RF_WriteReg(dev, 0x07, 0x0220); mdelay(1);
482 RF_WriteReg(dev, 0x07, 0x03E0); mdelay(1);
483
484 /* DAC calibration off 20070702 */
485 RF_WriteReg(dev, 0x06, 0x00c1); mdelay(1);
486 RF_WriteReg(dev, 0x0a, 0x0001); mdelay(1);
487 /* For crystal calibration, added by Roger, 2007.12.11. */
488 if (priv->bXtalCalibration) { /* reg 30. */
489 /*
490 * enable crystal calibration.
491 * RF Reg[30], (1)Xin:[12:9], Xout:[8:5], addr[4:0].
492 * (2)PA Pwr delay timer[15:14], default: 2.4us,
493 * set BIT15=0
494 * (3)RF signal on/off when calibration[13], default: on,
495 * set BIT13=0.
496 * So we should minus 4 BITs offset.
497 */
498 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5) |
499 (priv->XtalCal_Xout<<1) | BIT11 | BIT9); mdelay(1);
500 netdev_info(dev, "ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
501 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) |
502 BIT11 | BIT9);
503 } else {
504 /* using default value. Xin=6, Xout=6. */
505 RF_WriteReg(dev, 0x0f, 0x0acc); mdelay(1);
506 }
507 /* switch to reg0-reg15, and HSSI enable */
508 RF_WriteReg(dev, 0x00, 0x00bf); mdelay(1);
509 /* Rx BB start calibration, 00c//+edward */
510 RF_WriteReg(dev, 0x0d, 0x08df); mdelay(1);
511 /* temperature meter off */
512 RF_WriteReg(dev, 0x02, 0x004d); mdelay(1);
513 RF_WriteReg(dev, 0x04, 0x0975); mdelay(1); /* Rx mode */
514 mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
515 mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
516 mdelay(10); /* Deay 10 ms.*/ /* 0xfe */
517 /* Rx mode*/ /*+edward */
518 RF_WriteReg(dev, 0x00, 0x0197); mdelay(1);
519 /* Rx mode*/ /*+edward */
520 RF_WriteReg(dev, 0x05, 0x05ab); mdelay(1);
521 /* Rx mode*/ /*+edward */
522 RF_WriteReg(dev, 0x00, 0x009f); mdelay(1);
523 /* Rx mode*/ /*+edward */
524 RF_WriteReg(dev, 0x01, 0x0000); mdelay(1);
525 /* Rx mode*/ /*+edward */
526 RF_WriteReg(dev, 0x02, 0x0000); mdelay(1);
527 /* power save parameters. */
528 u1b24E = read_nic_byte(dev, 0x24E);
529 write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
530
531 /*======================================================================
532 *
533 *======================================================================
534 * CCKCONF.TXT
535 *======================================================================
536 *
537 * [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
538 * CCK reg0x00[7]=1'b1 :power saving for TX (default)
539 * CCK reg0x00[6]=1'b1: power saving for RX (default)
540 * CCK reg0x06[4]=1'b1: turn off channel estimation related
541 * circuits if not doing channel estimation.
542 * CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
543 * CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
544 */
545
546 write_phy_cck(dev, 0x00, 0xc8);
547 write_phy_cck(dev, 0x06, 0x1c);
548 write_phy_cck(dev, 0x10, 0x78);
549 write_phy_cck(dev, 0x2e, 0xd0);
550 write_phy_cck(dev, 0x2f, 0x06);
551 write_phy_cck(dev, 0x01, 0x46);
552
553 /* power control */
554 write_nic_byte(dev, CCK_TXAGC, 0x10);
555 write_nic_byte(dev, OFDM_TXAGC, 0x1B);
556 write_nic_byte(dev, ANTSEL, 0x03);
557
558
559
560 /*
561 *======================================================================
562 * AGC.txt
563 *======================================================================
564 */
565
566 write_phy_ofdm(dev, 0x00, 0x12);
567
568 for (i = 0; i < 128; i++) {
569
570 data = ZEBRA_AGC[i+1];
571 data = data << 8;
572 data = data | 0x0000008F;
573
574 addr = i + 0x80; /* enable writing AGC table */
575 addr = addr << 8;
576 addr = addr | 0x0000008E;
577
578 WriteBBPortUchar(dev, data);
579 WriteBBPortUchar(dev, addr);
580 WriteBBPortUchar(dev, 0x0000008E);
581 }
582
583 PlatformIOWrite4Byte(dev, PhyAddr, 0x00001080); /* Annie, 2006-05-05 */
584
585 /*
586 *======================================================================
587 *
588 *======================================================================
589 * OFDMCONF.TXT
590 *======================================================================
591 */
592
593 for (i = 0; i < 60; i++) {
594 u4bRegOffset = i;
595 u4bRegValue = OFDM_CONFIG[i];
596
597 WriteBBPortUchar(dev,
598 (0x00000080 |
599 (u4bRegOffset & 0x7f) |
600 ((u4bRegValue & 0xff) << 8)));
601 }
602
603 /*
604 *======================================================================
605 * by amy for antenna
606 *======================================================================
607 */
608 /*
609 * Config Sw/Hw Combinational Antenna Diversity. Added by Roger,
610 * 2008.02.26.
611 */
612 SetAntennaConfig87SE(dev, priv->bDefaultAntenna1,
613 priv->bSwAntennaDiverity);
614 }
615
616
617 void UpdateInitialGain(struct net_device *dev)
618 {
619 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
620
621 /* lzm add 080826 */
622 if (priv->eRFPowerState != RF_ON) {
623 /* Don't access BB/RF under disable PLL situation.
624 * RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain -
625 * pHalData->eRFPowerState!=RF_ON\n"));
626 * Back to the original state
627 */
628 priv->InitialGain = priv->InitialGainBackUp;
629 return;
630 }
631
632 switch (priv->InitialGain) {
633 case 1: /* m861dBm */
634 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
635 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
636 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
637 break;
638
639 case 2: /* m862dBm */
640 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
641 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
642 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
643 break;
644
645 case 3: /* m863dBm */
646 write_phy_ofdm(dev, 0x17, 0x36); mdelay(1);
647 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
648 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
649 break;
650
651 case 4: /* m864dBm */
652 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
653 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
654 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
655 break;
656
657 case 5: /* m82dBm */
658 write_phy_ofdm(dev, 0x17, 0x46); mdelay(1);
659 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
660 write_phy_ofdm(dev, 0x05, 0xfb); mdelay(1);
661 break;
662
663 case 6: /* m78dBm */
664 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
665 write_phy_ofdm(dev, 0x24, 0x96); mdelay(1);
666 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
667 break;
668
669 case 7: /* m74dBm */
670 write_phy_ofdm(dev, 0x17, 0x56); mdelay(1);
671 write_phy_ofdm(dev, 0x24, 0xa6); mdelay(1);
672 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
673 break;
674
675 case 8:
676 write_phy_ofdm(dev, 0x17, 0x66); mdelay(1);
677 write_phy_ofdm(dev, 0x24, 0xb6); mdelay(1);
678 write_phy_ofdm(dev, 0x05, 0xfc); mdelay(1);
679 break;
680
681 default: /* MP */
682 write_phy_ofdm(dev, 0x17, 0x26); mdelay(1);
683 write_phy_ofdm(dev, 0x24, 0x86); mdelay(1);
684 write_phy_ofdm(dev, 0x05, 0xfa); mdelay(1);
685 break;
686 }
687 }
688 /*
689 * Description:
690 * Tx Power tracking mechanism routine on 87SE.
691 * Created by Roger, 2007.12.11.
692 */
693 static void InitTxPwrTracking87SE(struct net_device *dev)
694 {
695 u32 u4bRfReg;
696
697 u4bRfReg = RF_ReadReg(dev, 0x02);
698
699 /* Enable Thermal meter indication. */
700 RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN); mdelay(1);
701 }
702
703 static void PhyConfig8185(struct net_device *dev)
704 {
705 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
706 write_nic_dword(dev, RCR, priv->ReceiveConfig);
707 priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
708 /* RF config */
709 ZEBRA_Config_85BASIC_HardCode(dev);
710 /* Set default initial gain state to 4, approved by SD3 DZ, by Bruce,
711 * 2007-06-06.
712 */
713 if (priv->bDigMechanism) {
714 if (priv->InitialGain == 0)
715 priv->InitialGain = 4;
716 }
717
718 /*
719 * Enable thermal meter indication to implement TxPower tracking
720 * on 87SE. We initialize thermal meter here to avoid unsuccessful
721 * configuration. Added by Roger, 2007.12.11.
722 */
723 if (priv->bTxPowerTrack)
724 InitTxPwrTracking87SE(dev);
725
726 priv->InitialGainBackUp = priv->InitialGain;
727 UpdateInitialGain(dev);
728
729 return;
730 }
731
732 static void HwConfigureRTL8185(struct net_device *dev)
733 {
734 /*
735 * RTL8185_TODO: Determine Retrylimit, TxAGC,
736 * AutoRateFallback control.
737 */
738 u8 bUNIVERSAL_CONTROL_RL = 0;
739 u8 bUNIVERSAL_CONTROL_AGC = 1;
740 u8 bUNIVERSAL_CONTROL_ANT = 1;
741 u8 bAUTO_RATE_FALLBACK_CTL = 1;
742 u8 val8;
743 write_nic_word(dev, BRSR, 0x0fff);
744 /* Retry limit */
745 val8 = read_nic_byte(dev, CW_CONF);
746
747 if (bUNIVERSAL_CONTROL_RL)
748 val8 = val8 & 0xfd;
749 else
750 val8 = val8 | 0x02;
751
752 write_nic_byte(dev, CW_CONF, val8);
753
754 /* Tx AGC */
755 val8 = read_nic_byte(dev, TXAGC_CTL);
756 if (bUNIVERSAL_CONTROL_AGC) {
757 write_nic_byte(dev, CCK_TXAGC, 128);
758 write_nic_byte(dev, OFDM_TXAGC, 128);
759 val8 = val8 & 0xfe;
760 } else {
761 val8 = val8 | 0x01;
762 }
763
764
765 write_nic_byte(dev, TXAGC_CTL, val8);
766
767 /* Tx Antenna including Feedback control */
768 val8 = read_nic_byte(dev, TXAGC_CTL);
769
770 if (bUNIVERSAL_CONTROL_ANT) {
771 write_nic_byte(dev, ANTSEL, 0x00);
772 val8 = val8 & 0xfd;
773 } else {
774 val8 = val8 & (val8|0x02); /* xiong-2006-11-15 */
775 }
776
777 write_nic_byte(dev, TXAGC_CTL, val8);
778
779 /* Auto Rate fallback control */
780 val8 = read_nic_byte(dev, RATE_FALLBACK);
781 val8 &= 0x7c;
782 if (bAUTO_RATE_FALLBACK_CTL) {
783 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
784
785 /* <RJ_TODO_8185B> We shall set up the ARFR according
786 * to user's setting.
787 */
788 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); /* set 1M ~ 54Mbps. */
789 }
790 write_nic_byte(dev, RATE_FALLBACK, val8);
791 }
792
793 static void MacConfig_85BASIC_HardCode(struct net_device *dev)
794 {
795 /*
796 *======================================================================
797 * MACREG.TXT
798 *======================================================================
799 */
800 int nLinesRead = 0;
801 u32 u4bRegOffset, u4bRegValue, u4bPageIndex = 0;
802 int i;
803
804 nLinesRead = sizeof(MAC_REG_TABLE)/2;
805
806 for (i = 0; i < nLinesRead; i++) { /* nLinesRead=101 */
807 u4bRegOffset = MAC_REG_TABLE[i][0];
808 u4bRegValue = MAC_REG_TABLE[i][1];
809
810 if (u4bRegOffset == 0x5e)
811 u4bPageIndex = u4bRegValue;
812 else
813 u4bRegOffset |= (u4bPageIndex << 8);
814
815 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
816 }
817 /* ================================================================= */
818 }
819
820 static void MacConfig_85BASIC(struct net_device *dev)
821 {
822
823 u8 u1DA;
824 MacConfig_85BASIC_HardCode(dev);
825
826 /* ================================================================= */
827
828 /* Follow TID_AC_MAP of WMac. */
829 write_nic_word(dev, TID_AC_MAP, 0xfa50);
830
831 /* Interrupt Migration, Jong suggested we use set 0x0000 first,
832 * 2005.12.14, by rcnjko.
833 */
834 write_nic_word(dev, IntMig, 0x0000);
835
836 /* Prevent TPC to cause CRC error. Added by Annie, 2006-06-10. */
837 PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
838 PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
839 PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
840
841 /* Asked for by SD3 CM Lin, 2006.06.27, by rcnjko. */
842
843 /*
844 * power save parameter based on
845 * "87SE power save parameters 20071127.doc", as follow.
846 */
847
848 /* Enable DA10 TX power saving */
849 u1DA = read_nic_byte(dev, PHYPR);
850 write_nic_byte(dev, PHYPR, (u1DA | BIT2));
851
852 /* POWER: */
853 write_nic_word(dev, 0x360, 0x1000);
854 write_nic_word(dev, 0x362, 0x1000);
855
856 /* AFE. */
857 write_nic_word(dev, 0x370, 0x0560);
858 write_nic_word(dev, 0x372, 0x0560);
859 write_nic_word(dev, 0x374, 0x0DA4);
860 write_nic_word(dev, 0x376, 0x0DA4);
861 write_nic_word(dev, 0x378, 0x0560);
862 write_nic_word(dev, 0x37A, 0x0560);
863 write_nic_word(dev, 0x37C, 0x00EC);
864 write_nic_word(dev, 0x37E, 0x00EC); /* +edward */
865 write_nic_byte(dev, 0x24E, 0x01);
866 }
867
868 static u8 GetSupportedWirelessMode8185(struct net_device *dev)
869 {
870 return WIRELESS_MODE_B | WIRELESS_MODE_G;
871 }
872
873 static void
874 ActUpdateChannelAccessSetting(struct net_device *dev,
875 enum wireless_mode mode,
876 struct chnl_access_setting *chnl_access_setting)
877 {
878 AC_CODING eACI;
879
880 /*
881 * <RJ_TODO_8185B>
882 * TODO: We still don't know how to set up these registers,
883 * just follow WMAC to verify 8185B FPAG.
884 *
885 * <RJ_TODO_8185B>
886 * Jong said CWmin/CWmax register are not functional in 8185B,
887 * so we shall fill channel access realted register into AC
888 * parameter registers,
889 * even in nQBss.
890 */
891
892 /* Suggested by Jong, 2005.12.08. */
893 chnl_access_setting->sifs_timer = 0x22;
894 chnl_access_setting->difs_timer = 0x1C; /* 2006.06.02, by rcnjko. */
895 chnl_access_setting->slot_time_timer = 9; /* 2006.06.02, by rcnjko. */
896 /*
897 * Suggested by wcchu, it is the default value of EIFS register,
898 * 2005.12.08.
899 */
900 chnl_access_setting->eifs_timer = 0x5B;
901 chnl_access_setting->cwmin_index = 3; /* 2006.06.02, by rcnjko. */
902 chnl_access_setting->cwmax_index = 7; /* 2006.06.02, by rcnjko. */
903
904 write_nic_byte(dev, SIFS, chnl_access_setting->sifs_timer);
905 /*
906 * Rewrited from directly use PlatformEFIOWrite1Byte(),
907 * by Annie, 2006-03-29.
908 */
909 write_nic_byte(dev, SLOT, chnl_access_setting->slot_time_timer);
910
911 write_nic_byte(dev, EIFS, chnl_access_setting->eifs_timer);
912
913 /*
914 * <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS
915 * register, 2005.12.08.
916 */
917 write_nic_byte(dev, AckTimeOutReg, 0x5B);
918
919 for (eACI = 0; eACI < AC_MAX; eACI++)
920 write_nic_byte(dev, ACM_CONTROL, 0);
921 }
922
923 static void ActSetWirelessMode8185(struct net_device *dev, u8 btWirelessMode)
924 {
925 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
926 struct ieee80211_device *ieee = priv->ieee80211;
927 u8 btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
928
929 if ((btWirelessMode & btSupportedWirelessMode) == 0) {
930 /*
931 * Don't switch to unsupported wireless mode, 2006.02.15,
932 * by rcnjko.
933 */
934 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
935 btWirelessMode, btSupportedWirelessMode);
936 return;
937 }
938
939 /* 1. Assign wireless mode to switch if necessary. */
940 if (btWirelessMode == WIRELESS_MODE_AUTO) {
941 if ((btSupportedWirelessMode & WIRELESS_MODE_A)) {
942 btWirelessMode = WIRELESS_MODE_A;
943 } else if (btSupportedWirelessMode & WIRELESS_MODE_G) {
944 btWirelessMode = WIRELESS_MODE_G;
945
946 } else if ((btSupportedWirelessMode & WIRELESS_MODE_B)) {
947 btWirelessMode = WIRELESS_MODE_B;
948 } else {
949 DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
950 btSupportedWirelessMode);
951 btWirelessMode = WIRELESS_MODE_B;
952 }
953 }
954
955 /*
956 * 2. Swtich band: RF or BB specific actions,
957 * for example, refresh tables in omc8255, or change initial gain if
958 * necessary. Nothing to do for Zebra to switch band. Update current
959 * wireless mode if we switch to specified band successfully.
960 */
961
962 ieee->mode = (enum wireless_mode)btWirelessMode;
963
964 /* 3. Change related setting. */
965 if (ieee->mode == WIRELESS_MODE_A)
966 DMESG("WIRELESS_MODE_A\n");
967 else if (ieee->mode == WIRELESS_MODE_B)
968 DMESG("WIRELESS_MODE_B\n");
969 else if (ieee->mode == WIRELESS_MODE_G)
970 DMESG("WIRELESS_MODE_G\n");
971
972 ActUpdateChannelAccessSetting(dev, ieee->mode,
973 &priv->ChannelAccessSetting);
974 }
975
976 void rtl8185b_irq_enable(struct net_device *dev)
977 {
978 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
979
980 priv->irq_enabled = 1;
981 write_nic_dword(dev, IMR, priv->IntrMask);
982 }
983
984 static void MgntDisconnectIBSS(struct net_device *dev)
985 {
986 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
987 u8 i;
988
989 for (i = 0; i < 6; i++)
990 priv->ieee80211->current_network.bssid[i] = 0x55;
991
992
993
994 priv->ieee80211->state = IEEE80211_NOLINK;
995 /*
996 * Stop Beacon.
997 *
998 * Vista add a Adhoc profile, HW radio off until
999 * OID_DOT11_RESET_REQUEST Driver would set MSR=NO_LINK,
1000 * then HW Radio ON, MgntQueue Stuck. Because Bcn DMA isn't
1001 * complete, mgnt queue would stuck until Bcn packet send.
1002 *
1003 * Disable Beacon Queue Own bit, suggested by jong
1004 */
1005 ieee80211_stop_send_beacons(priv->ieee80211);
1006
1007 priv->ieee80211->link_change(dev);
1008 notify_wx_assoc_event(priv->ieee80211);
1009 }
1010
1011 static void MlmeDisassociateRequest(struct net_device *dev, u8 *asSta, u8 asRsn)
1012 {
1013 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1014 u8 i;
1015
1016 SendDisassociation(priv->ieee80211, asSta, asRsn);
1017
1018 if (memcmp(priv->ieee80211->current_network.bssid, asSta, 6) == 0) {
1019 /* ShuChen TODO: change media status. */
1020
1021 for (i = 0; i < 6; i++)
1022 priv->ieee80211->current_network.bssid[i] = 0x22;
1023
1024 ieee80211_disassociate(priv->ieee80211);
1025 }
1026 }
1027
1028 static void MgntDisconnectAP(struct net_device *dev, u8 asRsn)
1029 {
1030 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1031
1032 /*
1033 * Commented out by rcnjko, 2005.01.27:
1034 * I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
1035 *
1036 * 2004/09/15, kcwu, the key should be cleared, or the new
1037 * handshaking will not success
1038 *
1039 * In WPA WPA2 need to Clear all key ... because new key will set
1040 * after new handshaking. 2004.10.11, by rcnjko.
1041 */
1042 MlmeDisassociateRequest(dev, priv->ieee80211->current_network.bssid,
1043 asRsn);
1044
1045 priv->ieee80211->state = IEEE80211_NOLINK;
1046 }
1047
1048 static bool MgntDisconnect(struct net_device *dev, u8 asRsn)
1049 {
1050 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1051 /*
1052 * Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
1053 */
1054
1055 if (IS_DOT11D_ENABLE(priv->ieee80211))
1056 Dot11d_Reset(priv->ieee80211);
1057 /* In adhoc mode, update beacon frame. */
1058 if (priv->ieee80211->state == IEEE80211_LINKED) {
1059 if (priv->ieee80211->iw_mode == IW_MODE_ADHOC)
1060 MgntDisconnectIBSS(dev);
1061
1062 if (priv->ieee80211->iw_mode == IW_MODE_INFRA) {
1063 /*
1064 * We clear key here instead of MgntDisconnectAP()
1065 * because that MgntActSet_802_11_DISASSOCIATE()
1066 * is an interface called by OS, e.g.
1067 * OID_802_11_DISASSOCIATE in Windows while as
1068 * MgntDisconnectAP() is used to handle
1069 * disassociation related things to AP, e.g. send
1070 * Disassoc frame to AP. 2005.01.27, by rcnjko.
1071 */
1072 MgntDisconnectAP(dev, asRsn);
1073 }
1074 /* Indicate Disconnect, 2005.02.23, by rcnjko. */
1075 }
1076 return true;
1077 }
1078 /*
1079 * Description:
1080 * Chang RF Power State.
1081 * Note that, only MgntActSet_RF_State() is allowed to set
1082 * HW_VAR_RF_STATE.
1083 *
1084 * Assumption:
1085 * PASSIVE LEVEL.
1086 */
1087 static bool SetRFPowerState(struct net_device *dev,
1088 enum rt_rf_power_state eRFPowerState)
1089 {
1090 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1091 bool bResult = false;
1092
1093 if (eRFPowerState == priv->eRFPowerState)
1094 return bResult;
1095
1096 bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
1097
1098 return bResult;
1099 }
1100
1101 bool MgntActSet_RF_State(struct net_device *dev, enum rt_rf_power_state StateToSet,
1102 u32 ChangeSource)
1103 {
1104 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1105 bool bActionAllowed = false;
1106 bool bConnectBySSID = false;
1107 enum rt_rf_power_state rtState;
1108 u16 RFWaitCounter = 0;
1109 unsigned long flag;
1110 /*
1111 * Prevent the race condition of RF state change. By Bruce,
1112 * 2007-11-28. Only one thread can change the RF state at one time,
1113 * and others should wait to be executed.
1114 */
1115 while (true) {
1116 spin_lock_irqsave(&priv->rf_ps_lock, flag);
1117 if (priv->RFChangeInProgress) {
1118 spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1119 /* Set RF after the previous action is done. */
1120 while (priv->RFChangeInProgress) {
1121 RFWaitCounter++;
1122 udelay(1000); /* 1 ms */
1123
1124 /*
1125 * Wait too long, return FALSE to avoid
1126 * to be stuck here.
1127 */
1128 if (RFWaitCounter > 1000) { /* 1sec */
1129 netdev_info(dev, "MgntActSet_RF_State(): Wait too long to set RF\n");
1130 /* TODO: Reset RF state? */
1131 return false;
1132 }
1133 }
1134 } else {
1135 priv->RFChangeInProgress = true;
1136 spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1137 break;
1138 }
1139 }
1140 rtState = priv->eRFPowerState;
1141
1142 switch (StateToSet) {
1143 case RF_ON:
1144 /*
1145 * Turn On RF no matter the IPS setting because we need to
1146 * update the RF state to Ndis under Vista, or the Windows
1147 * does not allow the driver to perform site survey any
1148 * more. By Bruce, 2007-10-02.
1149 */
1150 priv->RfOffReason &= (~ChangeSource);
1151
1152 if (!priv->RfOffReason) {
1153 priv->RfOffReason = 0;
1154 bActionAllowed = true;
1155
1156 if (rtState == RF_OFF &&
1157 ChangeSource >= RF_CHANGE_BY_HW)
1158 bConnectBySSID = true;
1159 }
1160 break;
1161
1162 case RF_OFF:
1163 /* 070125, rcnjko: we always keep connected in AP mode. */
1164
1165 if (priv->RfOffReason > RF_CHANGE_BY_IPS) {
1166 /*
1167 * 060808, Annie:
1168 * Disconnect to current BSS when radio off.
1169 * Asked by QuanTa.
1170 *
1171 * Calling MgntDisconnect() instead of
1172 * MgntActSet_802_11_DISASSOCIATE(), because
1173 * we do NOT need to set ssid to dummy ones.
1174 */
1175 MgntDisconnect(dev, disas_lv_ss);
1176 /*
1177 * Clear content of bssDesc[] and bssDesc4Query[]
1178 * to avoid reporting old bss to UI.
1179 */
1180 }
1181
1182 priv->RfOffReason |= ChangeSource;
1183 bActionAllowed = true;
1184 break;
1185 case RF_SLEEP:
1186 priv->RfOffReason |= ChangeSource;
1187 bActionAllowed = true;
1188 break;
1189 default:
1190 break;
1191 }
1192
1193 if (bActionAllowed) {
1194 /* Config HW to the specified mode. */
1195 SetRFPowerState(dev, StateToSet);
1196 }
1197
1198 /* Release RF spinlock */
1199 spin_lock_irqsave(&priv->rf_ps_lock, flag);
1200 priv->RFChangeInProgress = false;
1201 spin_unlock_irqrestore(&priv->rf_ps_lock, flag);
1202 return bActionAllowed;
1203 }
1204
1205 static void InactivePowerSave(struct net_device *dev)
1206 {
1207 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1208 /*
1209 * This flag "bSwRfProcessing", indicates the status of IPS
1210 * procedure, should be set if the IPS workitem is really
1211 * scheduled. The old code, sets this flag before scheduling the
1212 * IPS workitem and however, at the same time the previous IPS
1213 * workitem did not end yet, fails to schedule the current
1214 * workitem. Thus, bSwRfProcessing blocks the IPS procedure of
1215 * switching RF.
1216 */
1217 priv->bSwRfProcessing = true;
1218
1219 MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
1220
1221 /*
1222 * To solve CAM values miss in RF OFF, rewrite CAM values after
1223 * RF ON. By Bruce, 2007-09-20.
1224 */
1225
1226 priv->bSwRfProcessing = false;
1227 }
1228
1229 /*
1230 * Description:
1231 * Enter the inactive power save mode. RF will be off
1232 */
1233 void IPSEnter(struct net_device *dev)
1234 {
1235 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1236 enum rt_rf_power_state rtState;
1237 if (priv->bInactivePs) {
1238 rtState = priv->eRFPowerState;
1239
1240 /*
1241 * Do not enter IPS in the following conditions:
1242 * (1) RF is already OFF or
1243 * Sleep (2) bSwRfProcessing (indicates the IPS is still
1244 * under going) (3) Connected (only disconnected can
1245 * trigger IPS)(4) IBSS (send Beacon)
1246 * (5) AP mode (send Beacon)
1247 */
1248 if (rtState == RF_ON && !priv->bSwRfProcessing
1249 && (priv->ieee80211->state != IEEE80211_LINKED)) {
1250 priv->eInactivePowerState = RF_OFF;
1251 InactivePowerSave(dev);
1252 }
1253 }
1254 }
1255 void IPSLeave(struct net_device *dev)
1256 {
1257 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1258 enum rt_rf_power_state rtState;
1259 if (priv->bInactivePs) {
1260 rtState = priv->eRFPowerState;
1261 if ((rtState == RF_OFF || rtState == RF_SLEEP) &&
1262 !priv->bSwRfProcessing
1263 && priv->RfOffReason <= RF_CHANGE_BY_IPS) {
1264 priv->eInactivePowerState = RF_ON;
1265 InactivePowerSave(dev);
1266 }
1267 }
1268 }
1269
1270 void rtl8185b_adapter_start(struct net_device *dev)
1271 {
1272 struct r8180_priv *priv = ieee80211_priv(dev);
1273 struct ieee80211_device *ieee = priv->ieee80211;
1274
1275 u8 SupportedWirelessMode;
1276 u8 InitWirelessMode;
1277 u8 bInvalidWirelessMode = 0;
1278 u8 tmpu8;
1279 u8 btCR9346;
1280 u8 TmpU1b;
1281 u8 btPSR;
1282
1283 write_nic_byte(dev, 0x24e, (BIT5|BIT6|BIT0));
1284 rtl8180_reset(dev);
1285
1286 priv->dma_poll_mask = 0;
1287 priv->dma_poll_stop_mask = 0;
1288
1289 HwConfigureRTL8185(dev);
1290 write_nic_dword(dev, MAC0, ((u32 *)dev->dev_addr)[0]);
1291 write_nic_word(dev, MAC4, ((u32 *)dev->dev_addr)[1] & 0xffff);
1292 /* default network type to 'No Link' */
1293 write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);
1294 write_nic_word(dev, BcnItv, 100);
1295 write_nic_word(dev, AtimWnd, 2);
1296 PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
1297 write_nic_byte(dev, WPA_CONFIG, 0);
1298 MacConfig_85BASIC(dev);
1299 /* Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07,
1300 * by rcnjko.
1301 */
1302 /* BT_DEMO_BOARD type */
1303 PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
1304
1305 /*
1306 *---------------------------------------------------------------------
1307 * Set up PHY related.
1308 *---------------------------------------------------------------------
1309 */
1310 /* Enable Config3.PARAM_En to revise AnaaParm. */
1311 write_nic_byte(dev, CR9346, 0xc0); /* enable config register write */
1312 tmpu8 = read_nic_byte(dev, CONFIG3);
1313 write_nic_byte(dev, CONFIG3, (tmpu8 | CONFIG3_PARM_En));
1314 /* Turn on Analog power. */
1315 /* Asked for by William, otherwise, MAC 3-wire can't work,
1316 * 2006.06.27, by rcnjko.
1317 */
1318 write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
1319 write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
1320 write_nic_word(dev, ANAPARAM3, 0x0010);
1321
1322 write_nic_byte(dev, CONFIG3, tmpu8);
1323 write_nic_byte(dev, CR9346, 0x00);
1324 /* enable EEM0 and EEM1 in 9346CR */
1325 btCR9346 = read_nic_byte(dev, CR9346);
1326 write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
1327
1328 /* B cut use LED1 to control HW RF on/off */
1329 TmpU1b = read_nic_byte(dev, CONFIG5);
1330 TmpU1b = TmpU1b & ~BIT3;
1331 write_nic_byte(dev, CONFIG5, TmpU1b);
1332
1333 /* disable EEM0 and EEM1 in 9346CR */
1334 btCR9346 &= ~(0xC0);
1335 write_nic_byte(dev, CR9346, btCR9346);
1336
1337 /* Enable Led (suggested by Jong) */
1338 /* B-cut RF Radio on/off 5e[3]=0 */
1339 btPSR = read_nic_byte(dev, PSR);
1340 write_nic_byte(dev, PSR, (btPSR | BIT3));
1341 /* setup initial timing for RFE. */
1342 write_nic_word(dev, RFPinsOutput, 0x0480);
1343 SetOutputEnableOfRfPins(dev);
1344 write_nic_word(dev, RFPinsSelect, 0x2488);
1345
1346 /* PHY config. */
1347 PhyConfig8185(dev);
1348
1349 /*
1350 * We assume RegWirelessMode has already been initialized before,
1351 * however, we has to validate the wireless mode here and provide a
1352 * reasonable initialized value if necessary. 2005.01.13,
1353 * by rcnjko.
1354 */
1355 SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1356 if ((ieee->mode != WIRELESS_MODE_B) &&
1357 (ieee->mode != WIRELESS_MODE_G) &&
1358 (ieee->mode != WIRELESS_MODE_A) &&
1359 (ieee->mode != WIRELESS_MODE_AUTO)) {
1360 /* It should be one of B, G, A, or AUTO. */
1361 bInvalidWirelessMode = 1;
1362 } else {
1363 /* One of B, G, A, or AUTO. */
1364 /* Check if the wireless mode is supported by RF. */
1365 if ((ieee->mode != WIRELESS_MODE_AUTO) &&
1366 (ieee->mode & SupportedWirelessMode) == 0) {
1367 bInvalidWirelessMode = 1;
1368 }
1369 }
1370
1371 if (bInvalidWirelessMode || ieee->mode == WIRELESS_MODE_AUTO) {
1372 /* Auto or other invalid value. */
1373 /* Assigne a wireless mode to initialize. */
1374 if ((SupportedWirelessMode & WIRELESS_MODE_A)) {
1375 InitWirelessMode = WIRELESS_MODE_A;
1376 } else if ((SupportedWirelessMode & WIRELESS_MODE_G)) {
1377 InitWirelessMode = WIRELESS_MODE_G;
1378 } else if ((SupportedWirelessMode & WIRELESS_MODE_B)) {
1379 InitWirelessMode = WIRELESS_MODE_B;
1380 } else {
1381 DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
1382 SupportedWirelessMode);
1383 InitWirelessMode = WIRELESS_MODE_B;
1384 }
1385
1386 /* Initialize RegWirelessMode if it is not a valid one. */
1387 if (bInvalidWirelessMode)
1388 ieee->mode = (enum wireless_mode)InitWirelessMode;
1389
1390 } else {
1391 /* One of B, G, A. */
1392 InitWirelessMode = ieee->mode;
1393 }
1394 priv->eRFPowerState = RF_OFF;
1395 priv->RfOffReason = 0;
1396 {
1397 MgntActSet_RF_State(dev, RF_ON, 0);
1398 }
1399 /*
1400 * If inactive power mode is enabled, disable rf while in
1401 * disconnected state.
1402 */
1403 if (priv->bInactivePs)
1404 MgntActSet_RF_State(dev , RF_OFF, RF_CHANGE_BY_IPS);
1405
1406 ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
1407
1408 /* ----------------------------------------------------------------- */
1409
1410 rtl8185b_irq_enable(dev);
1411
1412 netif_start_queue(dev);
1413 }
1414
1415 void rtl8185b_rx_enable(struct net_device *dev)
1416 {
1417 u8 cmd;
1418 /* for now we accept data, management & ctl frame*/
1419 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1420
1421
1422 if (dev->flags & IFF_PROMISC)
1423 DMESG("NIC in promisc mode");
1424
1425 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR || dev->flags &
1426 IFF_PROMISC) {
1427 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
1428 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
1429 }
1430
1431 if (priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1432 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF |
1433 RCR_APWRMGT | RCR_AICV;
1434
1435
1436 if (priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
1437 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
1438
1439 write_nic_dword(dev, RCR, priv->ReceiveConfig);
1440
1441 fix_rx_fifo(dev);
1442
1443 cmd = read_nic_byte(dev, CMD);
1444 write_nic_byte(dev, CMD, cmd | (1<<CMD_RX_ENABLE_SHIFT));
1445
1446 }
1447
1448 void rtl8185b_tx_enable(struct net_device *dev)
1449 {
1450 u8 cmd;
1451 u8 byte;
1452 struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1453
1454 write_nic_dword(dev, TCR, priv->TransmitConfig);
1455 byte = read_nic_byte(dev, MSR);
1456 byte |= MSR_LINK_ENEDCA;
1457 write_nic_byte(dev, MSR, byte);
1458
1459 fix_tx_fifo(dev);
1460
1461 cmd = read_nic_byte(dev, CMD);
1462 write_nic_byte(dev, CMD, cmd | (1<<CMD_TX_ENABLE_SHIFT));
1463 }
1464
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