2 * Copyright (C) 2006-2007 Freescale Semicondutor, Inc. All rights reserved.
4 * Author: Shlomi Gridish <gridish@freescale.com>
5 * Li Yang <leoli@freescale.com>
8 * QE UCC Gigabit Ethernet Driver
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/slab.h>
19 #include <linux/stddef.h>
20 #include <linux/interrupt.h>
21 #include <linux/netdevice.h>
22 #include <linux/etherdevice.h>
23 #include <linux/skbuff.h>
24 #include <linux/spinlock.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/fsl_devices.h>
28 #include <linux/mii.h>
29 #include <linux/phy.h>
30 #include <linux/workqueue.h>
32 #include <asm/of_platform.h>
33 #include <asm/uaccess.h>
36 #include <asm/immap_qe.h>
39 #include <asm/ucc_fast.h>
42 #include "ucc_geth_mii.h"
46 #define ugeth_printk(level, format, arg...) \
47 printk(level format "\n", ## arg)
49 #define ugeth_dbg(format, arg...) \
50 ugeth_printk(KERN_DEBUG , format , ## arg)
51 #define ugeth_err(format, arg...) \
52 ugeth_printk(KERN_ERR , format , ## arg)
53 #define ugeth_info(format, arg...) \
54 ugeth_printk(KERN_INFO , format , ## arg)
55 #define ugeth_warn(format, arg...) \
56 ugeth_printk(KERN_WARNING , format , ## arg)
58 #ifdef UGETH_VERBOSE_DEBUG
59 #define ugeth_vdbg ugeth_dbg
61 #define ugeth_vdbg(fmt, args...) do { } while (0)
62 #endif /* UGETH_VERBOSE_DEBUG */
63 #define UGETH_MSG_DEFAULT (NETIF_MSG_IFUP << 1 ) - 1
65 void uec_set_ethtool_ops(struct net_device
*netdev
);
67 static DEFINE_SPINLOCK(ugeth_lock
);
73 module_param_named(debug
, debug
.msg_enable
, int, 0);
74 MODULE_PARM_DESC(debug
, "Debug verbosity level (0=none, ..., 0xffff=all)");
76 static struct ucc_geth_info ugeth_primary_info
= {
78 .bd_mem_part
= MEM_PART_SYSTEM
,
79 .rtsm
= UCC_FAST_SEND_IDLES_BETWEEN_FRAMES
,
80 .max_rx_buf_length
= 1536,
81 /* adjusted at startup if max-speed 1000 */
82 .urfs
= UCC_GETH_URFS_INIT
,
83 .urfet
= UCC_GETH_URFET_INIT
,
84 .urfset
= UCC_GETH_URFSET_INIT
,
85 .utfs
= UCC_GETH_UTFS_INIT
,
86 .utfet
= UCC_GETH_UTFET_INIT
,
87 .utftt
= UCC_GETH_UTFTT_INIT
,
89 .mode
= UCC_FAST_PROTOCOL_MODE_ETHERNET
,
90 .ttx_trx
= UCC_FAST_GUMR_TRANSPARENT_TTX_TRX_NORMAL
,
91 .tenc
= UCC_FAST_TX_ENCODING_NRZ
,
92 .renc
= UCC_FAST_RX_ENCODING_NRZ
,
93 .tcrc
= UCC_FAST_16_BIT_CRC
,
94 .synl
= UCC_FAST_SYNC_LEN_NOT_USED
,
98 .extendedFilteringChainPointer
= ((uint32_t) NULL
),
99 .typeorlen
= 3072 /*1536 */ ,
100 .nonBackToBackIfgPart1
= 0x40,
101 .nonBackToBackIfgPart2
= 0x60,
102 .miminumInterFrameGapEnforcement
= 0x50,
103 .backToBackInterFrameGap
= 0x60,
107 .strictpriorityq
= 0xff,
108 .altBebTruncation
= 0xa,
110 .maxRetransmission
= 0xf,
111 .collisionWindow
= 0x37,
112 .receiveFlowControl
= 1,
113 .transmitFlowControl
= 1,
114 .maxGroupAddrInHash
= 4,
115 .maxIndAddrInHash
= 4,
117 .maxFrameLength
= 1518,
118 .minFrameLength
= 64,
122 .ecamptr
= ((uint32_t) NULL
),
123 .eventRegMask
= UCCE_OTHER
,
124 .pausePeriod
= 0xf000,
125 .interruptcoalescingmaxvalue
= {1, 1, 1, 1, 1, 1, 1, 1},
146 .numStationAddresses
= UCC_GETH_NUM_OF_STATION_ADDRESSES_1
,
147 .largestexternallookupkeysize
=
148 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
,
149 .statisticsMode
= UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
|
150 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
|
151 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
,
152 .vlanOperationTagged
= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
,
153 .vlanOperationNonTagged
= UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
,
154 .rxQoSMode
= UCC_GETH_QOS_MODE_DEFAULT
,
155 .aufc
= UPSMR_AUTOMATIC_FLOW_CONTROL_MODE_NONE
,
156 .padAndCrc
= MACCFG2_PAD_AND_CRC_MODE_PAD_AND_CRC
,
157 .numThreadsTx
= UCC_GETH_NUM_OF_THREADS_4
,
158 .numThreadsRx
= UCC_GETH_NUM_OF_THREADS_4
,
159 .riscTx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
160 .riscRx
= QE_RISC_ALLOCATION_RISC1_AND_RISC2
,
163 static struct ucc_geth_info ugeth_info
[8];
166 static void mem_disp(u8
*addr
, int size
)
169 int size16Aling
= (size
>> 4) << 4;
170 int size4Aling
= (size
>> 2) << 2;
175 for (i
= addr
; (u32
) i
< (u32
) addr
+ size16Aling
; i
+= 16)
176 printk("0x%08x: %08x %08x %08x %08x\r\n",
180 *((u32
*) (i
+ 8)), *((u32
*) (i
+ 12)));
182 printk("0x%08x: ", (u32
) i
);
183 for (; (u32
) i
< (u32
) addr
+ size4Aling
; i
+= 4)
184 printk("%08x ", *((u32
*) (i
)));
185 for (; (u32
) i
< (u32
) addr
+ size
; i
++)
186 printk("%02x", *((u8
*) (i
)));
192 #ifdef CONFIG_UGETH_FILTERING
193 static void enqueue(struct list_head
*node
, struct list_head
*lh
)
197 spin_lock_irqsave(&ugeth_lock
, flags
);
198 list_add_tail(node
, lh
);
199 spin_unlock_irqrestore(&ugeth_lock
, flags
);
201 #endif /* CONFIG_UGETH_FILTERING */
203 static struct list_head
*dequeue(struct list_head
*lh
)
207 spin_lock_irqsave(&ugeth_lock
, flags
);
208 if (!list_empty(lh
)) {
209 struct list_head
*node
= lh
->next
;
211 spin_unlock_irqrestore(&ugeth_lock
, flags
);
214 spin_unlock_irqrestore(&ugeth_lock
, flags
);
219 static struct sk_buff
*get_new_skb(struct ucc_geth_private
*ugeth
, u8
*bd
)
221 struct sk_buff
*skb
= NULL
;
223 skb
= dev_alloc_skb(ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
224 UCC_GETH_RX_DATA_BUF_ALIGNMENT
);
229 /* We need the data buffer to be aligned properly. We will reserve
230 * as many bytes as needed to align the data properly
233 UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
234 (((unsigned)skb
->data
) & (UCC_GETH_RX_DATA_BUF_ALIGNMENT
-
237 skb
->dev
= ugeth
->dev
;
239 out_be32(&((struct qe_bd
*)bd
)->buf
,
242 ugeth
->ug_info
->uf_info
.max_rx_buf_length
+
243 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
246 out_be32((u32
*)bd
, (R_E
| R_I
| (in_be32((u32
*)bd
) & R_W
)));
251 static int rx_bd_buffer_set(struct ucc_geth_private
*ugeth
, u8 rxQ
)
258 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
262 bd_status
= in_be32((u32
*)bd
);
263 skb
= get_new_skb(ugeth
, bd
);
265 if (!skb
) /* If can not allocate data buffer,
266 abort. Cleanup will be elsewhere */
269 ugeth
->rx_skbuff
[rxQ
][i
] = skb
;
271 /* advance the BD pointer */
272 bd
+= sizeof(struct qe_bd
);
274 } while (!(bd_status
& R_W
));
279 static int fill_init_enet_entries(struct ucc_geth_private
*ugeth
,
280 volatile u32
*p_start
,
283 u32 thread_alignment
,
284 enum qe_risc_allocation risc
,
285 int skip_page_for_first_entry
)
287 u32 init_enet_offset
;
291 for (i
= 0; i
< num_entries
; i
++) {
292 if ((snum
= qe_get_snum()) < 0) {
293 if (netif_msg_ifup(ugeth
))
294 ugeth_err("fill_init_enet_entries: Can not get SNUM.");
297 if ((i
== 0) && skip_page_for_first_entry
)
298 /* First entry of Rx does not have page */
299 init_enet_offset
= 0;
302 qe_muram_alloc(thread_size
, thread_alignment
);
303 if (IS_ERR_VALUE(init_enet_offset
)) {
304 if (netif_msg_ifup(ugeth
))
305 ugeth_err("fill_init_enet_entries: Can not allocate DPRAM memory.");
306 qe_put_snum((u8
) snum
);
311 ((u8
) snum
<< ENET_INIT_PARAM_SNUM_SHIFT
) | init_enet_offset
318 static int return_init_enet_entries(struct ucc_geth_private
*ugeth
,
319 volatile u32
*p_start
,
321 enum qe_risc_allocation risc
,
322 int skip_page_for_first_entry
)
324 u32 init_enet_offset
;
328 for (i
= 0; i
< num_entries
; i
++) {
329 /* Check that this entry was actually valid --
330 needed in case failed in allocations */
331 if ((*p_start
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
333 (u32
) (*p_start
& ENET_INIT_PARAM_SNUM_MASK
) >>
334 ENET_INIT_PARAM_SNUM_SHIFT
;
335 qe_put_snum((u8
) snum
);
336 if (!((i
== 0) && skip_page_for_first_entry
)) {
337 /* First entry of Rx does not have page */
340 ENET_INIT_PARAM_PTR_MASK
);
341 qe_muram_free(init_enet_offset
);
343 *(p_start
++) = 0; /* Just for cosmetics */
351 static int dump_init_enet_entries(struct ucc_geth_private
*ugeth
,
352 volatile u32
*p_start
,
355 enum qe_risc_allocation risc
,
356 int skip_page_for_first_entry
)
358 u32 init_enet_offset
;
362 for (i
= 0; i
< num_entries
; i
++) {
363 /* Check that this entry was actually valid --
364 needed in case failed in allocations */
365 if ((*p_start
& ENET_INIT_PARAM_RISC_MASK
) == risc
) {
367 (u32
) (*p_start
& ENET_INIT_PARAM_SNUM_MASK
) >>
368 ENET_INIT_PARAM_SNUM_SHIFT
;
369 qe_put_snum((u8
) snum
);
370 if (!((i
== 0) && skip_page_for_first_entry
)) {
371 /* First entry of Rx does not have page */
374 ENET_INIT_PARAM_PTR_MASK
);
375 ugeth_info("Init enet entry %d:", i
);
376 ugeth_info("Base address: 0x%08x",
378 qe_muram_addr(init_enet_offset
));
379 mem_disp(qe_muram_addr(init_enet_offset
),
390 #ifdef CONFIG_UGETH_FILTERING
391 static struct enet_addr_container
*get_enet_addr_container(void)
393 struct enet_addr_container
*enet_addr_cont
;
395 /* allocate memory */
396 enet_addr_cont
= kmalloc(sizeof(struct enet_addr_container
), GFP_KERNEL
);
397 if (!enet_addr_cont
) {
398 ugeth_err("%s: No memory for enet_addr_container object.",
403 return enet_addr_cont
;
405 #endif /* CONFIG_UGETH_FILTERING */
407 static void put_enet_addr_container(struct enet_addr_container
*enet_addr_cont
)
409 kfree(enet_addr_cont
);
412 static void set_mac_addr(__be16 __iomem
*reg
, u8
*mac
)
414 out_be16(®
[0], ((u16
)mac
[5] << 8) | mac
[4]);
415 out_be16(®
[1], ((u16
)mac
[3] << 8) | mac
[2]);
416 out_be16(®
[2], ((u16
)mac
[1] << 8) | mac
[0]);
419 #ifdef CONFIG_UGETH_FILTERING
420 static int hw_add_addr_in_paddr(struct ucc_geth_private
*ugeth
,
421 u8
*p_enet_addr
, u8 paddr_num
)
423 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
425 if (!(paddr_num
< NUM_OF_PADDRS
)) {
426 ugeth_warn("%s: Illegal paddr_num.", __FUNCTION__
);
431 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
434 /* Ethernet frames are defined in Little Endian mode, */
435 /* therefore to insert the address we reverse the bytes. */
436 set_mac_addr(&p_82xx_addr_filt
->paddr
[paddr_num
].h
, p_enet_addr
);
439 #endif /* CONFIG_UGETH_FILTERING */
441 static int hw_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
, u8 paddr_num
)
443 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
445 if (!(paddr_num
< NUM_OF_PADDRS
)) {
446 ugeth_warn("%s: Illagel paddr_num.", __FUNCTION__
);
451 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
454 /* Writing address ff.ff.ff.ff.ff.ff disables address
455 recognition for this register */
456 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].h
, 0xffff);
457 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].m
, 0xffff);
458 out_be16(&p_82xx_addr_filt
->paddr
[paddr_num
].l
, 0xffff);
463 static void hw_add_addr_in_hash(struct ucc_geth_private
*ugeth
,
466 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
470 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
474 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
476 /* Ethernet frames are defined in Little Endian mode,
477 therefor to insert */
478 /* the address to the hash (Big Endian mode), we reverse the bytes.*/
480 set_mac_addr(&p_82xx_addr_filt
->taddr
.h
, p_enet_addr
);
482 qe_issue_cmd(QE_SET_GROUP_ADDRESS
, cecr_subblock
,
483 QE_CR_PROTOCOL_ETHERNET
, 0);
486 #ifdef CONFIG_UGETH_MAGIC_PACKET
487 static void magic_packet_detection_enable(struct ucc_geth_private
*ugeth
)
489 struct ucc_fast_private
*uccf
;
490 struct ucc_geth
*ug_regs
;
494 ug_regs
= ugeth
->ug_regs
;
496 /* Enable interrupts for magic packet detection */
497 uccm
= in_be32(uccf
->p_uccm
);
499 out_be32(uccf
->p_uccm
, uccm
);
501 /* Enable magic packet detection */
502 maccfg2
= in_be32(&ug_regs
->maccfg2
);
503 maccfg2
|= MACCFG2_MPE
;
504 out_be32(&ug_regs
->maccfg2
, maccfg2
);
507 static void magic_packet_detection_disable(struct ucc_geth_private
*ugeth
)
509 struct ucc_fast_private
*uccf
;
510 struct ucc_geth
*ug_regs
;
514 ug_regs
= ugeth
->ug_regs
;
516 /* Disable interrupts for magic packet detection */
517 uccm
= in_be32(uccf
->p_uccm
);
519 out_be32(uccf
->p_uccm
, uccm
);
521 /* Disable magic packet detection */
522 maccfg2
= in_be32(&ug_regs
->maccfg2
);
523 maccfg2
&= ~MACCFG2_MPE
;
524 out_be32(&ug_regs
->maccfg2
, maccfg2
);
526 #endif /* MAGIC_PACKET */
528 static inline int compare_addr(u8
**addr1
, u8
**addr2
)
530 return memcmp(addr1
, addr2
, ENET_NUM_OCTETS_PER_ADDRESS
);
534 static void get_statistics(struct ucc_geth_private
*ugeth
,
535 struct ucc_geth_tx_firmware_statistics
*
536 tx_firmware_statistics
,
537 struct ucc_geth_rx_firmware_statistics
*
538 rx_firmware_statistics
,
539 struct ucc_geth_hardware_statistics
*hardware_statistics
)
541 struct ucc_fast
*uf_regs
;
542 struct ucc_geth
*ug_regs
;
543 struct ucc_geth_tx_firmware_statistics_pram
*p_tx_fw_statistics_pram
;
544 struct ucc_geth_rx_firmware_statistics_pram
*p_rx_fw_statistics_pram
;
546 ug_regs
= ugeth
->ug_regs
;
547 uf_regs
= (struct ucc_fast
*) ug_regs
;
548 p_tx_fw_statistics_pram
= ugeth
->p_tx_fw_statistics_pram
;
549 p_rx_fw_statistics_pram
= ugeth
->p_rx_fw_statistics_pram
;
551 /* Tx firmware only if user handed pointer and driver actually
552 gathers Tx firmware statistics */
553 if (tx_firmware_statistics
&& p_tx_fw_statistics_pram
) {
554 tx_firmware_statistics
->sicoltx
=
555 in_be32(&p_tx_fw_statistics_pram
->sicoltx
);
556 tx_firmware_statistics
->mulcoltx
=
557 in_be32(&p_tx_fw_statistics_pram
->mulcoltx
);
558 tx_firmware_statistics
->latecoltxfr
=
559 in_be32(&p_tx_fw_statistics_pram
->latecoltxfr
);
560 tx_firmware_statistics
->frabortduecol
=
561 in_be32(&p_tx_fw_statistics_pram
->frabortduecol
);
562 tx_firmware_statistics
->frlostinmactxer
=
563 in_be32(&p_tx_fw_statistics_pram
->frlostinmactxer
);
564 tx_firmware_statistics
->carriersenseertx
=
565 in_be32(&p_tx_fw_statistics_pram
->carriersenseertx
);
566 tx_firmware_statistics
->frtxok
=
567 in_be32(&p_tx_fw_statistics_pram
->frtxok
);
568 tx_firmware_statistics
->txfrexcessivedefer
=
569 in_be32(&p_tx_fw_statistics_pram
->txfrexcessivedefer
);
570 tx_firmware_statistics
->txpkts256
=
571 in_be32(&p_tx_fw_statistics_pram
->txpkts256
);
572 tx_firmware_statistics
->txpkts512
=
573 in_be32(&p_tx_fw_statistics_pram
->txpkts512
);
574 tx_firmware_statistics
->txpkts1024
=
575 in_be32(&p_tx_fw_statistics_pram
->txpkts1024
);
576 tx_firmware_statistics
->txpktsjumbo
=
577 in_be32(&p_tx_fw_statistics_pram
->txpktsjumbo
);
580 /* Rx firmware only if user handed pointer and driver actually
581 * gathers Rx firmware statistics */
582 if (rx_firmware_statistics
&& p_rx_fw_statistics_pram
) {
584 rx_firmware_statistics
->frrxfcser
=
585 in_be32(&p_rx_fw_statistics_pram
->frrxfcser
);
586 rx_firmware_statistics
->fraligner
=
587 in_be32(&p_rx_fw_statistics_pram
->fraligner
);
588 rx_firmware_statistics
->inrangelenrxer
=
589 in_be32(&p_rx_fw_statistics_pram
->inrangelenrxer
);
590 rx_firmware_statistics
->outrangelenrxer
=
591 in_be32(&p_rx_fw_statistics_pram
->outrangelenrxer
);
592 rx_firmware_statistics
->frtoolong
=
593 in_be32(&p_rx_fw_statistics_pram
->frtoolong
);
594 rx_firmware_statistics
->runt
=
595 in_be32(&p_rx_fw_statistics_pram
->runt
);
596 rx_firmware_statistics
->verylongevent
=
597 in_be32(&p_rx_fw_statistics_pram
->verylongevent
);
598 rx_firmware_statistics
->symbolerror
=
599 in_be32(&p_rx_fw_statistics_pram
->symbolerror
);
600 rx_firmware_statistics
->dropbsy
=
601 in_be32(&p_rx_fw_statistics_pram
->dropbsy
);
602 for (i
= 0; i
< 0x8; i
++)
603 rx_firmware_statistics
->res0
[i
] =
604 p_rx_fw_statistics_pram
->res0
[i
];
605 rx_firmware_statistics
->mismatchdrop
=
606 in_be32(&p_rx_fw_statistics_pram
->mismatchdrop
);
607 rx_firmware_statistics
->underpkts
=
608 in_be32(&p_rx_fw_statistics_pram
->underpkts
);
609 rx_firmware_statistics
->pkts256
=
610 in_be32(&p_rx_fw_statistics_pram
->pkts256
);
611 rx_firmware_statistics
->pkts512
=
612 in_be32(&p_rx_fw_statistics_pram
->pkts512
);
613 rx_firmware_statistics
->pkts1024
=
614 in_be32(&p_rx_fw_statistics_pram
->pkts1024
);
615 rx_firmware_statistics
->pktsjumbo
=
616 in_be32(&p_rx_fw_statistics_pram
->pktsjumbo
);
617 rx_firmware_statistics
->frlossinmacer
=
618 in_be32(&p_rx_fw_statistics_pram
->frlossinmacer
);
619 rx_firmware_statistics
->pausefr
=
620 in_be32(&p_rx_fw_statistics_pram
->pausefr
);
621 for (i
= 0; i
< 0x4; i
++)
622 rx_firmware_statistics
->res1
[i
] =
623 p_rx_fw_statistics_pram
->res1
[i
];
624 rx_firmware_statistics
->removevlan
=
625 in_be32(&p_rx_fw_statistics_pram
->removevlan
);
626 rx_firmware_statistics
->replacevlan
=
627 in_be32(&p_rx_fw_statistics_pram
->replacevlan
);
628 rx_firmware_statistics
->insertvlan
=
629 in_be32(&p_rx_fw_statistics_pram
->insertvlan
);
632 /* Hardware only if user handed pointer and driver actually
633 gathers hardware statistics */
634 if (hardware_statistics
&& (in_be32(&uf_regs
->upsmr
) & UPSMR_HSE
)) {
635 hardware_statistics
->tx64
= in_be32(&ug_regs
->tx64
);
636 hardware_statistics
->tx127
= in_be32(&ug_regs
->tx127
);
637 hardware_statistics
->tx255
= in_be32(&ug_regs
->tx255
);
638 hardware_statistics
->rx64
= in_be32(&ug_regs
->rx64
);
639 hardware_statistics
->rx127
= in_be32(&ug_regs
->rx127
);
640 hardware_statistics
->rx255
= in_be32(&ug_regs
->rx255
);
641 hardware_statistics
->txok
= in_be32(&ug_regs
->txok
);
642 hardware_statistics
->txcf
= in_be16(&ug_regs
->txcf
);
643 hardware_statistics
->tmca
= in_be32(&ug_regs
->tmca
);
644 hardware_statistics
->tbca
= in_be32(&ug_regs
->tbca
);
645 hardware_statistics
->rxfok
= in_be32(&ug_regs
->rxfok
);
646 hardware_statistics
->rxbok
= in_be32(&ug_regs
->rxbok
);
647 hardware_statistics
->rbyt
= in_be32(&ug_regs
->rbyt
);
648 hardware_statistics
->rmca
= in_be32(&ug_regs
->rmca
);
649 hardware_statistics
->rbca
= in_be32(&ug_regs
->rbca
);
653 static void dump_bds(struct ucc_geth_private
*ugeth
)
658 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
659 if (ugeth
->p_tx_bd_ring
[i
]) {
661 (ugeth
->ug_info
->bdRingLenTx
[i
] *
662 sizeof(struct qe_bd
));
663 ugeth_info("TX BDs[%d]", i
);
664 mem_disp(ugeth
->p_tx_bd_ring
[i
], length
);
667 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
668 if (ugeth
->p_rx_bd_ring
[i
]) {
670 (ugeth
->ug_info
->bdRingLenRx
[i
] *
671 sizeof(struct qe_bd
));
672 ugeth_info("RX BDs[%d]", i
);
673 mem_disp(ugeth
->p_rx_bd_ring
[i
], length
);
678 static void dump_regs(struct ucc_geth_private
*ugeth
)
682 ugeth_info("UCC%d Geth registers:", ugeth
->ug_info
->uf_info
.ucc_num
);
683 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->ug_regs
);
685 ugeth_info("maccfg1 : addr - 0x%08x, val - 0x%08x",
686 (u32
) & ugeth
->ug_regs
->maccfg1
,
687 in_be32(&ugeth
->ug_regs
->maccfg1
));
688 ugeth_info("maccfg2 : addr - 0x%08x, val - 0x%08x",
689 (u32
) & ugeth
->ug_regs
->maccfg2
,
690 in_be32(&ugeth
->ug_regs
->maccfg2
));
691 ugeth_info("ipgifg : addr - 0x%08x, val - 0x%08x",
692 (u32
) & ugeth
->ug_regs
->ipgifg
,
693 in_be32(&ugeth
->ug_regs
->ipgifg
));
694 ugeth_info("hafdup : addr - 0x%08x, val - 0x%08x",
695 (u32
) & ugeth
->ug_regs
->hafdup
,
696 in_be32(&ugeth
->ug_regs
->hafdup
));
697 ugeth_info("ifctl : addr - 0x%08x, val - 0x%08x",
698 (u32
) & ugeth
->ug_regs
->ifctl
,
699 in_be32(&ugeth
->ug_regs
->ifctl
));
700 ugeth_info("ifstat : addr - 0x%08x, val - 0x%08x",
701 (u32
) & ugeth
->ug_regs
->ifstat
,
702 in_be32(&ugeth
->ug_regs
->ifstat
));
703 ugeth_info("macstnaddr1: addr - 0x%08x, val - 0x%08x",
704 (u32
) & ugeth
->ug_regs
->macstnaddr1
,
705 in_be32(&ugeth
->ug_regs
->macstnaddr1
));
706 ugeth_info("macstnaddr2: addr - 0x%08x, val - 0x%08x",
707 (u32
) & ugeth
->ug_regs
->macstnaddr2
,
708 in_be32(&ugeth
->ug_regs
->macstnaddr2
));
709 ugeth_info("uempr : addr - 0x%08x, val - 0x%08x",
710 (u32
) & ugeth
->ug_regs
->uempr
,
711 in_be32(&ugeth
->ug_regs
->uempr
));
712 ugeth_info("utbipar : addr - 0x%08x, val - 0x%08x",
713 (u32
) & ugeth
->ug_regs
->utbipar
,
714 in_be32(&ugeth
->ug_regs
->utbipar
));
715 ugeth_info("uescr : addr - 0x%08x, val - 0x%04x",
716 (u32
) & ugeth
->ug_regs
->uescr
,
717 in_be16(&ugeth
->ug_regs
->uescr
));
718 ugeth_info("tx64 : addr - 0x%08x, val - 0x%08x",
719 (u32
) & ugeth
->ug_regs
->tx64
,
720 in_be32(&ugeth
->ug_regs
->tx64
));
721 ugeth_info("tx127 : addr - 0x%08x, val - 0x%08x",
722 (u32
) & ugeth
->ug_regs
->tx127
,
723 in_be32(&ugeth
->ug_regs
->tx127
));
724 ugeth_info("tx255 : addr - 0x%08x, val - 0x%08x",
725 (u32
) & ugeth
->ug_regs
->tx255
,
726 in_be32(&ugeth
->ug_regs
->tx255
));
727 ugeth_info("rx64 : addr - 0x%08x, val - 0x%08x",
728 (u32
) & ugeth
->ug_regs
->rx64
,
729 in_be32(&ugeth
->ug_regs
->rx64
));
730 ugeth_info("rx127 : addr - 0x%08x, val - 0x%08x",
731 (u32
) & ugeth
->ug_regs
->rx127
,
732 in_be32(&ugeth
->ug_regs
->rx127
));
733 ugeth_info("rx255 : addr - 0x%08x, val - 0x%08x",
734 (u32
) & ugeth
->ug_regs
->rx255
,
735 in_be32(&ugeth
->ug_regs
->rx255
));
736 ugeth_info("txok : addr - 0x%08x, val - 0x%08x",
737 (u32
) & ugeth
->ug_regs
->txok
,
738 in_be32(&ugeth
->ug_regs
->txok
));
739 ugeth_info("txcf : addr - 0x%08x, val - 0x%04x",
740 (u32
) & ugeth
->ug_regs
->txcf
,
741 in_be16(&ugeth
->ug_regs
->txcf
));
742 ugeth_info("tmca : addr - 0x%08x, val - 0x%08x",
743 (u32
) & ugeth
->ug_regs
->tmca
,
744 in_be32(&ugeth
->ug_regs
->tmca
));
745 ugeth_info("tbca : addr - 0x%08x, val - 0x%08x",
746 (u32
) & ugeth
->ug_regs
->tbca
,
747 in_be32(&ugeth
->ug_regs
->tbca
));
748 ugeth_info("rxfok : addr - 0x%08x, val - 0x%08x",
749 (u32
) & ugeth
->ug_regs
->rxfok
,
750 in_be32(&ugeth
->ug_regs
->rxfok
));
751 ugeth_info("rxbok : addr - 0x%08x, val - 0x%08x",
752 (u32
) & ugeth
->ug_regs
->rxbok
,
753 in_be32(&ugeth
->ug_regs
->rxbok
));
754 ugeth_info("rbyt : addr - 0x%08x, val - 0x%08x",
755 (u32
) & ugeth
->ug_regs
->rbyt
,
756 in_be32(&ugeth
->ug_regs
->rbyt
));
757 ugeth_info("rmca : addr - 0x%08x, val - 0x%08x",
758 (u32
) & ugeth
->ug_regs
->rmca
,
759 in_be32(&ugeth
->ug_regs
->rmca
));
760 ugeth_info("rbca : addr - 0x%08x, val - 0x%08x",
761 (u32
) & ugeth
->ug_regs
->rbca
,
762 in_be32(&ugeth
->ug_regs
->rbca
));
763 ugeth_info("scar : addr - 0x%08x, val - 0x%08x",
764 (u32
) & ugeth
->ug_regs
->scar
,
765 in_be32(&ugeth
->ug_regs
->scar
));
766 ugeth_info("scam : addr - 0x%08x, val - 0x%08x",
767 (u32
) & ugeth
->ug_regs
->scam
,
768 in_be32(&ugeth
->ug_regs
->scam
));
770 if (ugeth
->p_thread_data_tx
) {
771 int numThreadsTxNumerical
;
772 switch (ugeth
->ug_info
->numThreadsTx
) {
773 case UCC_GETH_NUM_OF_THREADS_1
:
774 numThreadsTxNumerical
= 1;
776 case UCC_GETH_NUM_OF_THREADS_2
:
777 numThreadsTxNumerical
= 2;
779 case UCC_GETH_NUM_OF_THREADS_4
:
780 numThreadsTxNumerical
= 4;
782 case UCC_GETH_NUM_OF_THREADS_6
:
783 numThreadsTxNumerical
= 6;
785 case UCC_GETH_NUM_OF_THREADS_8
:
786 numThreadsTxNumerical
= 8;
789 numThreadsTxNumerical
= 0;
793 ugeth_info("Thread data TXs:");
794 ugeth_info("Base address: 0x%08x",
795 (u32
) ugeth
->p_thread_data_tx
);
796 for (i
= 0; i
< numThreadsTxNumerical
; i
++) {
797 ugeth_info("Thread data TX[%d]:", i
);
798 ugeth_info("Base address: 0x%08x",
799 (u32
) & ugeth
->p_thread_data_tx
[i
]);
800 mem_disp((u8
*) & ugeth
->p_thread_data_tx
[i
],
801 sizeof(struct ucc_geth_thread_data_tx
));
804 if (ugeth
->p_thread_data_rx
) {
805 int numThreadsRxNumerical
;
806 switch (ugeth
->ug_info
->numThreadsRx
) {
807 case UCC_GETH_NUM_OF_THREADS_1
:
808 numThreadsRxNumerical
= 1;
810 case UCC_GETH_NUM_OF_THREADS_2
:
811 numThreadsRxNumerical
= 2;
813 case UCC_GETH_NUM_OF_THREADS_4
:
814 numThreadsRxNumerical
= 4;
816 case UCC_GETH_NUM_OF_THREADS_6
:
817 numThreadsRxNumerical
= 6;
819 case UCC_GETH_NUM_OF_THREADS_8
:
820 numThreadsRxNumerical
= 8;
823 numThreadsRxNumerical
= 0;
827 ugeth_info("Thread data RX:");
828 ugeth_info("Base address: 0x%08x",
829 (u32
) ugeth
->p_thread_data_rx
);
830 for (i
= 0; i
< numThreadsRxNumerical
; i
++) {
831 ugeth_info("Thread data RX[%d]:", i
);
832 ugeth_info("Base address: 0x%08x",
833 (u32
) & ugeth
->p_thread_data_rx
[i
]);
834 mem_disp((u8
*) & ugeth
->p_thread_data_rx
[i
],
835 sizeof(struct ucc_geth_thread_data_rx
));
838 if (ugeth
->p_exf_glbl_param
) {
839 ugeth_info("EXF global param:");
840 ugeth_info("Base address: 0x%08x",
841 (u32
) ugeth
->p_exf_glbl_param
);
842 mem_disp((u8
*) ugeth
->p_exf_glbl_param
,
843 sizeof(*ugeth
->p_exf_glbl_param
));
845 if (ugeth
->p_tx_glbl_pram
) {
846 ugeth_info("TX global param:");
847 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_tx_glbl_pram
);
848 ugeth_info("temoder : addr - 0x%08x, val - 0x%04x",
849 (u32
) & ugeth
->p_tx_glbl_pram
->temoder
,
850 in_be16(&ugeth
->p_tx_glbl_pram
->temoder
));
851 ugeth_info("sqptr : addr - 0x%08x, val - 0x%08x",
852 (u32
) & ugeth
->p_tx_glbl_pram
->sqptr
,
853 in_be32(&ugeth
->p_tx_glbl_pram
->sqptr
));
854 ugeth_info("schedulerbasepointer: addr - 0x%08x, val - 0x%08x",
855 (u32
) & ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
856 in_be32(&ugeth
->p_tx_glbl_pram
->
857 schedulerbasepointer
));
858 ugeth_info("txrmonbaseptr: addr - 0x%08x, val - 0x%08x",
859 (u32
) & ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
860 in_be32(&ugeth
->p_tx_glbl_pram
->txrmonbaseptr
));
861 ugeth_info("tstate : addr - 0x%08x, val - 0x%08x",
862 (u32
) & ugeth
->p_tx_glbl_pram
->tstate
,
863 in_be32(&ugeth
->p_tx_glbl_pram
->tstate
));
864 ugeth_info("iphoffset[0] : addr - 0x%08x, val - 0x%02x",
865 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[0],
866 ugeth
->p_tx_glbl_pram
->iphoffset
[0]);
867 ugeth_info("iphoffset[1] : addr - 0x%08x, val - 0x%02x",
868 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[1],
869 ugeth
->p_tx_glbl_pram
->iphoffset
[1]);
870 ugeth_info("iphoffset[2] : addr - 0x%08x, val - 0x%02x",
871 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[2],
872 ugeth
->p_tx_glbl_pram
->iphoffset
[2]);
873 ugeth_info("iphoffset[3] : addr - 0x%08x, val - 0x%02x",
874 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[3],
875 ugeth
->p_tx_glbl_pram
->iphoffset
[3]);
876 ugeth_info("iphoffset[4] : addr - 0x%08x, val - 0x%02x",
877 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[4],
878 ugeth
->p_tx_glbl_pram
->iphoffset
[4]);
879 ugeth_info("iphoffset[5] : addr - 0x%08x, val - 0x%02x",
880 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[5],
881 ugeth
->p_tx_glbl_pram
->iphoffset
[5]);
882 ugeth_info("iphoffset[6] : addr - 0x%08x, val - 0x%02x",
883 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[6],
884 ugeth
->p_tx_glbl_pram
->iphoffset
[6]);
885 ugeth_info("iphoffset[7] : addr - 0x%08x, val - 0x%02x",
886 (u32
) & ugeth
->p_tx_glbl_pram
->iphoffset
[7],
887 ugeth
->p_tx_glbl_pram
->iphoffset
[7]);
888 ugeth_info("vtagtable[0] : addr - 0x%08x, val - 0x%08x",
889 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[0],
890 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[0]));
891 ugeth_info("vtagtable[1] : addr - 0x%08x, val - 0x%08x",
892 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[1],
893 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[1]));
894 ugeth_info("vtagtable[2] : addr - 0x%08x, val - 0x%08x",
895 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[2],
896 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[2]));
897 ugeth_info("vtagtable[3] : addr - 0x%08x, val - 0x%08x",
898 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[3],
899 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[3]));
900 ugeth_info("vtagtable[4] : addr - 0x%08x, val - 0x%08x",
901 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[4],
902 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[4]));
903 ugeth_info("vtagtable[5] : addr - 0x%08x, val - 0x%08x",
904 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[5],
905 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[5]));
906 ugeth_info("vtagtable[6] : addr - 0x%08x, val - 0x%08x",
907 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[6],
908 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[6]));
909 ugeth_info("vtagtable[7] : addr - 0x%08x, val - 0x%08x",
910 (u32
) & ugeth
->p_tx_glbl_pram
->vtagtable
[7],
911 in_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[7]));
912 ugeth_info("tqptr : addr - 0x%08x, val - 0x%08x",
913 (u32
) & ugeth
->p_tx_glbl_pram
->tqptr
,
914 in_be32(&ugeth
->p_tx_glbl_pram
->tqptr
));
916 if (ugeth
->p_rx_glbl_pram
) {
917 ugeth_info("RX global param:");
918 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_glbl_pram
);
919 ugeth_info("remoder : addr - 0x%08x, val - 0x%08x",
920 (u32
) & ugeth
->p_rx_glbl_pram
->remoder
,
921 in_be32(&ugeth
->p_rx_glbl_pram
->remoder
));
922 ugeth_info("rqptr : addr - 0x%08x, val - 0x%08x",
923 (u32
) & ugeth
->p_rx_glbl_pram
->rqptr
,
924 in_be32(&ugeth
->p_rx_glbl_pram
->rqptr
));
925 ugeth_info("typeorlen : addr - 0x%08x, val - 0x%04x",
926 (u32
) & ugeth
->p_rx_glbl_pram
->typeorlen
,
927 in_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
));
928 ugeth_info("rxgstpack : addr - 0x%08x, val - 0x%02x",
929 (u32
) & ugeth
->p_rx_glbl_pram
->rxgstpack
,
930 ugeth
->p_rx_glbl_pram
->rxgstpack
);
931 ugeth_info("rxrmonbaseptr : addr - 0x%08x, val - 0x%08x",
932 (u32
) & ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
933 in_be32(&ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
));
934 ugeth_info("intcoalescingptr: addr - 0x%08x, val - 0x%08x",
935 (u32
) & ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
936 in_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
));
937 ugeth_info("rstate : addr - 0x%08x, val - 0x%02x",
938 (u32
) & ugeth
->p_rx_glbl_pram
->rstate
,
939 ugeth
->p_rx_glbl_pram
->rstate
);
940 ugeth_info("mrblr : addr - 0x%08x, val - 0x%04x",
941 (u32
) & ugeth
->p_rx_glbl_pram
->mrblr
,
942 in_be16(&ugeth
->p_rx_glbl_pram
->mrblr
));
943 ugeth_info("rbdqptr : addr - 0x%08x, val - 0x%08x",
944 (u32
) & ugeth
->p_rx_glbl_pram
->rbdqptr
,
945 in_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
));
946 ugeth_info("mflr : addr - 0x%08x, val - 0x%04x",
947 (u32
) & ugeth
->p_rx_glbl_pram
->mflr
,
948 in_be16(&ugeth
->p_rx_glbl_pram
->mflr
));
949 ugeth_info("minflr : addr - 0x%08x, val - 0x%04x",
950 (u32
) & ugeth
->p_rx_glbl_pram
->minflr
,
951 in_be16(&ugeth
->p_rx_glbl_pram
->minflr
));
952 ugeth_info("maxd1 : addr - 0x%08x, val - 0x%04x",
953 (u32
) & ugeth
->p_rx_glbl_pram
->maxd1
,
954 in_be16(&ugeth
->p_rx_glbl_pram
->maxd1
));
955 ugeth_info("maxd2 : addr - 0x%08x, val - 0x%04x",
956 (u32
) & ugeth
->p_rx_glbl_pram
->maxd2
,
957 in_be16(&ugeth
->p_rx_glbl_pram
->maxd2
));
958 ugeth_info("ecamptr : addr - 0x%08x, val - 0x%08x",
959 (u32
) & ugeth
->p_rx_glbl_pram
->ecamptr
,
960 in_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
));
961 ugeth_info("l2qt : addr - 0x%08x, val - 0x%08x",
962 (u32
) & ugeth
->p_rx_glbl_pram
->l2qt
,
963 in_be32(&ugeth
->p_rx_glbl_pram
->l2qt
));
964 ugeth_info("l3qt[0] : addr - 0x%08x, val - 0x%08x",
965 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[0],
966 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[0]));
967 ugeth_info("l3qt[1] : addr - 0x%08x, val - 0x%08x",
968 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[1],
969 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[1]));
970 ugeth_info("l3qt[2] : addr - 0x%08x, val - 0x%08x",
971 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[2],
972 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[2]));
973 ugeth_info("l3qt[3] : addr - 0x%08x, val - 0x%08x",
974 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[3],
975 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[3]));
976 ugeth_info("l3qt[4] : addr - 0x%08x, val - 0x%08x",
977 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[4],
978 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[4]));
979 ugeth_info("l3qt[5] : addr - 0x%08x, val - 0x%08x",
980 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[5],
981 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[5]));
982 ugeth_info("l3qt[6] : addr - 0x%08x, val - 0x%08x",
983 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[6],
984 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[6]));
985 ugeth_info("l3qt[7] : addr - 0x%08x, val - 0x%08x",
986 (u32
) & ugeth
->p_rx_glbl_pram
->l3qt
[7],
987 in_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[7]));
988 ugeth_info("vlantype : addr - 0x%08x, val - 0x%04x",
989 (u32
) & ugeth
->p_rx_glbl_pram
->vlantype
,
990 in_be16(&ugeth
->p_rx_glbl_pram
->vlantype
));
991 ugeth_info("vlantci : addr - 0x%08x, val - 0x%04x",
992 (u32
) & ugeth
->p_rx_glbl_pram
->vlantci
,
993 in_be16(&ugeth
->p_rx_glbl_pram
->vlantci
));
994 for (i
= 0; i
< 64; i
++)
996 ("addressfiltering[%d]: addr - 0x%08x, val - 0x%02x",
998 (u32
) & ugeth
->p_rx_glbl_pram
->addressfiltering
[i
],
999 ugeth
->p_rx_glbl_pram
->addressfiltering
[i
]);
1000 ugeth_info("exfGlobalParam : addr - 0x%08x, val - 0x%08x",
1001 (u32
) & ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
1002 in_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
));
1004 if (ugeth
->p_send_q_mem_reg
) {
1005 ugeth_info("Send Q memory registers:");
1006 ugeth_info("Base address: 0x%08x",
1007 (u32
) ugeth
->p_send_q_mem_reg
);
1008 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
1009 ugeth_info("SQQD[%d]:", i
);
1010 ugeth_info("Base address: 0x%08x",
1011 (u32
) & ugeth
->p_send_q_mem_reg
->sqqd
[i
]);
1012 mem_disp((u8
*) & ugeth
->p_send_q_mem_reg
->sqqd
[i
],
1013 sizeof(struct ucc_geth_send_queue_qd
));
1016 if (ugeth
->p_scheduler
) {
1017 ugeth_info("Scheduler:");
1018 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_scheduler
);
1019 mem_disp((u8
*) ugeth
->p_scheduler
,
1020 sizeof(*ugeth
->p_scheduler
));
1022 if (ugeth
->p_tx_fw_statistics_pram
) {
1023 ugeth_info("TX FW statistics pram:");
1024 ugeth_info("Base address: 0x%08x",
1025 (u32
) ugeth
->p_tx_fw_statistics_pram
);
1026 mem_disp((u8
*) ugeth
->p_tx_fw_statistics_pram
,
1027 sizeof(*ugeth
->p_tx_fw_statistics_pram
));
1029 if (ugeth
->p_rx_fw_statistics_pram
) {
1030 ugeth_info("RX FW statistics pram:");
1031 ugeth_info("Base address: 0x%08x",
1032 (u32
) ugeth
->p_rx_fw_statistics_pram
);
1033 mem_disp((u8
*) ugeth
->p_rx_fw_statistics_pram
,
1034 sizeof(*ugeth
->p_rx_fw_statistics_pram
));
1036 if (ugeth
->p_rx_irq_coalescing_tbl
) {
1037 ugeth_info("RX IRQ coalescing tables:");
1038 ugeth_info("Base address: 0x%08x",
1039 (u32
) ugeth
->p_rx_irq_coalescing_tbl
);
1040 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1041 ugeth_info("RX IRQ coalescing table entry[%d]:", i
);
1042 ugeth_info("Base address: 0x%08x",
1043 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
1044 coalescingentry
[i
]);
1046 ("interruptcoalescingmaxvalue: addr - 0x%08x, val - 0x%08x",
1047 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
1048 coalescingentry
[i
].interruptcoalescingmaxvalue
,
1049 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
1051 interruptcoalescingmaxvalue
));
1053 ("interruptcoalescingcounter : addr - 0x%08x, val - 0x%08x",
1054 (u32
) & ugeth
->p_rx_irq_coalescing_tbl
->
1055 coalescingentry
[i
].interruptcoalescingcounter
,
1056 in_be32(&ugeth
->p_rx_irq_coalescing_tbl
->
1058 interruptcoalescingcounter
));
1061 if (ugeth
->p_rx_bd_qs_tbl
) {
1062 ugeth_info("RX BD QS tables:");
1063 ugeth_info("Base address: 0x%08x", (u32
) ugeth
->p_rx_bd_qs_tbl
);
1064 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
1065 ugeth_info("RX BD QS table[%d]:", i
);
1066 ugeth_info("Base address: 0x%08x",
1067 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
]);
1069 ("bdbaseptr : addr - 0x%08x, val - 0x%08x",
1070 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
,
1071 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdbaseptr
));
1073 ("bdptr : addr - 0x%08x, val - 0x%08x",
1074 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
,
1075 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].bdptr
));
1077 ("externalbdbaseptr: addr - 0x%08x, val - 0x%08x",
1078 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
1079 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].
1080 externalbdbaseptr
));
1082 ("externalbdptr : addr - 0x%08x, val - 0x%08x",
1083 (u32
) & ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
,
1084 in_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdptr
));
1085 ugeth_info("ucode RX Prefetched BDs:");
1086 ugeth_info("Base address: 0x%08x",
1088 qe_muram_addr(in_be32
1089 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1092 qe_muram_addr(in_be32
1093 (&ugeth
->p_rx_bd_qs_tbl
[i
].
1095 sizeof(struct ucc_geth_rx_prefetched_bds
));
1098 if (ugeth
->p_init_enet_param_shadow
) {
1100 ugeth_info("Init enet param shadow:");
1101 ugeth_info("Base address: 0x%08x",
1102 (u32
) ugeth
->p_init_enet_param_shadow
);
1103 mem_disp((u8
*) ugeth
->p_init_enet_param_shadow
,
1104 sizeof(*ugeth
->p_init_enet_param_shadow
));
1106 size
= sizeof(struct ucc_geth_thread_rx_pram
);
1107 if (ugeth
->ug_info
->rxExtendedFiltering
) {
1109 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
1110 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1111 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
1113 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
1114 if (ugeth
->ug_info
->largestexternallookupkeysize
==
1115 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
1117 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
1120 dump_init_enet_entries(ugeth
,
1121 &(ugeth
->p_init_enet_param_shadow
->
1123 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
1124 sizeof(struct ucc_geth_thread_tx_pram
),
1125 ugeth
->ug_info
->riscTx
, 0);
1126 dump_init_enet_entries(ugeth
,
1127 &(ugeth
->p_init_enet_param_shadow
->
1129 ENET_INIT_PARAM_MAX_ENTRIES_RX
, size
,
1130 ugeth
->ug_info
->riscRx
, 1);
1135 static void init_default_reg_vals(volatile u32
*upsmr_register
,
1136 volatile u32
*maccfg1_register
,
1137 volatile u32
*maccfg2_register
)
1139 out_be32(upsmr_register
, UCC_GETH_UPSMR_INIT
);
1140 out_be32(maccfg1_register
, UCC_GETH_MACCFG1_INIT
);
1141 out_be32(maccfg2_register
, UCC_GETH_MACCFG2_INIT
);
1144 static int init_half_duplex_params(int alt_beb
,
1145 int back_pressure_no_backoff
,
1148 u8 alt_beb_truncation
,
1149 u8 max_retransmissions
,
1150 u8 collision_window
,
1151 volatile u32
*hafdup_register
)
1155 if ((alt_beb_truncation
> HALFDUP_ALT_BEB_TRUNCATION_MAX
) ||
1156 (max_retransmissions
> HALFDUP_MAX_RETRANSMISSION_MAX
) ||
1157 (collision_window
> HALFDUP_COLLISION_WINDOW_MAX
))
1160 value
= (u32
) (alt_beb_truncation
<< HALFDUP_ALT_BEB_TRUNCATION_SHIFT
);
1163 value
|= HALFDUP_ALT_BEB
;
1164 if (back_pressure_no_backoff
)
1165 value
|= HALFDUP_BACK_PRESSURE_NO_BACKOFF
;
1167 value
|= HALFDUP_NO_BACKOFF
;
1169 value
|= HALFDUP_EXCESSIVE_DEFER
;
1171 value
|= (max_retransmissions
<< HALFDUP_MAX_RETRANSMISSION_SHIFT
);
1173 value
|= collision_window
;
1175 out_be32(hafdup_register
, value
);
1179 static int init_inter_frame_gap_params(u8 non_btb_cs_ipg
,
1183 volatile u32
*ipgifg_register
)
1187 /* Non-Back-to-back IPG part 1 should be <= Non-Back-to-back
1189 if (non_btb_cs_ipg
> non_btb_ipg
)
1192 if ((non_btb_cs_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART1_MAX
) ||
1193 (non_btb_ipg
> IPGIFG_NON_BACK_TO_BACK_IFG_PART2_MAX
) ||
1194 /*(min_ifg > IPGIFG_MINIMUM_IFG_ENFORCEMENT_MAX) || */
1195 (btb_ipg
> IPGIFG_BACK_TO_BACK_IFG_MAX
))
1199 ((non_btb_cs_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART1_SHIFT
) &
1200 IPGIFG_NBTB_CS_IPG_MASK
);
1202 ((non_btb_ipg
<< IPGIFG_NON_BACK_TO_BACK_IFG_PART2_SHIFT
) &
1203 IPGIFG_NBTB_IPG_MASK
);
1205 ((min_ifg
<< IPGIFG_MINIMUM_IFG_ENFORCEMENT_SHIFT
) &
1206 IPGIFG_MIN_IFG_MASK
);
1207 value
|= (btb_ipg
& IPGIFG_BTB_IPG_MASK
);
1209 out_be32(ipgifg_register
, value
);
1213 int init_flow_control_params(u32 automatic_flow_control_mode
,
1214 int rx_flow_control_enable
,
1215 int tx_flow_control_enable
,
1217 u16 extension_field
,
1218 volatile u32
*upsmr_register
,
1219 volatile u32
*uempr_register
,
1220 volatile u32
*maccfg1_register
)
1224 /* Set UEMPR register */
1225 value
= (u32
) pause_period
<< UEMPR_PAUSE_TIME_VALUE_SHIFT
;
1226 value
|= (u32
) extension_field
<< UEMPR_EXTENDED_PAUSE_TIME_VALUE_SHIFT
;
1227 out_be32(uempr_register
, value
);
1229 /* Set UPSMR register */
1230 value
= in_be32(upsmr_register
);
1231 value
|= automatic_flow_control_mode
;
1232 out_be32(upsmr_register
, value
);
1234 value
= in_be32(maccfg1_register
);
1235 if (rx_flow_control_enable
)
1236 value
|= MACCFG1_FLOW_RX
;
1237 if (tx_flow_control_enable
)
1238 value
|= MACCFG1_FLOW_TX
;
1239 out_be32(maccfg1_register
, value
);
1244 static int init_hw_statistics_gathering_mode(int enable_hardware_statistics
,
1245 int auto_zero_hardware_statistics
,
1246 volatile u32
*upsmr_register
,
1247 volatile u16
*uescr_register
)
1249 u32 upsmr_value
= 0;
1250 u16 uescr_value
= 0;
1251 /* Enable hardware statistics gathering if requested */
1252 if (enable_hardware_statistics
) {
1253 upsmr_value
= in_be32(upsmr_register
);
1254 upsmr_value
|= UPSMR_HSE
;
1255 out_be32(upsmr_register
, upsmr_value
);
1258 /* Clear hardware statistics counters */
1259 uescr_value
= in_be16(uescr_register
);
1260 uescr_value
|= UESCR_CLRCNT
;
1261 /* Automatically zero hardware statistics counters on read,
1263 if (auto_zero_hardware_statistics
)
1264 uescr_value
|= UESCR_AUTOZ
;
1265 out_be16(uescr_register
, uescr_value
);
1270 static int init_firmware_statistics_gathering_mode(int
1271 enable_tx_firmware_statistics
,
1272 int enable_rx_firmware_statistics
,
1273 volatile u32
*tx_rmon_base_ptr
,
1274 u32 tx_firmware_statistics_structure_address
,
1275 volatile u32
*rx_rmon_base_ptr
,
1276 u32 rx_firmware_statistics_structure_address
,
1277 volatile u16
*temoder_register
,
1278 volatile u32
*remoder_register
)
1280 /* Note: this function does not check if */
1281 /* the parameters it receives are NULL */
1285 if (enable_tx_firmware_statistics
) {
1286 out_be32(tx_rmon_base_ptr
,
1287 tx_firmware_statistics_structure_address
);
1288 temoder_value
= in_be16(temoder_register
);
1289 temoder_value
|= TEMODER_TX_RMON_STATISTICS_ENABLE
;
1290 out_be16(temoder_register
, temoder_value
);
1293 if (enable_rx_firmware_statistics
) {
1294 out_be32(rx_rmon_base_ptr
,
1295 rx_firmware_statistics_structure_address
);
1296 remoder_value
= in_be32(remoder_register
);
1297 remoder_value
|= REMODER_RX_RMON_STATISTICS_ENABLE
;
1298 out_be32(remoder_register
, remoder_value
);
1304 static int init_mac_station_addr_regs(u8 address_byte_0
,
1310 volatile u32
*macstnaddr1_register
,
1311 volatile u32
*macstnaddr2_register
)
1315 /* Example: for a station address of 0x12345678ABCD, */
1316 /* 0x12 is byte 0, 0x34 is byte 1 and so on and 0xCD is byte 5 */
1318 /* MACSTNADDR1 Register: */
1321 /* station address byte 5 station address byte 4 */
1323 /* station address byte 3 station address byte 2 */
1324 value
|= (u32
) ((address_byte_2
<< 0) & 0x000000FF);
1325 value
|= (u32
) ((address_byte_3
<< 8) & 0x0000FF00);
1326 value
|= (u32
) ((address_byte_4
<< 16) & 0x00FF0000);
1327 value
|= (u32
) ((address_byte_5
<< 24) & 0xFF000000);
1329 out_be32(macstnaddr1_register
, value
);
1331 /* MACSTNADDR2 Register: */
1334 /* station address byte 1 station address byte 0 */
1336 /* reserved reserved */
1338 value
|= (u32
) ((address_byte_0
<< 16) & 0x00FF0000);
1339 value
|= (u32
) ((address_byte_1
<< 24) & 0xFF000000);
1341 out_be32(macstnaddr2_register
, value
);
1346 static int init_check_frame_length_mode(int length_check
,
1347 volatile u32
*maccfg2_register
)
1351 value
= in_be32(maccfg2_register
);
1354 value
|= MACCFG2_LC
;
1356 value
&= ~MACCFG2_LC
;
1358 out_be32(maccfg2_register
, value
);
1362 static int init_preamble_length(u8 preamble_length
,
1363 volatile u32
*maccfg2_register
)
1367 if ((preamble_length
< 3) || (preamble_length
> 7))
1370 value
= in_be32(maccfg2_register
);
1371 value
&= ~MACCFG2_PREL_MASK
;
1372 value
|= (preamble_length
<< MACCFG2_PREL_SHIFT
);
1373 out_be32(maccfg2_register
, value
);
1377 static int init_rx_parameters(int reject_broadcast
,
1378 int receive_short_frames
,
1379 int promiscuous
, volatile u32
*upsmr_register
)
1383 value
= in_be32(upsmr_register
);
1385 if (reject_broadcast
)
1388 value
&= ~UPSMR_BRO
;
1390 if (receive_short_frames
)
1393 value
&= ~UPSMR_RSH
;
1398 value
&= ~UPSMR_PRO
;
1400 out_be32(upsmr_register
, value
);
1405 static int init_max_rx_buff_len(u16 max_rx_buf_len
,
1406 volatile u16
*mrblr_register
)
1408 /* max_rx_buf_len value must be a multiple of 128 */
1409 if ((max_rx_buf_len
== 0)
1410 || (max_rx_buf_len
% UCC_GETH_MRBLR_ALIGNMENT
))
1413 out_be16(mrblr_register
, max_rx_buf_len
);
1417 static int init_min_frame_len(u16 min_frame_length
,
1418 volatile u16
*minflr_register
,
1419 volatile u16
*mrblr_register
)
1421 u16 mrblr_value
= 0;
1423 mrblr_value
= in_be16(mrblr_register
);
1424 if (min_frame_length
>= (mrblr_value
- 4))
1427 out_be16(minflr_register
, min_frame_length
);
1431 static int adjust_enet_interface(struct ucc_geth_private
*ugeth
)
1433 struct ucc_geth_info
*ug_info
;
1434 struct ucc_geth
*ug_regs
;
1435 struct ucc_fast
*uf_regs
;
1437 u32 upsmr
, maccfg2
, tbiBaseAddress
;
1440 ugeth_vdbg("%s: IN", __FUNCTION__
);
1442 ug_info
= ugeth
->ug_info
;
1443 ug_regs
= ugeth
->ug_regs
;
1444 uf_regs
= ugeth
->uccf
->uf_regs
;
1447 maccfg2
= in_be32(&ug_regs
->maccfg2
);
1448 maccfg2
&= ~MACCFG2_INTERFACE_MODE_MASK
;
1449 if ((ugeth
->max_speed
== SPEED_10
) ||
1450 (ugeth
->max_speed
== SPEED_100
))
1451 maccfg2
|= MACCFG2_INTERFACE_MODE_NIBBLE
;
1452 else if (ugeth
->max_speed
== SPEED_1000
)
1453 maccfg2
|= MACCFG2_INTERFACE_MODE_BYTE
;
1454 maccfg2
|= ug_info
->padAndCrc
;
1455 out_be32(&ug_regs
->maccfg2
, maccfg2
);
1458 upsmr
= in_be32(&uf_regs
->upsmr
);
1459 upsmr
&= ~(UPSMR_RPM
| UPSMR_R10M
| UPSMR_TBIM
| UPSMR_RMM
);
1460 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1461 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1462 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1463 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1465 switch (ugeth
->max_speed
) {
1467 upsmr
|= UPSMR_R10M
;
1470 if (ugeth
->phy_interface
!= PHY_INTERFACE_MODE_RTBI
)
1474 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1475 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1476 upsmr
|= UPSMR_TBIM
;
1478 out_be32(&uf_regs
->upsmr
, upsmr
);
1480 /* Disable autonegotiation in tbi mode, because by default it
1481 comes up in autonegotiation mode. */
1482 /* Note that this depends on proper setting in utbipar register. */
1483 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_TBI
) ||
1484 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1485 tbiBaseAddress
= in_be32(&ug_regs
->utbipar
);
1486 tbiBaseAddress
&= UTBIPAR_PHY_ADDRESS_MASK
;
1487 tbiBaseAddress
>>= UTBIPAR_PHY_ADDRESS_SHIFT
;
1488 value
= ugeth
->phydev
->bus
->read(ugeth
->phydev
->bus
,
1489 (u8
) tbiBaseAddress
, ENET_TBI_MII_CR
);
1490 value
&= ~0x1000; /* Turn off autonegotiation */
1491 ugeth
->phydev
->bus
->write(ugeth
->phydev
->bus
,
1492 (u8
) tbiBaseAddress
, ENET_TBI_MII_CR
, value
);
1495 init_check_frame_length_mode(ug_info
->lengthCheckRx
, &ug_regs
->maccfg2
);
1497 ret_val
= init_preamble_length(ug_info
->prel
, &ug_regs
->maccfg2
);
1499 if (netif_msg_probe(ugeth
))
1500 ugeth_err("%s: Preamble length must be between 3 and 7 inclusive.",
1508 /* Called every time the controller might need to be made
1509 * aware of new link state. The PHY code conveys this
1510 * information through variables in the ugeth structure, and this
1511 * function converts those variables into the appropriate
1512 * register values, and can bring down the device if needed.
1515 static void adjust_link(struct net_device
*dev
)
1517 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
1518 struct ucc_geth
*ug_regs
;
1519 struct ucc_fast
*uf_regs
;
1520 struct phy_device
*phydev
= ugeth
->phydev
;
1521 unsigned long flags
;
1524 ug_regs
= ugeth
->ug_regs
;
1525 uf_regs
= ugeth
->uccf
->uf_regs
;
1527 spin_lock_irqsave(&ugeth
->lock
, flags
);
1530 u32 tempval
= in_be32(&ug_regs
->maccfg2
);
1531 u32 upsmr
= in_be32(&uf_regs
->upsmr
);
1532 /* Now we make sure that we can be in full duplex mode.
1533 * If not, we operate in half-duplex mode. */
1534 if (phydev
->duplex
!= ugeth
->oldduplex
) {
1536 if (!(phydev
->duplex
))
1537 tempval
&= ~(MACCFG2_FDX
);
1539 tempval
|= MACCFG2_FDX
;
1540 ugeth
->oldduplex
= phydev
->duplex
;
1543 if (phydev
->speed
!= ugeth
->oldspeed
) {
1545 switch (phydev
->speed
) {
1547 tempval
= ((tempval
&
1548 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1549 MACCFG2_INTERFACE_MODE_BYTE
);
1553 tempval
= ((tempval
&
1554 ~(MACCFG2_INTERFACE_MODE_MASK
)) |
1555 MACCFG2_INTERFACE_MODE_NIBBLE
);
1556 /* if reduced mode, re-set UPSMR.R10M */
1557 if ((ugeth
->phy_interface
== PHY_INTERFACE_MODE_RMII
) ||
1558 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII
) ||
1559 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RGMII_ID
) ||
1560 (ugeth
->phy_interface
== PHY_INTERFACE_MODE_RTBI
)) {
1561 if (phydev
->speed
== SPEED_10
)
1562 upsmr
|= UPSMR_R10M
;
1564 upsmr
&= ~(UPSMR_R10M
);
1568 if (netif_msg_link(ugeth
))
1570 "%s: Ack! Speed (%d) is not 10/100/1000!",
1571 dev
->name
, phydev
->speed
);
1574 ugeth
->oldspeed
= phydev
->speed
;
1577 out_be32(&ug_regs
->maccfg2
, tempval
);
1578 out_be32(&uf_regs
->upsmr
, upsmr
);
1580 if (!ugeth
->oldlink
) {
1583 netif_schedule(dev
);
1585 } else if (ugeth
->oldlink
) {
1588 ugeth
->oldspeed
= 0;
1589 ugeth
->oldduplex
= -1;
1592 if (new_state
&& netif_msg_link(ugeth
))
1593 phy_print_status(phydev
);
1595 spin_unlock_irqrestore(&ugeth
->lock
, flags
);
1598 /* Configure the PHY for dev.
1599 * returns 0 if success. -1 if failure
1601 static int init_phy(struct net_device
*dev
)
1603 struct ucc_geth_private
*priv
= netdev_priv(dev
);
1604 struct phy_device
*phydev
;
1605 char phy_id
[BUS_ID_SIZE
];
1609 priv
->oldduplex
= -1;
1611 snprintf(phy_id
, BUS_ID_SIZE
, PHY_ID_FMT
, priv
->ug_info
->mdio_bus
,
1612 priv
->ug_info
->phy_address
);
1614 phydev
= phy_connect(dev
, phy_id
, &adjust_link
, 0, priv
->phy_interface
);
1616 if (IS_ERR(phydev
)) {
1617 printk("%s: Could not attach to PHY\n", dev
->name
);
1618 return PTR_ERR(phydev
);
1621 phydev
->supported
&= (ADVERTISED_10baseT_Half
|
1622 ADVERTISED_10baseT_Full
|
1623 ADVERTISED_100baseT_Half
|
1624 ADVERTISED_100baseT_Full
);
1626 if (priv
->max_speed
== SPEED_1000
)
1627 phydev
->supported
|= ADVERTISED_1000baseT_Full
;
1629 phydev
->advertising
= phydev
->supported
;
1631 priv
->phydev
= phydev
;
1638 static int ugeth_graceful_stop_tx(struct ucc_geth_private
*ugeth
)
1640 struct ucc_fast_private
*uccf
;
1646 /* Mask GRACEFUL STOP TX interrupt bit and clear it */
1647 temp
= in_be32(uccf
->p_uccm
);
1649 out_be32(uccf
->p_uccm
, temp
);
1650 out_be32(uccf
->p_ucce
, UCCE_GRA
); /* clear by writing 1 */
1652 /* Issue host command */
1654 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1655 qe_issue_cmd(QE_GRACEFUL_STOP_TX
, cecr_subblock
,
1656 QE_CR_PROTOCOL_ETHERNET
, 0);
1658 /* Wait for command to complete */
1660 temp
= in_be32(uccf
->p_ucce
);
1661 } while (!(temp
& UCCE_GRA
));
1663 uccf
->stopped_tx
= 1;
1668 static int ugeth_graceful_stop_rx(struct ucc_geth_private
* ugeth
)
1670 struct ucc_fast_private
*uccf
;
1676 /* Clear acknowledge bit */
1677 temp
= ugeth
->p_rx_glbl_pram
->rxgstpack
;
1678 temp
&= ~GRACEFUL_STOP_ACKNOWLEDGE_RX
;
1679 ugeth
->p_rx_glbl_pram
->rxgstpack
= temp
;
1681 /* Keep issuing command and checking acknowledge bit until
1682 it is asserted, according to spec */
1684 /* Issue host command */
1686 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.
1688 qe_issue_cmd(QE_GRACEFUL_STOP_RX
, cecr_subblock
,
1689 QE_CR_PROTOCOL_ETHERNET
, 0);
1691 temp
= ugeth
->p_rx_glbl_pram
->rxgstpack
;
1692 } while (!(temp
& GRACEFUL_STOP_ACKNOWLEDGE_RX
));
1694 uccf
->stopped_rx
= 1;
1699 static int ugeth_restart_tx(struct ucc_geth_private
*ugeth
)
1701 struct ucc_fast_private
*uccf
;
1707 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1708 qe_issue_cmd(QE_RESTART_TX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
, 0);
1709 uccf
->stopped_tx
= 0;
1714 static int ugeth_restart_rx(struct ucc_geth_private
*ugeth
)
1716 struct ucc_fast_private
*uccf
;
1722 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
1723 qe_issue_cmd(QE_RESTART_RX
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
1725 uccf
->stopped_rx
= 0;
1730 static int ugeth_enable(struct ucc_geth_private
*ugeth
, enum comm_dir mode
)
1732 struct ucc_fast_private
*uccf
;
1733 int enabled_tx
, enabled_rx
;
1737 /* check if the UCC number is in range. */
1738 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1739 if (netif_msg_probe(ugeth
))
1740 ugeth_err("%s: ucc_num out of range.", __FUNCTION__
);
1744 enabled_tx
= uccf
->enabled_tx
;
1745 enabled_rx
= uccf
->enabled_rx
;
1747 /* Get Tx and Rx going again, in case this channel was actively
1749 if ((mode
& COMM_DIR_TX
) && (!enabled_tx
) && uccf
->stopped_tx
)
1750 ugeth_restart_tx(ugeth
);
1751 if ((mode
& COMM_DIR_RX
) && (!enabled_rx
) && uccf
->stopped_rx
)
1752 ugeth_restart_rx(ugeth
);
1754 ucc_fast_enable(uccf
, mode
); /* OK to do even if not disabled */
1760 static int ugeth_disable(struct ucc_geth_private
* ugeth
, enum comm_dir mode
)
1762 struct ucc_fast_private
*uccf
;
1766 /* check if the UCC number is in range. */
1767 if (ugeth
->ug_info
->uf_info
.ucc_num
>= UCC_MAX_NUM
) {
1768 if (netif_msg_probe(ugeth
))
1769 ugeth_err("%s: ucc_num out of range.", __FUNCTION__
);
1773 /* Stop any transmissions */
1774 if ((mode
& COMM_DIR_TX
) && uccf
->enabled_tx
&& !uccf
->stopped_tx
)
1775 ugeth_graceful_stop_tx(ugeth
);
1777 /* Stop any receptions */
1778 if ((mode
& COMM_DIR_RX
) && uccf
->enabled_rx
&& !uccf
->stopped_rx
)
1779 ugeth_graceful_stop_rx(ugeth
);
1781 ucc_fast_disable(ugeth
->uccf
, mode
); /* OK to do even if not enabled */
1786 static void ugeth_dump_regs(struct ucc_geth_private
*ugeth
)
1789 ucc_fast_dump_regs(ugeth
->uccf
);
1795 #ifdef CONFIG_UGETH_FILTERING
1796 static int ugeth_ext_filtering_serialize_tad(struct ucc_geth_tad_params
*
1798 struct qe_fltr_tad
*qe_fltr_tad
)
1802 /* Zero serialized TAD */
1803 memset(qe_fltr_tad
, 0, QE_FLTR_TAD_SIZE
);
1805 qe_fltr_tad
->serialized
[0] |= UCC_GETH_TAD_V
; /* Must have this */
1806 if (p_UccGethTadParams
->rx_non_dynamic_extended_features_mode
||
1807 (p_UccGethTadParams
->vtag_op
!= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
)
1808 || (p_UccGethTadParams
->vnontag_op
!=
1809 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
)
1811 qe_fltr_tad
->serialized
[0] |= UCC_GETH_TAD_EF
;
1812 if (p_UccGethTadParams
->reject_frame
)
1813 qe_fltr_tad
->serialized
[0] |= UCC_GETH_TAD_REJ
;
1815 (u16
) (((u16
) p_UccGethTadParams
->
1816 vtag_op
) << UCC_GETH_TAD_VTAG_OP_SHIFT
);
1817 qe_fltr_tad
->serialized
[0] |= (u8
) (temp
>> 8); /* upper bits */
1819 qe_fltr_tad
->serialized
[1] |= (u8
) (temp
& 0x00ff); /* lower bits */
1820 if (p_UccGethTadParams
->vnontag_op
==
1821 UCC_GETH_VLAN_OPERATION_NON_TAGGED_Q_TAG_INSERT
)
1822 qe_fltr_tad
->serialized
[1] |= UCC_GETH_TAD_V_NON_VTAG_OP
;
1823 qe_fltr_tad
->serialized
[1] |=
1824 p_UccGethTadParams
->rqos
<< UCC_GETH_TAD_RQOS_SHIFT
;
1826 qe_fltr_tad
->serialized
[2] |=
1827 p_UccGethTadParams
->vpri
<< UCC_GETH_TAD_V_PRIORITY_SHIFT
;
1829 qe_fltr_tad
->serialized
[2] |= (u8
) (p_UccGethTadParams
->vid
>> 8);
1831 qe_fltr_tad
->serialized
[3] |= (u8
) (p_UccGethTadParams
->vid
& 0x00ff);
1836 static struct enet_addr_container_t
1837 *ugeth_82xx_filtering_get_match_addr_in_hash(struct ucc_geth_private
*ugeth
,
1838 struct enet_addr
*p_enet_addr
)
1840 struct enet_addr_container
*enet_addr_cont
;
1841 struct list_head
*p_lh
;
1846 if ((*p_enet_addr
)[0] & ENET_GROUP_ADDR
) {
1847 p_lh
= &ugeth
->group_hash_q
;
1848 p_counter
= &(ugeth
->numGroupAddrInHash
);
1850 p_lh
= &ugeth
->ind_hash_q
;
1851 p_counter
= &(ugeth
->numIndAddrInHash
);
1859 for (i
= 0; i
< num
; i
++) {
1861 (struct enet_addr_container
*)
1862 ENET_ADDR_CONT_ENTRY(dequeue(p_lh
));
1863 for (j
= ENET_NUM_OCTETS_PER_ADDRESS
- 1; j
>= 0; j
--) {
1864 if ((*p_enet_addr
)[j
] != (enet_addr_cont
->address
)[j
])
1867 return enet_addr_cont
; /* Found */
1869 enqueue(p_lh
, &enet_addr_cont
->node
); /* Put it back */
1874 static int ugeth_82xx_filtering_add_addr_in_hash(struct ucc_geth_private
*ugeth
,
1875 struct enet_addr
*p_enet_addr
)
1877 enum ucc_geth_enet_address_recognition_location location
;
1878 struct enet_addr_container
*enet_addr_cont
;
1879 struct list_head
*p_lh
;
1884 if ((*p_enet_addr
)[0] & ENET_GROUP_ADDR
) {
1885 p_lh
= &ugeth
->group_hash_q
;
1886 limit
= ugeth
->ug_info
->maxGroupAddrInHash
;
1888 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_GROUP_HASH
;
1889 p_counter
= &(ugeth
->numGroupAddrInHash
);
1891 p_lh
= &ugeth
->ind_hash_q
;
1892 limit
= ugeth
->ug_info
->maxIndAddrInHash
;
1894 UCC_GETH_ENET_ADDRESS_RECOGNITION_LOCATION_INDIVIDUAL_HASH
;
1895 p_counter
= &(ugeth
->numIndAddrInHash
);
1898 if ((enet_addr_cont
=
1899 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth
, p_enet_addr
))) {
1900 list_add(p_lh
, &enet_addr_cont
->node
); /* Put it back */
1903 if ((!p_lh
) || (!(*p_counter
< limit
)))
1905 if (!(enet_addr_cont
= get_enet_addr_container()))
1907 for (i
= 0; i
< ENET_NUM_OCTETS_PER_ADDRESS
; i
++)
1908 (enet_addr_cont
->address
)[i
] = (*p_enet_addr
)[i
];
1909 enet_addr_cont
->location
= location
;
1910 enqueue(p_lh
, &enet_addr_cont
->node
); /* Put it back */
1913 hw_add_addr_in_hash(ugeth
, enet_addr_cont
->address
);
1917 static int ugeth_82xx_filtering_clear_addr_in_hash(struct ucc_geth_private
*ugeth
,
1918 struct enet_addr
*p_enet_addr
)
1920 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
1921 struct enet_addr_container
*enet_addr_cont
;
1922 struct ucc_fast_private
*uccf
;
1923 enum comm_dir comm_dir
;
1925 struct list_head
*p_lh
;
1926 u32
*addr_h
, *addr_l
;
1932 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
1937 ugeth_82xx_filtering_get_match_addr_in_hash(ugeth
, p_enet_addr
)))
1940 /* It's been found and removed from the CQ. */
1941 /* Now destroy its container */
1942 put_enet_addr_container(enet_addr_cont
);
1944 if ((*p_enet_addr
)[0] & ENET_GROUP_ADDR
) {
1945 addr_h
= &(p_82xx_addr_filt
->gaddr_h
);
1946 addr_l
= &(p_82xx_addr_filt
->gaddr_l
);
1947 p_lh
= &ugeth
->group_hash_q
;
1948 p_counter
= &(ugeth
->numGroupAddrInHash
);
1950 addr_h
= &(p_82xx_addr_filt
->iaddr_h
);
1951 addr_l
= &(p_82xx_addr_filt
->iaddr_l
);
1952 p_lh
= &ugeth
->ind_hash_q
;
1953 p_counter
= &(ugeth
->numIndAddrInHash
);
1957 if (uccf
->enabled_tx
)
1958 comm_dir
|= COMM_DIR_TX
;
1959 if (uccf
->enabled_rx
)
1960 comm_dir
|= COMM_DIR_RX
;
1962 ugeth_disable(ugeth
, comm_dir
);
1964 /* Clear the hash table. */
1965 out_be32(addr_h
, 0x00000000);
1966 out_be32(addr_l
, 0x00000000);
1968 /* Add all remaining CQ elements back into hash */
1969 num
= --(*p_counter
);
1970 for (i
= 0; i
< num
; i
++) {
1972 (struct enet_addr_container
*)
1973 ENET_ADDR_CONT_ENTRY(dequeue(p_lh
));
1974 hw_add_addr_in_hash(ugeth
, enet_addr_cont
->address
);
1975 enqueue(p_lh
, &enet_addr_cont
->node
); /* Put it back */
1979 ugeth_enable(ugeth
, comm_dir
);
1983 #endif /* CONFIG_UGETH_FILTERING */
1985 static int ugeth_82xx_filtering_clear_all_addr_in_hash(struct ucc_geth_private
*
1990 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
1991 struct ucc_fast_private
*uccf
;
1992 enum comm_dir comm_dir
;
1993 struct list_head
*p_lh
;
1995 u32
*addr_h
, *addr_l
;
2001 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->p_rx_glbl_pram
->
2004 if (enet_addr_type
== ENET_ADDR_TYPE_GROUP
) {
2005 addr_h
= &(p_82xx_addr_filt
->gaddr_h
);
2006 addr_l
= &(p_82xx_addr_filt
->gaddr_l
);
2007 p_lh
= &ugeth
->group_hash_q
;
2008 p_counter
= &(ugeth
->numGroupAddrInHash
);
2009 } else if (enet_addr_type
== ENET_ADDR_TYPE_INDIVIDUAL
) {
2010 addr_h
= &(p_82xx_addr_filt
->iaddr_h
);
2011 addr_l
= &(p_82xx_addr_filt
->iaddr_l
);
2012 p_lh
= &ugeth
->ind_hash_q
;
2013 p_counter
= &(ugeth
->numIndAddrInHash
);
2018 if (uccf
->enabled_tx
)
2019 comm_dir
|= COMM_DIR_TX
;
2020 if (uccf
->enabled_rx
)
2021 comm_dir
|= COMM_DIR_RX
;
2023 ugeth_disable(ugeth
, comm_dir
);
2025 /* Clear the hash table. */
2026 out_be32(addr_h
, 0x00000000);
2027 out_be32(addr_l
, 0x00000000);
2034 /* Delete all remaining CQ elements */
2035 for (i
= 0; i
< num
; i
++)
2036 put_enet_addr_container(ENET_ADDR_CONT_ENTRY(dequeue(p_lh
)));
2041 ugeth_enable(ugeth
, comm_dir
);
2046 #ifdef CONFIG_UGETH_FILTERING
2047 static int ugeth_82xx_filtering_add_addr_in_paddr(struct ucc_geth_private
*ugeth
,
2048 struct enet_addr
*p_enet_addr
,
2053 if ((*p_enet_addr
)[0] & ENET_GROUP_ADDR
)
2055 ("%s: multicast address added to paddr will have no "
2056 "effect - is this what you wanted?",
2059 ugeth
->indAddrRegUsed
[paddr_num
] = 1; /* mark this paddr as used */
2060 /* store address in our database */
2061 for (i
= 0; i
< ENET_NUM_OCTETS_PER_ADDRESS
; i
++)
2062 ugeth
->paddr
[paddr_num
][i
] = (*p_enet_addr
)[i
];
2063 /* put in hardware */
2064 return hw_add_addr_in_paddr(ugeth
, p_enet_addr
, paddr_num
);
2066 #endif /* CONFIG_UGETH_FILTERING */
2068 static int ugeth_82xx_filtering_clear_addr_in_paddr(struct ucc_geth_private
*ugeth
,
2071 ugeth
->indAddrRegUsed
[paddr_num
] = 0; /* mark this paddr as not used */
2072 return hw_clear_addr_in_paddr(ugeth
, paddr_num
);/* clear in hardware */
2075 static void ucc_geth_memclean(struct ucc_geth_private
*ugeth
)
2084 ucc_fast_free(ugeth
->uccf
);
2086 if (ugeth
->p_thread_data_tx
) {
2087 qe_muram_free(ugeth
->thread_dat_tx_offset
);
2088 ugeth
->p_thread_data_tx
= NULL
;
2090 if (ugeth
->p_thread_data_rx
) {
2091 qe_muram_free(ugeth
->thread_dat_rx_offset
);
2092 ugeth
->p_thread_data_rx
= NULL
;
2094 if (ugeth
->p_exf_glbl_param
) {
2095 qe_muram_free(ugeth
->exf_glbl_param_offset
);
2096 ugeth
->p_exf_glbl_param
= NULL
;
2098 if (ugeth
->p_rx_glbl_pram
) {
2099 qe_muram_free(ugeth
->rx_glbl_pram_offset
);
2100 ugeth
->p_rx_glbl_pram
= NULL
;
2102 if (ugeth
->p_tx_glbl_pram
) {
2103 qe_muram_free(ugeth
->tx_glbl_pram_offset
);
2104 ugeth
->p_tx_glbl_pram
= NULL
;
2106 if (ugeth
->p_send_q_mem_reg
) {
2107 qe_muram_free(ugeth
->send_q_mem_reg_offset
);
2108 ugeth
->p_send_q_mem_reg
= NULL
;
2110 if (ugeth
->p_scheduler
) {
2111 qe_muram_free(ugeth
->scheduler_offset
);
2112 ugeth
->p_scheduler
= NULL
;
2114 if (ugeth
->p_tx_fw_statistics_pram
) {
2115 qe_muram_free(ugeth
->tx_fw_statistics_pram_offset
);
2116 ugeth
->p_tx_fw_statistics_pram
= NULL
;
2118 if (ugeth
->p_rx_fw_statistics_pram
) {
2119 qe_muram_free(ugeth
->rx_fw_statistics_pram_offset
);
2120 ugeth
->p_rx_fw_statistics_pram
= NULL
;
2122 if (ugeth
->p_rx_irq_coalescing_tbl
) {
2123 qe_muram_free(ugeth
->rx_irq_coalescing_tbl_offset
);
2124 ugeth
->p_rx_irq_coalescing_tbl
= NULL
;
2126 if (ugeth
->p_rx_bd_qs_tbl
) {
2127 qe_muram_free(ugeth
->rx_bd_qs_tbl_offset
);
2128 ugeth
->p_rx_bd_qs_tbl
= NULL
;
2130 if (ugeth
->p_init_enet_param_shadow
) {
2131 return_init_enet_entries(ugeth
,
2132 &(ugeth
->p_init_enet_param_shadow
->
2134 ENET_INIT_PARAM_MAX_ENTRIES_RX
,
2135 ugeth
->ug_info
->riscRx
, 1);
2136 return_init_enet_entries(ugeth
,
2137 &(ugeth
->p_init_enet_param_shadow
->
2139 ENET_INIT_PARAM_MAX_ENTRIES_TX
,
2140 ugeth
->ug_info
->riscTx
, 0);
2141 kfree(ugeth
->p_init_enet_param_shadow
);
2142 ugeth
->p_init_enet_param_shadow
= NULL
;
2144 for (i
= 0; i
< ugeth
->ug_info
->numQueuesTx
; i
++) {
2145 bd
= ugeth
->p_tx_bd_ring
[i
];
2148 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenTx
[i
]; j
++) {
2149 if (ugeth
->tx_skbuff
[i
][j
]) {
2150 dma_unmap_single(NULL
,
2151 ((struct qe_bd
*)bd
)->buf
,
2152 (in_be32((u32
*)bd
) &
2155 dev_kfree_skb_any(ugeth
->tx_skbuff
[i
][j
]);
2156 ugeth
->tx_skbuff
[i
][j
] = NULL
;
2160 kfree(ugeth
->tx_skbuff
[i
]);
2162 if (ugeth
->p_tx_bd_ring
[i
]) {
2163 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2165 kfree((void *)ugeth
->tx_bd_ring_offset
[i
]);
2166 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2168 qe_muram_free(ugeth
->tx_bd_ring_offset
[i
]);
2169 ugeth
->p_tx_bd_ring
[i
] = NULL
;
2172 for (i
= 0; i
< ugeth
->ug_info
->numQueuesRx
; i
++) {
2173 if (ugeth
->p_rx_bd_ring
[i
]) {
2174 /* Return existing data buffers in ring */
2175 bd
= ugeth
->p_rx_bd_ring
[i
];
2176 for (j
= 0; j
< ugeth
->ug_info
->bdRingLenRx
[i
]; j
++) {
2177 if (ugeth
->rx_skbuff
[i
][j
]) {
2178 dma_unmap_single(NULL
,
2179 ((struct qe_bd
*)bd
)->buf
,
2181 uf_info
.max_rx_buf_length
+
2182 UCC_GETH_RX_DATA_BUF_ALIGNMENT
,
2185 ugeth
->rx_skbuff
[i
][j
]);
2186 ugeth
->rx_skbuff
[i
][j
] = NULL
;
2188 bd
+= sizeof(struct qe_bd
);
2191 kfree(ugeth
->rx_skbuff
[i
]);
2193 if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2195 kfree((void *)ugeth
->rx_bd_ring_offset
[i
]);
2196 else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2198 qe_muram_free(ugeth
->rx_bd_ring_offset
[i
]);
2199 ugeth
->p_rx_bd_ring
[i
] = NULL
;
2202 while (!list_empty(&ugeth
->group_hash_q
))
2203 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2204 (dequeue(&ugeth
->group_hash_q
)));
2205 while (!list_empty(&ugeth
->ind_hash_q
))
2206 put_enet_addr_container(ENET_ADDR_CONT_ENTRY
2207 (dequeue(&ugeth
->ind_hash_q
)));
2211 static void ucc_geth_set_multi(struct net_device
*dev
)
2213 struct ucc_geth_private
*ugeth
;
2214 struct dev_mc_list
*dmi
;
2215 struct ucc_fast
*uf_regs
;
2216 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
2221 ugeth
= netdev_priv(dev
);
2223 uf_regs
= ugeth
->uccf
->uf_regs
;
2225 if (dev
->flags
& IFF_PROMISC
) {
2227 uf_regs
->upsmr
|= UPSMR_PRO
;
2231 uf_regs
->upsmr
&= ~UPSMR_PRO
;
2234 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->
2235 p_rx_glbl_pram
->addressfiltering
;
2237 if (dev
->flags
& IFF_ALLMULTI
) {
2238 /* Catch all multicast addresses, so set the
2239 * filter to all 1's.
2241 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0xffffffff);
2242 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0xffffffff);
2244 /* Clear filter and add the addresses in the list.
2246 out_be32(&p_82xx_addr_filt
->gaddr_h
, 0x0);
2247 out_be32(&p_82xx_addr_filt
->gaddr_l
, 0x0);
2251 for (i
= 0; i
< dev
->mc_count
; i
++, dmi
= dmi
->next
) {
2253 /* Only support group multicast for now.
2255 if (!(dmi
->dmi_addr
[0] & 1))
2258 /* The address in dmi_addr is LSB first,
2259 * and taddr is MSB first. We have to
2260 * copy bytes MSB first from dmi_addr.
2262 mcptr
= (u8
*) dmi
->dmi_addr
+ 5;
2263 tdptr
= (u8
*) tempaddr
;
2264 for (j
= 0; j
< 6; j
++)
2265 *tdptr
++ = *mcptr
--;
2267 /* Ask CPM to run CRC and set bit in
2270 hw_add_addr_in_hash(ugeth
, tempaddr
);
2276 static void ucc_geth_stop(struct ucc_geth_private
*ugeth
)
2278 struct ucc_geth
*ug_regs
= ugeth
->ug_regs
;
2279 struct phy_device
*phydev
= ugeth
->phydev
;
2282 ugeth_vdbg("%s: IN", __FUNCTION__
);
2284 /* Disable the controller */
2285 ugeth_disable(ugeth
, COMM_DIR_RX_AND_TX
);
2287 /* Tell the kernel the link is down */
2290 /* Mask all interrupts */
2291 out_be32(ugeth
->uccf
->p_uccm
, 0x00000000);
2293 /* Clear all interrupts */
2294 out_be32(ugeth
->uccf
->p_ucce
, 0xffffffff);
2296 /* Disable Rx and Tx */
2297 tempval
= in_be32(&ug_regs
->maccfg1
);
2298 tempval
&= ~(MACCFG1_ENABLE_RX
| MACCFG1_ENABLE_TX
);
2299 out_be32(&ug_regs
->maccfg1
, tempval
);
2301 free_irq(ugeth
->ug_info
->uf_info
.irq
, ugeth
->dev
);
2303 ucc_geth_memclean(ugeth
);
2306 static int ucc_struct_init(struct ucc_geth_private
*ugeth
)
2308 struct ucc_geth_info
*ug_info
;
2309 struct ucc_fast_info
*uf_info
;
2312 ug_info
= ugeth
->ug_info
;
2313 uf_info
= &ug_info
->uf_info
;
2315 /* Create CQs for hash tables */
2316 INIT_LIST_HEAD(&ugeth
->group_hash_q
);
2317 INIT_LIST_HEAD(&ugeth
->ind_hash_q
);
2319 if (!((uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) ||
2320 (uf_info
->bd_mem_part
== MEM_PART_MURAM
))) {
2321 if (netif_msg_probe(ugeth
))
2322 ugeth_err("%s: Bad memory partition value.",
2328 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
2329 if ((ug_info
->bdRingLenRx
[i
] < UCC_GETH_RX_BD_RING_SIZE_MIN
) ||
2330 (ug_info
->bdRingLenRx
[i
] %
2331 UCC_GETH_RX_BD_RING_SIZE_ALIGNMENT
)) {
2332 if (netif_msg_probe(ugeth
))
2334 ("%s: Rx BD ring length must be multiple of 4, no smaller than 8.",
2341 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2342 if (ug_info
->bdRingLenTx
[i
] < UCC_GETH_TX_BD_RING_SIZE_MIN
) {
2343 if (netif_msg_probe(ugeth
))
2345 ("%s: Tx BD ring length must be no smaller than 2.",
2352 if ((uf_info
->max_rx_buf_length
== 0) ||
2353 (uf_info
->max_rx_buf_length
% UCC_GETH_MRBLR_ALIGNMENT
)) {
2354 if (netif_msg_probe(ugeth
))
2356 ("%s: max_rx_buf_length must be non-zero multiple of 128.",
2362 if (ug_info
->numQueuesTx
> NUM_TX_QUEUES
) {
2363 if (netif_msg_probe(ugeth
))
2364 ugeth_err("%s: number of tx queues too large.", __FUNCTION__
);
2369 if (ug_info
->numQueuesRx
> NUM_RX_QUEUES
) {
2370 if (netif_msg_probe(ugeth
))
2371 ugeth_err("%s: number of rx queues too large.", __FUNCTION__
);
2376 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++) {
2377 if (ug_info
->l2qt
[i
] >= ug_info
->numQueuesRx
) {
2378 if (netif_msg_probe(ugeth
))
2380 ("%s: VLAN priority table entry must not be"
2381 " larger than number of Rx queues.",
2388 for (i
= 0; i
< UCC_GETH_IP_PRIORITY_MAX
; i
++) {
2389 if (ug_info
->l3qt
[i
] >= ug_info
->numQueuesRx
) {
2390 if (netif_msg_probe(ugeth
))
2392 ("%s: IP priority table entry must not be"
2393 " larger than number of Rx queues.",
2399 if (ug_info
->cam
&& !ug_info
->ecamptr
) {
2400 if (netif_msg_probe(ugeth
))
2401 ugeth_err("%s: If cam mode is chosen, must supply cam ptr.",
2406 if ((ug_info
->numStationAddresses
!=
2407 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
)
2408 && ug_info
->rxExtendedFiltering
) {
2409 if (netif_msg_probe(ugeth
))
2410 ugeth_err("%s: Number of station addresses greater than 1 "
2411 "not allowed in extended parsing mode.",
2416 /* Generate uccm_mask for receive */
2417 uf_info
->uccm_mask
= ug_info
->eventRegMask
& UCCE_OTHER
;/* Errors */
2418 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++)
2419 uf_info
->uccm_mask
|= (UCCE_RXBF_SINGLE_MASK
<< i
);
2421 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++)
2422 uf_info
->uccm_mask
|= (UCCE_TXBF_SINGLE_MASK
<< i
);
2423 /* Initialize the general fast UCC block. */
2424 if (ucc_fast_init(uf_info
, &ugeth
->uccf
)) {
2425 if (netif_msg_probe(ugeth
))
2426 ugeth_err("%s: Failed to init uccf.", __FUNCTION__
);
2427 ucc_geth_memclean(ugeth
);
2431 ugeth
->ug_regs
= (struct ucc_geth
*) ioremap(uf_info
->regs
, sizeof(struct ucc_geth
));
2436 static int ucc_geth_startup(struct ucc_geth_private
*ugeth
)
2438 struct ucc_geth_82xx_address_filtering_pram
*p_82xx_addr_filt
;
2439 struct ucc_geth_init_pram
*p_init_enet_pram
;
2440 struct ucc_fast_private
*uccf
;
2441 struct ucc_geth_info
*ug_info
;
2442 struct ucc_fast_info
*uf_info
;
2443 struct ucc_fast
*uf_regs
;
2444 struct ucc_geth
*ug_regs
;
2445 int ret_val
= -EINVAL
;
2446 u32 remoder
= UCC_GETH_REMODER_INIT
;
2447 u32 init_enet_pram_offset
, cecr_subblock
, command
, maccfg1
;
2448 u32 ifstat
, i
, j
, size
, l2qt
, l3qt
, length
;
2449 u16 temoder
= UCC_GETH_TEMODER_INIT
;
2451 u8 function_code
= 0;
2453 u8 numThreadsRxNumerical
, numThreadsTxNumerical
;
2455 ugeth_vdbg("%s: IN", __FUNCTION__
);
2457 ug_info
= ugeth
->ug_info
;
2458 uf_info
= &ug_info
->uf_info
;
2459 uf_regs
= uccf
->uf_regs
;
2460 ug_regs
= ugeth
->ug_regs
;
2462 switch (ug_info
->numThreadsRx
) {
2463 case UCC_GETH_NUM_OF_THREADS_1
:
2464 numThreadsRxNumerical
= 1;
2466 case UCC_GETH_NUM_OF_THREADS_2
:
2467 numThreadsRxNumerical
= 2;
2469 case UCC_GETH_NUM_OF_THREADS_4
:
2470 numThreadsRxNumerical
= 4;
2472 case UCC_GETH_NUM_OF_THREADS_6
:
2473 numThreadsRxNumerical
= 6;
2475 case UCC_GETH_NUM_OF_THREADS_8
:
2476 numThreadsRxNumerical
= 8;
2479 if (netif_msg_ifup(ugeth
))
2480 ugeth_err("%s: Bad number of Rx threads value.",
2482 ucc_geth_memclean(ugeth
);
2487 switch (ug_info
->numThreadsTx
) {
2488 case UCC_GETH_NUM_OF_THREADS_1
:
2489 numThreadsTxNumerical
= 1;
2491 case UCC_GETH_NUM_OF_THREADS_2
:
2492 numThreadsTxNumerical
= 2;
2494 case UCC_GETH_NUM_OF_THREADS_4
:
2495 numThreadsTxNumerical
= 4;
2497 case UCC_GETH_NUM_OF_THREADS_6
:
2498 numThreadsTxNumerical
= 6;
2500 case UCC_GETH_NUM_OF_THREADS_8
:
2501 numThreadsTxNumerical
= 8;
2504 if (netif_msg_ifup(ugeth
))
2505 ugeth_err("%s: Bad number of Tx threads value.",
2507 ucc_geth_memclean(ugeth
);
2512 /* Calculate rx_extended_features */
2513 ugeth
->rx_non_dynamic_extended_features
= ug_info
->ipCheckSumCheck
||
2514 ug_info
->ipAddressAlignment
||
2515 (ug_info
->numStationAddresses
!=
2516 UCC_GETH_NUM_OF_STATION_ADDRESSES_1
);
2518 ugeth
->rx_extended_features
= ugeth
->rx_non_dynamic_extended_features
||
2519 (ug_info
->vlanOperationTagged
!= UCC_GETH_VLAN_OPERATION_TAGGED_NOP
)
2520 || (ug_info
->vlanOperationNonTagged
!=
2521 UCC_GETH_VLAN_OPERATION_NON_TAGGED_NOP
);
2523 init_default_reg_vals(&uf_regs
->upsmr
,
2524 &ug_regs
->maccfg1
, &ug_regs
->maccfg2
);
2527 /* For more details see the hardware spec. */
2528 init_rx_parameters(ug_info
->bro
,
2529 ug_info
->rsh
, ug_info
->pro
, &uf_regs
->upsmr
);
2531 /* We're going to ignore other registers for now, */
2532 /* except as needed to get up and running */
2535 /* For more details see the hardware spec. */
2536 init_flow_control_params(ug_info
->aufc
,
2537 ug_info
->receiveFlowControl
,
2538 ug_info
->transmitFlowControl
,
2539 ug_info
->pausePeriod
,
2540 ug_info
->extensionField
,
2542 &ug_regs
->uempr
, &ug_regs
->maccfg1
);
2544 maccfg1
= in_be32(&ug_regs
->maccfg1
);
2545 maccfg1
|= MACCFG1_ENABLE_RX
;
2546 maccfg1
|= MACCFG1_ENABLE_TX
;
2547 out_be32(&ug_regs
->maccfg1
, maccfg1
);
2550 /* For more details see the hardware spec. */
2551 ret_val
= init_inter_frame_gap_params(ug_info
->nonBackToBackIfgPart1
,
2552 ug_info
->nonBackToBackIfgPart2
,
2554 miminumInterFrameGapEnforcement
,
2555 ug_info
->backToBackInterFrameGap
,
2558 if (netif_msg_ifup(ugeth
))
2559 ugeth_err("%s: IPGIFG initialization parameter too large.",
2561 ucc_geth_memclean(ugeth
);
2566 /* For more details see the hardware spec. */
2567 ret_val
= init_half_duplex_params(ug_info
->altBeb
,
2568 ug_info
->backPressureNoBackoff
,
2570 ug_info
->excessDefer
,
2571 ug_info
->altBebTruncation
,
2572 ug_info
->maxRetransmission
,
2573 ug_info
->collisionWindow
,
2576 if (netif_msg_ifup(ugeth
))
2577 ugeth_err("%s: Half Duplex initialization parameter too large.",
2579 ucc_geth_memclean(ugeth
);
2584 /* For more details see the hardware spec. */
2585 /* Read only - resets upon read */
2586 ifstat
= in_be32(&ug_regs
->ifstat
);
2589 /* For more details see the hardware spec. */
2590 out_be32(&ug_regs
->uempr
, 0);
2593 /* For more details see the hardware spec. */
2594 init_hw_statistics_gathering_mode((ug_info
->statisticsMode
&
2595 UCC_GETH_STATISTICS_GATHERING_MODE_HARDWARE
),
2596 0, &uf_regs
->upsmr
, &ug_regs
->uescr
);
2598 /* Allocate Tx bds */
2599 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2600 /* Allocate in multiple of
2601 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT,
2602 according to spec */
2603 length
= ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
))
2604 / UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2605 * UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2606 if ((ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
)) %
2607 UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
)
2608 length
+= UCC_GETH_TX_BD_RING_SIZE_MEMORY_ALIGNMENT
;
2609 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2611 if (UCC_GETH_TX_BD_RING_ALIGNMENT
> 4)
2612 align
= UCC_GETH_TX_BD_RING_ALIGNMENT
;
2613 ugeth
->tx_bd_ring_offset
[j
] =
2614 kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2616 if (ugeth
->tx_bd_ring_offset
[j
] != 0)
2617 ugeth
->p_tx_bd_ring
[j
] =
2618 (void*)((ugeth
->tx_bd_ring_offset
[j
] +
2619 align
) & ~(align
- 1));
2620 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2621 ugeth
->tx_bd_ring_offset
[j
] =
2622 qe_muram_alloc(length
,
2623 UCC_GETH_TX_BD_RING_ALIGNMENT
);
2624 if (!IS_ERR_VALUE(ugeth
->tx_bd_ring_offset
[j
]))
2625 ugeth
->p_tx_bd_ring
[j
] =
2626 (u8
*) qe_muram_addr(ugeth
->
2627 tx_bd_ring_offset
[j
]);
2629 if (!ugeth
->p_tx_bd_ring
[j
]) {
2630 if (netif_msg_ifup(ugeth
))
2632 ("%s: Can not allocate memory for Tx bd rings.",
2634 ucc_geth_memclean(ugeth
);
2637 /* Zero unused end of bd ring, according to spec */
2638 memset(ugeth
->p_tx_bd_ring
[j
] +
2639 ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
), 0,
2640 length
- ug_info
->bdRingLenTx
[j
] * sizeof(struct qe_bd
));
2643 /* Allocate Rx bds */
2644 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2645 length
= ug_info
->bdRingLenRx
[j
] * sizeof(struct qe_bd
);
2646 if (uf_info
->bd_mem_part
== MEM_PART_SYSTEM
) {
2648 if (UCC_GETH_RX_BD_RING_ALIGNMENT
> 4)
2649 align
= UCC_GETH_RX_BD_RING_ALIGNMENT
;
2650 ugeth
->rx_bd_ring_offset
[j
] =
2651 kmalloc((u32
) (length
+ align
), GFP_KERNEL
);
2652 if (ugeth
->rx_bd_ring_offset
[j
] != 0)
2653 ugeth
->p_rx_bd_ring
[j
] =
2654 (void*)((ugeth
->rx_bd_ring_offset
[j
] +
2655 align
) & ~(align
- 1));
2656 } else if (uf_info
->bd_mem_part
== MEM_PART_MURAM
) {
2657 ugeth
->rx_bd_ring_offset
[j
] =
2658 qe_muram_alloc(length
,
2659 UCC_GETH_RX_BD_RING_ALIGNMENT
);
2660 if (!IS_ERR_VALUE(ugeth
->rx_bd_ring_offset
[j
]))
2661 ugeth
->p_rx_bd_ring
[j
] =
2662 (u8
*) qe_muram_addr(ugeth
->
2663 rx_bd_ring_offset
[j
]);
2665 if (!ugeth
->p_rx_bd_ring
[j
]) {
2666 if (netif_msg_ifup(ugeth
))
2668 ("%s: Can not allocate memory for Rx bd rings.",
2670 ucc_geth_memclean(ugeth
);
2676 for (j
= 0; j
< ug_info
->numQueuesTx
; j
++) {
2677 /* Setup the skbuff rings */
2678 ugeth
->tx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2679 ugeth
->ug_info
->bdRingLenTx
[j
],
2682 if (ugeth
->tx_skbuff
[j
] == NULL
) {
2683 if (netif_msg_ifup(ugeth
))
2684 ugeth_err("%s: Could not allocate tx_skbuff",
2686 ucc_geth_memclean(ugeth
);
2690 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenTx
[j
]; i
++)
2691 ugeth
->tx_skbuff
[j
][i
] = NULL
;
2693 ugeth
->skb_curtx
[j
] = ugeth
->skb_dirtytx
[j
] = 0;
2694 bd
= ugeth
->confBd
[j
] = ugeth
->txBd
[j
] = ugeth
->p_tx_bd_ring
[j
];
2695 for (i
= 0; i
< ug_info
->bdRingLenTx
[j
]; i
++) {
2696 /* clear bd buffer */
2697 out_be32(&((struct qe_bd
*)bd
)->buf
, 0);
2698 /* set bd status and length */
2699 out_be32((u32
*)bd
, 0);
2700 bd
+= sizeof(struct qe_bd
);
2702 bd
-= sizeof(struct qe_bd
);
2703 /* set bd status and length */
2704 out_be32((u32
*)bd
, T_W
); /* for last BD set Wrap bit */
2708 for (j
= 0; j
< ug_info
->numQueuesRx
; j
++) {
2709 /* Setup the skbuff rings */
2710 ugeth
->rx_skbuff
[j
] = kmalloc(sizeof(struct sk_buff
*) *
2711 ugeth
->ug_info
->bdRingLenRx
[j
],
2714 if (ugeth
->rx_skbuff
[j
] == NULL
) {
2715 if (netif_msg_ifup(ugeth
))
2716 ugeth_err("%s: Could not allocate rx_skbuff",
2718 ucc_geth_memclean(ugeth
);
2722 for (i
= 0; i
< ugeth
->ug_info
->bdRingLenRx
[j
]; i
++)
2723 ugeth
->rx_skbuff
[j
][i
] = NULL
;
2725 ugeth
->skb_currx
[j
] = 0;
2726 bd
= ugeth
->rxBd
[j
] = ugeth
->p_rx_bd_ring
[j
];
2727 for (i
= 0; i
< ug_info
->bdRingLenRx
[j
]; i
++) {
2728 /* set bd status and length */
2729 out_be32((u32
*)bd
, R_I
);
2730 /* clear bd buffer */
2731 out_be32(&((struct qe_bd
*)bd
)->buf
, 0);
2732 bd
+= sizeof(struct qe_bd
);
2734 bd
-= sizeof(struct qe_bd
);
2735 /* set bd status and length */
2736 out_be32((u32
*)bd
, R_W
); /* for last BD set Wrap bit */
2742 /* Tx global PRAM */
2743 /* Allocate global tx parameter RAM page */
2744 ugeth
->tx_glbl_pram_offset
=
2745 qe_muram_alloc(sizeof(struct ucc_geth_tx_global_pram
),
2746 UCC_GETH_TX_GLOBAL_PRAM_ALIGNMENT
);
2747 if (IS_ERR_VALUE(ugeth
->tx_glbl_pram_offset
)) {
2748 if (netif_msg_ifup(ugeth
))
2750 ("%s: Can not allocate DPRAM memory for p_tx_glbl_pram.",
2752 ucc_geth_memclean(ugeth
);
2755 ugeth
->p_tx_glbl_pram
=
2756 (struct ucc_geth_tx_global_pram
*) qe_muram_addr(ugeth
->
2757 tx_glbl_pram_offset
);
2758 /* Zero out p_tx_glbl_pram */
2759 memset(ugeth
->p_tx_glbl_pram
, 0, sizeof(struct ucc_geth_tx_global_pram
));
2761 /* Fill global PRAM */
2764 /* Size varies with number of Tx threads */
2765 ugeth
->thread_dat_tx_offset
=
2766 qe_muram_alloc(numThreadsTxNumerical
*
2767 sizeof(struct ucc_geth_thread_data_tx
) +
2768 32 * (numThreadsTxNumerical
== 1),
2769 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2770 if (IS_ERR_VALUE(ugeth
->thread_dat_tx_offset
)) {
2771 if (netif_msg_ifup(ugeth
))
2773 ("%s: Can not allocate DPRAM memory for p_thread_data_tx.",
2775 ucc_geth_memclean(ugeth
);
2779 ugeth
->p_thread_data_tx
=
2780 (struct ucc_geth_thread_data_tx
*) qe_muram_addr(ugeth
->
2781 thread_dat_tx_offset
);
2782 out_be32(&ugeth
->p_tx_glbl_pram
->tqptr
, ugeth
->thread_dat_tx_offset
);
2785 for (i
= 0; i
< UCC_GETH_TX_VTAG_TABLE_ENTRY_MAX
; i
++)
2786 out_be32(&ugeth
->p_tx_glbl_pram
->vtagtable
[i
],
2787 ug_info
->vtagtable
[i
]);
2790 for (i
= 0; i
< TX_IP_OFFSET_ENTRY_MAX
; i
++)
2791 ugeth
->p_tx_glbl_pram
->iphoffset
[i
] = ug_info
->iphoffset
[i
];
2794 /* Size varies with number of Tx queues */
2795 ugeth
->send_q_mem_reg_offset
=
2796 qe_muram_alloc(ug_info
->numQueuesTx
*
2797 sizeof(struct ucc_geth_send_queue_qd
),
2798 UCC_GETH_SEND_QUEUE_QUEUE_DESCRIPTOR_ALIGNMENT
);
2799 if (IS_ERR_VALUE(ugeth
->send_q_mem_reg_offset
)) {
2800 if (netif_msg_ifup(ugeth
))
2802 ("%s: Can not allocate DPRAM memory for p_send_q_mem_reg.",
2804 ucc_geth_memclean(ugeth
);
2808 ugeth
->p_send_q_mem_reg
=
2809 (struct ucc_geth_send_queue_mem_region
*) qe_muram_addr(ugeth
->
2810 send_q_mem_reg_offset
);
2811 out_be32(&ugeth
->p_tx_glbl_pram
->sqptr
, ugeth
->send_q_mem_reg_offset
);
2813 /* Setup the table */
2814 /* Assume BD rings are already established */
2815 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
2817 ugeth
->p_tx_bd_ring
[i
] + (ug_info
->bdRingLenTx
[i
] -
2818 1) * sizeof(struct qe_bd
);
2819 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
2820 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2821 (u32
) virt_to_phys(ugeth
->p_tx_bd_ring
[i
]));
2822 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2823 last_bd_completed_address
,
2824 (u32
) virt_to_phys(endOfRing
));
2825 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
2827 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].bd_ring_base
,
2828 (u32
) immrbar_virt_to_phys(ugeth
->
2830 out_be32(&ugeth
->p_send_q_mem_reg
->sqqd
[i
].
2831 last_bd_completed_address
,
2832 (u32
) immrbar_virt_to_phys(endOfRing
));
2836 /* schedulerbasepointer */
2838 if (ug_info
->numQueuesTx
> 1) {
2839 /* scheduler exists only if more than 1 tx queue */
2840 ugeth
->scheduler_offset
=
2841 qe_muram_alloc(sizeof(struct ucc_geth_scheduler
),
2842 UCC_GETH_SCHEDULER_ALIGNMENT
);
2843 if (IS_ERR_VALUE(ugeth
->scheduler_offset
)) {
2844 if (netif_msg_ifup(ugeth
))
2846 ("%s: Can not allocate DPRAM memory for p_scheduler.",
2848 ucc_geth_memclean(ugeth
);
2852 ugeth
->p_scheduler
=
2853 (struct ucc_geth_scheduler
*) qe_muram_addr(ugeth
->
2855 out_be32(&ugeth
->p_tx_glbl_pram
->schedulerbasepointer
,
2856 ugeth
->scheduler_offset
);
2857 /* Zero out p_scheduler */
2858 memset(ugeth
->p_scheduler
, 0, sizeof(struct ucc_geth_scheduler
));
2860 /* Set values in scheduler */
2861 out_be32(&ugeth
->p_scheduler
->mblinterval
,
2862 ug_info
->mblinterval
);
2863 out_be16(&ugeth
->p_scheduler
->nortsrbytetime
,
2864 ug_info
->nortsrbytetime
);
2865 ugeth
->p_scheduler
->fracsiz
= ug_info
->fracsiz
;
2866 ugeth
->p_scheduler
->strictpriorityq
= ug_info
->strictpriorityq
;
2867 ugeth
->p_scheduler
->txasap
= ug_info
->txasap
;
2868 ugeth
->p_scheduler
->extrabw
= ug_info
->extrabw
;
2869 for (i
= 0; i
< NUM_TX_QUEUES
; i
++)
2870 ugeth
->p_scheduler
->weightfactor
[i
] =
2871 ug_info
->weightfactor
[i
];
2873 /* Set pointers to cpucount registers in scheduler */
2874 ugeth
->p_cpucount
[0] = &(ugeth
->p_scheduler
->cpucount0
);
2875 ugeth
->p_cpucount
[1] = &(ugeth
->p_scheduler
->cpucount1
);
2876 ugeth
->p_cpucount
[2] = &(ugeth
->p_scheduler
->cpucount2
);
2877 ugeth
->p_cpucount
[3] = &(ugeth
->p_scheduler
->cpucount3
);
2878 ugeth
->p_cpucount
[4] = &(ugeth
->p_scheduler
->cpucount4
);
2879 ugeth
->p_cpucount
[5] = &(ugeth
->p_scheduler
->cpucount5
);
2880 ugeth
->p_cpucount
[6] = &(ugeth
->p_scheduler
->cpucount6
);
2881 ugeth
->p_cpucount
[7] = &(ugeth
->p_scheduler
->cpucount7
);
2884 /* schedulerbasepointer */
2885 /* TxRMON_PTR (statistics) */
2887 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
) {
2888 ugeth
->tx_fw_statistics_pram_offset
=
2889 qe_muram_alloc(sizeof
2890 (struct ucc_geth_tx_firmware_statistics_pram
),
2891 UCC_GETH_TX_STATISTICS_ALIGNMENT
);
2892 if (IS_ERR_VALUE(ugeth
->tx_fw_statistics_pram_offset
)) {
2893 if (netif_msg_ifup(ugeth
))
2895 ("%s: Can not allocate DPRAM memory for"
2896 " p_tx_fw_statistics_pram.",
2898 ucc_geth_memclean(ugeth
);
2901 ugeth
->p_tx_fw_statistics_pram
=
2902 (struct ucc_geth_tx_firmware_statistics_pram
*)
2903 qe_muram_addr(ugeth
->tx_fw_statistics_pram_offset
);
2904 /* Zero out p_tx_fw_statistics_pram */
2905 memset(ugeth
->p_tx_fw_statistics_pram
,
2906 0, sizeof(struct ucc_geth_tx_firmware_statistics_pram
));
2910 /* Already has speed set */
2912 if (ug_info
->numQueuesTx
> 1)
2913 temoder
|= TEMODER_SCHEDULER_ENABLE
;
2914 if (ug_info
->ipCheckSumGenerate
)
2915 temoder
|= TEMODER_IP_CHECKSUM_GENERATE
;
2916 temoder
|= ((ug_info
->numQueuesTx
- 1) << TEMODER_NUM_OF_QUEUES_SHIFT
);
2917 out_be16(&ugeth
->p_tx_glbl_pram
->temoder
, temoder
);
2919 test
= in_be16(&ugeth
->p_tx_glbl_pram
->temoder
);
2921 /* Function code register value to be used later */
2922 function_code
= QE_BMR_BYTE_ORDER_BO_MOT
| UCC_FAST_FUNCTION_CODE_GBL
;
2923 /* Required for QE */
2925 /* function code register */
2926 out_be32(&ugeth
->p_tx_glbl_pram
->tstate
, ((u32
) function_code
) << 24);
2928 /* Rx global PRAM */
2929 /* Allocate global rx parameter RAM page */
2930 ugeth
->rx_glbl_pram_offset
=
2931 qe_muram_alloc(sizeof(struct ucc_geth_rx_global_pram
),
2932 UCC_GETH_RX_GLOBAL_PRAM_ALIGNMENT
);
2933 if (IS_ERR_VALUE(ugeth
->rx_glbl_pram_offset
)) {
2934 if (netif_msg_ifup(ugeth
))
2936 ("%s: Can not allocate DPRAM memory for p_rx_glbl_pram.",
2938 ucc_geth_memclean(ugeth
);
2941 ugeth
->p_rx_glbl_pram
=
2942 (struct ucc_geth_rx_global_pram
*) qe_muram_addr(ugeth
->
2943 rx_glbl_pram_offset
);
2944 /* Zero out p_rx_glbl_pram */
2945 memset(ugeth
->p_rx_glbl_pram
, 0, sizeof(struct ucc_geth_rx_global_pram
));
2947 /* Fill global PRAM */
2950 /* Size varies with number of Rx threads */
2951 ugeth
->thread_dat_rx_offset
=
2952 qe_muram_alloc(numThreadsRxNumerical
*
2953 sizeof(struct ucc_geth_thread_data_rx
),
2954 UCC_GETH_THREAD_DATA_ALIGNMENT
);
2955 if (IS_ERR_VALUE(ugeth
->thread_dat_rx_offset
)) {
2956 if (netif_msg_ifup(ugeth
))
2958 ("%s: Can not allocate DPRAM memory for p_thread_data_rx.",
2960 ucc_geth_memclean(ugeth
);
2964 ugeth
->p_thread_data_rx
=
2965 (struct ucc_geth_thread_data_rx
*) qe_muram_addr(ugeth
->
2966 thread_dat_rx_offset
);
2967 out_be32(&ugeth
->p_rx_glbl_pram
->rqptr
, ugeth
->thread_dat_rx_offset
);
2970 out_be16(&ugeth
->p_rx_glbl_pram
->typeorlen
, ug_info
->typeorlen
);
2972 /* rxrmonbaseptr (statistics) */
2974 statisticsMode
& UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
) {
2975 ugeth
->rx_fw_statistics_pram_offset
=
2976 qe_muram_alloc(sizeof
2977 (struct ucc_geth_rx_firmware_statistics_pram
),
2978 UCC_GETH_RX_STATISTICS_ALIGNMENT
);
2979 if (IS_ERR_VALUE(ugeth
->rx_fw_statistics_pram_offset
)) {
2980 if (netif_msg_ifup(ugeth
))
2982 ("%s: Can not allocate DPRAM memory for"
2983 " p_rx_fw_statistics_pram.", __FUNCTION__
);
2984 ucc_geth_memclean(ugeth
);
2987 ugeth
->p_rx_fw_statistics_pram
=
2988 (struct ucc_geth_rx_firmware_statistics_pram
*)
2989 qe_muram_addr(ugeth
->rx_fw_statistics_pram_offset
);
2990 /* Zero out p_rx_fw_statistics_pram */
2991 memset(ugeth
->p_rx_fw_statistics_pram
, 0,
2992 sizeof(struct ucc_geth_rx_firmware_statistics_pram
));
2995 /* intCoalescingPtr */
2997 /* Size varies with number of Rx queues */
2998 ugeth
->rx_irq_coalescing_tbl_offset
=
2999 qe_muram_alloc(ug_info
->numQueuesRx
*
3000 sizeof(struct ucc_geth_rx_interrupt_coalescing_entry
)
3001 + 4, UCC_GETH_RX_INTERRUPT_COALESCING_ALIGNMENT
);
3002 if (IS_ERR_VALUE(ugeth
->rx_irq_coalescing_tbl_offset
)) {
3003 if (netif_msg_ifup(ugeth
))
3005 ("%s: Can not allocate DPRAM memory for"
3006 " p_rx_irq_coalescing_tbl.", __FUNCTION__
);
3007 ucc_geth_memclean(ugeth
);
3011 ugeth
->p_rx_irq_coalescing_tbl
=
3012 (struct ucc_geth_rx_interrupt_coalescing_table
*)
3013 qe_muram_addr(ugeth
->rx_irq_coalescing_tbl_offset
);
3014 out_be32(&ugeth
->p_rx_glbl_pram
->intcoalescingptr
,
3015 ugeth
->rx_irq_coalescing_tbl_offset
);
3017 /* Fill interrupt coalescing table */
3018 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3019 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
3020 interruptcoalescingmaxvalue
,
3021 ug_info
->interruptcoalescingmaxvalue
[i
]);
3022 out_be32(&ugeth
->p_rx_irq_coalescing_tbl
->coalescingentry
[i
].
3023 interruptcoalescingcounter
,
3024 ug_info
->interruptcoalescingmaxvalue
[i
]);
3028 init_max_rx_buff_len(uf_info
->max_rx_buf_length
,
3029 &ugeth
->p_rx_glbl_pram
->mrblr
);
3031 out_be16(&ugeth
->p_rx_glbl_pram
->mflr
, ug_info
->maxFrameLength
);
3033 init_min_frame_len(ug_info
->minFrameLength
,
3034 &ugeth
->p_rx_glbl_pram
->minflr
,
3035 &ugeth
->p_rx_glbl_pram
->mrblr
);
3037 out_be16(&ugeth
->p_rx_glbl_pram
->maxd1
, ug_info
->maxD1Length
);
3039 out_be16(&ugeth
->p_rx_glbl_pram
->maxd2
, ug_info
->maxD2Length
);
3043 for (i
= 0; i
< UCC_GETH_VLAN_PRIORITY_MAX
; i
++)
3044 l2qt
|= (ug_info
->l2qt
[i
] << (28 - 4 * i
));
3045 out_be32(&ugeth
->p_rx_glbl_pram
->l2qt
, l2qt
);
3048 for (j
= 0; j
< UCC_GETH_IP_PRIORITY_MAX
; j
+= 8) {
3050 for (i
= 0; i
< 8; i
++)
3051 l3qt
|= (ug_info
->l3qt
[j
+ i
] << (28 - 4 * i
));
3052 out_be32(&ugeth
->p_rx_glbl_pram
->l3qt
[j
/8], l3qt
);
3056 out_be16(&ugeth
->p_rx_glbl_pram
->vlantype
, ug_info
->vlantype
);
3059 out_be16(&ugeth
->p_rx_glbl_pram
->vlantci
, ug_info
->vlantci
);
3062 out_be32(&ugeth
->p_rx_glbl_pram
->ecamptr
, ug_info
->ecamptr
);
3065 /* Size varies with number of Rx queues */
3066 ugeth
->rx_bd_qs_tbl_offset
=
3067 qe_muram_alloc(ug_info
->numQueuesRx
*
3068 (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
3069 sizeof(struct ucc_geth_rx_prefetched_bds
)),
3070 UCC_GETH_RX_BD_QUEUES_ALIGNMENT
);
3071 if (IS_ERR_VALUE(ugeth
->rx_bd_qs_tbl_offset
)) {
3072 if (netif_msg_ifup(ugeth
))
3074 ("%s: Can not allocate DPRAM memory for p_rx_bd_qs_tbl.",
3076 ucc_geth_memclean(ugeth
);
3080 ugeth
->p_rx_bd_qs_tbl
=
3081 (struct ucc_geth_rx_bd_queues_entry
*) qe_muram_addr(ugeth
->
3082 rx_bd_qs_tbl_offset
);
3083 out_be32(&ugeth
->p_rx_glbl_pram
->rbdqptr
, ugeth
->rx_bd_qs_tbl_offset
);
3084 /* Zero out p_rx_bd_qs_tbl */
3085 memset(ugeth
->p_rx_bd_qs_tbl
,
3087 ug_info
->numQueuesRx
* (sizeof(struct ucc_geth_rx_bd_queues_entry
) +
3088 sizeof(struct ucc_geth_rx_prefetched_bds
)));
3090 /* Setup the table */
3091 /* Assume BD rings are already established */
3092 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3093 if (ugeth
->ug_info
->uf_info
.bd_mem_part
== MEM_PART_SYSTEM
) {
3094 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
3095 (u32
) virt_to_phys(ugeth
->p_rx_bd_ring
[i
]));
3096 } else if (ugeth
->ug_info
->uf_info
.bd_mem_part
==
3098 out_be32(&ugeth
->p_rx_bd_qs_tbl
[i
].externalbdbaseptr
,
3099 (u32
) immrbar_virt_to_phys(ugeth
->
3102 /* rest of fields handled by QE */
3106 /* Already has speed set */
3108 if (ugeth
->rx_extended_features
)
3109 remoder
|= REMODER_RX_EXTENDED_FEATURES
;
3110 if (ug_info
->rxExtendedFiltering
)
3111 remoder
|= REMODER_RX_EXTENDED_FILTERING
;
3112 if (ug_info
->dynamicMaxFrameLength
)
3113 remoder
|= REMODER_DYNAMIC_MAX_FRAME_LENGTH
;
3114 if (ug_info
->dynamicMinFrameLength
)
3115 remoder
|= REMODER_DYNAMIC_MIN_FRAME_LENGTH
;
3117 ug_info
->vlanOperationTagged
<< REMODER_VLAN_OPERATION_TAGGED_SHIFT
;
3120 vlanOperationNonTagged
<< REMODER_VLAN_OPERATION_NON_TAGGED_SHIFT
;
3121 remoder
|= ug_info
->rxQoSMode
<< REMODER_RX_QOS_MODE_SHIFT
;
3122 remoder
|= ((ug_info
->numQueuesRx
- 1) << REMODER_NUM_OF_QUEUES_SHIFT
);
3123 if (ug_info
->ipCheckSumCheck
)
3124 remoder
|= REMODER_IP_CHECKSUM_CHECK
;
3125 if (ug_info
->ipAddressAlignment
)
3126 remoder
|= REMODER_IP_ADDRESS_ALIGNMENT
;
3127 out_be32(&ugeth
->p_rx_glbl_pram
->remoder
, remoder
);
3129 /* Note that this function must be called */
3130 /* ONLY AFTER p_tx_fw_statistics_pram */
3131 /* andp_UccGethRxFirmwareStatisticsPram are allocated ! */
3132 init_firmware_statistics_gathering_mode((ug_info
->
3134 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_TX
),
3135 (ug_info
->statisticsMode
&
3136 UCC_GETH_STATISTICS_GATHERING_MODE_FIRMWARE_RX
),
3137 &ugeth
->p_tx_glbl_pram
->txrmonbaseptr
,
3138 ugeth
->tx_fw_statistics_pram_offset
,
3139 &ugeth
->p_rx_glbl_pram
->rxrmonbaseptr
,
3140 ugeth
->rx_fw_statistics_pram_offset
,
3141 &ugeth
->p_tx_glbl_pram
->temoder
,
3142 &ugeth
->p_rx_glbl_pram
->remoder
);
3144 /* function code register */
3145 ugeth
->p_rx_glbl_pram
->rstate
= function_code
;
3147 /* initialize extended filtering */
3148 if (ug_info
->rxExtendedFiltering
) {
3149 if (!ug_info
->extendedFilteringChainPointer
) {
3150 if (netif_msg_ifup(ugeth
))
3151 ugeth_err("%s: Null Extended Filtering Chain Pointer.",
3153 ucc_geth_memclean(ugeth
);
3157 /* Allocate memory for extended filtering Mode Global
3159 ugeth
->exf_glbl_param_offset
=
3160 qe_muram_alloc(sizeof(struct ucc_geth_exf_global_pram
),
3161 UCC_GETH_RX_EXTENDED_FILTERING_GLOBAL_PARAMETERS_ALIGNMENT
);
3162 if (IS_ERR_VALUE(ugeth
->exf_glbl_param_offset
)) {
3163 if (netif_msg_ifup(ugeth
))
3165 ("%s: Can not allocate DPRAM memory for"
3166 " p_exf_glbl_param.", __FUNCTION__
);
3167 ucc_geth_memclean(ugeth
);
3171 ugeth
->p_exf_glbl_param
=
3172 (struct ucc_geth_exf_global_pram
*) qe_muram_addr(ugeth
->
3173 exf_glbl_param_offset
);
3174 out_be32(&ugeth
->p_rx_glbl_pram
->exfGlobalParam
,
3175 ugeth
->exf_glbl_param_offset
);
3176 out_be32(&ugeth
->p_exf_glbl_param
->l2pcdptr
,
3177 (u32
) ug_info
->extendedFilteringChainPointer
);
3179 } else { /* initialize 82xx style address filtering */
3181 /* Init individual address recognition registers to disabled */
3183 for (j
= 0; j
< NUM_OF_PADDRS
; j
++)
3184 ugeth_82xx_filtering_clear_addr_in_paddr(ugeth
, (u8
) j
);
3187 (struct ucc_geth_82xx_address_filtering_pram
*) ugeth
->
3188 p_rx_glbl_pram
->addressfiltering
;
3190 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
3191 ENET_ADDR_TYPE_GROUP
);
3192 ugeth_82xx_filtering_clear_all_addr_in_hash(ugeth
,
3193 ENET_ADDR_TYPE_INDIVIDUAL
);
3197 * Initialize UCC at QE level
3200 command
= QE_INIT_TX_RX
;
3202 /* Allocate shadow InitEnet command parameter structure.
3203 * This is needed because after the InitEnet command is executed,
3204 * the structure in DPRAM is released, because DPRAM is a premium
3206 * This shadow structure keeps a copy of what was done so that the
3207 * allocated resources can be released when the channel is freed.
3209 if (!(ugeth
->p_init_enet_param_shadow
=
3210 kmalloc(sizeof(struct ucc_geth_init_pram
), GFP_KERNEL
))) {
3211 if (netif_msg_ifup(ugeth
))
3213 ("%s: Can not allocate memory for"
3214 " p_UccInitEnetParamShadows.", __FUNCTION__
);
3215 ucc_geth_memclean(ugeth
);
3218 /* Zero out *p_init_enet_param_shadow */
3219 memset((char *)ugeth
->p_init_enet_param_shadow
,
3220 0, sizeof(struct ucc_geth_init_pram
));
3222 /* Fill shadow InitEnet command parameter structure */
3224 ugeth
->p_init_enet_param_shadow
->resinit1
=
3225 ENET_INIT_PARAM_MAGIC_RES_INIT1
;
3226 ugeth
->p_init_enet_param_shadow
->resinit2
=
3227 ENET_INIT_PARAM_MAGIC_RES_INIT2
;
3228 ugeth
->p_init_enet_param_shadow
->resinit3
=
3229 ENET_INIT_PARAM_MAGIC_RES_INIT3
;
3230 ugeth
->p_init_enet_param_shadow
->resinit4
=
3231 ENET_INIT_PARAM_MAGIC_RES_INIT4
;
3232 ugeth
->p_init_enet_param_shadow
->resinit5
=
3233 ENET_INIT_PARAM_MAGIC_RES_INIT5
;
3234 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
3235 ((u32
) ug_info
->numThreadsRx
) << ENET_INIT_PARAM_RGF_SHIFT
;
3236 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
3237 ((u32
) ug_info
->numThreadsTx
) << ENET_INIT_PARAM_TGF_SHIFT
;
3239 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
|=
3240 ugeth
->rx_glbl_pram_offset
| ug_info
->riscRx
;
3241 if ((ug_info
->largestexternallookupkeysize
!=
3242 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE
)
3243 && (ug_info
->largestexternallookupkeysize
!=
3244 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
3245 && (ug_info
->largestexternallookupkeysize
!=
3246 QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)) {
3247 if (netif_msg_ifup(ugeth
))
3248 ugeth_err("%s: Invalid largest External Lookup Key Size.",
3250 ucc_geth_memclean(ugeth
);
3253 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
=
3254 ug_info
->largestexternallookupkeysize
;
3255 size
= sizeof(struct ucc_geth_thread_rx_pram
);
3256 if (ug_info
->rxExtendedFiltering
) {
3257 size
+= THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING
;
3258 if (ug_info
->largestexternallookupkeysize
==
3259 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES
)
3261 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_8
;
3262 if (ug_info
->largestexternallookupkeysize
==
3263 QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES
)
3265 THREAD_RX_PRAM_ADDITIONAL_FOR_EXTENDED_FILTERING_16
;
3268 if ((ret_val
= fill_init_enet_entries(ugeth
, &(ugeth
->
3269 p_init_enet_param_shadow
->rxthread
[0]),
3270 (u8
) (numThreadsRxNumerical
+ 1)
3271 /* Rx needs one extra for terminator */
3272 , size
, UCC_GETH_THREAD_RX_PRAM_ALIGNMENT
,
3273 ug_info
->riscRx
, 1)) != 0) {
3274 if (netif_msg_ifup(ugeth
))
3275 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3277 ucc_geth_memclean(ugeth
);
3281 ugeth
->p_init_enet_param_shadow
->txglobal
=
3282 ugeth
->tx_glbl_pram_offset
| ug_info
->riscTx
;
3284 fill_init_enet_entries(ugeth
,
3285 &(ugeth
->p_init_enet_param_shadow
->
3286 txthread
[0]), numThreadsTxNumerical
,
3287 sizeof(struct ucc_geth_thread_tx_pram
),
3288 UCC_GETH_THREAD_TX_PRAM_ALIGNMENT
,
3289 ug_info
->riscTx
, 0)) != 0) {
3290 if (netif_msg_ifup(ugeth
))
3291 ugeth_err("%s: Can not fill p_init_enet_param_shadow.",
3293 ucc_geth_memclean(ugeth
);
3297 /* Load Rx bds with buffers */
3298 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3299 if ((ret_val
= rx_bd_buffer_set(ugeth
, (u8
) i
)) != 0) {
3300 if (netif_msg_ifup(ugeth
))
3301 ugeth_err("%s: Can not fill Rx bds with buffers.",
3303 ucc_geth_memclean(ugeth
);
3308 /* Allocate InitEnet command parameter structure */
3309 init_enet_pram_offset
= qe_muram_alloc(sizeof(struct ucc_geth_init_pram
), 4);
3310 if (IS_ERR_VALUE(init_enet_pram_offset
)) {
3311 if (netif_msg_ifup(ugeth
))
3313 ("%s: Can not allocate DPRAM memory for p_init_enet_pram.",
3315 ucc_geth_memclean(ugeth
);
3319 (struct ucc_geth_init_pram
*) qe_muram_addr(init_enet_pram_offset
);
3321 /* Copy shadow InitEnet command parameter structure into PRAM */
3322 p_init_enet_pram
->resinit1
= ugeth
->p_init_enet_param_shadow
->resinit1
;
3323 p_init_enet_pram
->resinit2
= ugeth
->p_init_enet_param_shadow
->resinit2
;
3324 p_init_enet_pram
->resinit3
= ugeth
->p_init_enet_param_shadow
->resinit3
;
3325 p_init_enet_pram
->resinit4
= ugeth
->p_init_enet_param_shadow
->resinit4
;
3326 out_be16(&p_init_enet_pram
->resinit5
,
3327 ugeth
->p_init_enet_param_shadow
->resinit5
);
3328 p_init_enet_pram
->largestexternallookupkeysize
=
3329 ugeth
->p_init_enet_param_shadow
->largestexternallookupkeysize
;
3330 out_be32(&p_init_enet_pram
->rgftgfrxglobal
,
3331 ugeth
->p_init_enet_param_shadow
->rgftgfrxglobal
);
3332 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_RX
; i
++)
3333 out_be32(&p_init_enet_pram
->rxthread
[i
],
3334 ugeth
->p_init_enet_param_shadow
->rxthread
[i
]);
3335 out_be32(&p_init_enet_pram
->txglobal
,
3336 ugeth
->p_init_enet_param_shadow
->txglobal
);
3337 for (i
= 0; i
< ENET_INIT_PARAM_MAX_ENTRIES_TX
; i
++)
3338 out_be32(&p_init_enet_pram
->txthread
[i
],
3339 ugeth
->p_init_enet_param_shadow
->txthread
[i
]);
3341 /* Issue QE command */
3343 ucc_fast_get_qe_cr_subblock(ugeth
->ug_info
->uf_info
.ucc_num
);
3344 qe_issue_cmd(command
, cecr_subblock
, QE_CR_PROTOCOL_ETHERNET
,
3345 init_enet_pram_offset
);
3347 /* Free InitEnet command parameter */
3348 qe_muram_free(init_enet_pram_offset
);
3353 /* returns a net_device_stats structure pointer */
3354 static struct net_device_stats
*ucc_geth_get_stats(struct net_device
*dev
)
3356 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3358 return &(ugeth
->stats
);
3361 /* ucc_geth_timeout gets called when a packet has not been
3362 * transmitted after a set amount of time.
3363 * For now, assume that clearing out all the structures, and
3364 * starting over will fix the problem. */
3365 static void ucc_geth_timeout(struct net_device
*dev
)
3367 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3369 ugeth_vdbg("%s: IN", __FUNCTION__
);
3371 ugeth
->stats
.tx_errors
++;
3373 ugeth_dump_regs(ugeth
);
3375 if (dev
->flags
& IFF_UP
) {
3376 ucc_geth_stop(ugeth
);
3377 ucc_geth_startup(ugeth
);
3380 netif_schedule(dev
);
3383 /* This is called by the kernel when a frame is ready for transmission. */
3384 /* It is pointed to by the dev->hard_start_xmit function pointer */
3385 static int ucc_geth_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
3387 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3388 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3389 struct ucc_fast_private
*uccf
;
3391 u8
*bd
; /* BD pointer */
3395 ugeth_vdbg("%s: IN", __FUNCTION__
);
3397 spin_lock_irq(&ugeth
->lock
);
3399 ugeth
->stats
.tx_bytes
+= skb
->len
;
3401 /* Start from the next BD that should be filled */
3402 bd
= ugeth
->txBd
[txQ
];
3403 bd_status
= in_be32((u32
*)bd
);
3404 /* Save the skb pointer so we can free it later */
3405 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_curtx
[txQ
]] = skb
;
3407 /* Update the current skb pointer (wrapping if this was the last) */
3408 ugeth
->skb_curtx
[txQ
] =
3409 (ugeth
->skb_curtx
[txQ
] +
3410 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3412 /* set up the buffer descriptor */
3413 out_be32(&((struct qe_bd
*)bd
)->buf
,
3414 dma_map_single(NULL
, skb
->data
, skb
->len
, DMA_TO_DEVICE
));
3416 /* printk(KERN_DEBUG"skb->data is 0x%x\n",skb->data); */
3418 bd_status
= (bd_status
& T_W
) | T_R
| T_I
| T_L
| skb
->len
;
3420 /* set bd status and length */
3421 out_be32((u32
*)bd
, bd_status
);
3423 dev
->trans_start
= jiffies
;
3425 /* Move to next BD in the ring */
3426 if (!(bd_status
& T_W
))
3427 bd
+= sizeof(struct qe_bd
);
3429 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3431 /* If the next BD still needs to be cleaned up, then the bds
3432 are full. We need to tell the kernel to stop sending us stuff. */
3433 if (bd
== ugeth
->confBd
[txQ
]) {
3434 if (!netif_queue_stopped(dev
))
3435 netif_stop_queue(dev
);
3438 ugeth
->txBd
[txQ
] = bd
;
3440 if (ugeth
->p_scheduler
) {
3441 ugeth
->cpucount
[txQ
]++;
3442 /* Indicate to QE that there are more Tx bds ready for
3444 /* This is done by writing a running counter of the bd
3445 count to the scheduler PRAM. */
3446 out_be16(ugeth
->p_cpucount
[txQ
], ugeth
->cpucount
[txQ
]);
3449 #ifdef CONFIG_UGETH_TX_ON_DEMAND
3451 out_be16(uccf
->p_utodr
, UCC_FAST_TOD
);
3453 spin_unlock_irq(&ugeth
->lock
);
3458 static int ucc_geth_rx(struct ucc_geth_private
*ugeth
, u8 rxQ
, int rx_work_limit
)
3460 struct sk_buff
*skb
;
3462 u16 length
, howmany
= 0;
3466 ugeth_vdbg("%s: IN", __FUNCTION__
);
3468 /* collect received buffers */
3469 bd
= ugeth
->rxBd
[rxQ
];
3471 bd_status
= in_be32((u32
*)bd
);
3473 /* while there are received buffers and BD is full (~R_E) */
3474 while (!((bd_status
& (R_E
)) || (--rx_work_limit
< 0))) {
3475 bdBuffer
= (u8
*) in_be32(&((struct qe_bd
*)bd
)->buf
);
3476 length
= (u16
) ((bd_status
& BD_LENGTH_MASK
) - 4);
3477 skb
= ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]];
3479 /* determine whether buffer is first, last, first and last
3480 (single buffer frame) or middle (not first and not last) */
3482 (!(bd_status
& (R_F
| R_L
))) ||
3483 (bd_status
& R_ERRORS_FATAL
)) {
3484 if (netif_msg_rx_err(ugeth
))
3485 ugeth_err("%s, %d: ERROR!!! skb - 0x%08x",
3486 __FUNCTION__
, __LINE__
, (u32
) skb
);
3488 dev_kfree_skb_any(skb
);
3490 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = NULL
;
3491 ugeth
->stats
.rx_dropped
++;
3493 ugeth
->stats
.rx_packets
++;
3496 /* Prep the skb for the packet */
3497 skb_put(skb
, length
);
3499 /* Tell the skb what kind of packet this is */
3500 skb
->protocol
= eth_type_trans(skb
, ugeth
->dev
);
3502 ugeth
->stats
.rx_bytes
+= length
;
3503 /* Send the packet up the stack */
3504 #ifdef CONFIG_UGETH_NAPI
3505 netif_receive_skb(skb
);
3508 #endif /* CONFIG_UGETH_NAPI */
3511 ugeth
->dev
->last_rx
= jiffies
;
3513 skb
= get_new_skb(ugeth
, bd
);
3515 if (netif_msg_rx_err(ugeth
))
3516 ugeth_warn("%s: No Rx Data Buffer", __FUNCTION__
);
3517 ugeth
->stats
.rx_dropped
++;
3521 ugeth
->rx_skbuff
[rxQ
][ugeth
->skb_currx
[rxQ
]] = skb
;
3523 /* update to point at the next skb */
3524 ugeth
->skb_currx
[rxQ
] =
3525 (ugeth
->skb_currx
[rxQ
] +
3526 1) & RX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenRx
[rxQ
]);
3528 if (bd_status
& R_W
)
3529 bd
= ugeth
->p_rx_bd_ring
[rxQ
];
3531 bd
+= sizeof(struct qe_bd
);
3533 bd_status
= in_be32((u32
*)bd
);
3536 ugeth
->rxBd
[rxQ
] = bd
;
3540 static int ucc_geth_tx(struct net_device
*dev
, u8 txQ
)
3542 /* Start from the next BD that should be filled */
3543 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3544 u8
*bd
; /* BD pointer */
3547 bd
= ugeth
->confBd
[txQ
];
3548 bd_status
= in_be32((u32
*)bd
);
3550 /* Normal processing. */
3551 while ((bd_status
& T_R
) == 0) {
3552 /* BD contains already transmitted buffer. */
3553 /* Handle the transmitted buffer and release */
3554 /* the BD to be used with the current frame */
3556 if ((bd
== ugeth
->txBd
[txQ
]) && (netif_queue_stopped(dev
) == 0))
3559 ugeth
->stats
.tx_packets
++;
3561 /* Free the sk buffer associated with this TxBD */
3562 dev_kfree_skb_irq(ugeth
->
3563 tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]]);
3564 ugeth
->tx_skbuff
[txQ
][ugeth
->skb_dirtytx
[txQ
]] = NULL
;
3565 ugeth
->skb_dirtytx
[txQ
] =
3566 (ugeth
->skb_dirtytx
[txQ
] +
3567 1) & TX_RING_MOD_MASK(ugeth
->ug_info
->bdRingLenTx
[txQ
]);
3569 /* We freed a buffer, so now we can restart transmission */
3570 if (netif_queue_stopped(dev
))
3571 netif_wake_queue(dev
);
3573 /* Advance the confirmation BD pointer */
3574 if (!(bd_status
& T_W
))
3575 bd
+= sizeof(struct qe_bd
);
3577 bd
= ugeth
->p_tx_bd_ring
[txQ
];
3578 bd_status
= in_be32((u32
*)bd
);
3580 ugeth
->confBd
[txQ
] = bd
;
3584 #ifdef CONFIG_UGETH_NAPI
3585 static int ucc_geth_poll(struct net_device
*dev
, int *budget
)
3587 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3588 struct ucc_geth_info
*ug_info
;
3589 struct ucc_fast_private
*uccf
;
3595 ug_info
= ugeth
->ug_info
;
3597 rx_work_limit
= *budget
;
3598 if (rx_work_limit
> dev
->quota
)
3599 rx_work_limit
= dev
->quota
;
3603 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3604 howmany
+= ucc_geth_rx(ugeth
, i
, rx_work_limit
);
3607 dev
->quota
-= howmany
;
3608 rx_work_limit
-= howmany
;
3611 if (rx_work_limit
> 0) {
3612 netif_rx_complete(dev
);
3614 uccm
= in_be32(uccf
->p_uccm
);
3615 uccm
|= UCCE_RX_EVENTS
;
3616 out_be32(uccf
->p_uccm
, uccm
);
3619 return (rx_work_limit
> 0) ? 0 : 1;
3621 #endif /* CONFIG_UGETH_NAPI */
3623 static irqreturn_t
ucc_geth_irq_handler(int irq
, void *info
)
3625 struct net_device
*dev
= (struct net_device
*)info
;
3626 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3627 struct ucc_fast_private
*uccf
;
3628 struct ucc_geth_info
*ug_info
;
3631 #ifndef CONFIG_UGETH_NAPI
3632 register u32 rx_mask
;
3634 register u32 tx_mask
;
3637 ugeth_vdbg("%s: IN", __FUNCTION__
);
3643 ug_info
= ugeth
->ug_info
;
3645 /* read and clear events */
3646 ucce
= (u32
) in_be32(uccf
->p_ucce
);
3647 uccm
= (u32
) in_be32(uccf
->p_uccm
);
3649 out_be32(uccf
->p_ucce
, ucce
);
3651 /* check for receive events that require processing */
3652 if (ucce
& UCCE_RX_EVENTS
) {
3653 #ifdef CONFIG_UGETH_NAPI
3654 if (netif_rx_schedule_prep(dev
)) {
3655 uccm
&= ~UCCE_RX_EVENTS
;
3656 out_be32(uccf
->p_uccm
, uccm
);
3657 __netif_rx_schedule(dev
);
3660 rx_mask
= UCCE_RXBF_SINGLE_MASK
;
3661 for (i
= 0; i
< ug_info
->numQueuesRx
; i
++) {
3663 ucc_geth_rx(ugeth
, i
, (int)ugeth
->ug_info
->bdRingLenRx
[i
]);
3667 #endif /* CONFIG_UGETH_NAPI */
3670 /* Tx event processing */
3671 if (ucce
& UCCE_TX_EVENTS
) {
3672 spin_lock(&ugeth
->lock
);
3673 tx_mask
= UCCE_TXBF_SINGLE_MASK
;
3674 for (i
= 0; i
< ug_info
->numQueuesTx
; i
++) {
3676 ucc_geth_tx(dev
, i
);
3680 spin_unlock(&ugeth
->lock
);
3683 /* Errors and other events */
3684 if (ucce
& UCCE_OTHER
) {
3685 if (ucce
& UCCE_BSY
) {
3686 ugeth
->stats
.rx_errors
++;
3688 if (ucce
& UCCE_TXE
) {
3689 ugeth
->stats
.tx_errors
++;
3696 /* Called when something needs to use the ethernet device */
3697 /* Returns 0 for success. */
3698 static int ucc_geth_open(struct net_device
*dev
)
3700 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3703 ugeth_vdbg("%s: IN", __FUNCTION__
);
3705 /* Test station address */
3706 if (dev
->dev_addr
[0] & ENET_GROUP_ADDR
) {
3707 if (netif_msg_ifup(ugeth
))
3708 ugeth_err("%s: Multicast address used for station address"
3709 " - is this what you wanted?", __FUNCTION__
);
3713 err
= ucc_struct_init(ugeth
);
3715 if (netif_msg_ifup(ugeth
))
3716 ugeth_err("%s: Cannot configure internal struct, aborting.", dev
->name
);
3720 err
= ucc_geth_startup(ugeth
);
3722 if (netif_msg_ifup(ugeth
))
3723 ugeth_err("%s: Cannot configure net device, aborting.",
3728 err
= adjust_enet_interface(ugeth
);
3730 if (netif_msg_ifup(ugeth
))
3731 ugeth_err("%s: Cannot configure net device, aborting.",
3736 /* Set MACSTNADDR1, MACSTNADDR2 */
3737 /* For more details see the hardware spec. */
3738 init_mac_station_addr_regs(dev
->dev_addr
[0],
3744 &ugeth
->ug_regs
->macstnaddr1
,
3745 &ugeth
->ug_regs
->macstnaddr2
);
3747 err
= init_phy(dev
);
3749 if (netif_msg_ifup(ugeth
))
3750 ugeth_err("%s: Cannot initialize PHY, aborting.", dev
->name
);
3754 phy_start(ugeth
->phydev
);
3757 request_irq(ugeth
->ug_info
->uf_info
.irq
, ucc_geth_irq_handler
, 0,
3760 if (netif_msg_ifup(ugeth
))
3761 ugeth_err("%s: Cannot get IRQ for net device, aborting.",
3763 ucc_geth_stop(ugeth
);
3767 err
= ugeth_enable(ugeth
, COMM_DIR_RX_AND_TX
);
3769 if (netif_msg_ifup(ugeth
))
3770 ugeth_err("%s: Cannot enable net device, aborting.", dev
->name
);
3771 ucc_geth_stop(ugeth
);
3775 netif_start_queue(dev
);
3780 /* Stops the kernel queue, and halts the controller */
3781 static int ucc_geth_close(struct net_device
*dev
)
3783 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
3785 ugeth_vdbg("%s: IN", __FUNCTION__
);
3787 ucc_geth_stop(ugeth
);
3789 phy_disconnect(ugeth
->phydev
);
3790 ugeth
->phydev
= NULL
;
3792 netif_stop_queue(dev
);
3797 static phy_interface_t
to_phy_interface(const char *phy_connection_type
)
3799 if (strcasecmp(phy_connection_type
, "mii") == 0)
3800 return PHY_INTERFACE_MODE_MII
;
3801 if (strcasecmp(phy_connection_type
, "gmii") == 0)
3802 return PHY_INTERFACE_MODE_GMII
;
3803 if (strcasecmp(phy_connection_type
, "tbi") == 0)
3804 return PHY_INTERFACE_MODE_TBI
;
3805 if (strcasecmp(phy_connection_type
, "rmii") == 0)
3806 return PHY_INTERFACE_MODE_RMII
;
3807 if (strcasecmp(phy_connection_type
, "rgmii") == 0)
3808 return PHY_INTERFACE_MODE_RGMII
;
3809 if (strcasecmp(phy_connection_type
, "rgmii-id") == 0)
3810 return PHY_INTERFACE_MODE_RGMII_ID
;
3811 if (strcasecmp(phy_connection_type
, "rtbi") == 0)
3812 return PHY_INTERFACE_MODE_RTBI
;
3814 return PHY_INTERFACE_MODE_MII
;
3817 static int ucc_geth_probe(struct of_device
* ofdev
, const struct of_device_id
*match
)
3819 struct device
*device
= &ofdev
->dev
;
3820 struct device_node
*np
= ofdev
->node
;
3821 struct device_node
*mdio
;
3822 struct net_device
*dev
= NULL
;
3823 struct ucc_geth_private
*ugeth
= NULL
;
3824 struct ucc_geth_info
*ug_info
;
3825 struct resource res
;
3826 struct device_node
*phy
;
3827 int err
, ucc_num
, max_speed
= 0;
3829 const unsigned int *prop
;
3830 const void *mac_addr
;
3831 phy_interface_t phy_interface
;
3832 static const int enet_to_speed
[] = {
3833 SPEED_10
, SPEED_10
, SPEED_10
,
3834 SPEED_100
, SPEED_100
, SPEED_100
,
3835 SPEED_1000
, SPEED_1000
, SPEED_1000
, SPEED_1000
,
3837 static const phy_interface_t enet_to_phy_interface
[] = {
3838 PHY_INTERFACE_MODE_MII
, PHY_INTERFACE_MODE_RMII
,
3839 PHY_INTERFACE_MODE_RGMII
, PHY_INTERFACE_MODE_MII
,
3840 PHY_INTERFACE_MODE_RMII
, PHY_INTERFACE_MODE_RGMII
,
3841 PHY_INTERFACE_MODE_GMII
, PHY_INTERFACE_MODE_RGMII
,
3842 PHY_INTERFACE_MODE_TBI
, PHY_INTERFACE_MODE_RTBI
,
3845 ugeth_vdbg("%s: IN", __FUNCTION__
);
3847 prop
= of_get_property(np
, "device-id", NULL
);
3848 ucc_num
= *prop
- 1;
3849 if ((ucc_num
< 0) || (ucc_num
> 7))
3852 ug_info
= &ugeth_info
[ucc_num
];
3853 if (ug_info
== NULL
) {
3854 if (netif_msg_probe(&debug
))
3855 ugeth_err("%s: [%d] Missing additional data!",
3856 __FUNCTION__
, ucc_num
);
3860 ug_info
->uf_info
.ucc_num
= ucc_num
;
3862 prop
= of_get_property(np
, "rx-clock", NULL
);
3863 ug_info
->uf_info
.rx_clock
= *prop
;
3864 prop
= of_get_property(np
, "tx-clock", NULL
);
3865 ug_info
->uf_info
.tx_clock
= *prop
;
3866 err
= of_address_to_resource(np
, 0, &res
);
3870 ug_info
->uf_info
.regs
= res
.start
;
3871 ug_info
->uf_info
.irq
= irq_of_parse_and_map(np
, 0);
3873 ph
= of_get_property(np
, "phy-handle", NULL
);
3874 phy
= of_find_node_by_phandle(*ph
);
3879 /* set the PHY address */
3880 prop
= of_get_property(phy
, "reg", NULL
);
3883 ug_info
->phy_address
= *prop
;
3885 /* get the phy interface type, or default to MII */
3886 prop
= of_get_property(np
, "phy-connection-type", NULL
);
3888 /* handle interface property present in old trees */
3889 prop
= of_get_property(phy
, "interface", NULL
);
3891 phy_interface
= enet_to_phy_interface
[*prop
];
3892 max_speed
= enet_to_speed
[*prop
];
3894 phy_interface
= PHY_INTERFACE_MODE_MII
;
3896 phy_interface
= to_phy_interface((const char *)prop
);
3899 /* get speed, or derive from PHY interface */
3901 switch (phy_interface
) {
3902 case PHY_INTERFACE_MODE_GMII
:
3903 case PHY_INTERFACE_MODE_RGMII
:
3904 case PHY_INTERFACE_MODE_RGMII_ID
:
3905 case PHY_INTERFACE_MODE_TBI
:
3906 case PHY_INTERFACE_MODE_RTBI
:
3907 max_speed
= SPEED_1000
;
3910 max_speed
= SPEED_100
;
3914 if (max_speed
== SPEED_1000
) {
3915 /* configure muram FIFOs for gigabit operation */
3916 ug_info
->uf_info
.urfs
= UCC_GETH_URFS_GIGA_INIT
;
3917 ug_info
->uf_info
.urfet
= UCC_GETH_URFET_GIGA_INIT
;
3918 ug_info
->uf_info
.urfset
= UCC_GETH_URFSET_GIGA_INIT
;
3919 ug_info
->uf_info
.utfs
= UCC_GETH_UTFS_GIGA_INIT
;
3920 ug_info
->uf_info
.utfet
= UCC_GETH_UTFET_GIGA_INIT
;
3921 ug_info
->uf_info
.utftt
= UCC_GETH_UTFTT_GIGA_INIT
;
3924 /* Set the bus id */
3925 mdio
= of_get_parent(phy
);
3930 err
= of_address_to_resource(mdio
, 0, &res
);
3936 ug_info
->mdio_bus
= res
.start
;
3938 if (netif_msg_probe(&debug
))
3939 printk(KERN_INFO
"ucc_geth: UCC%1d at 0x%8x (irq = %d) \n",
3940 ug_info
->uf_info
.ucc_num
+ 1, ug_info
->uf_info
.regs
,
3941 ug_info
->uf_info
.irq
);
3943 /* Create an ethernet device instance */
3944 dev
= alloc_etherdev(sizeof(*ugeth
));
3949 ugeth
= netdev_priv(dev
);
3950 spin_lock_init(&ugeth
->lock
);
3952 dev_set_drvdata(device
, dev
);
3954 /* Set the dev->base_addr to the gfar reg region */
3955 dev
->base_addr
= (unsigned long)(ug_info
->uf_info
.regs
);
3957 SET_MODULE_OWNER(dev
);
3958 SET_NETDEV_DEV(dev
, device
);
3960 /* Fill in the dev structure */
3961 uec_set_ethtool_ops(dev
);
3962 dev
->open
= ucc_geth_open
;
3963 dev
->hard_start_xmit
= ucc_geth_start_xmit
;
3964 dev
->tx_timeout
= ucc_geth_timeout
;
3965 dev
->watchdog_timeo
= TX_TIMEOUT
;
3966 #ifdef CONFIG_UGETH_NAPI
3967 dev
->poll
= ucc_geth_poll
;
3968 dev
->weight
= UCC_GETH_DEV_WEIGHT
;
3969 #endif /* CONFIG_UGETH_NAPI */
3970 dev
->stop
= ucc_geth_close
;
3971 dev
->get_stats
= ucc_geth_get_stats
;
3972 // dev->change_mtu = ucc_geth_change_mtu;
3974 dev
->set_multicast_list
= ucc_geth_set_multi
;
3976 ugeth
->msg_enable
= netif_msg_init(debug
.msg_enable
, UGETH_MSG_DEFAULT
);
3977 ugeth
->phy_interface
= phy_interface
;
3978 ugeth
->max_speed
= max_speed
;
3980 err
= register_netdev(dev
);
3982 if (netif_msg_probe(ugeth
))
3983 ugeth_err("%s: Cannot register net device, aborting.",
3989 mac_addr
= of_get_mac_address(np
);
3991 memcpy(dev
->dev_addr
, mac_addr
, 6);
3993 ugeth
->ug_info
= ug_info
;
3999 static int ucc_geth_remove(struct of_device
* ofdev
)
4001 struct device
*device
= &ofdev
->dev
;
4002 struct net_device
*dev
= dev_get_drvdata(device
);
4003 struct ucc_geth_private
*ugeth
= netdev_priv(dev
);
4005 dev_set_drvdata(device
, NULL
);
4006 ucc_geth_memclean(ugeth
);
4012 static struct of_device_id ucc_geth_match
[] = {
4015 .compatible
= "ucc_geth",
4020 MODULE_DEVICE_TABLE(of
, ucc_geth_match
);
4022 static struct of_platform_driver ucc_geth_driver
= {
4024 .match_table
= ucc_geth_match
,
4025 .probe
= ucc_geth_probe
,
4026 .remove
= ucc_geth_remove
,
4029 static int __init
ucc_geth_init(void)
4033 ret
= uec_mdio_init();
4038 if (netif_msg_drv(&debug
))
4039 printk(KERN_INFO
"ucc_geth: " DRV_DESC
"\n");
4040 for (i
= 0; i
< 8; i
++)
4041 memcpy(&(ugeth_info
[i
]), &ugeth_primary_info
,
4042 sizeof(ugeth_primary_info
));
4044 ret
= of_register_platform_driver(&ucc_geth_driver
);
4052 static void __exit
ucc_geth_exit(void)
4054 of_unregister_platform_driver(&ucc_geth_driver
);
4058 module_init(ucc_geth_init
);
4059 module_exit(ucc_geth_exit
);
4061 MODULE_AUTHOR("Freescale Semiconductor, Inc");
4062 MODULE_DESCRIPTION(DRV_DESC
);
4063 MODULE_VERSION(DRV_VERSION
);
4064 MODULE_LICENSE("GPL");