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x86/mce: Move MCACOD defines from mce-severity.c to <asm/mce.h>
[linux-2.6/btrfs-unstable.git] / drivers / ata / ata_piix.c
blob3c809bfbccf58a2af573be99719a4fda77bd3815
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independent device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independent timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
97
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
100
101 enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* constants for mapping table */
122 P0 = 0, /* port 0 */
123 P1 = 1, /* port 1 */
124 P2 = 2, /* port 2 */
125 P3 = 3, /* port 3 */
126 IDE = -1, /* IDE */
127 NA = -2, /* not available */
128 RV = -3, /* reserved */
129
130 PIIX_AHCI_DEVICE = 6,
131
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
134 };
135
136 enum piix_controller_ids {
137 /* controller IDs */
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
144 ich5_sata,
145 ich6_sata,
146 ich6m_sata,
147 ich8_sata,
148 ich8_2port_sata,
149 ich8m_apple_sata, /* locks up on second port enable */
150 tolapai_sata,
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
152 ich8_sata_snb,
153 };
154
155 struct piix_map_db {
156 const u32 mask;
157 const u16 port_enable;
158 const int map[][4];
159 };
160
161 struct piix_host_priv {
162 const int *map;
163 u32 saved_iocfg;
164 void __iomem *sidpr;
165 };
166
167 static int piix_init_one(struct pci_dev *pdev,
168 const struct pci_device_id *ent);
169 static void piix_remove_one(struct pci_dev *pdev);
170 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline);
171 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev);
172 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev);
173 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev);
174 static int ich_pata_cable_detect(struct ata_port *ap);
175 static u8 piix_vmw_bmdma_status(struct ata_port *ap);
176 static int piix_sidpr_scr_read(struct ata_link *link,
177 unsigned int reg, u32 *val);
178 static int piix_sidpr_scr_write(struct ata_link *link,
179 unsigned int reg, u32 val);
180 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
181 unsigned hints);
182 static bool piix_irq_check(struct ata_port *ap);
183 static int piix_port_start(struct ata_port *ap);
184 #ifdef CONFIG_PM
185 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
186 static int piix_pci_device_resume(struct pci_dev *pdev);
187 #endif
188
189 static unsigned int in_module_init = 1;
190
191 static const struct pci_device_id piix_pci_tbl[] = {
192 /* Intel PIIX3 for the 430HX etc */
193 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
194 /* VMware ICH4 */
195 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
196 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
197 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
198 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
199 /* Intel PIIX4 */
200 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
201 /* Intel PIIX4 */
202 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
203 /* Intel PIIX */
204 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
205 /* Intel ICH (i810, i815, i840) UDMA 66*/
206 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
207 /* Intel ICH0 : UDMA 33*/
208 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
209 /* Intel ICH2M */
210 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
211 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
212 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213 /* Intel ICH3M */
214 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
215 /* Intel ICH3 (E7500/1) UDMA 100 */
216 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
217 /* Intel ICH4-L */
218 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
219 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
220 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
221 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
222 /* Intel ICH5 */
223 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
224 /* C-ICH (i810E2) */
225 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
226 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
227 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
228 /* ICH6 (and 6) (i915) UDMA 100 */
229 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
230 /* ICH7/7-R (i945, i975) UDMA 100*/
231 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
232 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
233 /* ICH8 Mobile PATA Controller */
234 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
235
236 /* SATA ports */
237
238 /* 82801EB (ICH5) */
239 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
240 /* 82801EB (ICH5) */
241 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
242 /* 6300ESB (ICH5 variant with broken PCS present bits) */
243 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
244 /* 6300ESB pretending RAID */
245 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
246 /* 82801FB/FW (ICH6/ICH6W) */
247 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
248 /* 82801FR/FRW (ICH6R/ICH6RW) */
249 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
250 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
251 * Attach iff the controller is in IDE mode. */
252 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
253 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
254 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
255 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
256 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
257 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
258 /* Enterprise Southbridge 2 (631xESB/632xESB) */
259 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
260 /* SATA Controller 1 IDE (ICH8) */
261 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
262 /* SATA Controller 2 IDE (ICH8) */
263 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
264 /* Mobile SATA Controller IDE (ICH8M), Apple */
265 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
266 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
267 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
268 /* Mobile SATA Controller IDE (ICH8M) */
269 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
270 /* SATA Controller IDE (ICH9) */
271 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (ICH9) */
273 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (ICH9) */
275 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (ICH9M) */
277 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
278 /* SATA Controller IDE (ICH9M) */
279 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (ICH9M) */
281 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
282 /* SATA Controller IDE (Tolapai) */
283 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
284 /* SATA Controller IDE (ICH10) */
285 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
286 /* SATA Controller IDE (ICH10) */
287 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (ICH10) */
289 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
290 /* SATA Controller IDE (ICH10) */
291 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
292 /* SATA Controller IDE (PCH) */
293 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
294 /* SATA Controller IDE (PCH) */
295 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
296 /* SATA Controller IDE (PCH) */
297 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
298 /* SATA Controller IDE (PCH) */
299 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
300 /* SATA Controller IDE (PCH) */
301 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
302 /* SATA Controller IDE (PCH) */
303 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
304 /* SATA Controller IDE (CPT) */
305 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
306 /* SATA Controller IDE (CPT) */
307 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
308 /* SATA Controller IDE (CPT) */
309 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
310 /* SATA Controller IDE (CPT) */
311 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
312 /* SATA Controller IDE (PBG) */
313 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
314 /* SATA Controller IDE (PBG) */
315 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
316 /* SATA Controller IDE (Panther Point) */
317 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
318 /* SATA Controller IDE (Panther Point) */
319 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
320 /* SATA Controller IDE (Panther Point) */
321 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
322 /* SATA Controller IDE (Panther Point) */
323 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
324 /* SATA Controller IDE (Lynx Point) */
325 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
326 /* SATA Controller IDE (Lynx Point) */
327 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
328 /* SATA Controller IDE (Lynx Point) */
329 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
330 /* SATA Controller IDE (Lynx Point) */
331 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
332 /* SATA Controller IDE (DH89xxCC) */
333 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
334 { } /* terminate list */
335 };
336
337 static struct pci_driver piix_pci_driver = {
338 .name = DRV_NAME,
339 .id_table = piix_pci_tbl,
340 .probe = piix_init_one,
341 .remove = piix_remove_one,
342 #ifdef CONFIG_PM
343 .suspend = piix_pci_device_suspend,
344 .resume = piix_pci_device_resume,
345 #endif
346 };
347
348 static struct scsi_host_template piix_sht = {
349 ATA_BMDMA_SHT(DRV_NAME),
350 };
351
352 static struct ata_port_operations piix_sata_ops = {
353 .inherits = &ata_bmdma32_port_ops,
354 .sff_irq_check = piix_irq_check,
355 .port_start = piix_port_start,
356 };
357
358 static struct ata_port_operations piix_pata_ops = {
359 .inherits = &piix_sata_ops,
360 .cable_detect = ata_cable_40wire,
361 .set_piomode = piix_set_piomode,
362 .set_dmamode = piix_set_dmamode,
363 .prereset = piix_pata_prereset,
364 };
365
366 static struct ata_port_operations piix_vmw_ops = {
367 .inherits = &piix_pata_ops,
368 .bmdma_status = piix_vmw_bmdma_status,
369 };
370
371 static struct ata_port_operations ich_pata_ops = {
372 .inherits = &piix_pata_ops,
373 .cable_detect = ich_pata_cable_detect,
374 .set_dmamode = ich_set_dmamode,
375 };
376
377 static struct device_attribute *piix_sidpr_shost_attrs[] = {
378 &dev_attr_link_power_management_policy,
379 NULL
380 };
381
382 static struct scsi_host_template piix_sidpr_sht = {
383 ATA_BMDMA_SHT(DRV_NAME),
384 .shost_attrs = piix_sidpr_shost_attrs,
385 };
386
387 static struct ata_port_operations piix_sidpr_sata_ops = {
388 .inherits = &piix_sata_ops,
389 .hardreset = sata_std_hardreset,
390 .scr_read = piix_sidpr_scr_read,
391 .scr_write = piix_sidpr_scr_write,
392 .set_lpm = piix_sidpr_set_lpm,
393 };
394
395 static const struct piix_map_db ich5_map_db = {
396 .mask = 0x7,
397 .port_enable = 0x3,
398 .map = {
399 /* PM PS SM SS MAP */
400 { P0, NA, P1, NA }, /* 000b */
401 { P1, NA, P0, NA }, /* 001b */
402 { RV, RV, RV, RV },
403 { RV, RV, RV, RV },
404 { P0, P1, IDE, IDE }, /* 100b */
405 { P1, P0, IDE, IDE }, /* 101b */
406 { IDE, IDE, P0, P1 }, /* 110b */
407 { IDE, IDE, P1, P0 }, /* 111b */
408 },
409 };
410
411 static const struct piix_map_db ich6_map_db = {
412 .mask = 0x3,
413 .port_enable = 0xf,
414 .map = {
415 /* PM PS SM SS MAP */
416 { P0, P2, P1, P3 }, /* 00b */
417 { IDE, IDE, P1, P3 }, /* 01b */
418 { P0, P2, IDE, IDE }, /* 10b */
419 { RV, RV, RV, RV },
420 },
421 };
422
423 static const struct piix_map_db ich6m_map_db = {
424 .mask = 0x3,
425 .port_enable = 0x5,
426
427 /* Map 01b isn't specified in the doc but some notebooks use
428 * it anyway. MAP 01b have been spotted on both ICH6M and
429 * ICH7M.
430 */
431 .map = {
432 /* PM PS SM SS MAP */
433 { P0, P2, NA, NA }, /* 00b */
434 { IDE, IDE, P1, P3 }, /* 01b */
435 { P0, P2, IDE, IDE }, /* 10b */
436 { RV, RV, RV, RV },
437 },
438 };
439
440 static const struct piix_map_db ich8_map_db = {
441 .mask = 0x3,
442 .port_enable = 0xf,
443 .map = {
444 /* PM PS SM SS MAP */
445 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
446 { RV, RV, RV, RV },
447 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
448 { RV, RV, RV, RV },
449 },
450 };
451
452 static const struct piix_map_db ich8_2port_map_db = {
453 .mask = 0x3,
454 .port_enable = 0x3,
455 .map = {
456 /* PM PS SM SS MAP */
457 { P0, NA, P1, NA }, /* 00b */
458 { RV, RV, RV, RV }, /* 01b */
459 { RV, RV, RV, RV }, /* 10b */
460 { RV, RV, RV, RV },
461 },
462 };
463
464 static const struct piix_map_db ich8m_apple_map_db = {
465 .mask = 0x3,
466 .port_enable = 0x1,
467 .map = {
468 /* PM PS SM SS MAP */
469 { P0, NA, NA, NA }, /* 00b */
470 { RV, RV, RV, RV },
471 { P0, P2, IDE, IDE }, /* 10b */
472 { RV, RV, RV, RV },
473 },
474 };
475
476 static const struct piix_map_db tolapai_map_db = {
477 .mask = 0x3,
478 .port_enable = 0x3,
479 .map = {
480 /* PM PS SM SS MAP */
481 { P0, NA, P1, NA }, /* 00b */
482 { RV, RV, RV, RV }, /* 01b */
483 { RV, RV, RV, RV }, /* 10b */
484 { RV, RV, RV, RV },
485 },
486 };
487
488 static const struct piix_map_db *piix_map_db_table[] = {
489 [ich5_sata] = &ich5_map_db,
490 [ich6_sata] = &ich6_map_db,
491 [ich6m_sata] = &ich6m_map_db,
492 [ich8_sata] = &ich8_map_db,
493 [ich8_2port_sata] = &ich8_2port_map_db,
494 [ich8m_apple_sata] = &ich8m_apple_map_db,
495 [tolapai_sata] = &tolapai_map_db,
496 [ich8_sata_snb] = &ich8_map_db,
497 };
498
499 static struct ata_port_info piix_port_info[] = {
500 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
501 {
502 .flags = PIIX_PATA_FLAGS,
503 .pio_mask = ATA_PIO4,
504 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
505 .port_ops = &piix_pata_ops,
506 },
507
508 [piix_pata_33] = /* PIIX4 at 33MHz */
509 {
510 .flags = PIIX_PATA_FLAGS,
511 .pio_mask = ATA_PIO4,
512 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
513 .udma_mask = ATA_UDMA2,
514 .port_ops = &piix_pata_ops,
515 },
516
517 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
518 {
519 .flags = PIIX_PATA_FLAGS,
520 .pio_mask = ATA_PIO4,
521 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
522 .udma_mask = ATA_UDMA2,
523 .port_ops = &ich_pata_ops,
524 },
525
526 [ich_pata_66] = /* ICH controllers up to 66MHz */
527 {
528 .flags = PIIX_PATA_FLAGS,
529 .pio_mask = ATA_PIO4,
530 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
531 .udma_mask = ATA_UDMA4,
532 .port_ops = &ich_pata_ops,
533 },
534
535 [ich_pata_100] =
536 {
537 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
538 .pio_mask = ATA_PIO4,
539 .mwdma_mask = ATA_MWDMA12_ONLY,
540 .udma_mask = ATA_UDMA5,
541 .port_ops = &ich_pata_ops,
542 },
543
544 [ich_pata_100_nomwdma1] =
545 {
546 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
547 .pio_mask = ATA_PIO4,
548 .mwdma_mask = ATA_MWDMA2_ONLY,
549 .udma_mask = ATA_UDMA5,
550 .port_ops = &ich_pata_ops,
551 },
552
553 [ich5_sata] =
554 {
555 .flags = PIIX_SATA_FLAGS,
556 .pio_mask = ATA_PIO4,
557 .mwdma_mask = ATA_MWDMA2,
558 .udma_mask = ATA_UDMA6,
559 .port_ops = &piix_sata_ops,
560 },
561
562 [ich6_sata] =
563 {
564 .flags = PIIX_SATA_FLAGS,
565 .pio_mask = ATA_PIO4,
566 .mwdma_mask = ATA_MWDMA2,
567 .udma_mask = ATA_UDMA6,
568 .port_ops = &piix_sata_ops,
569 },
570
571 [ich6m_sata] =
572 {
573 .flags = PIIX_SATA_FLAGS,
574 .pio_mask = ATA_PIO4,
575 .mwdma_mask = ATA_MWDMA2,
576 .udma_mask = ATA_UDMA6,
577 .port_ops = &piix_sata_ops,
578 },
579
580 [ich8_sata] =
581 {
582 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
583 .pio_mask = ATA_PIO4,
584 .mwdma_mask = ATA_MWDMA2,
585 .udma_mask = ATA_UDMA6,
586 .port_ops = &piix_sata_ops,
587 },
588
589 [ich8_2port_sata] =
590 {
591 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
592 .pio_mask = ATA_PIO4,
593 .mwdma_mask = ATA_MWDMA2,
594 .udma_mask = ATA_UDMA6,
595 .port_ops = &piix_sata_ops,
596 },
597
598 [tolapai_sata] =
599 {
600 .flags = PIIX_SATA_FLAGS,
601 .pio_mask = ATA_PIO4,
602 .mwdma_mask = ATA_MWDMA2,
603 .udma_mask = ATA_UDMA6,
604 .port_ops = &piix_sata_ops,
605 },
606
607 [ich8m_apple_sata] =
608 {
609 .flags = PIIX_SATA_FLAGS,
610 .pio_mask = ATA_PIO4,
611 .mwdma_mask = ATA_MWDMA2,
612 .udma_mask = ATA_UDMA6,
613 .port_ops = &piix_sata_ops,
614 },
615
616 [piix_pata_vmw] =
617 {
618 .flags = PIIX_PATA_FLAGS,
619 .pio_mask = ATA_PIO4,
620 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
621 .udma_mask = ATA_UDMA2,
622 .port_ops = &piix_vmw_ops,
623 },
624
625 /*
626 * some Sandybridge chipsets have broken 32 mode up to now,
627 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
628 */
629 [ich8_sata_snb] =
630 {
631 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
632 .pio_mask = ATA_PIO4,
633 .mwdma_mask = ATA_MWDMA2,
634 .udma_mask = ATA_UDMA6,
635 .port_ops = &piix_sata_ops,
636 },
637
638 };
639
640 static struct pci_bits piix_enable_bits[] = {
641 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
642 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
643 };
644
645 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
646 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
647 MODULE_LICENSE("GPL");
648 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
649 MODULE_VERSION(DRV_VERSION);
650
651 struct ich_laptop {
652 u16 device;
653 u16 subvendor;
654 u16 subdevice;
655 };
656
657 /*
658 * List of laptops that use short cables rather than 80 wire
659 */
660
661 static const struct ich_laptop ich_laptop[] = {
662 /* devid, subvendor, subdev */
663 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
664 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
665 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
666 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
667 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
668 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
669 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
670 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
671 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
672 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
673 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
674 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
675 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
676 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
677 /* end marker */
678 { 0, }
679 };
680
681 static int piix_port_start(struct ata_port *ap)
682 {
683 if (!(ap->flags & PIIX_FLAG_PIO16))
684 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
685
686 return ata_bmdma_port_start(ap);
687 }
688
689 /**
690 * ich_pata_cable_detect - Probe host controller cable detect info
691 * @ap: Port for which cable detect info is desired
692 *
693 * Read 80c cable indicator from ATA PCI device's PCI config
694 * register. This register is normally set by firmware (BIOS).
695 *
696 * LOCKING:
697 * None (inherited from caller).
698 */
699
700 static int ich_pata_cable_detect(struct ata_port *ap)
701 {
702 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
703 struct piix_host_priv *hpriv = ap->host->private_data;
704 const struct ich_laptop *lap = &ich_laptop[0];
705 u8 mask;
706
707 /* Check for specials - Acer Aspire 5602WLMi */
708 while (lap->device) {
709 if (lap->device == pdev->device &&
710 lap->subvendor == pdev->subsystem_vendor &&
711 lap->subdevice == pdev->subsystem_device)
712 return ATA_CBL_PATA40_SHORT;
713
714 lap++;
715 }
716
717 /* check BIOS cable detect results */
718 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
719 if ((hpriv->saved_iocfg & mask) == 0)
720 return ATA_CBL_PATA40;
721 return ATA_CBL_PATA80;
722 }
723
724 /**
725 * piix_pata_prereset - prereset for PATA host controller
726 * @link: Target link
727 * @deadline: deadline jiffies for the operation
728 *
729 * LOCKING:
730 * None (inherited from caller).
731 */
732 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
733 {
734 struct ata_port *ap = link->ap;
735 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
736
737 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
738 return -ENOENT;
739 return ata_sff_prereset(link, deadline);
740 }
741
742 static DEFINE_SPINLOCK(piix_lock);
743
744 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
745 u8 pio)
746 {
747 struct pci_dev *dev = to_pci_dev(ap->host->dev);
748 unsigned long flags;
749 unsigned int is_slave = (adev->devno != 0);
750 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
751 unsigned int slave_port = 0x44;
752 u16 master_data;
753 u8 slave_data;
754 u8 udma_enable;
755 int control = 0;
756
757 /*
758 * See Intel Document 298600-004 for the timing programing rules
759 * for ICH controllers.
760 */
761
762 static const /* ISP RTC */
763 u8 timings[][2] = { { 0, 0 },
764 { 0, 0 },
765 { 1, 0 },
766 { 2, 1 },
767 { 2, 3 }, };
768
769 if (pio >= 2)
770 control |= 1; /* TIME1 enable */
771 if (ata_pio_need_iordy(adev))
772 control |= 2; /* IE enable */
773 /* Intel specifies that the PPE functionality is for disk only */
774 if (adev->class == ATA_DEV_ATA)
775 control |= 4; /* PPE enable */
776 /*
777 * If the drive MWDMA is faster than it can do PIO then
778 * we must force PIO into PIO0
779 */
780 if (adev->pio_mode < XFER_PIO_0 + pio)
781 /* Enable DMA timing only */
782 control |= 8; /* PIO cycles in PIO0 */
783
784 spin_lock_irqsave(&piix_lock, flags);
785
786 /* PIO configuration clears DTE unconditionally. It will be
787 * programmed in set_dmamode which is guaranteed to be called
788 * after set_piomode if any DMA mode is available.
789 */
790 pci_read_config_word(dev, master_port, &master_data);
791 if (is_slave) {
792 /* clear TIME1|IE1|PPE1|DTE1 */
793 master_data &= 0xff0f;
794 /* enable PPE1, IE1 and TIME1 as needed */
795 master_data |= (control << 4);
796 pci_read_config_byte(dev, slave_port, &slave_data);
797 slave_data &= (ap->port_no ? 0x0f : 0xf0);
798 /* Load the timing nibble for this slave */
799 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
800 << (ap->port_no ? 4 : 0);
801 } else {
802 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
803 master_data &= 0xccf0;
804 /* Enable PPE, IE and TIME as appropriate */
805 master_data |= control;
806 /* load ISP and RCT */
807 master_data |=
808 (timings[pio][0] << 12) |
809 (timings[pio][1] << 8);
810 }
811
812 /* Enable SITRE (separate slave timing register) */
813 master_data |= 0x4000;
814 pci_write_config_word(dev, master_port, master_data);
815 if (is_slave)
816 pci_write_config_byte(dev, slave_port, slave_data);
817
818 /* Ensure the UDMA bit is off - it will be turned back on if
819 UDMA is selected */
820
821 if (ap->udma_mask) {
822 pci_read_config_byte(dev, 0x48, &udma_enable);
823 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
824 pci_write_config_byte(dev, 0x48, udma_enable);
825 }
826
827 spin_unlock_irqrestore(&piix_lock, flags);
828 }
829
830 /**
831 * piix_set_piomode - Initialize host controller PATA PIO timings
832 * @ap: Port whose timings we are configuring
833 * @adev: Drive in question
834 *
835 * Set PIO mode for device, in host controller PCI config space.
836 *
837 * LOCKING:
838 * None (inherited from caller).
839 */
840
841 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
842 {
843 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
844 }
845
846 /**
847 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
848 * @ap: Port whose timings we are configuring
849 * @adev: Drive in question
850 * @isich: set if the chip is an ICH device
851 *
852 * Set UDMA mode for device, in host controller PCI config space.
853 *
854 * LOCKING:
855 * None (inherited from caller).
856 */
857
858 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
859 {
860 struct pci_dev *dev = to_pci_dev(ap->host->dev);
861 unsigned long flags;
862 u8 speed = adev->dma_mode;
863 int devid = adev->devno + 2 * ap->port_no;
864 u8 udma_enable = 0;
865
866 if (speed >= XFER_UDMA_0) {
867 unsigned int udma = speed - XFER_UDMA_0;
868 u16 udma_timing;
869 u16 ideconf;
870 int u_clock, u_speed;
871
872 spin_lock_irqsave(&piix_lock, flags);
873
874 pci_read_config_byte(dev, 0x48, &udma_enable);
875
876 /*
877 * UDMA is handled by a combination of clock switching and
878 * selection of dividers
879 *
880 * Handy rule: Odd modes are UDMATIMx 01, even are 02
881 * except UDMA0 which is 00
882 */
883 u_speed = min(2 - (udma & 1), udma);
884 if (udma == 5)
885 u_clock = 0x1000; /* 100Mhz */
886 else if (udma > 2)
887 u_clock = 1; /* 66Mhz */
888 else
889 u_clock = 0; /* 33Mhz */
890
891 udma_enable |= (1 << devid);
892
893 /* Load the CT/RP selection */
894 pci_read_config_word(dev, 0x4A, &udma_timing);
895 udma_timing &= ~(3 << (4 * devid));
896 udma_timing |= u_speed << (4 * devid);
897 pci_write_config_word(dev, 0x4A, udma_timing);
898
899 if (isich) {
900 /* Select a 33/66/100Mhz clock */
901 pci_read_config_word(dev, 0x54, &ideconf);
902 ideconf &= ~(0x1001 << devid);
903 ideconf |= u_clock << devid;
904 /* For ICH or later we should set bit 10 for better
905 performance (WR_PingPong_En) */
906 pci_write_config_word(dev, 0x54, ideconf);
907 }
908
909 pci_write_config_byte(dev, 0x48, udma_enable);
910
911 spin_unlock_irqrestore(&piix_lock, flags);
912 } else {
913 /* MWDMA is driven by the PIO timings. */
914 unsigned int mwdma = speed - XFER_MW_DMA_0;
915 const unsigned int needed_pio[3] = {
916 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
917 };
918 int pio = needed_pio[mwdma] - XFER_PIO_0;
919
920 /* XFER_PIO_0 is never used currently */
921 piix_set_timings(ap, adev, pio);
922 }
923 }
924
925 /**
926 * piix_set_dmamode - Initialize host controller PATA DMA timings
927 * @ap: Port whose timings we are configuring
928 * @adev: um
929 *
930 * Set MW/UDMA mode for device, in host controller PCI config space.
931 *
932 * LOCKING:
933 * None (inherited from caller).
934 */
935
936 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
937 {
938 do_pata_set_dmamode(ap, adev, 0);
939 }
940
941 /**
942 * ich_set_dmamode - Initialize host controller PATA DMA timings
943 * @ap: Port whose timings we are configuring
944 * @adev: um
945 *
946 * Set MW/UDMA mode for device, in host controller PCI config space.
947 *
948 * LOCKING:
949 * None (inherited from caller).
950 */
951
952 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
953 {
954 do_pata_set_dmamode(ap, adev, 1);
955 }
956
957 /*
958 * Serial ATA Index/Data Pair Superset Registers access
959 *
960 * Beginning from ICH8, there's a sane way to access SCRs using index
961 * and data register pair located at BAR5 which means that we have
962 * separate SCRs for master and slave. This is handled using libata
963 * slave_link facility.
964 */
965 static const int piix_sidx_map[] = {
966 [SCR_STATUS] = 0,
967 [SCR_ERROR] = 2,
968 [SCR_CONTROL] = 1,
969 };
970
971 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
972 {
973 struct ata_port *ap = link->ap;
974 struct piix_host_priv *hpriv = ap->host->private_data;
975
976 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
977 hpriv->sidpr + PIIX_SIDPR_IDX);
978 }
979
980 static int piix_sidpr_scr_read(struct ata_link *link,
981 unsigned int reg, u32 *val)
982 {
983 struct piix_host_priv *hpriv = link->ap->host->private_data;
984
985 if (reg >= ARRAY_SIZE(piix_sidx_map))
986 return -EINVAL;
987
988 piix_sidpr_sel(link, reg);
989 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
990 return 0;
991 }
992
993 static int piix_sidpr_scr_write(struct ata_link *link,
994 unsigned int reg, u32 val)
995 {
996 struct piix_host_priv *hpriv = link->ap->host->private_data;
997
998 if (reg >= ARRAY_SIZE(piix_sidx_map))
999 return -EINVAL;
1000
1001 piix_sidpr_sel(link, reg);
1002 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
1003 return 0;
1004 }
1005
1006 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
1007 unsigned hints)
1008 {
1009 return sata_link_scr_lpm(link, policy, false);
1010 }
1011
1012 static bool piix_irq_check(struct ata_port *ap)
1013 {
1014 if (unlikely(!ap->ioaddr.bmdma_addr))
1015 return false;
1016
1017 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
1018 }
1019
1020 #ifdef CONFIG_PM
1021 static int piix_broken_suspend(void)
1022 {
1023 static const struct dmi_system_id sysids[] = {
1024 {
1025 .ident = "TECRA M3",
1026 .matches = {
1027 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1028 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
1029 },
1030 },
1031 {
1032 .ident = "TECRA M3",
1033 .matches = {
1034 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1035 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
1036 },
1037 },
1038 {
1039 .ident = "TECRA M4",
1040 .matches = {
1041 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1042 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
1043 },
1044 },
1045 {
1046 .ident = "TECRA M4",
1047 .matches = {
1048 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1049 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
1050 },
1051 },
1052 {
1053 .ident = "TECRA M5",
1054 .matches = {
1055 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1056 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
1057 },
1058 },
1059 {
1060 .ident = "TECRA M6",
1061 .matches = {
1062 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1063 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
1064 },
1065 },
1066 {
1067 .ident = "TECRA M7",
1068 .matches = {
1069 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1070 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
1071 },
1072 },
1073 {
1074 .ident = "TECRA A8",
1075 .matches = {
1076 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1077 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
1078 },
1079 },
1080 {
1081 .ident = "Satellite R20",
1082 .matches = {
1083 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1084 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
1085 },
1086 },
1087 {
1088 .ident = "Satellite R25",
1089 .matches = {
1090 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1091 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
1092 },
1093 },
1094 {
1095 .ident = "Satellite U200",
1096 .matches = {
1097 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1098 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
1099 },
1100 },
1101 {
1102 .ident = "Satellite U200",
1103 .matches = {
1104 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1105 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
1106 },
1107 },
1108 {
1109 .ident = "Satellite Pro U200",
1110 .matches = {
1111 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1112 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
1113 },
1114 },
1115 {
1116 .ident = "Satellite U205",
1117 .matches = {
1118 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1119 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
1120 },
1121 },
1122 {
1123 .ident = "SATELLITE U205",
1124 .matches = {
1125 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1126 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
1127 },
1128 },
1129 {
1130 .ident = "Satellite Pro A120",
1131 .matches = {
1132 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1133 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
1134 },
1135 },
1136 {
1137 .ident = "Portege M500",
1138 .matches = {
1139 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
1140 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
1141 },
1142 },
1143 {
1144 .ident = "VGN-BX297XP",
1145 .matches = {
1146 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
1147 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
1148 },
1149 },
1150
1151 { } /* terminate list */
1152 };
1153 static const char *oemstrs[] = {
1154 "Tecra M3,",
1155 };
1156 int i;
1157
1158 if (dmi_check_system(sysids))
1159 return 1;
1160
1161 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
1162 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
1163 return 1;
1164
1165 /* TECRA M4 sometimes forgets its identify and reports bogus
1166 * DMI information. As the bogus information is a bit
1167 * generic, match as many entries as possible. This manual
1168 * matching is necessary because dmi_system_id.matches is
1169 * limited to four entries.
1170 */
1171 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
1172 dmi_match(DMI_PRODUCT_NAME, "000000") &&
1173 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
1174 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
1175 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
1176 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
1177 dmi_match(DMI_BOARD_VERSION, "Version A0"))
1178 return 1;
1179
1180 return 0;
1181 }
1182
1183 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
1184 {
1185 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1186 unsigned long flags;
1187 int rc = 0;
1188
1189 rc = ata_host_suspend(host, mesg);
1190 if (rc)
1191 return rc;
1192
1193 /* Some braindamaged ACPI suspend implementations expect the
1194 * controller to be awake on entry; otherwise, it burns cpu
1195 * cycles and power trying to do something to the sleeping
1196 * beauty.
1197 */
1198 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
1199 pci_save_state(pdev);
1200
1201 /* mark its power state as "unknown", since we don't
1202 * know if e.g. the BIOS will change its device state
1203 * when we suspend.
1204 */
1205 if (pdev->current_state == PCI_D0)
1206 pdev->current_state = PCI_UNKNOWN;
1207
1208 /* tell resume that it's waking up from broken suspend */
1209 spin_lock_irqsave(&host->lock, flags);
1210 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
1211 spin_unlock_irqrestore(&host->lock, flags);
1212 } else
1213 ata_pci_device_do_suspend(pdev, mesg);
1214
1215 return 0;
1216 }
1217
1218 static int piix_pci_device_resume(struct pci_dev *pdev)
1219 {
1220 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1221 unsigned long flags;
1222 int rc;
1223
1224 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1225 spin_lock_irqsave(&host->lock, flags);
1226 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1227 spin_unlock_irqrestore(&host->lock, flags);
1228
1229 pci_set_power_state(pdev, PCI_D0);
1230 pci_restore_state(pdev);
1231
1232 /* PCI device wasn't disabled during suspend. Use
1233 * pci_reenable_device() to avoid affecting the enable
1234 * count.
1235 */
1236 rc = pci_reenable_device(pdev);
1237 if (rc)
1238 dev_err(&pdev->dev,
1239 "failed to enable device after resume (%d)\n",
1240 rc);
1241 } else
1242 rc = ata_pci_device_do_resume(pdev);
1243
1244 if (rc == 0)
1245 ata_host_resume(host);
1246
1247 return rc;
1248 }
1249 #endif
1250
1251 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1252 {
1253 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1254 }
1255
1256 #define AHCI_PCI_BAR 5
1257 #define AHCI_GLOBAL_CTL 0x04
1258 #define AHCI_ENABLE (1 << 31)
1259 static int piix_disable_ahci(struct pci_dev *pdev)
1260 {
1261 void __iomem *mmio;
1262 u32 tmp;
1263 int rc = 0;
1264
1265 /* BUG: pci_enable_device has not yet been called. This
1266 * works because this device is usually set up by BIOS.
1267 */
1268
1269 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1270 !pci_resource_len(pdev, AHCI_PCI_BAR))
1271 return 0;
1272
1273 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1274 if (!mmio)
1275 return -ENOMEM;
1276
1277 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1278 if (tmp & AHCI_ENABLE) {
1279 tmp &= ~AHCI_ENABLE;
1280 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1281
1282 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1283 if (tmp & AHCI_ENABLE)
1284 rc = -EIO;
1285 }
1286
1287 pci_iounmap(pdev, mmio);
1288 return rc;
1289 }
1290
1291 /**
1292 * piix_check_450nx_errata - Check for problem 450NX setup
1293 * @ata_dev: the PCI device to check
1294 *
1295 * Check for the present of 450NX errata #19 and errata #25. If
1296 * they are found return an error code so we can turn off DMA
1297 */
1298
1299 static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
1300 {
1301 struct pci_dev *pdev = NULL;
1302 u16 cfg;
1303 int no_piix_dma = 0;
1304
1305 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1306 /* Look for 450NX PXB. Check for problem configurations
1307 A PCI quirk checks bit 6 already */
1308 pci_read_config_word(pdev, 0x41, &cfg);
1309 /* Only on the original revision: IDE DMA can hang */
1310 if (pdev->revision == 0x00)
1311 no_piix_dma = 1;
1312 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1313 else if (cfg & (1<<14) && pdev->revision < 5)
1314 no_piix_dma = 2;
1315 }
1316 if (no_piix_dma)
1317 dev_warn(&ata_dev->dev,
1318 "450NX errata present, disabling IDE DMA%s\n",
1319 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1320 : "");
1321
1322 return no_piix_dma;
1323 }
1324
1325 static void __devinit piix_init_pcs(struct ata_host *host,
1326 const struct piix_map_db *map_db)
1327 {
1328 struct pci_dev *pdev = to_pci_dev(host->dev);
1329 u16 pcs, new_pcs;
1330
1331 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1332
1333 new_pcs = pcs | map_db->port_enable;
1334
1335 if (new_pcs != pcs) {
1336 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1337 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1338 msleep(150);
1339 }
1340 }
1341
1342 static const int *__devinit piix_init_sata_map(struct pci_dev *pdev,
1343 struct ata_port_info *pinfo,
1344 const struct piix_map_db *map_db)
1345 {
1346 const int *map;
1347 int i, invalid_map = 0;
1348 u8 map_value;
1349
1350 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1351
1352 map = map_db->map[map_value & map_db->mask];
1353
1354 dev_info(&pdev->dev, "MAP [");
1355 for (i = 0; i < 4; i++) {
1356 switch (map[i]) {
1357 case RV:
1358 invalid_map = 1;
1359 pr_cont(" XX");
1360 break;
1361
1362 case NA:
1363 pr_cont(" --");
1364 break;
1365
1366 case IDE:
1367 WARN_ON((i & 1) || map[i + 1] != IDE);
1368 pinfo[i / 2] = piix_port_info[ich_pata_100];
1369 i++;
1370 pr_cont(" IDE IDE");
1371 break;
1372
1373 default:
1374 pr_cont(" P%d", map[i]);
1375 if (i & 1)
1376 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1377 break;
1378 }
1379 }
1380 pr_cont(" ]\n");
1381
1382 if (invalid_map)
1383 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1384
1385 return map;
1386 }
1387
1388 static bool piix_no_sidpr(struct ata_host *host)
1389 {
1390 struct pci_dev *pdev = to_pci_dev(host->dev);
1391
1392 /*
1393 * Samsung DB-P70 only has three ATA ports exposed and
1394 * curiously the unconnected first port reports link online
1395 * while not responding to SRST protocol causing excessive
1396 * detection delay.
1397 *
1398 * Unfortunately, the system doesn't carry enough DMI
1399 * information to identify the machine but does have subsystem
1400 * vendor and device set. As it's unclear whether the
1401 * subsystem vendor/device is used only for this specific
1402 * board, the port can't be disabled solely with the
1403 * information; however, turning off SIDPR access works around
1404 * the problem. Turn it off.
1405 *
1406 * This problem is reported in bnc#441240.
1407 *
1408 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1409 */
1410 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1411 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1412 pdev->subsystem_device == 0xb049) {
1413 dev_warn(host->dev,
1414 "Samsung DB-P70 detected, disabling SIDPR\n");
1415 return true;
1416 }
1417
1418 return false;
1419 }
1420
1421 static int __devinit piix_init_sidpr(struct ata_host *host)
1422 {
1423 struct pci_dev *pdev = to_pci_dev(host->dev);
1424 struct piix_host_priv *hpriv = host->private_data;
1425 struct ata_link *link0 = &host->ports[0]->link;
1426 u32 scontrol;
1427 int i, rc;
1428
1429 /* check for availability */
1430 for (i = 0; i < 4; i++)
1431 if (hpriv->map[i] == IDE)
1432 return 0;
1433
1434 /* is it blacklisted? */
1435 if (piix_no_sidpr(host))
1436 return 0;
1437
1438 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1439 return 0;
1440
1441 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1442 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1443 return 0;
1444
1445 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1446 return 0;
1447
1448 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1449
1450 /* SCR access via SIDPR doesn't work on some configurations.
1451 * Give it a test drive by inhibiting power save modes which
1452 * we'll do anyway.
1453 */
1454 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1455
1456 /* if IPM is already 3, SCR access is probably working. Don't
1457 * un-inhibit power save modes as BIOS might have inhibited
1458 * them for a reason.
1459 */
1460 if ((scontrol & 0xf00) != 0x300) {
1461 scontrol |= 0x300;
1462 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1463 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1464
1465 if ((scontrol & 0xf00) != 0x300) {
1466 dev_info(host->dev,
1467 "SCR access via SIDPR is available but doesn't work\n");
1468 return 0;
1469 }
1470 }
1471
1472 /* okay, SCRs available, set ops and ask libata for slave_link */
1473 for (i = 0; i < 2; i++) {
1474 struct ata_port *ap = host->ports[i];
1475
1476 ap->ops = &piix_sidpr_sata_ops;
1477
1478 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1479 rc = ata_slave_link_init(ap);
1480 if (rc)
1481 return rc;
1482 }
1483 }
1484
1485 return 0;
1486 }
1487
1488 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1489 {
1490 static const struct dmi_system_id sysids[] = {
1491 {
1492 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1493 * isn't used to boot the system which
1494 * disables the channel.
1495 */
1496 .ident = "M570U",
1497 .matches = {
1498 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1499 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1500 },
1501 },
1502
1503 { } /* terminate list */
1504 };
1505 struct pci_dev *pdev = to_pci_dev(host->dev);
1506 struct piix_host_priv *hpriv = host->private_data;
1507
1508 if (!dmi_check_system(sysids))
1509 return;
1510
1511 /* The datasheet says that bit 18 is NOOP but certain systems
1512 * seem to use it to disable a channel. Clear the bit on the
1513 * affected systems.
1514 */
1515 if (hpriv->saved_iocfg & (1 << 18)) {
1516 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1517 pci_write_config_dword(pdev, PIIX_IOCFG,
1518 hpriv->saved_iocfg & ~(1 << 18));
1519 }
1520 }
1521
1522 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1523 {
1524 static const struct dmi_system_id broken_systems[] = {
1525 {
1526 .ident = "HP Compaq 2510p",
1527 .matches = {
1528 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1529 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1530 },
1531 /* PCI slot number of the controller */
1532 .driver_data = (void *)0x1FUL,
1533 },
1534 {
1535 .ident = "HP Compaq nc6000",
1536 .matches = {
1537 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1538 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1539 },
1540 /* PCI slot number of the controller */
1541 .driver_data = (void *)0x1FUL,
1542 },
1543
1544 { } /* terminate list */
1545 };
1546 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1547
1548 if (dmi) {
1549 unsigned long slot = (unsigned long)dmi->driver_data;
1550 /* apply the quirk only to on-board controllers */
1551 return slot == PCI_SLOT(pdev->devfn);
1552 }
1553
1554 return false;
1555 }
1556
1557 static int prefer_ms_hyperv = 1;
1558 module_param(prefer_ms_hyperv, int, 0);
1559
1560 static void piix_ignore_devices_quirk(struct ata_host *host)
1561 {
1562 #if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1563 static const struct dmi_system_id ignore_hyperv[] = {
1564 {
1565 /* On Hyper-V hypervisors the disks are exposed on
1566 * both the emulated SATA controller and on the
1567 * paravirtualised drivers. The CD/DVD devices
1568 * are only exposed on the emulated controller.
1569 * Request we ignore ATA devices on this host.
1570 */
1571 .ident = "Hyper-V Virtual Machine",
1572 .matches = {
1573 DMI_MATCH(DMI_SYS_VENDOR,
1574 "Microsoft Corporation"),
1575 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1576 },
1577 },
1578 { } /* terminate list */
1579 };
1580 const struct dmi_system_id *dmi = dmi_first_match(ignore_hyperv);
1581
1582 if (dmi && prefer_ms_hyperv) {
1583 host->flags |= ATA_HOST_IGNORE_ATA;
1584 dev_info(host->dev, "%s detected, ATA device ignore set\n",
1585 dmi->ident);
1586 }
1587 #endif
1588 }
1589
1590 /**
1591 * piix_init_one - Register PIIX ATA PCI device with kernel services
1592 * @pdev: PCI device to register
1593 * @ent: Entry in piix_pci_tbl matching with @pdev
1594 *
1595 * Called from kernel PCI layer. We probe for combined mode (sigh),
1596 * and then hand over control to libata, for it to do the rest.
1597 *
1598 * LOCKING:
1599 * Inherited from PCI layer (may sleep).
1600 *
1601 * RETURNS:
1602 * Zero on success, or -ERRNO value.
1603 */
1604
1605 static int __devinit piix_init_one(struct pci_dev *pdev,
1606 const struct pci_device_id *ent)
1607 {
1608 struct device *dev = &pdev->dev;
1609 struct ata_port_info port_info[2];
1610 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1611 struct scsi_host_template *sht = &piix_sht;
1612 unsigned long port_flags;
1613 struct ata_host *host;
1614 struct piix_host_priv *hpriv;
1615 int rc;
1616
1617 ata_print_version_once(&pdev->dev, DRV_VERSION);
1618
1619 /* no hotplugging support for later devices (FIXME) */
1620 if (!in_module_init && ent->driver_data >= ich5_sata)
1621 return -ENODEV;
1622
1623 if (piix_broken_system_poweroff(pdev)) {
1624 piix_port_info[ent->driver_data].flags |=
1625 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1626 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1627 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1628 "on poweroff and hibernation\n");
1629 }
1630
1631 port_info[0] = piix_port_info[ent->driver_data];
1632 port_info[1] = piix_port_info[ent->driver_data];
1633
1634 port_flags = port_info[0].flags;
1635
1636 /* enable device and prepare host */
1637 rc = pcim_enable_device(pdev);
1638 if (rc)
1639 return rc;
1640
1641 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1642 if (!hpriv)
1643 return -ENOMEM;
1644
1645 /* Save IOCFG, this will be used for cable detection, quirk
1646 * detection and restoration on detach. This is necessary
1647 * because some ACPI implementations mess up cable related
1648 * bits on _STM. Reported on kernel bz#11879.
1649 */
1650 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1651
1652 /* ICH6R may be driven by either ata_piix or ahci driver
1653 * regardless of BIOS configuration. Make sure AHCI mode is
1654 * off.
1655 */
1656 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1657 rc = piix_disable_ahci(pdev);
1658 if (rc)
1659 return rc;
1660 }
1661
1662 /* SATA map init can change port_info, do it before prepping host */
1663 if (port_flags & ATA_FLAG_SATA)
1664 hpriv->map = piix_init_sata_map(pdev, port_info,
1665 piix_map_db_table[ent->driver_data]);
1666
1667 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1668 if (rc)
1669 return rc;
1670 host->private_data = hpriv;
1671
1672 /* initialize controller */
1673 if (port_flags & ATA_FLAG_SATA) {
1674 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1675 rc = piix_init_sidpr(host);
1676 if (rc)
1677 return rc;
1678 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1679 sht = &piix_sidpr_sht;
1680 }
1681
1682 /* apply IOCFG bit18 quirk */
1683 piix_iocfg_bit18_quirk(host);
1684
1685 /* On ICH5, some BIOSen disable the interrupt using the
1686 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1687 * On ICH6, this bit has the same effect, but only when
1688 * MSI is disabled (and it is disabled, as we don't use
1689 * message-signalled interrupts currently).
1690 */
1691 if (port_flags & PIIX_FLAG_CHECKINTR)
1692 pci_intx(pdev, 1);
1693
1694 if (piix_check_450nx_errata(pdev)) {
1695 /* This writes into the master table but it does not
1696 really matter for this errata as we will apply it to
1697 all the PIIX devices on the board */
1698 host->ports[0]->mwdma_mask = 0;
1699 host->ports[0]->udma_mask = 0;
1700 host->ports[1]->mwdma_mask = 0;
1701 host->ports[1]->udma_mask = 0;
1702 }
1703 host->flags |= ATA_HOST_PARALLEL_SCAN;
1704
1705 /* Allow hosts to specify device types to ignore when scanning. */
1706 piix_ignore_devices_quirk(host);
1707
1708 pci_set_master(pdev);
1709 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1710 }
1711
1712 static void piix_remove_one(struct pci_dev *pdev)
1713 {
1714 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1715 struct piix_host_priv *hpriv = host->private_data;
1716
1717 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1718
1719 ata_pci_remove_one(pdev);
1720 }
1721
1722 static int __init piix_init(void)
1723 {
1724 int rc;
1725
1726 DPRINTK("pci_register_driver\n");
1727 rc = pci_register_driver(&piix_pci_driver);
1728 if (rc)
1729 return rc;
1730
1731 in_module_init = 0;
1732
1733 DPRINTK("done\n");
1734 return 0;
1735 }
1736
1737 static void __exit piix_exit(void)
1738 {
1739 pci_unregister_driver(&piix_pci_driver);
1740 }
1741
1742 module_init(piix_init);
1743 module_exit(piix_exit);
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