2 * Copyright (C) 2005 - 2015 Emulex
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
10 * Contact Information:
11 * linux-drivers@emulex.com
15 * Costa Mesa, CA 92626
18 #include <linux/module.h>
22 static char *be_port_misconfig_evt_desc
[] = {
23 "A valid SFP module detected",
24 "Optics faulted/ incorrectly installed/ not installed.",
25 "Optics of two types installed.",
26 "Incompatible optics.",
27 "Unknown port SFP status"
30 static char *be_port_misconfig_remedy_desc
[] = {
32 "Reseat optics. If issue not resolved, replace",
33 "Remove one optic or install matching pair of optics",
34 "Replace with compatible optics for card to function",
38 static struct be_cmd_priv_map cmd_priv_map
[] = {
40 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
42 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
43 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
46 OPCODE_COMMON_GET_FLOW_CONTROL
,
48 BE_PRIV_LNKQUERY
| BE_PRIV_VHADM
|
49 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
52 OPCODE_COMMON_SET_FLOW_CONTROL
,
54 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
55 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
58 OPCODE_ETH_GET_PPORT_STATS
,
60 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
61 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
64 OPCODE_COMMON_GET_PHY_DETAILS
,
66 BE_PRIV_LNKMGMT
| BE_PRIV_VHADM
|
67 BE_PRIV_DEVCFG
| BE_PRIV_DEVSEC
71 static bool be_cmd_allowed(struct be_adapter
*adapter
, u8 opcode
, u8 subsystem
)
74 int num_entries
= sizeof(cmd_priv_map
)/sizeof(struct be_cmd_priv_map
);
75 u32 cmd_privileges
= adapter
->cmd_privileges
;
77 for (i
= 0; i
< num_entries
; i
++)
78 if (opcode
== cmd_priv_map
[i
].opcode
&&
79 subsystem
== cmd_priv_map
[i
].subsystem
)
80 if (!(cmd_privileges
& cmd_priv_map
[i
].priv_mask
))
86 static inline void *embedded_payload(struct be_mcc_wrb
*wrb
)
88 return wrb
->payload
.embedded_payload
;
91 static int be_mcc_notify(struct be_adapter
*adapter
)
93 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
96 if (be_check_error(adapter
, BE_ERROR_ANY
))
99 val
|= mccq
->id
& DB_MCCQ_RING_ID_MASK
;
100 val
|= 1 << DB_MCCQ_NUM_POSTED_SHIFT
;
103 iowrite32(val
, adapter
->db
+ DB_MCCQ_OFFSET
);
108 /* To check if valid bit is set, check the entire word as we don't know
109 * the endianness of the data (old entry is host endian while a new entry is
111 static inline bool be_mcc_compl_is_new(struct be_mcc_compl
*compl)
115 if (compl->flags
!= 0) {
116 flags
= le32_to_cpu(compl->flags
);
117 if (flags
& CQE_FLAGS_VALID_MASK
) {
118 compl->flags
= flags
;
125 /* Need to reset the entire word that houses the valid bit */
126 static inline void be_mcc_compl_use(struct be_mcc_compl
*compl)
131 static struct be_cmd_resp_hdr
*be_decode_resp_hdr(u32 tag0
, u32 tag1
)
136 addr
= ((addr
<< 16) << 16) | tag0
;
140 static bool be_skip_err_log(u8 opcode
, u16 base_status
, u16 addl_status
)
142 if (base_status
== MCC_STATUS_NOT_SUPPORTED
||
143 base_status
== MCC_STATUS_ILLEGAL_REQUEST
||
144 addl_status
== MCC_ADDL_STATUS_TOO_MANY_INTERFACES
||
145 addl_status
== MCC_ADDL_STATUS_INSUFFICIENT_VLANS
||
146 (opcode
== OPCODE_COMMON_WRITE_FLASHROM
&&
147 (base_status
== MCC_STATUS_ILLEGAL_FIELD
||
148 addl_status
== MCC_ADDL_STATUS_FLASH_IMAGE_CRC_MISMATCH
)))
154 /* Place holder for all the async MCC cmds wherein the caller is not in a busy
155 * loop (has not issued be_mcc_notify_wait())
157 static void be_async_cmd_process(struct be_adapter
*adapter
,
158 struct be_mcc_compl
*compl,
159 struct be_cmd_resp_hdr
*resp_hdr
)
161 enum mcc_base_status base_status
= base_status(compl->status
);
162 u8 opcode
= 0, subsystem
= 0;
165 opcode
= resp_hdr
->opcode
;
166 subsystem
= resp_hdr
->subsystem
;
169 if (opcode
== OPCODE_LOWLEVEL_LOOPBACK_TEST
&&
170 subsystem
== CMD_SUBSYSTEM_LOWLEVEL
) {
171 complete(&adapter
->et_cmd_compl
);
175 if (opcode
== OPCODE_LOWLEVEL_SET_LOOPBACK_MODE
&&
176 subsystem
== CMD_SUBSYSTEM_LOWLEVEL
) {
177 complete(&adapter
->et_cmd_compl
);
181 if ((opcode
== OPCODE_COMMON_WRITE_FLASHROM
||
182 opcode
== OPCODE_COMMON_WRITE_OBJECT
) &&
183 subsystem
== CMD_SUBSYSTEM_COMMON
) {
184 adapter
->flash_status
= compl->status
;
185 complete(&adapter
->et_cmd_compl
);
189 if ((opcode
== OPCODE_ETH_GET_STATISTICS
||
190 opcode
== OPCODE_ETH_GET_PPORT_STATS
) &&
191 subsystem
== CMD_SUBSYSTEM_ETH
&&
192 base_status
== MCC_STATUS_SUCCESS
) {
193 be_parse_stats(adapter
);
194 adapter
->stats_cmd_sent
= false;
198 if (opcode
== OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
&&
199 subsystem
== CMD_SUBSYSTEM_COMMON
) {
200 if (base_status
== MCC_STATUS_SUCCESS
) {
201 struct be_cmd_resp_get_cntl_addnl_attribs
*resp
=
203 adapter
->hwmon_info
.be_on_die_temp
=
204 resp
->on_die_temperature
;
206 adapter
->be_get_temp_freq
= 0;
207 adapter
->hwmon_info
.be_on_die_temp
=
214 static int be_mcc_compl_process(struct be_adapter
*adapter
,
215 struct be_mcc_compl
*compl)
217 enum mcc_base_status base_status
;
218 enum mcc_addl_status addl_status
;
219 struct be_cmd_resp_hdr
*resp_hdr
;
220 u8 opcode
= 0, subsystem
= 0;
222 /* Just swap the status to host endian; mcc tag is opaquely copied
224 be_dws_le_to_cpu(compl, 4);
226 base_status
= base_status(compl->status
);
227 addl_status
= addl_status(compl->status
);
229 resp_hdr
= be_decode_resp_hdr(compl->tag0
, compl->tag1
);
231 opcode
= resp_hdr
->opcode
;
232 subsystem
= resp_hdr
->subsystem
;
235 be_async_cmd_process(adapter
, compl, resp_hdr
);
237 if (base_status
!= MCC_STATUS_SUCCESS
&&
238 !be_skip_err_log(opcode
, base_status
, addl_status
)) {
239 if (base_status
== MCC_STATUS_UNAUTHORIZED_REQUEST
) {
240 dev_warn(&adapter
->pdev
->dev
,
241 "VF is not privileged to issue opcode %d-%d\n",
244 dev_err(&adapter
->pdev
->dev
,
245 "opcode %d-%d failed:status %d-%d\n",
246 opcode
, subsystem
, base_status
, addl_status
);
249 return compl->status
;
252 /* Link state evt is a string of bytes; no need for endian swapping */
253 static void be_async_link_state_process(struct be_adapter
*adapter
,
254 struct be_mcc_compl
*compl)
256 struct be_async_event_link_state
*evt
=
257 (struct be_async_event_link_state
*)compl;
259 /* When link status changes, link speed must be re-queried from FW */
260 adapter
->phy
.link_speed
= -1;
262 /* On BEx the FW does not send a separate link status
263 * notification for physical and logical link.
264 * On other chips just process the logical link
265 * status notification
267 if (!BEx_chip(adapter
) &&
268 !(evt
->port_link_status
& LOGICAL_LINK_STATUS_MASK
))
271 /* For the initial link status do not rely on the ASYNC event as
272 * it may not be received in some cases.
274 if (adapter
->flags
& BE_FLAGS_LINK_STATUS_INIT
)
275 be_link_status_update(adapter
,
276 evt
->port_link_status
& LINK_STATUS_MASK
);
279 static void be_async_port_misconfig_event_process(struct be_adapter
*adapter
,
280 struct be_mcc_compl
*compl)
282 struct be_async_event_misconfig_port
*evt
=
283 (struct be_async_event_misconfig_port
*)compl;
284 u32 sfp_mismatch_evt
= le32_to_cpu(evt
->event_data_word1
);
285 struct device
*dev
= &adapter
->pdev
->dev
;
286 u8 port_misconfig_evt
;
289 ((sfp_mismatch_evt
>> (adapter
->hba_port_num
* 8)) & 0xff);
291 /* Log an error message that would allow a user to determine
292 * whether the SFPs have an issue
294 dev_info(dev
, "Port %c: %s %s", adapter
->port_name
,
295 be_port_misconfig_evt_desc
[port_misconfig_evt
],
296 be_port_misconfig_remedy_desc
[port_misconfig_evt
]);
298 if (port_misconfig_evt
== INCOMPATIBLE_SFP
)
299 adapter
->flags
|= BE_FLAGS_EVT_INCOMPATIBLE_SFP
;
302 /* Grp5 CoS Priority evt */
303 static void be_async_grp5_cos_priority_process(struct be_adapter
*adapter
,
304 struct be_mcc_compl
*compl)
306 struct be_async_event_grp5_cos_priority
*evt
=
307 (struct be_async_event_grp5_cos_priority
*)compl;
310 adapter
->vlan_prio_bmap
= evt
->available_priority_bmap
;
311 adapter
->recommended_prio
&= ~VLAN_PRIO_MASK
;
312 adapter
->recommended_prio
=
313 evt
->reco_default_priority
<< VLAN_PRIO_SHIFT
;
317 /* Grp5 QOS Speed evt: qos_link_speed is in units of 10 Mbps */
318 static void be_async_grp5_qos_speed_process(struct be_adapter
*adapter
,
319 struct be_mcc_compl
*compl)
321 struct be_async_event_grp5_qos_link_speed
*evt
=
322 (struct be_async_event_grp5_qos_link_speed
*)compl;
324 if (adapter
->phy
.link_speed
>= 0 &&
325 evt
->physical_port
== adapter
->port_num
)
326 adapter
->phy
.link_speed
= le16_to_cpu(evt
->qos_link_speed
) * 10;
330 static void be_async_grp5_pvid_state_process(struct be_adapter
*adapter
,
331 struct be_mcc_compl
*compl)
333 struct be_async_event_grp5_pvid_state
*evt
=
334 (struct be_async_event_grp5_pvid_state
*)compl;
337 adapter
->pvid
= le16_to_cpu(evt
->tag
) & VLAN_VID_MASK
;
338 dev_info(&adapter
->pdev
->dev
, "LPVID: %d\n", adapter
->pvid
);
344 #define MGMT_ENABLE_MASK 0x4
345 static void be_async_grp5_fw_control_process(struct be_adapter
*adapter
,
346 struct be_mcc_compl
*compl)
348 struct be_async_fw_control
*evt
= (struct be_async_fw_control
*)compl;
349 u32 evt_dw1
= le32_to_cpu(evt
->event_data_word1
);
351 if (evt_dw1
& MGMT_ENABLE_MASK
) {
352 adapter
->flags
|= BE_FLAGS_OS2BMC
;
353 adapter
->bmc_filt_mask
= le32_to_cpu(evt
->event_data_word2
);
355 adapter
->flags
&= ~BE_FLAGS_OS2BMC
;
359 static void be_async_grp5_evt_process(struct be_adapter
*adapter
,
360 struct be_mcc_compl
*compl)
362 u8 event_type
= (compl->flags
>> ASYNC_EVENT_TYPE_SHIFT
) &
363 ASYNC_EVENT_TYPE_MASK
;
365 switch (event_type
) {
366 case ASYNC_EVENT_COS_PRIORITY
:
367 be_async_grp5_cos_priority_process(adapter
, compl);
369 case ASYNC_EVENT_QOS_SPEED
:
370 be_async_grp5_qos_speed_process(adapter
, compl);
372 case ASYNC_EVENT_PVID_STATE
:
373 be_async_grp5_pvid_state_process(adapter
, compl);
375 /* Async event to disable/enable os2bmc and/or mac-learning */
376 case ASYNC_EVENT_FW_CONTROL
:
377 be_async_grp5_fw_control_process(adapter
, compl);
384 static void be_async_dbg_evt_process(struct be_adapter
*adapter
,
385 struct be_mcc_compl
*cmp
)
388 struct be_async_event_qnq
*evt
= (struct be_async_event_qnq
*)cmp
;
390 event_type
= (cmp
->flags
>> ASYNC_EVENT_TYPE_SHIFT
) &
391 ASYNC_EVENT_TYPE_MASK
;
393 switch (event_type
) {
394 case ASYNC_DEBUG_EVENT_TYPE_QNQ
:
396 adapter
->qnq_vid
= le16_to_cpu(evt
->vlan_tag
);
397 adapter
->flags
|= BE_FLAGS_QNQ_ASYNC_EVT_RCVD
;
400 dev_warn(&adapter
->pdev
->dev
, "Unknown debug event 0x%x!\n",
406 static void be_async_sliport_evt_process(struct be_adapter
*adapter
,
407 struct be_mcc_compl
*cmp
)
409 u8 event_type
= (cmp
->flags
>> ASYNC_EVENT_TYPE_SHIFT
) &
410 ASYNC_EVENT_TYPE_MASK
;
412 if (event_type
== ASYNC_EVENT_PORT_MISCONFIG
)
413 be_async_port_misconfig_event_process(adapter
, cmp
);
416 static inline bool is_link_state_evt(u32 flags
)
418 return ((flags
>> ASYNC_EVENT_CODE_SHIFT
) & ASYNC_EVENT_CODE_MASK
) ==
419 ASYNC_EVENT_CODE_LINK_STATE
;
422 static inline bool is_grp5_evt(u32 flags
)
424 return ((flags
>> ASYNC_EVENT_CODE_SHIFT
) & ASYNC_EVENT_CODE_MASK
) ==
425 ASYNC_EVENT_CODE_GRP_5
;
428 static inline bool is_dbg_evt(u32 flags
)
430 return ((flags
>> ASYNC_EVENT_CODE_SHIFT
) & ASYNC_EVENT_CODE_MASK
) ==
431 ASYNC_EVENT_CODE_QNQ
;
434 static inline bool is_sliport_evt(u32 flags
)
436 return ((flags
>> ASYNC_EVENT_CODE_SHIFT
) & ASYNC_EVENT_CODE_MASK
) ==
437 ASYNC_EVENT_CODE_SLIPORT
;
440 static void be_mcc_event_process(struct be_adapter
*adapter
,
441 struct be_mcc_compl
*compl)
443 if (is_link_state_evt(compl->flags
))
444 be_async_link_state_process(adapter
, compl);
445 else if (is_grp5_evt(compl->flags
))
446 be_async_grp5_evt_process(adapter
, compl);
447 else if (is_dbg_evt(compl->flags
))
448 be_async_dbg_evt_process(adapter
, compl);
449 else if (is_sliport_evt(compl->flags
))
450 be_async_sliport_evt_process(adapter
, compl);
453 static struct be_mcc_compl
*be_mcc_compl_get(struct be_adapter
*adapter
)
455 struct be_queue_info
*mcc_cq
= &adapter
->mcc_obj
.cq
;
456 struct be_mcc_compl
*compl = queue_tail_node(mcc_cq
);
458 if (be_mcc_compl_is_new(compl)) {
459 queue_tail_inc(mcc_cq
);
465 void be_async_mcc_enable(struct be_adapter
*adapter
)
467 spin_lock_bh(&adapter
->mcc_cq_lock
);
469 be_cq_notify(adapter
, adapter
->mcc_obj
.cq
.id
, true, 0);
470 adapter
->mcc_obj
.rearm_cq
= true;
472 spin_unlock_bh(&adapter
->mcc_cq_lock
);
475 void be_async_mcc_disable(struct be_adapter
*adapter
)
477 spin_lock_bh(&adapter
->mcc_cq_lock
);
479 adapter
->mcc_obj
.rearm_cq
= false;
480 be_cq_notify(adapter
, adapter
->mcc_obj
.cq
.id
, false, 0);
482 spin_unlock_bh(&adapter
->mcc_cq_lock
);
485 int be_process_mcc(struct be_adapter
*adapter
)
487 struct be_mcc_compl
*compl;
488 int num
= 0, status
= 0;
489 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
491 spin_lock(&adapter
->mcc_cq_lock
);
493 while ((compl = be_mcc_compl_get(adapter
))) {
494 if (compl->flags
& CQE_FLAGS_ASYNC_MASK
) {
495 be_mcc_event_process(adapter
, compl);
496 } else if (compl->flags
& CQE_FLAGS_COMPLETED_MASK
) {
497 status
= be_mcc_compl_process(adapter
, compl);
498 atomic_dec(&mcc_obj
->q
.used
);
500 be_mcc_compl_use(compl);
505 be_cq_notify(adapter
, mcc_obj
->cq
.id
, mcc_obj
->rearm_cq
, num
);
507 spin_unlock(&adapter
->mcc_cq_lock
);
511 /* Wait till no more pending mcc requests are present */
512 static int be_mcc_wait_compl(struct be_adapter
*adapter
)
514 #define mcc_timeout 120000 /* 12s timeout */
516 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
518 for (i
= 0; i
< mcc_timeout
; i
++) {
519 if (be_check_error(adapter
, BE_ERROR_ANY
))
523 status
= be_process_mcc(adapter
);
526 if (atomic_read(&mcc_obj
->q
.used
) == 0)
530 if (i
== mcc_timeout
) {
531 dev_err(&adapter
->pdev
->dev
, "FW not responding\n");
532 be_set_error(adapter
, BE_ERROR_FW
);
538 /* Notify MCC requests and wait for completion */
539 static int be_mcc_notify_wait(struct be_adapter
*adapter
)
542 struct be_mcc_wrb
*wrb
;
543 struct be_mcc_obj
*mcc_obj
= &adapter
->mcc_obj
;
544 u16 index
= mcc_obj
->q
.head
;
545 struct be_cmd_resp_hdr
*resp
;
547 index_dec(&index
, mcc_obj
->q
.len
);
548 wrb
= queue_index_node(&mcc_obj
->q
, index
);
550 resp
= be_decode_resp_hdr(wrb
->tag0
, wrb
->tag1
);
552 status
= be_mcc_notify(adapter
);
556 status
= be_mcc_wait_compl(adapter
);
560 status
= (resp
->base_status
|
561 ((resp
->addl_status
& CQE_ADDL_STATUS_MASK
) <<
562 CQE_ADDL_STATUS_SHIFT
));
567 static int be_mbox_db_ready_wait(struct be_adapter
*adapter
, void __iomem
*db
)
573 if (be_check_error(adapter
, BE_ERROR_ANY
))
576 ready
= ioread32(db
);
577 if (ready
== 0xffffffff)
580 ready
&= MPU_MAILBOX_DB_RDY_MASK
;
585 dev_err(&adapter
->pdev
->dev
, "FW not responding\n");
586 be_set_error(adapter
, BE_ERROR_FW
);
587 be_detect_error(adapter
);
599 * Insert the mailbox address into the doorbell in two steps
600 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
602 static int be_mbox_notify_wait(struct be_adapter
*adapter
)
606 void __iomem
*db
= adapter
->db
+ MPU_MAILBOX_DB_OFFSET
;
607 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
608 struct be_mcc_mailbox
*mbox
= mbox_mem
->va
;
609 struct be_mcc_compl
*compl = &mbox
->compl;
611 /* wait for ready to be set */
612 status
= be_mbox_db_ready_wait(adapter
, db
);
616 val
|= MPU_MAILBOX_DB_HI_MASK
;
617 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
618 val
|= (upper_32_bits(mbox_mem
->dma
) >> 2) << 2;
621 /* wait for ready to be set */
622 status
= be_mbox_db_ready_wait(adapter
, db
);
627 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
628 val
|= (u32
)(mbox_mem
->dma
>> 4) << 2;
631 status
= be_mbox_db_ready_wait(adapter
, db
);
635 /* A cq entry has been made now */
636 if (be_mcc_compl_is_new(compl)) {
637 status
= be_mcc_compl_process(adapter
, &mbox
->compl);
638 be_mcc_compl_use(compl);
642 dev_err(&adapter
->pdev
->dev
, "invalid mailbox completion\n");
648 static u16
be_POST_stage_get(struct be_adapter
*adapter
)
652 if (BEx_chip(adapter
))
653 sem
= ioread32(adapter
->csr
+ SLIPORT_SEMAPHORE_OFFSET_BEx
);
655 pci_read_config_dword(adapter
->pdev
,
656 SLIPORT_SEMAPHORE_OFFSET_SH
, &sem
);
658 return sem
& POST_STAGE_MASK
;
661 static int lancer_wait_ready(struct be_adapter
*adapter
)
663 #define SLIPORT_READY_TIMEOUT 30
667 for (i
= 0; i
< SLIPORT_READY_TIMEOUT
; i
++) {
668 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
669 if (sliport_status
& SLIPORT_STATUS_RDY_MASK
)
672 if (sliport_status
& SLIPORT_STATUS_ERR_MASK
&&
673 !(sliport_status
& SLIPORT_STATUS_RN_MASK
))
679 return sliport_status
? : -1;
682 int be_fw_wait_ready(struct be_adapter
*adapter
)
685 int status
, timeout
= 0;
686 struct device
*dev
= &adapter
->pdev
->dev
;
688 if (lancer_chip(adapter
)) {
689 status
= lancer_wait_ready(adapter
);
698 /* There's no means to poll POST state on BE2/3 VFs */
699 if (BEx_chip(adapter
) && be_virtfn(adapter
))
702 stage
= be_POST_stage_get(adapter
);
703 if (stage
== POST_STAGE_ARMFW_RDY
)
706 dev_info(dev
, "Waiting for POST, %ds elapsed\n", timeout
);
707 if (msleep_interruptible(2000)) {
708 dev_err(dev
, "Waiting for POST aborted\n");
712 } while (timeout
< 60);
715 dev_err(dev
, "POST timeout; stage=%#x\n", stage
);
719 static inline struct be_sge
*nonembedded_sgl(struct be_mcc_wrb
*wrb
)
721 return &wrb
->payload
.sgl
[0];
724 static inline void fill_wrb_tags(struct be_mcc_wrb
*wrb
, unsigned long addr
)
726 wrb
->tag0
= addr
& 0xFFFFFFFF;
727 wrb
->tag1
= upper_32_bits(addr
);
730 /* Don't touch the hdr after it's prepared */
731 /* mem will be NULL for embedded commands */
732 static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr
*req_hdr
,
733 u8 subsystem
, u8 opcode
, int cmd_len
,
734 struct be_mcc_wrb
*wrb
,
735 struct be_dma_mem
*mem
)
739 req_hdr
->opcode
= opcode
;
740 req_hdr
->subsystem
= subsystem
;
741 req_hdr
->request_length
= cpu_to_le32(cmd_len
- sizeof(*req_hdr
));
742 req_hdr
->version
= 0;
743 fill_wrb_tags(wrb
, (ulong
) req_hdr
);
744 wrb
->payload_length
= cmd_len
;
746 wrb
->embedded
|= (1 & MCC_WRB_SGE_CNT_MASK
) <<
747 MCC_WRB_SGE_CNT_SHIFT
;
748 sge
= nonembedded_sgl(wrb
);
749 sge
->pa_hi
= cpu_to_le32(upper_32_bits(mem
->dma
));
750 sge
->pa_lo
= cpu_to_le32(mem
->dma
& 0xFFFFFFFF);
751 sge
->len
= cpu_to_le32(mem
->size
);
753 wrb
->embedded
|= MCC_WRB_EMBEDDED_MASK
;
754 be_dws_cpu_to_le(wrb
, 8);
757 static void be_cmd_page_addrs_prepare(struct phys_addr
*pages
, u32 max_pages
,
758 struct be_dma_mem
*mem
)
760 int i
, buf_pages
= min(PAGES_4K_SPANNED(mem
->va
, mem
->size
), max_pages
);
761 u64 dma
= (u64
)mem
->dma
;
763 for (i
= 0; i
< buf_pages
; i
++) {
764 pages
[i
].lo
= cpu_to_le32(dma
& 0xFFFFFFFF);
765 pages
[i
].hi
= cpu_to_le32(upper_32_bits(dma
));
770 static inline struct be_mcc_wrb
*wrb_from_mbox(struct be_adapter
*adapter
)
772 struct be_dma_mem
*mbox_mem
= &adapter
->mbox_mem
;
773 struct be_mcc_wrb
*wrb
774 = &((struct be_mcc_mailbox
*)(mbox_mem
->va
))->wrb
;
775 memset(wrb
, 0, sizeof(*wrb
));
779 static struct be_mcc_wrb
*wrb_from_mccq(struct be_adapter
*adapter
)
781 struct be_queue_info
*mccq
= &adapter
->mcc_obj
.q
;
782 struct be_mcc_wrb
*wrb
;
787 if (atomic_read(&mccq
->used
) >= mccq
->len
)
790 wrb
= queue_head_node(mccq
);
791 queue_head_inc(mccq
);
792 atomic_inc(&mccq
->used
);
793 memset(wrb
, 0, sizeof(*wrb
));
797 static bool use_mcc(struct be_adapter
*adapter
)
799 return adapter
->mcc_obj
.q
.created
;
802 /* Must be used only in process context */
803 static int be_cmd_lock(struct be_adapter
*adapter
)
805 if (use_mcc(adapter
)) {
806 spin_lock_bh(&adapter
->mcc_lock
);
809 return mutex_lock_interruptible(&adapter
->mbox_lock
);
813 /* Must be used only in process context */
814 static void be_cmd_unlock(struct be_adapter
*adapter
)
816 if (use_mcc(adapter
))
817 spin_unlock_bh(&adapter
->mcc_lock
);
819 return mutex_unlock(&adapter
->mbox_lock
);
822 static struct be_mcc_wrb
*be_cmd_copy(struct be_adapter
*adapter
,
823 struct be_mcc_wrb
*wrb
)
825 struct be_mcc_wrb
*dest_wrb
;
827 if (use_mcc(adapter
)) {
828 dest_wrb
= wrb_from_mccq(adapter
);
832 dest_wrb
= wrb_from_mbox(adapter
);
835 memcpy(dest_wrb
, wrb
, sizeof(*wrb
));
836 if (wrb
->embedded
& cpu_to_le32(MCC_WRB_EMBEDDED_MASK
))
837 fill_wrb_tags(dest_wrb
, (ulong
) embedded_payload(wrb
));
842 /* Must be used only in process context */
843 static int be_cmd_notify_wait(struct be_adapter
*adapter
,
844 struct be_mcc_wrb
*wrb
)
846 struct be_mcc_wrb
*dest_wrb
;
849 status
= be_cmd_lock(adapter
);
853 dest_wrb
= be_cmd_copy(adapter
, wrb
);
859 if (use_mcc(adapter
))
860 status
= be_mcc_notify_wait(adapter
);
862 status
= be_mbox_notify_wait(adapter
);
865 memcpy(wrb
, dest_wrb
, sizeof(*wrb
));
868 be_cmd_unlock(adapter
);
872 /* Tell fw we're about to start firing cmds by writing a
873 * special pattern across the wrb hdr; uses mbox
875 int be_cmd_fw_init(struct be_adapter
*adapter
)
880 if (lancer_chip(adapter
))
883 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
886 wrb
= (u8
*)wrb_from_mbox(adapter
);
896 status
= be_mbox_notify_wait(adapter
);
898 mutex_unlock(&adapter
->mbox_lock
);
902 /* Tell fw we're done with firing cmds by writing a
903 * special pattern across the wrb hdr; uses mbox
905 int be_cmd_fw_clean(struct be_adapter
*adapter
)
910 if (lancer_chip(adapter
))
913 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
916 wrb
= (u8
*)wrb_from_mbox(adapter
);
926 status
= be_mbox_notify_wait(adapter
);
928 mutex_unlock(&adapter
->mbox_lock
);
932 int be_cmd_eq_create(struct be_adapter
*adapter
, struct be_eq_obj
*eqo
)
934 struct be_mcc_wrb
*wrb
;
935 struct be_cmd_req_eq_create
*req
;
936 struct be_dma_mem
*q_mem
= &eqo
->q
.dma_mem
;
939 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
942 wrb
= wrb_from_mbox(adapter
);
943 req
= embedded_payload(wrb
);
945 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
946 OPCODE_COMMON_EQ_CREATE
, sizeof(*req
), wrb
,
949 /* Support for EQ_CREATEv2 available only SH-R onwards */
950 if (!(BEx_chip(adapter
) || lancer_chip(adapter
)))
953 req
->hdr
.version
= ver
;
954 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
956 AMAP_SET_BITS(struct amap_eq_context
, valid
, req
->context
, 1);
958 AMAP_SET_BITS(struct amap_eq_context
, size
, req
->context
, 0);
959 AMAP_SET_BITS(struct amap_eq_context
, count
, req
->context
,
960 __ilog2_u32(eqo
->q
.len
/ 256));
961 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
963 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
965 status
= be_mbox_notify_wait(adapter
);
967 struct be_cmd_resp_eq_create
*resp
= embedded_payload(wrb
);
969 eqo
->q
.id
= le16_to_cpu(resp
->eq_id
);
971 (ver
== 2) ? le16_to_cpu(resp
->msix_idx
) : eqo
->idx
;
972 eqo
->q
.created
= true;
975 mutex_unlock(&adapter
->mbox_lock
);
980 int be_cmd_mac_addr_query(struct be_adapter
*adapter
, u8
*mac_addr
,
981 bool permanent
, u32 if_handle
, u32 pmac_id
)
983 struct be_mcc_wrb
*wrb
;
984 struct be_cmd_req_mac_query
*req
;
987 spin_lock_bh(&adapter
->mcc_lock
);
989 wrb
= wrb_from_mccq(adapter
);
994 req
= embedded_payload(wrb
);
996 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
997 OPCODE_COMMON_NTWK_MAC_QUERY
, sizeof(*req
), wrb
,
999 req
->type
= MAC_ADDRESS_TYPE_NETWORK
;
1003 req
->if_id
= cpu_to_le16((u16
)if_handle
);
1004 req
->pmac_id
= cpu_to_le32(pmac_id
);
1008 status
= be_mcc_notify_wait(adapter
);
1010 struct be_cmd_resp_mac_query
*resp
= embedded_payload(wrb
);
1012 memcpy(mac_addr
, resp
->mac
.addr
, ETH_ALEN
);
1016 spin_unlock_bh(&adapter
->mcc_lock
);
1020 /* Uses synchronous MCCQ */
1021 int be_cmd_pmac_add(struct be_adapter
*adapter
, u8
*mac_addr
,
1022 u32 if_id
, u32
*pmac_id
, u32 domain
)
1024 struct be_mcc_wrb
*wrb
;
1025 struct be_cmd_req_pmac_add
*req
;
1028 spin_lock_bh(&adapter
->mcc_lock
);
1030 wrb
= wrb_from_mccq(adapter
);
1035 req
= embedded_payload(wrb
);
1037 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1038 OPCODE_COMMON_NTWK_PMAC_ADD
, sizeof(*req
), wrb
,
1041 req
->hdr
.domain
= domain
;
1042 req
->if_id
= cpu_to_le32(if_id
);
1043 memcpy(req
->mac_address
, mac_addr
, ETH_ALEN
);
1045 status
= be_mcc_notify_wait(adapter
);
1047 struct be_cmd_resp_pmac_add
*resp
= embedded_payload(wrb
);
1049 *pmac_id
= le32_to_cpu(resp
->pmac_id
);
1053 spin_unlock_bh(&adapter
->mcc_lock
);
1055 if (status
== MCC_STATUS_UNAUTHORIZED_REQUEST
)
1061 /* Uses synchronous MCCQ */
1062 int be_cmd_pmac_del(struct be_adapter
*adapter
, u32 if_id
, int pmac_id
, u32 dom
)
1064 struct be_mcc_wrb
*wrb
;
1065 struct be_cmd_req_pmac_del
*req
;
1071 spin_lock_bh(&adapter
->mcc_lock
);
1073 wrb
= wrb_from_mccq(adapter
);
1078 req
= embedded_payload(wrb
);
1080 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1081 OPCODE_COMMON_NTWK_PMAC_DEL
, sizeof(*req
),
1084 req
->hdr
.domain
= dom
;
1085 req
->if_id
= cpu_to_le32(if_id
);
1086 req
->pmac_id
= cpu_to_le32(pmac_id
);
1088 status
= be_mcc_notify_wait(adapter
);
1091 spin_unlock_bh(&adapter
->mcc_lock
);
1096 int be_cmd_cq_create(struct be_adapter
*adapter
, struct be_queue_info
*cq
,
1097 struct be_queue_info
*eq
, bool no_delay
, int coalesce_wm
)
1099 struct be_mcc_wrb
*wrb
;
1100 struct be_cmd_req_cq_create
*req
;
1101 struct be_dma_mem
*q_mem
= &cq
->dma_mem
;
1105 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1108 wrb
= wrb_from_mbox(adapter
);
1109 req
= embedded_payload(wrb
);
1110 ctxt
= &req
->context
;
1112 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1113 OPCODE_COMMON_CQ_CREATE
, sizeof(*req
), wrb
,
1116 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1118 if (BEx_chip(adapter
)) {
1119 AMAP_SET_BITS(struct amap_cq_context_be
, coalescwm
, ctxt
,
1121 AMAP_SET_BITS(struct amap_cq_context_be
, nodelay
,
1123 AMAP_SET_BITS(struct amap_cq_context_be
, count
, ctxt
,
1124 __ilog2_u32(cq
->len
/ 256));
1125 AMAP_SET_BITS(struct amap_cq_context_be
, valid
, ctxt
, 1);
1126 AMAP_SET_BITS(struct amap_cq_context_be
, eventable
, ctxt
, 1);
1127 AMAP_SET_BITS(struct amap_cq_context_be
, eqid
, ctxt
, eq
->id
);
1129 req
->hdr
.version
= 2;
1130 req
->page_size
= 1; /* 1 for 4K */
1132 /* coalesce-wm field in this cmd is not relevant to Lancer.
1133 * Lancer uses COMMON_MODIFY_CQ to set this field
1135 if (!lancer_chip(adapter
))
1136 AMAP_SET_BITS(struct amap_cq_context_v2
, coalescwm
,
1138 AMAP_SET_BITS(struct amap_cq_context_v2
, nodelay
, ctxt
,
1140 AMAP_SET_BITS(struct amap_cq_context_v2
, count
, ctxt
,
1141 __ilog2_u32(cq
->len
/ 256));
1142 AMAP_SET_BITS(struct amap_cq_context_v2
, valid
, ctxt
, 1);
1143 AMAP_SET_BITS(struct amap_cq_context_v2
, eventable
, ctxt
, 1);
1144 AMAP_SET_BITS(struct amap_cq_context_v2
, eqid
, ctxt
, eq
->id
);
1147 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1149 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1151 status
= be_mbox_notify_wait(adapter
);
1153 struct be_cmd_resp_cq_create
*resp
= embedded_payload(wrb
);
1155 cq
->id
= le16_to_cpu(resp
->cq_id
);
1159 mutex_unlock(&adapter
->mbox_lock
);
1164 static u32
be_encoded_q_len(int q_len
)
1166 u32 len_encoded
= fls(q_len
); /* log2(len) + 1 */
1168 if (len_encoded
== 16)
1173 static int be_cmd_mccq_ext_create(struct be_adapter
*adapter
,
1174 struct be_queue_info
*mccq
,
1175 struct be_queue_info
*cq
)
1177 struct be_mcc_wrb
*wrb
;
1178 struct be_cmd_req_mcc_ext_create
*req
;
1179 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
1183 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1186 wrb
= wrb_from_mbox(adapter
);
1187 req
= embedded_payload(wrb
);
1188 ctxt
= &req
->context
;
1190 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1191 OPCODE_COMMON_MCC_CREATE_EXT
, sizeof(*req
), wrb
,
1194 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1195 if (BEx_chip(adapter
)) {
1196 AMAP_SET_BITS(struct amap_mcc_context_be
, valid
, ctxt
, 1);
1197 AMAP_SET_BITS(struct amap_mcc_context_be
, ring_size
, ctxt
,
1198 be_encoded_q_len(mccq
->len
));
1199 AMAP_SET_BITS(struct amap_mcc_context_be
, cq_id
, ctxt
, cq
->id
);
1201 req
->hdr
.version
= 1;
1202 req
->cq_id
= cpu_to_le16(cq
->id
);
1204 AMAP_SET_BITS(struct amap_mcc_context_v1
, ring_size
, ctxt
,
1205 be_encoded_q_len(mccq
->len
));
1206 AMAP_SET_BITS(struct amap_mcc_context_v1
, valid
, ctxt
, 1);
1207 AMAP_SET_BITS(struct amap_mcc_context_v1
, async_cq_id
,
1209 AMAP_SET_BITS(struct amap_mcc_context_v1
, async_cq_valid
,
1213 /* Subscribe to Link State, Sliport Event and Group 5 Events
1214 * (bits 1, 5 and 17 set)
1216 req
->async_event_bitmap
[0] =
1217 cpu_to_le32(BIT(ASYNC_EVENT_CODE_LINK_STATE
) |
1218 BIT(ASYNC_EVENT_CODE_GRP_5
) |
1219 BIT(ASYNC_EVENT_CODE_QNQ
) |
1220 BIT(ASYNC_EVENT_CODE_SLIPORT
));
1222 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1224 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1226 status
= be_mbox_notify_wait(adapter
);
1228 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
1230 mccq
->id
= le16_to_cpu(resp
->id
);
1231 mccq
->created
= true;
1233 mutex_unlock(&adapter
->mbox_lock
);
1238 static int be_cmd_mccq_org_create(struct be_adapter
*adapter
,
1239 struct be_queue_info
*mccq
,
1240 struct be_queue_info
*cq
)
1242 struct be_mcc_wrb
*wrb
;
1243 struct be_cmd_req_mcc_create
*req
;
1244 struct be_dma_mem
*q_mem
= &mccq
->dma_mem
;
1248 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1251 wrb
= wrb_from_mbox(adapter
);
1252 req
= embedded_payload(wrb
);
1253 ctxt
= &req
->context
;
1255 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1256 OPCODE_COMMON_MCC_CREATE
, sizeof(*req
), wrb
,
1259 req
->num_pages
= cpu_to_le16(PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
));
1261 AMAP_SET_BITS(struct amap_mcc_context_be
, valid
, ctxt
, 1);
1262 AMAP_SET_BITS(struct amap_mcc_context_be
, ring_size
, ctxt
,
1263 be_encoded_q_len(mccq
->len
));
1264 AMAP_SET_BITS(struct amap_mcc_context_be
, cq_id
, ctxt
, cq
->id
);
1266 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
1268 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1270 status
= be_mbox_notify_wait(adapter
);
1272 struct be_cmd_resp_mcc_create
*resp
= embedded_payload(wrb
);
1274 mccq
->id
= le16_to_cpu(resp
->id
);
1275 mccq
->created
= true;
1278 mutex_unlock(&adapter
->mbox_lock
);
1282 int be_cmd_mccq_create(struct be_adapter
*adapter
,
1283 struct be_queue_info
*mccq
, struct be_queue_info
*cq
)
1287 status
= be_cmd_mccq_ext_create(adapter
, mccq
, cq
);
1288 if (status
&& BEx_chip(adapter
)) {
1289 dev_warn(&adapter
->pdev
->dev
, "Upgrade to F/W ver 2.102.235.0 "
1290 "or newer to avoid conflicting priorities between NIC "
1291 "and FCoE traffic");
1292 status
= be_cmd_mccq_org_create(adapter
, mccq
, cq
);
1297 int be_cmd_txq_create(struct be_adapter
*adapter
, struct be_tx_obj
*txo
)
1299 struct be_mcc_wrb wrb
= {0};
1300 struct be_cmd_req_eth_tx_create
*req
;
1301 struct be_queue_info
*txq
= &txo
->q
;
1302 struct be_queue_info
*cq
= &txo
->cq
;
1303 struct be_dma_mem
*q_mem
= &txq
->dma_mem
;
1304 int status
, ver
= 0;
1306 req
= embedded_payload(&wrb
);
1307 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1308 OPCODE_ETH_TX_CREATE
, sizeof(*req
), &wrb
, NULL
);
1310 if (lancer_chip(adapter
)) {
1311 req
->hdr
.version
= 1;
1312 } else if (BEx_chip(adapter
)) {
1313 if (adapter
->function_caps
& BE_FUNCTION_CAPS_SUPER_NIC
)
1314 req
->hdr
.version
= 2;
1315 } else { /* For SH */
1316 req
->hdr
.version
= 2;
1319 if (req
->hdr
.version
> 0)
1320 req
->if_id
= cpu_to_le16(adapter
->if_handle
);
1321 req
->num_pages
= PAGES_4K_SPANNED(q_mem
->va
, q_mem
->size
);
1322 req
->ulp_num
= BE_ULP1_NUM
;
1323 req
->type
= BE_ETH_TX_RING_TYPE_STANDARD
;
1324 req
->cq_id
= cpu_to_le16(cq
->id
);
1325 req
->queue_size
= be_encoded_q_len(txq
->len
);
1326 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1327 ver
= req
->hdr
.version
;
1329 status
= be_cmd_notify_wait(adapter
, &wrb
);
1331 struct be_cmd_resp_eth_tx_create
*resp
= embedded_payload(&wrb
);
1333 txq
->id
= le16_to_cpu(resp
->cid
);
1335 txo
->db_offset
= le32_to_cpu(resp
->db_offset
);
1337 txo
->db_offset
= DB_TXULP1_OFFSET
;
1338 txq
->created
= true;
1345 int be_cmd_rxq_create(struct be_adapter
*adapter
,
1346 struct be_queue_info
*rxq
, u16 cq_id
, u16 frag_size
,
1347 u32 if_id
, u32 rss
, u8
*rss_id
)
1349 struct be_mcc_wrb
*wrb
;
1350 struct be_cmd_req_eth_rx_create
*req
;
1351 struct be_dma_mem
*q_mem
= &rxq
->dma_mem
;
1354 spin_lock_bh(&adapter
->mcc_lock
);
1356 wrb
= wrb_from_mccq(adapter
);
1361 req
= embedded_payload(wrb
);
1363 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1364 OPCODE_ETH_RX_CREATE
, sizeof(*req
), wrb
, NULL
);
1366 req
->cq_id
= cpu_to_le16(cq_id
);
1367 req
->frag_size
= fls(frag_size
) - 1;
1369 be_cmd_page_addrs_prepare(req
->pages
, ARRAY_SIZE(req
->pages
), q_mem
);
1370 req
->interface_id
= cpu_to_le32(if_id
);
1371 req
->max_frame_size
= cpu_to_le16(BE_MAX_JUMBO_FRAME_SIZE
);
1372 req
->rss_queue
= cpu_to_le32(rss
);
1374 status
= be_mcc_notify_wait(adapter
);
1376 struct be_cmd_resp_eth_rx_create
*resp
= embedded_payload(wrb
);
1378 rxq
->id
= le16_to_cpu(resp
->id
);
1379 rxq
->created
= true;
1380 *rss_id
= resp
->rss_id
;
1384 spin_unlock_bh(&adapter
->mcc_lock
);
1388 /* Generic destroyer function for all types of queues
1391 int be_cmd_q_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
,
1394 struct be_mcc_wrb
*wrb
;
1395 struct be_cmd_req_q_destroy
*req
;
1396 u8 subsys
= 0, opcode
= 0;
1399 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
1402 wrb
= wrb_from_mbox(adapter
);
1403 req
= embedded_payload(wrb
);
1405 switch (queue_type
) {
1407 subsys
= CMD_SUBSYSTEM_COMMON
;
1408 opcode
= OPCODE_COMMON_EQ_DESTROY
;
1411 subsys
= CMD_SUBSYSTEM_COMMON
;
1412 opcode
= OPCODE_COMMON_CQ_DESTROY
;
1415 subsys
= CMD_SUBSYSTEM_ETH
;
1416 opcode
= OPCODE_ETH_TX_DESTROY
;
1419 subsys
= CMD_SUBSYSTEM_ETH
;
1420 opcode
= OPCODE_ETH_RX_DESTROY
;
1423 subsys
= CMD_SUBSYSTEM_COMMON
;
1424 opcode
= OPCODE_COMMON_MCC_DESTROY
;
1430 be_wrb_cmd_hdr_prepare(&req
->hdr
, subsys
, opcode
, sizeof(*req
), wrb
,
1432 req
->id
= cpu_to_le16(q
->id
);
1434 status
= be_mbox_notify_wait(adapter
);
1437 mutex_unlock(&adapter
->mbox_lock
);
1442 int be_cmd_rxq_destroy(struct be_adapter
*adapter
, struct be_queue_info
*q
)
1444 struct be_mcc_wrb
*wrb
;
1445 struct be_cmd_req_q_destroy
*req
;
1448 spin_lock_bh(&adapter
->mcc_lock
);
1450 wrb
= wrb_from_mccq(adapter
);
1455 req
= embedded_payload(wrb
);
1457 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1458 OPCODE_ETH_RX_DESTROY
, sizeof(*req
), wrb
, NULL
);
1459 req
->id
= cpu_to_le16(q
->id
);
1461 status
= be_mcc_notify_wait(adapter
);
1465 spin_unlock_bh(&adapter
->mcc_lock
);
1469 /* Create an rx filtering policy configuration on an i/f
1470 * Will use MBOX only if MCCQ has not been created.
1472 int be_cmd_if_create(struct be_adapter
*adapter
, u32 cap_flags
, u32 en_flags
,
1473 u32
*if_handle
, u32 domain
)
1475 struct be_mcc_wrb wrb
= {0};
1476 struct be_cmd_req_if_create
*req
;
1479 req
= embedded_payload(&wrb
);
1480 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1481 OPCODE_COMMON_NTWK_INTERFACE_CREATE
,
1482 sizeof(*req
), &wrb
, NULL
);
1483 req
->hdr
.domain
= domain
;
1484 req
->capability_flags
= cpu_to_le32(cap_flags
);
1485 req
->enable_flags
= cpu_to_le32(en_flags
);
1486 req
->pmac_invalid
= true;
1488 status
= be_cmd_notify_wait(adapter
, &wrb
);
1490 struct be_cmd_resp_if_create
*resp
= embedded_payload(&wrb
);
1492 *if_handle
= le32_to_cpu(resp
->interface_id
);
1494 /* Hack to retrieve VF's pmac-id on BE3 */
1495 if (BE3_chip(adapter
) && be_virtfn(adapter
))
1496 adapter
->pmac_id
[0] = le32_to_cpu(resp
->pmac_id
);
1502 int be_cmd_if_destroy(struct be_adapter
*adapter
, int interface_id
, u32 domain
)
1504 struct be_mcc_wrb
*wrb
;
1505 struct be_cmd_req_if_destroy
*req
;
1508 if (interface_id
== -1)
1511 spin_lock_bh(&adapter
->mcc_lock
);
1513 wrb
= wrb_from_mccq(adapter
);
1518 req
= embedded_payload(wrb
);
1520 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1521 OPCODE_COMMON_NTWK_INTERFACE_DESTROY
,
1522 sizeof(*req
), wrb
, NULL
);
1523 req
->hdr
.domain
= domain
;
1524 req
->interface_id
= cpu_to_le32(interface_id
);
1526 status
= be_mcc_notify_wait(adapter
);
1528 spin_unlock_bh(&adapter
->mcc_lock
);
1532 /* Get stats is a non embedded command: the request is not embedded inside
1533 * WRB but is a separate dma memory block
1534 * Uses asynchronous MCC
1536 int be_cmd_get_stats(struct be_adapter
*adapter
, struct be_dma_mem
*nonemb_cmd
)
1538 struct be_mcc_wrb
*wrb
;
1539 struct be_cmd_req_hdr
*hdr
;
1542 spin_lock_bh(&adapter
->mcc_lock
);
1544 wrb
= wrb_from_mccq(adapter
);
1549 hdr
= nonemb_cmd
->va
;
1551 be_wrb_cmd_hdr_prepare(hdr
, CMD_SUBSYSTEM_ETH
,
1552 OPCODE_ETH_GET_STATISTICS
, nonemb_cmd
->size
, wrb
,
1555 /* version 1 of the cmd is not supported only by BE2 */
1556 if (BE2_chip(adapter
))
1558 if (BE3_chip(adapter
) || lancer_chip(adapter
))
1563 status
= be_mcc_notify(adapter
);
1567 adapter
->stats_cmd_sent
= true;
1570 spin_unlock_bh(&adapter
->mcc_lock
);
1575 int lancer_cmd_get_pport_stats(struct be_adapter
*adapter
,
1576 struct be_dma_mem
*nonemb_cmd
)
1578 struct be_mcc_wrb
*wrb
;
1579 struct lancer_cmd_req_pport_stats
*req
;
1582 if (!be_cmd_allowed(adapter
, OPCODE_ETH_GET_PPORT_STATS
,
1586 spin_lock_bh(&adapter
->mcc_lock
);
1588 wrb
= wrb_from_mccq(adapter
);
1593 req
= nonemb_cmd
->va
;
1595 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
1596 OPCODE_ETH_GET_PPORT_STATS
, nonemb_cmd
->size
,
1599 req
->cmd_params
.params
.pport_num
= cpu_to_le16(adapter
->hba_port_num
);
1600 req
->cmd_params
.params
.reset_stats
= 0;
1602 status
= be_mcc_notify(adapter
);
1606 adapter
->stats_cmd_sent
= true;
1609 spin_unlock_bh(&adapter
->mcc_lock
);
1613 static int be_mac_to_link_speed(int mac_speed
)
1615 switch (mac_speed
) {
1616 case PHY_LINK_SPEED_ZERO
:
1618 case PHY_LINK_SPEED_10MBPS
:
1620 case PHY_LINK_SPEED_100MBPS
:
1622 case PHY_LINK_SPEED_1GBPS
:
1624 case PHY_LINK_SPEED_10GBPS
:
1626 case PHY_LINK_SPEED_20GBPS
:
1628 case PHY_LINK_SPEED_25GBPS
:
1630 case PHY_LINK_SPEED_40GBPS
:
1636 /* Uses synchronous mcc
1637 * Returns link_speed in Mbps
1639 int be_cmd_link_status_query(struct be_adapter
*adapter
, u16
*link_speed
,
1640 u8
*link_status
, u32 dom
)
1642 struct be_mcc_wrb
*wrb
;
1643 struct be_cmd_req_link_status
*req
;
1646 spin_lock_bh(&adapter
->mcc_lock
);
1649 *link_status
= LINK_DOWN
;
1651 wrb
= wrb_from_mccq(adapter
);
1656 req
= embedded_payload(wrb
);
1658 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1659 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY
,
1660 sizeof(*req
), wrb
, NULL
);
1662 /* version 1 of the cmd is not supported only by BE2 */
1663 if (!BE2_chip(adapter
))
1664 req
->hdr
.version
= 1;
1666 req
->hdr
.domain
= dom
;
1668 status
= be_mcc_notify_wait(adapter
);
1670 struct be_cmd_resp_link_status
*resp
= embedded_payload(wrb
);
1673 *link_speed
= resp
->link_speed
?
1674 le16_to_cpu(resp
->link_speed
) * 10 :
1675 be_mac_to_link_speed(resp
->mac_speed
);
1677 if (!resp
->logical_link_status
)
1681 *link_status
= resp
->logical_link_status
;
1685 spin_unlock_bh(&adapter
->mcc_lock
);
1689 /* Uses synchronous mcc */
1690 int be_cmd_get_die_temperature(struct be_adapter
*adapter
)
1692 struct be_mcc_wrb
*wrb
;
1693 struct be_cmd_req_get_cntl_addnl_attribs
*req
;
1696 spin_lock_bh(&adapter
->mcc_lock
);
1698 wrb
= wrb_from_mccq(adapter
);
1703 req
= embedded_payload(wrb
);
1705 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1706 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES
,
1707 sizeof(*req
), wrb
, NULL
);
1709 status
= be_mcc_notify(adapter
);
1711 spin_unlock_bh(&adapter
->mcc_lock
);
1715 /* Uses synchronous mcc */
1716 int be_cmd_get_reg_len(struct be_adapter
*adapter
, u32
*log_size
)
1718 struct be_mcc_wrb
*wrb
;
1719 struct be_cmd_req_get_fat
*req
;
1722 spin_lock_bh(&adapter
->mcc_lock
);
1724 wrb
= wrb_from_mccq(adapter
);
1729 req
= embedded_payload(wrb
);
1731 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1732 OPCODE_COMMON_MANAGE_FAT
, sizeof(*req
), wrb
,
1734 req
->fat_operation
= cpu_to_le32(QUERY_FAT
);
1735 status
= be_mcc_notify_wait(adapter
);
1737 struct be_cmd_resp_get_fat
*resp
= embedded_payload(wrb
);
1739 if (log_size
&& resp
->log_size
)
1740 *log_size
= le32_to_cpu(resp
->log_size
) -
1744 spin_unlock_bh(&adapter
->mcc_lock
);
1748 int be_cmd_get_regs(struct be_adapter
*adapter
, u32 buf_len
, void *buf
)
1750 struct be_dma_mem get_fat_cmd
;
1751 struct be_mcc_wrb
*wrb
;
1752 struct be_cmd_req_get_fat
*req
;
1753 u32 offset
= 0, total_size
, buf_size
,
1754 log_offset
= sizeof(u32
), payload_len
;
1760 total_size
= buf_len
;
1762 get_fat_cmd
.size
= sizeof(struct be_cmd_req_get_fat
) + 60*1024;
1763 get_fat_cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
,
1765 &get_fat_cmd
.dma
, GFP_ATOMIC
);
1766 if (!get_fat_cmd
.va
) {
1767 dev_err(&adapter
->pdev
->dev
,
1768 "Memory allocation failure while reading FAT data\n");
1772 spin_lock_bh(&adapter
->mcc_lock
);
1774 while (total_size
) {
1775 buf_size
= min(total_size
, (u32
)60*1024);
1776 total_size
-= buf_size
;
1778 wrb
= wrb_from_mccq(adapter
);
1783 req
= get_fat_cmd
.va
;
1785 payload_len
= sizeof(struct be_cmd_req_get_fat
) + buf_size
;
1786 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1787 OPCODE_COMMON_MANAGE_FAT
, payload_len
,
1790 req
->fat_operation
= cpu_to_le32(RETRIEVE_FAT
);
1791 req
->read_log_offset
= cpu_to_le32(log_offset
);
1792 req
->read_log_length
= cpu_to_le32(buf_size
);
1793 req
->data_buffer_size
= cpu_to_le32(buf_size
);
1795 status
= be_mcc_notify_wait(adapter
);
1797 struct be_cmd_resp_get_fat
*resp
= get_fat_cmd
.va
;
1799 memcpy(buf
+ offset
,
1801 le32_to_cpu(resp
->read_log_length
));
1803 dev_err(&adapter
->pdev
->dev
, "FAT Table Retrieve error\n");
1807 log_offset
+= buf_size
;
1810 dma_free_coherent(&adapter
->pdev
->dev
, get_fat_cmd
.size
,
1811 get_fat_cmd
.va
, get_fat_cmd
.dma
);
1812 spin_unlock_bh(&adapter
->mcc_lock
);
1816 /* Uses synchronous mcc */
1817 int be_cmd_get_fw_ver(struct be_adapter
*adapter
)
1819 struct be_mcc_wrb
*wrb
;
1820 struct be_cmd_req_get_fw_version
*req
;
1823 spin_lock_bh(&adapter
->mcc_lock
);
1825 wrb
= wrb_from_mccq(adapter
);
1831 req
= embedded_payload(wrb
);
1833 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1834 OPCODE_COMMON_GET_FW_VERSION
, sizeof(*req
), wrb
,
1836 status
= be_mcc_notify_wait(adapter
);
1838 struct be_cmd_resp_get_fw_version
*resp
= embedded_payload(wrb
);
1840 strlcpy(adapter
->fw_ver
, resp
->firmware_version_string
,
1841 sizeof(adapter
->fw_ver
));
1842 strlcpy(adapter
->fw_on_flash
, resp
->fw_on_flash_version_string
,
1843 sizeof(adapter
->fw_on_flash
));
1846 spin_unlock_bh(&adapter
->mcc_lock
);
1850 /* set the EQ delay interval of an EQ to specified value
1853 static int __be_cmd_modify_eqd(struct be_adapter
*adapter
,
1854 struct be_set_eqd
*set_eqd
, int num
)
1856 struct be_mcc_wrb
*wrb
;
1857 struct be_cmd_req_modify_eq_delay
*req
;
1860 spin_lock_bh(&adapter
->mcc_lock
);
1862 wrb
= wrb_from_mccq(adapter
);
1867 req
= embedded_payload(wrb
);
1869 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1870 OPCODE_COMMON_MODIFY_EQ_DELAY
, sizeof(*req
), wrb
,
1873 req
->num_eq
= cpu_to_le32(num
);
1874 for (i
= 0; i
< num
; i
++) {
1875 req
->set_eqd
[i
].eq_id
= cpu_to_le32(set_eqd
[i
].eq_id
);
1876 req
->set_eqd
[i
].phase
= 0;
1877 req
->set_eqd
[i
].delay_multiplier
=
1878 cpu_to_le32(set_eqd
[i
].delay_multiplier
);
1881 status
= be_mcc_notify(adapter
);
1883 spin_unlock_bh(&adapter
->mcc_lock
);
1887 int be_cmd_modify_eqd(struct be_adapter
*adapter
, struct be_set_eqd
*set_eqd
,
1893 num_eqs
= min(num
, 8);
1894 __be_cmd_modify_eqd(adapter
, &set_eqd
[i
], num_eqs
);
1902 /* Uses sycnhronous mcc */
1903 int be_cmd_vlan_config(struct be_adapter
*adapter
, u32 if_id
, u16
*vtag_array
,
1904 u32 num
, u32 domain
)
1906 struct be_mcc_wrb
*wrb
;
1907 struct be_cmd_req_vlan_config
*req
;
1910 spin_lock_bh(&adapter
->mcc_lock
);
1912 wrb
= wrb_from_mccq(adapter
);
1917 req
= embedded_payload(wrb
);
1919 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1920 OPCODE_COMMON_NTWK_VLAN_CONFIG
, sizeof(*req
),
1922 req
->hdr
.domain
= domain
;
1924 req
->interface_id
= if_id
;
1925 req
->untagged
= BE_IF_FLAGS_UNTAGGED
& be_if_cap_flags(adapter
) ? 1 : 0;
1926 req
->num_vlan
= num
;
1927 memcpy(req
->normal_vlan
, vtag_array
,
1928 req
->num_vlan
* sizeof(vtag_array
[0]));
1930 status
= be_mcc_notify_wait(adapter
);
1932 spin_unlock_bh(&adapter
->mcc_lock
);
1936 static int __be_cmd_rx_filter(struct be_adapter
*adapter
, u32 flags
, u32 value
)
1938 struct be_mcc_wrb
*wrb
;
1939 struct be_dma_mem
*mem
= &adapter
->rx_filter
;
1940 struct be_cmd_req_rx_filter
*req
= mem
->va
;
1943 spin_lock_bh(&adapter
->mcc_lock
);
1945 wrb
= wrb_from_mccq(adapter
);
1950 memset(req
, 0, sizeof(*req
));
1951 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
1952 OPCODE_COMMON_NTWK_RX_FILTER
, sizeof(*req
),
1955 req
->if_id
= cpu_to_le32(adapter
->if_handle
);
1956 req
->if_flags_mask
= cpu_to_le32(flags
);
1957 req
->if_flags
= (value
== ON
) ? req
->if_flags_mask
: 0;
1959 if (flags
& BE_IF_FLAGS_MULTICAST
) {
1960 struct netdev_hw_addr
*ha
;
1963 /* Reset mcast promisc mode if already set by setting mask
1964 * and not setting flags field
1966 req
->if_flags_mask
|=
1967 cpu_to_le32(BE_IF_FLAGS_MCAST_PROMISCUOUS
&
1968 be_if_cap_flags(adapter
));
1969 req
->mcast_num
= cpu_to_le32(netdev_mc_count(adapter
->netdev
));
1970 netdev_for_each_mc_addr(ha
, adapter
->netdev
)
1971 memcpy(req
->mcast_mac
[i
++].byte
, ha
->addr
, ETH_ALEN
);
1974 status
= be_mcc_notify_wait(adapter
);
1976 spin_unlock_bh(&adapter
->mcc_lock
);
1980 int be_cmd_rx_filter(struct be_adapter
*adapter
, u32 flags
, u32 value
)
1982 struct device
*dev
= &adapter
->pdev
->dev
;
1984 if ((flags
& be_if_cap_flags(adapter
)) != flags
) {
1985 dev_warn(dev
, "Cannot set rx filter flags 0x%x\n", flags
);
1986 dev_warn(dev
, "Interface is capable of 0x%x flags only\n",
1987 be_if_cap_flags(adapter
));
1989 flags
&= be_if_cap_flags(adapter
);
1991 return __be_cmd_rx_filter(adapter
, flags
, value
);
1994 /* Uses synchrounous mcc */
1995 int be_cmd_set_flow_control(struct be_adapter
*adapter
, u32 tx_fc
, u32 rx_fc
)
1997 struct be_mcc_wrb
*wrb
;
1998 struct be_cmd_req_set_flow_control
*req
;
2001 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_SET_FLOW_CONTROL
,
2002 CMD_SUBSYSTEM_COMMON
))
2005 spin_lock_bh(&adapter
->mcc_lock
);
2007 wrb
= wrb_from_mccq(adapter
);
2012 req
= embedded_payload(wrb
);
2014 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2015 OPCODE_COMMON_SET_FLOW_CONTROL
, sizeof(*req
),
2018 req
->hdr
.version
= 1;
2019 req
->tx_flow_control
= cpu_to_le16((u16
)tx_fc
);
2020 req
->rx_flow_control
= cpu_to_le16((u16
)rx_fc
);
2022 status
= be_mcc_notify_wait(adapter
);
2025 spin_unlock_bh(&adapter
->mcc_lock
);
2027 if (base_status(status
) == MCC_STATUS_FEATURE_NOT_SUPPORTED
)
2034 int be_cmd_get_flow_control(struct be_adapter
*adapter
, u32
*tx_fc
, u32
*rx_fc
)
2036 struct be_mcc_wrb
*wrb
;
2037 struct be_cmd_req_get_flow_control
*req
;
2040 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_GET_FLOW_CONTROL
,
2041 CMD_SUBSYSTEM_COMMON
))
2044 spin_lock_bh(&adapter
->mcc_lock
);
2046 wrb
= wrb_from_mccq(adapter
);
2051 req
= embedded_payload(wrb
);
2053 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2054 OPCODE_COMMON_GET_FLOW_CONTROL
, sizeof(*req
),
2057 status
= be_mcc_notify_wait(adapter
);
2059 struct be_cmd_resp_get_flow_control
*resp
=
2060 embedded_payload(wrb
);
2062 *tx_fc
= le16_to_cpu(resp
->tx_flow_control
);
2063 *rx_fc
= le16_to_cpu(resp
->rx_flow_control
);
2067 spin_unlock_bh(&adapter
->mcc_lock
);
2072 int be_cmd_query_fw_cfg(struct be_adapter
*adapter
)
2074 struct be_mcc_wrb
*wrb
;
2075 struct be_cmd_req_query_fw_cfg
*req
;
2078 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2081 wrb
= wrb_from_mbox(adapter
);
2082 req
= embedded_payload(wrb
);
2084 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2085 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG
,
2086 sizeof(*req
), wrb
, NULL
);
2088 status
= be_mbox_notify_wait(adapter
);
2090 struct be_cmd_resp_query_fw_cfg
*resp
= embedded_payload(wrb
);
2092 adapter
->port_num
= le32_to_cpu(resp
->phys_port
);
2093 adapter
->function_mode
= le32_to_cpu(resp
->function_mode
);
2094 adapter
->function_caps
= le32_to_cpu(resp
->function_caps
);
2095 adapter
->asic_rev
= le32_to_cpu(resp
->asic_revision
) & 0xFF;
2096 dev_info(&adapter
->pdev
->dev
,
2097 "FW config: function_mode=0x%x, function_caps=0x%x\n",
2098 adapter
->function_mode
, adapter
->function_caps
);
2101 mutex_unlock(&adapter
->mbox_lock
);
2106 int be_cmd_reset_function(struct be_adapter
*adapter
)
2108 struct be_mcc_wrb
*wrb
;
2109 struct be_cmd_req_hdr
*req
;
2112 if (lancer_chip(adapter
)) {
2113 iowrite32(SLI_PORT_CONTROL_IP_MASK
,
2114 adapter
->db
+ SLIPORT_CONTROL_OFFSET
);
2115 status
= lancer_wait_ready(adapter
);
2117 dev_err(&adapter
->pdev
->dev
,
2118 "Adapter in non recoverable error\n");
2122 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2125 wrb
= wrb_from_mbox(adapter
);
2126 req
= embedded_payload(wrb
);
2128 be_wrb_cmd_hdr_prepare(req
, CMD_SUBSYSTEM_COMMON
,
2129 OPCODE_COMMON_FUNCTION_RESET
, sizeof(*req
), wrb
,
2132 status
= be_mbox_notify_wait(adapter
);
2134 mutex_unlock(&adapter
->mbox_lock
);
2138 int be_cmd_rss_config(struct be_adapter
*adapter
, u8
*rsstable
,
2139 u32 rss_hash_opts
, u16 table_size
, const u8
*rss_hkey
)
2141 struct be_mcc_wrb
*wrb
;
2142 struct be_cmd_req_rss_config
*req
;
2145 if (!(be_if_cap_flags(adapter
) & BE_IF_FLAGS_RSS
))
2148 spin_lock_bh(&adapter
->mcc_lock
);
2150 wrb
= wrb_from_mccq(adapter
);
2155 req
= embedded_payload(wrb
);
2157 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
2158 OPCODE_ETH_RSS_CONFIG
, sizeof(*req
), wrb
, NULL
);
2160 req
->if_id
= cpu_to_le32(adapter
->if_handle
);
2161 req
->enable_rss
= cpu_to_le16(rss_hash_opts
);
2162 req
->cpu_table_size_log2
= cpu_to_le16(fls(table_size
) - 1);
2164 if (!BEx_chip(adapter
))
2165 req
->hdr
.version
= 1;
2167 memcpy(req
->cpu_table
, rsstable
, table_size
);
2168 memcpy(req
->hash
, rss_hkey
, RSS_HASH_KEY_LEN
);
2169 be_dws_cpu_to_le(req
->hash
, sizeof(req
->hash
));
2171 status
= be_mcc_notify_wait(adapter
);
2173 spin_unlock_bh(&adapter
->mcc_lock
);
2178 int be_cmd_set_beacon_state(struct be_adapter
*adapter
, u8 port_num
,
2179 u8 bcn
, u8 sts
, u8 state
)
2181 struct be_mcc_wrb
*wrb
;
2182 struct be_cmd_req_enable_disable_beacon
*req
;
2185 spin_lock_bh(&adapter
->mcc_lock
);
2187 wrb
= wrb_from_mccq(adapter
);
2192 req
= embedded_payload(wrb
);
2194 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2195 OPCODE_COMMON_ENABLE_DISABLE_BEACON
,
2196 sizeof(*req
), wrb
, NULL
);
2198 req
->port_num
= port_num
;
2199 req
->beacon_state
= state
;
2200 req
->beacon_duration
= bcn
;
2201 req
->status_duration
= sts
;
2203 status
= be_mcc_notify_wait(adapter
);
2206 spin_unlock_bh(&adapter
->mcc_lock
);
2211 int be_cmd_get_beacon_state(struct be_adapter
*adapter
, u8 port_num
, u32
*state
)
2213 struct be_mcc_wrb
*wrb
;
2214 struct be_cmd_req_get_beacon_state
*req
;
2217 spin_lock_bh(&adapter
->mcc_lock
);
2219 wrb
= wrb_from_mccq(adapter
);
2224 req
= embedded_payload(wrb
);
2226 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2227 OPCODE_COMMON_GET_BEACON_STATE
, sizeof(*req
),
2230 req
->port_num
= port_num
;
2232 status
= be_mcc_notify_wait(adapter
);
2234 struct be_cmd_resp_get_beacon_state
*resp
=
2235 embedded_payload(wrb
);
2237 *state
= resp
->beacon_state
;
2241 spin_unlock_bh(&adapter
->mcc_lock
);
2246 int be_cmd_read_port_transceiver_data(struct be_adapter
*adapter
,
2247 u8 page_num
, u8
*data
)
2249 struct be_dma_mem cmd
;
2250 struct be_mcc_wrb
*wrb
;
2251 struct be_cmd_req_port_type
*req
;
2254 if (page_num
> TR_PAGE_A2
)
2257 cmd
.size
= sizeof(struct be_cmd_resp_port_type
);
2258 cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
, cmd
.size
, &cmd
.dma
,
2261 dev_err(&adapter
->pdev
->dev
, "Memory allocation failed\n");
2265 spin_lock_bh(&adapter
->mcc_lock
);
2267 wrb
= wrb_from_mccq(adapter
);
2274 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2275 OPCODE_COMMON_READ_TRANSRECV_DATA
,
2276 cmd
.size
, wrb
, &cmd
);
2278 req
->port
= cpu_to_le32(adapter
->hba_port_num
);
2279 req
->page_num
= cpu_to_le32(page_num
);
2280 status
= be_mcc_notify_wait(adapter
);
2282 struct be_cmd_resp_port_type
*resp
= cmd
.va
;
2284 memcpy(data
, resp
->page_data
, PAGE_DATA_LEN
);
2287 spin_unlock_bh(&adapter
->mcc_lock
);
2288 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
, cmd
.va
, cmd
.dma
);
2292 int lancer_cmd_write_object(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2293 u32 data_size
, u32 data_offset
,
2294 const char *obj_name
, u32
*data_written
,
2295 u8
*change_status
, u8
*addn_status
)
2297 struct be_mcc_wrb
*wrb
;
2298 struct lancer_cmd_req_write_object
*req
;
2299 struct lancer_cmd_resp_write_object
*resp
;
2303 spin_lock_bh(&adapter
->mcc_lock
);
2304 adapter
->flash_status
= 0;
2306 wrb
= wrb_from_mccq(adapter
);
2312 req
= embedded_payload(wrb
);
2314 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2315 OPCODE_COMMON_WRITE_OBJECT
,
2316 sizeof(struct lancer_cmd_req_write_object
), wrb
,
2319 ctxt
= &req
->context
;
2320 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2321 write_length
, ctxt
, data_size
);
2324 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2327 AMAP_SET_BITS(struct amap_lancer_write_obj_context
,
2330 be_dws_cpu_to_le(ctxt
, sizeof(req
->context
));
2331 req
->write_offset
= cpu_to_le32(data_offset
);
2332 strlcpy(req
->object_name
, obj_name
, sizeof(req
->object_name
));
2333 req
->descriptor_count
= cpu_to_le32(1);
2334 req
->buf_len
= cpu_to_le32(data_size
);
2335 req
->addr_low
= cpu_to_le32((cmd
->dma
+
2336 sizeof(struct lancer_cmd_req_write_object
))
2338 req
->addr_high
= cpu_to_le32(upper_32_bits(cmd
->dma
+
2339 sizeof(struct lancer_cmd_req_write_object
)));
2341 status
= be_mcc_notify(adapter
);
2345 spin_unlock_bh(&adapter
->mcc_lock
);
2347 if (!wait_for_completion_timeout(&adapter
->et_cmd_compl
,
2348 msecs_to_jiffies(60000)))
2349 status
= -ETIMEDOUT
;
2351 status
= adapter
->flash_status
;
2353 resp
= embedded_payload(wrb
);
2355 *data_written
= le32_to_cpu(resp
->actual_write_len
);
2356 *change_status
= resp
->change_status
;
2358 *addn_status
= resp
->additional_status
;
2364 spin_unlock_bh(&adapter
->mcc_lock
);
2368 int be_cmd_query_cable_type(struct be_adapter
*adapter
)
2370 u8 page_data
[PAGE_DATA_LEN
];
2373 status
= be_cmd_read_port_transceiver_data(adapter
, TR_PAGE_A0
,
2376 switch (adapter
->phy
.interface_type
) {
2378 adapter
->phy
.cable_type
=
2379 page_data
[QSFP_PLUS_CABLE_TYPE_OFFSET
];
2381 case PHY_TYPE_SFP_PLUS_10GB
:
2382 adapter
->phy
.cable_type
=
2383 page_data
[SFP_PLUS_CABLE_TYPE_OFFSET
];
2386 adapter
->phy
.cable_type
= 0;
2393 int be_cmd_query_sfp_info(struct be_adapter
*adapter
)
2395 u8 page_data
[PAGE_DATA_LEN
];
2398 status
= be_cmd_read_port_transceiver_data(adapter
, TR_PAGE_A0
,
2401 strlcpy(adapter
->phy
.vendor_name
, page_data
+
2402 SFP_VENDOR_NAME_OFFSET
, SFP_VENDOR_NAME_LEN
- 1);
2403 strlcpy(adapter
->phy
.vendor_pn
,
2404 page_data
+ SFP_VENDOR_PN_OFFSET
,
2405 SFP_VENDOR_NAME_LEN
- 1);
2411 int lancer_cmd_delete_object(struct be_adapter
*adapter
, const char *obj_name
)
2413 struct lancer_cmd_req_delete_object
*req
;
2414 struct be_mcc_wrb
*wrb
;
2417 spin_lock_bh(&adapter
->mcc_lock
);
2419 wrb
= wrb_from_mccq(adapter
);
2425 req
= embedded_payload(wrb
);
2427 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2428 OPCODE_COMMON_DELETE_OBJECT
,
2429 sizeof(*req
), wrb
, NULL
);
2431 strlcpy(req
->object_name
, obj_name
, sizeof(req
->object_name
));
2433 status
= be_mcc_notify_wait(adapter
);
2435 spin_unlock_bh(&adapter
->mcc_lock
);
2439 int lancer_cmd_read_object(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2440 u32 data_size
, u32 data_offset
, const char *obj_name
,
2441 u32
*data_read
, u32
*eof
, u8
*addn_status
)
2443 struct be_mcc_wrb
*wrb
;
2444 struct lancer_cmd_req_read_object
*req
;
2445 struct lancer_cmd_resp_read_object
*resp
;
2448 spin_lock_bh(&adapter
->mcc_lock
);
2450 wrb
= wrb_from_mccq(adapter
);
2456 req
= embedded_payload(wrb
);
2458 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2459 OPCODE_COMMON_READ_OBJECT
,
2460 sizeof(struct lancer_cmd_req_read_object
), wrb
,
2463 req
->desired_read_len
= cpu_to_le32(data_size
);
2464 req
->read_offset
= cpu_to_le32(data_offset
);
2465 strcpy(req
->object_name
, obj_name
);
2466 req
->descriptor_count
= cpu_to_le32(1);
2467 req
->buf_len
= cpu_to_le32(data_size
);
2468 req
->addr_low
= cpu_to_le32((cmd
->dma
& 0xFFFFFFFF));
2469 req
->addr_high
= cpu_to_le32(upper_32_bits(cmd
->dma
));
2471 status
= be_mcc_notify_wait(adapter
);
2473 resp
= embedded_payload(wrb
);
2475 *data_read
= le32_to_cpu(resp
->actual_read_len
);
2476 *eof
= le32_to_cpu(resp
->eof
);
2478 *addn_status
= resp
->additional_status
;
2482 spin_unlock_bh(&adapter
->mcc_lock
);
2486 int be_cmd_write_flashrom(struct be_adapter
*adapter
, struct be_dma_mem
*cmd
,
2487 u32 flash_type
, u32 flash_opcode
, u32 img_offset
,
2490 struct be_mcc_wrb
*wrb
;
2491 struct be_cmd_write_flashrom
*req
;
2494 spin_lock_bh(&adapter
->mcc_lock
);
2495 adapter
->flash_status
= 0;
2497 wrb
= wrb_from_mccq(adapter
);
2504 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2505 OPCODE_COMMON_WRITE_FLASHROM
, cmd
->size
, wrb
,
2508 req
->params
.op_type
= cpu_to_le32(flash_type
);
2509 if (flash_type
== OPTYPE_OFFSET_SPECIFIED
)
2510 req
->params
.offset
= cpu_to_le32(img_offset
);
2512 req
->params
.op_code
= cpu_to_le32(flash_opcode
);
2513 req
->params
.data_buf_size
= cpu_to_le32(buf_size
);
2515 status
= be_mcc_notify(adapter
);
2519 spin_unlock_bh(&adapter
->mcc_lock
);
2521 if (!wait_for_completion_timeout(&adapter
->et_cmd_compl
,
2522 msecs_to_jiffies(40000)))
2523 status
= -ETIMEDOUT
;
2525 status
= adapter
->flash_status
;
2530 spin_unlock_bh(&adapter
->mcc_lock
);
2534 int be_cmd_get_flash_crc(struct be_adapter
*adapter
, u8
*flashed_crc
,
2535 u16 img_optype
, u32 img_offset
, u32 crc_offset
)
2537 struct be_cmd_read_flash_crc
*req
;
2538 struct be_mcc_wrb
*wrb
;
2541 spin_lock_bh(&adapter
->mcc_lock
);
2543 wrb
= wrb_from_mccq(adapter
);
2548 req
= embedded_payload(wrb
);
2550 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2551 OPCODE_COMMON_READ_FLASHROM
, sizeof(*req
),
2554 req
->params
.op_type
= cpu_to_le32(img_optype
);
2555 if (img_optype
== OPTYPE_OFFSET_SPECIFIED
)
2556 req
->params
.offset
= cpu_to_le32(img_offset
+ crc_offset
);
2558 req
->params
.offset
= cpu_to_le32(crc_offset
);
2560 req
->params
.op_code
= cpu_to_le32(FLASHROM_OPER_REPORT
);
2561 req
->params
.data_buf_size
= cpu_to_le32(0x4);
2563 status
= be_mcc_notify_wait(adapter
);
2565 memcpy(flashed_crc
, req
->crc
, 4);
2568 spin_unlock_bh(&adapter
->mcc_lock
);
2572 int be_cmd_enable_magic_wol(struct be_adapter
*adapter
, u8
*mac
,
2573 struct be_dma_mem
*nonemb_cmd
)
2575 struct be_mcc_wrb
*wrb
;
2576 struct be_cmd_req_acpi_wol_magic_config
*req
;
2579 spin_lock_bh(&adapter
->mcc_lock
);
2581 wrb
= wrb_from_mccq(adapter
);
2586 req
= nonemb_cmd
->va
;
2588 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
2589 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
, sizeof(*req
),
2591 memcpy(req
->magic_mac
, mac
, ETH_ALEN
);
2593 status
= be_mcc_notify_wait(adapter
);
2596 spin_unlock_bh(&adapter
->mcc_lock
);
2600 int be_cmd_set_loopback(struct be_adapter
*adapter
, u8 port_num
,
2601 u8 loopback_type
, u8 enable
)
2603 struct be_mcc_wrb
*wrb
;
2604 struct be_cmd_req_set_lmode
*req
;
2607 spin_lock_bh(&adapter
->mcc_lock
);
2609 wrb
= wrb_from_mccq(adapter
);
2615 req
= embedded_payload(wrb
);
2617 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2618 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE
, sizeof(*req
),
2621 req
->src_port
= port_num
;
2622 req
->dest_port
= port_num
;
2623 req
->loopback_type
= loopback_type
;
2624 req
->loopback_state
= enable
;
2626 status
= be_mcc_notify(adapter
);
2630 spin_unlock_bh(&adapter
->mcc_lock
);
2632 if (!wait_for_completion_timeout(&adapter
->et_cmd_compl
,
2633 msecs_to_jiffies(SET_LB_MODE_TIMEOUT
)))
2634 status
= -ETIMEDOUT
;
2639 spin_unlock_bh(&adapter
->mcc_lock
);
2643 int be_cmd_loopback_test(struct be_adapter
*adapter
, u32 port_num
,
2644 u32 loopback_type
, u32 pkt_size
, u32 num_pkts
,
2647 struct be_mcc_wrb
*wrb
;
2648 struct be_cmd_req_loopback_test
*req
;
2649 struct be_cmd_resp_loopback_test
*resp
;
2652 spin_lock_bh(&adapter
->mcc_lock
);
2654 wrb
= wrb_from_mccq(adapter
);
2660 req
= embedded_payload(wrb
);
2662 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2663 OPCODE_LOWLEVEL_LOOPBACK_TEST
, sizeof(*req
), wrb
,
2666 req
->hdr
.timeout
= cpu_to_le32(15);
2667 req
->pattern
= cpu_to_le64(pattern
);
2668 req
->src_port
= cpu_to_le32(port_num
);
2669 req
->dest_port
= cpu_to_le32(port_num
);
2670 req
->pkt_size
= cpu_to_le32(pkt_size
);
2671 req
->num_pkts
= cpu_to_le32(num_pkts
);
2672 req
->loopback_type
= cpu_to_le32(loopback_type
);
2674 status
= be_mcc_notify(adapter
);
2678 spin_unlock_bh(&adapter
->mcc_lock
);
2680 wait_for_completion(&adapter
->et_cmd_compl
);
2681 resp
= embedded_payload(wrb
);
2682 status
= le32_to_cpu(resp
->status
);
2686 spin_unlock_bh(&adapter
->mcc_lock
);
2690 int be_cmd_ddr_dma_test(struct be_adapter
*adapter
, u64 pattern
,
2691 u32 byte_cnt
, struct be_dma_mem
*cmd
)
2693 struct be_mcc_wrb
*wrb
;
2694 struct be_cmd_req_ddrdma_test
*req
;
2698 spin_lock_bh(&adapter
->mcc_lock
);
2700 wrb
= wrb_from_mccq(adapter
);
2706 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_LOWLEVEL
,
2707 OPCODE_LOWLEVEL_HOST_DDR_DMA
, cmd
->size
, wrb
,
2710 req
->pattern
= cpu_to_le64(pattern
);
2711 req
->byte_count
= cpu_to_le32(byte_cnt
);
2712 for (i
= 0; i
< byte_cnt
; i
++) {
2713 req
->snd_buff
[i
] = (u8
)(pattern
>> (j
*8));
2719 status
= be_mcc_notify_wait(adapter
);
2722 struct be_cmd_resp_ddrdma_test
*resp
;
2725 if ((memcmp(resp
->rcv_buff
, req
->snd_buff
, byte_cnt
) != 0) ||
2732 spin_unlock_bh(&adapter
->mcc_lock
);
2736 int be_cmd_get_seeprom_data(struct be_adapter
*adapter
,
2737 struct be_dma_mem
*nonemb_cmd
)
2739 struct be_mcc_wrb
*wrb
;
2740 struct be_cmd_req_seeprom_read
*req
;
2743 spin_lock_bh(&adapter
->mcc_lock
);
2745 wrb
= wrb_from_mccq(adapter
);
2750 req
= nonemb_cmd
->va
;
2752 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2753 OPCODE_COMMON_SEEPROM_READ
, sizeof(*req
), wrb
,
2756 status
= be_mcc_notify_wait(adapter
);
2759 spin_unlock_bh(&adapter
->mcc_lock
);
2763 int be_cmd_get_phy_info(struct be_adapter
*adapter
)
2765 struct be_mcc_wrb
*wrb
;
2766 struct be_cmd_req_get_phy_info
*req
;
2767 struct be_dma_mem cmd
;
2770 if (!be_cmd_allowed(adapter
, OPCODE_COMMON_GET_PHY_DETAILS
,
2771 CMD_SUBSYSTEM_COMMON
))
2774 spin_lock_bh(&adapter
->mcc_lock
);
2776 wrb
= wrb_from_mccq(adapter
);
2781 cmd
.size
= sizeof(struct be_cmd_req_get_phy_info
);
2782 cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
, cmd
.size
, &cmd
.dma
,
2785 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
2792 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2793 OPCODE_COMMON_GET_PHY_DETAILS
, sizeof(*req
),
2796 status
= be_mcc_notify_wait(adapter
);
2798 struct be_phy_info
*resp_phy_info
=
2799 cmd
.va
+ sizeof(struct be_cmd_req_hdr
);
2801 adapter
->phy
.phy_type
= le16_to_cpu(resp_phy_info
->phy_type
);
2802 adapter
->phy
.interface_type
=
2803 le16_to_cpu(resp_phy_info
->interface_type
);
2804 adapter
->phy
.auto_speeds_supported
=
2805 le16_to_cpu(resp_phy_info
->auto_speeds_supported
);
2806 adapter
->phy
.fixed_speeds_supported
=
2807 le16_to_cpu(resp_phy_info
->fixed_speeds_supported
);
2808 adapter
->phy
.misc_params
=
2809 le32_to_cpu(resp_phy_info
->misc_params
);
2811 if (BE2_chip(adapter
)) {
2812 adapter
->phy
.fixed_speeds_supported
=
2813 BE_SUPPORTED_SPEED_10GBPS
|
2814 BE_SUPPORTED_SPEED_1GBPS
;
2817 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
, cmd
.va
, cmd
.dma
);
2819 spin_unlock_bh(&adapter
->mcc_lock
);
2823 static int be_cmd_set_qos(struct be_adapter
*adapter
, u32 bps
, u32 domain
)
2825 struct be_mcc_wrb
*wrb
;
2826 struct be_cmd_req_set_qos
*req
;
2829 spin_lock_bh(&adapter
->mcc_lock
);
2831 wrb
= wrb_from_mccq(adapter
);
2837 req
= embedded_payload(wrb
);
2839 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2840 OPCODE_COMMON_SET_QOS
, sizeof(*req
), wrb
, NULL
);
2842 req
->hdr
.domain
= domain
;
2843 req
->valid_bits
= cpu_to_le32(BE_QOS_BITS_NIC
);
2844 req
->max_bps_nic
= cpu_to_le32(bps
);
2846 status
= be_mcc_notify_wait(adapter
);
2849 spin_unlock_bh(&adapter
->mcc_lock
);
2853 int be_cmd_get_cntl_attributes(struct be_adapter
*adapter
)
2855 struct be_mcc_wrb
*wrb
;
2856 struct be_cmd_req_cntl_attribs
*req
;
2857 struct be_cmd_resp_cntl_attribs
*resp
;
2859 int payload_len
= max(sizeof(*req
), sizeof(*resp
));
2860 struct mgmt_controller_attrib
*attribs
;
2861 struct be_dma_mem attribs_cmd
;
2864 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2867 memset(&attribs_cmd
, 0, sizeof(struct be_dma_mem
));
2868 attribs_cmd
.size
= sizeof(struct be_cmd_resp_cntl_attribs
);
2869 attribs_cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
,
2871 &attribs_cmd
.dma
, GFP_ATOMIC
);
2872 if (!attribs_cmd
.va
) {
2873 dev_err(&adapter
->pdev
->dev
, "Memory allocation failure\n");
2878 wrb
= wrb_from_mbox(adapter
);
2883 req
= attribs_cmd
.va
;
2885 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2886 OPCODE_COMMON_GET_CNTL_ATTRIBUTES
, payload_len
,
2889 status
= be_mbox_notify_wait(adapter
);
2891 attribs
= attribs_cmd
.va
+ sizeof(struct be_cmd_resp_hdr
);
2892 adapter
->hba_port_num
= attribs
->hba_attribs
.phy_port
;
2893 adapter
->pci_func_num
= attribs
->pci_func_num
;
2894 serial_num
= attribs
->hba_attribs
.controller_serial_number
;
2895 for (i
= 0; i
< CNTL_SERIAL_NUM_WORDS
; i
++)
2896 adapter
->serial_num
[i
] = le32_to_cpu(serial_num
[i
]) &
2901 mutex_unlock(&adapter
->mbox_lock
);
2903 dma_free_coherent(&adapter
->pdev
->dev
, attribs_cmd
.size
,
2904 attribs_cmd
.va
, attribs_cmd
.dma
);
2909 int be_cmd_req_native_mode(struct be_adapter
*adapter
)
2911 struct be_mcc_wrb
*wrb
;
2912 struct be_cmd_req_set_func_cap
*req
;
2915 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
2918 wrb
= wrb_from_mbox(adapter
);
2924 req
= embedded_payload(wrb
);
2926 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2927 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP
,
2928 sizeof(*req
), wrb
, NULL
);
2930 req
->valid_cap_flags
= cpu_to_le32(CAPABILITY_SW_TIMESTAMPS
|
2931 CAPABILITY_BE3_NATIVE_ERX_API
);
2932 req
->cap_flags
= cpu_to_le32(CAPABILITY_BE3_NATIVE_ERX_API
);
2934 status
= be_mbox_notify_wait(adapter
);
2936 struct be_cmd_resp_set_func_cap
*resp
= embedded_payload(wrb
);
2938 adapter
->be3_native
= le32_to_cpu(resp
->cap_flags
) &
2939 CAPABILITY_BE3_NATIVE_ERX_API
;
2940 if (!adapter
->be3_native
)
2941 dev_warn(&adapter
->pdev
->dev
,
2942 "adapter not in advanced mode\n");
2945 mutex_unlock(&adapter
->mbox_lock
);
2949 /* Get privilege(s) for a function */
2950 int be_cmd_get_fn_privileges(struct be_adapter
*adapter
, u32
*privilege
,
2953 struct be_mcc_wrb
*wrb
;
2954 struct be_cmd_req_get_fn_privileges
*req
;
2957 spin_lock_bh(&adapter
->mcc_lock
);
2959 wrb
= wrb_from_mccq(adapter
);
2965 req
= embedded_payload(wrb
);
2967 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
2968 OPCODE_COMMON_GET_FN_PRIVILEGES
, sizeof(*req
),
2971 req
->hdr
.domain
= domain
;
2973 status
= be_mcc_notify_wait(adapter
);
2975 struct be_cmd_resp_get_fn_privileges
*resp
=
2976 embedded_payload(wrb
);
2978 *privilege
= le32_to_cpu(resp
->privilege_mask
);
2980 /* In UMC mode FW does not return right privileges.
2981 * Override with correct privilege equivalent to PF.
2983 if (BEx_chip(adapter
) && be_is_mc(adapter
) &&
2985 *privilege
= MAX_PRIVILEGES
;
2989 spin_unlock_bh(&adapter
->mcc_lock
);
2993 /* Set privilege(s) for a function */
2994 int be_cmd_set_fn_privileges(struct be_adapter
*adapter
, u32 privileges
,
2997 struct be_mcc_wrb
*wrb
;
2998 struct be_cmd_req_set_fn_privileges
*req
;
3001 spin_lock_bh(&adapter
->mcc_lock
);
3003 wrb
= wrb_from_mccq(adapter
);
3009 req
= embedded_payload(wrb
);
3010 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3011 OPCODE_COMMON_SET_FN_PRIVILEGES
, sizeof(*req
),
3013 req
->hdr
.domain
= domain
;
3014 if (lancer_chip(adapter
))
3015 req
->privileges_lancer
= cpu_to_le32(privileges
);
3017 req
->privileges
= cpu_to_le32(privileges
);
3019 status
= be_mcc_notify_wait(adapter
);
3021 spin_unlock_bh(&adapter
->mcc_lock
);
3025 /* pmac_id_valid: true => pmac_id is supplied and MAC address is requested.
3026 * pmac_id_valid: false => pmac_id or MAC address is requested.
3027 * If pmac_id is returned, pmac_id_valid is returned as true
3029 int be_cmd_get_mac_from_list(struct be_adapter
*adapter
, u8
*mac
,
3030 bool *pmac_id_valid
, u32
*pmac_id
, u32 if_handle
,
3033 struct be_mcc_wrb
*wrb
;
3034 struct be_cmd_req_get_mac_list
*req
;
3037 struct be_dma_mem get_mac_list_cmd
;
3040 memset(&get_mac_list_cmd
, 0, sizeof(struct be_dma_mem
));
3041 get_mac_list_cmd
.size
= sizeof(struct be_cmd_resp_get_mac_list
);
3042 get_mac_list_cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
,
3043 get_mac_list_cmd
.size
,
3044 &get_mac_list_cmd
.dma
,
3047 if (!get_mac_list_cmd
.va
) {
3048 dev_err(&adapter
->pdev
->dev
,
3049 "Memory allocation failure during GET_MAC_LIST\n");
3053 spin_lock_bh(&adapter
->mcc_lock
);
3055 wrb
= wrb_from_mccq(adapter
);
3061 req
= get_mac_list_cmd
.va
;
3063 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3064 OPCODE_COMMON_GET_MAC_LIST
,
3065 get_mac_list_cmd
.size
, wrb
, &get_mac_list_cmd
);
3066 req
->hdr
.domain
= domain
;
3067 req
->mac_type
= MAC_ADDRESS_TYPE_NETWORK
;
3068 if (*pmac_id_valid
) {
3069 req
->mac_id
= cpu_to_le32(*pmac_id
);
3070 req
->iface_id
= cpu_to_le16(if_handle
);
3071 req
->perm_override
= 0;
3073 req
->perm_override
= 1;
3076 status
= be_mcc_notify_wait(adapter
);
3078 struct be_cmd_resp_get_mac_list
*resp
=
3079 get_mac_list_cmd
.va
;
3081 if (*pmac_id_valid
) {
3082 memcpy(mac
, resp
->macid_macaddr
.mac_addr_id
.macaddr
,
3087 mac_count
= resp
->true_mac_count
+ resp
->pseudo_mac_count
;
3088 /* Mac list returned could contain one or more active mac_ids
3089 * or one or more true or pseudo permanent mac addresses.
3090 * If an active mac_id is present, return first active mac_id
3093 for (i
= 0; i
< mac_count
; i
++) {
3094 struct get_list_macaddr
*mac_entry
;
3098 mac_entry
= &resp
->macaddr_list
[i
];
3099 mac_addr_size
= le16_to_cpu(mac_entry
->mac_addr_size
);
3100 /* mac_id is a 32 bit value and mac_addr size
3103 if (mac_addr_size
== sizeof(u32
)) {
3104 *pmac_id_valid
= true;
3105 mac_id
= mac_entry
->mac_addr_id
.s_mac_id
.mac_id
;
3106 *pmac_id
= le32_to_cpu(mac_id
);
3110 /* If no active mac_id found, return first mac addr */
3111 *pmac_id_valid
= false;
3112 memcpy(mac
, resp
->macaddr_list
[0].mac_addr_id
.macaddr
,
3117 spin_unlock_bh(&adapter
->mcc_lock
);
3118 dma_free_coherent(&adapter
->pdev
->dev
, get_mac_list_cmd
.size
,
3119 get_mac_list_cmd
.va
, get_mac_list_cmd
.dma
);
3123 int be_cmd_get_active_mac(struct be_adapter
*adapter
, u32 curr_pmac_id
,
3124 u8
*mac
, u32 if_handle
, bool active
, u32 domain
)
3127 be_cmd_get_mac_from_list(adapter
, mac
, &active
, &curr_pmac_id
,
3129 if (BEx_chip(adapter
))
3130 return be_cmd_mac_addr_query(adapter
, mac
, false,
3131 if_handle
, curr_pmac_id
);
3133 /* Fetch the MAC address using pmac_id */
3134 return be_cmd_get_mac_from_list(adapter
, mac
, &active
,
3139 int be_cmd_get_perm_mac(struct be_adapter
*adapter
, u8
*mac
)
3142 bool pmac_valid
= false;
3146 if (BEx_chip(adapter
)) {
3147 if (be_physfn(adapter
))
3148 status
= be_cmd_mac_addr_query(adapter
, mac
, true, 0,
3151 status
= be_cmd_mac_addr_query(adapter
, mac
, false,
3152 adapter
->if_handle
, 0);
3154 status
= be_cmd_get_mac_from_list(adapter
, mac
, &pmac_valid
,
3155 NULL
, adapter
->if_handle
, 0);
3161 /* Uses synchronous MCCQ */
3162 int be_cmd_set_mac_list(struct be_adapter
*adapter
, u8
*mac_array
,
3163 u8 mac_count
, u32 domain
)
3165 struct be_mcc_wrb
*wrb
;
3166 struct be_cmd_req_set_mac_list
*req
;
3168 struct be_dma_mem cmd
;
3170 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3171 cmd
.size
= sizeof(struct be_cmd_req_set_mac_list
);
3172 cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
, cmd
.size
, &cmd
.dma
,
3177 spin_lock_bh(&adapter
->mcc_lock
);
3179 wrb
= wrb_from_mccq(adapter
);
3186 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3187 OPCODE_COMMON_SET_MAC_LIST
, sizeof(*req
),
3190 req
->hdr
.domain
= domain
;
3191 req
->mac_count
= mac_count
;
3193 memcpy(req
->mac
, mac_array
, ETH_ALEN
*mac_count
);
3195 status
= be_mcc_notify_wait(adapter
);
3198 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
, cmd
.va
, cmd
.dma
);
3199 spin_unlock_bh(&adapter
->mcc_lock
);
3203 /* Wrapper to delete any active MACs and provision the new mac.
3204 * Changes to MAC_LIST are allowed iff none of the MAC addresses in the
3205 * current list are active.
3207 int be_cmd_set_mac(struct be_adapter
*adapter
, u8
*mac
, int if_id
, u32 dom
)
3209 bool active_mac
= false;
3210 u8 old_mac
[ETH_ALEN
];
3214 status
= be_cmd_get_mac_from_list(adapter
, old_mac
, &active_mac
,
3215 &pmac_id
, if_id
, dom
);
3217 if (!status
&& active_mac
)
3218 be_cmd_pmac_del(adapter
, if_id
, pmac_id
, dom
);
3220 return be_cmd_set_mac_list(adapter
, mac
, mac
? 1 : 0, dom
);
3223 int be_cmd_set_hsw_config(struct be_adapter
*adapter
, u16 pvid
,
3224 u32 domain
, u16 intf_id
, u16 hsw_mode
, u8 spoofchk
)
3226 struct be_mcc_wrb
*wrb
;
3227 struct be_cmd_req_set_hsw_config
*req
;
3231 spin_lock_bh(&adapter
->mcc_lock
);
3233 wrb
= wrb_from_mccq(adapter
);
3239 req
= embedded_payload(wrb
);
3240 ctxt
= &req
->context
;
3242 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3243 OPCODE_COMMON_SET_HSW_CONFIG
, sizeof(*req
), wrb
,
3246 req
->hdr
.domain
= domain
;
3247 AMAP_SET_BITS(struct amap_set_hsw_context
, interface_id
, ctxt
, intf_id
);
3249 AMAP_SET_BITS(struct amap_set_hsw_context
, pvid_valid
, ctxt
, 1);
3250 AMAP_SET_BITS(struct amap_set_hsw_context
, pvid
, ctxt
, pvid
);
3252 if (!BEx_chip(adapter
) && hsw_mode
) {
3253 AMAP_SET_BITS(struct amap_set_hsw_context
, interface_id
,
3254 ctxt
, adapter
->hba_port_num
);
3255 AMAP_SET_BITS(struct amap_set_hsw_context
, pport
, ctxt
, 1);
3256 AMAP_SET_BITS(struct amap_set_hsw_context
, port_fwd_type
,
3260 /* Enable/disable both mac and vlan spoof checking */
3261 if (!BEx_chip(adapter
) && spoofchk
) {
3262 AMAP_SET_BITS(struct amap_set_hsw_context
, mac_spoofchk
,
3264 AMAP_SET_BITS(struct amap_set_hsw_context
, vlan_spoofchk
,
3268 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
3269 status
= be_mcc_notify_wait(adapter
);
3272 spin_unlock_bh(&adapter
->mcc_lock
);
3276 /* Get Hyper switch config */
3277 int be_cmd_get_hsw_config(struct be_adapter
*adapter
, u16
*pvid
,
3278 u32 domain
, u16 intf_id
, u8
*mode
, bool *spoofchk
)
3280 struct be_mcc_wrb
*wrb
;
3281 struct be_cmd_req_get_hsw_config
*req
;
3286 spin_lock_bh(&adapter
->mcc_lock
);
3288 wrb
= wrb_from_mccq(adapter
);
3294 req
= embedded_payload(wrb
);
3295 ctxt
= &req
->context
;
3297 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3298 OPCODE_COMMON_GET_HSW_CONFIG
, sizeof(*req
), wrb
,
3301 req
->hdr
.domain
= domain
;
3302 AMAP_SET_BITS(struct amap_get_hsw_req_context
, interface_id
,
3304 AMAP_SET_BITS(struct amap_get_hsw_req_context
, pvid_valid
, ctxt
, 1);
3306 if (!BEx_chip(adapter
) && mode
) {
3307 AMAP_SET_BITS(struct amap_get_hsw_req_context
, interface_id
,
3308 ctxt
, adapter
->hba_port_num
);
3309 AMAP_SET_BITS(struct amap_get_hsw_req_context
, pport
, ctxt
, 1);
3311 be_dws_cpu_to_le(req
->context
, sizeof(req
->context
));
3313 status
= be_mcc_notify_wait(adapter
);
3315 struct be_cmd_resp_get_hsw_config
*resp
=
3316 embedded_payload(wrb
);
3318 be_dws_le_to_cpu(&resp
->context
, sizeof(resp
->context
));
3319 vid
= AMAP_GET_BITS(struct amap_get_hsw_resp_context
,
3320 pvid
, &resp
->context
);
3322 *pvid
= le16_to_cpu(vid
);
3324 *mode
= AMAP_GET_BITS(struct amap_get_hsw_resp_context
,
3325 port_fwd_type
, &resp
->context
);
3328 AMAP_GET_BITS(struct amap_get_hsw_resp_context
,
3329 spoofchk
, &resp
->context
);
3333 spin_unlock_bh(&adapter
->mcc_lock
);
3337 static bool be_is_wol_excluded(struct be_adapter
*adapter
)
3339 struct pci_dev
*pdev
= adapter
->pdev
;
3341 if (be_virtfn(adapter
))
3344 switch (pdev
->subsystem_device
) {
3345 case OC_SUBSYS_DEVICE_ID1
:
3346 case OC_SUBSYS_DEVICE_ID2
:
3347 case OC_SUBSYS_DEVICE_ID3
:
3348 case OC_SUBSYS_DEVICE_ID4
:
3355 int be_cmd_get_acpi_wol_cap(struct be_adapter
*adapter
)
3357 struct be_mcc_wrb
*wrb
;
3358 struct be_cmd_req_acpi_wol_magic_config_v1
*req
;
3360 struct be_dma_mem cmd
;
3362 if (!be_cmd_allowed(adapter
, OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
3366 if (be_is_wol_excluded(adapter
))
3369 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3372 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3373 cmd
.size
= sizeof(struct be_cmd_resp_acpi_wol_magic_config_v1
);
3374 cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
, cmd
.size
, &cmd
.dma
,
3377 dev_err(&adapter
->pdev
->dev
, "Memory allocation failure\n");
3382 wrb
= wrb_from_mbox(adapter
);
3390 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_ETH
,
3391 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG
,
3392 sizeof(*req
), wrb
, &cmd
);
3394 req
->hdr
.version
= 1;
3395 req
->query_options
= BE_GET_WOL_CAP
;
3397 status
= be_mbox_notify_wait(adapter
);
3399 struct be_cmd_resp_acpi_wol_magic_config_v1
*resp
;
3401 resp
= (struct be_cmd_resp_acpi_wol_magic_config_v1
*)cmd
.va
;
3403 adapter
->wol_cap
= resp
->wol_settings
;
3404 if (adapter
->wol_cap
& BE_WOL_CAP
)
3405 adapter
->wol_en
= true;
3408 mutex_unlock(&adapter
->mbox_lock
);
3410 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
, cmd
.va
,
3416 int be_cmd_set_fw_log_level(struct be_adapter
*adapter
, u32 level
)
3418 struct be_dma_mem extfat_cmd
;
3419 struct be_fat_conf_params
*cfgs
;
3423 memset(&extfat_cmd
, 0, sizeof(struct be_dma_mem
));
3424 extfat_cmd
.size
= sizeof(struct be_cmd_resp_get_ext_fat_caps
);
3425 extfat_cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
,
3426 extfat_cmd
.size
, &extfat_cmd
.dma
,
3431 status
= be_cmd_get_ext_fat_capabilites(adapter
, &extfat_cmd
);
3435 cfgs
= (struct be_fat_conf_params
*)
3436 (extfat_cmd
.va
+ sizeof(struct be_cmd_resp_hdr
));
3437 for (i
= 0; i
< le32_to_cpu(cfgs
->num_modules
); i
++) {
3438 u32 num_modes
= le32_to_cpu(cfgs
->module
[i
].num_modes
);
3440 for (j
= 0; j
< num_modes
; j
++) {
3441 if (cfgs
->module
[i
].trace_lvl
[j
].mode
== MODE_UART
)
3442 cfgs
->module
[i
].trace_lvl
[j
].dbg_lvl
=
3447 status
= be_cmd_set_ext_fat_capabilites(adapter
, &extfat_cmd
, cfgs
);
3449 dma_free_coherent(&adapter
->pdev
->dev
, extfat_cmd
.size
, extfat_cmd
.va
,
3454 int be_cmd_get_fw_log_level(struct be_adapter
*adapter
)
3456 struct be_dma_mem extfat_cmd
;
3457 struct be_fat_conf_params
*cfgs
;
3461 memset(&extfat_cmd
, 0, sizeof(struct be_dma_mem
));
3462 extfat_cmd
.size
= sizeof(struct be_cmd_resp_get_ext_fat_caps
);
3463 extfat_cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
,
3464 extfat_cmd
.size
, &extfat_cmd
.dma
,
3467 if (!extfat_cmd
.va
) {
3468 dev_err(&adapter
->pdev
->dev
, "%s: Memory allocation failure\n",
3473 status
= be_cmd_get_ext_fat_capabilites(adapter
, &extfat_cmd
);
3475 cfgs
= (struct be_fat_conf_params
*)(extfat_cmd
.va
+
3476 sizeof(struct be_cmd_resp_hdr
));
3478 for (j
= 0; j
< le32_to_cpu(cfgs
->module
[0].num_modes
); j
++) {
3479 if (cfgs
->module
[0].trace_lvl
[j
].mode
== MODE_UART
)
3480 level
= cfgs
->module
[0].trace_lvl
[j
].dbg_lvl
;
3483 dma_free_coherent(&adapter
->pdev
->dev
, extfat_cmd
.size
, extfat_cmd
.va
,
3489 int be_cmd_get_ext_fat_capabilites(struct be_adapter
*adapter
,
3490 struct be_dma_mem
*cmd
)
3492 struct be_mcc_wrb
*wrb
;
3493 struct be_cmd_req_get_ext_fat_caps
*req
;
3496 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3499 wrb
= wrb_from_mbox(adapter
);
3506 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3507 OPCODE_COMMON_GET_EXT_FAT_CAPABILITES
,
3508 cmd
->size
, wrb
, cmd
);
3509 req
->parameter_type
= cpu_to_le32(1);
3511 status
= be_mbox_notify_wait(adapter
);
3513 mutex_unlock(&adapter
->mbox_lock
);
3517 int be_cmd_set_ext_fat_capabilites(struct be_adapter
*adapter
,
3518 struct be_dma_mem
*cmd
,
3519 struct be_fat_conf_params
*configs
)
3521 struct be_mcc_wrb
*wrb
;
3522 struct be_cmd_req_set_ext_fat_caps
*req
;
3525 spin_lock_bh(&adapter
->mcc_lock
);
3527 wrb
= wrb_from_mccq(adapter
);
3534 memcpy(&req
->set_params
, configs
, sizeof(struct be_fat_conf_params
));
3535 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3536 OPCODE_COMMON_SET_EXT_FAT_CAPABILITES
,
3537 cmd
->size
, wrb
, cmd
);
3539 status
= be_mcc_notify_wait(adapter
);
3541 spin_unlock_bh(&adapter
->mcc_lock
);
3545 int be_cmd_query_port_name(struct be_adapter
*adapter
)
3547 struct be_cmd_req_get_port_name
*req
;
3548 struct be_mcc_wrb
*wrb
;
3551 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3554 wrb
= wrb_from_mbox(adapter
);
3555 req
= embedded_payload(wrb
);
3557 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3558 OPCODE_COMMON_GET_PORT_NAME
, sizeof(*req
), wrb
,
3560 if (!BEx_chip(adapter
))
3561 req
->hdr
.version
= 1;
3563 status
= be_mbox_notify_wait(adapter
);
3565 struct be_cmd_resp_get_port_name
*resp
= embedded_payload(wrb
);
3567 adapter
->port_name
= resp
->port_name
[adapter
->hba_port_num
];
3569 adapter
->port_name
= adapter
->hba_port_num
+ '0';
3572 mutex_unlock(&adapter
->mbox_lock
);
3576 /* Descriptor type */
3582 static struct be_nic_res_desc
*be_get_nic_desc(u8
*buf
, u32 desc_count
,
3585 struct be_res_desc_hdr
*hdr
= (struct be_res_desc_hdr
*)buf
;
3586 struct be_nic_res_desc
*nic
;
3589 for (i
= 0; i
< desc_count
; i
++) {
3590 if (hdr
->desc_type
== NIC_RESOURCE_DESC_TYPE_V0
||
3591 hdr
->desc_type
== NIC_RESOURCE_DESC_TYPE_V1
) {
3592 nic
= (struct be_nic_res_desc
*)hdr
;
3593 if (desc_type
== FUNC_DESC
||
3594 (desc_type
== VFT_DESC
&&
3595 nic
->flags
& (1 << VFT_SHIFT
)))
3599 hdr
->desc_len
= hdr
->desc_len
? : RESOURCE_DESC_SIZE_V0
;
3600 hdr
= (void *)hdr
+ hdr
->desc_len
;
3605 static struct be_nic_res_desc
*be_get_vft_desc(u8
*buf
, u32 desc_count
)
3607 return be_get_nic_desc(buf
, desc_count
, VFT_DESC
);
3610 static struct be_nic_res_desc
*be_get_func_nic_desc(u8
*buf
, u32 desc_count
)
3612 return be_get_nic_desc(buf
, desc_count
, FUNC_DESC
);
3615 static struct be_pcie_res_desc
*be_get_pcie_desc(u8 devfn
, u8
*buf
,
3618 struct be_res_desc_hdr
*hdr
= (struct be_res_desc_hdr
*)buf
;
3619 struct be_pcie_res_desc
*pcie
;
3622 for (i
= 0; i
< desc_count
; i
++) {
3623 if ((hdr
->desc_type
== PCIE_RESOURCE_DESC_TYPE_V0
||
3624 hdr
->desc_type
== PCIE_RESOURCE_DESC_TYPE_V1
)) {
3625 pcie
= (struct be_pcie_res_desc
*)hdr
;
3626 if (pcie
->pf_num
== devfn
)
3630 hdr
->desc_len
= hdr
->desc_len
? : RESOURCE_DESC_SIZE_V0
;
3631 hdr
= (void *)hdr
+ hdr
->desc_len
;
3636 static struct be_port_res_desc
*be_get_port_desc(u8
*buf
, u32 desc_count
)
3638 struct be_res_desc_hdr
*hdr
= (struct be_res_desc_hdr
*)buf
;
3641 for (i
= 0; i
< desc_count
; i
++) {
3642 if (hdr
->desc_type
== PORT_RESOURCE_DESC_TYPE_V1
)
3643 return (struct be_port_res_desc
*)hdr
;
3645 hdr
->desc_len
= hdr
->desc_len
? : RESOURCE_DESC_SIZE_V0
;
3646 hdr
= (void *)hdr
+ hdr
->desc_len
;
3651 static void be_copy_nic_desc(struct be_resources
*res
,
3652 struct be_nic_res_desc
*desc
)
3654 res
->max_uc_mac
= le16_to_cpu(desc
->unicast_mac_count
);
3655 res
->max_vlans
= le16_to_cpu(desc
->vlan_count
);
3656 res
->max_mcast_mac
= le16_to_cpu(desc
->mcast_mac_count
);
3657 res
->max_tx_qs
= le16_to_cpu(desc
->txq_count
);
3658 res
->max_rss_qs
= le16_to_cpu(desc
->rssq_count
);
3659 res
->max_rx_qs
= le16_to_cpu(desc
->rq_count
);
3660 res
->max_evt_qs
= le16_to_cpu(desc
->eq_count
);
3661 res
->max_cq_count
= le16_to_cpu(desc
->cq_count
);
3662 res
->max_iface_count
= le16_to_cpu(desc
->iface_count
);
3663 res
->max_mcc_count
= le16_to_cpu(desc
->mcc_count
);
3664 /* Clear flags that driver is not interested in */
3665 res
->if_cap_flags
= le32_to_cpu(desc
->cap_flags
) &
3666 BE_IF_CAP_FLAGS_WANT
;
3670 int be_cmd_get_func_config(struct be_adapter
*adapter
, struct be_resources
*res
)
3672 struct be_mcc_wrb
*wrb
;
3673 struct be_cmd_req_get_func_config
*req
;
3675 struct be_dma_mem cmd
;
3677 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
3680 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3681 cmd
.size
= sizeof(struct be_cmd_resp_get_func_config
);
3682 cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
, cmd
.size
, &cmd
.dma
,
3685 dev_err(&adapter
->pdev
->dev
, "Memory alloc failure\n");
3690 wrb
= wrb_from_mbox(adapter
);
3698 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3699 OPCODE_COMMON_GET_FUNC_CONFIG
,
3700 cmd
.size
, wrb
, &cmd
);
3702 if (skyhawk_chip(adapter
))
3703 req
->hdr
.version
= 1;
3705 status
= be_mbox_notify_wait(adapter
);
3707 struct be_cmd_resp_get_func_config
*resp
= cmd
.va
;
3708 u32 desc_count
= le32_to_cpu(resp
->desc_count
);
3709 struct be_nic_res_desc
*desc
;
3711 desc
= be_get_func_nic_desc(resp
->func_param
, desc_count
);
3716 adapter
->pf_number
= desc
->pf_num
;
3717 be_copy_nic_desc(res
, desc
);
3720 mutex_unlock(&adapter
->mbox_lock
);
3722 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
, cmd
.va
,
3727 /* Will use MBOX only if MCCQ has not been created
3728 * non-zero domain => a PF is querying this on behalf of a VF
3729 * zero domain => a PF or a VF is querying this for itself
3731 int be_cmd_get_profile_config(struct be_adapter
*adapter
,
3732 struct be_resources
*res
, u8 query
, u8 domain
)
3734 struct be_cmd_resp_get_profile_config
*resp
;
3735 struct be_cmd_req_get_profile_config
*req
;
3736 struct be_nic_res_desc
*vf_res
;
3737 struct be_pcie_res_desc
*pcie
;
3738 struct be_port_res_desc
*port
;
3739 struct be_nic_res_desc
*nic
;
3740 struct be_mcc_wrb wrb
= {0};
3741 struct be_dma_mem cmd
;
3745 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3746 cmd
.size
= sizeof(struct be_cmd_resp_get_profile_config
);
3747 cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
, cmd
.size
, &cmd
.dma
,
3753 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3754 OPCODE_COMMON_GET_PROFILE_CONFIG
,
3755 cmd
.size
, &wrb
, &cmd
);
3757 if (!lancer_chip(adapter
))
3758 req
->hdr
.version
= 1;
3759 req
->type
= ACTIVE_PROFILE_TYPE
;
3760 /* When a function is querying profile information relating to
3761 * itself hdr.pf_number must be set to it's pci_func_num + 1
3763 req
->hdr
.domain
= domain
;
3765 req
->hdr
.pf_num
= adapter
->pci_func_num
+ 1;
3767 /* When QUERY_MODIFIABLE_FIELDS_TYPE bit is set, cmd returns the
3768 * descriptors with all bits set to "1" for the fields which can be
3769 * modified using SET_PROFILE_CONFIG cmd.
3771 if (query
== RESOURCE_MODIFIABLE
)
3772 req
->type
|= QUERY_MODIFIABLE_FIELDS_TYPE
;
3774 status
= be_cmd_notify_wait(adapter
, &wrb
);
3779 desc_count
= le16_to_cpu(resp
->desc_count
);
3781 pcie
= be_get_pcie_desc(adapter
->pdev
->devfn
, resp
->func_param
,
3784 res
->max_vfs
= le16_to_cpu(pcie
->num_vfs
);
3786 port
= be_get_port_desc(resp
->func_param
, desc_count
);
3788 adapter
->mc_type
= port
->mc_type
;
3790 nic
= be_get_func_nic_desc(resp
->func_param
, desc_count
);
3792 be_copy_nic_desc(res
, nic
);
3794 vf_res
= be_get_vft_desc(resp
->func_param
, desc_count
);
3796 res
->vf_if_cap_flags
= vf_res
->cap_flags
;
3799 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
, cmd
.va
,
3804 /* Will use MBOX only if MCCQ has not been created */
3805 static int be_cmd_set_profile_config(struct be_adapter
*adapter
, void *desc
,
3806 int size
, int count
, u8 version
, u8 domain
)
3808 struct be_cmd_req_set_profile_config
*req
;
3809 struct be_mcc_wrb wrb
= {0};
3810 struct be_dma_mem cmd
;
3813 memset(&cmd
, 0, sizeof(struct be_dma_mem
));
3814 cmd
.size
= sizeof(struct be_cmd_req_set_profile_config
);
3815 cmd
.va
= dma_zalloc_coherent(&adapter
->pdev
->dev
, cmd
.size
, &cmd
.dma
,
3821 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
3822 OPCODE_COMMON_SET_PROFILE_CONFIG
, cmd
.size
,
3824 req
->hdr
.version
= version
;
3825 req
->hdr
.domain
= domain
;
3826 req
->desc_count
= cpu_to_le32(count
);
3827 memcpy(req
->desc
, desc
, size
);
3829 status
= be_cmd_notify_wait(adapter
, &wrb
);
3832 dma_free_coherent(&adapter
->pdev
->dev
, cmd
.size
, cmd
.va
,
3837 /* Mark all fields invalid */
3838 static void be_reset_nic_desc(struct be_nic_res_desc
*nic
)
3840 memset(nic
, 0, sizeof(*nic
));
3841 nic
->unicast_mac_count
= 0xFFFF;
3842 nic
->mcc_count
= 0xFFFF;
3843 nic
->vlan_count
= 0xFFFF;
3844 nic
->mcast_mac_count
= 0xFFFF;
3845 nic
->txq_count
= 0xFFFF;
3846 nic
->rq_count
= 0xFFFF;
3847 nic
->rssq_count
= 0xFFFF;
3848 nic
->lro_count
= 0xFFFF;
3849 nic
->cq_count
= 0xFFFF;
3850 nic
->toe_conn_count
= 0xFFFF;
3851 nic
->eq_count
= 0xFFFF;
3852 nic
->iface_count
= 0xFFFF;
3853 nic
->link_param
= 0xFF;
3854 nic
->channel_id_param
= cpu_to_le16(0xF000);
3855 nic
->acpi_params
= 0xFF;
3856 nic
->wol_param
= 0x0F;
3857 nic
->tunnel_iface_count
= 0xFFFF;
3858 nic
->direct_tenant_iface_count
= 0xFFFF;
3859 nic
->bw_min
= 0xFFFFFFFF;
3860 nic
->bw_max
= 0xFFFFFFFF;
3863 /* Mark all fields invalid */
3864 static void be_reset_pcie_desc(struct be_pcie_res_desc
*pcie
)
3866 memset(pcie
, 0, sizeof(*pcie
));
3867 pcie
->sriov_state
= 0xFF;
3868 pcie
->pf_state
= 0xFF;
3869 pcie
->pf_type
= 0xFF;
3870 pcie
->num_vfs
= 0xFFFF;
3873 int be_cmd_config_qos(struct be_adapter
*adapter
, u32 max_rate
, u16 link_speed
,
3876 struct be_nic_res_desc nic_desc
;
3880 if (BE3_chip(adapter
))
3881 return be_cmd_set_qos(adapter
, max_rate
/ 10, domain
);
3883 be_reset_nic_desc(&nic_desc
);
3884 nic_desc
.pf_num
= adapter
->pf_number
;
3885 nic_desc
.vf_num
= domain
;
3886 nic_desc
.bw_min
= 0;
3887 if (lancer_chip(adapter
)) {
3888 nic_desc
.hdr
.desc_type
= NIC_RESOURCE_DESC_TYPE_V0
;
3889 nic_desc
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V0
;
3890 nic_desc
.flags
= (1 << QUN_SHIFT
) | (1 << IMM_SHIFT
) |
3892 nic_desc
.bw_max
= cpu_to_le32(max_rate
/ 10);
3895 nic_desc
.hdr
.desc_type
= NIC_RESOURCE_DESC_TYPE_V1
;
3896 nic_desc
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V1
;
3897 nic_desc
.flags
= (1 << IMM_SHIFT
) | (1 << NOSV_SHIFT
);
3898 bw_percent
= max_rate
? (max_rate
* 100) / link_speed
: 100;
3899 nic_desc
.bw_max
= cpu_to_le32(bw_percent
);
3902 return be_cmd_set_profile_config(adapter
, &nic_desc
,
3903 nic_desc
.hdr
.desc_len
,
3904 1, version
, domain
);
3907 static void be_fill_vf_res_template(struct be_adapter
*adapter
,
3908 struct be_resources pool_res
,
3909 u16 num_vfs
, u16 num_vf_qs
,
3910 struct be_nic_res_desc
*nic_vft
)
3912 u32 vf_if_cap_flags
= pool_res
.vf_if_cap_flags
;
3913 struct be_resources res_mod
= {0};
3915 /* Resource with fields set to all '1's by GET_PROFILE_CONFIG cmd,
3916 * which are modifiable using SET_PROFILE_CONFIG cmd.
3918 be_cmd_get_profile_config(adapter
, &res_mod
, RESOURCE_MODIFIABLE
, 0);
3920 /* If RSS IFACE capability flags are modifiable for a VF, set the
3921 * capability flag as valid and set RSS and DEFQ_RSS IFACE flags if
3922 * more than 1 RSSQ is available for a VF.
3923 * Otherwise, provision only 1 queue pair for VF.
3925 if (res_mod
.vf_if_cap_flags
& BE_IF_FLAGS_RSS
) {
3926 nic_vft
->flags
|= BIT(IF_CAPS_FLAGS_VALID_SHIFT
);
3927 if (num_vf_qs
> 1) {
3928 vf_if_cap_flags
|= BE_IF_FLAGS_RSS
;
3929 if (pool_res
.if_cap_flags
& BE_IF_FLAGS_DEFQ_RSS
)
3930 vf_if_cap_flags
|= BE_IF_FLAGS_DEFQ_RSS
;
3932 vf_if_cap_flags
&= ~(BE_IF_FLAGS_RSS
|
3933 BE_IF_FLAGS_DEFQ_RSS
);
3936 nic_vft
->cap_flags
= cpu_to_le32(vf_if_cap_flags
);
3941 nic_vft
->rq_count
= cpu_to_le16(num_vf_qs
);
3942 nic_vft
->txq_count
= cpu_to_le16(num_vf_qs
);
3943 nic_vft
->rssq_count
= cpu_to_le16(num_vf_qs
);
3944 nic_vft
->cq_count
= cpu_to_le16(pool_res
.max_cq_count
/
3947 /* Distribute unicast MACs, VLANs, IFACE count and MCCQ count equally
3948 * among the PF and it's VFs, if the fields are changeable
3950 if (res_mod
.max_uc_mac
== FIELD_MODIFIABLE
)
3951 nic_vft
->unicast_mac_count
= cpu_to_le16(pool_res
.max_uc_mac
/
3954 if (res_mod
.max_vlans
== FIELD_MODIFIABLE
)
3955 nic_vft
->vlan_count
= cpu_to_le16(pool_res
.max_vlans
/
3958 if (res_mod
.max_iface_count
== FIELD_MODIFIABLE
)
3959 nic_vft
->iface_count
= cpu_to_le16(pool_res
.max_iface_count
/
3962 if (res_mod
.max_mcc_count
== FIELD_MODIFIABLE
)
3963 nic_vft
->mcc_count
= cpu_to_le16(pool_res
.max_mcc_count
/
3967 int be_cmd_set_sriov_config(struct be_adapter
*adapter
,
3968 struct be_resources pool_res
, u16 num_vfs
,
3972 struct be_pcie_res_desc pcie
;
3973 struct be_nic_res_desc nic_vft
;
3976 /* PF PCIE descriptor */
3977 be_reset_pcie_desc(&desc
.pcie
);
3978 desc
.pcie
.hdr
.desc_type
= PCIE_RESOURCE_DESC_TYPE_V1
;
3979 desc
.pcie
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V1
;
3980 desc
.pcie
.flags
= BIT(IMM_SHIFT
) | BIT(NOSV_SHIFT
);
3981 desc
.pcie
.pf_num
= adapter
->pdev
->devfn
;
3982 desc
.pcie
.sriov_state
= num_vfs
? 1 : 0;
3983 desc
.pcie
.num_vfs
= cpu_to_le16(num_vfs
);
3985 /* VF NIC Template descriptor */
3986 be_reset_nic_desc(&desc
.nic_vft
);
3987 desc
.nic_vft
.hdr
.desc_type
= NIC_RESOURCE_DESC_TYPE_V1
;
3988 desc
.nic_vft
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V1
;
3989 desc
.nic_vft
.flags
= BIT(VFT_SHIFT
) | BIT(IMM_SHIFT
) | BIT(NOSV_SHIFT
);
3990 desc
.nic_vft
.pf_num
= adapter
->pdev
->devfn
;
3991 desc
.nic_vft
.vf_num
= 0;
3993 be_fill_vf_res_template(adapter
, pool_res
, num_vfs
, num_vf_qs
,
3996 return be_cmd_set_profile_config(adapter
, &desc
,
3997 2 * RESOURCE_DESC_SIZE_V1
, 2, 1, 0);
4000 int be_cmd_manage_iface(struct be_adapter
*adapter
, u32 iface
, u8 op
)
4002 struct be_mcc_wrb
*wrb
;
4003 struct be_cmd_req_manage_iface_filters
*req
;
4006 if (iface
== 0xFFFFFFFF)
4009 spin_lock_bh(&adapter
->mcc_lock
);
4011 wrb
= wrb_from_mccq(adapter
);
4016 req
= embedded_payload(wrb
);
4018 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4019 OPCODE_COMMON_MANAGE_IFACE_FILTERS
, sizeof(*req
),
4022 req
->target_iface_id
= cpu_to_le32(iface
);
4024 status
= be_mcc_notify_wait(adapter
);
4026 spin_unlock_bh(&adapter
->mcc_lock
);
4030 int be_cmd_set_vxlan_port(struct be_adapter
*adapter
, __be16 port
)
4032 struct be_port_res_desc port_desc
;
4034 memset(&port_desc
, 0, sizeof(port_desc
));
4035 port_desc
.hdr
.desc_type
= PORT_RESOURCE_DESC_TYPE_V1
;
4036 port_desc
.hdr
.desc_len
= RESOURCE_DESC_SIZE_V1
;
4037 port_desc
.flags
= (1 << IMM_SHIFT
) | (1 << NOSV_SHIFT
);
4038 port_desc
.link_num
= adapter
->hba_port_num
;
4040 port_desc
.nv_flags
= NV_TYPE_VXLAN
| (1 << SOCVID_SHIFT
) |
4042 port_desc
.nv_port
= swab16(port
);
4044 port_desc
.nv_flags
= NV_TYPE_DISABLED
;
4045 port_desc
.nv_port
= 0;
4048 return be_cmd_set_profile_config(adapter
, &port_desc
,
4049 RESOURCE_DESC_SIZE_V1
, 1, 1, 0);
4052 int be_cmd_get_if_id(struct be_adapter
*adapter
, struct be_vf_cfg
*vf_cfg
,
4055 struct be_mcc_wrb
*wrb
;
4056 struct be_cmd_req_get_iface_list
*req
;
4057 struct be_cmd_resp_get_iface_list
*resp
;
4060 spin_lock_bh(&adapter
->mcc_lock
);
4062 wrb
= wrb_from_mccq(adapter
);
4067 req
= embedded_payload(wrb
);
4069 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4070 OPCODE_COMMON_GET_IFACE_LIST
, sizeof(*resp
),
4072 req
->hdr
.domain
= vf_num
+ 1;
4074 status
= be_mcc_notify_wait(adapter
);
4076 resp
= (struct be_cmd_resp_get_iface_list
*)req
;
4077 vf_cfg
->if_handle
= le32_to_cpu(resp
->if_desc
.if_id
);
4081 spin_unlock_bh(&adapter
->mcc_lock
);
4085 static int lancer_wait_idle(struct be_adapter
*adapter
)
4087 #define SLIPORT_IDLE_TIMEOUT 30
4091 for (i
= 0; i
< SLIPORT_IDLE_TIMEOUT
; i
++) {
4092 reg_val
= ioread32(adapter
->db
+ PHYSDEV_CONTROL_OFFSET
);
4093 if ((reg_val
& PHYSDEV_CONTROL_INP_MASK
) == 0)
4099 if (i
== SLIPORT_IDLE_TIMEOUT
)
4105 int lancer_physdev_ctrl(struct be_adapter
*adapter
, u32 mask
)
4109 status
= lancer_wait_idle(adapter
);
4113 iowrite32(mask
, adapter
->db
+ PHYSDEV_CONTROL_OFFSET
);
4118 /* Routine to check whether dump image is present or not */
4119 bool dump_present(struct be_adapter
*adapter
)
4121 u32 sliport_status
= 0;
4123 sliport_status
= ioread32(adapter
->db
+ SLIPORT_STATUS_OFFSET
);
4124 return !!(sliport_status
& SLIPORT_STATUS_DIP_MASK
);
4127 int lancer_initiate_dump(struct be_adapter
*adapter
)
4129 struct device
*dev
= &adapter
->pdev
->dev
;
4132 if (dump_present(adapter
)) {
4133 dev_info(dev
, "Previous dump not cleared, not forcing dump\n");
4137 /* give firmware reset and diagnostic dump */
4138 status
= lancer_physdev_ctrl(adapter
, PHYSDEV_CONTROL_FW_RESET_MASK
|
4139 PHYSDEV_CONTROL_DD_MASK
);
4141 dev_err(dev
, "FW reset failed\n");
4145 status
= lancer_wait_idle(adapter
);
4149 if (!dump_present(adapter
)) {
4150 dev_err(dev
, "FW dump not generated\n");
4157 int lancer_delete_dump(struct be_adapter
*adapter
)
4161 status
= lancer_cmd_delete_object(adapter
, LANCER_FW_DUMP_FILE
);
4162 return be_cmd_status(status
);
4166 int be_cmd_enable_vf(struct be_adapter
*adapter
, u8 domain
)
4168 struct be_mcc_wrb
*wrb
;
4169 struct be_cmd_enable_disable_vf
*req
;
4172 if (BEx_chip(adapter
))
4175 spin_lock_bh(&adapter
->mcc_lock
);
4177 wrb
= wrb_from_mccq(adapter
);
4183 req
= embedded_payload(wrb
);
4185 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4186 OPCODE_COMMON_ENABLE_DISABLE_VF
, sizeof(*req
),
4189 req
->hdr
.domain
= domain
;
4191 status
= be_mcc_notify_wait(adapter
);
4193 spin_unlock_bh(&adapter
->mcc_lock
);
4197 int be_cmd_intr_set(struct be_adapter
*adapter
, bool intr_enable
)
4199 struct be_mcc_wrb
*wrb
;
4200 struct be_cmd_req_intr_set
*req
;
4203 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
4206 wrb
= wrb_from_mbox(adapter
);
4208 req
= embedded_payload(wrb
);
4210 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4211 OPCODE_COMMON_SET_INTERRUPT_ENABLE
, sizeof(*req
),
4214 req
->intr_enabled
= intr_enable
;
4216 status
= be_mbox_notify_wait(adapter
);
4218 mutex_unlock(&adapter
->mbox_lock
);
4223 int be_cmd_get_active_profile(struct be_adapter
*adapter
, u16
*profile_id
)
4225 struct be_cmd_req_get_active_profile
*req
;
4226 struct be_mcc_wrb
*wrb
;
4229 if (mutex_lock_interruptible(&adapter
->mbox_lock
))
4232 wrb
= wrb_from_mbox(adapter
);
4238 req
= embedded_payload(wrb
);
4240 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4241 OPCODE_COMMON_GET_ACTIVE_PROFILE
, sizeof(*req
),
4244 status
= be_mbox_notify_wait(adapter
);
4246 struct be_cmd_resp_get_active_profile
*resp
=
4247 embedded_payload(wrb
);
4249 *profile_id
= le16_to_cpu(resp
->active_profile_id
);
4253 mutex_unlock(&adapter
->mbox_lock
);
4257 int be_cmd_set_logical_link_config(struct be_adapter
*adapter
,
4258 int link_state
, u8 domain
)
4260 struct be_mcc_wrb
*wrb
;
4261 struct be_cmd_req_set_ll_link
*req
;
4264 if (BEx_chip(adapter
) || lancer_chip(adapter
))
4267 spin_lock_bh(&adapter
->mcc_lock
);
4269 wrb
= wrb_from_mccq(adapter
);
4275 req
= embedded_payload(wrb
);
4277 be_wrb_cmd_hdr_prepare(&req
->hdr
, CMD_SUBSYSTEM_COMMON
,
4278 OPCODE_COMMON_SET_LOGICAL_LINK_CONFIG
,
4279 sizeof(*req
), wrb
, NULL
);
4281 req
->hdr
.version
= 1;
4282 req
->hdr
.domain
= domain
;
4284 if (link_state
== IFLA_VF_LINK_STATE_ENABLE
)
4285 req
->link_config
|= 1;
4287 if (link_state
== IFLA_VF_LINK_STATE_AUTO
)
4288 req
->link_config
|= 1 << PLINK_TRACK_SHIFT
;
4290 status
= be_mcc_notify_wait(adapter
);
4292 spin_unlock_bh(&adapter
->mcc_lock
);
4296 int be_roce_mcc_cmd(void *netdev_handle
, void *wrb_payload
,
4297 int wrb_payload_size
, u16
*cmd_status
, u16
*ext_status
)
4299 struct be_adapter
*adapter
= netdev_priv(netdev_handle
);
4300 struct be_mcc_wrb
*wrb
;
4301 struct be_cmd_req_hdr
*hdr
= (struct be_cmd_req_hdr
*)wrb_payload
;
4302 struct be_cmd_req_hdr
*req
;
4303 struct be_cmd_resp_hdr
*resp
;
4306 spin_lock_bh(&adapter
->mcc_lock
);
4308 wrb
= wrb_from_mccq(adapter
);
4313 req
= embedded_payload(wrb
);
4314 resp
= embedded_payload(wrb
);
4316 be_wrb_cmd_hdr_prepare(req
, hdr
->subsystem
,
4317 hdr
->opcode
, wrb_payload_size
, wrb
, NULL
);
4318 memcpy(req
, wrb_payload
, wrb_payload_size
);
4319 be_dws_cpu_to_le(req
, wrb_payload_size
);
4321 status
= be_mcc_notify_wait(adapter
);
4323 *cmd_status
= (status
& 0xffff);
4326 memcpy(wrb_payload
, resp
, sizeof(*resp
) + resp
->response_length
);
4327 be_dws_le_to_cpu(wrb_payload
, sizeof(*resp
) + resp
->response_length
);
4329 spin_unlock_bh(&adapter
->mcc_lock
);
4332 EXPORT_SYMBOL(be_roce_mcc_cmd
);