include/linux/mtd/nand.h

   1 /*
   2  *  linux/include/linux/mtd/nand.h
   3  *
   4  *  Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
   5  *                        Steven J. Hill <sjhill@realitydiluted.com>
   6  *                        Thomas Gleixner <tglx@linutronix.de>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2 as
  10  * published by the Free Software Foundation.
  11  *
  12  * Info:
  13  *      Contains standard defines and IDs for NAND flash devices
  14  *
  15  * Changelog:
  16  *      See git changelog.
  17  */
  18 #ifndef __LINUX_MTD_NAND_H
  19 #define __LINUX_MTD_NAND_H
  20
  21 #include <linux/wait.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/mtd/mtd.h>
  24 #include <linux/mtd/flashchip.h>
  25 #include <linux/mtd/bbm.h>
  26
  27 struct mtd_info;
  28 struct nand_flash_dev;
  29 /* Scan and identify a NAND device */
  30 extern int nand_scan(struct mtd_info *mtd, int max_chips);
  31 /*
  32  * Separate phases of nand_scan(), allowing board driver to intervene
  33  * and override command or ECC setup according to flash type.
  34  */
  35 extern int nand_scan_ident(struct mtd_info *mtd, int max_chips,
  36                            struct nand_flash_dev *table);
  37 extern int nand_scan_tail(struct mtd_info *mtd);
  38
  39 /* Free resources held by the NAND device */
  40 extern void nand_release(struct mtd_info *mtd);
  41
  42 /* Internal helper for board drivers which need to override command function */
  43 extern void nand_wait_ready(struct mtd_info *mtd);
  44
  45 /* locks all blocks present in the device */
  46 extern int nand_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  47
  48 /* unlocks specified locked blocks */
  49 extern int nand_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
  50
  51 /* The maximum number of NAND chips in an array */
  52 #define NAND_MAX_CHIPS          8
  53
  54 /*
  55  * This constant declares the max. oobsize / page, which
  56  * is supported now. If you add a chip with bigger oobsize/page
  57  * adjust this accordingly.
  58  */
  59 #define NAND_MAX_OOBSIZE        576
  60 #define NAND_MAX_PAGESIZE       8192
  61
  62 /*
  63  * Constants for hardware specific CLE/ALE/NCE function
  64  *
  65  * These are bits which can be or'ed to set/clear multiple
  66  * bits in one go.
  67  */
  68 /* Select the chip by setting nCE to low */
  69 #define NAND_NCE                0x01
  70 /* Select the command latch by setting CLE to high */
  71 #define NAND_CLE                0x02
  72 /* Select the address latch by setting ALE to high */
  73 #define NAND_ALE                0x04
  74
  75 #define NAND_CTRL_CLE           (NAND_NCE | NAND_CLE)
  76 #define NAND_CTRL_ALE           (NAND_NCE | NAND_ALE)
  77 #define NAND_CTRL_CHANGE        0x80
  78
  79 /*
  80  * Standard NAND flash commands
  81  */
  82 #define NAND_CMD_READ0          0
  83 #define NAND_CMD_READ1          1
  84 #define NAND_CMD_RNDOUT         5
  85 #define NAND_CMD_PAGEPROG       0x10
  86 #define NAND_CMD_READOOB        0x50
  87 #define NAND_CMD_ERASE1         0x60
  88 #define NAND_CMD_STATUS         0x70
  89 #define NAND_CMD_STATUS_MULTI   0x71
  90 #define NAND_CMD_SEQIN          0x80
  91 #define NAND_CMD_RNDIN          0x85
  92 #define NAND_CMD_READID         0x90
  93 #define NAND_CMD_ERASE2         0xd0
  94 #define NAND_CMD_PARAM          0xec
  95 #define NAND_CMD_RESET          0xff
  96
  97 #define NAND_CMD_LOCK           0x2a
  98 #define NAND_CMD_UNLOCK1        0x23
  99 #define NAND_CMD_UNLOCK2        0x24
 100
 101 /* Extended commands for large page devices */
 102 #define NAND_CMD_READSTART      0x30
 103 #define NAND_CMD_RNDOUTSTART    0xE0
 104 #define NAND_CMD_CACHEDPROG     0x15
 105
 106 /* Extended commands for AG-AND device */
 107 /*
 108  * Note: the command for NAND_CMD_DEPLETE1 is really 0x00 but
 109  *       there is no way to distinguish that from NAND_CMD_READ0
 110  *       until the remaining sequence of commands has been completed
 111  *       so add a high order bit and mask it off in the command.
 112  */
 113 #define NAND_CMD_DEPLETE1       0x100
 114 #define NAND_CMD_DEPLETE2       0x38
 115 #define NAND_CMD_STATUS_MULTI   0x71
 116 #define NAND_CMD_STATUS_ERROR   0x72
 117 /* multi-bank error status (banks 0-3) */
 118 #define NAND_CMD_STATUS_ERROR0  0x73
 119 #define NAND_CMD_STATUS_ERROR1  0x74
 120 #define NAND_CMD_STATUS_ERROR2  0x75
 121 #define NAND_CMD_STATUS_ERROR3  0x76
 122 #define NAND_CMD_STATUS_RESET   0x7f
 123 #define NAND_CMD_STATUS_CLEAR   0xff
 124
 125 #define NAND_CMD_NONE           -1
 126
 127 /* Status bits */
 128 #define NAND_STATUS_FAIL        0x01
 129 #define NAND_STATUS_FAIL_N1     0x02
 130 #define NAND_STATUS_TRUE_READY  0x20
 131 #define NAND_STATUS_READY       0x40
 132 #define NAND_STATUS_WP          0x80
 133
 134 /*
 135  * Constants for ECC_MODES
 136  */
 137 typedef enum {
 138         NAND_ECC_NONE,
 139         NAND_ECC_SOFT,
 140         NAND_ECC_HW,
 141         NAND_ECC_HW_SYNDROME,
 142         NAND_ECC_HW_OOB_FIRST,
 143         NAND_ECC_SOFT_BCH,
 144 } nand_ecc_modes_t;
 145
 146 /*
 147  * Constants for Hardware ECC
 148  */
 149 /* Reset Hardware ECC for read */
 150 #define NAND_ECC_READ           0
 151 /* Reset Hardware ECC for write */
 152 #define NAND_ECC_WRITE          1
 153 /* Enable Hardware ECC before syndrome is read back from flash */
 154 #define NAND_ECC_READSYN        2
 155
 156 /* Bit mask for flags passed to do_nand_read_ecc */
 157 #define NAND_GET_DEVICE         0x80
 158
 159
 160 /*
 161  * Option constants for bizarre disfunctionality and real
 162  * features.
 163  */
 164 /* Chip can not auto increment pages */
 165 #define NAND_NO_AUTOINCR        0x00000001
 166 /* Buswidth is 16 bit */
 167 #define NAND_BUSWIDTH_16        0x00000002
 168 /* Device supports partial programming without padding */
 169 #define NAND_NO_PADDING         0x00000004
 170 /* Chip has cache program function */
 171 #define NAND_CACHEPRG           0x00000008
 172 /* Chip has copy back function */
 173 #define NAND_COPYBACK           0x00000010
 174 /*
 175  * AND Chip which has 4 banks and a confusing page / block
 176  * assignment. See Renesas datasheet for further information.
 177  */
 178 #define NAND_IS_AND             0x00000020
 179 /*
 180  * Chip has a array of 4 pages which can be read without
 181  * additional ready /busy waits.
 182  */
 183 #define NAND_4PAGE_ARRAY        0x00000040
 184 /*
 185  * Chip requires that BBT is periodically rewritten to prevent
 186  * bits from adjacent blocks from 'leaking' in altering data.
 187  * This happens with the Renesas AG-AND chips, possibly others.
 188  */
 189 #define BBT_AUTO_REFRESH        0x00000080
 190 /*
 191  * Chip does not require ready check on read. True
 192  * for all large page devices, as they do not support
 193  * autoincrement.
 194  */
 195 #define NAND_NO_READRDY         0x00000100
 196 /* Chip does not allow subpage writes */
 197 #define NAND_NO_SUBPAGE_WRITE   0x00000200
 198
 199 /* Device is one of 'new' xD cards that expose fake nand command set */
 200 #define NAND_BROKEN_XD          0x00000400
 201
 202 /* Device behaves just like nand, but is readonly */
 203 #define NAND_ROM                0x00000800
 204
 205 /* Options valid for Samsung large page devices */
 206 #define NAND_SAMSUNG_LP_OPTIONS \
 207         (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK)
 208
 209 /* Macros to identify the above */
 210 #define NAND_CANAUTOINCR(chip) (!(chip->options & NAND_NO_AUTOINCR))
 211 #define NAND_MUST_PAD(chip) (!(chip->options & NAND_NO_PADDING))
 212 #define NAND_HAS_CACHEPROG(chip) ((chip->options & NAND_CACHEPRG))
 213 #define NAND_HAS_COPYBACK(chip) ((chip->options & NAND_COPYBACK))
 214 /* Large page NAND with SOFT_ECC should support subpage reads */
 215 #define NAND_SUBPAGE_READ(chip) ((chip->ecc.mode == NAND_ECC_SOFT) \
 216                                         && (chip->page_shift > 9))
 217
 218 /* Mask to zero out the chip options, which come from the id table */
 219 #define NAND_CHIPOPTIONS_MSK    (0x0000ffff & ~NAND_NO_AUTOINCR)
 220
 221 /* Non chip related options */
 222 /* This option skips the bbt scan during initialization. */
 223 #define NAND_SKIP_BBTSCAN       0x00010000
 224 /*
 225  * This option is defined if the board driver allocates its own buffers
 226  * (e.g. because it needs them DMA-coherent).
 227  */
 228 #define NAND_OWN_BUFFERS        0x00020000
 229 /* Chip may not exist, so silence any errors in scan */
 230 #define NAND_SCAN_SILENT_NODEV  0x00040000
 231
 232 /* Options set by nand scan */
 233 /* Nand scan has allocated controller struct */
 234 #define NAND_CONTROLLER_ALLOC   0x80000000
 235
 236 /* Cell info constants */
 237 #define NAND_CI_CHIPNR_MSK      0x03
 238 #define NAND_CI_CELLTYPE_MSK    0x0C
 239
 240 /* Keep gcc happy */
 241 struct nand_chip;
 242
 243 struct nand_onfi_params {
 244         /* rev info and features block */
 245         /* 'O' 'N' 'F' 'I'  */
 246         u8 sig[4];
 247         __le16 revision;
 248         __le16 features;
 249         __le16 opt_cmd;
 250         u8 reserved[22];
 251
 252         /* manufacturer information block */
 253         char manufacturer[12];
 254         char model[20];
 255         u8 jedec_id;
 256         __le16 date_code;
 257         u8 reserved2[13];
 258
 259         /* memory organization block */
 260         __le32 byte_per_page;
 261         __le16 spare_bytes_per_page;
 262         __le32 data_bytes_per_ppage;
 263         __le16 spare_bytes_per_ppage;
 264         __le32 pages_per_block;
 265         __le32 blocks_per_lun;
 266         u8 lun_count;
 267         u8 addr_cycles;
 268         u8 bits_per_cell;
 269         __le16 bb_per_lun;
 270         __le16 block_endurance;
 271         u8 guaranteed_good_blocks;
 272         __le16 guaranteed_block_endurance;
 273         u8 programs_per_page;
 274         u8 ppage_attr;
 275         u8 ecc_bits;
 276         u8 interleaved_bits;
 277         u8 interleaved_ops;
 278         u8 reserved3[13];
 279
 280         /* electrical parameter block */
 281         u8 io_pin_capacitance_max;
 282         __le16 async_timing_mode;
 283         __le16 program_cache_timing_mode;
 284         __le16 t_prog;
 285         __le16 t_bers;
 286         __le16 t_r;
 287         __le16 t_ccs;
 288         __le16 src_sync_timing_mode;
 289         __le16 src_ssync_features;
 290         __le16 clk_pin_capacitance_typ;
 291         __le16 io_pin_capacitance_typ;
 292         __le16 input_pin_capacitance_typ;
 293         u8 input_pin_capacitance_max;
 294         u8 driver_strenght_support;
 295         __le16 t_int_r;
 296         __le16 t_ald;
 297         u8 reserved4[7];
 298
 299         /* vendor */
 300         u8 reserved5[90];
 301
 302         __le16 crc;
 303 } __attribute__((packed));
 304
 305 #define ONFI_CRC_BASE   0x4F4E
 306
 307 /**
 308  * struct nand_hw_control - Control structure for hardware controller (e.g ECC generator) shared among independent devices
 309  * @lock:               protection lock
 310  * @active:             the mtd device which holds the controller currently
 311  * @wq:                 wait queue to sleep on if a NAND operation is in
 312  *                      progress used instead of the per chip wait queue
 313  *                      when a hw controller is available.
 314  */
 315 struct nand_hw_control {
 316         spinlock_t lock;
 317         struct nand_chip *active;
 318         wait_queue_head_t wq;
 319 };
 320
 321 /**
 322  * struct nand_ecc_ctrl - Control structure for ECC
 323  * @mode:       ECC mode
 324  * @steps:      number of ECC steps per page
 325  * @size:       data bytes per ECC step
 326  * @bytes:      ECC bytes per step
 327  * @total:      total number of ECC bytes per page
 328  * @prepad:     padding information for syndrome based ECC generators
 329  * @postpad:    padding information for syndrome based ECC generators
 330  * @layout:     ECC layout control struct pointer
 331  * @priv:       pointer to private ECC control data
 332  * @hwctl:      function to control hardware ECC generator. Must only
 333  *              be provided if an hardware ECC is available
 334  * @calculate:  function for ECC calculation or readback from ECC hardware
 335  * @correct:    function for ECC correction, matching to ECC generator (sw/hw)
 336  * @read_page_raw:      function to read a raw page without ECC
 337  * @write_page_raw:     function to write a raw page without ECC
 338  * @read_page:  function to read a page according to the ECC generator
 339  *              requirements.
 340  * @read_subpage:       function to read parts of the page covered by ECC.
 341  * @write_page: function to write a page according to the ECC generator
 342  *              requirements.
 343  * @write_oob_raw:      function to write chip OOB data without ECC
 344  * @read_oob_raw:       function to read chip OOB data without ECC
 345  * @read_oob:   function to read chip OOB data
 346  * @write_oob:  function to write chip OOB data
 347  */
 348 struct nand_ecc_ctrl {
 349         nand_ecc_modes_t mode;
 350         int steps;
 351         int size;
 352         int bytes;
 353         int total;
 354         int prepad;
 355         int postpad;
 356         struct nand_ecclayout   *layout;
 357         void *priv;
 358         void (*hwctl)(struct mtd_info *mtd, int mode);
 359         int (*calculate)(struct mtd_info *mtd, const uint8_t *dat,
 360                         uint8_t *ecc_code);
 361         int (*correct)(struct mtd_info *mtd, uint8_t *dat, uint8_t *read_ecc,
 362                         uint8_t *calc_ecc);
 363         int (*read_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 364                         uint8_t *buf, int page);
 365         void (*write_page_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 366                         const uint8_t *buf);
 367         int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
 368                         uint8_t *buf, int page);
 369         int (*read_subpage)(struct mtd_info *mtd, struct nand_chip *chip,
 370                         uint32_t offs, uint32_t len, uint8_t *buf);
 371         void (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 372                         const uint8_t *buf);
 373         int (*write_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 374                         int page);
 375         int (*read_oob_raw)(struct mtd_info *mtd, struct nand_chip *chip,
 376                         int page, int sndcmd);
 377         int (*read_oob)(struct mtd_info *mtd, struct nand_chip *chip, int page,
 378                         int sndcmd);
 379         int (*write_oob)(struct mtd_info *mtd, struct nand_chip *chip,
 380                         int page);
 381 };
 382
 383 /**
 384  * struct nand_buffers - buffer structure for read/write
 385  * @ecccalc:    buffer for calculated ECC
 386  * @ecccode:    buffer for ECC read from flash
 387  * @databuf:    buffer for data - dynamically sized
 388  *
 389  * Do not change the order of buffers. databuf and oobrbuf must be in
 390  * consecutive order.
 391  */
 392 struct nand_buffers {
 393         uint8_t ecccalc[NAND_MAX_OOBSIZE];
 394         uint8_t ecccode[NAND_MAX_OOBSIZE];
 395         uint8_t databuf[NAND_MAX_PAGESIZE + NAND_MAX_OOBSIZE];
 396 };
 397
 398 /**
 399  * struct nand_chip - NAND Private Flash Chip Data
 400  * @IO_ADDR_R:          [BOARDSPECIFIC] address to read the 8 I/O lines of the
 401  *                      flash device
 402  * @IO_ADDR_W:          [BOARDSPECIFIC] address to write the 8 I/O lines of the
 403  *                      flash device.
 404  * @read_byte:          [REPLACEABLE] read one byte from the chip
 405  * @read_word:          [REPLACEABLE] read one word from the chip
 406  * @write_buf:          [REPLACEABLE] write data from the buffer to the chip
 407  * @read_buf:           [REPLACEABLE] read data from the chip into the buffer
 408  * @verify_buf:         [REPLACEABLE] verify buffer contents against the chip
 409  *                      data.
 410  * @select_chip:        [REPLACEABLE] select chip nr
 411  * @block_bad:          [REPLACEABLE] check, if the block is bad
 412  * @block_markbad:      [REPLACEABLE] mark the block bad
 413  * @cmd_ctrl:           [BOARDSPECIFIC] hardwarespecific function for controlling
 414  *                      ALE/CLE/nCE. Also used to write command and address
 415  * @init_size:          [BOARDSPECIFIC] hardwarespecific function for setting
 416  *                      mtd->oobsize, mtd->writesize and so on.
 417  *                      @id_data contains the 8 bytes values of NAND_CMD_READID.
 418  *                      Return with the bus width.
 419  * @dev_ready:          [BOARDSPECIFIC] hardwarespecific function for accessing
 420  *                      device ready/busy line. If set to NULL no access to
 421  *                      ready/busy is available and the ready/busy information
 422  *                      is read from the chip status register.
 423  * @cmdfunc:            [REPLACEABLE] hardwarespecific function for writing
 424  *                      commands to the chip.
 425  * @waitfunc:           [REPLACEABLE] hardwarespecific function for wait on
 426  *                      ready.
 427  * @ecc:                [BOARDSPECIFIC] ECC control structure
 428  * @buffers:            buffer structure for read/write
 429  * @hwcontrol:          platform-specific hardware control structure
 430  * @erase_cmd:          [INTERN] erase command write function, selectable due
 431  *                      to AND support.
 432  * @scan_bbt:           [REPLACEABLE] function to scan bad block table
 433  * @chip_delay:         [BOARDSPECIFIC] chip dependent delay for transferring
 434  *                      data from array to read regs (tR).
 435  * @state:              [INTERN] the current state of the NAND device
 436  * @oob_poi:            "poison value buffer," used for laying out OOB data
 437  *                      before writing
 438  * @page_shift:         [INTERN] number of address bits in a page (column
 439  *                      address bits).
 440  * @phys_erase_shift:   [INTERN] number of address bits in a physical eraseblock
 441  * @bbt_erase_shift:    [INTERN] number of address bits in a bbt entry
 442  * @chip_shift:         [INTERN] number of address bits in one chip
 443  * @options:            [BOARDSPECIFIC] various chip options. They can partly
 444  *                      be set to inform nand_scan about special functionality.
 445  *                      See the defines for further explanation.
 446  * @bbt_options:        [INTERN] bad block specific options. All options used
 447  *                      here must come from bbm.h. By default, these options
 448  *                      will be copied to the appropriate nand_bbt_descr's.
 449  * @badblockpos:        [INTERN] position of the bad block marker in the oob
 450  *                      area.
 451  * @badblockbits:       [INTERN] number of bits to left-shift the bad block
 452  *                      number
 453  * @cellinfo:           [INTERN] MLC/multichip data from chip ident
 454  * @numchips:           [INTERN] number of physical chips
 455  * @chipsize:           [INTERN] the size of one chip for multichip arrays
 456  * @pagemask:           [INTERN] page number mask = number of (pages / chip) - 1
 457  * @pagebuf:            [INTERN] holds the pagenumber which is currently in
 458  *                      data_buf.
 459  * @subpagesize:        [INTERN] holds the subpagesize
 460  * @onfi_version:       [INTERN] holds the chip ONFI version (BCD encoded),
 461  *                      non 0 if ONFI supported.
 462  * @onfi_params:        [INTERN] holds the ONFI page parameter when ONFI is
 463  *                      supported, 0 otherwise.
 464  * @ecclayout:          [REPLACEABLE] the default ECC placement scheme
 465  * @bbt:                [INTERN] bad block table pointer
 466  * @bbt_td:             [REPLACEABLE] bad block table descriptor for flash
 467  *                      lookup.
 468  * @bbt_md:             [REPLACEABLE] bad block table mirror descriptor
 469  * @badblock_pattern:   [REPLACEABLE] bad block scan pattern used for initial
 470  *                      bad block scan.
 471  * @controller:         [REPLACEABLE] a pointer to a hardware controller
 472  *                      structure which is shared among multiple independent
 473  *                      devices.
 474  * @priv:               [OPTIONAL] pointer to private chip data
 475  * @errstat:            [OPTIONAL] hardware specific function to perform
 476  *                      additional error status checks (determine if errors are
 477  *                      correctable).
 478  * @write_page:         [REPLACEABLE] High-level page write function
 479  */
 480
 481 struct nand_chip {
 482         void __iomem *IO_ADDR_R;
 483         void __iomem *IO_ADDR_W;
 484
 485         uint8_t (*read_byte)(struct mtd_info *mtd);
 486         u16 (*read_word)(struct mtd_info *mtd);
 487         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 488         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 489         int (*verify_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 490         void (*select_chip)(struct mtd_info *mtd, int chip);
 491         int (*block_bad)(struct mtd_info *mtd, loff_t ofs, int getchip);
 492         int (*block_markbad)(struct mtd_info *mtd, loff_t ofs);
 493         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 494         int (*init_size)(struct mtd_info *mtd, struct nand_chip *this,
 495                         u8 *id_data);
 496         int (*dev_ready)(struct mtd_info *mtd);
 497         void (*cmdfunc)(struct mtd_info *mtd, unsigned command, int column,
 498                         int page_addr);
 499         int(*waitfunc)(struct mtd_info *mtd, struct nand_chip *this);
 500         void (*erase_cmd)(struct mtd_info *mtd, int page);
 501         int (*scan_bbt)(struct mtd_info *mtd);
 502         int (*errstat)(struct mtd_info *mtd, struct nand_chip *this, int state,
 503                         int status, int page);
 504         int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
 505                         const uint8_t *buf, int page, int cached, int raw);
 506
 507         int chip_delay;
 508         unsigned int options;
 509         unsigned int bbt_options;
 510
 511         int page_shift;
 512         int phys_erase_shift;
 513         int bbt_erase_shift;
 514         int chip_shift;
 515         int numchips;
 516         uint64_t chipsize;
 517         int pagemask;
 518         int pagebuf;
 519         int subpagesize;
 520         uint8_t cellinfo;
 521         int badblockpos;
 522         int badblockbits;
 523
 524         int onfi_version;
 525         struct nand_onfi_params onfi_params;
 526
 527         flstate_t state;
 528
 529         uint8_t *oob_poi;
 530         struct nand_hw_control *controller;
 531         struct nand_ecclayout *ecclayout;
 532
 533         struct nand_ecc_ctrl ecc;
 534         struct nand_buffers *buffers;
 535         struct nand_hw_control hwcontrol;
 536
 537         uint8_t *bbt;
 538         struct nand_bbt_descr *bbt_td;
 539         struct nand_bbt_descr *bbt_md;
 540
 541         struct nand_bbt_descr *badblock_pattern;
 542
 543         void *priv;
 544 };
 545
 546 /*
 547  * NAND Flash Manufacturer ID Codes
 548  */
 549 #define NAND_MFR_TOSHIBA        0x98
 550 #define NAND_MFR_SAMSUNG        0xec
 551 #define NAND_MFR_FUJITSU        0x04
 552 #define NAND_MFR_NATIONAL       0x8f
 553 #define NAND_MFR_RENESAS        0x07
 554 #define NAND_MFR_STMICRO        0x20
 555 #define NAND_MFR_HYNIX          0xad
 556 #define NAND_MFR_MICRON         0x2c
 557 #define NAND_MFR_AMD            0x01
 558 #define NAND_MFR_MACRONIX       0xc2
 559
 560 /**
 561  * struct nand_flash_dev - NAND Flash Device ID Structure
 562  * @name:       Identify the device type
 563  * @id:         device ID code
 564  * @pagesize:   Pagesize in bytes. Either 256 or 512 or 0
 565  *              If the pagesize is 0, then the real pagesize
 566  *              and the eraseize are determined from the
 567  *              extended id bytes in the chip
 568  * @erasesize:  Size of an erase block in the flash device.
 569  * @chipsize:   Total chipsize in Mega Bytes
 570  * @options:    Bitfield to store chip relevant options
 571  */
 572 struct nand_flash_dev {
 573         char *name;
 574         int id;
 575         unsigned long pagesize;
 576         unsigned long chipsize;
 577         unsigned long erasesize;
 578         unsigned long options;
 579 };
 580
 581 /**
 582  * struct nand_manufacturers - NAND Flash Manufacturer ID Structure
 583  * @name:       Manufacturer name
 584  * @id:         manufacturer ID code of device.
 585 */
 586 struct nand_manufacturers {
 587         int id;
 588         char *name;
 589 };
 590
 591 extern struct nand_flash_dev nand_flash_ids[];
 592 extern struct nand_manufacturers nand_manuf_ids[];
 593
 594 extern int nand_scan_bbt(struct mtd_info *mtd, struct nand_bbt_descr *bd);
 595 extern int nand_update_bbt(struct mtd_info *mtd, loff_t offs);
 596 extern int nand_default_bbt(struct mtd_info *mtd);
 597 extern int nand_isbad_bbt(struct mtd_info *mtd, loff_t offs, int allowbbt);
 598 extern int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
 599                            int allowbbt);
 600 extern int nand_do_read(struct mtd_info *mtd, loff_t from, size_t len,
 601                         size_t *retlen, uint8_t *buf);
 602
 603 /**
 604  * struct platform_nand_chip - chip level device structure
 605  * @nr_chips:           max. number of chips to scan for
 606  * @chip_offset:        chip number offset
 607  * @nr_partitions:      number of partitions pointed to by partitions (or zero)
 608  * @partitions:         mtd partition list
 609  * @chip_delay:         R/B delay value in us
 610  * @options:            Option flags, e.g. 16bit buswidth
 611  * @bbt_options:        BBT option flags, e.g. NAND_BBT_USE_FLASH
 612  * @ecclayout:          ECC layout info structure
 613  * @part_probe_types:   NULL-terminated array of probe types
 614  */
 615 struct platform_nand_chip {
 616         int nr_chips;
 617         int chip_offset;
 618         int nr_partitions;
 619         struct mtd_partition *partitions;
 620         struct nand_ecclayout *ecclayout;
 621         int chip_delay;
 622         unsigned int options;
 623         unsigned int bbt_options;
 624         const char **part_probe_types;
 625 };
 626
 627 /* Keep gcc happy */
 628 struct platform_device;
 629
 630 /**
 631  * struct platform_nand_ctrl - controller level device structure
 632  * @probe:              platform specific function to probe/setup hardware
 633  * @remove:             platform specific function to remove/teardown hardware
 634  * @hwcontrol:          platform specific hardware control structure
 635  * @dev_ready:          platform specific function to read ready/busy pin
 636  * @select_chip:        platform specific chip select function
 637  * @cmd_ctrl:           platform specific function for controlling
 638  *                      ALE/CLE/nCE. Also used to write command and address
 639  * @write_buf:          platform specific function for write buffer
 640  * @read_buf:           platform specific function for read buffer
 641  * @priv:               private data to transport driver specific settings
 642  *
 643  * All fields are optional and depend on the hardware driver requirements
 644  */
 645 struct platform_nand_ctrl {
 646         int (*probe)(struct platform_device *pdev);
 647         void (*remove)(struct platform_device *pdev);
 648         void (*hwcontrol)(struct mtd_info *mtd, int cmd);
 649         int (*dev_ready)(struct mtd_info *mtd);
 650         void (*select_chip)(struct mtd_info *mtd, int chip);
 651         void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl);
 652         void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len);
 653         void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len);
 654         void *priv;
 655 };
 656
 657 /**
 658  * struct platform_nand_data - container structure for platform-specific data
 659  * @chip:               chip level chip structure
 660  * @ctrl:               controller level device structure
 661  */
 662 struct platform_nand_data {
 663         struct platform_nand_chip chip;
 664         struct platform_nand_ctrl ctrl;
 665 };
 666
 667 /* Some helpers to access the data structures */
 668 static inline
 669 struct platform_nand_chip *get_platform_nandchip(struct mtd_info *mtd)
 670 {
 671         struct nand_chip *chip = mtd->priv;
 672
 673         return chip->priv;
 674 }
 675
 676 #endif /* __LINUX_MTD_NAND_H */