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drivers/net: const-ify ethtool_ops declarations
[linux-2.6/btrfs-unstable.git] / drivers / net / pcnet32.c
blob21dc68eff514c424a7771848347f78e66c7d6581
1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
2 /*
3 * Copyright 1996-1999 Thomas Bogendoerfer
4 *
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
6 *
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
9 *
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
12 *
13 * This driver is for PCnet32 and PCnetPCI based ethercards
14 */
15 /**************************************************************************
16 * 23 Oct, 2000.
17 * Fixed a few bugs, related to running the controller in 32bit mode.
18 *
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
21 *
22 *************************************************************************/
23
24 #include <linux/config.h>
25
26 #define DRV_NAME "pcnet32"
27 #ifdef CONFIG_PCNET32_NAPI
28 #define DRV_VERSION "1.33-NAPI"
29 #else
30 #define DRV_VERSION "1.33"
31 #endif
32 #define DRV_RELDATE "27.Jun.2006"
33 #define PFX DRV_NAME ": "
34
35 static const char *const version =
36 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
37
38 #include <linux/module.h>
39 #include <linux/kernel.h>
40 #include <linux/string.h>
41 #include <linux/errno.h>
42 #include <linux/ioport.h>
43 #include <linux/slab.h>
44 #include <linux/interrupt.h>
45 #include <linux/pci.h>
46 #include <linux/delay.h>
47 #include <linux/init.h>
48 #include <linux/ethtool.h>
49 #include <linux/mii.h>
50 #include <linux/crc32.h>
51 #include <linux/netdevice.h>
52 #include <linux/etherdevice.h>
53 #include <linux/skbuff.h>
54 #include <linux/spinlock.h>
55 #include <linux/moduleparam.h>
56 #include <linux/bitops.h>
57
58 #include <asm/dma.h>
59 #include <asm/io.h>
60 #include <asm/uaccess.h>
61 #include <asm/irq.h>
62
63 /*
64 * PCI device identifiers for "new style" Linux PCI Device Drivers
65 */
66 static struct pci_device_id pcnet32_pci_tbl[] = {
67 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME), },
68 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE), },
69
70 /*
71 * Adapters that were sold with IBM's RS/6000 or pSeries hardware have
72 * the incorrect vendor id.
73 */
74 { PCI_DEVICE(PCI_VENDOR_ID_TRIDENT, PCI_DEVICE_ID_AMD_LANCE),
75 .class = (PCI_CLASS_NETWORK_ETHERNET << 8), .class_mask = 0xffff00, },
76
77 { } /* terminate list */
78 };
79
80 MODULE_DEVICE_TABLE(pci, pcnet32_pci_tbl);
81
82 static int cards_found;
83
84 /*
85 * VLB I/O addresses
86 */
87 static unsigned int pcnet32_portlist[] __initdata =
88 { 0x300, 0x320, 0x340, 0x360, 0 };
89
90 static int pcnet32_debug = 0;
91 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
92 static int pcnet32vlb; /* check for VLB cards ? */
93
94 static struct net_device *pcnet32_dev;
95
96 static int max_interrupt_work = 2;
97 static int rx_copybreak = 200;
98
99 #define PCNET32_PORT_AUI 0x00
100 #define PCNET32_PORT_10BT 0x01
101 #define PCNET32_PORT_GPSI 0x02
102 #define PCNET32_PORT_MII 0x03
103
104 #define PCNET32_PORT_PORTSEL 0x03
105 #define PCNET32_PORT_ASEL 0x04
106 #define PCNET32_PORT_100 0x40
107 #define PCNET32_PORT_FD 0x80
108
109 #define PCNET32_DMA_MASK 0xffffffff
110
111 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
112 #define PCNET32_BLINK_TIMEOUT (jiffies + (HZ/4))
113
114 /*
115 * table to translate option values from tulip
116 * to internal options
117 */
118 static const unsigned char options_mapping[] = {
119 PCNET32_PORT_ASEL, /* 0 Auto-select */
120 PCNET32_PORT_AUI, /* 1 BNC/AUI */
121 PCNET32_PORT_AUI, /* 2 AUI/BNC */
122 PCNET32_PORT_ASEL, /* 3 not supported */
123 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
124 PCNET32_PORT_ASEL, /* 5 not supported */
125 PCNET32_PORT_ASEL, /* 6 not supported */
126 PCNET32_PORT_ASEL, /* 7 not supported */
127 PCNET32_PORT_ASEL, /* 8 not supported */
128 PCNET32_PORT_MII, /* 9 MII 10baseT */
129 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
130 PCNET32_PORT_MII, /* 11 MII (autosel) */
131 PCNET32_PORT_10BT, /* 12 10BaseT */
132 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
133 /* 14 MII 100BaseTx-FD */
134 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD,
135 PCNET32_PORT_ASEL /* 15 not supported */
136 };
137
138 static const char pcnet32_gstrings_test[][ETH_GSTRING_LEN] = {
139 "Loopback test (offline)"
140 };
141
142 #define PCNET32_TEST_LEN (sizeof(pcnet32_gstrings_test) / ETH_GSTRING_LEN)
143
144 #define PCNET32_NUM_REGS 136
145
146 #define MAX_UNITS 8 /* More are supported, limit only on options */
147 static int options[MAX_UNITS];
148 static int full_duplex[MAX_UNITS];
149 static int homepna[MAX_UNITS];
150
151 /*
152 * Theory of Operation
153 *
154 * This driver uses the same software structure as the normal lance
155 * driver. So look for a verbose description in lance.c. The differences
156 * to the normal lance driver is the use of the 32bit mode of PCnet32
157 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
158 * 16MB limitation and we don't need bounce buffers.
159 */
160
161 /*
162 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
163 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
164 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
165 */
166 #ifndef PCNET32_LOG_TX_BUFFERS
167 #define PCNET32_LOG_TX_BUFFERS 4
168 #define PCNET32_LOG_RX_BUFFERS 5
169 #define PCNET32_LOG_MAX_TX_BUFFERS 9 /* 2^9 == 512 */
170 #define PCNET32_LOG_MAX_RX_BUFFERS 9
171 #endif
172
173 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
174 #define TX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_TX_BUFFERS))
175
176 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
177 #define RX_MAX_RING_SIZE (1 << (PCNET32_LOG_MAX_RX_BUFFERS))
178
179 #define PKT_BUF_SZ 1544
180
181 /* Offsets from base I/O address. */
182 #define PCNET32_WIO_RDP 0x10
183 #define PCNET32_WIO_RAP 0x12
184 #define PCNET32_WIO_RESET 0x14
185 #define PCNET32_WIO_BDP 0x16
186
187 #define PCNET32_DWIO_RDP 0x10
188 #define PCNET32_DWIO_RAP 0x14
189 #define PCNET32_DWIO_RESET 0x18
190 #define PCNET32_DWIO_BDP 0x1C
191
192 #define PCNET32_TOTAL_SIZE 0x20
193
194 #define CSR0 0
195 #define CSR0_INIT 0x1
196 #define CSR0_START 0x2
197 #define CSR0_STOP 0x4
198 #define CSR0_TXPOLL 0x8
199 #define CSR0_INTEN 0x40
200 #define CSR0_IDON 0x0100
201 #define CSR0_NORMAL (CSR0_START | CSR0_INTEN)
202 #define PCNET32_INIT_LOW 1
203 #define PCNET32_INIT_HIGH 2
204 #define CSR3 3
205 #define CSR4 4
206 #define CSR5 5
207 #define CSR5_SUSPEND 0x0001
208 #define CSR15 15
209 #define PCNET32_MC_FILTER 8
210
211 #define PCNET32_79C970A 0x2621
212
213 /* The PCNET32 Rx and Tx ring descriptors. */
214 struct pcnet32_rx_head {
215 u32 base;
216 s16 buf_length; /* two`s complement of length */
217 s16 status;
218 u32 msg_length;
219 u32 reserved;
220 };
221
222 struct pcnet32_tx_head {
223 u32 base;
224 s16 length; /* two`s complement of length */
225 s16 status;
226 u32 misc;
227 u32 reserved;
228 };
229
230 /* The PCNET32 32-Bit initialization block, described in databook. */
231 struct pcnet32_init_block {
232 u16 mode;
233 u16 tlen_rlen;
234 u8 phys_addr[6];
235 u16 reserved;
236 u32 filter[2];
237 /* Receive and transmit ring base, along with extra bits. */
238 u32 rx_ring;
239 u32 tx_ring;
240 };
241
242 /* PCnet32 access functions */
243 struct pcnet32_access {
244 u16 (*read_csr) (unsigned long, int);
245 void (*write_csr) (unsigned long, int, u16);
246 u16 (*read_bcr) (unsigned long, int);
247 void (*write_bcr) (unsigned long, int, u16);
248 u16 (*read_rap) (unsigned long);
249 void (*write_rap) (unsigned long, u16);
250 void (*reset) (unsigned long);
251 };
252
253 /*
254 * The first field of pcnet32_private is read by the ethernet device
255 * so the structure should be allocated using pci_alloc_consistent().
256 */
257 struct pcnet32_private {
258 struct pcnet32_init_block init_block;
259 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
260 struct pcnet32_rx_head *rx_ring;
261 struct pcnet32_tx_head *tx_ring;
262 dma_addr_t dma_addr;/* DMA address of beginning of this
263 object, returned by pci_alloc_consistent */
264 struct pci_dev *pci_dev;
265 const char *name;
266 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
267 struct sk_buff **tx_skbuff;
268 struct sk_buff **rx_skbuff;
269 dma_addr_t *tx_dma_addr;
270 dma_addr_t *rx_dma_addr;
271 struct pcnet32_access a;
272 spinlock_t lock; /* Guard lock */
273 unsigned int cur_rx, cur_tx; /* The next free ring entry */
274 unsigned int rx_ring_size; /* current rx ring size */
275 unsigned int tx_ring_size; /* current tx ring size */
276 unsigned int rx_mod_mask; /* rx ring modular mask */
277 unsigned int tx_mod_mask; /* tx ring modular mask */
278 unsigned short rx_len_bits;
279 unsigned short tx_len_bits;
280 dma_addr_t rx_ring_dma_addr;
281 dma_addr_t tx_ring_dma_addr;
282 unsigned int dirty_rx, /* ring entries to be freed. */
283 dirty_tx;
284
285 struct net_device_stats stats;
286 char tx_full;
287 char phycount; /* number of phys found */
288 int options;
289 unsigned int shared_irq:1, /* shared irq possible */
290 dxsuflo:1, /* disable transmit stop on uflo */
291 mii:1; /* mii port available */
292 struct net_device *next;
293 struct mii_if_info mii_if;
294 struct timer_list watchdog_timer;
295 struct timer_list blink_timer;
296 u32 msg_enable; /* debug message level */
297
298 /* each bit indicates an available PHY */
299 u32 phymask;
300 unsigned short chip_version; /* which variant this is */
301 };
302
303 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
304 static int pcnet32_probe1(unsigned long, int, struct pci_dev *);
305 static int pcnet32_open(struct net_device *);
306 static int pcnet32_init_ring(struct net_device *);
307 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
308 static void pcnet32_tx_timeout(struct net_device *dev);
309 static irqreturn_t pcnet32_interrupt(int, void *, struct pt_regs *);
310 static int pcnet32_close(struct net_device *);
311 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
312 static void pcnet32_load_multicast(struct net_device *dev);
313 static void pcnet32_set_multicast_list(struct net_device *);
314 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
315 static void pcnet32_watchdog(struct net_device *);
316 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
317 static void mdio_write(struct net_device *dev, int phy_id, int reg_num,
318 int val);
319 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits);
320 static void pcnet32_ethtool_test(struct net_device *dev,
321 struct ethtool_test *eth_test, u64 * data);
322 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1);
323 static int pcnet32_phys_id(struct net_device *dev, u32 data);
324 static void pcnet32_led_blink_callback(struct net_device *dev);
325 static int pcnet32_get_regs_len(struct net_device *dev);
326 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
327 void *ptr);
328 static void pcnet32_purge_tx_ring(struct net_device *dev);
329 static int pcnet32_alloc_ring(struct net_device *dev, char *name);
330 static void pcnet32_free_ring(struct net_device *dev);
331 static void pcnet32_check_media(struct net_device *dev, int verbose);
332
333 static u16 pcnet32_wio_read_csr(unsigned long addr, int index)
334 {
335 outw(index, addr + PCNET32_WIO_RAP);
336 return inw(addr + PCNET32_WIO_RDP);
337 }
338
339 static void pcnet32_wio_write_csr(unsigned long addr, int index, u16 val)
340 {
341 outw(index, addr + PCNET32_WIO_RAP);
342 outw(val, addr + PCNET32_WIO_RDP);
343 }
344
345 static u16 pcnet32_wio_read_bcr(unsigned long addr, int index)
346 {
347 outw(index, addr + PCNET32_WIO_RAP);
348 return inw(addr + PCNET32_WIO_BDP);
349 }
350
351 static void pcnet32_wio_write_bcr(unsigned long addr, int index, u16 val)
352 {
353 outw(index, addr + PCNET32_WIO_RAP);
354 outw(val, addr + PCNET32_WIO_BDP);
355 }
356
357 static u16 pcnet32_wio_read_rap(unsigned long addr)
358 {
359 return inw(addr + PCNET32_WIO_RAP);
360 }
361
362 static void pcnet32_wio_write_rap(unsigned long addr, u16 val)
363 {
364 outw(val, addr + PCNET32_WIO_RAP);
365 }
366
367 static void pcnet32_wio_reset(unsigned long addr)
368 {
369 inw(addr + PCNET32_WIO_RESET);
370 }
371
372 static int pcnet32_wio_check(unsigned long addr)
373 {
374 outw(88, addr + PCNET32_WIO_RAP);
375 return (inw(addr + PCNET32_WIO_RAP) == 88);
376 }
377
378 static struct pcnet32_access pcnet32_wio = {
379 .read_csr = pcnet32_wio_read_csr,
380 .write_csr = pcnet32_wio_write_csr,
381 .read_bcr = pcnet32_wio_read_bcr,
382 .write_bcr = pcnet32_wio_write_bcr,
383 .read_rap = pcnet32_wio_read_rap,
384 .write_rap = pcnet32_wio_write_rap,
385 .reset = pcnet32_wio_reset
386 };
387
388 static u16 pcnet32_dwio_read_csr(unsigned long addr, int index)
389 {
390 outl(index, addr + PCNET32_DWIO_RAP);
391 return (inl(addr + PCNET32_DWIO_RDP) & 0xffff);
392 }
393
394 static void pcnet32_dwio_write_csr(unsigned long addr, int index, u16 val)
395 {
396 outl(index, addr + PCNET32_DWIO_RAP);
397 outl(val, addr + PCNET32_DWIO_RDP);
398 }
399
400 static u16 pcnet32_dwio_read_bcr(unsigned long addr, int index)
401 {
402 outl(index, addr + PCNET32_DWIO_RAP);
403 return (inl(addr + PCNET32_DWIO_BDP) & 0xffff);
404 }
405
406 static void pcnet32_dwio_write_bcr(unsigned long addr, int index, u16 val)
407 {
408 outl(index, addr + PCNET32_DWIO_RAP);
409 outl(val, addr + PCNET32_DWIO_BDP);
410 }
411
412 static u16 pcnet32_dwio_read_rap(unsigned long addr)
413 {
414 return (inl(addr + PCNET32_DWIO_RAP) & 0xffff);
415 }
416
417 static void pcnet32_dwio_write_rap(unsigned long addr, u16 val)
418 {
419 outl(val, addr + PCNET32_DWIO_RAP);
420 }
421
422 static void pcnet32_dwio_reset(unsigned long addr)
423 {
424 inl(addr + PCNET32_DWIO_RESET);
425 }
426
427 static int pcnet32_dwio_check(unsigned long addr)
428 {
429 outl(88, addr + PCNET32_DWIO_RAP);
430 return ((inl(addr + PCNET32_DWIO_RAP) & 0xffff) == 88);
431 }
432
433 static struct pcnet32_access pcnet32_dwio = {
434 .read_csr = pcnet32_dwio_read_csr,
435 .write_csr = pcnet32_dwio_write_csr,
436 .read_bcr = pcnet32_dwio_read_bcr,
437 .write_bcr = pcnet32_dwio_write_bcr,
438 .read_rap = pcnet32_dwio_read_rap,
439 .write_rap = pcnet32_dwio_write_rap,
440 .reset = pcnet32_dwio_reset
441 };
442
443 static void pcnet32_netif_stop(struct net_device *dev)
444 {
445 dev->trans_start = jiffies;
446 netif_poll_disable(dev);
447 netif_tx_disable(dev);
448 }
449
450 static void pcnet32_netif_start(struct net_device *dev)
451 {
452 netif_wake_queue(dev);
453 netif_poll_enable(dev);
454 }
455
456 /*
457 * Allocate space for the new sized tx ring.
458 * Free old resources
459 * Save new resources.
460 * Any failure keeps old resources.
461 * Must be called with lp->lock held.
462 */
463 static void pcnet32_realloc_tx_ring(struct net_device *dev,
464 struct pcnet32_private *lp,
465 unsigned int size)
466 {
467 dma_addr_t new_ring_dma_addr;
468 dma_addr_t *new_dma_addr_list;
469 struct pcnet32_tx_head *new_tx_ring;
470 struct sk_buff **new_skb_list;
471
472 pcnet32_purge_tx_ring(dev);
473
474 new_tx_ring = pci_alloc_consistent(lp->pci_dev,
475 sizeof(struct pcnet32_tx_head) *
476 (1 << size),
477 &new_ring_dma_addr);
478 if (new_tx_ring == NULL) {
479 if (netif_msg_drv(lp))
480 printk("\n" KERN_ERR
481 "%s: Consistent memory allocation failed.\n",
482 dev->name);
483 return;
484 }
485 memset(new_tx_ring, 0, sizeof(struct pcnet32_tx_head) * (1 << size));
486
487 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
488 GFP_ATOMIC);
489 if (!new_dma_addr_list) {
490 if (netif_msg_drv(lp))
491 printk("\n" KERN_ERR
492 "%s: Memory allocation failed.\n", dev->name);
493 goto free_new_tx_ring;
494 }
495
496 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
497 GFP_ATOMIC);
498 if (!new_skb_list) {
499 if (netif_msg_drv(lp))
500 printk("\n" KERN_ERR
501 "%s: Memory allocation failed.\n", dev->name);
502 goto free_new_lists;
503 }
504
505 kfree(lp->tx_skbuff);
506 kfree(lp->tx_dma_addr);
507 pci_free_consistent(lp->pci_dev,
508 sizeof(struct pcnet32_tx_head) *
509 lp->tx_ring_size, lp->tx_ring,
510 lp->tx_ring_dma_addr);
511
512 lp->tx_ring_size = (1 << size);
513 lp->tx_mod_mask = lp->tx_ring_size - 1;
514 lp->tx_len_bits = (size << 12);
515 lp->tx_ring = new_tx_ring;
516 lp->tx_ring_dma_addr = new_ring_dma_addr;
517 lp->tx_dma_addr = new_dma_addr_list;
518 lp->tx_skbuff = new_skb_list;
519 return;
520
521 free_new_lists:
522 kfree(new_dma_addr_list);
523 free_new_tx_ring:
524 pci_free_consistent(lp->pci_dev,
525 sizeof(struct pcnet32_tx_head) *
526 (1 << size),
527 new_tx_ring,
528 new_ring_dma_addr);
529 return;
530 }
531
532 /*
533 * Allocate space for the new sized rx ring.
534 * Re-use old receive buffers.
535 * alloc extra buffers
536 * free unneeded buffers
537 * free unneeded buffers
538 * Save new resources.
539 * Any failure keeps old resources.
540 * Must be called with lp->lock held.
541 */
542 static void pcnet32_realloc_rx_ring(struct net_device *dev,
543 struct pcnet32_private *lp,
544 unsigned int size)
545 {
546 dma_addr_t new_ring_dma_addr;
547 dma_addr_t *new_dma_addr_list;
548 struct pcnet32_rx_head *new_rx_ring;
549 struct sk_buff **new_skb_list;
550 int new, overlap;
551
552 new_rx_ring = pci_alloc_consistent(lp->pci_dev,
553 sizeof(struct pcnet32_rx_head) *
554 (1 << size),
555 &new_ring_dma_addr);
556 if (new_rx_ring == NULL) {
557 if (netif_msg_drv(lp))
558 printk("\n" KERN_ERR
559 "%s: Consistent memory allocation failed.\n",
560 dev->name);
561 return;
562 }
563 memset(new_rx_ring, 0, sizeof(struct pcnet32_rx_head) * (1 << size));
564
565 new_dma_addr_list = kcalloc((1 << size), sizeof(dma_addr_t),
566 GFP_ATOMIC);
567 if (!new_dma_addr_list) {
568 if (netif_msg_drv(lp))
569 printk("\n" KERN_ERR
570 "%s: Memory allocation failed.\n", dev->name);
571 goto free_new_rx_ring;
572 }
573
574 new_skb_list = kcalloc((1 << size), sizeof(struct sk_buff *),
575 GFP_ATOMIC);
576 if (!new_skb_list) {
577 if (netif_msg_drv(lp))
578 printk("\n" KERN_ERR
579 "%s: Memory allocation failed.\n", dev->name);
580 goto free_new_lists;
581 }
582
583 /* first copy the current receive buffers */
584 overlap = min(size, lp->rx_ring_size);
585 for (new = 0; new < overlap; new++) {
586 new_rx_ring[new] = lp->rx_ring[new];
587 new_dma_addr_list[new] = lp->rx_dma_addr[new];
588 new_skb_list[new] = lp->rx_skbuff[new];
589 }
590 /* now allocate any new buffers needed */
591 for (; new < size; new++ ) {
592 struct sk_buff *rx_skbuff;
593 new_skb_list[new] = dev_alloc_skb(PKT_BUF_SZ);
594 if (!(rx_skbuff = new_skb_list[new])) {
595 /* keep the original lists and buffers */
596 if (netif_msg_drv(lp))
597 printk(KERN_ERR
598 "%s: pcnet32_realloc_rx_ring dev_alloc_skb failed.\n",
599 dev->name);
600 goto free_all_new;
601 }
602 skb_reserve(rx_skbuff, 2);
603
604 new_dma_addr_list[new] =
605 pci_map_single(lp->pci_dev, rx_skbuff->data,
606 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
607 new_rx_ring[new].base = (u32) le32_to_cpu(new_dma_addr_list[new]);
608 new_rx_ring[new].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
609 new_rx_ring[new].status = le16_to_cpu(0x8000);
610 }
611 /* and free any unneeded buffers */
612 for (; new < lp->rx_ring_size; new++) {
613 if (lp->rx_skbuff[new]) {
614 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[new],
615 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
616 dev_kfree_skb(lp->rx_skbuff[new]);
617 }
618 }
619
620 kfree(lp->rx_skbuff);
621 kfree(lp->rx_dma_addr);
622 pci_free_consistent(lp->pci_dev,
623 sizeof(struct pcnet32_rx_head) *
624 lp->rx_ring_size, lp->rx_ring,
625 lp->rx_ring_dma_addr);
626
627 lp->rx_ring_size = (1 << size);
628 lp->rx_mod_mask = lp->rx_ring_size - 1;
629 lp->rx_len_bits = (size << 4);
630 lp->rx_ring = new_rx_ring;
631 lp->rx_ring_dma_addr = new_ring_dma_addr;
632 lp->rx_dma_addr = new_dma_addr_list;
633 lp->rx_skbuff = new_skb_list;
634 return;
635
636 free_all_new:
637 for (; --new >= lp->rx_ring_size; ) {
638 if (new_skb_list[new]) {
639 pci_unmap_single(lp->pci_dev, new_dma_addr_list[new],
640 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
641 dev_kfree_skb(new_skb_list[new]);
642 }
643 }
644 kfree(new_skb_list);
645 free_new_lists:
646 kfree(new_dma_addr_list);
647 free_new_rx_ring:
648 pci_free_consistent(lp->pci_dev,
649 sizeof(struct pcnet32_rx_head) *
650 (1 << size),
651 new_rx_ring,
652 new_ring_dma_addr);
653 return;
654 }
655
656 static void pcnet32_purge_rx_ring(struct net_device *dev)
657 {
658 struct pcnet32_private *lp = dev->priv;
659 int i;
660
661 /* free all allocated skbuffs */
662 for (i = 0; i < lp->rx_ring_size; i++) {
663 lp->rx_ring[i].status = 0; /* CPU owns buffer */
664 wmb(); /* Make sure adapter sees owner change */
665 if (lp->rx_skbuff[i]) {
666 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i],
667 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
668 dev_kfree_skb_any(lp->rx_skbuff[i]);
669 }
670 lp->rx_skbuff[i] = NULL;
671 lp->rx_dma_addr[i] = 0;
672 }
673 }
674
675 #ifdef CONFIG_NET_POLL_CONTROLLER
676 static void pcnet32_poll_controller(struct net_device *dev)
677 {
678 disable_irq(dev->irq);
679 pcnet32_interrupt(0, dev, NULL);
680 enable_irq(dev->irq);
681 }
682 #endif
683
684 static int pcnet32_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
685 {
686 struct pcnet32_private *lp = dev->priv;
687 unsigned long flags;
688 int r = -EOPNOTSUPP;
689
690 if (lp->mii) {
691 spin_lock_irqsave(&lp->lock, flags);
692 mii_ethtool_gset(&lp->mii_if, cmd);
693 spin_unlock_irqrestore(&lp->lock, flags);
694 r = 0;
695 }
696 return r;
697 }
698
699 static int pcnet32_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
700 {
701 struct pcnet32_private *lp = dev->priv;
702 unsigned long flags;
703 int r = -EOPNOTSUPP;
704
705 if (lp->mii) {
706 spin_lock_irqsave(&lp->lock, flags);
707 r = mii_ethtool_sset(&lp->mii_if, cmd);
708 spin_unlock_irqrestore(&lp->lock, flags);
709 }
710 return r;
711 }
712
713 static void pcnet32_get_drvinfo(struct net_device *dev,
714 struct ethtool_drvinfo *info)
715 {
716 struct pcnet32_private *lp = dev->priv;
717
718 strcpy(info->driver, DRV_NAME);
719 strcpy(info->version, DRV_VERSION);
720 if (lp->pci_dev)
721 strcpy(info->bus_info, pci_name(lp->pci_dev));
722 else
723 sprintf(info->bus_info, "VLB 0x%lx", dev->base_addr);
724 }
725
726 static u32 pcnet32_get_link(struct net_device *dev)
727 {
728 struct pcnet32_private *lp = dev->priv;
729 unsigned long flags;
730 int r;
731
732 spin_lock_irqsave(&lp->lock, flags);
733 if (lp->mii) {
734 r = mii_link_ok(&lp->mii_if);
735 } else if (lp->chip_version >= PCNET32_79C970A) {
736 ulong ioaddr = dev->base_addr; /* card base I/O address */
737 r = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
738 } else { /* can not detect link on really old chips */
739 r = 1;
740 }
741 spin_unlock_irqrestore(&lp->lock, flags);
742
743 return r;
744 }
745
746 static u32 pcnet32_get_msglevel(struct net_device *dev)
747 {
748 struct pcnet32_private *lp = dev->priv;
749 return lp->msg_enable;
750 }
751
752 static void pcnet32_set_msglevel(struct net_device *dev, u32 value)
753 {
754 struct pcnet32_private *lp = dev->priv;
755 lp->msg_enable = value;
756 }
757
758 static int pcnet32_nway_reset(struct net_device *dev)
759 {
760 struct pcnet32_private *lp = dev->priv;
761 unsigned long flags;
762 int r = -EOPNOTSUPP;
763
764 if (lp->mii) {
765 spin_lock_irqsave(&lp->lock, flags);
766 r = mii_nway_restart(&lp->mii_if);
767 spin_unlock_irqrestore(&lp->lock, flags);
768 }
769 return r;
770 }
771
772 static void pcnet32_get_ringparam(struct net_device *dev,
773 struct ethtool_ringparam *ering)
774 {
775 struct pcnet32_private *lp = dev->priv;
776
777 ering->tx_max_pending = TX_MAX_RING_SIZE;
778 ering->tx_pending = lp->tx_ring_size;
779 ering->rx_max_pending = RX_MAX_RING_SIZE;
780 ering->rx_pending = lp->rx_ring_size;
781 }
782
783 static int pcnet32_set_ringparam(struct net_device *dev,
784 struct ethtool_ringparam *ering)
785 {
786 struct pcnet32_private *lp = dev->priv;
787 unsigned long flags;
788 unsigned int size;
789 ulong ioaddr = dev->base_addr;
790 int i;
791
792 if (ering->rx_mini_pending || ering->rx_jumbo_pending)
793 return -EINVAL;
794
795 if (netif_running(dev))
796 pcnet32_netif_stop(dev);
797
798 spin_lock_irqsave(&lp->lock, flags);
799 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
800
801 size = min(ering->tx_pending, (unsigned int)TX_MAX_RING_SIZE);
802
803 /* set the minimum ring size to 4, to allow the loopback test to work
804 * unchanged.
805 */
806 for (i = 2; i <= PCNET32_LOG_MAX_TX_BUFFERS; i++) {
807 if (size <= (1 << i))
808 break;
809 }
810 if ((1 << i) != lp->tx_ring_size)
811 pcnet32_realloc_tx_ring(dev, lp, i);
812
813 size = min(ering->rx_pending, (unsigned int)RX_MAX_RING_SIZE);
814 for (i = 2; i <= PCNET32_LOG_MAX_RX_BUFFERS; i++) {
815 if (size <= (1 << i))
816 break;
817 }
818 if ((1 << i) != lp->rx_ring_size)
819 pcnet32_realloc_rx_ring(dev, lp, i);
820
821 dev->weight = lp->rx_ring_size / 2;
822
823 if (netif_running(dev)) {
824 pcnet32_netif_start(dev);
825 pcnet32_restart(dev, CSR0_NORMAL);
826 }
827
828 spin_unlock_irqrestore(&lp->lock, flags);
829
830 if (netif_msg_drv(lp))
831 printk(KERN_INFO
832 "%s: Ring Param Settings: RX: %d, TX: %d\n", dev->name,
833 lp->rx_ring_size, lp->tx_ring_size);
834
835 return 0;
836 }
837
838 static void pcnet32_get_strings(struct net_device *dev, u32 stringset,
839 u8 * data)
840 {
841 memcpy(data, pcnet32_gstrings_test, sizeof(pcnet32_gstrings_test));
842 }
843
844 static int pcnet32_self_test_count(struct net_device *dev)
845 {
846 return PCNET32_TEST_LEN;
847 }
848
849 static void pcnet32_ethtool_test(struct net_device *dev,
850 struct ethtool_test *test, u64 * data)
851 {
852 struct pcnet32_private *lp = dev->priv;
853 int rc;
854
855 if (test->flags == ETH_TEST_FL_OFFLINE) {
856 rc = pcnet32_loopback_test(dev, data);
857 if (rc) {
858 if (netif_msg_hw(lp))
859 printk(KERN_DEBUG "%s: Loopback test failed.\n",
860 dev->name);
861 test->flags |= ETH_TEST_FL_FAILED;
862 } else if (netif_msg_hw(lp))
863 printk(KERN_DEBUG "%s: Loopback test passed.\n",
864 dev->name);
865 } else if (netif_msg_hw(lp))
866 printk(KERN_DEBUG
867 "%s: No tests to run (specify 'Offline' on ethtool).",
868 dev->name);
869 } /* end pcnet32_ethtool_test */
870
871 static int pcnet32_loopback_test(struct net_device *dev, uint64_t * data1)
872 {
873 struct pcnet32_private *lp = dev->priv;
874 struct pcnet32_access *a = &lp->a; /* access to registers */
875 ulong ioaddr = dev->base_addr; /* card base I/O address */
876 struct sk_buff *skb; /* sk buff */
877 int x, i; /* counters */
878 int numbuffs = 4; /* number of TX/RX buffers and descs */
879 u16 status = 0x8300; /* TX ring status */
880 u16 teststatus; /* test of ring status */
881 int rc; /* return code */
882 int size; /* size of packets */
883 unsigned char *packet; /* source packet data */
884 static const int data_len = 60; /* length of source packets */
885 unsigned long flags;
886 unsigned long ticks;
887
888 rc = 1; /* default to fail */
889
890 if (netif_running(dev))
891 #ifdef CONFIG_PCNET32_NAPI
892 pcnet32_netif_stop(dev);
893 #else
894 pcnet32_close(dev);
895 #endif
896
897 spin_lock_irqsave(&lp->lock, flags);
898 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* stop the chip */
899
900 numbuffs = min(numbuffs, (int)min(lp->rx_ring_size, lp->tx_ring_size));
901
902 /* Reset the PCNET32 */
903 lp->a.reset(ioaddr);
904 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
905
906 /* switch pcnet32 to 32bit mode */
907 lp->a.write_bcr(ioaddr, 20, 2);
908
909 /* purge & init rings but don't actually restart */
910 pcnet32_restart(dev, 0x0000);
911
912 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
913
914 /* Initialize Transmit buffers. */
915 size = data_len + 15;
916 for (x = 0; x < numbuffs; x++) {
917 if (!(skb = dev_alloc_skb(size))) {
918 if (netif_msg_hw(lp))
919 printk(KERN_DEBUG
920 "%s: Cannot allocate skb at line: %d!\n",
921 dev->name, __LINE__);
922 goto clean_up;
923 } else {
924 packet = skb->data;
925 skb_put(skb, size); /* create space for data */
926 lp->tx_skbuff[x] = skb;
927 lp->tx_ring[x].length = le16_to_cpu(-skb->len);
928 lp->tx_ring[x].misc = 0;
929
930 /* put DA and SA into the skb */
931 for (i = 0; i < 6; i++)
932 *packet++ = dev->dev_addr[i];
933 for (i = 0; i < 6; i++)
934 *packet++ = dev->dev_addr[i];
935 /* type */
936 *packet++ = 0x08;
937 *packet++ = 0x06;
938 /* packet number */
939 *packet++ = x;
940 /* fill packet with data */
941 for (i = 0; i < data_len; i++)
942 *packet++ = i;
943
944 lp->tx_dma_addr[x] =
945 pci_map_single(lp->pci_dev, skb->data, skb->len,
946 PCI_DMA_TODEVICE);
947 lp->tx_ring[x].base =
948 (u32) le32_to_cpu(lp->tx_dma_addr[x]);
949 wmb(); /* Make sure owner changes after all others are visible */
950 lp->tx_ring[x].status = le16_to_cpu(status);
951 }
952 }
953
954 x = a->read_bcr(ioaddr, 32); /* set internal loopback in BCR32 */
955 a->write_bcr(ioaddr, 32, x | 0x0002);
956
957 /* set int loopback in CSR15 */
958 x = a->read_csr(ioaddr, CSR15) & 0xfffc;
959 lp->a.write_csr(ioaddr, CSR15, x | 0x0044);
960
961 teststatus = le16_to_cpu(0x8000);
962 lp->a.write_csr(ioaddr, CSR0, CSR0_START); /* Set STRT bit */
963
964 /* Check status of descriptors */
965 for (x = 0; x < numbuffs; x++) {
966 ticks = 0;
967 rmb();
968 while ((lp->rx_ring[x].status & teststatus) && (ticks < 200)) {
969 spin_unlock_irqrestore(&lp->lock, flags);
970 msleep(1);
971 spin_lock_irqsave(&lp->lock, flags);
972 rmb();
973 ticks++;
974 }
975 if (ticks == 200) {
976 if (netif_msg_hw(lp))
977 printk("%s: Desc %d failed to reset!\n",
978 dev->name, x);
979 break;
980 }
981 }
982
983 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP); /* Set STOP bit */
984 wmb();
985 if (netif_msg_hw(lp) && netif_msg_pktdata(lp)) {
986 printk(KERN_DEBUG "%s: RX loopback packets:\n", dev->name);
987
988 for (x = 0; x < numbuffs; x++) {
989 printk(KERN_DEBUG "%s: Packet %d:\n", dev->name, x);
990 skb = lp->rx_skbuff[x];
991 for (i = 0; i < size; i++) {
992 printk("%02x ", *(skb->data + i));
993 }
994 printk("\n");
995 }
996 }
997
998 x = 0;
999 rc = 0;
1000 while (x < numbuffs && !rc) {
1001 skb = lp->rx_skbuff[x];
1002 packet = lp->tx_skbuff[x]->data;
1003 for (i = 0; i < size; i++) {
1004 if (*(skb->data + i) != packet[i]) {
1005 if (netif_msg_hw(lp))
1006 printk(KERN_DEBUG
1007 "%s: Error in compare! %2x - %02x %02x\n",
1008 dev->name, i, *(skb->data + i),
1009 packet[i]);
1010 rc = 1;
1011 break;
1012 }
1013 }
1014 x++;
1015 }
1016
1017 clean_up:
1018 *data1 = rc;
1019 pcnet32_purge_tx_ring(dev);
1020
1021 x = a->read_csr(ioaddr, CSR15);
1022 a->write_csr(ioaddr, CSR15, (x & ~0x0044)); /* reset bits 6 and 2 */
1023
1024 x = a->read_bcr(ioaddr, 32); /* reset internal loopback */
1025 a->write_bcr(ioaddr, 32, (x & ~0x0002));
1026
1027 #ifdef CONFIG_PCNET32_NAPI
1028 if (netif_running(dev)) {
1029 pcnet32_netif_start(dev);
1030 pcnet32_restart(dev, CSR0_NORMAL);
1031 } else {
1032 pcnet32_purge_rx_ring(dev);
1033 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1034 }
1035 spin_unlock_irqrestore(&lp->lock, flags);
1036 #else
1037 if (netif_running(dev)) {
1038 spin_unlock_irqrestore(&lp->lock, flags);
1039 pcnet32_open(dev);
1040 } else {
1041 pcnet32_purge_rx_ring(dev);
1042 lp->a.write_bcr(ioaddr, 20, 4); /* return to 16bit mode */
1043 spin_unlock_irqrestore(&lp->lock, flags);
1044 }
1045 #endif
1046
1047 return (rc);
1048 } /* end pcnet32_loopback_test */
1049
1050 static void pcnet32_led_blink_callback(struct net_device *dev)
1051 {
1052 struct pcnet32_private *lp = dev->priv;
1053 struct pcnet32_access *a = &lp->a;
1054 ulong ioaddr = dev->base_addr;
1055 unsigned long flags;
1056 int i;
1057
1058 spin_lock_irqsave(&lp->lock, flags);
1059 for (i = 4; i < 8; i++) {
1060 a->write_bcr(ioaddr, i, a->read_bcr(ioaddr, i) ^ 0x4000);
1061 }
1062 spin_unlock_irqrestore(&lp->lock, flags);
1063
1064 mod_timer(&lp->blink_timer, PCNET32_BLINK_TIMEOUT);
1065 }
1066
1067 static int pcnet32_phys_id(struct net_device *dev, u32 data)
1068 {
1069 struct pcnet32_private *lp = dev->priv;
1070 struct pcnet32_access *a = &lp->a;
1071 ulong ioaddr = dev->base_addr;
1072 unsigned long flags;
1073 int i, regs[4];
1074
1075 if (!lp->blink_timer.function) {
1076 init_timer(&lp->blink_timer);
1077 lp->blink_timer.function = (void *)pcnet32_led_blink_callback;
1078 lp->blink_timer.data = (unsigned long)dev;
1079 }
1080
1081 /* Save the current value of the bcrs */
1082 spin_lock_irqsave(&lp->lock, flags);
1083 for (i = 4; i < 8; i++) {
1084 regs[i - 4] = a->read_bcr(ioaddr, i);
1085 }
1086 spin_unlock_irqrestore(&lp->lock, flags);
1087
1088 mod_timer(&lp->blink_timer, jiffies);
1089 set_current_state(TASK_INTERRUPTIBLE);
1090
1091 if ((!data) || (data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ)))
1092 data = (u32) (MAX_SCHEDULE_TIMEOUT / HZ);
1093
1094 msleep_interruptible(data * 1000);
1095 del_timer_sync(&lp->blink_timer);
1096
1097 /* Restore the original value of the bcrs */
1098 spin_lock_irqsave(&lp->lock, flags);
1099 for (i = 4; i < 8; i++) {
1100 a->write_bcr(ioaddr, i, regs[i - 4]);
1101 }
1102 spin_unlock_irqrestore(&lp->lock, flags);
1103
1104 return 0;
1105 }
1106
1107 /*
1108 * lp->lock must be held.
1109 */
1110 static int pcnet32_suspend(struct net_device *dev, unsigned long *flags,
1111 int can_sleep)
1112 {
1113 int csr5;
1114 struct pcnet32_private *lp = dev->priv;
1115 struct pcnet32_access *a = &lp->a;
1116 ulong ioaddr = dev->base_addr;
1117 int ticks;
1118
1119 /* really old chips have to be stopped. */
1120 if (lp->chip_version < PCNET32_79C970A)
1121 return 0;
1122
1123 /* set SUSPEND (SPND) - CSR5 bit 0 */
1124 csr5 = a->read_csr(ioaddr, CSR5);
1125 a->write_csr(ioaddr, CSR5, csr5 | CSR5_SUSPEND);
1126
1127 /* poll waiting for bit to be set */
1128 ticks = 0;
1129 while (!(a->read_csr(ioaddr, CSR5) & CSR5_SUSPEND)) {
1130 spin_unlock_irqrestore(&lp->lock, *flags);
1131 if (can_sleep)
1132 msleep(1);
1133 else
1134 mdelay(1);
1135 spin_lock_irqsave(&lp->lock, *flags);
1136 ticks++;
1137 if (ticks > 200) {
1138 if (netif_msg_hw(lp))
1139 printk(KERN_DEBUG
1140 "%s: Error getting into suspend!\n",
1141 dev->name);
1142 return 0;
1143 }
1144 }
1145 return 1;
1146 }
1147
1148 /*
1149 * process one receive descriptor entry
1150 */
1151
1152 static void pcnet32_rx_entry(struct net_device *dev,
1153 struct pcnet32_private *lp,
1154 struct pcnet32_rx_head *rxp,
1155 int entry)
1156 {
1157 int status = (short)le16_to_cpu(rxp->status) >> 8;
1158 int rx_in_place = 0;
1159 struct sk_buff *skb;
1160 short pkt_len;
1161
1162 if (status != 0x03) { /* There was an error. */
1163 /*
1164 * There is a tricky error noted by John Murphy,
1165 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1166 * buffers it's possible for a jabber packet to use two
1167 * buffers, with only the last correctly noting the error.
1168 */
1169 if (status & 0x01) /* Only count a general error at the */
1170 lp->stats.rx_errors++; /* end of a packet. */
1171 if (status & 0x20)
1172 lp->stats.rx_frame_errors++;
1173 if (status & 0x10)
1174 lp->stats.rx_over_errors++;
1175 if (status & 0x08)
1176 lp->stats.rx_crc_errors++;
1177 if (status & 0x04)
1178 lp->stats.rx_fifo_errors++;
1179 return;
1180 }
1181
1182 pkt_len = (le32_to_cpu(rxp->msg_length) & 0xfff) - 4;
1183
1184 /* Discard oversize frames. */
1185 if (unlikely(pkt_len > PKT_BUF_SZ - 2)) {
1186 if (netif_msg_drv(lp))
1187 printk(KERN_ERR "%s: Impossible packet size %d!\n",
1188 dev->name, pkt_len);
1189 lp->stats.rx_errors++;
1190 return;
1191 }
1192 if (pkt_len < 60) {
1193 if (netif_msg_rx_err(lp))
1194 printk(KERN_ERR "%s: Runt packet!\n", dev->name);
1195 lp->stats.rx_errors++;
1196 return;
1197 }
1198
1199 if (pkt_len > rx_copybreak) {
1200 struct sk_buff *newskb;
1201
1202 if ((newskb = dev_alloc_skb(PKT_BUF_SZ))) {
1203 skb_reserve(newskb, 2);
1204 skb = lp->rx_skbuff[entry];
1205 pci_unmap_single(lp->pci_dev,
1206 lp->rx_dma_addr[entry],
1207 PKT_BUF_SZ - 2,
1208 PCI_DMA_FROMDEVICE);
1209 skb_put(skb, pkt_len);
1210 lp->rx_skbuff[entry] = newskb;
1211 newskb->dev = dev;
1212 lp->rx_dma_addr[entry] =
1213 pci_map_single(lp->pci_dev,
1214 newskb->data,
1215 PKT_BUF_SZ - 2,
1216 PCI_DMA_FROMDEVICE);
1217 rxp->base = le32_to_cpu(lp->rx_dma_addr[entry]);
1218 rx_in_place = 1;
1219 } else
1220 skb = NULL;
1221 } else {
1222 skb = dev_alloc_skb(pkt_len + 2);
1223 }
1224
1225 if (skb == NULL) {
1226 if (netif_msg_drv(lp))
1227 printk(KERN_ERR
1228 "%s: Memory squeeze, dropping packet.\n",
1229 dev->name);
1230 lp->stats.rx_dropped++;
1231 return;
1232 }
1233 skb->dev = dev;
1234 if (!rx_in_place) {
1235 skb_reserve(skb, 2); /* 16 byte align */
1236 skb_put(skb, pkt_len); /* Make room */
1237 pci_dma_sync_single_for_cpu(lp->pci_dev,
1238 lp->rx_dma_addr[entry],
1239 PKT_BUF_SZ - 2,
1240 PCI_DMA_FROMDEVICE);
1241 eth_copy_and_sum(skb,
1242 (unsigned char *)(lp->rx_skbuff[entry]->data),
1243 pkt_len, 0);
1244 pci_dma_sync_single_for_device(lp->pci_dev,
1245 lp->rx_dma_addr[entry],
1246 PKT_BUF_SZ - 2,
1247 PCI_DMA_FROMDEVICE);
1248 }
1249 lp->stats.rx_bytes += skb->len;
1250 skb->protocol = eth_type_trans(skb, dev);
1251 #ifdef CONFIG_PCNET32_NAPI
1252 netif_receive_skb(skb);
1253 #else
1254 netif_rx(skb);
1255 #endif
1256 dev->last_rx = jiffies;
1257 lp->stats.rx_packets++;
1258 return;
1259 }
1260
1261 static int pcnet32_rx(struct net_device *dev, int quota)
1262 {
1263 struct pcnet32_private *lp = dev->priv;
1264 int entry = lp->cur_rx & lp->rx_mod_mask;
1265 struct pcnet32_rx_head *rxp = &lp->rx_ring[entry];
1266 int npackets = 0;
1267
1268 /* If we own the next entry, it's a new packet. Send it up. */
1269 while (quota > npackets && (short)le16_to_cpu(rxp->status) >= 0) {
1270 pcnet32_rx_entry(dev, lp, rxp, entry);
1271 npackets += 1;
1272 /*
1273 * The docs say that the buffer length isn't touched, but Andrew
1274 * Boyd of QNX reports that some revs of the 79C965 clear it.
1275 */
1276 rxp->buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
1277 wmb(); /* Make sure owner changes after others are visible */
1278 rxp->status = le16_to_cpu(0x8000);
1279 entry = (++lp->cur_rx) & lp->rx_mod_mask;
1280 rxp = &lp->rx_ring[entry];
1281 }
1282
1283 return npackets;
1284 }
1285
1286 static int pcnet32_tx(struct net_device *dev)
1287 {
1288 struct pcnet32_private *lp = dev->priv;
1289 unsigned int dirty_tx = lp->dirty_tx;
1290 int delta;
1291 int must_restart = 0;
1292
1293 while (dirty_tx != lp->cur_tx) {
1294 int entry = dirty_tx & lp->tx_mod_mask;
1295 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1296
1297 if (status < 0)
1298 break; /* It still hasn't been Txed */
1299
1300 lp->tx_ring[entry].base = 0;
1301
1302 if (status & 0x4000) {
1303 /* There was a major error, log it. */
1304 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1305 lp->stats.tx_errors++;
1306 if (netif_msg_tx_err(lp))
1307 printk(KERN_ERR
1308 "%s: Tx error status=%04x err_status=%08x\n",
1309 dev->name, status,
1310 err_status);
1311 if (err_status & 0x04000000)
1312 lp->stats.tx_aborted_errors++;
1313 if (err_status & 0x08000000)
1314 lp->stats.tx_carrier_errors++;
1315 if (err_status & 0x10000000)
1316 lp->stats.tx_window_errors++;
1317 #ifndef DO_DXSUFLO
1318 if (err_status & 0x40000000) {
1319 lp->stats.tx_fifo_errors++;
1320 /* Ackk! On FIFO errors the Tx unit is turned off! */
1321 /* Remove this verbosity later! */
1322 if (netif_msg_tx_err(lp))
1323 printk(KERN_ERR
1324 "%s: Tx FIFO error!\n",
1325 dev->name);
1326 must_restart = 1;
1327 }
1328 #else
1329 if (err_status & 0x40000000) {
1330 lp->stats.tx_fifo_errors++;
1331 if (!lp->dxsuflo) { /* If controller doesn't recover ... */
1332 /* Ackk! On FIFO errors the Tx unit is turned off! */
1333 /* Remove this verbosity later! */
1334 if (netif_msg_tx_err(lp))
1335 printk(KERN_ERR
1336 "%s: Tx FIFO error!\n",
1337 dev->name);
1338 must_restart = 1;
1339 }
1340 }
1341 #endif
1342 } else {
1343 if (status & 0x1800)
1344 lp->stats.collisions++;
1345 lp->stats.tx_packets++;
1346 }
1347
1348 /* We must free the original skb */
1349 if (lp->tx_skbuff[entry]) {
1350 pci_unmap_single(lp->pci_dev,
1351 lp->tx_dma_addr[entry],
1352 lp->tx_skbuff[entry]->
1353 len, PCI_DMA_TODEVICE);
1354 dev_kfree_skb_any(lp->tx_skbuff[entry]);
1355 lp->tx_skbuff[entry] = NULL;
1356 lp->tx_dma_addr[entry] = 0;
1357 }
1358 dirty_tx++;
1359 }
1360
1361 delta = (lp->cur_tx - dirty_tx) & (lp->tx_mod_mask + lp->tx_ring_size);
1362 if (delta > lp->tx_ring_size) {
1363 if (netif_msg_drv(lp))
1364 printk(KERN_ERR
1365 "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1366 dev->name, dirty_tx, lp->cur_tx,
1367 lp->tx_full);
1368 dirty_tx += lp->tx_ring_size;
1369 delta -= lp->tx_ring_size;
1370 }
1371
1372 if (lp->tx_full &&
1373 netif_queue_stopped(dev) &&
1374 delta < lp->tx_ring_size - 2) {
1375 /* The ring is no longer full, clear tbusy. */
1376 lp->tx_full = 0;
1377 netif_wake_queue(dev);
1378 }
1379 lp->dirty_tx = dirty_tx;
1380
1381 return must_restart;
1382 }
1383
1384 #ifdef CONFIG_PCNET32_NAPI
1385 static int pcnet32_poll(struct net_device *dev, int *budget)
1386 {
1387 struct pcnet32_private *lp = dev->priv;
1388 int quota = min(dev->quota, *budget);
1389 unsigned long ioaddr = dev->base_addr;
1390 unsigned long flags;
1391 u16 val;
1392
1393 quota = pcnet32_rx(dev, quota);
1394
1395 spin_lock_irqsave(&lp->lock, flags);
1396 if (pcnet32_tx(dev)) {
1397 /* reset the chip to clear the error condition, then restart */
1398 lp->a.reset(ioaddr);
1399 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
1400 pcnet32_restart(dev, CSR0_START);
1401 netif_wake_queue(dev);
1402 }
1403 spin_unlock_irqrestore(&lp->lock, flags);
1404
1405 *budget -= quota;
1406 dev->quota -= quota;
1407
1408 if (dev->quota == 0) {
1409 return 1;
1410 }
1411
1412 netif_rx_complete(dev);
1413
1414 spin_lock_irqsave(&lp->lock, flags);
1415
1416 /* clear interrupt masks */
1417 val = lp->a.read_csr(ioaddr, CSR3);
1418 val &= 0x00ff;
1419 lp->a.write_csr(ioaddr, CSR3, val);
1420
1421 /* Set interrupt enable. */
1422 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
1423 mmiowb();
1424 spin_unlock_irqrestore(&lp->lock, flags);
1425
1426 return 0;
1427 }
1428 #endif
1429
1430 #define PCNET32_REGS_PER_PHY 32
1431 #define PCNET32_MAX_PHYS 32
1432 static int pcnet32_get_regs_len(struct net_device *dev)
1433 {
1434 struct pcnet32_private *lp = dev->priv;
1435 int j = lp->phycount * PCNET32_REGS_PER_PHY;
1436
1437 return ((PCNET32_NUM_REGS + j) * sizeof(u16));
1438 }
1439
1440 static void pcnet32_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1441 void *ptr)
1442 {
1443 int i, csr0;
1444 u16 *buff = ptr;
1445 struct pcnet32_private *lp = dev->priv;
1446 struct pcnet32_access *a = &lp->a;
1447 ulong ioaddr = dev->base_addr;
1448 unsigned long flags;
1449
1450 spin_lock_irqsave(&lp->lock, flags);
1451
1452 csr0 = a->read_csr(ioaddr, CSR0);
1453 if (!(csr0 & CSR0_STOP)) /* If not stopped */
1454 pcnet32_suspend(dev, &flags, 1);
1455
1456 /* read address PROM */
1457 for (i = 0; i < 16; i += 2)
1458 *buff++ = inw(ioaddr + i);
1459
1460 /* read control and status registers */
1461 for (i = 0; i < 90; i++) {
1462 *buff++ = a->read_csr(ioaddr, i);
1463 }
1464
1465 *buff++ = a->read_csr(ioaddr, 112);
1466 *buff++ = a->read_csr(ioaddr, 114);
1467
1468 /* read bus configuration registers */
1469 for (i = 0; i < 30; i++) {
1470 *buff++ = a->read_bcr(ioaddr, i);
1471 }
1472 *buff++ = 0; /* skip bcr30 so as not to hang 79C976 */
1473 for (i = 31; i < 36; i++) {
1474 *buff++ = a->read_bcr(ioaddr, i);
1475 }
1476
1477 /* read mii phy registers */
1478 if (lp->mii) {
1479 int j;
1480 for (j = 0; j < PCNET32_MAX_PHYS; j++) {
1481 if (lp->phymask & (1 << j)) {
1482 for (i = 0; i < PCNET32_REGS_PER_PHY; i++) {
1483 lp->a.write_bcr(ioaddr, 33,
1484 (j << 5) | i);
1485 *buff++ = lp->a.read_bcr(ioaddr, 34);
1486 }
1487 }
1488 }
1489 }
1490
1491 if (!(csr0 & CSR0_STOP)) { /* If not stopped */
1492 int csr5;
1493
1494 /* clear SUSPEND (SPND) - CSR5 bit 0 */
1495 csr5 = a->read_csr(ioaddr, CSR5);
1496 a->write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
1497 }
1498
1499 spin_unlock_irqrestore(&lp->lock, flags);
1500 }
1501
1502 static const struct ethtool_ops pcnet32_ethtool_ops = {
1503 .get_settings = pcnet32_get_settings,
1504 .set_settings = pcnet32_set_settings,
1505 .get_drvinfo = pcnet32_get_drvinfo,
1506 .get_msglevel = pcnet32_get_msglevel,
1507 .set_msglevel = pcnet32_set_msglevel,
1508 .nway_reset = pcnet32_nway_reset,
1509 .get_link = pcnet32_get_link,
1510 .get_ringparam = pcnet32_get_ringparam,
1511 .set_ringparam = pcnet32_set_ringparam,
1512 .get_tx_csum = ethtool_op_get_tx_csum,
1513 .get_sg = ethtool_op_get_sg,
1514 .get_tso = ethtool_op_get_tso,
1515 .get_strings = pcnet32_get_strings,
1516 .self_test_count = pcnet32_self_test_count,
1517 .self_test = pcnet32_ethtool_test,
1518 .phys_id = pcnet32_phys_id,
1519 .get_regs_len = pcnet32_get_regs_len,
1520 .get_regs = pcnet32_get_regs,
1521 .get_perm_addr = ethtool_op_get_perm_addr,
1522 };
1523
1524 /* only probes for non-PCI devices, the rest are handled by
1525 * pci_register_driver via pcnet32_probe_pci */
1526
1527 static void __devinit pcnet32_probe_vlbus(unsigned int *pcnet32_portlist)
1528 {
1529 unsigned int *port, ioaddr;
1530
1531 /* search for PCnet32 VLB cards at known addresses */
1532 for (port = pcnet32_portlist; (ioaddr = *port); port++) {
1533 if (request_region
1534 (ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_vlbus")) {
1535 /* check if there is really a pcnet chip on that ioaddr */
1536 if ((inb(ioaddr + 14) == 0x57)
1537 && (inb(ioaddr + 15) == 0x57)) {
1538 pcnet32_probe1(ioaddr, 0, NULL);
1539 } else {
1540 release_region(ioaddr, PCNET32_TOTAL_SIZE);
1541 }
1542 }
1543 }
1544 }
1545
1546 static int __devinit
1547 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
1548 {
1549 unsigned long ioaddr;
1550 int err;
1551
1552 err = pci_enable_device(pdev);
1553 if (err < 0) {
1554 if (pcnet32_debug & NETIF_MSG_PROBE)
1555 printk(KERN_ERR PFX
1556 "failed to enable device -- err=%d\n", err);
1557 return err;
1558 }
1559 pci_set_master(pdev);
1560
1561 ioaddr = pci_resource_start(pdev, 0);
1562 if (!ioaddr) {
1563 if (pcnet32_debug & NETIF_MSG_PROBE)
1564 printk(KERN_ERR PFX
1565 "card has no PCI IO resources, aborting\n");
1566 return -ENODEV;
1567 }
1568
1569 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
1570 if (pcnet32_debug & NETIF_MSG_PROBE)
1571 printk(KERN_ERR PFX
1572 "architecture does not support 32bit PCI busmaster DMA\n");
1573 return -ENODEV;
1574 }
1575 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, "pcnet32_probe_pci") ==
1576 NULL) {
1577 if (pcnet32_debug & NETIF_MSG_PROBE)
1578 printk(KERN_ERR PFX
1579 "io address range already allocated\n");
1580 return -EBUSY;
1581 }
1582
1583 err = pcnet32_probe1(ioaddr, 1, pdev);
1584 if (err < 0) {
1585 pci_disable_device(pdev);
1586 }
1587 return err;
1588 }
1589
1590 /* pcnet32_probe1
1591 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
1592 * pdev will be NULL when called from pcnet32_probe_vlbus.
1593 */
1594 static int __devinit
1595 pcnet32_probe1(unsigned long ioaddr, int shared, struct pci_dev *pdev)
1596 {
1597 struct pcnet32_private *lp;
1598 dma_addr_t lp_dma_addr;
1599 int i, media;
1600 int fdx, mii, fset, dxsuflo;
1601 int chip_version;
1602 char *chipname;
1603 struct net_device *dev;
1604 struct pcnet32_access *a = NULL;
1605 u8 promaddr[6];
1606 int ret = -ENODEV;
1607
1608 /* reset the chip */
1609 pcnet32_wio_reset(ioaddr);
1610
1611 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
1612 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
1613 a = &pcnet32_wio;
1614 } else {
1615 pcnet32_dwio_reset(ioaddr);
1616 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4
1617 && pcnet32_dwio_check(ioaddr)) {
1618 a = &pcnet32_dwio;
1619 } else
1620 goto err_release_region;
1621 }
1622
1623 chip_version =
1624 a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr, 89) << 16);
1625 if ((pcnet32_debug & NETIF_MSG_PROBE) && (pcnet32_debug & NETIF_MSG_HW))
1626 printk(KERN_INFO " PCnet chip version is %#x.\n",
1627 chip_version);
1628 if ((chip_version & 0xfff) != 0x003) {
1629 if (pcnet32_debug & NETIF_MSG_PROBE)
1630 printk(KERN_INFO PFX "Unsupported chip version.\n");
1631 goto err_release_region;
1632 }
1633
1634 /* initialize variables */
1635 fdx = mii = fset = dxsuflo = 0;
1636 chip_version = (chip_version >> 12) & 0xffff;
1637
1638 switch (chip_version) {
1639 case 0x2420:
1640 chipname = "PCnet/PCI 79C970"; /* PCI */
1641 break;
1642 case 0x2430:
1643 if (shared)
1644 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
1645 else
1646 chipname = "PCnet/32 79C965"; /* 486/VL bus */
1647 break;
1648 case 0x2621:
1649 chipname = "PCnet/PCI II 79C970A"; /* PCI */
1650 fdx = 1;
1651 break;
1652 case 0x2623:
1653 chipname = "PCnet/FAST 79C971"; /* PCI */
1654 fdx = 1;
1655 mii = 1;
1656 fset = 1;
1657 break;
1658 case 0x2624:
1659 chipname = "PCnet/FAST+ 79C972"; /* PCI */
1660 fdx = 1;
1661 mii = 1;
1662 fset = 1;
1663 break;
1664 case 0x2625:
1665 chipname = "PCnet/FAST III 79C973"; /* PCI */
1666 fdx = 1;
1667 mii = 1;
1668 break;
1669 case 0x2626:
1670 chipname = "PCnet/Home 79C978"; /* PCI */
1671 fdx = 1;
1672 /*
1673 * This is based on specs published at www.amd.com. This section
1674 * assumes that a card with a 79C978 wants to go into standard
1675 * ethernet mode. The 79C978 can also go into 1Mb HomePNA mode,
1676 * and the module option homepna=1 can select this instead.
1677 */
1678 media = a->read_bcr(ioaddr, 49);
1679 media &= ~3; /* default to 10Mb ethernet */
1680 if (cards_found < MAX_UNITS && homepna[cards_found])
1681 media |= 1; /* switch to home wiring mode */
1682 if (pcnet32_debug & NETIF_MSG_PROBE)
1683 printk(KERN_DEBUG PFX "media set to %sMbit mode.\n",
1684 (media & 1) ? "1" : "10");
1685 a->write_bcr(ioaddr, 49, media);
1686 break;
1687 case 0x2627:
1688 chipname = "PCnet/FAST III 79C975"; /* PCI */
1689 fdx = 1;
1690 mii = 1;
1691 break;
1692 case 0x2628:
1693 chipname = "PCnet/PRO 79C976";
1694 fdx = 1;
1695 mii = 1;
1696 break;
1697 default:
1698 if (pcnet32_debug & NETIF_MSG_PROBE)
1699 printk(KERN_INFO PFX
1700 "PCnet version %#x, no PCnet32 chip.\n",
1701 chip_version);
1702 goto err_release_region;
1703 }
1704
1705 /*
1706 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
1707 * starting until the packet is loaded. Strike one for reliability, lose
1708 * one for latency - although on PCI this isnt a big loss. Older chips
1709 * have FIFO's smaller than a packet, so you can't do this.
1710 * Turn on BCR18:BurstRdEn and BCR18:BurstWrEn.
1711 */
1712
1713 if (fset) {
1714 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0860));
1715 a->write_csr(ioaddr, 80,
1716 (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
1717 dxsuflo = 1;
1718 }
1719
1720 dev = alloc_etherdev(0);
1721 if (!dev) {
1722 if (pcnet32_debug & NETIF_MSG_PROBE)
1723 printk(KERN_ERR PFX "Memory allocation failed.\n");
1724 ret = -ENOMEM;
1725 goto err_release_region;
1726 }
1727 SET_NETDEV_DEV(dev, &pdev->dev);
1728
1729 if (pcnet32_debug & NETIF_MSG_PROBE)
1730 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
1731
1732 /* In most chips, after a chip reset, the ethernet address is read from the
1733 * station address PROM at the base address and programmed into the
1734 * "Physical Address Registers" CSR12-14.
1735 * As a precautionary measure, we read the PROM values and complain if
1736 * they disagree with the CSRs. If they miscompare, and the PROM addr
1737 * is valid, then the PROM addr is used.
1738 */
1739 for (i = 0; i < 3; i++) {
1740 unsigned int val;
1741 val = a->read_csr(ioaddr, i + 12) & 0x0ffff;
1742 /* There may be endianness issues here. */
1743 dev->dev_addr[2 * i] = val & 0x0ff;
1744 dev->dev_addr[2 * i + 1] = (val >> 8) & 0x0ff;
1745 }
1746
1747 /* read PROM address and compare with CSR address */
1748 for (i = 0; i < 6; i++)
1749 promaddr[i] = inb(ioaddr + i);
1750
1751 if (memcmp(promaddr, dev->dev_addr, 6)
1752 || !is_valid_ether_addr(dev->dev_addr)) {
1753 if (is_valid_ether_addr(promaddr)) {
1754 if (pcnet32_debug & NETIF_MSG_PROBE) {
1755 printk(" warning: CSR address invalid,\n");
1756 printk(KERN_INFO
1757 " using instead PROM address of");
1758 }
1759 memcpy(dev->dev_addr, promaddr, 6);
1760 }
1761 }
1762 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
1763
1764 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
1765 if (!is_valid_ether_addr(dev->perm_addr))
1766 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
1767
1768 if (pcnet32_debug & NETIF_MSG_PROBE) {
1769 for (i = 0; i < 6; i++)
1770 printk(" %2.2x", dev->dev_addr[i]);
1771
1772 /* Version 0x2623 and 0x2624 */
1773 if (((chip_version + 1) & 0xfffe) == 0x2624) {
1774 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
1775 printk("\n" KERN_INFO " tx_start_pt(0x%04x):", i);
1776 switch (i >> 10) {
1777 case 0:
1778 printk(" 20 bytes,");
1779 break;
1780 case 1:
1781 printk(" 64 bytes,");
1782 break;
1783 case 2:
1784 printk(" 128 bytes,");
1785 break;
1786 case 3:
1787 printk("~220 bytes,");
1788 break;
1789 }
1790 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
1791 printk(" BCR18(%x):", i & 0xffff);
1792 if (i & (1 << 5))
1793 printk("BurstWrEn ");
1794 if (i & (1 << 6))
1795 printk("BurstRdEn ");
1796 if (i & (1 << 7))
1797 printk("DWordIO ");
1798 if (i & (1 << 11))
1799 printk("NoUFlow ");
1800 i = a->read_bcr(ioaddr, 25);
1801 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,", i << 8);
1802 i = a->read_bcr(ioaddr, 26);
1803 printk(" SRAM_BND=0x%04x,", i << 8);
1804 i = a->read_bcr(ioaddr, 27);
1805 if (i & (1 << 14))
1806 printk("LowLatRx");
1807 }
1808 }
1809
1810 dev->base_addr = ioaddr;
1811 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
1812 if ((lp =
1813 pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
1814 if (pcnet32_debug & NETIF_MSG_PROBE)
1815 printk(KERN_ERR PFX
1816 "Consistent memory allocation failed.\n");
1817 ret = -ENOMEM;
1818 goto err_free_netdev;
1819 }
1820
1821 memset(lp, 0, sizeof(*lp));
1822 lp->dma_addr = lp_dma_addr;
1823 lp->pci_dev = pdev;
1824
1825 spin_lock_init(&lp->lock);
1826
1827 SET_MODULE_OWNER(dev);
1828 SET_NETDEV_DEV(dev, &pdev->dev);
1829 dev->priv = lp;
1830 lp->name = chipname;
1831 lp->shared_irq = shared;
1832 lp->tx_ring_size = TX_RING_SIZE; /* default tx ring size */
1833 lp->rx_ring_size = RX_RING_SIZE; /* default rx ring size */
1834 lp->tx_mod_mask = lp->tx_ring_size - 1;
1835 lp->rx_mod_mask = lp->rx_ring_size - 1;
1836 lp->tx_len_bits = (PCNET32_LOG_TX_BUFFERS << 12);
1837 lp->rx_len_bits = (PCNET32_LOG_RX_BUFFERS << 4);
1838 lp->mii_if.full_duplex = fdx;
1839 lp->mii_if.phy_id_mask = 0x1f;
1840 lp->mii_if.reg_num_mask = 0x1f;
1841 lp->dxsuflo = dxsuflo;
1842 lp->mii = mii;
1843 lp->chip_version = chip_version;
1844 lp->msg_enable = pcnet32_debug;
1845 if ((cards_found >= MAX_UNITS)
1846 || (options[cards_found] > sizeof(options_mapping)))
1847 lp->options = PCNET32_PORT_ASEL;
1848 else
1849 lp->options = options_mapping[options[cards_found]];
1850 lp->mii_if.dev = dev;
1851 lp->mii_if.mdio_read = mdio_read;
1852 lp->mii_if.mdio_write = mdio_write;
1853
1854 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
1855 ((cards_found >= MAX_UNITS) || full_duplex[cards_found]))
1856 lp->options |= PCNET32_PORT_FD;
1857
1858 if (!a) {
1859 if (pcnet32_debug & NETIF_MSG_PROBE)
1860 printk(KERN_ERR PFX "No access methods\n");
1861 ret = -ENODEV;
1862 goto err_free_consistent;
1863 }
1864 lp->a = *a;
1865
1866 /* prior to register_netdev, dev->name is not yet correct */
1867 if (pcnet32_alloc_ring(dev, pci_name(lp->pci_dev))) {
1868 ret = -ENOMEM;
1869 goto err_free_ring;
1870 }
1871 /* detect special T1/E1 WAN card by checking for MAC address */
1872 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0
1873 && dev->dev_addr[2] == 0x75)
1874 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
1875
1876 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
1877 lp->init_block.tlen_rlen =
1878 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
1879 for (i = 0; i < 6; i++)
1880 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1881 lp->init_block.filter[0] = 0x00000000;
1882 lp->init_block.filter[1] = 0x00000000;
1883 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
1884 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
1885
1886 /* switch pcnet32 to 32bit mode */
1887 a->write_bcr(ioaddr, 20, 2);
1888
1889 a->write_csr(ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private,
1890 init_block)) & 0xffff);
1891 a->write_csr(ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private,
1892 init_block)) >> 16);
1893
1894 if (pdev) { /* use the IRQ provided by PCI */
1895 dev->irq = pdev->irq;
1896 if (pcnet32_debug & NETIF_MSG_PROBE)
1897 printk(" assigned IRQ %d.\n", dev->irq);
1898 } else {
1899 unsigned long irq_mask = probe_irq_on();
1900
1901 /*
1902 * To auto-IRQ we enable the initialization-done and DMA error
1903 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
1904 * boards will work.
1905 */
1906 /* Trigger an initialization just for the interrupt. */
1907 a->write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_INIT);
1908 mdelay(1);
1909
1910 dev->irq = probe_irq_off(irq_mask);
1911 if (!dev->irq) {
1912 if (pcnet32_debug & NETIF_MSG_PROBE)
1913 printk(", failed to detect IRQ line.\n");
1914 ret = -ENODEV;
1915 goto err_free_ring;
1916 }
1917 if (pcnet32_debug & NETIF_MSG_PROBE)
1918 printk(", probed IRQ %d.\n", dev->irq);
1919 }
1920
1921 /* Set the mii phy_id so that we can query the link state */
1922 if (lp->mii) {
1923 /* lp->phycount and lp->phymask are set to 0 by memset above */
1924
1925 lp->mii_if.phy_id = ((lp->a.read_bcr(ioaddr, 33)) >> 5) & 0x1f;
1926 /* scan for PHYs */
1927 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
1928 unsigned short id1, id2;
1929
1930 id1 = mdio_read(dev, i, MII_PHYSID1);
1931 if (id1 == 0xffff)
1932 continue;
1933 id2 = mdio_read(dev, i, MII_PHYSID2);
1934 if (id2 == 0xffff)
1935 continue;
1936 if (i == 31 && ((chip_version + 1) & 0xfffe) == 0x2624)
1937 continue; /* 79C971 & 79C972 have phantom phy at id 31 */
1938 lp->phycount++;
1939 lp->phymask |= (1 << i);
1940 lp->mii_if.phy_id = i;
1941 if (pcnet32_debug & NETIF_MSG_PROBE)
1942 printk(KERN_INFO PFX
1943 "Found PHY %04x:%04x at address %d.\n",
1944 id1, id2, i);
1945 }
1946 lp->a.write_bcr(ioaddr, 33, (lp->mii_if.phy_id) << 5);
1947 if (lp->phycount > 1) {
1948 lp->options |= PCNET32_PORT_MII;
1949 }
1950 }
1951
1952 init_timer(&lp->watchdog_timer);
1953 lp->watchdog_timer.data = (unsigned long)dev;
1954 lp->watchdog_timer.function = (void *)&pcnet32_watchdog;
1955
1956 /* The PCNET32-specific entries in the device structure. */
1957 dev->open = &pcnet32_open;
1958 dev->hard_start_xmit = &pcnet32_start_xmit;
1959 dev->stop = &pcnet32_close;
1960 dev->get_stats = &pcnet32_get_stats;
1961 dev->set_multicast_list = &pcnet32_set_multicast_list;
1962 dev->do_ioctl = &pcnet32_ioctl;
1963 dev->ethtool_ops = &pcnet32_ethtool_ops;
1964 dev->tx_timeout = pcnet32_tx_timeout;
1965 dev->watchdog_timeo = (5 * HZ);
1966 dev->weight = lp->rx_ring_size / 2;
1967 #ifdef CONFIG_PCNET32_NAPI
1968 dev->poll = pcnet32_poll;
1969 #endif
1970
1971 #ifdef CONFIG_NET_POLL_CONTROLLER
1972 dev->poll_controller = pcnet32_poll_controller;
1973 #endif
1974
1975 /* Fill in the generic fields of the device structure. */
1976 if (register_netdev(dev))
1977 goto err_free_ring;
1978
1979 if (pdev) {
1980 pci_set_drvdata(pdev, dev);
1981 } else {
1982 lp->next = pcnet32_dev;
1983 pcnet32_dev = dev;
1984 }
1985
1986 if (pcnet32_debug & NETIF_MSG_PROBE)
1987 printk(KERN_INFO "%s: registered as %s\n", dev->name, lp->name);
1988 cards_found++;
1989
1990 /* enable LED writes */
1991 a->write_bcr(ioaddr, 2, a->read_bcr(ioaddr, 2) | 0x1000);
1992
1993 return 0;
1994
1995 err_free_ring:
1996 pcnet32_free_ring(dev);
1997 err_free_consistent:
1998 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1999 err_free_netdev:
2000 free_netdev(dev);
2001 err_release_region:
2002 release_region(ioaddr, PCNET32_TOTAL_SIZE);
2003 return ret;
2004 }
2005
2006 /* if any allocation fails, caller must also call pcnet32_free_ring */
2007 static int pcnet32_alloc_ring(struct net_device *dev, char *name)
2008 {
2009 struct pcnet32_private *lp = dev->priv;
2010
2011 lp->tx_ring = pci_alloc_consistent(lp->pci_dev,
2012 sizeof(struct pcnet32_tx_head) *
2013 lp->tx_ring_size,
2014 &lp->tx_ring_dma_addr);
2015 if (lp->tx_ring == NULL) {
2016 if (netif_msg_drv(lp))
2017 printk("\n" KERN_ERR PFX
2018 "%s: Consistent memory allocation failed.\n",
2019 name);
2020 return -ENOMEM;
2021 }
2022
2023 lp->rx_ring = pci_alloc_consistent(lp->pci_dev,
2024 sizeof(struct pcnet32_rx_head) *
2025 lp->rx_ring_size,
2026 &lp->rx_ring_dma_addr);
2027 if (lp->rx_ring == NULL) {
2028 if (netif_msg_drv(lp))
2029 printk("\n" KERN_ERR PFX
2030 "%s: Consistent memory allocation failed.\n",
2031 name);
2032 return -ENOMEM;
2033 }
2034
2035 lp->tx_dma_addr = kcalloc(lp->tx_ring_size, sizeof(dma_addr_t),
2036 GFP_ATOMIC);
2037 if (!lp->tx_dma_addr) {
2038 if (netif_msg_drv(lp))
2039 printk("\n" KERN_ERR PFX
2040 "%s: Memory allocation failed.\n", name);
2041 return -ENOMEM;
2042 }
2043
2044 lp->rx_dma_addr = kcalloc(lp->rx_ring_size, sizeof(dma_addr_t),
2045 GFP_ATOMIC);
2046 if (!lp->rx_dma_addr) {
2047 if (netif_msg_drv(lp))
2048 printk("\n" KERN_ERR PFX
2049 "%s: Memory allocation failed.\n", name);
2050 return -ENOMEM;
2051 }
2052
2053 lp->tx_skbuff = kcalloc(lp->tx_ring_size, sizeof(struct sk_buff *),
2054 GFP_ATOMIC);
2055 if (!lp->tx_skbuff) {
2056 if (netif_msg_drv(lp))
2057 printk("\n" KERN_ERR PFX
2058 "%s: Memory allocation failed.\n", name);
2059 return -ENOMEM;
2060 }
2061
2062 lp->rx_skbuff = kcalloc(lp->rx_ring_size, sizeof(struct sk_buff *),
2063 GFP_ATOMIC);
2064 if (!lp->rx_skbuff) {
2065 if (netif_msg_drv(lp))
2066 printk("\n" KERN_ERR PFX
2067 "%s: Memory allocation failed.\n", name);
2068 return -ENOMEM;
2069 }
2070
2071 return 0;
2072 }
2073
2074 static void pcnet32_free_ring(struct net_device *dev)
2075 {
2076 struct pcnet32_private *lp = dev->priv;
2077
2078 kfree(lp->tx_skbuff);
2079 lp->tx_skbuff = NULL;
2080
2081 kfree(lp->rx_skbuff);
2082 lp->rx_skbuff = NULL;
2083
2084 kfree(lp->tx_dma_addr);
2085 lp->tx_dma_addr = NULL;
2086
2087 kfree(lp->rx_dma_addr);
2088 lp->rx_dma_addr = NULL;
2089
2090 if (lp->tx_ring) {
2091 pci_free_consistent(lp->pci_dev,
2092 sizeof(struct pcnet32_tx_head) *
2093 lp->tx_ring_size, lp->tx_ring,
2094 lp->tx_ring_dma_addr);
2095 lp->tx_ring = NULL;
2096 }
2097
2098 if (lp->rx_ring) {
2099 pci_free_consistent(lp->pci_dev,
2100 sizeof(struct pcnet32_rx_head) *
2101 lp->rx_ring_size, lp->rx_ring,
2102 lp->rx_ring_dma_addr);
2103 lp->rx_ring = NULL;
2104 }
2105 }
2106
2107 static int pcnet32_open(struct net_device *dev)
2108 {
2109 struct pcnet32_private *lp = dev->priv;
2110 unsigned long ioaddr = dev->base_addr;
2111 u16 val;
2112 int i;
2113 int rc;
2114 unsigned long flags;
2115
2116 if (request_irq(dev->irq, &pcnet32_interrupt,
2117 lp->shared_irq ? IRQF_SHARED : 0, dev->name,
2118 (void *)dev)) {
2119 return -EAGAIN;
2120 }
2121
2122 spin_lock_irqsave(&lp->lock, flags);
2123 /* Check for a valid station address */
2124 if (!is_valid_ether_addr(dev->dev_addr)) {
2125 rc = -EINVAL;
2126 goto err_free_irq;
2127 }
2128
2129 /* Reset the PCNET32 */
2130 lp->a.reset(ioaddr);
2131
2132 /* switch pcnet32 to 32bit mode */
2133 lp->a.write_bcr(ioaddr, 20, 2);
2134
2135 if (netif_msg_ifup(lp))
2136 printk(KERN_DEBUG
2137 "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
2138 dev->name, dev->irq, (u32) (lp->tx_ring_dma_addr),
2139 (u32) (lp->rx_ring_dma_addr),
2140 (u32) (lp->dma_addr +
2141 offsetof(struct pcnet32_private, init_block)));
2142
2143 /* set/reset autoselect bit */
2144 val = lp->a.read_bcr(ioaddr, 2) & ~2;
2145 if (lp->options & PCNET32_PORT_ASEL)
2146 val |= 2;
2147 lp->a.write_bcr(ioaddr, 2, val);
2148
2149 /* handle full duplex setting */
2150 if (lp->mii_if.full_duplex) {
2151 val = lp->a.read_bcr(ioaddr, 9) & ~3;
2152 if (lp->options & PCNET32_PORT_FD) {
2153 val |= 1;
2154 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
2155 val |= 2;
2156 } else if (lp->options & PCNET32_PORT_ASEL) {
2157 /* workaround of xSeries250, turn on for 79C975 only */
2158 if (lp->chip_version == 0x2627)
2159 val |= 3;
2160 }
2161 lp->a.write_bcr(ioaddr, 9, val);
2162 }
2163
2164 /* set/reset GPSI bit in test register */
2165 val = lp->a.read_csr(ioaddr, 124) & ~0x10;
2166 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
2167 val |= 0x10;
2168 lp->a.write_csr(ioaddr, 124, val);
2169
2170 /* Allied Telesyn AT 2700/2701 FX are 100Mbit only and do not negotiate */
2171 if (lp->pci_dev->subsystem_vendor == PCI_VENDOR_ID_AT &&
2172 (lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2700FX ||
2173 lp->pci_dev->subsystem_device == PCI_SUBDEVICE_ID_AT_2701FX)) {
2174 if (lp->options & PCNET32_PORT_ASEL) {
2175 lp->options = PCNET32_PORT_FD | PCNET32_PORT_100;
2176 if (netif_msg_link(lp))
2177 printk(KERN_DEBUG
2178 "%s: Setting 100Mb-Full Duplex.\n",
2179 dev->name);
2180 }
2181 }
2182 if (lp->phycount < 2) {
2183 /*
2184 * 24 Jun 2004 according AMD, in order to change the PHY,
2185 * DANAS (or DISPM for 79C976) must be set; then select the speed,
2186 * duplex, and/or enable auto negotiation, and clear DANAS
2187 */
2188 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
2189 lp->a.write_bcr(ioaddr, 32,
2190 lp->a.read_bcr(ioaddr, 32) | 0x0080);
2191 /* disable Auto Negotiation, set 10Mpbs, HD */
2192 val = lp->a.read_bcr(ioaddr, 32) & ~0xb8;
2193 if (lp->options & PCNET32_PORT_FD)
2194 val |= 0x10;
2195 if (lp->options & PCNET32_PORT_100)
2196 val |= 0x08;
2197 lp->a.write_bcr(ioaddr, 32, val);
2198 } else {
2199 if (lp->options & PCNET32_PORT_ASEL) {
2200 lp->a.write_bcr(ioaddr, 32,
2201 lp->a.read_bcr(ioaddr,
2202 32) | 0x0080);
2203 /* enable auto negotiate, setup, disable fd */
2204 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
2205 val |= 0x20;
2206 lp->a.write_bcr(ioaddr, 32, val);
2207 }
2208 }
2209 } else {
2210 int first_phy = -1;
2211 u16 bmcr;
2212 u32 bcr9;
2213 struct ethtool_cmd ecmd;
2214
2215 /*
2216 * There is really no good other way to handle multiple PHYs
2217 * other than turning off all automatics
2218 */
2219 val = lp->a.read_bcr(ioaddr, 2);
2220 lp->a.write_bcr(ioaddr, 2, val & ~2);
2221 val = lp->a.read_bcr(ioaddr, 32);
2222 lp->a.write_bcr(ioaddr, 32, val & ~(1 << 7)); /* stop MII manager */
2223
2224 if (!(lp->options & PCNET32_PORT_ASEL)) {
2225 /* setup ecmd */
2226 ecmd.port = PORT_MII;
2227 ecmd.transceiver = XCVR_INTERNAL;
2228 ecmd.autoneg = AUTONEG_DISABLE;
2229 ecmd.speed =
2230 lp->
2231 options & PCNET32_PORT_100 ? SPEED_100 : SPEED_10;
2232 bcr9 = lp->a.read_bcr(ioaddr, 9);
2233
2234 if (lp->options & PCNET32_PORT_FD) {
2235 ecmd.duplex = DUPLEX_FULL;
2236 bcr9 |= (1 << 0);
2237 } else {
2238 ecmd.duplex = DUPLEX_HALF;
2239 bcr9 |= ~(1 << 0);
2240 }
2241 lp->a.write_bcr(ioaddr, 9, bcr9);
2242 }
2243
2244 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2245 if (lp->phymask & (1 << i)) {
2246 /* isolate all but the first PHY */
2247 bmcr = mdio_read(dev, i, MII_BMCR);
2248 if (first_phy == -1) {
2249 first_phy = i;
2250 mdio_write(dev, i, MII_BMCR,
2251 bmcr & ~BMCR_ISOLATE);
2252 } else {
2253 mdio_write(dev, i, MII_BMCR,
2254 bmcr | BMCR_ISOLATE);
2255 }
2256 /* use mii_ethtool_sset to setup PHY */
2257 lp->mii_if.phy_id = i;
2258 ecmd.phy_address = i;
2259 if (lp->options & PCNET32_PORT_ASEL) {
2260 mii_ethtool_gset(&lp->mii_if, &ecmd);
2261 ecmd.autoneg = AUTONEG_ENABLE;
2262 }
2263 mii_ethtool_sset(&lp->mii_if, &ecmd);
2264 }
2265 }
2266 lp->mii_if.phy_id = first_phy;
2267 if (netif_msg_link(lp))
2268 printk(KERN_INFO "%s: Using PHY number %d.\n",
2269 dev->name, first_phy);
2270 }
2271
2272 #ifdef DO_DXSUFLO
2273 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
2274 val = lp->a.read_csr(ioaddr, CSR3);
2275 val |= 0x40;
2276 lp->a.write_csr(ioaddr, CSR3, val);
2277 }
2278 #endif
2279
2280 lp->init_block.mode =
2281 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2282 pcnet32_load_multicast(dev);
2283
2284 if (pcnet32_init_ring(dev)) {
2285 rc = -ENOMEM;
2286 goto err_free_ring;
2287 }
2288
2289 /* Re-initialize the PCNET32, and start it when done. */
2290 lp->a.write_csr(ioaddr, 1, (lp->dma_addr +
2291 offsetof(struct pcnet32_private,
2292 init_block)) & 0xffff);
2293 lp->a.write_csr(ioaddr, 2,
2294 (lp->dma_addr +
2295 offsetof(struct pcnet32_private, init_block)) >> 16);
2296
2297 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2298 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2299
2300 netif_start_queue(dev);
2301
2302 if (lp->chip_version >= PCNET32_79C970A) {
2303 /* Print the link status and start the watchdog */
2304 pcnet32_check_media(dev, 1);
2305 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2306 }
2307
2308 i = 0;
2309 while (i++ < 100)
2310 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2311 break;
2312 /*
2313 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
2314 * reports that doing so triggers a bug in the '974.
2315 */
2316 lp->a.write_csr(ioaddr, CSR0, CSR0_NORMAL);
2317
2318 if (netif_msg_ifup(lp))
2319 printk(KERN_DEBUG
2320 "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
2321 dev->name, i,
2322 (u32) (lp->dma_addr +
2323 offsetof(struct pcnet32_private, init_block)),
2324 lp->a.read_csr(ioaddr, CSR0));
2325
2326 spin_unlock_irqrestore(&lp->lock, flags);
2327
2328 return 0; /* Always succeed */
2329
2330 err_free_ring:
2331 /* free any allocated skbuffs */
2332 pcnet32_purge_rx_ring(dev);
2333
2334 /*
2335 * Switch back to 16bit mode to avoid problems with dumb
2336 * DOS packet driver after a warm reboot
2337 */
2338 lp->a.write_bcr(ioaddr, 20, 4);
2339
2340 err_free_irq:
2341 spin_unlock_irqrestore(&lp->lock, flags);
2342 free_irq(dev->irq, dev);
2343 return rc;
2344 }
2345
2346 /*
2347 * The LANCE has been halted for one reason or another (busmaster memory
2348 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
2349 * etc.). Modern LANCE variants always reload their ring-buffer
2350 * configuration when restarted, so we must reinitialize our ring
2351 * context before restarting. As part of this reinitialization,
2352 * find all packets still on the Tx ring and pretend that they had been
2353 * sent (in effect, drop the packets on the floor) - the higher-level
2354 * protocols will time out and retransmit. It'd be better to shuffle
2355 * these skbs to a temp list and then actually re-Tx them after
2356 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
2357 */
2358
2359 static void pcnet32_purge_tx_ring(struct net_device *dev)
2360 {
2361 struct pcnet32_private *lp = dev->priv;
2362 int i;
2363
2364 for (i = 0; i < lp->tx_ring_size; i++) {
2365 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2366 wmb(); /* Make sure adapter sees owner change */
2367 if (lp->tx_skbuff[i]) {
2368 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i],
2369 lp->tx_skbuff[i]->len,
2370 PCI_DMA_TODEVICE);
2371 dev_kfree_skb_any(lp->tx_skbuff[i]);
2372 }
2373 lp->tx_skbuff[i] = NULL;
2374 lp->tx_dma_addr[i] = 0;
2375 }
2376 }
2377
2378 /* Initialize the PCNET32 Rx and Tx rings. */
2379 static int pcnet32_init_ring(struct net_device *dev)
2380 {
2381 struct pcnet32_private *lp = dev->priv;
2382 int i;
2383
2384 lp->tx_full = 0;
2385 lp->cur_rx = lp->cur_tx = 0;
2386 lp->dirty_rx = lp->dirty_tx = 0;
2387
2388 for (i = 0; i < lp->rx_ring_size; i++) {
2389 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
2390 if (rx_skbuff == NULL) {
2391 if (!
2392 (rx_skbuff = lp->rx_skbuff[i] =
2393 dev_alloc_skb(PKT_BUF_SZ))) {
2394 /* there is not much, we can do at this point */
2395 if (netif_msg_drv(lp))
2396 printk(KERN_ERR
2397 "%s: pcnet32_init_ring dev_alloc_skb failed.\n",
2398 dev->name);
2399 return -1;
2400 }
2401 skb_reserve(rx_skbuff, 2);
2402 }
2403
2404 rmb();
2405 if (lp->rx_dma_addr[i] == 0)
2406 lp->rx_dma_addr[i] =
2407 pci_map_single(lp->pci_dev, rx_skbuff->data,
2408 PKT_BUF_SZ - 2, PCI_DMA_FROMDEVICE);
2409 lp->rx_ring[i].base = (u32) le32_to_cpu(lp->rx_dma_addr[i]);
2410 lp->rx_ring[i].buf_length = le16_to_cpu(2 - PKT_BUF_SZ);
2411 wmb(); /* Make sure owner changes after all others are visible */
2412 lp->rx_ring[i].status = le16_to_cpu(0x8000);
2413 }
2414 /* The Tx buffer address is filled in as needed, but we do need to clear
2415 * the upper ownership bit. */
2416 for (i = 0; i < lp->tx_ring_size; i++) {
2417 lp->tx_ring[i].status = 0; /* CPU owns buffer */
2418 wmb(); /* Make sure adapter sees owner change */
2419 lp->tx_ring[i].base = 0;
2420 lp->tx_dma_addr[i] = 0;
2421 }
2422
2423 lp->init_block.tlen_rlen =
2424 le16_to_cpu(lp->tx_len_bits | lp->rx_len_bits);
2425 for (i = 0; i < 6; i++)
2426 lp->init_block.phys_addr[i] = dev->dev_addr[i];
2427 lp->init_block.rx_ring = (u32) le32_to_cpu(lp->rx_ring_dma_addr);
2428 lp->init_block.tx_ring = (u32) le32_to_cpu(lp->tx_ring_dma_addr);
2429 wmb(); /* Make sure all changes are visible */
2430 return 0;
2431 }
2432
2433 /* the pcnet32 has been issued a stop or reset. Wait for the stop bit
2434 * then flush the pending transmit operations, re-initialize the ring,
2435 * and tell the chip to initialize.
2436 */
2437 static void pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
2438 {
2439 struct pcnet32_private *lp = dev->priv;
2440 unsigned long ioaddr = dev->base_addr;
2441 int i;
2442
2443 /* wait for stop */
2444 for (i = 0; i < 100; i++)
2445 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_STOP)
2446 break;
2447
2448 if (i >= 100 && netif_msg_drv(lp))
2449 printk(KERN_ERR
2450 "%s: pcnet32_restart timed out waiting for stop.\n",
2451 dev->name);
2452
2453 pcnet32_purge_tx_ring(dev);
2454 if (pcnet32_init_ring(dev))
2455 return;
2456
2457 /* ReInit Ring */
2458 lp->a.write_csr(ioaddr, CSR0, CSR0_INIT);
2459 i = 0;
2460 while (i++ < 1000)
2461 if (lp->a.read_csr(ioaddr, CSR0) & CSR0_IDON)
2462 break;
2463
2464 lp->a.write_csr(ioaddr, CSR0, csr0_bits);
2465 }
2466
2467 static void pcnet32_tx_timeout(struct net_device *dev)
2468 {
2469 struct pcnet32_private *lp = dev->priv;
2470 unsigned long ioaddr = dev->base_addr, flags;
2471
2472 spin_lock_irqsave(&lp->lock, flags);
2473 /* Transmitter timeout, serious problems. */
2474 if (pcnet32_debug & NETIF_MSG_DRV)
2475 printk(KERN_ERR
2476 "%s: transmit timed out, status %4.4x, resetting.\n",
2477 dev->name, lp->a.read_csr(ioaddr, CSR0));
2478 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2479 lp->stats.tx_errors++;
2480 if (netif_msg_tx_err(lp)) {
2481 int i;
2482 printk(KERN_DEBUG
2483 " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
2484 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
2485 lp->cur_rx);
2486 for (i = 0; i < lp->rx_ring_size; i++)
2487 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2488 le32_to_cpu(lp->rx_ring[i].base),
2489 (-le16_to_cpu(lp->rx_ring[i].buf_length)) &
2490 0xffff, le32_to_cpu(lp->rx_ring[i].msg_length),
2491 le16_to_cpu(lp->rx_ring[i].status));
2492 for (i = 0; i < lp->tx_ring_size; i++)
2493 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
2494 le32_to_cpu(lp->tx_ring[i].base),
2495 (-le16_to_cpu(lp->tx_ring[i].length)) & 0xffff,
2496 le32_to_cpu(lp->tx_ring[i].misc),
2497 le16_to_cpu(lp->tx_ring[i].status));
2498 printk("\n");
2499 }
2500 pcnet32_restart(dev, CSR0_NORMAL);
2501
2502 dev->trans_start = jiffies;
2503 netif_wake_queue(dev);
2504
2505 spin_unlock_irqrestore(&lp->lock, flags);
2506 }
2507
2508 static int pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
2509 {
2510 struct pcnet32_private *lp = dev->priv;
2511 unsigned long ioaddr = dev->base_addr;
2512 u16 status;
2513 int entry;
2514 unsigned long flags;
2515
2516 spin_lock_irqsave(&lp->lock, flags);
2517
2518 if (netif_msg_tx_queued(lp)) {
2519 printk(KERN_DEBUG
2520 "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
2521 dev->name, lp->a.read_csr(ioaddr, CSR0));
2522 }
2523
2524 /* Default status -- will not enable Successful-TxDone
2525 * interrupt when that option is available to us.
2526 */
2527 status = 0x8300;
2528
2529 /* Fill in a Tx ring entry */
2530
2531 /* Mask to ring buffer boundary. */
2532 entry = lp->cur_tx & lp->tx_mod_mask;
2533
2534 /* Caution: the write order is important here, set the status
2535 * with the "ownership" bits last. */
2536
2537 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
2538
2539 lp->tx_ring[entry].misc = 0x00000000;
2540
2541 lp->tx_skbuff[entry] = skb;
2542 lp->tx_dma_addr[entry] =
2543 pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
2544 lp->tx_ring[entry].base = (u32) le32_to_cpu(lp->tx_dma_addr[entry]);
2545 wmb(); /* Make sure owner changes after all others are visible */
2546 lp->tx_ring[entry].status = le16_to_cpu(status);
2547
2548 lp->cur_tx++;
2549 lp->stats.tx_bytes += skb->len;
2550
2551 /* Trigger an immediate send poll. */
2552 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN | CSR0_TXPOLL);
2553
2554 dev->trans_start = jiffies;
2555
2556 if (lp->tx_ring[(entry + 1) & lp->tx_mod_mask].base != 0) {
2557 lp->tx_full = 1;
2558 netif_stop_queue(dev);
2559 }
2560 spin_unlock_irqrestore(&lp->lock, flags);
2561 return 0;
2562 }
2563
2564 /* The PCNET32 interrupt handler. */
2565 static irqreturn_t
2566 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2567 {
2568 struct net_device *dev = dev_id;
2569 struct pcnet32_private *lp;
2570 unsigned long ioaddr;
2571 u16 csr0;
2572 int boguscnt = max_interrupt_work;
2573
2574 if (!dev) {
2575 if (pcnet32_debug & NETIF_MSG_INTR)
2576 printk(KERN_DEBUG "%s(): irq %d for unknown device\n",
2577 __FUNCTION__, irq);
2578 return IRQ_NONE;
2579 }
2580
2581 ioaddr = dev->base_addr;
2582 lp = dev->priv;
2583
2584 spin_lock(&lp->lock);
2585
2586 csr0 = lp->a.read_csr(ioaddr, CSR0);
2587 while ((csr0 & 0x8f00) && --boguscnt >= 0) {
2588 if (csr0 == 0xffff) {
2589 break; /* PCMCIA remove happened */
2590 }
2591 /* Acknowledge all of the current interrupt sources ASAP. */
2592 lp->a.write_csr(ioaddr, CSR0, csr0 & ~0x004f);
2593
2594 if (netif_msg_intr(lp))
2595 printk(KERN_DEBUG
2596 "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
2597 dev->name, csr0, lp->a.read_csr(ioaddr, CSR0));
2598
2599 /* Log misc errors. */
2600 if (csr0 & 0x4000)
2601 lp->stats.tx_errors++; /* Tx babble. */
2602 if (csr0 & 0x1000) {
2603 /*
2604 * This happens when our receive ring is full. This
2605 * shouldn't be a problem as we will see normal rx
2606 * interrupts for the frames in the receive ring. But
2607 * there are some PCI chipsets (I can reproduce this
2608 * on SP3G with Intel saturn chipset) which have
2609 * sometimes problems and will fill up the receive
2610 * ring with error descriptors. In this situation we
2611 * don't get a rx interrupt, but a missed frame
2612 * interrupt sooner or later.
2613 */
2614 lp->stats.rx_errors++; /* Missed a Rx frame. */
2615 }
2616 if (csr0 & 0x0800) {
2617 if (netif_msg_drv(lp))
2618 printk(KERN_ERR
2619 "%s: Bus master arbitration failure, status %4.4x.\n",
2620 dev->name, csr0);
2621 /* unlike for the lance, there is no restart needed */
2622 }
2623 #ifdef CONFIG_PCNET32_NAPI
2624 if (netif_rx_schedule_prep(dev)) {
2625 u16 val;
2626 /* set interrupt masks */
2627 val = lp->a.read_csr(ioaddr, CSR3);
2628 val |= 0x5f00;
2629 lp->a.write_csr(ioaddr, CSR3, val);
2630 mmiowb();
2631 __netif_rx_schedule(dev);
2632 break;
2633 }
2634 #else
2635 pcnet32_rx(dev, dev->weight);
2636 if (pcnet32_tx(dev)) {
2637 /* reset the chip to clear the error condition, then restart */
2638 lp->a.reset(ioaddr);
2639 lp->a.write_csr(ioaddr, CSR4, 0x0915); /* auto tx pad */
2640 pcnet32_restart(dev, CSR0_START);
2641 netif_wake_queue(dev);
2642 }
2643 #endif
2644 csr0 = lp->a.read_csr(ioaddr, CSR0);
2645 }
2646
2647 #ifndef CONFIG_PCNET32_NAPI
2648 /* Set interrupt enable. */
2649 lp->a.write_csr(ioaddr, CSR0, CSR0_INTEN);
2650 #endif
2651
2652 if (netif_msg_intr(lp))
2653 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
2654 dev->name, lp->a.read_csr(ioaddr, CSR0));
2655
2656 spin_unlock(&lp->lock);
2657
2658 return IRQ_HANDLED;
2659 }
2660
2661 static int pcnet32_close(struct net_device *dev)
2662 {
2663 unsigned long ioaddr = dev->base_addr;
2664 struct pcnet32_private *lp = dev->priv;
2665 unsigned long flags;
2666
2667 del_timer_sync(&lp->watchdog_timer);
2668
2669 netif_stop_queue(dev);
2670
2671 spin_lock_irqsave(&lp->lock, flags);
2672
2673 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2674
2675 if (netif_msg_ifdown(lp))
2676 printk(KERN_DEBUG
2677 "%s: Shutting down ethercard, status was %2.2x.\n",
2678 dev->name, lp->a.read_csr(ioaddr, CSR0));
2679
2680 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
2681 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2682
2683 /*
2684 * Switch back to 16bit mode to avoid problems with dumb
2685 * DOS packet driver after a warm reboot
2686 */
2687 lp->a.write_bcr(ioaddr, 20, 4);
2688
2689 spin_unlock_irqrestore(&lp->lock, flags);
2690
2691 free_irq(dev->irq, dev);
2692
2693 spin_lock_irqsave(&lp->lock, flags);
2694
2695 pcnet32_purge_rx_ring(dev);
2696 pcnet32_purge_tx_ring(dev);
2697
2698 spin_unlock_irqrestore(&lp->lock, flags);
2699
2700 return 0;
2701 }
2702
2703 static struct net_device_stats *pcnet32_get_stats(struct net_device *dev)
2704 {
2705 struct pcnet32_private *lp = dev->priv;
2706 unsigned long ioaddr = dev->base_addr;
2707 unsigned long flags;
2708
2709 spin_lock_irqsave(&lp->lock, flags);
2710 lp->stats.rx_missed_errors = lp->a.read_csr(ioaddr, 112);
2711 spin_unlock_irqrestore(&lp->lock, flags);
2712
2713 return &lp->stats;
2714 }
2715
2716 /* taken from the sunlance driver, which it took from the depca driver */
2717 static void pcnet32_load_multicast(struct net_device *dev)
2718 {
2719 struct pcnet32_private *lp = dev->priv;
2720 volatile struct pcnet32_init_block *ib = &lp->init_block;
2721 volatile u16 *mcast_table = (u16 *) & ib->filter;
2722 struct dev_mc_list *dmi = dev->mc_list;
2723 unsigned long ioaddr = dev->base_addr;
2724 char *addrs;
2725 int i;
2726 u32 crc;
2727
2728 /* set all multicast bits */
2729 if (dev->flags & IFF_ALLMULTI) {
2730 ib->filter[0] = 0xffffffff;
2731 ib->filter[1] = 0xffffffff;
2732 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER, 0xffff);
2733 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+1, 0xffff);
2734 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+2, 0xffff);
2735 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER+3, 0xffff);
2736 return;
2737 }
2738 /* clear the multicast filter */
2739 ib->filter[0] = 0;
2740 ib->filter[1] = 0;
2741
2742 /* Add addresses */
2743 for (i = 0; i < dev->mc_count; i++) {
2744 addrs = dmi->dmi_addr;
2745 dmi = dmi->next;
2746
2747 /* multicast address? */
2748 if (!(*addrs & 1))
2749 continue;
2750
2751 crc = ether_crc_le(6, addrs);
2752 crc = crc >> 26;
2753 mcast_table[crc >> 4] =
2754 le16_to_cpu(le16_to_cpu(mcast_table[crc >> 4]) |
2755 (1 << (crc & 0xf)));
2756 }
2757 for (i = 0; i < 4; i++)
2758 lp->a.write_csr(ioaddr, PCNET32_MC_FILTER + i,
2759 le16_to_cpu(mcast_table[i]));
2760 return;
2761 }
2762
2763 /*
2764 * Set or clear the multicast filter for this adaptor.
2765 */
2766 static void pcnet32_set_multicast_list(struct net_device *dev)
2767 {
2768 unsigned long ioaddr = dev->base_addr, flags;
2769 struct pcnet32_private *lp = dev->priv;
2770 int csr15, suspended;
2771
2772 spin_lock_irqsave(&lp->lock, flags);
2773 suspended = pcnet32_suspend(dev, &flags, 0);
2774 csr15 = lp->a.read_csr(ioaddr, CSR15);
2775 if (dev->flags & IFF_PROMISC) {
2776 /* Log any net taps. */
2777 if (netif_msg_hw(lp))
2778 printk(KERN_INFO "%s: Promiscuous mode enabled.\n",
2779 dev->name);
2780 lp->init_block.mode =
2781 le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) <<
2782 7);
2783 lp->a.write_csr(ioaddr, CSR15, csr15 | 0x8000);
2784 } else {
2785 lp->init_block.mode =
2786 le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
2787 lp->a.write_csr(ioaddr, CSR15, csr15 & 0x7fff);
2788 pcnet32_load_multicast(dev);
2789 }
2790
2791 if (suspended) {
2792 int csr5;
2793 /* clear SUSPEND (SPND) - CSR5 bit 0 */
2794 csr5 = lp->a.read_csr(ioaddr, CSR5);
2795 lp->a.write_csr(ioaddr, CSR5, csr5 & (~CSR5_SUSPEND));
2796 } else {
2797 lp->a.write_csr(ioaddr, CSR0, CSR0_STOP);
2798 pcnet32_restart(dev, CSR0_NORMAL);
2799 netif_wake_queue(dev);
2800 }
2801
2802 spin_unlock_irqrestore(&lp->lock, flags);
2803 }
2804
2805 /* This routine assumes that the lp->lock is held */
2806 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
2807 {
2808 struct pcnet32_private *lp = dev->priv;
2809 unsigned long ioaddr = dev->base_addr;
2810 u16 val_out;
2811
2812 if (!lp->mii)
2813 return 0;
2814
2815 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2816 val_out = lp->a.read_bcr(ioaddr, 34);
2817
2818 return val_out;
2819 }
2820
2821 /* This routine assumes that the lp->lock is held */
2822 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
2823 {
2824 struct pcnet32_private *lp = dev->priv;
2825 unsigned long ioaddr = dev->base_addr;
2826
2827 if (!lp->mii)
2828 return;
2829
2830 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
2831 lp->a.write_bcr(ioaddr, 34, val);
2832 }
2833
2834 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2835 {
2836 struct pcnet32_private *lp = dev->priv;
2837 int rc;
2838 unsigned long flags;
2839
2840 /* SIOC[GS]MIIxxx ioctls */
2841 if (lp->mii) {
2842 spin_lock_irqsave(&lp->lock, flags);
2843 rc = generic_mii_ioctl(&lp->mii_if, if_mii(rq), cmd, NULL);
2844 spin_unlock_irqrestore(&lp->lock, flags);
2845 } else {
2846 rc = -EOPNOTSUPP;
2847 }
2848
2849 return rc;
2850 }
2851
2852 static int pcnet32_check_otherphy(struct net_device *dev)
2853 {
2854 struct pcnet32_private *lp = dev->priv;
2855 struct mii_if_info mii = lp->mii_if;
2856 u16 bmcr;
2857 int i;
2858
2859 for (i = 0; i < PCNET32_MAX_PHYS; i++) {
2860 if (i == lp->mii_if.phy_id)
2861 continue; /* skip active phy */
2862 if (lp->phymask & (1 << i)) {
2863 mii.phy_id = i;
2864 if (mii_link_ok(&mii)) {
2865 /* found PHY with active link */
2866 if (netif_msg_link(lp))
2867 printk(KERN_INFO
2868 "%s: Using PHY number %d.\n",
2869 dev->name, i);
2870
2871 /* isolate inactive phy */
2872 bmcr =
2873 mdio_read(dev, lp->mii_if.phy_id, MII_BMCR);
2874 mdio_write(dev, lp->mii_if.phy_id, MII_BMCR,
2875 bmcr | BMCR_ISOLATE);
2876
2877 /* de-isolate new phy */
2878 bmcr = mdio_read(dev, i, MII_BMCR);
2879 mdio_write(dev, i, MII_BMCR,
2880 bmcr & ~BMCR_ISOLATE);
2881
2882 /* set new phy address */
2883 lp->mii_if.phy_id = i;
2884 return 1;
2885 }
2886 }
2887 }
2888 return 0;
2889 }
2890
2891 /*
2892 * Show the status of the media. Similar to mii_check_media however it
2893 * correctly shows the link speed for all (tested) pcnet32 variants.
2894 * Devices with no mii just report link state without speed.
2895 *
2896 * Caller is assumed to hold and release the lp->lock.
2897 */
2898
2899 static void pcnet32_check_media(struct net_device *dev, int verbose)
2900 {
2901 struct pcnet32_private *lp = dev->priv;
2902 int curr_link;
2903 int prev_link = netif_carrier_ok(dev) ? 1 : 0;
2904 u32 bcr9;
2905
2906 if (lp->mii) {
2907 curr_link = mii_link_ok(&lp->mii_if);
2908 } else {
2909 ulong ioaddr = dev->base_addr; /* card base I/O address */
2910 curr_link = (lp->a.read_bcr(ioaddr, 4) != 0xc0);
2911 }
2912 if (!curr_link) {
2913 if (prev_link || verbose) {
2914 netif_carrier_off(dev);
2915 if (netif_msg_link(lp))
2916 printk(KERN_INFO "%s: link down\n", dev->name);
2917 }
2918 if (lp->phycount > 1) {
2919 curr_link = pcnet32_check_otherphy(dev);
2920 prev_link = 0;
2921 }
2922 } else if (verbose || !prev_link) {
2923 netif_carrier_on(dev);
2924 if (lp->mii) {
2925 if (netif_msg_link(lp)) {
2926 struct ethtool_cmd ecmd;
2927 mii_ethtool_gset(&lp->mii_if, &ecmd);
2928 printk(KERN_INFO
2929 "%s: link up, %sMbps, %s-duplex\n",
2930 dev->name,
2931 (ecmd.speed == SPEED_100) ? "100" : "10",
2932 (ecmd.duplex ==
2933 DUPLEX_FULL) ? "full" : "half");
2934 }
2935 bcr9 = lp->a.read_bcr(dev->base_addr, 9);
2936 if ((bcr9 & (1 << 0)) != lp->mii_if.full_duplex) {
2937 if (lp->mii_if.full_duplex)
2938 bcr9 |= (1 << 0);
2939 else
2940 bcr9 &= ~(1 << 0);
2941 lp->a.write_bcr(dev->base_addr, 9, bcr9);
2942 }
2943 } else {
2944 if (netif_msg_link(lp))
2945 printk(KERN_INFO "%s: link up\n", dev->name);
2946 }
2947 }
2948 }
2949
2950 /*
2951 * Check for loss of link and link establishment.
2952 * Can not use mii_check_media because it does nothing if mode is forced.
2953 */
2954
2955 static void pcnet32_watchdog(struct net_device *dev)
2956 {
2957 struct pcnet32_private *lp = dev->priv;
2958 unsigned long flags;
2959
2960 /* Print the link status if it has changed */
2961 spin_lock_irqsave(&lp->lock, flags);
2962 pcnet32_check_media(dev, 0);
2963 spin_unlock_irqrestore(&lp->lock, flags);
2964
2965 mod_timer(&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
2966 }
2967
2968 static void __devexit pcnet32_remove_one(struct pci_dev *pdev)
2969 {
2970 struct net_device *dev = pci_get_drvdata(pdev);
2971
2972 if (dev) {
2973 struct pcnet32_private *lp = dev->priv;
2974
2975 unregister_netdev(dev);
2976 pcnet32_free_ring(dev);
2977 release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
2978 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
2979 free_netdev(dev);
2980 pci_disable_device(pdev);
2981 pci_set_drvdata(pdev, NULL);
2982 }
2983 }
2984
2985 static struct pci_driver pcnet32_driver = {
2986 .name = DRV_NAME,
2987 .probe = pcnet32_probe_pci,
2988 .remove = __devexit_p(pcnet32_remove_one),
2989 .id_table = pcnet32_pci_tbl,
2990 };
2991
2992 /* An additional parameter that may be passed in... */
2993 static int debug = -1;
2994 static int tx_start_pt = -1;
2995 static int pcnet32_have_pci;
2996
2997 module_param(debug, int, 0);
2998 MODULE_PARM_DESC(debug, DRV_NAME " debug level");
2999 module_param(max_interrupt_work, int, 0);
3000 MODULE_PARM_DESC(max_interrupt_work,
3001 DRV_NAME " maximum events handled per interrupt");
3002 module_param(rx_copybreak, int, 0);
3003 MODULE_PARM_DESC(rx_copybreak,
3004 DRV_NAME " copy breakpoint for copy-only-tiny-frames");
3005 module_param(tx_start_pt, int, 0);
3006 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
3007 module_param(pcnet32vlb, int, 0);
3008 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
3009 module_param_array(options, int, NULL, 0);
3010 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
3011 module_param_array(full_duplex, int, NULL, 0);
3012 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
3013 /* Module Parameter for HomePNA cards added by Patrick Simmons, 2004 */
3014 module_param_array(homepna, int, NULL, 0);
3015 MODULE_PARM_DESC(homepna,
3016 DRV_NAME
3017 " mode for 79C978 cards (1 for HomePNA, 0 for Ethernet, default Ethernet");
3018
3019 MODULE_AUTHOR("Thomas Bogendoerfer");
3020 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
3021 MODULE_LICENSE("GPL");
3022
3023 #define PCNET32_MSG_DEFAULT (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)
3024
3025 static int __init pcnet32_init_module(void)
3026 {
3027 printk(KERN_INFO "%s", version);
3028
3029 pcnet32_debug = netif_msg_init(debug, PCNET32_MSG_DEFAULT);
3030
3031 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
3032 tx_start = tx_start_pt;
3033
3034 /* find the PCI devices */
3035 if (!pci_register_driver(&pcnet32_driver))
3036 pcnet32_have_pci = 1;
3037
3038 /* should we find any remaining VLbus devices ? */
3039 if (pcnet32vlb)
3040 pcnet32_probe_vlbus(pcnet32_portlist);
3041
3042 if (cards_found && (pcnet32_debug & NETIF_MSG_PROBE))
3043 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
3044
3045 return (pcnet32_have_pci + cards_found) ? 0 : -ENODEV;
3046 }
3047
3048 static void __exit pcnet32_cleanup_module(void)
3049 {
3050 struct net_device *next_dev;
3051
3052 while (pcnet32_dev) {
3053 struct pcnet32_private *lp = pcnet32_dev->priv;
3054 next_dev = lp->next;
3055 unregister_netdev(pcnet32_dev);
3056 pcnet32_free_ring(pcnet32_dev);
3057 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
3058 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
3059 free_netdev(pcnet32_dev);
3060 pcnet32_dev = next_dev;
3061 }
3062
3063 if (pcnet32_have_pci)
3064 pci_unregister_driver(&pcnet32_driver);
3065 }
3066
3067 module_init(pcnet32_init_module);
3068 module_exit(pcnet32_cleanup_module);
3069
3070 /*
3071 * Local variables:
3072 * c-indent-level: 4
3073 * tab-width: 8
3074 * End:
3075 */
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