arch/x86/kernel/mpparse_64.c

   1 /*
   2  *      Intel Multiprocessor Specification 1.1 and 1.4
   3  *      compliant MP-table parsing routines.
   4  *
   5  *      (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
   6  *      (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
   7  *
   8  *      Fixes
   9  *              Erich Boleyn    :       MP v1.4 and additional changes.
  10  *              Alan Cox        :       Added EBDA scanning
  11  *              Ingo Molnar     :       various cleanups and rewrites
  12  *              Maciej W. Rozycki:      Bits for default MP configurations
  13  *              Paul Diefenbaugh:       Added full ACPI support
  14  */
  15
  16 #include <linux/mm.h>
  17 #include <linux/init.h>
  18 #include <linux/delay.h>
  19 #include <linux/bootmem.h>
  20 #include <linux/kernel_stat.h>
  21 #include <linux/mc146818rtc.h>
  22 #include <linux/acpi.h>
  23 #include <linux/module.h>
  24
  25 #include <asm/smp.h>
  26 #include <asm/mtrr.h>
  27 #include <asm/mpspec.h>
  28 #include <asm/pgalloc.h>
  29 #include <asm/io_apic.h>
  30 #include <asm/proto.h>
  31 #include <asm/acpi.h>
  32
  33 /* Have we found an MP table */
  34 int smp_found_config;
  35
  36 /*
  37  * Various Linux-internal data structures created from the
  38  * MP-table.
  39  */
  40 DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES);
  41 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
  42
  43 static int mp_current_pci_id = 0;
  44 /* I/O APIC entries */
  45 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
  46
  47 /* # of MP IRQ source entries */
  48 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
  49
  50 /* MP IRQ source entries */
  51 int mp_irq_entries;
  52
  53 int nr_ioapics;
  54 unsigned long mp_lapic_addr = 0;
  55
  56
  57
  58 /* Processor that is doing the boot up */
  59 unsigned int boot_cpu_id = -1U;
  60 EXPORT_SYMBOL(boot_cpu_id);
  61
  62 /* Internal processor count */
  63 unsigned int num_processors __cpuinitdata = 0;
  64
  65 unsigned disabled_cpus __cpuinitdata;
  66
  67 /* Bitmask of physically existing CPUs */
  68 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
  69
  70 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
  71
  72
  73 /*
  74  * Intel MP BIOS table parsing routines:
  75  */
  76
  77 /*
  78  * Checksum an MP configuration block.
  79  */
  80
  81 static int __init mpf_checksum(unsigned char *mp, int len)
  82 {
  83         int sum = 0;
  84
  85         while (len--)
  86                 sum += *mp++;
  87
  88         return sum & 0xFF;
  89 }
  90
  91 static void __cpuinit MP_processor_info(struct mpc_config_processor *m)
  92 {
  93         int cpu;
  94         cpumask_t tmp_map;
  95         char *bootup_cpu = "";
  96
  97         if (!(m->mpc_cpuflag & CPU_ENABLED)) {
  98                 disabled_cpus++;
  99                 return;
 100         }
 101         if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
 102                 bootup_cpu = " (Bootup-CPU)";
 103                 boot_cpu_id = m->mpc_apicid;
 104         }
 105
 106         printk(KERN_INFO "Processor #%d%s\n", m->mpc_apicid, bootup_cpu);
 107
 108         if (num_processors >= NR_CPUS) {
 109                 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
 110                         " Processor ignored.\n", NR_CPUS);
 111                 return;
 112         }
 113
 114         num_processors++;
 115         cpus_complement(tmp_map, cpu_present_map);
 116         cpu = first_cpu(tmp_map);
 117
 118         physid_set(m->mpc_apicid, phys_cpu_present_map);
 119         if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
 120                 /*
 121                  * bios_cpu_apicid is required to have processors listed
 122                  * in same order as logical cpu numbers. Hence the first
 123                  * entry is BSP, and so on.
 124                  */
 125                 cpu = 0;
 126         }
 127         bios_cpu_apicid[cpu] = m->mpc_apicid;
 128         /*
 129          * We get called early in the the start_kernel initialization
 130          * process when the per_cpu data area is not yet setup, so we
 131          * use a static array that is removed after the per_cpu data
 132          * area is created.
 133          */
 134         if (x86_cpu_to_apicid_ptr) {
 135                 u8 *x86_cpu_to_apicid = (u8 *)x86_cpu_to_apicid_ptr;
 136                 x86_cpu_to_apicid[cpu] = m->mpc_apicid;
 137         } else {
 138                 per_cpu(x86_cpu_to_apicid, cpu) = m->mpc_apicid;
 139         }
 140
 141         cpu_set(cpu, cpu_possible_map);
 142         cpu_set(cpu, cpu_present_map);
 143 }
 144
 145 static void __init MP_bus_info (struct mpc_config_bus *m)
 146 {
 147         char str[7];
 148
 149         memcpy(str, m->mpc_bustype, 6);
 150         str[6] = 0;
 151         Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
 152
 153         if (strncmp(str, "ISA", 3) == 0) {
 154                 set_bit(m->mpc_busid, mp_bus_not_pci);
 155         } else if (strncmp(str, "PCI", 3) == 0) {
 156                 clear_bit(m->mpc_busid, mp_bus_not_pci);
 157                 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
 158                 mp_current_pci_id++;
 159         } else {
 160                 printk(KERN_ERR "Unknown bustype %s\n", str);
 161         }
 162 }
 163
 164 static int bad_ioapic(unsigned long address)
 165 {
 166         if (nr_ioapics >= MAX_IO_APICS) {
 167                 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
 168                         "(found %d)\n", MAX_IO_APICS, nr_ioapics);
 169                 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
 170         }
 171         if (!address) {
 172                 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
 173                         " found in table, skipping!\n");
 174                 return 1;
 175         }
 176         return 0;
 177 }
 178
 179 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
 180 {
 181         if (!(m->mpc_flags & MPC_APIC_USABLE))
 182                 return;
 183
 184         printk("I/O APIC #%d at 0x%X.\n",
 185                 m->mpc_apicid, m->mpc_apicaddr);
 186
 187         if (bad_ioapic(m->mpc_apicaddr))
 188                 return;
 189
 190         mp_ioapics[nr_ioapics] = *m;
 191         nr_ioapics++;
 192 }
 193
 194 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
 195 {
 196         mp_irqs [mp_irq_entries] = *m;
 197         Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
 198                 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
 199                         m->mpc_irqtype, m->mpc_irqflag & 3,
 200                         (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
 201                         m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
 202         if (++mp_irq_entries >= MAX_IRQ_SOURCES)
 203                 panic("Max # of irq sources exceeded!!\n");
 204 }
 205
 206 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
 207 {
 208         Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
 209                 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
 210                         m->mpc_irqtype, m->mpc_irqflag & 3,
 211                         (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
 212                         m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
 213 }
 214
 215 /*
 216  * Read/parse the MPC
 217  */
 218
 219 static int __init smp_read_mpc(struct mp_config_table *mpc)
 220 {
 221         char str[16];
 222         int count=sizeof(*mpc);
 223         unsigned char *mpt=((unsigned char *)mpc)+count;
 224
 225         if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
 226                 printk("MPTABLE: bad signature [%c%c%c%c]!\n",
 227                         mpc->mpc_signature[0],
 228                         mpc->mpc_signature[1],
 229                         mpc->mpc_signature[2],
 230                         mpc->mpc_signature[3]);
 231                 return 0;
 232         }
 233         if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
 234                 printk("MPTABLE: checksum error!\n");
 235                 return 0;
 236         }
 237         if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
 238                 printk(KERN_ERR "MPTABLE: bad table version (%d)!!\n",
 239                         mpc->mpc_spec);
 240                 return 0;
 241         }
 242         if (!mpc->mpc_lapic) {
 243                 printk(KERN_ERR "MPTABLE: null local APIC address!\n");
 244                 return 0;
 245         }
 246         memcpy(str,mpc->mpc_oem,8);
 247         str[8] = 0;
 248         printk(KERN_INFO "MPTABLE: OEM ID: %s ",str);
 249
 250         memcpy(str,mpc->mpc_productid,12);
 251         str[12] = 0;
 252         printk("MPTABLE: Product ID: %s ",str);
 253
 254         printk("MPTABLE: APIC at: 0x%X\n",mpc->mpc_lapic);
 255
 256         /* save the local APIC address, it might be non-default */
 257         if (!acpi_lapic)
 258                 mp_lapic_addr = mpc->mpc_lapic;
 259
 260         /*
 261          *      Now process the configuration blocks.
 262          */
 263         while (count < mpc->mpc_length) {
 264                 switch(*mpt) {
 265                         case MP_PROCESSOR:
 266                         {
 267                                 struct mpc_config_processor *m=
 268                                         (struct mpc_config_processor *)mpt;
 269                                 if (!acpi_lapic)
 270                                         MP_processor_info(m);
 271                                 mpt += sizeof(*m);
 272                                 count += sizeof(*m);
 273                                 break;
 274                         }
 275                         case MP_BUS:
 276                         {
 277                                 struct mpc_config_bus *m=
 278                                         (struct mpc_config_bus *)mpt;
 279                                 MP_bus_info(m);
 280                                 mpt += sizeof(*m);
 281                                 count += sizeof(*m);
 282                                 break;
 283                         }
 284                         case MP_IOAPIC:
 285                         {
 286                                 struct mpc_config_ioapic *m=
 287                                         (struct mpc_config_ioapic *)mpt;
 288                                 MP_ioapic_info(m);
 289                                 mpt += sizeof(*m);
 290                                 count += sizeof(*m);
 291                                 break;
 292                         }
 293                         case MP_INTSRC:
 294                         {
 295                                 struct mpc_config_intsrc *m=
 296                                         (struct mpc_config_intsrc *)mpt;
 297
 298                                 MP_intsrc_info(m);
 299                                 mpt += sizeof(*m);
 300                                 count += sizeof(*m);
 301                                 break;
 302                         }
 303                         case MP_LINTSRC:
 304                         {
 305                                 struct mpc_config_lintsrc *m=
 306                                         (struct mpc_config_lintsrc *)mpt;
 307                                 MP_lintsrc_info(m);
 308                                 mpt += sizeof(*m);
 309                                 count += sizeof(*m);
 310                                 break;
 311                         }
 312                 }
 313         }
 314         setup_apic_routing();
 315         if (!num_processors)
 316                 printk(KERN_ERR "MPTABLE: no processors registered!\n");
 317         return num_processors;
 318 }
 319
 320 static int __init ELCR_trigger(unsigned int irq)
 321 {
 322         unsigned int port;
 323
 324         port = 0x4d0 + (irq >> 3);
 325         return (inb(port) >> (irq & 7)) & 1;
 326 }
 327
 328 static void __init construct_default_ioirq_mptable(int mpc_default_type)
 329 {
 330         struct mpc_config_intsrc intsrc;
 331         int i;
 332         int ELCR_fallback = 0;
 333
 334         intsrc.mpc_type = MP_INTSRC;
 335         intsrc.mpc_irqflag = 0;                 /* conforming */
 336         intsrc.mpc_srcbus = 0;
 337         intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
 338
 339         intsrc.mpc_irqtype = mp_INT;
 340
 341         /*
 342          *  If true, we have an ISA/PCI system with no IRQ entries
 343          *  in the MP table. To prevent the PCI interrupts from being set up
 344          *  incorrectly, we try to use the ELCR. The sanity check to see if
 345          *  there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
 346          *  never be level sensitive, so we simply see if the ELCR agrees.
 347          *  If it does, we assume it's valid.
 348          */
 349         if (mpc_default_type == 5) {
 350                 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
 351
 352                 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
 353                         printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
 354                 else {
 355                         printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
 356                         ELCR_fallback = 1;
 357                 }
 358         }
 359
 360         for (i = 0; i < 16; i++) {
 361                 switch (mpc_default_type) {
 362                 case 2:
 363                         if (i == 0 || i == 13)
 364                                 continue;       /* IRQ0 & IRQ13 not connected */
 365                         /* fall through */
 366                 default:
 367                         if (i == 2)
 368                                 continue;       /* IRQ2 is never connected */
 369                 }
 370
 371                 if (ELCR_fallback) {
 372                         /*
 373                          *  If the ELCR indicates a level-sensitive interrupt, we
 374                          *  copy that information over to the MP table in the
 375                          *  irqflag field (level sensitive, active high polarity).
 376                          */
 377                         if (ELCR_trigger(i))
 378                                 intsrc.mpc_irqflag = 13;
 379                         else
 380                                 intsrc.mpc_irqflag = 0;
 381                 }
 382
 383                 intsrc.mpc_srcbusirq = i;
 384                 intsrc.mpc_dstirq = i ? i : 2;          /* IRQ0 to INTIN2 */
 385                 MP_intsrc_info(&intsrc);
 386         }
 387
 388         intsrc.mpc_irqtype = mp_ExtINT;
 389         intsrc.mpc_srcbusirq = 0;
 390         intsrc.mpc_dstirq = 0;                          /* 8259A to INTIN0 */
 391         MP_intsrc_info(&intsrc);
 392 }
 393
 394 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
 395 {
 396         struct mpc_config_processor processor;
 397         struct mpc_config_bus bus;
 398         struct mpc_config_ioapic ioapic;
 399         struct mpc_config_lintsrc lintsrc;
 400         int linttypes[2] = { mp_ExtINT, mp_NMI };
 401         int i;
 402
 403         /*
 404          * local APIC has default address
 405          */
 406         mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
 407
 408         /*
 409          * 2 CPUs, numbered 0 & 1.
 410          */
 411         processor.mpc_type = MP_PROCESSOR;
 412         processor.mpc_apicver = 0;
 413         processor.mpc_cpuflag = CPU_ENABLED;
 414         processor.mpc_cpufeature = 0;
 415         processor.mpc_featureflag = 0;
 416         processor.mpc_reserved[0] = 0;
 417         processor.mpc_reserved[1] = 0;
 418         for (i = 0; i < 2; i++) {
 419                 processor.mpc_apicid = i;
 420                 MP_processor_info(&processor);
 421         }
 422
 423         bus.mpc_type = MP_BUS;
 424         bus.mpc_busid = 0;
 425         switch (mpc_default_type) {
 426                 default:
 427                         printk(KERN_ERR "???\nUnknown standard configuration %d\n",
 428                                 mpc_default_type);
 429                         /* fall through */
 430                 case 1:
 431                 case 5:
 432                         memcpy(bus.mpc_bustype, "ISA   ", 6);
 433                         break;
 434         }
 435         MP_bus_info(&bus);
 436         if (mpc_default_type > 4) {
 437                 bus.mpc_busid = 1;
 438                 memcpy(bus.mpc_bustype, "PCI   ", 6);
 439                 MP_bus_info(&bus);
 440         }
 441
 442         ioapic.mpc_type = MP_IOAPIC;
 443         ioapic.mpc_apicid = 2;
 444         ioapic.mpc_apicver = 0;
 445         ioapic.mpc_flags = MPC_APIC_USABLE;
 446         ioapic.mpc_apicaddr = 0xFEC00000;
 447         MP_ioapic_info(&ioapic);
 448
 449         /*
 450          * We set up most of the low 16 IO-APIC pins according to MPS rules.
 451          */
 452         construct_default_ioirq_mptable(mpc_default_type);
 453
 454         lintsrc.mpc_type = MP_LINTSRC;
 455         lintsrc.mpc_irqflag = 0;                /* conforming */
 456         lintsrc.mpc_srcbusid = 0;
 457         lintsrc.mpc_srcbusirq = 0;
 458         lintsrc.mpc_destapic = MP_APIC_ALL;
 459         for (i = 0; i < 2; i++) {
 460                 lintsrc.mpc_irqtype = linttypes[i];
 461                 lintsrc.mpc_destapiclint = i;
 462                 MP_lintsrc_info(&lintsrc);
 463         }
 464 }
 465
 466 static struct intel_mp_floating *mpf_found;
 467
 468 /*
 469  * Scan the memory blocks for an SMP configuration block.
 470  */
 471 void __init get_smp_config (void)
 472 {
 473         struct intel_mp_floating *mpf = mpf_found;
 474
 475         /*
 476          * ACPI supports both logical (e.g. Hyper-Threading) and physical
 477          * processors, where MPS only supports physical.
 478          */
 479         if (acpi_lapic && acpi_ioapic) {
 480                 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
 481                 return;
 482         }
 483         else if (acpi_lapic)
 484                 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
 485
 486         printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
 487
 488         /*
 489          * Now see if we need to read further.
 490          */
 491         if (mpf->mpf_feature1 != 0) {
 492
 493                 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
 494                 construct_default_ISA_mptable(mpf->mpf_feature1);
 495
 496         } else if (mpf->mpf_physptr) {
 497
 498                 /*
 499                  * Read the physical hardware table.  Anything here will
 500                  * override the defaults.
 501                  */
 502                 if (!smp_read_mpc(phys_to_virt(mpf->mpf_physptr))) {
 503                         smp_found_config = 0;
 504                         printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
 505                         printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
 506                         return;
 507                 }
 508                 /*
 509                  * If there are no explicit MP IRQ entries, then we are
 510                  * broken.  We set up most of the low 16 IO-APIC pins to
 511                  * ISA defaults and hope it will work.
 512                  */
 513                 if (!mp_irq_entries) {
 514                         struct mpc_config_bus bus;
 515
 516                         printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
 517
 518                         bus.mpc_type = MP_BUS;
 519                         bus.mpc_busid = 0;
 520                         memcpy(bus.mpc_bustype, "ISA   ", 6);
 521                         MP_bus_info(&bus);
 522
 523                         construct_default_ioirq_mptable(0);
 524                 }
 525
 526         } else
 527                 BUG();
 528
 529         printk(KERN_INFO "Processors: %d\n", num_processors);
 530         /*
 531          * Only use the first configuration found.
 532          */
 533 }
 534
 535 static int __init smp_scan_config (unsigned long base, unsigned long length)
 536 {
 537         extern void __bad_mpf_size(void);
 538         unsigned int *bp = phys_to_virt(base);
 539         struct intel_mp_floating *mpf;
 540
 541         Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
 542         if (sizeof(*mpf) != 16)
 543                 __bad_mpf_size();
 544
 545         while (length > 0) {
 546                 mpf = (struct intel_mp_floating *)bp;
 547                 if ((*bp == SMP_MAGIC_IDENT) &&
 548                         (mpf->mpf_length == 1) &&
 549                         !mpf_checksum((unsigned char *)bp, 16) &&
 550                         ((mpf->mpf_specification == 1)
 551                                 || (mpf->mpf_specification == 4)) ) {
 552
 553                         smp_found_config = 1;
 554                         reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
 555                         if (mpf->mpf_physptr)
 556                                 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
 557                         mpf_found = mpf;
 558                         return 1;
 559                 }
 560                 bp += 4;
 561                 length -= 16;
 562         }
 563         return 0;
 564 }
 565
 566 void __init find_smp_config(void)
 567 {
 568         unsigned int address;
 569
 570         /*
 571          * FIXME: Linux assumes you have 640K of base ram..
 572          * this continues the error...
 573          *
 574          * 1) Scan the bottom 1K for a signature
 575          * 2) Scan the top 1K of base RAM
 576          * 3) Scan the 64K of bios
 577          */
 578         if (smp_scan_config(0x0,0x400) ||
 579                 smp_scan_config(639*0x400,0x400) ||
 580                         smp_scan_config(0xF0000,0x10000))
 581                 return;
 582         /*
 583          * If it is an SMP machine we should know now.
 584          *
 585          * there is a real-mode segmented pointer pointing to the
 586          * 4K EBDA area at 0x40E, calculate and scan it here.
 587          *
 588          * NOTE! There are Linux loaders that will corrupt the EBDA
 589          * area, and as such this kind of SMP config may be less
 590          * trustworthy, simply because the SMP table may have been
 591          * stomped on during early boot. These loaders are buggy and
 592          * should be fixed.
 593          */
 594
 595         address = *(unsigned short *)phys_to_virt(0x40E);
 596         address <<= 4;
 597         if (smp_scan_config(address, 0x1000))
 598                 return;
 599
 600         /* If we have come this far, we did not find an MP table  */
 601          printk(KERN_INFO "No mptable found.\n");
 602 }
 603
 604 /* --------------------------------------------------------------------------
 605                             ACPI-based MP Configuration
 606    -------------------------------------------------------------------------- */
 607
 608 #ifdef CONFIG_ACPI
 609
 610 void __init mp_register_lapic_address(u64 address)
 611 {
 612         mp_lapic_addr = (unsigned long) address;
 613         set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
 614         if (boot_cpu_id == -1U)
 615                 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
 616 }
 617
 618 void __cpuinit mp_register_lapic (u8 id, u8 enabled)
 619 {
 620         struct mpc_config_processor processor;
 621         int                     boot_cpu = 0;
 622
 623         if (id == boot_cpu_id)
 624                 boot_cpu = 1;
 625
 626         processor.mpc_type = MP_PROCESSOR;
 627         processor.mpc_apicid = id;
 628         processor.mpc_apicver = 0;
 629         processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
 630         processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
 631         processor.mpc_cpufeature = 0;
 632         processor.mpc_featureflag = 0;
 633         processor.mpc_reserved[0] = 0;
 634         processor.mpc_reserved[1] = 0;
 635
 636         MP_processor_info(&processor);
 637 }
 638
 639 #define MP_ISA_BUS              0
 640 #define MP_MAX_IOAPIC_PIN       127
 641
 642 static struct mp_ioapic_routing {
 643         int                     apic_id;
 644         int                     gsi_start;
 645         int                     gsi_end;
 646         u32                     pin_programmed[4];
 647 } mp_ioapic_routing[MAX_IO_APICS];
 648
 649 static int mp_find_ioapic(int gsi)
 650 {
 651         int i = 0;
 652
 653         /* Find the IOAPIC that manages this GSI. */
 654         for (i = 0; i < nr_ioapics; i++) {
 655                 if ((gsi >= mp_ioapic_routing[i].gsi_start)
 656                         && (gsi <= mp_ioapic_routing[i].gsi_end))
 657                         return i;
 658         }
 659
 660         printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
 661         return -1;
 662 }
 663
 664 static u8 uniq_ioapic_id(u8 id)
 665 {
 666         int i;
 667         DECLARE_BITMAP(used, 256);
 668         bitmap_zero(used, 256);
 669         for (i = 0; i < nr_ioapics; i++) {
 670                 struct mpc_config_ioapic *ia = &mp_ioapics[i];
 671                 __set_bit(ia->mpc_apicid, used);
 672         }
 673         if (!test_bit(id, used))
 674                 return id;
 675         return find_first_zero_bit(used, 256);
 676 }
 677
 678 void __init mp_register_ioapic(u8 id, u32 address, u32 gsi_base)
 679 {
 680         int idx = 0;
 681
 682         if (bad_ioapic(address))
 683                 return;
 684
 685         idx = nr_ioapics;
 686
 687         mp_ioapics[idx].mpc_type = MP_IOAPIC;
 688         mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
 689         mp_ioapics[idx].mpc_apicaddr = address;
 690
 691         set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
 692         mp_ioapics[idx].mpc_apicid = uniq_ioapic_id(id);
 693         mp_ioapics[idx].mpc_apicver = 0;
 694
 695         /*
 696          * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
 697          * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
 698          */
 699         mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
 700         mp_ioapic_routing[idx].gsi_start = gsi_base;
 701         mp_ioapic_routing[idx].gsi_end = gsi_base +
 702                 io_apic_get_redir_entries(idx);
 703
 704         printk(KERN_INFO "IOAPIC[%d]: apic_id %d, address 0x%x, "
 705                 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
 706                 mp_ioapics[idx].mpc_apicaddr,
 707                 mp_ioapic_routing[idx].gsi_start,
 708                 mp_ioapic_routing[idx].gsi_end);
 709
 710         nr_ioapics++;
 711 }
 712
 713 void __init
 714 mp_override_legacy_irq(u8 bus_irq, u8 polarity, u8 trigger, u32 gsi)
 715 {
 716         struct mpc_config_intsrc intsrc;
 717         int                     ioapic = -1;
 718         int                     pin = -1;
 719
 720         /*
 721          * Convert 'gsi' to 'ioapic.pin'.
 722          */
 723         ioapic = mp_find_ioapic(gsi);
 724         if (ioapic < 0)
 725                 return;
 726         pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
 727
 728         /*
 729          * TBD: This check is for faulty timer entries, where the override
 730          *      erroneously sets the trigger to level, resulting in a HUGE
 731          *      increase of timer interrupts!
 732          */
 733         if ((bus_irq == 0) && (trigger == 3))
 734                 trigger = 1;
 735
 736         intsrc.mpc_type = MP_INTSRC;
 737         intsrc.mpc_irqtype = mp_INT;
 738         intsrc.mpc_irqflag = (trigger << 2) | polarity;
 739         intsrc.mpc_srcbus = MP_ISA_BUS;
 740         intsrc.mpc_srcbusirq = bus_irq;                                /* IRQ */
 741         intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;        /* APIC ID */
 742         intsrc.mpc_dstirq = pin;                                    /* INTIN# */
 743
 744         Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
 745                 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
 746                 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
 747                 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
 748
 749         mp_irqs[mp_irq_entries] = intsrc;
 750         if (++mp_irq_entries == MAX_IRQ_SOURCES)
 751                 panic("Max # of irq sources exceeded!\n");
 752 }
 753
 754 void __init mp_config_acpi_legacy_irqs(void)
 755 {
 756         struct mpc_config_intsrc intsrc;
 757         int i = 0;
 758         int ioapic = -1;
 759
 760         /*
 761          * Fabricate the legacy ISA bus (bus #31).
 762          */
 763         set_bit(MP_ISA_BUS, mp_bus_not_pci);
 764
 765         /*
 766          * Locate the IOAPIC that manages the ISA IRQs (0-15).
 767          */
 768         ioapic = mp_find_ioapic(0);
 769         if (ioapic < 0)
 770                 return;
 771
 772         intsrc.mpc_type = MP_INTSRC;
 773         intsrc.mpc_irqflag = 0;                                 /* Conforming */
 774         intsrc.mpc_srcbus = MP_ISA_BUS;
 775         intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
 776
 777         /*
 778          * Use the default configuration for the IRQs 0-15.  Unless
 779          * overridden by (MADT) interrupt source override entries.
 780          */
 781         for (i = 0; i < 16; i++) {
 782                 int idx;
 783
 784                 for (idx = 0; idx < mp_irq_entries; idx++) {
 785                         struct mpc_config_intsrc *irq = mp_irqs + idx;
 786
 787                         /* Do we already have a mapping for this ISA IRQ? */
 788                         if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
 789                                 break;
 790
 791                         /* Do we already have a mapping for this IOAPIC pin */
 792                         if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
 793                                 (irq->mpc_dstirq == i))
 794                                 break;
 795                 }
 796
 797                 if (idx != mp_irq_entries) {
 798                         printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
 799                         continue;                       /* IRQ already used */
 800                 }
 801
 802                 intsrc.mpc_irqtype = mp_INT;
 803                 intsrc.mpc_srcbusirq = i;                  /* Identity mapped */
 804                 intsrc.mpc_dstirq = i;
 805
 806                 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
 807                         "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
 808                         (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
 809                         intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
 810                         intsrc.mpc_dstirq);
 811
 812                 mp_irqs[mp_irq_entries] = intsrc;
 813                 if (++mp_irq_entries == MAX_IRQ_SOURCES)
 814                         panic("Max # of irq sources exceeded!\n");
 815         }
 816 }
 817
 818 int mp_register_gsi(u32 gsi, int triggering, int polarity)
 819 {
 820         int ioapic = -1;
 821         int ioapic_pin = 0;
 822         int idx, bit = 0;
 823
 824         if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
 825                 return gsi;
 826
 827         /* Don't set up the ACPI SCI because it's already set up */
 828         if (acpi_gbl_FADT.sci_interrupt == gsi)
 829                 return gsi;
 830
 831         ioapic = mp_find_ioapic(gsi);
 832         if (ioapic < 0) {
 833                 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
 834                 return gsi;
 835         }
 836
 837         ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
 838
 839         /*
 840          * Avoid pin reprogramming.  PRTs typically include entries
 841          * with redundant pin->gsi mappings (but unique PCI devices);
 842          * we only program the IOAPIC on the first.
 843          */
 844         bit = ioapic_pin % 32;
 845         idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
 846         if (idx > 3) {
 847                 printk(KERN_ERR "Invalid reference to IOAPIC pin "
 848                         "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
 849                         ioapic_pin);
 850                 return gsi;
 851         }
 852         if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
 853                 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
 854                         mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
 855                 return gsi;
 856         }
 857
 858         mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
 859
 860         io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
 861                 triggering == ACPI_EDGE_SENSITIVE ? 0 : 1,
 862                 polarity == ACPI_ACTIVE_HIGH ? 0 : 1);
 863         return gsi;
 864 }
 865 #endif /*CONFIG_ACPI*/