2 * Firmware replacement code.
4 * Work around broken BIOSes that don't set an aperture or only set the
5 * aperture in the AGP bridge.
6 * If all fails map the aperture over some low memory. This is cheaper than
7 * doing bounce buffering. The memory is lost. This is done at early boot
8 * because only the bootmem allocator can allocate 32+MB.
10 * Copyright 2002 Andi Kleen, SuSE Labs.
12 #include <linux/kernel.h>
13 #include <linux/types.h>
14 #include <linux/init.h>
15 #include <linux/bootmem.h>
16 #include <linux/mmzone.h>
17 #include <linux/pci_ids.h>
18 #include <linux/pci.h>
19 #include <linux/bitops.h>
20 #include <linux/ioport.h>
24 #include <asm/pci-direct.h>
28 int gart_iommu_aperture
;
29 int gart_iommu_aperture_disabled __initdata
= 0;
30 int gart_iommu_aperture_allowed __initdata
= 0;
32 int fallback_aper_order __initdata
= 1; /* 64MB */
33 int fallback_aper_force __initdata
= 0;
35 int fix_aperture __initdata
= 1;
37 static struct resource gart_resource
= {
39 .flags
= IORESOURCE_MEM
,
42 static void __init
insert_aperture_resource(u32 aper_base
, u32 aper_size
)
44 gart_resource
.start
= aper_base
;
45 gart_resource
.end
= aper_base
+ aper_size
- 1;
46 insert_resource(&iomem_resource
, &gart_resource
);
49 /* This code runs before the PCI subsystem is initialized, so just
50 access the northbridge directly. */
52 static u32 __init
allocate_aperture(void)
57 if (fallback_aper_order
> 7)
58 fallback_aper_order
= 7;
59 aper_size
= (32 * 1024 * 1024) << fallback_aper_order
;
62 * Aperture has to be naturally aligned. This means a 2GB aperture
63 * won't have much chance of finding a place in the lower 4GB of
64 * memory. Unfortunately we cannot move it up because that would
65 * make the IOMMU useless.
67 p
= __alloc_bootmem_nopanic(aper_size
, aper_size
, 0);
68 if (!p
|| __pa(p
)+aper_size
> 0xffffffff) {
70 "Cannot allocate aperture memory hole (%p,%uK)\n",
73 free_bootmem(__pa(p
), aper_size
);
76 printk(KERN_INFO
"Mapping aperture over %d KB of RAM @ %lx\n",
77 aper_size
>> 10, __pa(p
));
78 insert_aperture_resource((u32
)__pa(p
), aper_size
);
83 static int __init
aperture_valid(u64 aper_base
, u32 aper_size
)
88 if (aper_size
< 64*1024*1024) {
89 printk(KERN_ERR
"Aperture too small (%d MB)\n", aper_size
>>20);
92 if (aper_base
+ aper_size
> 0x100000000UL
) {
93 printk(KERN_ERR
"Aperture beyond 4GB. Ignoring.\n");
96 if (e820_any_mapped(aper_base
, aper_base
+ aper_size
, E820_RAM
)) {
97 printk(KERN_ERR
"Aperture pointing to e820 RAM. Ignoring.\n");
104 /* Find a PCI capability */
105 static __u32 __init
find_cap(int num
, int slot
, int func
, int cap
)
110 if (!(read_pci_config_16(num
, slot
, func
, PCI_STATUS
) &
111 PCI_STATUS_CAP_LIST
))
114 pos
= read_pci_config_byte(num
, slot
, func
, PCI_CAPABILITY_LIST
);
115 for (bytes
= 0; bytes
< 48 && pos
>= 0x40; bytes
++) {
119 id
= read_pci_config_byte(num
, slot
, func
, pos
+PCI_CAP_LIST_ID
);
124 pos
= read_pci_config_byte(num
, slot
, func
,
125 pos
+PCI_CAP_LIST_NEXT
);
130 /* Read a standard AGPv3 bridge header */
131 static __u32 __init
read_agp(int num
, int slot
, int func
, int cap
, u32
*order
)
136 u32 aper_low
, aper_hi
;
139 printk(KERN_INFO
"AGP bridge at %02x:%02x:%02x\n", num
, slot
, func
);
140 apsizereg
= read_pci_config_16(num
, slot
, func
, cap
+ 0x14);
141 if (apsizereg
== 0xffffffff) {
142 printk(KERN_ERR
"APSIZE in AGP bridge unreadable\n");
146 apsize
= apsizereg
& 0xfff;
147 /* Some BIOS use weird encodings not in the AGPv3 table. */
150 nbits
= hweight16(apsize
);
152 if ((int)*order
< 0) /* < 32MB */
155 aper_low
= read_pci_config(num
, slot
, func
, 0x10);
156 aper_hi
= read_pci_config(num
, slot
, func
, 0x14);
157 aper
= (aper_low
& ~((1<<22)-1)) | ((u64
)aper_hi
<< 32);
159 printk(KERN_INFO
"Aperture from AGP @ %Lx size %u MB (APSIZE %x)\n",
160 aper
, 32 << *order
, apsizereg
);
162 if (!aperture_valid(aper
, (32*1024*1024) << *order
))
168 * Look for an AGP bridge. Windows only expects the aperture in the
169 * AGP bridge and some BIOS forget to initialize the Northbridge too.
170 * Work around this here.
172 * Do an PCI bus scan by hand because we're running before the PCI
175 * All K8 AGP bridges are AGPv3 compliant, so we can do this scan
176 * generically. It's probably overkill to always scan all slots because
177 * the AGP bridges should be always an own bus on the HT hierarchy,
178 * but do it here for future safety.
180 static __u32 __init
search_agp_bridge(u32
*order
, int *valid_agp
)
184 /* Poor man's PCI discovery */
185 for (num
= 0; num
< 256; num
++) {
186 for (slot
= 0; slot
< 32; slot
++) {
187 for (func
= 0; func
< 8; func
++) {
190 class = read_pci_config(num
, slot
, func
,
192 if (class == 0xffffffff)
195 switch (class >> 16) {
196 case PCI_CLASS_BRIDGE_HOST
:
197 case PCI_CLASS_BRIDGE_OTHER
: /* needed? */
199 cap
= find_cap(num
, slot
, func
,
204 return read_agp(num
, slot
, func
, cap
,
208 /* No multi-function device? */
209 type
= read_pci_config_byte(num
, slot
, func
,
216 printk(KERN_INFO
"No AGP bridge found\n");
221 void __init
gart_iommu_hole_init(void)
223 u32 aper_size
, aper_alloc
= 0, aper_order
= 0, last_aper_order
= 0;
224 u64 aper_base
, last_aper_base
= 0;
225 int fix
, num
, valid_agp
= 0;
227 if (gart_iommu_aperture_disabled
|| !fix_aperture
||
228 !early_pci_allowed())
231 printk(KERN_INFO
"Checking aperture...\n");
234 for (num
= 24; num
< 32; num
++) {
235 if (!early_is_k8_nb(read_pci_config(0, num
, 3, 0x00)))
239 gart_iommu_aperture
= 1;
241 aper_order
= (read_pci_config(0, num
, 3, 0x90) >> 1) & 7;
242 aper_size
= (32 * 1024 * 1024) << aper_order
;
243 aper_base
= read_pci_config(0, num
, 3, 0x94) & 0x7fff;
246 printk(KERN_INFO
"CPU %d: aperture @ %Lx size %u MB\n",
247 num
-24, aper_base
, aper_size
>>20);
249 if (!aperture_valid(aper_base
, aper_size
)) {
254 if ((last_aper_order
&& aper_order
!= last_aper_order
) ||
255 (last_aper_base
&& aper_base
!= last_aper_base
)) {
259 last_aper_order
= aper_order
;
260 last_aper_base
= aper_base
;
263 if (!fix
&& !fallback_aper_force
) {
264 if (last_aper_base
) {
265 unsigned long n
= (32 * 1024 * 1024) << last_aper_order
;
267 insert_aperture_resource((u32
)last_aper_base
, n
);
272 if (!fallback_aper_force
)
273 aper_alloc
= search_agp_bridge(&aper_order
, &valid_agp
);
276 /* Got the aperture from the AGP bridge */
277 } else if (swiotlb
&& !valid_agp
) {
279 } else if ((!no_iommu
&& end_pfn
> MAX_DMA32_PFN
) ||
282 fallback_aper_force
) {
284 "Your BIOS doesn't leave a aperture memory hole\n");
286 "Please enable the IOMMU option in the BIOS setup\n");
288 "This costs you %d MB of RAM\n",
289 32 << fallback_aper_order
);
291 aper_order
= fallback_aper_order
;
292 aper_alloc
= allocate_aperture();
295 * Could disable AGP and IOMMU here, but it's
296 * probably not worth it. But the later users
297 * cannot deal with bad apertures and turning
298 * on the aperture over memory causes very
299 * strange problems, so it's better to panic
302 panic("Not enough memory for aperture");
308 /* Fix up the north bridges */
309 for (num
= 24; num
< 32; num
++) {
310 if (!early_is_k8_nb(read_pci_config(0, num
, 3, 0x00)))
314 * Don't enable translation yet. That is done later.
315 * Assume this BIOS didn't initialise the GART so
316 * just overwrite all previous bits
318 write_pci_config(0, num
, 3, 0x90, aper_order
<<1);
319 write_pci_config(0, num
, 3, 0x94, aper_alloc
>>25);