drivers/spi/spi-sirf.c

   1 /*
   2  * SPI bus driver for CSR SiRFprimaII
   3  *
   4  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   5  *
   6  * Licensed under GPLv2 or later.
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/kernel.h>
  11 #include <linux/slab.h>
  12 #include <linux/clk.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/io.h>
  15 #include <linux/of.h>
  16 #include <linux/bitops.h>
  17 #include <linux/err.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/of_gpio.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/spi/spi_bitbang.h>
  22 #include <linux/pinctrl/pinmux.h>
  23
  24 #define DRIVER_NAME "sirfsoc_spi"
  25
  26 #define SIRFSOC_SPI_CTRL                0x0000
  27 #define SIRFSOC_SPI_CMD                 0x0004
  28 #define SIRFSOC_SPI_TX_RX_EN            0x0008
  29 #define SIRFSOC_SPI_INT_EN              0x000C
  30 #define SIRFSOC_SPI_INT_STATUS          0x0010
  31 #define SIRFSOC_SPI_TX_DMA_IO_CTRL      0x0100
  32 #define SIRFSOC_SPI_TX_DMA_IO_LEN       0x0104
  33 #define SIRFSOC_SPI_TXFIFO_CTRL         0x0108
  34 #define SIRFSOC_SPI_TXFIFO_LEVEL_CHK    0x010C
  35 #define SIRFSOC_SPI_TXFIFO_OP           0x0110
  36 #define SIRFSOC_SPI_TXFIFO_STATUS       0x0114
  37 #define SIRFSOC_SPI_TXFIFO_DATA         0x0118
  38 #define SIRFSOC_SPI_RX_DMA_IO_CTRL      0x0120
  39 #define SIRFSOC_SPI_RX_DMA_IO_LEN       0x0124
  40 #define SIRFSOC_SPI_RXFIFO_CTRL         0x0128
  41 #define SIRFSOC_SPI_RXFIFO_LEVEL_CHK    0x012C
  42 #define SIRFSOC_SPI_RXFIFO_OP           0x0130
  43 #define SIRFSOC_SPI_RXFIFO_STATUS       0x0134
  44 #define SIRFSOC_SPI_RXFIFO_DATA         0x0138
  45 #define SIRFSOC_SPI_DUMMY_DELAY_CTL     0x0144
  46
  47 /* SPI CTRL register defines */
  48 #define SIRFSOC_SPI_SLV_MODE            BIT(16)
  49 #define SIRFSOC_SPI_CMD_MODE            BIT(17)
  50 #define SIRFSOC_SPI_CS_IO_OUT           BIT(18)
  51 #define SIRFSOC_SPI_CS_IO_MODE          BIT(19)
  52 #define SIRFSOC_SPI_CLK_IDLE_STAT       BIT(20)
  53 #define SIRFSOC_SPI_CS_IDLE_STAT        BIT(21)
  54 #define SIRFSOC_SPI_TRAN_MSB            BIT(22)
  55 #define SIRFSOC_SPI_DRV_POS_EDGE        BIT(23)
  56 #define SIRFSOC_SPI_CS_HOLD_TIME        BIT(24)
  57 #define SIRFSOC_SPI_CLK_SAMPLE_MODE     BIT(25)
  58 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_8   (0 << 26)
  59 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_12  (1 << 26)
  60 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_16  (2 << 26)
  61 #define SIRFSOC_SPI_TRAN_DAT_FORMAT_32  (3 << 26)
  62 #define SIRFSOC_SPI_CMD_BYTE_NUM(x)             ((x & 3) << 28)
  63 #define SIRFSOC_SPI_ENA_AUTO_CLR                BIT(30)
  64 #define SIRFSOC_SPI_MUL_DAT_MODE                BIT(31)
  65
  66 /* Interrupt Enable */
  67 #define SIRFSOC_SPI_RX_DONE_INT_EN              BIT(0)
  68 #define SIRFSOC_SPI_TX_DONE_INT_EN              BIT(1)
  69 #define SIRFSOC_SPI_RX_OFLOW_INT_EN             BIT(2)
  70 #define SIRFSOC_SPI_TX_UFLOW_INT_EN             BIT(3)
  71 #define SIRFSOC_SPI_RX_IO_DMA_INT_EN    BIT(4)
  72 #define SIRFSOC_SPI_TX_IO_DMA_INT_EN    BIT(5)
  73 #define SIRFSOC_SPI_RXFIFO_FULL_INT_EN  BIT(6)
  74 #define SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN BIT(7)
  75 #define SIRFSOC_SPI_RXFIFO_THD_INT_EN   BIT(8)
  76 #define SIRFSOC_SPI_TXFIFO_THD_INT_EN   BIT(9)
  77 #define SIRFSOC_SPI_FRM_END_INT_EN      BIT(10)
  78
  79 #define SIRFSOC_SPI_INT_MASK_ALL                0x1FFF
  80
  81 /* Interrupt status */
  82 #define SIRFSOC_SPI_RX_DONE             BIT(0)
  83 #define SIRFSOC_SPI_TX_DONE             BIT(1)
  84 #define SIRFSOC_SPI_RX_OFLOW            BIT(2)
  85 #define SIRFSOC_SPI_TX_UFLOW            BIT(3)
  86 #define SIRFSOC_SPI_RX_FIFO_FULL        BIT(6)
  87 #define SIRFSOC_SPI_TXFIFO_EMPTY        BIT(7)
  88 #define SIRFSOC_SPI_RXFIFO_THD_REACH    BIT(8)
  89 #define SIRFSOC_SPI_TXFIFO_THD_REACH    BIT(9)
  90 #define SIRFSOC_SPI_FRM_END             BIT(10)
  91
  92 /* TX RX enable */
  93 #define SIRFSOC_SPI_RX_EN               BIT(0)
  94 #define SIRFSOC_SPI_TX_EN               BIT(1)
  95 #define SIRFSOC_SPI_CMD_TX_EN           BIT(2)
  96
  97 #define SIRFSOC_SPI_IO_MODE_SEL         BIT(0)
  98 #define SIRFSOC_SPI_RX_DMA_FLUSH        BIT(2)
  99
 100 /* FIFO OPs */
 101 #define SIRFSOC_SPI_FIFO_RESET          BIT(0)
 102 #define SIRFSOC_SPI_FIFO_START          BIT(1)
 103
 104 /* FIFO CTRL */
 105 #define SIRFSOC_SPI_FIFO_WIDTH_BYTE     (0 << 0)
 106 #define SIRFSOC_SPI_FIFO_WIDTH_WORD     (1 << 0)
 107 #define SIRFSOC_SPI_FIFO_WIDTH_DWORD    (2 << 0)
 108
 109 /* FIFO Status */
 110 #define SIRFSOC_SPI_FIFO_LEVEL_MASK     0xFF
 111 #define SIRFSOC_SPI_FIFO_FULL           BIT(8)
 112 #define SIRFSOC_SPI_FIFO_EMPTY          BIT(9)
 113
 114 /* 256 bytes rx/tx FIFO */
 115 #define SIRFSOC_SPI_FIFO_SIZE           256
 116 #define SIRFSOC_SPI_DAT_FRM_LEN_MAX     (64 * 1024)
 117
 118 #define SIRFSOC_SPI_FIFO_SC(x)          ((x) & 0x3F)
 119 #define SIRFSOC_SPI_FIFO_LC(x)          (((x) & 0x3F) << 10)
 120 #define SIRFSOC_SPI_FIFO_HC(x)          (((x) & 0x3F) << 20)
 121 #define SIRFSOC_SPI_FIFO_THD(x)         (((x) & 0xFF) << 2)
 122
 123 struct sirfsoc_spi {
 124         struct spi_bitbang bitbang;
 125         struct completion done;
 126
 127         void __iomem *base;
 128         u32 ctrl_freq;  /* SPI controller clock speed */
 129         struct clk *clk;
 130         struct pinmux *pmx;
 131
 132         /* rx & tx bufs from the spi_transfer */
 133         const void *tx;
 134         void *rx;
 135
 136         /* place received word into rx buffer */
 137         void (*rx_word) (struct sirfsoc_spi *);
 138         /* get word from tx buffer for sending */
 139         void (*tx_word) (struct sirfsoc_spi *);
 140
 141         /* number of words left to be tranmitted/received */
 142         unsigned int left_tx_cnt;
 143         unsigned int left_rx_cnt;
 144
 145         /* tasklet to push tx msg into FIFO */
 146         struct tasklet_struct tasklet_tx;
 147
 148         int chipselect[0];
 149 };
 150
 151 static void spi_sirfsoc_rx_word_u8(struct sirfsoc_spi *sspi)
 152 {
 153         u32 data;
 154         u8 *rx = sspi->rx;
 155
 156         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 157
 158         if (rx) {
 159                 *rx++ = (u8) data;
 160                 sspi->rx = rx;
 161         }
 162
 163         sspi->left_rx_cnt--;
 164 }
 165
 166 static void spi_sirfsoc_tx_word_u8(struct sirfsoc_spi *sspi)
 167 {
 168         u32 data = 0;
 169         const u8 *tx = sspi->tx;
 170
 171         if (tx) {
 172                 data = *tx++;
 173                 sspi->tx = tx;
 174         }
 175
 176         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 177         sspi->left_tx_cnt--;
 178 }
 179
 180 static void spi_sirfsoc_rx_word_u16(struct sirfsoc_spi *sspi)
 181 {
 182         u32 data;
 183         u16 *rx = sspi->rx;
 184
 185         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 186
 187         if (rx) {
 188                 *rx++ = (u16) data;
 189                 sspi->rx = rx;
 190         }
 191
 192         sspi->left_rx_cnt--;
 193 }
 194
 195 static void spi_sirfsoc_tx_word_u16(struct sirfsoc_spi *sspi)
 196 {
 197         u32 data = 0;
 198         const u16 *tx = sspi->tx;
 199
 200         if (tx) {
 201                 data = *tx++;
 202                 sspi->tx = tx;
 203         }
 204
 205         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 206         sspi->left_tx_cnt--;
 207 }
 208
 209 static void spi_sirfsoc_rx_word_u32(struct sirfsoc_spi *sspi)
 210 {
 211         u32 data;
 212         u32 *rx = sspi->rx;
 213
 214         data = readl(sspi->base + SIRFSOC_SPI_RXFIFO_DATA);
 215
 216         if (rx) {
 217                 *rx++ = (u32) data;
 218                 sspi->rx = rx;
 219         }
 220
 221         sspi->left_rx_cnt--;
 222
 223 }
 224
 225 static void spi_sirfsoc_tx_word_u32(struct sirfsoc_spi *sspi)
 226 {
 227         u32 data = 0;
 228         const u32 *tx = sspi->tx;
 229
 230         if (tx) {
 231                 data = *tx++;
 232                 sspi->tx = tx;
 233         }
 234
 235         writel(data, sspi->base + SIRFSOC_SPI_TXFIFO_DATA);
 236         sspi->left_tx_cnt--;
 237 }
 238
 239 static void spi_sirfsoc_tasklet_tx(unsigned long arg)
 240 {
 241         struct sirfsoc_spi *sspi = (struct sirfsoc_spi *)arg;
 242
 243         /* Fill Tx FIFO while there are left words to be transmitted */
 244         while (!((readl(sspi->base + SIRFSOC_SPI_TXFIFO_STATUS) &
 245                         SIRFSOC_SPI_FIFO_FULL)) &&
 246                         sspi->left_tx_cnt)
 247                 sspi->tx_word(sspi);
 248 }
 249
 250 static irqreturn_t spi_sirfsoc_irq(int irq, void *dev_id)
 251 {
 252         struct sirfsoc_spi *sspi = dev_id;
 253         u32 spi_stat = readl(sspi->base + SIRFSOC_SPI_INT_STATUS);
 254
 255         writel(spi_stat, sspi->base + SIRFSOC_SPI_INT_STATUS);
 256
 257         /* Error Conditions */
 258         if (spi_stat & SIRFSOC_SPI_RX_OFLOW ||
 259                         spi_stat & SIRFSOC_SPI_TX_UFLOW) {
 260                 complete(&sspi->done);
 261                 writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 262         }
 263
 264         if (spi_stat & SIRFSOC_SPI_FRM_END) {
 265                 while (!((readl(sspi->base + SIRFSOC_SPI_RXFIFO_STATUS)
 266                                 & SIRFSOC_SPI_FIFO_EMPTY)) &&
 267                                 sspi->left_rx_cnt)
 268                         sspi->rx_word(sspi);
 269
 270                 /* Received all words */
 271                 if ((sspi->left_rx_cnt == 0) && (sspi->left_tx_cnt == 0)) {
 272                         complete(&sspi->done);
 273                         writel(0x0, sspi->base + SIRFSOC_SPI_INT_EN);
 274                 }
 275         }
 276
 277         if (spi_stat & SIRFSOC_SPI_RXFIFO_THD_REACH ||
 278                 spi_stat & SIRFSOC_SPI_TXFIFO_THD_REACH ||
 279                 spi_stat & SIRFSOC_SPI_RX_FIFO_FULL ||
 280                 spi_stat & SIRFSOC_SPI_TXFIFO_EMPTY)
 281                 tasklet_schedule(&sspi->tasklet_tx);
 282
 283         return IRQ_HANDLED;
 284 }
 285
 286 static int spi_sirfsoc_transfer(struct spi_device *spi, struct spi_transfer *t)
 287 {
 288         struct sirfsoc_spi *sspi;
 289         int timeout = t->len * 10;
 290         sspi = spi_master_get_devdata(spi->master);
 291
 292         sspi->tx = t->tx_buf;
 293         sspi->rx = t->rx_buf;
 294         sspi->left_tx_cnt = sspi->left_rx_cnt = t->len;
 295         INIT_COMPLETION(sspi->done);
 296
 297         writel(SIRFSOC_SPI_INT_MASK_ALL, sspi->base + SIRFSOC_SPI_INT_STATUS);
 298
 299         if (t->len == 1) {
 300                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 301                         SIRFSOC_SPI_ENA_AUTO_CLR,
 302                         sspi->base + SIRFSOC_SPI_CTRL);
 303                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 304                 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 305         } else if ((t->len > 1) && (t->len < SIRFSOC_SPI_DAT_FRM_LEN_MAX)) {
 306                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL) |
 307                                 SIRFSOC_SPI_MUL_DAT_MODE |
 308                                 SIRFSOC_SPI_ENA_AUTO_CLR,
 309                         sspi->base + SIRFSOC_SPI_CTRL);
 310                 writel(t->len - 1, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 311                 writel(t->len - 1, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 312         } else {
 313                 writel(readl(sspi->base + SIRFSOC_SPI_CTRL),
 314                         sspi->base + SIRFSOC_SPI_CTRL);
 315                 writel(0, sspi->base + SIRFSOC_SPI_TX_DMA_IO_LEN);
 316                 writel(0, sspi->base + SIRFSOC_SPI_RX_DMA_IO_LEN);
 317         }
 318
 319         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 320         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 321         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 322         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 323
 324         /* Send the first word to trigger the whole tx/rx process */
 325         sspi->tx_word(sspi);
 326
 327         writel(SIRFSOC_SPI_RX_OFLOW_INT_EN | SIRFSOC_SPI_TX_UFLOW_INT_EN |
 328                 SIRFSOC_SPI_RXFIFO_THD_INT_EN | SIRFSOC_SPI_TXFIFO_THD_INT_EN |
 329                 SIRFSOC_SPI_FRM_END_INT_EN | SIRFSOC_SPI_RXFIFO_FULL_INT_EN |
 330                 SIRFSOC_SPI_TXFIFO_EMPTY_INT_EN, sspi->base + SIRFSOC_SPI_INT_EN);
 331         writel(SIRFSOC_SPI_RX_EN | SIRFSOC_SPI_TX_EN, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 332
 333         if (wait_for_completion_timeout(&sspi->done, timeout) == 0)
 334                 dev_err(&spi->dev, "transfer timeout\n");
 335
 336         /* TX, RX FIFO stop */
 337         writel(0, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 338         writel(0, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 339         writel(0, sspi->base + SIRFSOC_SPI_TX_RX_EN);
 340         writel(0, sspi->base + SIRFSOC_SPI_INT_EN);
 341
 342         return t->len - sspi->left_rx_cnt;
 343 }
 344
 345 static void spi_sirfsoc_chipselect(struct spi_device *spi, int value)
 346 {
 347         struct sirfsoc_spi *sspi = spi_master_get_devdata(spi->master);
 348
 349         if (sspi->chipselect[spi->chip_select] == 0) {
 350                 u32 regval = readl(sspi->base + SIRFSOC_SPI_CTRL);
 351                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 352                 switch (value) {
 353                 case BITBANG_CS_ACTIVE:
 354                         if (spi->mode & SPI_CS_HIGH)
 355                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 356                         else
 357                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 358                         break;
 359                 case BITBANG_CS_INACTIVE:
 360                         if (spi->mode & SPI_CS_HIGH)
 361                                 regval &= ~SIRFSOC_SPI_CS_IO_OUT;
 362                         else
 363                                 regval |= SIRFSOC_SPI_CS_IO_OUT;
 364                         break;
 365                 }
 366                 writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 367         } else {
 368                 int gpio = sspi->chipselect[spi->chip_select];
 369                 gpio_direction_output(gpio, spi->mode & SPI_CS_HIGH ? 0 : 1);
 370         }
 371 }
 372
 373 static int
 374 spi_sirfsoc_setup_transfer(struct spi_device *spi, struct spi_transfer *t)
 375 {
 376         struct sirfsoc_spi *sspi;
 377         u8 bits_per_word = 0;
 378         int hz = 0;
 379         u32 regval;
 380         u32 txfifo_ctrl, rxfifo_ctrl;
 381         u32 fifo_size = SIRFSOC_SPI_FIFO_SIZE / 4;
 382
 383         sspi = spi_master_get_devdata(spi->master);
 384
 385         bits_per_word = t && t->bits_per_word ? t->bits_per_word :
 386                 spi->bits_per_word;
 387         hz = t && t->speed_hz ? t->speed_hz : spi->max_speed_hz;
 388
 389         /* Enable IO mode for RX, TX */
 390         writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_TX_DMA_IO_CTRL);
 391         writel(SIRFSOC_SPI_IO_MODE_SEL, sspi->base + SIRFSOC_SPI_RX_DMA_IO_CTRL);
 392         regval = (sspi->ctrl_freq / (2 * hz)) - 1;
 393
 394         if (regval > 0xFFFF || regval < 0) {
 395                 dev_err(&spi->dev, "Speed %d not supported\n", hz);
 396                 return -EINVAL;
 397         }
 398
 399         switch (bits_per_word) {
 400         case 8:
 401                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_8;
 402                 sspi->rx_word = spi_sirfsoc_rx_word_u8;
 403                 sspi->tx_word = spi_sirfsoc_tx_word_u8;
 404                 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 405                                         SIRFSOC_SPI_FIFO_WIDTH_BYTE;
 406                 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 407                                         SIRFSOC_SPI_FIFO_WIDTH_BYTE;
 408                 break;
 409         case 12:
 410         case 16:
 411                 regval |= (bits_per_word ==  12) ? SIRFSOC_SPI_TRAN_DAT_FORMAT_12 :
 412                         SIRFSOC_SPI_TRAN_DAT_FORMAT_16;
 413                 sspi->rx_word = spi_sirfsoc_rx_word_u16;
 414                 sspi->tx_word = spi_sirfsoc_tx_word_u16;
 415                 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 416                                         SIRFSOC_SPI_FIFO_WIDTH_WORD;
 417                 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 418                                         SIRFSOC_SPI_FIFO_WIDTH_WORD;
 419                 break;
 420         case 32:
 421                 regval |= SIRFSOC_SPI_TRAN_DAT_FORMAT_32;
 422                 sspi->rx_word = spi_sirfsoc_rx_word_u32;
 423                 sspi->tx_word = spi_sirfsoc_tx_word_u32;
 424                 txfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 425                                         SIRFSOC_SPI_FIFO_WIDTH_DWORD;
 426                 rxfifo_ctrl = SIRFSOC_SPI_FIFO_THD(SIRFSOC_SPI_FIFO_SIZE / 2) |
 427                                         SIRFSOC_SPI_FIFO_WIDTH_DWORD;
 428                 break;
 429         default:
 430                 dev_err(&spi->dev, "Bits per word %d not supported\n",
 431                        bits_per_word);
 432                 return -EINVAL;
 433         }
 434
 435         if (!(spi->mode & SPI_CS_HIGH))
 436                 regval |= SIRFSOC_SPI_CS_IDLE_STAT;
 437         if (!(spi->mode & SPI_LSB_FIRST))
 438                 regval |= SIRFSOC_SPI_TRAN_MSB;
 439         if (spi->mode & SPI_CPOL)
 440                 regval |= SIRFSOC_SPI_CLK_IDLE_STAT;
 441
 442         /*
 443          * Data should be driven at least 1/2 cycle before the fetch edge to make
 444          * sure that data gets stable at the fetch edge.
 445          */
 446         if (((spi->mode & SPI_CPOL) && (spi->mode & SPI_CPHA)) ||
 447             (!(spi->mode & SPI_CPOL) && !(spi->mode & SPI_CPHA)))
 448                 regval &= ~SIRFSOC_SPI_DRV_POS_EDGE;
 449         else
 450                 regval |= SIRFSOC_SPI_DRV_POS_EDGE;
 451
 452         writel(SIRFSOC_SPI_FIFO_SC(fifo_size - 2) |
 453                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 454                         SIRFSOC_SPI_FIFO_HC(2),
 455                 sspi->base + SIRFSOC_SPI_TXFIFO_LEVEL_CHK);
 456         writel(SIRFSOC_SPI_FIFO_SC(2) |
 457                         SIRFSOC_SPI_FIFO_LC(fifo_size / 2) |
 458                         SIRFSOC_SPI_FIFO_HC(fifo_size - 2),
 459                 sspi->base + SIRFSOC_SPI_RXFIFO_LEVEL_CHK);
 460         writel(txfifo_ctrl, sspi->base + SIRFSOC_SPI_TXFIFO_CTRL);
 461         writel(rxfifo_ctrl, sspi->base + SIRFSOC_SPI_RXFIFO_CTRL);
 462
 463         writel(regval, sspi->base + SIRFSOC_SPI_CTRL);
 464         return 0;
 465 }
 466
 467 static int spi_sirfsoc_setup(struct spi_device *spi)
 468 {
 469         struct sirfsoc_spi *sspi;
 470
 471         if (!spi->max_speed_hz)
 472                 return -EINVAL;
 473
 474         sspi = spi_master_get_devdata(spi->master);
 475
 476         if (!spi->bits_per_word)
 477                 spi->bits_per_word = 8;
 478
 479         return spi_sirfsoc_setup_transfer(spi, NULL);
 480 }
 481
 482 static int __devinit spi_sirfsoc_probe(struct platform_device *pdev)
 483 {
 484         struct sirfsoc_spi *sspi;
 485         struct spi_master *master;
 486         struct resource *mem_res;
 487         int num_cs, cs_gpio, irq;
 488         int i;
 489         int ret;
 490
 491         ret = of_property_read_u32(pdev->dev.of_node,
 492                         "sirf,spi-num-chipselects", &num_cs);
 493         if (ret < 0) {
 494                 dev_err(&pdev->dev, "Unable to get chip select number\n");
 495                 goto err_cs;
 496         }
 497
 498         master = spi_alloc_master(&pdev->dev, sizeof(*sspi) + sizeof(int) * num_cs);
 499         if (!master) {
 500                 dev_err(&pdev->dev, "Unable to allocate SPI master\n");
 501                 return -ENOMEM;
 502         }
 503         platform_set_drvdata(pdev, master);
 504         sspi = spi_master_get_devdata(master);
 505
 506         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 507         if (!mem_res) {
 508                 dev_err(&pdev->dev, "Unable to get IO resource\n");
 509                 ret = -ENODEV;
 510                 goto free_master;
 511         }
 512         master->num_chipselect = num_cs;
 513
 514         for (i = 0; i < master->num_chipselect; i++) {
 515                 cs_gpio = of_get_named_gpio(pdev->dev.of_node, "cs-gpios", i);
 516                 if (cs_gpio < 0) {
 517                         dev_err(&pdev->dev, "can't get cs gpio from DT\n");
 518                         ret = -ENODEV;
 519                         goto free_master;
 520                 }
 521
 522                 sspi->chipselect[i] = cs_gpio;
 523                 if (cs_gpio == 0)
 524                         continue; /* use cs from spi controller */
 525
 526                 ret = gpio_request(cs_gpio, DRIVER_NAME);
 527                 if (ret) {
 528                         while (i > 0) {
 529                                 i--;
 530                                 if (sspi->chipselect[i] > 0)
 531                                         gpio_free(sspi->chipselect[i]);
 532                         }
 533                         dev_err(&pdev->dev, "fail to request cs gpios\n");
 534                         goto free_master;
 535                 }
 536         }
 537
 538         sspi->base = devm_request_and_ioremap(&pdev->dev, mem_res);
 539         if (!sspi->base) {
 540                 dev_err(&pdev->dev, "IO remap failed!\n");
 541                 ret = -ENOMEM;
 542                 goto free_master;
 543         }
 544
 545         irq = platform_get_irq(pdev, 0);
 546         if (irq < 0) {
 547                 ret = -ENXIO;
 548                 goto free_master;
 549         }
 550         ret = devm_request_irq(&pdev->dev, irq, spi_sirfsoc_irq, 0,
 551                                 DRIVER_NAME, sspi);
 552         if (ret)
 553                 goto free_master;
 554
 555         sspi->bitbang.master = spi_master_get(master);
 556         sspi->bitbang.chipselect = spi_sirfsoc_chipselect;
 557         sspi->bitbang.setup_transfer = spi_sirfsoc_setup_transfer;
 558         sspi->bitbang.txrx_bufs = spi_sirfsoc_transfer;
 559         sspi->bitbang.master->setup = spi_sirfsoc_setup;
 560         master->bus_num = pdev->id;
 561         sspi->bitbang.master->dev.of_node = pdev->dev.of_node;
 562
 563         sspi->pmx = pinmux_get(&pdev->dev, NULL);
 564         ret = IS_ERR(sspi->pmx);
 565         if (ret)
 566                 goto free_master;
 567
 568         pinmux_enable(sspi->pmx);
 569
 570         sspi->clk = clk_get(&pdev->dev, NULL);
 571         if (IS_ERR(sspi->clk)) {
 572                 ret = -EINVAL;
 573                 goto free_pmx;
 574         }
 575         clk_enable(sspi->clk);
 576         sspi->ctrl_freq = clk_get_rate(sspi->clk);
 577
 578         init_completion(&sspi->done);
 579
 580         tasklet_init(&sspi->tasklet_tx, spi_sirfsoc_tasklet_tx,
 581                      (unsigned long)sspi);
 582
 583         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 584         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 585         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 586         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 587         /* We are not using dummy delay between command and data */
 588         writel(0, sspi->base + SIRFSOC_SPI_DUMMY_DELAY_CTL);
 589
 590         ret = spi_bitbang_start(&sspi->bitbang);
 591         if (ret)
 592                 goto free_clk;
 593
 594         dev_info(&pdev->dev, "registerred, bus number = %d\n", master->bus_num);
 595
 596         return 0;
 597
 598 free_clk:
 599         clk_disable(sspi->clk);
 600         clk_put(sspi->clk);
 601 free_pmx:
 602         pinmux_disable(sspi->pmx);
 603         pinmux_put(sspi->pmx);
 604 free_master:
 605         spi_master_put(master);
 606 err_cs:
 607         return ret;
 608 }
 609
 610 static int  __devexit spi_sirfsoc_remove(struct platform_device *pdev)
 611 {
 612         struct spi_master *master;
 613         struct sirfsoc_spi *sspi;
 614         int i;
 615
 616         master = platform_get_drvdata(pdev);
 617         sspi = spi_master_get_devdata(master);
 618
 619         spi_bitbang_stop(&sspi->bitbang);
 620         for (i = 0; i < master->num_chipselect; i++) {
 621                 if (sspi->chipselect[i] > 0)
 622                         gpio_free(sspi->chipselect[i]);
 623         }
 624         clk_disable(sspi->clk);
 625         clk_put(sspi->clk);
 626         pinmux_disable(sspi->pmx);
 627         pinmux_put(sspi->pmx);
 628         spi_master_put(master);
 629         return 0;
 630 }
 631
 632 #ifdef CONFIG_PM
 633 static int spi_sirfsoc_suspend(struct device *dev)
 634 {
 635         struct platform_device *pdev = to_platform_device(dev);
 636         struct spi_master *master = platform_get_drvdata(pdev);
 637         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 638
 639         clk_disable(sspi->clk);
 640         return 0;
 641 }
 642
 643 static int spi_sirfsoc_resume(struct device *dev)
 644 {
 645         struct platform_device *pdev = to_platform_device(dev);
 646         struct spi_master *master = platform_get_drvdata(pdev);
 647         struct sirfsoc_spi *sspi = spi_master_get_devdata(master);
 648
 649         clk_enable(sspi->clk);
 650         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 651         writel(SIRFSOC_SPI_FIFO_RESET, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 652         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_RXFIFO_OP);
 653         writel(SIRFSOC_SPI_FIFO_START, sspi->base + SIRFSOC_SPI_TXFIFO_OP);
 654
 655         return 0;
 656 }
 657
 658 static const struct dev_pm_ops spi_sirfsoc_pm_ops = {
 659         .suspend = spi_sirfsoc_suspend,
 660         .resume = spi_sirfsoc_resume,
 661 };
 662 #endif
 663
 664 static const struct of_device_id spi_sirfsoc_of_match[] = {
 665         { .compatible = "sirf,prima2-spi", },
 666         {}
 667 };
 668 MODULE_DEVICE_TABLE(of, sirfsoc_spi_of_match);
 669
 670 static struct platform_driver spi_sirfsoc_driver = {
 671         .driver = {
 672                 .name = DRIVER_NAME,
 673                 .owner = THIS_MODULE,
 674 #ifdef CONFIG_PM
 675                 .pm     = &spi_sirfsoc_pm_ops,
 676 #endif
 677                 .of_match_table = spi_sirfsoc_of_match,
 678         },
 679         .probe = spi_sirfsoc_probe,
 680         .remove = __devexit_p(spi_sirfsoc_remove),
 681 };
 682 module_platform_driver(spi_sirfsoc_driver);
 683
 684 MODULE_DESCRIPTION("SiRF SoC SPI master driver");
 685 MODULE_AUTHOR("Zhiwu Song <Zhiwu.Song@csr.com>, "
 686                 "Barry Song <Baohua.Song@csr.com>");
 687 MODULE_LICENSE("GPL v2");