2 * Broadcom specific AMBA
5 * Copyright 2005 - 2011, Broadcom Corporation
6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
9 * Licensed under the GNU/GPL. See COPYING for details.
12 #include "bcma_private.h"
13 #include <linux/export.h>
14 #include <linux/bcma/bcma.h>
15 #include <asm/paccess.h>
17 /* Probe a 32bit value on the bus and catch bus exceptions.
18 * Returns nonzero on a bus exception.
19 * This is MIPS specific */
20 #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr)))
22 /* Assume one-hot slot wiring */
23 #define BCMA_PCI_SLOT_MAX 16
24 #define PCI_CONFIG_SPACE_SIZE 256
26 bool __devinit
bcma_core_pci_is_in_hostmode(struct bcma_drv_pci
*pc
)
28 struct bcma_bus
*bus
= pc
->core
->bus
;
32 chipid_top
= (bus
->chipinfo
.id
& 0xFF00);
33 if (chipid_top
!= 0x4700 &&
37 if (bus
->sprom
.boardflags_lo
& BCMA_CORE_PCI_BFL_NOPCI
) {
38 pr_info("This PCI core is disabled and not working\n");
42 bcma_core_enable(pc
->core
, 0);
44 return !mips_busprobe32(tmp
, pc
->core
->io_addr
);
47 static u32
bcma_pcie_read_config(struct bcma_drv_pci
*pc
, u32 address
)
49 pcicore_write32(pc
, BCMA_CORE_PCI_CONFIG_ADDR
, address
);
50 pcicore_read32(pc
, BCMA_CORE_PCI_CONFIG_ADDR
);
51 return pcicore_read32(pc
, BCMA_CORE_PCI_CONFIG_DATA
);
54 static void bcma_pcie_write_config(struct bcma_drv_pci
*pc
, u32 address
,
57 pcicore_write32(pc
, BCMA_CORE_PCI_CONFIG_ADDR
, address
);
58 pcicore_read32(pc
, BCMA_CORE_PCI_CONFIG_ADDR
);
59 pcicore_write32(pc
, BCMA_CORE_PCI_CONFIG_DATA
, data
);
62 static u32
bcma_get_cfgspace_addr(struct bcma_drv_pci
*pc
, unsigned int dev
,
63 unsigned int func
, unsigned int off
)
67 /* Issue config commands only when the data link is up (atleast
68 * one external pcie device is present).
70 if (dev
>= 2 || !(bcma_pcie_read(pc
, BCMA_CORE_PCI_DLLP_LSREG
)
71 & BCMA_CORE_PCI_DLLP_LSREG_LINKUP
))
74 /* Type 0 transaction */
75 /* Slide the PCI window to the appropriate slot */
76 pcicore_write32(pc
, BCMA_CORE_PCI_SBTOPCI1
, BCMA_CORE_PCI_SBTOPCI_CFG0
);
77 /* Calculate the address */
78 addr
= pc
->host_controller
->host_cfg_addr
;
79 addr
|= (dev
<< BCMA_CORE_PCI_CFG_SLOT_SHIFT
);
80 addr
|= (func
<< BCMA_CORE_PCI_CFG_FUN_SHIFT
);
87 static int bcma_extpci_read_config(struct bcma_drv_pci
*pc
, unsigned int dev
,
88 unsigned int func
, unsigned int off
,
93 void __iomem
*mmio
= 0;
95 WARN_ON(!pc
->hostmode
);
96 if (unlikely(len
!= 1 && len
!= 2 && len
!= 4))
99 /* we support only two functions on device 0 */
103 /* accesses to config registers with offsets >= 256
104 * requires indirect access.
106 if (off
>= PCI_CONFIG_SPACE_SIZE
) {
108 addr
|= (off
& 0x0FFF);
109 val
= bcma_pcie_read_config(pc
, addr
);
111 addr
= BCMA_CORE_PCI_PCICFG0
;
113 addr
|= (off
& 0xfc);
114 val
= pcicore_read32(pc
, addr
);
117 addr
= bcma_get_cfgspace_addr(pc
, dev
, func
, off
);
121 mmio
= ioremap_nocache(addr
, len
);
125 if (mips_busprobe32(val
, mmio
)) {
132 val
>>= (8 * (off
& 3));
136 *((u8
*)buf
) = (u8
)val
;
139 *((u16
*)buf
) = (u16
)val
;
142 *((u32
*)buf
) = (u32
)val
;
153 static int bcma_extpci_write_config(struct bcma_drv_pci
*pc
, unsigned int dev
,
154 unsigned int func
, unsigned int off
,
155 const void *buf
, int len
)
158 u32 addr
= 0, val
= 0;
159 void __iomem
*mmio
= 0;
160 u16 chipid
= pc
->core
->bus
->chipinfo
.id
;
162 WARN_ON(!pc
->hostmode
);
163 if (unlikely(len
!= 1 && len
!= 2 && len
!= 4))
166 /* accesses to config registers with offsets >= 256
167 * requires indirect access.
169 if (off
< PCI_CONFIG_SPACE_SIZE
) {
170 addr
= pc
->core
->addr
+ BCMA_CORE_PCI_PCICFG0
;
172 addr
|= (off
& 0xfc);
173 mmio
= ioremap_nocache(addr
, len
);
178 addr
= bcma_get_cfgspace_addr(pc
, dev
, func
, off
);
182 mmio
= ioremap_nocache(addr
, len
);
186 if (mips_busprobe32(val
, mmio
)) {
195 val
&= ~(0xFF << (8 * (off
& 3)));
196 val
|= *((const u8
*)buf
) << (8 * (off
& 3));
200 val
&= ~(0xFFFF << (8 * (off
& 3)));
201 val
|= *((const u16
*)buf
) << (8 * (off
& 3));
204 val
= *((const u32
*)buf
);
207 if (dev
== 0 && !addr
) {
208 /* accesses to config registers with offsets >= 256
209 * requires indirect access.
212 addr
|= (off
& 0x0FFF);
213 bcma_pcie_write_config(pc
, addr
, val
);
217 if (chipid
== 0x4716 || chipid
== 0x4748)
229 static int bcma_core_pci_hostmode_read_config(struct pci_bus
*bus
,
231 int reg
, int size
, u32
*val
)
235 struct bcma_drv_pci
*pc
;
236 struct bcma_drv_pci_host
*pc_host
;
238 pc_host
= container_of(bus
->ops
, struct bcma_drv_pci_host
, pci_ops
);
241 spin_lock_irqsave(&pc_host
->cfgspace_lock
, flags
);
242 err
= bcma_extpci_read_config(pc
, PCI_SLOT(devfn
),
243 PCI_FUNC(devfn
), reg
, val
, size
);
244 spin_unlock_irqrestore(&pc_host
->cfgspace_lock
, flags
);
246 return err
? PCIBIOS_DEVICE_NOT_FOUND
: PCIBIOS_SUCCESSFUL
;
249 static int bcma_core_pci_hostmode_write_config(struct pci_bus
*bus
,
251 int reg
, int size
, u32 val
)
255 struct bcma_drv_pci
*pc
;
256 struct bcma_drv_pci_host
*pc_host
;
258 pc_host
= container_of(bus
->ops
, struct bcma_drv_pci_host
, pci_ops
);
261 spin_lock_irqsave(&pc_host
->cfgspace_lock
, flags
);
262 err
= bcma_extpci_write_config(pc
, PCI_SLOT(devfn
),
263 PCI_FUNC(devfn
), reg
, &val
, size
);
264 spin_unlock_irqrestore(&pc_host
->cfgspace_lock
, flags
);
266 return err
? PCIBIOS_DEVICE_NOT_FOUND
: PCIBIOS_SUCCESSFUL
;
269 /* return cap_offset if requested capability exists in the PCI config space */
270 static u8 __devinit
bcma_find_pci_capability(struct bcma_drv_pci
*pc
,
272 unsigned int func
, u8 req_cap_id
,
273 unsigned char *buf
, u32
*buflen
)
280 /* check for Header type 0 */
281 bcma_extpci_read_config(pc
, dev
, func
, PCI_HEADER_TYPE
, &byte_val
,
283 if ((byte_val
& 0x7f) != PCI_HEADER_TYPE_NORMAL
)
286 /* check if the capability pointer field exists */
287 bcma_extpci_read_config(pc
, dev
, func
, PCI_STATUS
, &byte_val
,
289 if (!(byte_val
& PCI_STATUS_CAP_LIST
))
292 /* check if the capability pointer is 0x00 */
293 bcma_extpci_read_config(pc
, dev
, func
, PCI_CAPABILITY_LIST
, &cap_ptr
,
298 /* loop thr'u the capability list and see if the requested capabilty
300 bcma_extpci_read_config(pc
, dev
, func
, cap_ptr
, &cap_id
, sizeof(u8
));
301 while (cap_id
!= req_cap_id
) {
302 bcma_extpci_read_config(pc
, dev
, func
, cap_ptr
+ 1, &cap_ptr
,
306 bcma_extpci_read_config(pc
, dev
, func
, cap_ptr
, &cap_id
,
310 /* found the caller requested capability */
311 if ((buf
!= NULL
) && (buflen
!= NULL
)) {
320 /* copy the cpability data excluding cap ID and next ptr */
321 cap_data
= cap_ptr
+ 2;
322 if ((bufsize
+ cap_data
) > PCI_CONFIG_SPACE_SIZE
)
323 bufsize
= PCI_CONFIG_SPACE_SIZE
- cap_data
;
326 bcma_extpci_read_config(pc
, dev
, func
, cap_data
, buf
,
336 /* If the root port is capable of returning Config Request
337 * Retry Status (CRS) Completion Status to software then
338 * enable the feature.
340 static void __devinit
bcma_core_pci_enable_crs(struct bcma_drv_pci
*pc
)
342 u8 cap_ptr
, root_ctrl
, root_cap
, dev
;
346 cap_ptr
= bcma_find_pci_capability(pc
, 0, 0, PCI_CAP_ID_EXP
, NULL
,
348 root_cap
= cap_ptr
+ PCI_EXP_RTCAP
;
349 bcma_extpci_read_config(pc
, 0, 0, root_cap
, &val16
, sizeof(u16
));
350 if (val16
& BCMA_CORE_PCI_RC_CRS_VISIBILITY
) {
351 /* Enable CRS software visibility */
352 root_ctrl
= cap_ptr
+ PCI_EXP_RTCTL
;
353 val16
= PCI_EXP_RTCTL_CRSSVE
;
354 bcma_extpci_read_config(pc
, 0, 0, root_ctrl
, &val16
,
357 /* Initiate a configuration request to read the vendor id
358 * field of the device function's config space header after
359 * 100 ms wait time from the end of Reset. If the device is
360 * not done with its internal initialization, it must at
361 * least return a completion TLP, with a completion status
362 * of "Configuration Request Retry Status (CRS)". The root
363 * complex must complete the request to the host by returning
364 * a read-data value of 0001h for the Vendor ID field and
365 * all 1s for any additional bytes included in the request.
366 * Poll using the config reads for max wait time of 1 sec or
367 * until we receive the successful completion status. Repeat
368 * the procedure for all the devices.
370 for (dev
= 1; dev
< BCMA_PCI_SLOT_MAX
; dev
++) {
371 for (i
= 0; i
< 100000; i
++) {
372 bcma_extpci_read_config(pc
, dev
, 0,
373 PCI_VENDOR_ID
, &val16
,
380 pr_err("PCI: Broken device in slot %d\n", dev
);
385 void __devinit
bcma_core_pci_hostmode_init(struct bcma_drv_pci
*pc
)
387 struct bcma_bus
*bus
= pc
->core
->bus
;
388 struct bcma_drv_pci_host
*pc_host
;
391 unsigned long io_map_base
;
393 pr_info("PCIEcore in host mode found\n");
395 pc_host
= kzalloc(sizeof(*pc_host
), GFP_KERNEL
);
397 pr_err("can not allocate memory");
401 pc
->host_controller
= pc_host
;
402 pc_host
->pci_controller
.io_resource
= &pc_host
->io_resource
;
403 pc_host
->pci_controller
.mem_resource
= &pc_host
->mem_resource
;
404 pc_host
->pci_controller
.pci_ops
= &pc_host
->pci_ops
;
407 pci_membase_1G
= BCMA_SOC_PCI_DMA
;
408 pc_host
->host_cfg_addr
= BCMA_SOC_PCI_CFG
;
410 pc_host
->pci_ops
.read
= bcma_core_pci_hostmode_read_config
;
411 pc_host
->pci_ops
.write
= bcma_core_pci_hostmode_write_config
;
413 pc_host
->mem_resource
.name
= "BCMA PCIcore external memory",
414 pc_host
->mem_resource
.start
= BCMA_SOC_PCI_DMA
;
415 pc_host
->mem_resource
.end
= BCMA_SOC_PCI_DMA
+ BCMA_SOC_PCI_DMA_SZ
- 1;
416 pc_host
->mem_resource
.flags
= IORESOURCE_MEM
| IORESOURCE_PCI_FIXED
;
418 pc_host
->io_resource
.name
= "BCMA PCIcore external I/O",
419 pc_host
->io_resource
.start
= 0x100;
420 pc_host
->io_resource
.end
= 0x7FF;
421 pc_host
->io_resource
.flags
= IORESOURCE_IO
| IORESOURCE_PCI_FIXED
;
425 pcicore_write32(pc
, BCMA_CORE_PCI_CTL
, BCMA_CORE_PCI_CTL_RST_OE
);
427 pcicore_write32(pc
, BCMA_CORE_PCI_CTL
, BCMA_CORE_PCI_CTL_RST
|
428 BCMA_CORE_PCI_CTL_RST_OE
);
430 /* 64 MB I/O access window. On 4716, use
431 * sbtopcie0 to access the device registers. We
432 * can't use address match 2 (1 GB window) region
433 * as mips can't generate 64-bit address on the
436 if (bus
->chipinfo
.id
== 0x4716 || bus
->chipinfo
.id
== 0x4748) {
437 pc_host
->mem_resource
.start
= BCMA_SOC_PCI_MEM
;
438 pc_host
->mem_resource
.end
= BCMA_SOC_PCI_MEM
+
439 BCMA_SOC_PCI_MEM_SZ
- 1;
440 pcicore_write32(pc
, BCMA_CORE_PCI_SBTOPCI0
,
441 BCMA_CORE_PCI_SBTOPCI_MEM
| BCMA_SOC_PCI_MEM
);
442 } else if (bus
->chipinfo
.id
== 0x5300) {
443 tmp
= BCMA_CORE_PCI_SBTOPCI_MEM
;
444 tmp
|= BCMA_CORE_PCI_SBTOPCI_PREF
;
445 tmp
|= BCMA_CORE_PCI_SBTOPCI_BURST
;
446 if (pc
->core
->core_unit
== 0) {
447 pc_host
->mem_resource
.start
= BCMA_SOC_PCI_MEM
;
448 pc_host
->mem_resource
.end
= BCMA_SOC_PCI_MEM
+
449 BCMA_SOC_PCI_MEM_SZ
- 1;
450 pci_membase_1G
= BCMA_SOC_PCIE_DMA_H32
;
451 pcicore_write32(pc
, BCMA_CORE_PCI_SBTOPCI0
,
452 tmp
| BCMA_SOC_PCI_MEM
);
453 } else if (pc
->core
->core_unit
== 1) {
454 pc_host
->mem_resource
.start
= BCMA_SOC_PCI1_MEM
;
455 pc_host
->mem_resource
.end
= BCMA_SOC_PCI1_MEM
+
456 BCMA_SOC_PCI_MEM_SZ
- 1;
457 pci_membase_1G
= BCMA_SOC_PCIE1_DMA_H32
;
458 pc_host
->host_cfg_addr
= BCMA_SOC_PCI1_CFG
;
459 pcicore_write32(pc
, BCMA_CORE_PCI_SBTOPCI0
,
460 tmp
| BCMA_SOC_PCI1_MEM
);
463 pcicore_write32(pc
, BCMA_CORE_PCI_SBTOPCI0
,
464 BCMA_CORE_PCI_SBTOPCI_IO
);
466 /* 64 MB configuration access window */
467 pcicore_write32(pc
, BCMA_CORE_PCI_SBTOPCI1
, BCMA_CORE_PCI_SBTOPCI_CFG0
);
469 /* 1 GB memory access window */
470 pcicore_write32(pc
, BCMA_CORE_PCI_SBTOPCI2
,
471 BCMA_CORE_PCI_SBTOPCI_MEM
| pci_membase_1G
);
474 /* As per PCI Express Base Spec 1.1 we need to wait for
475 * at least 100 ms from the end of a reset (cold/warm/hot)
476 * before issuing configuration requests to PCI Express
481 bcma_core_pci_enable_crs(pc
);
483 /* Enable PCI bridge BAR0 memory & master access */
484 tmp
= PCI_COMMAND_MASTER
| PCI_COMMAND_MEMORY
;
485 bcma_extpci_write_config(pc
, 0, 0, PCI_COMMAND
, &tmp
, sizeof(tmp
));
487 /* Enable PCI interrupts */
488 pcicore_write32(pc
, BCMA_CORE_PCI_IMASK
, BCMA_CORE_PCI_IMASK_INTA
);
490 /* Ok, ready to run, register it to the system.
491 * The following needs change, if we want to port hostmode
492 * to non-MIPS platform. */
493 io_map_base
= (unsigned long)ioremap_nocache(BCMA_SOC_PCI_MEM
,
495 pc_host
->pci_controller
.io_map_base
= io_map_base
;
496 set_io_port_base(pc_host
->pci_controller
.io_map_base
);
497 /* Give some time to the PCI controller to configure itself with the new
498 * values. Not waiting at this point causes crashes of the machine. */
500 register_pci_controller(&pc_host
->pci_controller
);
504 /* Early PCI fixup for a device on the PCI-core bridge. */
505 static void bcma_core_pci_fixup_pcibridge(struct pci_dev
*dev
)
507 if (dev
->bus
->ops
->read
!= bcma_core_pci_hostmode_read_config
) {
508 /* This is not a device on the PCI-core bridge. */
511 if (PCI_SLOT(dev
->devfn
) != 0)
514 pr_info("PCI: Fixing up bridge %s\n", pci_name(dev
));
516 /* Enable PCI bridge bus mastering and memory space */
518 if (pcibios_enable_device(dev
, ~0) < 0) {
519 pr_err("PCI: BCMA bridge enable failed\n");
523 /* Enable PCI bridge BAR1 prefetch and burst */
524 pci_write_config_dword(dev
, BCMA_PCI_BAR1_CONTROL
, 3);
526 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID
, PCI_ANY_ID
, bcma_core_pci_fixup_pcibridge
);
528 /* Early PCI fixup for all PCI-cores to set the correct memory address. */
529 static void bcma_core_pci_fixup_addresses(struct pci_dev
*dev
)
531 struct resource
*res
;
534 if (dev
->bus
->ops
->read
!= bcma_core_pci_hostmode_read_config
) {
535 /* This is not a device on the PCI-core bridge. */
538 if (PCI_SLOT(dev
->devfn
) == 0)
541 pr_info("PCI: Fixing up addresses %s\n", pci_name(dev
));
543 for (pos
= 0; pos
< 6; pos
++) {
544 res
= &dev
->resource
[pos
];
545 if (res
->flags
& (IORESOURCE_IO
| IORESOURCE_MEM
))
546 pci_assign_resource(dev
, pos
);
549 DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID
, PCI_ANY_ID
, bcma_core_pci_fixup_addresses
);
551 /* This function is called when doing a pci_enable_device().
552 * We must first check if the device is a device on the PCI-core bridge. */
553 int bcma_core_pci_plat_dev_init(struct pci_dev
*dev
)
555 struct bcma_drv_pci_host
*pc_host
;
557 if (dev
->bus
->ops
->read
!= bcma_core_pci_hostmode_read_config
) {
558 /* This is not a device on the PCI-core bridge. */
561 pc_host
= container_of(dev
->bus
->ops
, struct bcma_drv_pci_host
,
564 pr_info("PCI: Fixing up device %s\n", pci_name(dev
));
566 /* Fix up interrupt lines */
567 dev
->irq
= bcma_core_mips_irq(pc_host
->pdev
->core
) + 2;
568 pci_write_config_byte(dev
, PCI_INTERRUPT_LINE
, dev
->irq
);
572 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init
);
574 /* PCI device IRQ mapping. */
575 int bcma_core_pci_pcibios_map_irq(const struct pci_dev
*dev
)
577 struct bcma_drv_pci_host
*pc_host
;
579 if (dev
->bus
->ops
->read
!= bcma_core_pci_hostmode_read_config
) {
580 /* This is not a device on the PCI-core bridge. */
584 pc_host
= container_of(dev
->bus
->ops
, struct bcma_drv_pci_host
,
586 return bcma_core_mips_irq(pc_host
->pdev
->core
) + 2;
588 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq
);