2 * sound/soc/omap/mcbsp.c
4 * Copyright (C) 2004 Nokia Corporation
5 * Author: Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Contact: Jarkko Nikula <jarkko.nikula@bitmer.com>
8 * Peter Ujfalusi <peter.ujfalusi@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
14 * Multichannel mode not supported.
17 #include <linux/module.h>
18 #include <linux/init.h>
19 #include <linux/device.h>
20 #include <linux/platform_device.h>
21 #include <linux/interrupt.h>
22 #include <linux/err.h>
23 #include <linux/clk.h>
24 #include <linux/delay.h>
26 #include <linux/slab.h>
28 #include <plat/mcbsp.h>
29 #include <linux/pm_runtime.h>
31 struct omap_mcbsp
**mcbsp_ptr
;
34 #define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
35 #define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
37 static void omap_mcbsp_write(struct omap_mcbsp
*mcbsp
, u16 reg
, u32 val
)
39 void __iomem
*addr
= mcbsp
->io_base
+ reg
* mcbsp
->pdata
->reg_step
;
41 if (mcbsp
->pdata
->reg_size
== 2) {
42 ((u16
*)mcbsp
->reg_cache
)[reg
] = (u16
)val
;
43 __raw_writew((u16
)val
, addr
);
45 ((u32
*)mcbsp
->reg_cache
)[reg
] = val
;
46 __raw_writel(val
, addr
);
50 static int omap_mcbsp_read(struct omap_mcbsp
*mcbsp
, u16 reg
, bool from_cache
)
52 void __iomem
*addr
= mcbsp
->io_base
+ reg
* mcbsp
->pdata
->reg_step
;
54 if (mcbsp
->pdata
->reg_size
== 2) {
55 return !from_cache
? __raw_readw(addr
) :
56 ((u16
*)mcbsp
->reg_cache
)[reg
];
58 return !from_cache
? __raw_readl(addr
) :
59 ((u32
*)mcbsp
->reg_cache
)[reg
];
63 static void omap_mcbsp_st_write(struct omap_mcbsp
*mcbsp
, u16 reg
, u32 val
)
65 __raw_writel(val
, mcbsp
->st_data
->io_base_st
+ reg
);
68 static int omap_mcbsp_st_read(struct omap_mcbsp
*mcbsp
, u16 reg
)
70 return __raw_readl(mcbsp
->st_data
->io_base_st
+ reg
);
73 #define MCBSP_READ(mcbsp, reg) \
74 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 0)
75 #define MCBSP_WRITE(mcbsp, reg, val) \
76 omap_mcbsp_write(mcbsp, OMAP_MCBSP_REG_##reg, val)
77 #define MCBSP_READ_CACHE(mcbsp, reg) \
78 omap_mcbsp_read(mcbsp, OMAP_MCBSP_REG_##reg, 1)
80 #define MCBSP_ST_READ(mcbsp, reg) \
81 omap_mcbsp_st_read(mcbsp, OMAP_ST_REG_##reg)
82 #define MCBSP_ST_WRITE(mcbsp, reg, val) \
83 omap_mcbsp_st_write(mcbsp, OMAP_ST_REG_##reg, val)
85 static void omap_mcbsp_dump_reg(u8 id
)
87 struct omap_mcbsp
*mcbsp
= id_to_mcbsp_ptr(id
);
89 dev_dbg(mcbsp
->dev
, "**** McBSP%d regs ****\n", mcbsp
->id
);
90 dev_dbg(mcbsp
->dev
, "DRR2: 0x%04x\n",
91 MCBSP_READ(mcbsp
, DRR2
));
92 dev_dbg(mcbsp
->dev
, "DRR1: 0x%04x\n",
93 MCBSP_READ(mcbsp
, DRR1
));
94 dev_dbg(mcbsp
->dev
, "DXR2: 0x%04x\n",
95 MCBSP_READ(mcbsp
, DXR2
));
96 dev_dbg(mcbsp
->dev
, "DXR1: 0x%04x\n",
97 MCBSP_READ(mcbsp
, DXR1
));
98 dev_dbg(mcbsp
->dev
, "SPCR2: 0x%04x\n",
99 MCBSP_READ(mcbsp
, SPCR2
));
100 dev_dbg(mcbsp
->dev
, "SPCR1: 0x%04x\n",
101 MCBSP_READ(mcbsp
, SPCR1
));
102 dev_dbg(mcbsp
->dev
, "RCR2: 0x%04x\n",
103 MCBSP_READ(mcbsp
, RCR2
));
104 dev_dbg(mcbsp
->dev
, "RCR1: 0x%04x\n",
105 MCBSP_READ(mcbsp
, RCR1
));
106 dev_dbg(mcbsp
->dev
, "XCR2: 0x%04x\n",
107 MCBSP_READ(mcbsp
, XCR2
));
108 dev_dbg(mcbsp
->dev
, "XCR1: 0x%04x\n",
109 MCBSP_READ(mcbsp
, XCR1
));
110 dev_dbg(mcbsp
->dev
, "SRGR2: 0x%04x\n",
111 MCBSP_READ(mcbsp
, SRGR2
));
112 dev_dbg(mcbsp
->dev
, "SRGR1: 0x%04x\n",
113 MCBSP_READ(mcbsp
, SRGR1
));
114 dev_dbg(mcbsp
->dev
, "PCR0: 0x%04x\n",
115 MCBSP_READ(mcbsp
, PCR0
));
116 dev_dbg(mcbsp
->dev
, "***********************\n");
119 static irqreturn_t
omap_mcbsp_tx_irq_handler(int irq
, void *dev_id
)
121 struct omap_mcbsp
*mcbsp_tx
= dev_id
;
124 irqst_spcr2
= MCBSP_READ(mcbsp_tx
, SPCR2
);
125 dev_dbg(mcbsp_tx
->dev
, "TX IRQ callback : 0x%x\n", irqst_spcr2
);
127 if (irqst_spcr2
& XSYNC_ERR
) {
128 dev_err(mcbsp_tx
->dev
, "TX Frame Sync Error! : 0x%x\n",
130 /* Writing zero to XSYNC_ERR clears the IRQ */
131 MCBSP_WRITE(mcbsp_tx
, SPCR2
, MCBSP_READ_CACHE(mcbsp_tx
, SPCR2
));
137 static irqreturn_t
omap_mcbsp_rx_irq_handler(int irq
, void *dev_id
)
139 struct omap_mcbsp
*mcbsp_rx
= dev_id
;
142 irqst_spcr1
= MCBSP_READ(mcbsp_rx
, SPCR1
);
143 dev_dbg(mcbsp_rx
->dev
, "RX IRQ callback : 0x%x\n", irqst_spcr1
);
145 if (irqst_spcr1
& RSYNC_ERR
) {
146 dev_err(mcbsp_rx
->dev
, "RX Frame Sync Error! : 0x%x\n",
148 /* Writing zero to RSYNC_ERR clears the IRQ */
149 MCBSP_WRITE(mcbsp_rx
, SPCR1
, MCBSP_READ_CACHE(mcbsp_rx
, SPCR1
));
156 * omap_mcbsp_config simply write a config to the
158 * You either call this function or set the McBSP registers
159 * by yourself before calling omap_mcbsp_start().
161 void omap_mcbsp_config(unsigned int id
, const struct omap_mcbsp_reg_cfg
*config
)
163 struct omap_mcbsp
*mcbsp
;
165 if (!omap_mcbsp_check_valid_id(id
)) {
166 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
169 mcbsp
= id_to_mcbsp_ptr(id
);
171 dev_dbg(mcbsp
->dev
, "Configuring McBSP%d phys_base: 0x%08lx\n",
172 mcbsp
->id
, mcbsp
->phys_base
);
174 /* We write the given config */
175 MCBSP_WRITE(mcbsp
, SPCR2
, config
->spcr2
);
176 MCBSP_WRITE(mcbsp
, SPCR1
, config
->spcr1
);
177 MCBSP_WRITE(mcbsp
, RCR2
, config
->rcr2
);
178 MCBSP_WRITE(mcbsp
, RCR1
, config
->rcr1
);
179 MCBSP_WRITE(mcbsp
, XCR2
, config
->xcr2
);
180 MCBSP_WRITE(mcbsp
, XCR1
, config
->xcr1
);
181 MCBSP_WRITE(mcbsp
, SRGR2
, config
->srgr2
);
182 MCBSP_WRITE(mcbsp
, SRGR1
, config
->srgr1
);
183 MCBSP_WRITE(mcbsp
, MCR2
, config
->mcr2
);
184 MCBSP_WRITE(mcbsp
, MCR1
, config
->mcr1
);
185 MCBSP_WRITE(mcbsp
, PCR0
, config
->pcr0
);
186 if (mcbsp
->pdata
->has_ccr
) {
187 MCBSP_WRITE(mcbsp
, XCCR
, config
->xccr
);
188 MCBSP_WRITE(mcbsp
, RCCR
, config
->rccr
);
191 EXPORT_SYMBOL(omap_mcbsp_config
);
194 * omap_mcbsp_dma_params - returns the dma channel number
196 * @stream - indicates the direction of data flow (rx or tx)
198 * Returns the dma channel number for the rx channel or tx channel
199 * based on the value of @stream for the requested mcbsp given by @id
201 int omap_mcbsp_dma_ch_params(unsigned int id
, unsigned int stream
)
203 struct omap_mcbsp
*mcbsp
;
205 if (!omap_mcbsp_check_valid_id(id
)) {
206 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
209 mcbsp
= id_to_mcbsp_ptr(id
);
212 return mcbsp
->dma_rx_sync
;
214 return mcbsp
->dma_tx_sync
;
216 EXPORT_SYMBOL(omap_mcbsp_dma_ch_params
);
219 * omap_mcbsp_dma_reg_params - returns the address of mcbsp data register
221 * @stream - indicates the direction of data flow (rx or tx)
223 * Returns the address of mcbsp data transmit register or data receive register
224 * to be used by DMA for transferring/receiving data based on the value of
225 * @stream for the requested mcbsp given by @id
227 int omap_mcbsp_dma_reg_params(unsigned int id
, unsigned int stream
)
229 struct omap_mcbsp
*mcbsp
;
232 if (!omap_mcbsp_check_valid_id(id
)) {
233 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
236 mcbsp
= id_to_mcbsp_ptr(id
);
238 if (mcbsp
->pdata
->reg_size
== 2) {
240 data_reg
= OMAP_MCBSP_REG_DRR1
;
242 data_reg
= OMAP_MCBSP_REG_DXR1
;
245 data_reg
= OMAP_MCBSP_REG_DRR
;
247 data_reg
= OMAP_MCBSP_REG_DXR
;
250 return mcbsp
->phys_dma_base
+ data_reg
* mcbsp
->pdata
->reg_step
;
252 EXPORT_SYMBOL(omap_mcbsp_dma_reg_params
);
254 static void omap_st_on(struct omap_mcbsp
*mcbsp
)
258 if (mcbsp
->pdata
->enable_st_clock
)
259 mcbsp
->pdata
->enable_st_clock(mcbsp
->id
, 1);
261 /* Enable McBSP Sidetone */
262 w
= MCBSP_READ(mcbsp
, SSELCR
);
263 MCBSP_WRITE(mcbsp
, SSELCR
, w
| SIDETONEEN
);
265 /* Enable Sidetone from Sidetone Core */
266 w
= MCBSP_ST_READ(mcbsp
, SSELCR
);
267 MCBSP_ST_WRITE(mcbsp
, SSELCR
, w
| ST_SIDETONEEN
);
270 static void omap_st_off(struct omap_mcbsp
*mcbsp
)
274 w
= MCBSP_ST_READ(mcbsp
, SSELCR
);
275 MCBSP_ST_WRITE(mcbsp
, SSELCR
, w
& ~(ST_SIDETONEEN
));
277 w
= MCBSP_READ(mcbsp
, SSELCR
);
278 MCBSP_WRITE(mcbsp
, SSELCR
, w
& ~(SIDETONEEN
));
280 if (mcbsp
->pdata
->enable_st_clock
)
281 mcbsp
->pdata
->enable_st_clock(mcbsp
->id
, 0);
284 static void omap_st_fir_write(struct omap_mcbsp
*mcbsp
, s16
*fir
)
288 val
= MCBSP_ST_READ(mcbsp
, SSELCR
);
290 if (val
& ST_COEFFWREN
)
291 MCBSP_ST_WRITE(mcbsp
, SSELCR
, val
& ~(ST_COEFFWREN
));
293 MCBSP_ST_WRITE(mcbsp
, SSELCR
, val
| ST_COEFFWREN
);
295 for (i
= 0; i
< 128; i
++)
296 MCBSP_ST_WRITE(mcbsp
, SFIRCR
, fir
[i
]);
300 val
= MCBSP_ST_READ(mcbsp
, SSELCR
);
301 while (!(val
& ST_COEFFWRDONE
) && (++i
< 1000))
302 val
= MCBSP_ST_READ(mcbsp
, SSELCR
);
304 MCBSP_ST_WRITE(mcbsp
, SSELCR
, val
& ~(ST_COEFFWREN
));
307 dev_err(mcbsp
->dev
, "McBSP FIR load error!\n");
310 static void omap_st_chgain(struct omap_mcbsp
*mcbsp
)
313 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
315 w
= MCBSP_ST_READ(mcbsp
, SSELCR
);
317 MCBSP_ST_WRITE(mcbsp
, SGAINCR
, ST_CH0GAIN(st_data
->ch0gain
) | \
318 ST_CH1GAIN(st_data
->ch1gain
));
321 int omap_st_set_chgain(unsigned int id
, int channel
, s16 chgain
)
323 struct omap_mcbsp
*mcbsp
;
324 struct omap_mcbsp_st_data
*st_data
;
327 if (!omap_mcbsp_check_valid_id(id
)) {
328 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
332 mcbsp
= id_to_mcbsp_ptr(id
);
333 st_data
= mcbsp
->st_data
;
338 spin_lock_irq(&mcbsp
->lock
);
340 st_data
->ch0gain
= chgain
;
341 else if (channel
== 1)
342 st_data
->ch1gain
= chgain
;
346 if (st_data
->enabled
)
347 omap_st_chgain(mcbsp
);
348 spin_unlock_irq(&mcbsp
->lock
);
352 EXPORT_SYMBOL(omap_st_set_chgain
);
354 int omap_st_get_chgain(unsigned int id
, int channel
, s16
*chgain
)
356 struct omap_mcbsp
*mcbsp
;
357 struct omap_mcbsp_st_data
*st_data
;
360 if (!omap_mcbsp_check_valid_id(id
)) {
361 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
365 mcbsp
= id_to_mcbsp_ptr(id
);
366 st_data
= mcbsp
->st_data
;
371 spin_lock_irq(&mcbsp
->lock
);
373 *chgain
= st_data
->ch0gain
;
374 else if (channel
== 1)
375 *chgain
= st_data
->ch1gain
;
378 spin_unlock_irq(&mcbsp
->lock
);
382 EXPORT_SYMBOL(omap_st_get_chgain
);
384 static int omap_st_start(struct omap_mcbsp
*mcbsp
)
386 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
388 if (st_data
&& st_data
->enabled
&& !st_data
->running
) {
389 omap_st_fir_write(mcbsp
, st_data
->taps
);
390 omap_st_chgain(mcbsp
);
394 st_data
->running
= 1;
401 int omap_st_enable(unsigned int id
)
403 struct omap_mcbsp
*mcbsp
;
404 struct omap_mcbsp_st_data
*st_data
;
406 if (!omap_mcbsp_check_valid_id(id
)) {
407 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
411 mcbsp
= id_to_mcbsp_ptr(id
);
412 st_data
= mcbsp
->st_data
;
417 spin_lock_irq(&mcbsp
->lock
);
418 st_data
->enabled
= 1;
419 omap_st_start(mcbsp
);
420 spin_unlock_irq(&mcbsp
->lock
);
424 EXPORT_SYMBOL(omap_st_enable
);
426 static int omap_st_stop(struct omap_mcbsp
*mcbsp
)
428 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
430 if (st_data
&& st_data
->running
) {
433 st_data
->running
= 0;
440 int omap_st_disable(unsigned int id
)
442 struct omap_mcbsp
*mcbsp
;
443 struct omap_mcbsp_st_data
*st_data
;
446 if (!omap_mcbsp_check_valid_id(id
)) {
447 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
451 mcbsp
= id_to_mcbsp_ptr(id
);
452 st_data
= mcbsp
->st_data
;
457 spin_lock_irq(&mcbsp
->lock
);
459 st_data
->enabled
= 0;
460 spin_unlock_irq(&mcbsp
->lock
);
464 EXPORT_SYMBOL(omap_st_disable
);
466 int omap_st_is_enabled(unsigned int id
)
468 struct omap_mcbsp
*mcbsp
;
469 struct omap_mcbsp_st_data
*st_data
;
471 if (!omap_mcbsp_check_valid_id(id
)) {
472 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
476 mcbsp
= id_to_mcbsp_ptr(id
);
477 st_data
= mcbsp
->st_data
;
483 return st_data
->enabled
;
485 EXPORT_SYMBOL(omap_st_is_enabled
);
488 * omap_mcbsp_set_rx_threshold configures the transmit threshold in words.
489 * The threshold parameter is 1 based, and it is converted (threshold - 1)
490 * for the THRSH2 register.
492 void omap_mcbsp_set_tx_threshold(unsigned int id
, u16 threshold
)
494 struct omap_mcbsp
*mcbsp
;
496 if (!omap_mcbsp_check_valid_id(id
)) {
497 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
500 mcbsp
= id_to_mcbsp_ptr(id
);
501 if (mcbsp
->pdata
->buffer_size
== 0)
504 if (threshold
&& threshold
<= mcbsp
->max_tx_thres
)
505 MCBSP_WRITE(mcbsp
, THRSH2
, threshold
- 1);
507 EXPORT_SYMBOL(omap_mcbsp_set_tx_threshold
);
510 * omap_mcbsp_set_rx_threshold configures the receive threshold in words.
511 * The threshold parameter is 1 based, and it is converted (threshold - 1)
512 * for the THRSH1 register.
514 void omap_mcbsp_set_rx_threshold(unsigned int id
, u16 threshold
)
516 struct omap_mcbsp
*mcbsp
;
518 if (!omap_mcbsp_check_valid_id(id
)) {
519 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
522 mcbsp
= id_to_mcbsp_ptr(id
);
523 if (mcbsp
->pdata
->buffer_size
== 0)
526 if (threshold
&& threshold
<= mcbsp
->max_rx_thres
)
527 MCBSP_WRITE(mcbsp
, THRSH1
, threshold
- 1);
529 EXPORT_SYMBOL(omap_mcbsp_set_rx_threshold
);
532 * omap_mcbsp_get_max_tx_thres just return the current configured
533 * maximum threshold for transmission
535 u16
omap_mcbsp_get_max_tx_threshold(unsigned int id
)
537 struct omap_mcbsp
*mcbsp
;
539 if (!omap_mcbsp_check_valid_id(id
)) {
540 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
543 mcbsp
= id_to_mcbsp_ptr(id
);
545 return mcbsp
->max_tx_thres
;
547 EXPORT_SYMBOL(omap_mcbsp_get_max_tx_threshold
);
550 * omap_mcbsp_get_max_rx_thres just return the current configured
551 * maximum threshold for reception
553 u16
omap_mcbsp_get_max_rx_threshold(unsigned int id
)
555 struct omap_mcbsp
*mcbsp
;
557 if (!omap_mcbsp_check_valid_id(id
)) {
558 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
561 mcbsp
= id_to_mcbsp_ptr(id
);
563 return mcbsp
->max_rx_thres
;
565 EXPORT_SYMBOL(omap_mcbsp_get_max_rx_threshold
);
567 u16
omap_mcbsp_get_fifo_size(unsigned int id
)
569 struct omap_mcbsp
*mcbsp
;
571 if (!omap_mcbsp_check_valid_id(id
)) {
572 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
575 mcbsp
= id_to_mcbsp_ptr(id
);
577 return mcbsp
->pdata
->buffer_size
;
579 EXPORT_SYMBOL(omap_mcbsp_get_fifo_size
);
582 * omap_mcbsp_get_tx_delay returns the number of used slots in the McBSP FIFO
584 u16
omap_mcbsp_get_tx_delay(unsigned int id
)
586 struct omap_mcbsp
*mcbsp
;
589 if (!omap_mcbsp_check_valid_id(id
)) {
590 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
593 mcbsp
= id_to_mcbsp_ptr(id
);
594 if (mcbsp
->pdata
->buffer_size
== 0)
597 /* Returns the number of free locations in the buffer */
598 buffstat
= MCBSP_READ(mcbsp
, XBUFFSTAT
);
600 /* Number of slots are different in McBSP ports */
601 return mcbsp
->pdata
->buffer_size
- buffstat
;
603 EXPORT_SYMBOL(omap_mcbsp_get_tx_delay
);
606 * omap_mcbsp_get_rx_delay returns the number of free slots in the McBSP FIFO
607 * to reach the threshold value (when the DMA will be triggered to read it)
609 u16
omap_mcbsp_get_rx_delay(unsigned int id
)
611 struct omap_mcbsp
*mcbsp
;
612 u16 buffstat
, threshold
;
614 if (!omap_mcbsp_check_valid_id(id
)) {
615 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
618 mcbsp
= id_to_mcbsp_ptr(id
);
619 if (mcbsp
->pdata
->buffer_size
== 0)
622 /* Returns the number of used locations in the buffer */
623 buffstat
= MCBSP_READ(mcbsp
, RBUFFSTAT
);
625 threshold
= MCBSP_READ(mcbsp
, THRSH1
);
627 /* Return the number of location till we reach the threshold limit */
628 if (threshold
<= buffstat
)
631 return threshold
- buffstat
;
633 EXPORT_SYMBOL(omap_mcbsp_get_rx_delay
);
636 * omap_mcbsp_get_dma_op_mode just return the current configured
637 * operating mode for the mcbsp channel
639 int omap_mcbsp_get_dma_op_mode(unsigned int id
)
641 struct omap_mcbsp
*mcbsp
;
644 if (!omap_mcbsp_check_valid_id(id
)) {
645 printk(KERN_ERR
"%s: Invalid id (%u)\n", __func__
, id
+ 1);
648 mcbsp
= id_to_mcbsp_ptr(id
);
650 dma_op_mode
= mcbsp
->dma_op_mode
;
654 EXPORT_SYMBOL(omap_mcbsp_get_dma_op_mode
);
656 int omap_mcbsp_request(unsigned int id
)
658 struct omap_mcbsp
*mcbsp
;
662 if (!omap_mcbsp_check_valid_id(id
)) {
663 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
666 mcbsp
= id_to_mcbsp_ptr(id
);
668 reg_cache
= kzalloc(mcbsp
->reg_cache_size
, GFP_KERNEL
);
673 spin_lock(&mcbsp
->lock
);
675 dev_err(mcbsp
->dev
, "McBSP%d is currently in use\n",
682 mcbsp
->reg_cache
= reg_cache
;
683 spin_unlock(&mcbsp
->lock
);
685 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->request
)
686 mcbsp
->pdata
->ops
->request(id
);
688 pm_runtime_get_sync(mcbsp
->dev
);
690 /* Enable wakeup behavior */
691 if (mcbsp
->pdata
->has_wakeup
)
692 MCBSP_WRITE(mcbsp
, WAKEUPEN
, XRDYEN
| RRDYEN
);
695 * Make sure that transmitter, receiver and sample-rate generator are
696 * not running before activating IRQs.
698 MCBSP_WRITE(mcbsp
, SPCR1
, 0);
699 MCBSP_WRITE(mcbsp
, SPCR2
, 0);
701 err
= request_irq(mcbsp
->tx_irq
, omap_mcbsp_tx_irq_handler
,
702 0, "McBSP", (void *)mcbsp
);
704 dev_err(mcbsp
->dev
, "Unable to request TX IRQ %d "
705 "for McBSP%d\n", mcbsp
->tx_irq
,
707 goto err_clk_disable
;
711 err
= request_irq(mcbsp
->rx_irq
,
712 omap_mcbsp_rx_irq_handler
,
713 0, "McBSP", (void *)mcbsp
);
715 dev_err(mcbsp
->dev
, "Unable to request RX IRQ %d "
716 "for McBSP%d\n", mcbsp
->rx_irq
,
724 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
726 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->free
)
727 mcbsp
->pdata
->ops
->free(id
);
729 /* Disable wakeup behavior */
730 if (mcbsp
->pdata
->has_wakeup
)
731 MCBSP_WRITE(mcbsp
, WAKEUPEN
, 0);
733 pm_runtime_put_sync(mcbsp
->dev
);
735 spin_lock(&mcbsp
->lock
);
737 mcbsp
->reg_cache
= NULL
;
739 spin_unlock(&mcbsp
->lock
);
744 EXPORT_SYMBOL(omap_mcbsp_request
);
746 void omap_mcbsp_free(unsigned int id
)
748 struct omap_mcbsp
*mcbsp
;
751 if (!omap_mcbsp_check_valid_id(id
)) {
752 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
755 mcbsp
= id_to_mcbsp_ptr(id
);
757 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&& mcbsp
->pdata
->ops
->free
)
758 mcbsp
->pdata
->ops
->free(id
);
760 /* Disable wakeup behavior */
761 if (mcbsp
->pdata
->has_wakeup
)
762 MCBSP_WRITE(mcbsp
, WAKEUPEN
, 0);
764 pm_runtime_put_sync(mcbsp
->dev
);
767 free_irq(mcbsp
->rx_irq
, (void *)mcbsp
);
768 free_irq(mcbsp
->tx_irq
, (void *)mcbsp
);
770 reg_cache
= mcbsp
->reg_cache
;
772 spin_lock(&mcbsp
->lock
);
774 dev_err(mcbsp
->dev
, "McBSP%d was not reserved\n", mcbsp
->id
);
777 mcbsp
->reg_cache
= NULL
;
778 spin_unlock(&mcbsp
->lock
);
783 EXPORT_SYMBOL(omap_mcbsp_free
);
786 * Here we start the McBSP, by enabling transmitter, receiver or both.
787 * If no transmitter or receiver is active prior calling, then sample-rate
788 * generator and frame sync are started.
790 void omap_mcbsp_start(unsigned int id
, int tx
, int rx
)
792 struct omap_mcbsp
*mcbsp
;
796 if (!omap_mcbsp_check_valid_id(id
)) {
797 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
800 mcbsp
= id_to_mcbsp_ptr(id
);
803 omap_st_start(mcbsp
);
805 /* Only enable SRG, if McBSP is master */
806 w
= MCBSP_READ_CACHE(mcbsp
, PCR0
);
807 if (w
& (FSXM
| FSRM
| CLKXM
| CLKRM
))
808 enable_srg
= !((MCBSP_READ_CACHE(mcbsp
, SPCR2
) |
809 MCBSP_READ_CACHE(mcbsp
, SPCR1
)) & 1);
812 /* Start the sample generator */
813 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
814 MCBSP_WRITE(mcbsp
, SPCR2
, w
| (1 << 6));
817 /* Enable transmitter and receiver */
819 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
820 MCBSP_WRITE(mcbsp
, SPCR2
, w
| tx
);
823 w
= MCBSP_READ_CACHE(mcbsp
, SPCR1
);
824 MCBSP_WRITE(mcbsp
, SPCR1
, w
| rx
);
827 * Worst case: CLKSRG*2 = 8000khz: (1/8000) * 2 * 2 usec
828 * REVISIT: 100us may give enough time for two CLKSRG, however
829 * due to some unknown PM related, clock gating etc. reason it
835 /* Start frame sync */
836 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
837 MCBSP_WRITE(mcbsp
, SPCR2
, w
| (1 << 7));
840 if (mcbsp
->pdata
->has_ccr
) {
841 /* Release the transmitter and receiver */
842 w
= MCBSP_READ_CACHE(mcbsp
, XCCR
);
843 w
&= ~(tx
? XDISABLE
: 0);
844 MCBSP_WRITE(mcbsp
, XCCR
, w
);
845 w
= MCBSP_READ_CACHE(mcbsp
, RCCR
);
846 w
&= ~(rx
? RDISABLE
: 0);
847 MCBSP_WRITE(mcbsp
, RCCR
, w
);
850 /* Dump McBSP Regs */
851 omap_mcbsp_dump_reg(id
);
853 EXPORT_SYMBOL(omap_mcbsp_start
);
855 void omap_mcbsp_stop(unsigned int id
, int tx
, int rx
)
857 struct omap_mcbsp
*mcbsp
;
861 if (!omap_mcbsp_check_valid_id(id
)) {
862 printk(KERN_ERR
"%s: Invalid id (%d)\n", __func__
, id
+ 1);
866 mcbsp
= id_to_mcbsp_ptr(id
);
868 /* Reset transmitter */
870 if (mcbsp
->pdata
->has_ccr
) {
871 w
= MCBSP_READ_CACHE(mcbsp
, XCCR
);
872 w
|= (tx
? XDISABLE
: 0);
873 MCBSP_WRITE(mcbsp
, XCCR
, w
);
875 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
876 MCBSP_WRITE(mcbsp
, SPCR2
, w
& ~tx
);
880 if (mcbsp
->pdata
->has_ccr
) {
881 w
= MCBSP_READ_CACHE(mcbsp
, RCCR
);
882 w
|= (rx
? RDISABLE
: 0);
883 MCBSP_WRITE(mcbsp
, RCCR
, w
);
885 w
= MCBSP_READ_CACHE(mcbsp
, SPCR1
);
886 MCBSP_WRITE(mcbsp
, SPCR1
, w
& ~rx
);
888 idle
= !((MCBSP_READ_CACHE(mcbsp
, SPCR2
) |
889 MCBSP_READ_CACHE(mcbsp
, SPCR1
)) & 1);
892 /* Reset the sample rate generator */
893 w
= MCBSP_READ_CACHE(mcbsp
, SPCR2
);
894 MCBSP_WRITE(mcbsp
, SPCR2
, w
& ~(1 << 6));
900 EXPORT_SYMBOL(omap_mcbsp_stop
);
902 int omap2_mcbsp_set_clks_src(u8 id
, u8 fck_src_id
)
904 struct omap_mcbsp
*mcbsp
;
907 if (!omap_mcbsp_check_valid_id(id
)) {
908 pr_err("%s: Invalid id (%d)\n", __func__
, id
+ 1);
911 mcbsp
= id_to_mcbsp_ptr(id
);
913 if (fck_src_id
== MCBSP_CLKS_PAD_SRC
)
915 else if (fck_src_id
== MCBSP_CLKS_PRCM_SRC
)
920 if (mcbsp
->pdata
->set_clk_src
)
921 return mcbsp
->pdata
->set_clk_src(mcbsp
->dev
, mcbsp
->fclk
, src
);
925 EXPORT_SYMBOL(omap2_mcbsp_set_clks_src
);
927 void omap2_mcbsp1_mux_clkr_src(u8 mux
)
929 struct omap_mcbsp
*mcbsp
;
932 if (mux
== CLKR_SRC_CLKR
)
934 else if (mux
== CLKR_SRC_CLKX
)
939 mcbsp
= id_to_mcbsp_ptr(0);
940 if (mcbsp
->pdata
->mux_signal
)
941 mcbsp
->pdata
->mux_signal(mcbsp
->dev
, "clkr", src
);
943 EXPORT_SYMBOL(omap2_mcbsp1_mux_clkr_src
);
945 void omap2_mcbsp1_mux_fsr_src(u8 mux
)
947 struct omap_mcbsp
*mcbsp
;
950 if (mux
== FSR_SRC_FSR
)
952 else if (mux
== FSR_SRC_FSX
)
957 mcbsp
= id_to_mcbsp_ptr(0);
958 if (mcbsp
->pdata
->mux_signal
)
959 mcbsp
->pdata
->mux_signal(mcbsp
->dev
, "fsr", src
);
961 EXPORT_SYMBOL(omap2_mcbsp1_mux_fsr_src
);
963 #define max_thres(m) (mcbsp->pdata->buffer_size)
964 #define valid_threshold(m, val) ((val) <= max_thres(m))
965 #define THRESHOLD_PROP_BUILDER(prop) \
966 static ssize_t prop##_show(struct device *dev, \
967 struct device_attribute *attr, char *buf) \
969 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
971 return sprintf(buf, "%u\n", mcbsp->prop); \
974 static ssize_t prop##_store(struct device *dev, \
975 struct device_attribute *attr, \
976 const char *buf, size_t size) \
978 struct omap_mcbsp *mcbsp = dev_get_drvdata(dev); \
982 status = strict_strtoul(buf, 0, &val); \
986 if (!valid_threshold(mcbsp, val)) \
993 static DEVICE_ATTR(prop, 0644, prop##_show, prop##_store);
995 THRESHOLD_PROP_BUILDER(max_tx_thres
);
996 THRESHOLD_PROP_BUILDER(max_rx_thres
);
998 static const char *dma_op_modes
[] = {
999 "element", "threshold", "frame",
1002 static ssize_t
dma_op_mode_show(struct device
*dev
,
1003 struct device_attribute
*attr
, char *buf
)
1005 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1006 int dma_op_mode
, i
= 0;
1008 const char * const *s
;
1010 dma_op_mode
= mcbsp
->dma_op_mode
;
1012 for (s
= &dma_op_modes
[i
]; i
< ARRAY_SIZE(dma_op_modes
); s
++, i
++) {
1013 if (dma_op_mode
== i
)
1014 len
+= sprintf(buf
+ len
, "[%s] ", *s
);
1016 len
+= sprintf(buf
+ len
, "%s ", *s
);
1018 len
+= sprintf(buf
+ len
, "\n");
1023 static ssize_t
dma_op_mode_store(struct device
*dev
,
1024 struct device_attribute
*attr
,
1025 const char *buf
, size_t size
)
1027 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1028 const char * const *s
;
1031 for (s
= &dma_op_modes
[i
]; i
< ARRAY_SIZE(dma_op_modes
); s
++, i
++)
1032 if (sysfs_streq(buf
, *s
))
1035 if (i
== ARRAY_SIZE(dma_op_modes
))
1038 spin_lock_irq(&mcbsp
->lock
);
1043 mcbsp
->dma_op_mode
= i
;
1046 spin_unlock_irq(&mcbsp
->lock
);
1051 static DEVICE_ATTR(dma_op_mode
, 0644, dma_op_mode_show
, dma_op_mode_store
);
1053 static const struct attribute
*additional_attrs
[] = {
1054 &dev_attr_max_tx_thres
.attr
,
1055 &dev_attr_max_rx_thres
.attr
,
1056 &dev_attr_dma_op_mode
.attr
,
1060 static const struct attribute_group additional_attr_group
= {
1061 .attrs
= (struct attribute
**)additional_attrs
,
1064 static ssize_t
st_taps_show(struct device
*dev
,
1065 struct device_attribute
*attr
, char *buf
)
1067 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1068 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
1072 spin_lock_irq(&mcbsp
->lock
);
1073 for (i
= 0; i
< st_data
->nr_taps
; i
++)
1074 status
+= sprintf(&buf
[status
], (i
? ", %d" : "%d"),
1077 status
+= sprintf(&buf
[status
], "\n");
1078 spin_unlock_irq(&mcbsp
->lock
);
1083 static ssize_t
st_taps_store(struct device
*dev
,
1084 struct device_attribute
*attr
,
1085 const char *buf
, size_t size
)
1087 struct omap_mcbsp
*mcbsp
= dev_get_drvdata(dev
);
1088 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
1089 int val
, tmp
, status
, i
= 0;
1091 spin_lock_irq(&mcbsp
->lock
);
1092 memset(st_data
->taps
, 0, sizeof(st_data
->taps
));
1093 st_data
->nr_taps
= 0;
1096 status
= sscanf(buf
, "%d%n", &val
, &tmp
);
1097 if (status
< 0 || status
== 0) {
1101 if (val
< -32768 || val
> 32767) {
1105 st_data
->taps
[i
++] = val
;
1112 st_data
->nr_taps
= i
;
1115 spin_unlock_irq(&mcbsp
->lock
);
1120 static DEVICE_ATTR(st_taps
, 0644, st_taps_show
, st_taps_store
);
1122 static const struct attribute
*sidetone_attrs
[] = {
1123 &dev_attr_st_taps
.attr
,
1127 static const struct attribute_group sidetone_attr_group
= {
1128 .attrs
= (struct attribute
**)sidetone_attrs
,
1131 static int __devinit
omap_st_add(struct omap_mcbsp
*mcbsp
,
1132 struct resource
*res
)
1134 struct omap_mcbsp_st_data
*st_data
;
1137 st_data
= kzalloc(sizeof(*mcbsp
->st_data
), GFP_KERNEL
);
1143 st_data
->io_base_st
= ioremap(res
->start
, resource_size(res
));
1144 if (!st_data
->io_base_st
) {
1149 err
= sysfs_create_group(&mcbsp
->dev
->kobj
, &sidetone_attr_group
);
1153 mcbsp
->st_data
= st_data
;
1157 iounmap(st_data
->io_base_st
);
1165 static void __devexit
omap_st_remove(struct omap_mcbsp
*mcbsp
)
1167 struct omap_mcbsp_st_data
*st_data
= mcbsp
->st_data
;
1169 sysfs_remove_group(&mcbsp
->dev
->kobj
, &sidetone_attr_group
);
1170 iounmap(st_data
->io_base_st
);
1175 * McBSP1 and McBSP3 are directly mapped on 1610 and 1510.
1176 * 730 has only 2 McBSP, and both of them are MPU peripherals.
1178 static int __devinit
omap_mcbsp_probe(struct platform_device
*pdev
)
1180 struct omap_mcbsp_platform_data
*pdata
= pdev
->dev
.platform_data
;
1181 struct omap_mcbsp
*mcbsp
;
1182 int id
= pdev
->id
- 1;
1183 struct resource
*res
;
1187 dev_err(&pdev
->dev
, "McBSP device initialized without"
1193 dev_dbg(&pdev
->dev
, "Initializing OMAP McBSP (%d).\n", pdev
->id
);
1195 if (id
>= omap_mcbsp_count
) {
1196 dev_err(&pdev
->dev
, "Invalid McBSP device id (%d)\n", id
);
1201 mcbsp
= kzalloc(sizeof(struct omap_mcbsp
), GFP_KERNEL
);
1207 spin_lock_init(&mcbsp
->lock
);
1211 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mpu");
1213 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1215 dev_err(&pdev
->dev
, "%s:mcbsp%d has invalid memory"
1216 "resource\n", __func__
, pdev
->id
);
1221 mcbsp
->phys_base
= res
->start
;
1222 mcbsp
->reg_cache_size
= resource_size(res
);
1223 mcbsp
->io_base
= ioremap(res
->start
, resource_size(res
));
1224 if (!mcbsp
->io_base
) {
1229 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "dma");
1231 mcbsp
->phys_dma_base
= mcbsp
->phys_base
;
1233 mcbsp
->phys_dma_base
= res
->start
;
1235 mcbsp
->tx_irq
= platform_get_irq_byname(pdev
, "tx");
1236 mcbsp
->rx_irq
= platform_get_irq_byname(pdev
, "rx");
1238 /* From OMAP4 there will be a single irq line */
1239 if (mcbsp
->tx_irq
== -ENXIO
)
1240 mcbsp
->tx_irq
= platform_get_irq(pdev
, 0);
1242 res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
, "rx");
1244 dev_err(&pdev
->dev
, "%s:mcbsp%d has invalid rx DMA channel\n",
1245 __func__
, pdev
->id
);
1249 mcbsp
->dma_rx_sync
= res
->start
;
1251 res
= platform_get_resource_byname(pdev
, IORESOURCE_DMA
, "tx");
1253 dev_err(&pdev
->dev
, "%s:mcbsp%d has invalid tx DMA channel\n",
1254 __func__
, pdev
->id
);
1258 mcbsp
->dma_tx_sync
= res
->start
;
1260 mcbsp
->fclk
= clk_get(&pdev
->dev
, "fck");
1261 if (IS_ERR(mcbsp
->fclk
)) {
1262 ret
= PTR_ERR(mcbsp
->fclk
);
1263 dev_err(&pdev
->dev
, "unable to get fck: %d\n", ret
);
1267 mcbsp
->pdata
= pdata
;
1268 mcbsp
->dev
= &pdev
->dev
;
1269 mcbsp_ptr
[id
] = mcbsp
;
1270 platform_set_drvdata(pdev
, mcbsp
);
1271 pm_runtime_enable(mcbsp
->dev
);
1273 mcbsp
->dma_op_mode
= MCBSP_DMA_MODE_ELEMENT
;
1274 if (mcbsp
->pdata
->buffer_size
) {
1276 * Initially configure the maximum thresholds to a safe value.
1277 * The McBSP FIFO usage with these values should not go under
1279 * If the whole FIFO without safety buffer is used, than there
1280 * is a possibility that the DMA will be not able to push the
1281 * new data on time, causing channel shifts in runtime.
1283 mcbsp
->max_tx_thres
= max_thres(mcbsp
) - 0x10;
1284 mcbsp
->max_rx_thres
= max_thres(mcbsp
) - 0x10;
1286 ret
= sysfs_create_group(&mcbsp
->dev
->kobj
,
1287 &additional_attr_group
);
1290 "Unable to create additional controls\n");
1294 mcbsp
->max_tx_thres
= -EINVAL
;
1295 mcbsp
->max_rx_thres
= -EINVAL
;
1298 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "sidetone");
1300 ret
= omap_st_add(mcbsp
, res
);
1303 "Unable to create sidetone controls\n");
1311 if (mcbsp
->pdata
->buffer_size
)
1312 sysfs_remove_group(&mcbsp
->dev
->kobj
,
1313 &additional_attr_group
);
1315 clk_put(mcbsp
->fclk
);
1317 iounmap(mcbsp
->io_base
);
1324 static int __devexit
omap_mcbsp_remove(struct platform_device
*pdev
)
1326 struct omap_mcbsp
*mcbsp
= platform_get_drvdata(pdev
);
1328 platform_set_drvdata(pdev
, NULL
);
1331 if (mcbsp
->pdata
&& mcbsp
->pdata
->ops
&&
1332 mcbsp
->pdata
->ops
->free
)
1333 mcbsp
->pdata
->ops
->free(mcbsp
->id
);
1335 if (mcbsp
->pdata
->buffer_size
)
1336 sysfs_remove_group(&mcbsp
->dev
->kobj
,
1337 &additional_attr_group
);
1340 omap_st_remove(mcbsp
);
1342 clk_put(mcbsp
->fclk
);
1344 iounmap(mcbsp
->io_base
);
1351 static struct platform_driver omap_mcbsp_driver
= {
1352 .probe
= omap_mcbsp_probe
,
1353 .remove
= __devexit_p(omap_mcbsp_remove
),
1355 .name
= "omap-mcbsp",
1359 module_platform_driver(omap_mcbsp_driver
);
1361 MODULE_AUTHOR("Samuel Ortiz <samuel.ortiz@nokia.com>");
1362 MODULE_DESCRIPTION("OMAP McBSP core driver");
1363 MODULE_LICENSE("GPL");
1364 MODULE_ALIAS("platform:omap-mcbsp");