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powerpc: Remove function descriptors and dot symbols on new ABI
[linux-2.6/btrfs-unstable.git] / drivers / tty / serial / sh-sci.c
blob88236da0ddf731ae13d0701448497595e389ef62
1 /*
2 * SuperH on-chip serial module support. (SCI with no FIFO / with FIFO)
3 *
4 * Copyright (C) 2002 - 2011 Paul Mundt
5 * Modified to support SH7720 SCIF. Markus Brunner, Mark Jonas (Jul 2007).
6 *
7 * based off of the old drivers/char/sh-sci.c by:
8 *
9 * Copyright (C) 1999, 2000 Niibe Yutaka
10 * Copyright (C) 2000 Sugioka Toshinobu
11 * Modified to support multiple serial ports. Stuart Menefy (May 2000).
12 * Modified to support SecureEdge. David McCullough (2002)
13 * Modified to support SH7300 SCIF. Takashi Kusuda (Jun 2003).
14 * Removed SH7300 support (Jul 2007).
15 *
16 * This file is subject to the terms and conditions of the GNU General Public
17 * License. See the file "COPYING" in the main directory of this archive
18 * for more details.
19 */
20 #if defined(CONFIG_SERIAL_SH_SCI_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
21 #define SUPPORT_SYSRQ
22 #endif
23
24 #undef DEBUG
25
26 #include <linux/clk.h>
27 #include <linux/console.h>
28 #include <linux/ctype.h>
29 #include <linux/cpufreq.h>
30 #include <linux/delay.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/errno.h>
35 #include <linux/init.h>
36 #include <linux/interrupt.h>
37 #include <linux/ioport.h>
38 #include <linux/major.h>
39 #include <linux/module.h>
40 #include <linux/mm.h>
41 #include <linux/notifier.h>
42 #include <linux/of.h>
43 #include <linux/platform_device.h>
44 #include <linux/pm_runtime.h>
45 #include <linux/scatterlist.h>
46 #include <linux/serial.h>
47 #include <linux/serial_sci.h>
48 #include <linux/sh_dma.h>
49 #include <linux/slab.h>
50 #include <linux/string.h>
51 #include <linux/sysrq.h>
52 #include <linux/timer.h>
53 #include <linux/tty.h>
54 #include <linux/tty_flip.h>
55
56 #ifdef CONFIG_SUPERH
57 #include <asm/sh_bios.h>
58 #endif
59
60 #include "sh-sci.h"
61
62 /* Offsets into the sci_port->irqs array */
63 enum {
64 SCIx_ERI_IRQ,
65 SCIx_RXI_IRQ,
66 SCIx_TXI_IRQ,
67 SCIx_BRI_IRQ,
68 SCIx_NR_IRQS,
69
70 SCIx_MUX_IRQ = SCIx_NR_IRQS, /* special case */
71 };
72
73 #define SCIx_IRQ_IS_MUXED(port) \
74 ((port)->irqs[SCIx_ERI_IRQ] == \
75 (port)->irqs[SCIx_RXI_IRQ]) || \
76 ((port)->irqs[SCIx_ERI_IRQ] && \
77 ((port)->irqs[SCIx_RXI_IRQ] < 0))
78
79 struct sci_port {
80 struct uart_port port;
81
82 /* Platform configuration */
83 struct plat_sci_port *cfg;
84 int overrun_bit;
85 unsigned int error_mask;
86 unsigned int sampling_rate;
87
88
89 /* Break timer */
90 struct timer_list break_timer;
91 int break_flag;
92
93 /* Interface clock */
94 struct clk *iclk;
95 /* Function clock */
96 struct clk *fclk;
97
98 int irqs[SCIx_NR_IRQS];
99 char *irqstr[SCIx_NR_IRQS];
100
101 struct dma_chan *chan_tx;
102 struct dma_chan *chan_rx;
103
104 #ifdef CONFIG_SERIAL_SH_SCI_DMA
105 struct dma_async_tx_descriptor *desc_tx;
106 struct dma_async_tx_descriptor *desc_rx[2];
107 dma_cookie_t cookie_tx;
108 dma_cookie_t cookie_rx[2];
109 dma_cookie_t active_rx;
110 struct scatterlist sg_tx;
111 unsigned int sg_len_tx;
112 struct scatterlist sg_rx[2];
113 size_t buf_len_rx;
114 struct sh_dmae_slave param_tx;
115 struct sh_dmae_slave param_rx;
116 struct work_struct work_tx;
117 struct work_struct work_rx;
118 struct timer_list rx_timer;
119 unsigned int rx_timeout;
120 #endif
121
122 struct notifier_block freq_transition;
123 };
124
125 /* Function prototypes */
126 static void sci_start_tx(struct uart_port *port);
127 static void sci_stop_tx(struct uart_port *port);
128 static void sci_start_rx(struct uart_port *port);
129
130 #define SCI_NPORTS CONFIG_SERIAL_SH_SCI_NR_UARTS
131
132 static struct sci_port sci_ports[SCI_NPORTS];
133 static struct uart_driver sci_uart_driver;
134
135 static inline struct sci_port *
136 to_sci_port(struct uart_port *uart)
137 {
138 return container_of(uart, struct sci_port, port);
139 }
140
141 struct plat_sci_reg {
142 u8 offset, size;
143 };
144
145 /* Helper for invalidating specific entries of an inherited map. */
146 #define sci_reg_invalid { .offset = 0, .size = 0 }
147
148 static struct plat_sci_reg sci_regmap[SCIx_NR_REGTYPES][SCIx_NR_REGS] = {
149 [SCIx_PROBE_REGTYPE] = {
150 [0 ... SCIx_NR_REGS - 1] = sci_reg_invalid,
151 },
152
153 /*
154 * Common SCI definitions, dependent on the port's regshift
155 * value.
156 */
157 [SCIx_SCI_REGTYPE] = {
158 [SCSMR] = { 0x00, 8 },
159 [SCBRR] = { 0x01, 8 },
160 [SCSCR] = { 0x02, 8 },
161 [SCxTDR] = { 0x03, 8 },
162 [SCxSR] = { 0x04, 8 },
163 [SCxRDR] = { 0x05, 8 },
164 [SCFCR] = sci_reg_invalid,
165 [SCFDR] = sci_reg_invalid,
166 [SCTFDR] = sci_reg_invalid,
167 [SCRFDR] = sci_reg_invalid,
168 [SCSPTR] = sci_reg_invalid,
169 [SCLSR] = sci_reg_invalid,
170 [HSSRR] = sci_reg_invalid,
171 },
172
173 /*
174 * Common definitions for legacy IrDA ports, dependent on
175 * regshift value.
176 */
177 [SCIx_IRDA_REGTYPE] = {
178 [SCSMR] = { 0x00, 8 },
179 [SCBRR] = { 0x01, 8 },
180 [SCSCR] = { 0x02, 8 },
181 [SCxTDR] = { 0x03, 8 },
182 [SCxSR] = { 0x04, 8 },
183 [SCxRDR] = { 0x05, 8 },
184 [SCFCR] = { 0x06, 8 },
185 [SCFDR] = { 0x07, 16 },
186 [SCTFDR] = sci_reg_invalid,
187 [SCRFDR] = sci_reg_invalid,
188 [SCSPTR] = sci_reg_invalid,
189 [SCLSR] = sci_reg_invalid,
190 [HSSRR] = sci_reg_invalid,
191 },
192
193 /*
194 * Common SCIFA definitions.
195 */
196 [SCIx_SCIFA_REGTYPE] = {
197 [SCSMR] = { 0x00, 16 },
198 [SCBRR] = { 0x04, 8 },
199 [SCSCR] = { 0x08, 16 },
200 [SCxTDR] = { 0x20, 8 },
201 [SCxSR] = { 0x14, 16 },
202 [SCxRDR] = { 0x24, 8 },
203 [SCFCR] = { 0x18, 16 },
204 [SCFDR] = { 0x1c, 16 },
205 [SCTFDR] = sci_reg_invalid,
206 [SCRFDR] = sci_reg_invalid,
207 [SCSPTR] = sci_reg_invalid,
208 [SCLSR] = sci_reg_invalid,
209 [HSSRR] = sci_reg_invalid,
210 },
211
212 /*
213 * Common SCIFB definitions.
214 */
215 [SCIx_SCIFB_REGTYPE] = {
216 [SCSMR] = { 0x00, 16 },
217 [SCBRR] = { 0x04, 8 },
218 [SCSCR] = { 0x08, 16 },
219 [SCxTDR] = { 0x40, 8 },
220 [SCxSR] = { 0x14, 16 },
221 [SCxRDR] = { 0x60, 8 },
222 [SCFCR] = { 0x18, 16 },
223 [SCFDR] = sci_reg_invalid,
224 [SCTFDR] = { 0x38, 16 },
225 [SCRFDR] = { 0x3c, 16 },
226 [SCSPTR] = sci_reg_invalid,
227 [SCLSR] = sci_reg_invalid,
228 [HSSRR] = sci_reg_invalid,
229 },
230
231 /*
232 * Common SH-2(A) SCIF definitions for ports with FIFO data
233 * count registers.
234 */
235 [SCIx_SH2_SCIF_FIFODATA_REGTYPE] = {
236 [SCSMR] = { 0x00, 16 },
237 [SCBRR] = { 0x04, 8 },
238 [SCSCR] = { 0x08, 16 },
239 [SCxTDR] = { 0x0c, 8 },
240 [SCxSR] = { 0x10, 16 },
241 [SCxRDR] = { 0x14, 8 },
242 [SCFCR] = { 0x18, 16 },
243 [SCFDR] = { 0x1c, 16 },
244 [SCTFDR] = sci_reg_invalid,
245 [SCRFDR] = sci_reg_invalid,
246 [SCSPTR] = { 0x20, 16 },
247 [SCLSR] = { 0x24, 16 },
248 [HSSRR] = sci_reg_invalid,
249 },
250
251 /*
252 * Common SH-3 SCIF definitions.
253 */
254 [SCIx_SH3_SCIF_REGTYPE] = {
255 [SCSMR] = { 0x00, 8 },
256 [SCBRR] = { 0x02, 8 },
257 [SCSCR] = { 0x04, 8 },
258 [SCxTDR] = { 0x06, 8 },
259 [SCxSR] = { 0x08, 16 },
260 [SCxRDR] = { 0x0a, 8 },
261 [SCFCR] = { 0x0c, 8 },
262 [SCFDR] = { 0x0e, 16 },
263 [SCTFDR] = sci_reg_invalid,
264 [SCRFDR] = sci_reg_invalid,
265 [SCSPTR] = sci_reg_invalid,
266 [SCLSR] = sci_reg_invalid,
267 [HSSRR] = sci_reg_invalid,
268 },
269
270 /*
271 * Common SH-4(A) SCIF(B) definitions.
272 */
273 [SCIx_SH4_SCIF_REGTYPE] = {
274 [SCSMR] = { 0x00, 16 },
275 [SCBRR] = { 0x04, 8 },
276 [SCSCR] = { 0x08, 16 },
277 [SCxTDR] = { 0x0c, 8 },
278 [SCxSR] = { 0x10, 16 },
279 [SCxRDR] = { 0x14, 8 },
280 [SCFCR] = { 0x18, 16 },
281 [SCFDR] = { 0x1c, 16 },
282 [SCTFDR] = sci_reg_invalid,
283 [SCRFDR] = sci_reg_invalid,
284 [SCSPTR] = { 0x20, 16 },
285 [SCLSR] = { 0x24, 16 },
286 [HSSRR] = sci_reg_invalid,
287 },
288
289 /*
290 * Common HSCIF definitions.
291 */
292 [SCIx_HSCIF_REGTYPE] = {
293 [SCSMR] = { 0x00, 16 },
294 [SCBRR] = { 0x04, 8 },
295 [SCSCR] = { 0x08, 16 },
296 [SCxTDR] = { 0x0c, 8 },
297 [SCxSR] = { 0x10, 16 },
298 [SCxRDR] = { 0x14, 8 },
299 [SCFCR] = { 0x18, 16 },
300 [SCFDR] = { 0x1c, 16 },
301 [SCTFDR] = sci_reg_invalid,
302 [SCRFDR] = sci_reg_invalid,
303 [SCSPTR] = { 0x20, 16 },
304 [SCLSR] = { 0x24, 16 },
305 [HSSRR] = { 0x40, 16 },
306 },
307
308 /*
309 * Common SH-4(A) SCIF(B) definitions for ports without an SCSPTR
310 * register.
311 */
312 [SCIx_SH4_SCIF_NO_SCSPTR_REGTYPE] = {
313 [SCSMR] = { 0x00, 16 },
314 [SCBRR] = { 0x04, 8 },
315 [SCSCR] = { 0x08, 16 },
316 [SCxTDR] = { 0x0c, 8 },
317 [SCxSR] = { 0x10, 16 },
318 [SCxRDR] = { 0x14, 8 },
319 [SCFCR] = { 0x18, 16 },
320 [SCFDR] = { 0x1c, 16 },
321 [SCTFDR] = sci_reg_invalid,
322 [SCRFDR] = sci_reg_invalid,
323 [SCSPTR] = sci_reg_invalid,
324 [SCLSR] = { 0x24, 16 },
325 [HSSRR] = sci_reg_invalid,
326 },
327
328 /*
329 * Common SH-4(A) SCIF(B) definitions for ports with FIFO data
330 * count registers.
331 */
332 [SCIx_SH4_SCIF_FIFODATA_REGTYPE] = {
333 [SCSMR] = { 0x00, 16 },
334 [SCBRR] = { 0x04, 8 },
335 [SCSCR] = { 0x08, 16 },
336 [SCxTDR] = { 0x0c, 8 },
337 [SCxSR] = { 0x10, 16 },
338 [SCxRDR] = { 0x14, 8 },
339 [SCFCR] = { 0x18, 16 },
340 [SCFDR] = { 0x1c, 16 },
341 [SCTFDR] = { 0x1c, 16 }, /* aliased to SCFDR */
342 [SCRFDR] = { 0x20, 16 },
343 [SCSPTR] = { 0x24, 16 },
344 [SCLSR] = { 0x28, 16 },
345 [HSSRR] = sci_reg_invalid,
346 },
347
348 /*
349 * SH7705-style SCIF(B) ports, lacking both SCSPTR and SCLSR
350 * registers.
351 */
352 [SCIx_SH7705_SCIF_REGTYPE] = {
353 [SCSMR] = { 0x00, 16 },
354 [SCBRR] = { 0x04, 8 },
355 [SCSCR] = { 0x08, 16 },
356 [SCxTDR] = { 0x20, 8 },
357 [SCxSR] = { 0x14, 16 },
358 [SCxRDR] = { 0x24, 8 },
359 [SCFCR] = { 0x18, 16 },
360 [SCFDR] = { 0x1c, 16 },
361 [SCTFDR] = sci_reg_invalid,
362 [SCRFDR] = sci_reg_invalid,
363 [SCSPTR] = sci_reg_invalid,
364 [SCLSR] = sci_reg_invalid,
365 [HSSRR] = sci_reg_invalid,
366 },
367 };
368
369 #define sci_getreg(up, offset) (sci_regmap[to_sci_port(up)->cfg->regtype] + offset)
370
371 /*
372 * The "offset" here is rather misleading, in that it refers to an enum
373 * value relative to the port mapping rather than the fixed offset
374 * itself, which needs to be manually retrieved from the platform's
375 * register map for the given port.
376 */
377 static unsigned int sci_serial_in(struct uart_port *p, int offset)
378 {
379 struct plat_sci_reg *reg = sci_getreg(p, offset);
380
381 if (reg->size == 8)
382 return ioread8(p->membase + (reg->offset << p->regshift));
383 else if (reg->size == 16)
384 return ioread16(p->membase + (reg->offset << p->regshift));
385 else
386 WARN(1, "Invalid register access\n");
387
388 return 0;
389 }
390
391 static void sci_serial_out(struct uart_port *p, int offset, int value)
392 {
393 struct plat_sci_reg *reg = sci_getreg(p, offset);
394
395 if (reg->size == 8)
396 iowrite8(value, p->membase + (reg->offset << p->regshift));
397 else if (reg->size == 16)
398 iowrite16(value, p->membase + (reg->offset << p->regshift));
399 else
400 WARN(1, "Invalid register access\n");
401 }
402
403 static int sci_probe_regmap(struct plat_sci_port *cfg)
404 {
405 switch (cfg->type) {
406 case PORT_SCI:
407 cfg->regtype = SCIx_SCI_REGTYPE;
408 break;
409 case PORT_IRDA:
410 cfg->regtype = SCIx_IRDA_REGTYPE;
411 break;
412 case PORT_SCIFA:
413 cfg->regtype = SCIx_SCIFA_REGTYPE;
414 break;
415 case PORT_SCIFB:
416 cfg->regtype = SCIx_SCIFB_REGTYPE;
417 break;
418 case PORT_SCIF:
419 /*
420 * The SH-4 is a bit of a misnomer here, although that's
421 * where this particular port layout originated. This
422 * configuration (or some slight variation thereof)
423 * remains the dominant model for all SCIFs.
424 */
425 cfg->regtype = SCIx_SH4_SCIF_REGTYPE;
426 break;
427 case PORT_HSCIF:
428 cfg->regtype = SCIx_HSCIF_REGTYPE;
429 break;
430 default:
431 pr_err("Can't probe register map for given port\n");
432 return -EINVAL;
433 }
434
435 return 0;
436 }
437
438 static void sci_port_enable(struct sci_port *sci_port)
439 {
440 if (!sci_port->port.dev)
441 return;
442
443 pm_runtime_get_sync(sci_port->port.dev);
444
445 clk_prepare_enable(sci_port->iclk);
446 sci_port->port.uartclk = clk_get_rate(sci_port->iclk);
447 clk_prepare_enable(sci_port->fclk);
448 }
449
450 static void sci_port_disable(struct sci_port *sci_port)
451 {
452 if (!sci_port->port.dev)
453 return;
454
455 /* Cancel the break timer to ensure that the timer handler will not try
456 * to access the hardware with clocks and power disabled. Reset the
457 * break flag to make the break debouncing state machine ready for the
458 * next break.
459 */
460 del_timer_sync(&sci_port->break_timer);
461 sci_port->break_flag = 0;
462
463 clk_disable_unprepare(sci_port->fclk);
464 clk_disable_unprepare(sci_port->iclk);
465
466 pm_runtime_put_sync(sci_port->port.dev);
467 }
468
469 #if defined(CONFIG_CONSOLE_POLL) || defined(CONFIG_SERIAL_SH_SCI_CONSOLE)
470
471 #ifdef CONFIG_CONSOLE_POLL
472 static int sci_poll_get_char(struct uart_port *port)
473 {
474 unsigned short status;
475 int c;
476
477 do {
478 status = serial_port_in(port, SCxSR);
479 if (status & SCxSR_ERRORS(port)) {
480 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
481 continue;
482 }
483 break;
484 } while (1);
485
486 if (!(status & SCxSR_RDxF(port)))
487 return NO_POLL_CHAR;
488
489 c = serial_port_in(port, SCxRDR);
490
491 /* Dummy read */
492 serial_port_in(port, SCxSR);
493 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
494
495 return c;
496 }
497 #endif
498
499 static void sci_poll_put_char(struct uart_port *port, unsigned char c)
500 {
501 unsigned short status;
502
503 do {
504 status = serial_port_in(port, SCxSR);
505 } while (!(status & SCxSR_TDxE(port)));
506
507 serial_port_out(port, SCxTDR, c);
508 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port) & ~SCxSR_TEND(port));
509 }
510 #endif /* CONFIG_CONSOLE_POLL || CONFIG_SERIAL_SH_SCI_CONSOLE */
511
512 static void sci_init_pins(struct uart_port *port, unsigned int cflag)
513 {
514 struct sci_port *s = to_sci_port(port);
515 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
516
517 /*
518 * Use port-specific handler if provided.
519 */
520 if (s->cfg->ops && s->cfg->ops->init_pins) {
521 s->cfg->ops->init_pins(port, cflag);
522 return;
523 }
524
525 /*
526 * For the generic path SCSPTR is necessary. Bail out if that's
527 * unavailable, too.
528 */
529 if (!reg->size)
530 return;
531
532 if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
533 ((!(cflag & CRTSCTS)))) {
534 unsigned short status;
535
536 status = serial_port_in(port, SCSPTR);
537 status &= ~SCSPTR_CTSIO;
538 status |= SCSPTR_RTSIO;
539 serial_port_out(port, SCSPTR, status); /* Set RTS = 1 */
540 }
541 }
542
543 static int sci_txfill(struct uart_port *port)
544 {
545 struct plat_sci_reg *reg;
546
547 reg = sci_getreg(port, SCTFDR);
548 if (reg->size)
549 return serial_port_in(port, SCTFDR) & ((port->fifosize << 1) - 1);
550
551 reg = sci_getreg(port, SCFDR);
552 if (reg->size)
553 return serial_port_in(port, SCFDR) >> 8;
554
555 return !(serial_port_in(port, SCxSR) & SCI_TDRE);
556 }
557
558 static int sci_txroom(struct uart_port *port)
559 {
560 return port->fifosize - sci_txfill(port);
561 }
562
563 static int sci_rxfill(struct uart_port *port)
564 {
565 struct plat_sci_reg *reg;
566
567 reg = sci_getreg(port, SCRFDR);
568 if (reg->size)
569 return serial_port_in(port, SCRFDR) & ((port->fifosize << 1) - 1);
570
571 reg = sci_getreg(port, SCFDR);
572 if (reg->size)
573 return serial_port_in(port, SCFDR) & ((port->fifosize << 1) - 1);
574
575 return (serial_port_in(port, SCxSR) & SCxSR_RDxF(port)) != 0;
576 }
577
578 /*
579 * SCI helper for checking the state of the muxed port/RXD pins.
580 */
581 static inline int sci_rxd_in(struct uart_port *port)
582 {
583 struct sci_port *s = to_sci_port(port);
584
585 if (s->cfg->port_reg <= 0)
586 return 1;
587
588 /* Cast for ARM damage */
589 return !!__raw_readb((void __iomem *)(uintptr_t)s->cfg->port_reg);
590 }
591
592 /* ********************************************************************** *
593 * the interrupt related routines *
594 * ********************************************************************** */
595
596 static void sci_transmit_chars(struct uart_port *port)
597 {
598 struct circ_buf *xmit = &port->state->xmit;
599 unsigned int stopped = uart_tx_stopped(port);
600 unsigned short status;
601 unsigned short ctrl;
602 int count;
603
604 status = serial_port_in(port, SCxSR);
605 if (!(status & SCxSR_TDxE(port))) {
606 ctrl = serial_port_in(port, SCSCR);
607 if (uart_circ_empty(xmit))
608 ctrl &= ~SCSCR_TIE;
609 else
610 ctrl |= SCSCR_TIE;
611 serial_port_out(port, SCSCR, ctrl);
612 return;
613 }
614
615 count = sci_txroom(port);
616
617 do {
618 unsigned char c;
619
620 if (port->x_char) {
621 c = port->x_char;
622 port->x_char = 0;
623 } else if (!uart_circ_empty(xmit) && !stopped) {
624 c = xmit->buf[xmit->tail];
625 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
626 } else {
627 break;
628 }
629
630 serial_port_out(port, SCxTDR, c);
631
632 port->icount.tx++;
633 } while (--count > 0);
634
635 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
636
637 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
638 uart_write_wakeup(port);
639 if (uart_circ_empty(xmit)) {
640 sci_stop_tx(port);
641 } else {
642 ctrl = serial_port_in(port, SCSCR);
643
644 if (port->type != PORT_SCI) {
645 serial_port_in(port, SCxSR); /* Dummy read */
646 serial_port_out(port, SCxSR, SCxSR_TDxE_CLEAR(port));
647 }
648
649 ctrl |= SCSCR_TIE;
650 serial_port_out(port, SCSCR, ctrl);
651 }
652 }
653
654 /* On SH3, SCIF may read end-of-break as a space->mark char */
655 #define STEPFN(c) ({int __c = (c); (((__c-1)|(__c)) == -1); })
656
657 static void sci_receive_chars(struct uart_port *port)
658 {
659 struct sci_port *sci_port = to_sci_port(port);
660 struct tty_port *tport = &port->state->port;
661 int i, count, copied = 0;
662 unsigned short status;
663 unsigned char flag;
664
665 status = serial_port_in(port, SCxSR);
666 if (!(status & SCxSR_RDxF(port)))
667 return;
668
669 while (1) {
670 /* Don't copy more bytes than there is room for in the buffer */
671 count = tty_buffer_request_room(tport, sci_rxfill(port));
672
673 /* If for any reason we can't copy more data, we're done! */
674 if (count == 0)
675 break;
676
677 if (port->type == PORT_SCI) {
678 char c = serial_port_in(port, SCxRDR);
679 if (uart_handle_sysrq_char(port, c) ||
680 sci_port->break_flag)
681 count = 0;
682 else
683 tty_insert_flip_char(tport, c, TTY_NORMAL);
684 } else {
685 for (i = 0; i < count; i++) {
686 char c = serial_port_in(port, SCxRDR);
687
688 status = serial_port_in(port, SCxSR);
689 #if defined(CONFIG_CPU_SH3)
690 /* Skip "chars" during break */
691 if (sci_port->break_flag) {
692 if ((c == 0) &&
693 (status & SCxSR_FER(port))) {
694 count--; i--;
695 continue;
696 }
697
698 /* Nonzero => end-of-break */
699 dev_dbg(port->dev, "debounce<%02x>\n", c);
700 sci_port->break_flag = 0;
701
702 if (STEPFN(c)) {
703 count--; i--;
704 continue;
705 }
706 }
707 #endif /* CONFIG_CPU_SH3 */
708 if (uart_handle_sysrq_char(port, c)) {
709 count--; i--;
710 continue;
711 }
712
713 /* Store data and status */
714 if (status & SCxSR_FER(port)) {
715 flag = TTY_FRAME;
716 port->icount.frame++;
717 dev_notice(port->dev, "frame error\n");
718 } else if (status & SCxSR_PER(port)) {
719 flag = TTY_PARITY;
720 port->icount.parity++;
721 dev_notice(port->dev, "parity error\n");
722 } else
723 flag = TTY_NORMAL;
724
725 tty_insert_flip_char(tport, c, flag);
726 }
727 }
728
729 serial_port_in(port, SCxSR); /* dummy read */
730 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
731
732 copied += count;
733 port->icount.rx += count;
734 }
735
736 if (copied) {
737 /* Tell the rest of the system the news. New characters! */
738 tty_flip_buffer_push(tport);
739 } else {
740 serial_port_in(port, SCxSR); /* dummy read */
741 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
742 }
743 }
744
745 #define SCI_BREAK_JIFFIES (HZ/20)
746
747 /*
748 * The sci generates interrupts during the break,
749 * 1 per millisecond or so during the break period, for 9600 baud.
750 * So dont bother disabling interrupts.
751 * But dont want more than 1 break event.
752 * Use a kernel timer to periodically poll the rx line until
753 * the break is finished.
754 */
755 static inline void sci_schedule_break_timer(struct sci_port *port)
756 {
757 mod_timer(&port->break_timer, jiffies + SCI_BREAK_JIFFIES);
758 }
759
760 /* Ensure that two consecutive samples find the break over. */
761 static void sci_break_timer(unsigned long data)
762 {
763 struct sci_port *port = (struct sci_port *)data;
764
765 if (sci_rxd_in(&port->port) == 0) {
766 port->break_flag = 1;
767 sci_schedule_break_timer(port);
768 } else if (port->break_flag == 1) {
769 /* break is over. */
770 port->break_flag = 2;
771 sci_schedule_break_timer(port);
772 } else
773 port->break_flag = 0;
774 }
775
776 static int sci_handle_errors(struct uart_port *port)
777 {
778 int copied = 0;
779 unsigned short status = serial_port_in(port, SCxSR);
780 struct tty_port *tport = &port->state->port;
781 struct sci_port *s = to_sci_port(port);
782
783 /* Handle overruns */
784 if (status & (1 << s->overrun_bit)) {
785 port->icount.overrun++;
786
787 /* overrun error */
788 if (tty_insert_flip_char(tport, 0, TTY_OVERRUN))
789 copied++;
790
791 dev_notice(port->dev, "overrun error\n");
792 }
793
794 if (status & SCxSR_FER(port)) {
795 if (sci_rxd_in(port) == 0) {
796 /* Notify of BREAK */
797 struct sci_port *sci_port = to_sci_port(port);
798
799 if (!sci_port->break_flag) {
800 port->icount.brk++;
801
802 sci_port->break_flag = 1;
803 sci_schedule_break_timer(sci_port);
804
805 /* Do sysrq handling. */
806 if (uart_handle_break(port))
807 return 0;
808
809 dev_dbg(port->dev, "BREAK detected\n");
810
811 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
812 copied++;
813 }
814
815 } else {
816 /* frame error */
817 port->icount.frame++;
818
819 if (tty_insert_flip_char(tport, 0, TTY_FRAME))
820 copied++;
821
822 dev_notice(port->dev, "frame error\n");
823 }
824 }
825
826 if (status & SCxSR_PER(port)) {
827 /* parity error */
828 port->icount.parity++;
829
830 if (tty_insert_flip_char(tport, 0, TTY_PARITY))
831 copied++;
832
833 dev_notice(port->dev, "parity error\n");
834 }
835
836 if (copied)
837 tty_flip_buffer_push(tport);
838
839 return copied;
840 }
841
842 static int sci_handle_fifo_overrun(struct uart_port *port)
843 {
844 struct tty_port *tport = &port->state->port;
845 struct sci_port *s = to_sci_port(port);
846 struct plat_sci_reg *reg;
847 int copied = 0;
848
849 reg = sci_getreg(port, SCLSR);
850 if (!reg->size)
851 return 0;
852
853 if ((serial_port_in(port, SCLSR) & (1 << s->overrun_bit))) {
854 serial_port_out(port, SCLSR, 0);
855
856 port->icount.overrun++;
857
858 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
859 tty_flip_buffer_push(tport);
860
861 dev_notice(port->dev, "overrun error\n");
862 copied++;
863 }
864
865 return copied;
866 }
867
868 static int sci_handle_breaks(struct uart_port *port)
869 {
870 int copied = 0;
871 unsigned short status = serial_port_in(port, SCxSR);
872 struct tty_port *tport = &port->state->port;
873 struct sci_port *s = to_sci_port(port);
874
875 if (uart_handle_break(port))
876 return 0;
877
878 if (!s->break_flag && status & SCxSR_BRK(port)) {
879 #if defined(CONFIG_CPU_SH3)
880 /* Debounce break */
881 s->break_flag = 1;
882 #endif
883
884 port->icount.brk++;
885
886 /* Notify of BREAK */
887 if (tty_insert_flip_char(tport, 0, TTY_BREAK))
888 copied++;
889
890 dev_dbg(port->dev, "BREAK detected\n");
891 }
892
893 if (copied)
894 tty_flip_buffer_push(tport);
895
896 copied += sci_handle_fifo_overrun(port);
897
898 return copied;
899 }
900
901 static irqreturn_t sci_rx_interrupt(int irq, void *ptr)
902 {
903 #ifdef CONFIG_SERIAL_SH_SCI_DMA
904 struct uart_port *port = ptr;
905 struct sci_port *s = to_sci_port(port);
906
907 if (s->chan_rx) {
908 u16 scr = serial_port_in(port, SCSCR);
909 u16 ssr = serial_port_in(port, SCxSR);
910
911 /* Disable future Rx interrupts */
912 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
913 disable_irq_nosync(irq);
914 scr |= SCSCR_RDRQE;
915 } else {
916 scr &= ~SCSCR_RIE;
917 }
918 serial_port_out(port, SCSCR, scr);
919 /* Clear current interrupt */
920 serial_port_out(port, SCxSR, ssr & ~(1 | SCxSR_RDxF(port)));
921 dev_dbg(port->dev, "Rx IRQ %lu: setup t-out in %u jiffies\n",
922 jiffies, s->rx_timeout);
923 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
924
925 return IRQ_HANDLED;
926 }
927 #endif
928
929 /* I think sci_receive_chars has to be called irrespective
930 * of whether the I_IXOFF is set, otherwise, how is the interrupt
931 * to be disabled?
932 */
933 sci_receive_chars(ptr);
934
935 return IRQ_HANDLED;
936 }
937
938 static irqreturn_t sci_tx_interrupt(int irq, void *ptr)
939 {
940 struct uart_port *port = ptr;
941 unsigned long flags;
942
943 spin_lock_irqsave(&port->lock, flags);
944 sci_transmit_chars(port);
945 spin_unlock_irqrestore(&port->lock, flags);
946
947 return IRQ_HANDLED;
948 }
949
950 static irqreturn_t sci_er_interrupt(int irq, void *ptr)
951 {
952 struct uart_port *port = ptr;
953
954 /* Handle errors */
955 if (port->type == PORT_SCI) {
956 if (sci_handle_errors(port)) {
957 /* discard character in rx buffer */
958 serial_port_in(port, SCxSR);
959 serial_port_out(port, SCxSR, SCxSR_RDxF_CLEAR(port));
960 }
961 } else {
962 sci_handle_fifo_overrun(port);
963 sci_rx_interrupt(irq, ptr);
964 }
965
966 serial_port_out(port, SCxSR, SCxSR_ERROR_CLEAR(port));
967
968 /* Kick the transmission */
969 sci_tx_interrupt(irq, ptr);
970
971 return IRQ_HANDLED;
972 }
973
974 static irqreturn_t sci_br_interrupt(int irq, void *ptr)
975 {
976 struct uart_port *port = ptr;
977
978 /* Handle BREAKs */
979 sci_handle_breaks(port);
980 serial_port_out(port, SCxSR, SCxSR_BREAK_CLEAR(port));
981
982 return IRQ_HANDLED;
983 }
984
985 static inline unsigned long port_rx_irq_mask(struct uart_port *port)
986 {
987 /*
988 * Not all ports (such as SCIFA) will support REIE. Rather than
989 * special-casing the port type, we check the port initialization
990 * IRQ enable mask to see whether the IRQ is desired at all. If
991 * it's unset, it's logically inferred that there's no point in
992 * testing for it.
993 */
994 return SCSCR_RIE | (to_sci_port(port)->cfg->scscr & SCSCR_REIE);
995 }
996
997 static irqreturn_t sci_mpxed_interrupt(int irq, void *ptr)
998 {
999 unsigned short ssr_status, scr_status, err_enabled;
1000 struct uart_port *port = ptr;
1001 struct sci_port *s = to_sci_port(port);
1002 irqreturn_t ret = IRQ_NONE;
1003
1004 ssr_status = serial_port_in(port, SCxSR);
1005 scr_status = serial_port_in(port, SCSCR);
1006 err_enabled = scr_status & port_rx_irq_mask(port);
1007
1008 /* Tx Interrupt */
1009 if ((ssr_status & SCxSR_TDxE(port)) && (scr_status & SCSCR_TIE) &&
1010 !s->chan_tx)
1011 ret = sci_tx_interrupt(irq, ptr);
1012
1013 /*
1014 * Rx Interrupt: if we're using DMA, the DMA controller clears RDF /
1015 * DR flags
1016 */
1017 if (((ssr_status & SCxSR_RDxF(port)) || s->chan_rx) &&
1018 (scr_status & SCSCR_RIE))
1019 ret = sci_rx_interrupt(irq, ptr);
1020
1021 /* Error Interrupt */
1022 if ((ssr_status & SCxSR_ERRORS(port)) && err_enabled)
1023 ret = sci_er_interrupt(irq, ptr);
1024
1025 /* Break Interrupt */
1026 if ((ssr_status & SCxSR_BRK(port)) && err_enabled)
1027 ret = sci_br_interrupt(irq, ptr);
1028
1029 return ret;
1030 }
1031
1032 /*
1033 * Here we define a transition notifier so that we can update all of our
1034 * ports' baud rate when the peripheral clock changes.
1035 */
1036 static int sci_notifier(struct notifier_block *self,
1037 unsigned long phase, void *p)
1038 {
1039 struct sci_port *sci_port;
1040 unsigned long flags;
1041
1042 sci_port = container_of(self, struct sci_port, freq_transition);
1043
1044 if (phase == CPUFREQ_POSTCHANGE) {
1045 struct uart_port *port = &sci_port->port;
1046
1047 spin_lock_irqsave(&port->lock, flags);
1048 port->uartclk = clk_get_rate(sci_port->iclk);
1049 spin_unlock_irqrestore(&port->lock, flags);
1050 }
1051
1052 return NOTIFY_OK;
1053 }
1054
1055 static struct sci_irq_desc {
1056 const char *desc;
1057 irq_handler_t handler;
1058 } sci_irq_desc[] = {
1059 /*
1060 * Split out handlers, the default case.
1061 */
1062 [SCIx_ERI_IRQ] = {
1063 .desc = "rx err",
1064 .handler = sci_er_interrupt,
1065 },
1066
1067 [SCIx_RXI_IRQ] = {
1068 .desc = "rx full",
1069 .handler = sci_rx_interrupt,
1070 },
1071
1072 [SCIx_TXI_IRQ] = {
1073 .desc = "tx empty",
1074 .handler = sci_tx_interrupt,
1075 },
1076
1077 [SCIx_BRI_IRQ] = {
1078 .desc = "break",
1079 .handler = sci_br_interrupt,
1080 },
1081
1082 /*
1083 * Special muxed handler.
1084 */
1085 [SCIx_MUX_IRQ] = {
1086 .desc = "mux",
1087 .handler = sci_mpxed_interrupt,
1088 },
1089 };
1090
1091 static int sci_request_irq(struct sci_port *port)
1092 {
1093 struct uart_port *up = &port->port;
1094 int i, j, ret = 0;
1095
1096 for (i = j = 0; i < SCIx_NR_IRQS; i++, j++) {
1097 struct sci_irq_desc *desc;
1098 int irq;
1099
1100 if (SCIx_IRQ_IS_MUXED(port)) {
1101 i = SCIx_MUX_IRQ;
1102 irq = up->irq;
1103 } else {
1104 irq = port->irqs[i];
1105
1106 /*
1107 * Certain port types won't support all of the
1108 * available interrupt sources.
1109 */
1110 if (unlikely(irq < 0))
1111 continue;
1112 }
1113
1114 desc = sci_irq_desc + i;
1115 port->irqstr[j] = kasprintf(GFP_KERNEL, "%s:%s",
1116 dev_name(up->dev), desc->desc);
1117 if (!port->irqstr[j]) {
1118 dev_err(up->dev, "Failed to allocate %s IRQ string\n",
1119 desc->desc);
1120 goto out_nomem;
1121 }
1122
1123 ret = request_irq(irq, desc->handler, up->irqflags,
1124 port->irqstr[j], port);
1125 if (unlikely(ret)) {
1126 dev_err(up->dev, "Can't allocate %s IRQ\n", desc->desc);
1127 goto out_noirq;
1128 }
1129 }
1130
1131 return 0;
1132
1133 out_noirq:
1134 while (--i >= 0)
1135 free_irq(port->irqs[i], port);
1136
1137 out_nomem:
1138 while (--j >= 0)
1139 kfree(port->irqstr[j]);
1140
1141 return ret;
1142 }
1143
1144 static void sci_free_irq(struct sci_port *port)
1145 {
1146 int i;
1147
1148 /*
1149 * Intentionally in reverse order so we iterate over the muxed
1150 * IRQ first.
1151 */
1152 for (i = 0; i < SCIx_NR_IRQS; i++) {
1153 int irq = port->irqs[i];
1154
1155 /*
1156 * Certain port types won't support all of the available
1157 * interrupt sources.
1158 */
1159 if (unlikely(irq < 0))
1160 continue;
1161
1162 free_irq(port->irqs[i], port);
1163 kfree(port->irqstr[i]);
1164
1165 if (SCIx_IRQ_IS_MUXED(port)) {
1166 /* If there's only one IRQ, we're done. */
1167 return;
1168 }
1169 }
1170 }
1171
1172 static unsigned int sci_tx_empty(struct uart_port *port)
1173 {
1174 unsigned short status = serial_port_in(port, SCxSR);
1175 unsigned short in_tx_fifo = sci_txfill(port);
1176
1177 return (status & SCxSR_TEND(port)) && !in_tx_fifo ? TIOCSER_TEMT : 0;
1178 }
1179
1180 /*
1181 * Modem control is a bit of a mixed bag for SCI(F) ports. Generally
1182 * CTS/RTS is supported in hardware by at least one port and controlled
1183 * via SCSPTR (SCxPCR for SCIFA/B parts), or external pins (presently
1184 * handled via the ->init_pins() op, which is a bit of a one-way street,
1185 * lacking any ability to defer pin control -- this will later be
1186 * converted over to the GPIO framework).
1187 *
1188 * Other modes (such as loopback) are supported generically on certain
1189 * port types, but not others. For these it's sufficient to test for the
1190 * existence of the support register and simply ignore the port type.
1191 */
1192 static void sci_set_mctrl(struct uart_port *port, unsigned int mctrl)
1193 {
1194 if (mctrl & TIOCM_LOOP) {
1195 struct plat_sci_reg *reg;
1196
1197 /*
1198 * Standard loopback mode for SCFCR ports.
1199 */
1200 reg = sci_getreg(port, SCFCR);
1201 if (reg->size)
1202 serial_port_out(port, SCFCR,
1203 serial_port_in(port, SCFCR) |
1204 SCFCR_LOOP);
1205 }
1206 }
1207
1208 static unsigned int sci_get_mctrl(struct uart_port *port)
1209 {
1210 /*
1211 * CTS/RTS is handled in hardware when supported, while nothing
1212 * else is wired up. Keep it simple and simply assert DSR/CAR.
1213 */
1214 return TIOCM_DSR | TIOCM_CAR;
1215 }
1216
1217 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1218 static void sci_dma_tx_complete(void *arg)
1219 {
1220 struct sci_port *s = arg;
1221 struct uart_port *port = &s->port;
1222 struct circ_buf *xmit = &port->state->xmit;
1223 unsigned long flags;
1224
1225 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1226
1227 spin_lock_irqsave(&port->lock, flags);
1228
1229 xmit->tail += sg_dma_len(&s->sg_tx);
1230 xmit->tail &= UART_XMIT_SIZE - 1;
1231
1232 port->icount.tx += sg_dma_len(&s->sg_tx);
1233
1234 async_tx_ack(s->desc_tx);
1235 s->desc_tx = NULL;
1236
1237 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
1238 uart_write_wakeup(port);
1239
1240 if (!uart_circ_empty(xmit)) {
1241 s->cookie_tx = 0;
1242 schedule_work(&s->work_tx);
1243 } else {
1244 s->cookie_tx = -EINVAL;
1245 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1246 u16 ctrl = serial_port_in(port, SCSCR);
1247 serial_port_out(port, SCSCR, ctrl & ~SCSCR_TIE);
1248 }
1249 }
1250
1251 spin_unlock_irqrestore(&port->lock, flags);
1252 }
1253
1254 /* Locking: called with port lock held */
1255 static int sci_dma_rx_push(struct sci_port *s, size_t count)
1256 {
1257 struct uart_port *port = &s->port;
1258 struct tty_port *tport = &port->state->port;
1259 int i, active, room;
1260
1261 room = tty_buffer_request_room(tport, count);
1262
1263 if (s->active_rx == s->cookie_rx[0]) {
1264 active = 0;
1265 } else if (s->active_rx == s->cookie_rx[1]) {
1266 active = 1;
1267 } else {
1268 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1269 return 0;
1270 }
1271
1272 if (room < count)
1273 dev_warn(port->dev, "Rx overrun: dropping %zu bytes\n",
1274 count - room);
1275 if (!room)
1276 return room;
1277
1278 for (i = 0; i < room; i++)
1279 tty_insert_flip_char(tport, ((u8 *)sg_virt(&s->sg_rx[active]))[i],
1280 TTY_NORMAL);
1281
1282 port->icount.rx += room;
1283
1284 return room;
1285 }
1286
1287 static void sci_dma_rx_complete(void *arg)
1288 {
1289 struct sci_port *s = arg;
1290 struct uart_port *port = &s->port;
1291 unsigned long flags;
1292 int count;
1293
1294 dev_dbg(port->dev, "%s(%d) active #%d\n",
1295 __func__, port->line, s->active_rx);
1296
1297 spin_lock_irqsave(&port->lock, flags);
1298
1299 count = sci_dma_rx_push(s, s->buf_len_rx);
1300
1301 mod_timer(&s->rx_timer, jiffies + s->rx_timeout);
1302
1303 spin_unlock_irqrestore(&port->lock, flags);
1304
1305 if (count)
1306 tty_flip_buffer_push(&port->state->port);
1307
1308 schedule_work(&s->work_rx);
1309 }
1310
1311 static void sci_rx_dma_release(struct sci_port *s, bool enable_pio)
1312 {
1313 struct dma_chan *chan = s->chan_rx;
1314 struct uart_port *port = &s->port;
1315
1316 s->chan_rx = NULL;
1317 s->cookie_rx[0] = s->cookie_rx[1] = -EINVAL;
1318 dma_release_channel(chan);
1319 if (sg_dma_address(&s->sg_rx[0]))
1320 dma_free_coherent(port->dev, s->buf_len_rx * 2,
1321 sg_virt(&s->sg_rx[0]), sg_dma_address(&s->sg_rx[0]));
1322 if (enable_pio)
1323 sci_start_rx(port);
1324 }
1325
1326 static void sci_tx_dma_release(struct sci_port *s, bool enable_pio)
1327 {
1328 struct dma_chan *chan = s->chan_tx;
1329 struct uart_port *port = &s->port;
1330
1331 s->chan_tx = NULL;
1332 s->cookie_tx = -EINVAL;
1333 dma_release_channel(chan);
1334 if (enable_pio)
1335 sci_start_tx(port);
1336 }
1337
1338 static void sci_submit_rx(struct sci_port *s)
1339 {
1340 struct dma_chan *chan = s->chan_rx;
1341 int i;
1342
1343 for (i = 0; i < 2; i++) {
1344 struct scatterlist *sg = &s->sg_rx[i];
1345 struct dma_async_tx_descriptor *desc;
1346
1347 desc = dmaengine_prep_slave_sg(chan,
1348 sg, 1, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1349
1350 if (desc) {
1351 s->desc_rx[i] = desc;
1352 desc->callback = sci_dma_rx_complete;
1353 desc->callback_param = s;
1354 s->cookie_rx[i] = desc->tx_submit(desc);
1355 }
1356
1357 if (!desc || s->cookie_rx[i] < 0) {
1358 if (i) {
1359 async_tx_ack(s->desc_rx[0]);
1360 s->cookie_rx[0] = -EINVAL;
1361 }
1362 if (desc) {
1363 async_tx_ack(desc);
1364 s->cookie_rx[i] = -EINVAL;
1365 }
1366 dev_warn(s->port.dev,
1367 "failed to re-start DMA, using PIO\n");
1368 sci_rx_dma_release(s, true);
1369 return;
1370 }
1371 dev_dbg(s->port.dev, "%s(): cookie %d to #%d\n",
1372 __func__, s->cookie_rx[i], i);
1373 }
1374
1375 s->active_rx = s->cookie_rx[0];
1376
1377 dma_async_issue_pending(chan);
1378 }
1379
1380 static void work_fn_rx(struct work_struct *work)
1381 {
1382 struct sci_port *s = container_of(work, struct sci_port, work_rx);
1383 struct uart_port *port = &s->port;
1384 struct dma_async_tx_descriptor *desc;
1385 int new;
1386
1387 if (s->active_rx == s->cookie_rx[0]) {
1388 new = 0;
1389 } else if (s->active_rx == s->cookie_rx[1]) {
1390 new = 1;
1391 } else {
1392 dev_err(port->dev, "cookie %d not found!\n", s->active_rx);
1393 return;
1394 }
1395 desc = s->desc_rx[new];
1396
1397 if (dma_async_is_tx_complete(s->chan_rx, s->active_rx, NULL, NULL) !=
1398 DMA_COMPLETE) {
1399 /* Handle incomplete DMA receive */
1400 struct dma_chan *chan = s->chan_rx;
1401 struct shdma_desc *sh_desc = container_of(desc,
1402 struct shdma_desc, async_tx);
1403 unsigned long flags;
1404 int count;
1405
1406 chan->device->device_control(chan, DMA_TERMINATE_ALL, 0);
1407 dev_dbg(port->dev, "Read %zu bytes with cookie %d\n",
1408 sh_desc->partial, sh_desc->cookie);
1409
1410 spin_lock_irqsave(&port->lock, flags);
1411 count = sci_dma_rx_push(s, sh_desc->partial);
1412 spin_unlock_irqrestore(&port->lock, flags);
1413
1414 if (count)
1415 tty_flip_buffer_push(&port->state->port);
1416
1417 sci_submit_rx(s);
1418
1419 return;
1420 }
1421
1422 s->cookie_rx[new] = desc->tx_submit(desc);
1423 if (s->cookie_rx[new] < 0) {
1424 dev_warn(port->dev, "Failed submitting Rx DMA descriptor\n");
1425 sci_rx_dma_release(s, true);
1426 return;
1427 }
1428
1429 s->active_rx = s->cookie_rx[!new];
1430
1431 dev_dbg(port->dev, "%s: cookie %d #%d, new active #%d\n",
1432 __func__, s->cookie_rx[new], new, s->active_rx);
1433 }
1434
1435 static void work_fn_tx(struct work_struct *work)
1436 {
1437 struct sci_port *s = container_of(work, struct sci_port, work_tx);
1438 struct dma_async_tx_descriptor *desc;
1439 struct dma_chan *chan = s->chan_tx;
1440 struct uart_port *port = &s->port;
1441 struct circ_buf *xmit = &port->state->xmit;
1442 struct scatterlist *sg = &s->sg_tx;
1443
1444 /*
1445 * DMA is idle now.
1446 * Port xmit buffer is already mapped, and it is one page... Just adjust
1447 * offsets and lengths. Since it is a circular buffer, we have to
1448 * transmit till the end, and then the rest. Take the port lock to get a
1449 * consistent xmit buffer state.
1450 */
1451 spin_lock_irq(&port->lock);
1452 sg->offset = xmit->tail & (UART_XMIT_SIZE - 1);
1453 sg_dma_address(sg) = (sg_dma_address(sg) & ~(UART_XMIT_SIZE - 1)) +
1454 sg->offset;
1455 sg_dma_len(sg) = min((int)CIRC_CNT(xmit->head, xmit->tail, UART_XMIT_SIZE),
1456 CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE));
1457 spin_unlock_irq(&port->lock);
1458
1459 BUG_ON(!sg_dma_len(sg));
1460
1461 desc = dmaengine_prep_slave_sg(chan,
1462 sg, s->sg_len_tx, DMA_MEM_TO_DEV,
1463 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
1464 if (!desc) {
1465 /* switch to PIO */
1466 sci_tx_dma_release(s, true);
1467 return;
1468 }
1469
1470 dma_sync_sg_for_device(port->dev, sg, 1, DMA_TO_DEVICE);
1471
1472 spin_lock_irq(&port->lock);
1473 s->desc_tx = desc;
1474 desc->callback = sci_dma_tx_complete;
1475 desc->callback_param = s;
1476 spin_unlock_irq(&port->lock);
1477 s->cookie_tx = desc->tx_submit(desc);
1478 if (s->cookie_tx < 0) {
1479 dev_warn(port->dev, "Failed submitting Tx DMA descriptor\n");
1480 /* switch to PIO */
1481 sci_tx_dma_release(s, true);
1482 return;
1483 }
1484
1485 dev_dbg(port->dev, "%s: %p: %d...%d, cookie %d\n",
1486 __func__, xmit->buf, xmit->tail, xmit->head, s->cookie_tx);
1487
1488 dma_async_issue_pending(chan);
1489 }
1490 #endif
1491
1492 static void sci_start_tx(struct uart_port *port)
1493 {
1494 struct sci_port *s = to_sci_port(port);
1495 unsigned short ctrl;
1496
1497 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1498 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1499 u16 new, scr = serial_port_in(port, SCSCR);
1500 if (s->chan_tx)
1501 new = scr | SCSCR_TDRQE;
1502 else
1503 new = scr & ~SCSCR_TDRQE;
1504 if (new != scr)
1505 serial_port_out(port, SCSCR, new);
1506 }
1507
1508 if (s->chan_tx && !uart_circ_empty(&s->port.state->xmit) &&
1509 s->cookie_tx < 0) {
1510 s->cookie_tx = 0;
1511 schedule_work(&s->work_tx);
1512 }
1513 #endif
1514
1515 if (!s->chan_tx || port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1516 /* Set TIE (Transmit Interrupt Enable) bit in SCSCR */
1517 ctrl = serial_port_in(port, SCSCR);
1518 serial_port_out(port, SCSCR, ctrl | SCSCR_TIE);
1519 }
1520 }
1521
1522 static void sci_stop_tx(struct uart_port *port)
1523 {
1524 unsigned short ctrl;
1525
1526 /* Clear TIE (Transmit Interrupt Enable) bit in SCSCR */
1527 ctrl = serial_port_in(port, SCSCR);
1528
1529 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1530 ctrl &= ~SCSCR_TDRQE;
1531
1532 ctrl &= ~SCSCR_TIE;
1533
1534 serial_port_out(port, SCSCR, ctrl);
1535 }
1536
1537 static void sci_start_rx(struct uart_port *port)
1538 {
1539 unsigned short ctrl;
1540
1541 ctrl = serial_port_in(port, SCSCR) | port_rx_irq_mask(port);
1542
1543 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1544 ctrl &= ~SCSCR_RDRQE;
1545
1546 serial_port_out(port, SCSCR, ctrl);
1547 }
1548
1549 static void sci_stop_rx(struct uart_port *port)
1550 {
1551 unsigned short ctrl;
1552
1553 ctrl = serial_port_in(port, SCSCR);
1554
1555 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB)
1556 ctrl &= ~SCSCR_RDRQE;
1557
1558 ctrl &= ~port_rx_irq_mask(port);
1559
1560 serial_port_out(port, SCSCR, ctrl);
1561 }
1562
1563 static void sci_enable_ms(struct uart_port *port)
1564 {
1565 /*
1566 * Not supported by hardware, always a nop.
1567 */
1568 }
1569
1570 static void sci_break_ctl(struct uart_port *port, int break_state)
1571 {
1572 struct sci_port *s = to_sci_port(port);
1573 struct plat_sci_reg *reg = sci_regmap[s->cfg->regtype] + SCSPTR;
1574 unsigned short scscr, scsptr;
1575
1576 /* check wheter the port has SCSPTR */
1577 if (!reg->size) {
1578 /*
1579 * Not supported by hardware. Most parts couple break and rx
1580 * interrupts together, with break detection always enabled.
1581 */
1582 return;
1583 }
1584
1585 scsptr = serial_port_in(port, SCSPTR);
1586 scscr = serial_port_in(port, SCSCR);
1587
1588 if (break_state == -1) {
1589 scsptr = (scsptr | SCSPTR_SPB2IO) & ~SCSPTR_SPB2DT;
1590 scscr &= ~SCSCR_TE;
1591 } else {
1592 scsptr = (scsptr | SCSPTR_SPB2DT) & ~SCSPTR_SPB2IO;
1593 scscr |= SCSCR_TE;
1594 }
1595
1596 serial_port_out(port, SCSPTR, scsptr);
1597 serial_port_out(port, SCSCR, scscr);
1598 }
1599
1600 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1601 static bool filter(struct dma_chan *chan, void *slave)
1602 {
1603 struct sh_dmae_slave *param = slave;
1604
1605 dev_dbg(chan->device->dev, "%s: slave ID %d\n",
1606 __func__, param->shdma_slave.slave_id);
1607
1608 chan->private = &param->shdma_slave;
1609 return true;
1610 }
1611
1612 static void rx_timer_fn(unsigned long arg)
1613 {
1614 struct sci_port *s = (struct sci_port *)arg;
1615 struct uart_port *port = &s->port;
1616 u16 scr = serial_port_in(port, SCSCR);
1617
1618 if (port->type == PORT_SCIFA || port->type == PORT_SCIFB) {
1619 scr &= ~SCSCR_RDRQE;
1620 enable_irq(s->irqs[SCIx_RXI_IRQ]);
1621 }
1622 serial_port_out(port, SCSCR, scr | SCSCR_RIE);
1623 dev_dbg(port->dev, "DMA Rx timed out\n");
1624 schedule_work(&s->work_rx);
1625 }
1626
1627 static void sci_request_dma(struct uart_port *port)
1628 {
1629 struct sci_port *s = to_sci_port(port);
1630 struct sh_dmae_slave *param;
1631 struct dma_chan *chan;
1632 dma_cap_mask_t mask;
1633 int nent;
1634
1635 dev_dbg(port->dev, "%s: port %d\n", __func__, port->line);
1636
1637 if (s->cfg->dma_slave_tx <= 0 || s->cfg->dma_slave_rx <= 0)
1638 return;
1639
1640 dma_cap_zero(mask);
1641 dma_cap_set(DMA_SLAVE, mask);
1642
1643 param = &s->param_tx;
1644
1645 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_TX */
1646 param->shdma_slave.slave_id = s->cfg->dma_slave_tx;
1647
1648 s->cookie_tx = -EINVAL;
1649 chan = dma_request_channel(mask, filter, param);
1650 dev_dbg(port->dev, "%s: TX: got channel %p\n", __func__, chan);
1651 if (chan) {
1652 s->chan_tx = chan;
1653 sg_init_table(&s->sg_tx, 1);
1654 /* UART circular tx buffer is an aligned page. */
1655 BUG_ON((uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1656 sg_set_page(&s->sg_tx, virt_to_page(port->state->xmit.buf),
1657 UART_XMIT_SIZE,
1658 (uintptr_t)port->state->xmit.buf & ~PAGE_MASK);
1659 nent = dma_map_sg(port->dev, &s->sg_tx, 1, DMA_TO_DEVICE);
1660 if (!nent)
1661 sci_tx_dma_release(s, false);
1662 else
1663 dev_dbg(port->dev, "%s: mapped %d@%p to %pad\n",
1664 __func__,
1665 sg_dma_len(&s->sg_tx), port->state->xmit.buf,
1666 &sg_dma_address(&s->sg_tx));
1667
1668 s->sg_len_tx = nent;
1669
1670 INIT_WORK(&s->work_tx, work_fn_tx);
1671 }
1672
1673 param = &s->param_rx;
1674
1675 /* Slave ID, e.g., SHDMA_SLAVE_SCIF0_RX */
1676 param->shdma_slave.slave_id = s->cfg->dma_slave_rx;
1677
1678 chan = dma_request_channel(mask, filter, param);
1679 dev_dbg(port->dev, "%s: RX: got channel %p\n", __func__, chan);
1680 if (chan) {
1681 dma_addr_t dma[2];
1682 void *buf[2];
1683 int i;
1684
1685 s->chan_rx = chan;
1686
1687 s->buf_len_rx = 2 * max(16, (int)port->fifosize);
1688 buf[0] = dma_alloc_coherent(port->dev, s->buf_len_rx * 2,
1689 &dma[0], GFP_KERNEL);
1690
1691 if (!buf[0]) {
1692 dev_warn(port->dev,
1693 "failed to allocate dma buffer, using PIO\n");
1694 sci_rx_dma_release(s, true);
1695 return;
1696 }
1697
1698 buf[1] = buf[0] + s->buf_len_rx;
1699 dma[1] = dma[0] + s->buf_len_rx;
1700
1701 for (i = 0; i < 2; i++) {
1702 struct scatterlist *sg = &s->sg_rx[i];
1703
1704 sg_init_table(sg, 1);
1705 sg_set_page(sg, virt_to_page(buf[i]), s->buf_len_rx,
1706 (uintptr_t)buf[i] & ~PAGE_MASK);
1707 sg_dma_address(sg) = dma[i];
1708 }
1709
1710 INIT_WORK(&s->work_rx, work_fn_rx);
1711 setup_timer(&s->rx_timer, rx_timer_fn, (unsigned long)s);
1712
1713 sci_submit_rx(s);
1714 }
1715 }
1716
1717 static void sci_free_dma(struct uart_port *port)
1718 {
1719 struct sci_port *s = to_sci_port(port);
1720
1721 if (s->chan_tx)
1722 sci_tx_dma_release(s, false);
1723 if (s->chan_rx)
1724 sci_rx_dma_release(s, false);
1725 }
1726 #else
1727 static inline void sci_request_dma(struct uart_port *port)
1728 {
1729 }
1730
1731 static inline void sci_free_dma(struct uart_port *port)
1732 {
1733 }
1734 #endif
1735
1736 static int sci_startup(struct uart_port *port)
1737 {
1738 struct sci_port *s = to_sci_port(port);
1739 unsigned long flags;
1740 int ret;
1741
1742 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1743
1744 ret = sci_request_irq(s);
1745 if (unlikely(ret < 0))
1746 return ret;
1747
1748 sci_request_dma(port);
1749
1750 spin_lock_irqsave(&port->lock, flags);
1751 sci_start_tx(port);
1752 sci_start_rx(port);
1753 spin_unlock_irqrestore(&port->lock, flags);
1754
1755 return 0;
1756 }
1757
1758 static void sci_shutdown(struct uart_port *port)
1759 {
1760 struct sci_port *s = to_sci_port(port);
1761 unsigned long flags;
1762
1763 dev_dbg(port->dev, "%s(%d)\n", __func__, port->line);
1764
1765 spin_lock_irqsave(&port->lock, flags);
1766 sci_stop_rx(port);
1767 sci_stop_tx(port);
1768 spin_unlock_irqrestore(&port->lock, flags);
1769
1770 sci_free_dma(port);
1771 sci_free_irq(s);
1772 }
1773
1774 static unsigned int sci_scbrr_calc(struct sci_port *s, unsigned int bps,
1775 unsigned long freq)
1776 {
1777 if (s->sampling_rate)
1778 return DIV_ROUND_CLOSEST(freq, s->sampling_rate * bps) - 1;
1779
1780 /* Warn, but use a safe default */
1781 WARN_ON(1);
1782
1783 return ((freq + 16 * bps) / (32 * bps) - 1);
1784 }
1785
1786 /* calculate sample rate, BRR, and clock select for HSCIF */
1787 static void sci_baud_calc_hscif(unsigned int bps, unsigned long freq,
1788 int *brr, unsigned int *srr,
1789 unsigned int *cks)
1790 {
1791 int sr, c, br, err;
1792 int min_err = 1000; /* 100% */
1793
1794 /* Find the combination of sample rate and clock select with the
1795 smallest deviation from the desired baud rate. */
1796 for (sr = 8; sr <= 32; sr++) {
1797 for (c = 0; c <= 3; c++) {
1798 /* integerized formulas from HSCIF documentation */
1799 br = freq / (sr * (1 << (2 * c + 1)) * bps) - 1;
1800 if (br < 0 || br > 255)
1801 continue;
1802 err = freq / ((br + 1) * bps * sr *
1803 (1 << (2 * c + 1)) / 1000) - 1000;
1804 if (min_err > err) {
1805 min_err = err;
1806 *brr = br;
1807 *srr = sr - 1;
1808 *cks = c;
1809 }
1810 }
1811 }
1812
1813 if (min_err == 1000) {
1814 WARN_ON(1);
1815 /* use defaults */
1816 *brr = 255;
1817 *srr = 15;
1818 *cks = 0;
1819 }
1820 }
1821
1822 static void sci_reset(struct uart_port *port)
1823 {
1824 struct plat_sci_reg *reg;
1825 unsigned int status;
1826
1827 do {
1828 status = serial_port_in(port, SCxSR);
1829 } while (!(status & SCxSR_TEND(port)));
1830
1831 serial_port_out(port, SCSCR, 0x00); /* TE=0, RE=0, CKE1=0 */
1832
1833 reg = sci_getreg(port, SCFCR);
1834 if (reg->size)
1835 serial_port_out(port, SCFCR, SCFCR_RFRST | SCFCR_TFRST);
1836 }
1837
1838 static void sci_set_termios(struct uart_port *port, struct ktermios *termios,
1839 struct ktermios *old)
1840 {
1841 struct sci_port *s = to_sci_port(port);
1842 struct plat_sci_reg *reg;
1843 unsigned int baud, smr_val, max_baud, cks = 0;
1844 int t = -1;
1845 unsigned int srr = 15;
1846
1847 /*
1848 * earlyprintk comes here early on with port->uartclk set to zero.
1849 * the clock framework is not up and running at this point so here
1850 * we assume that 115200 is the maximum baud rate. please note that
1851 * the baud rate is not programmed during earlyprintk - it is assumed
1852 * that the previous boot loader has enabled required clocks and
1853 * setup the baud rate generator hardware for us already.
1854 */
1855 max_baud = port->uartclk ? port->uartclk / 16 : 115200;
1856
1857 baud = uart_get_baud_rate(port, termios, old, 0, max_baud);
1858 if (likely(baud && port->uartclk)) {
1859 if (s->cfg->type == PORT_HSCIF) {
1860 sci_baud_calc_hscif(baud, port->uartclk, &t, &srr,
1861 &cks);
1862 } else {
1863 t = sci_scbrr_calc(s, baud, port->uartclk);
1864 for (cks = 0; t >= 256 && cks <= 3; cks++)
1865 t >>= 2;
1866 }
1867 }
1868
1869 sci_port_enable(s);
1870
1871 sci_reset(port);
1872
1873 smr_val = serial_port_in(port, SCSMR) & 3;
1874
1875 if ((termios->c_cflag & CSIZE) == CS7)
1876 smr_val |= SCSMR_CHR;
1877 if (termios->c_cflag & PARENB)
1878 smr_val |= SCSMR_PE;
1879 if (termios->c_cflag & PARODD)
1880 smr_val |= SCSMR_PE | SCSMR_ODD;
1881 if (termios->c_cflag & CSTOPB)
1882 smr_val |= SCSMR_STOP;
1883
1884 uart_update_timeout(port, termios->c_cflag, baud);
1885
1886 dev_dbg(port->dev, "%s: SMR %x, cks %x, t %x, SCSCR %x\n",
1887 __func__, smr_val, cks, t, s->cfg->scscr);
1888
1889 if (t >= 0) {
1890 serial_port_out(port, SCSMR, (smr_val & ~SCSMR_CKS) | cks);
1891 serial_port_out(port, SCBRR, t);
1892 reg = sci_getreg(port, HSSRR);
1893 if (reg->size)
1894 serial_port_out(port, HSSRR, srr | HSCIF_SRE);
1895 udelay((1000000+(baud-1)) / baud); /* Wait one bit interval */
1896 } else
1897 serial_port_out(port, SCSMR, smr_val);
1898
1899 sci_init_pins(port, termios->c_cflag);
1900
1901 reg = sci_getreg(port, SCFCR);
1902 if (reg->size) {
1903 unsigned short ctrl = serial_port_in(port, SCFCR);
1904
1905 if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
1906 if (termios->c_cflag & CRTSCTS)
1907 ctrl |= SCFCR_MCE;
1908 else
1909 ctrl &= ~SCFCR_MCE;
1910 }
1911
1912 /*
1913 * As we've done a sci_reset() above, ensure we don't
1914 * interfere with the FIFOs while toggling MCE. As the
1915 * reset values could still be set, simply mask them out.
1916 */
1917 ctrl &= ~(SCFCR_RFRST | SCFCR_TFRST);
1918
1919 serial_port_out(port, SCFCR, ctrl);
1920 }
1921
1922 serial_port_out(port, SCSCR, s->cfg->scscr);
1923
1924 #ifdef CONFIG_SERIAL_SH_SCI_DMA
1925 /*
1926 * Calculate delay for 1.5 DMA buffers: see
1927 * drivers/serial/serial_core.c::uart_update_timeout(). With 10 bits
1928 * (CS8), 250Hz, 115200 baud and 64 bytes FIFO, the above function
1929 * calculates 1 jiffie for the data plus 5 jiffies for the "slop(e)."
1930 * Then below we calculate 3 jiffies (12ms) for 1.5 DMA buffers (3 FIFO
1931 * sizes), but it has been found out experimentally, that this is not
1932 * enough: the driver too often needlessly runs on a DMA timeout. 20ms
1933 * as a minimum seem to work perfectly.
1934 */
1935 if (s->chan_rx) {
1936 s->rx_timeout = (port->timeout - HZ / 50) * s->buf_len_rx * 3 /
1937 port->fifosize / 2;
1938 dev_dbg(port->dev, "DMA Rx t-out %ums, tty t-out %u jiffies\n",
1939 s->rx_timeout * 1000 / HZ, port->timeout);
1940 if (s->rx_timeout < msecs_to_jiffies(20))
1941 s->rx_timeout = msecs_to_jiffies(20);
1942 }
1943 #endif
1944
1945 if ((termios->c_cflag & CREAD) != 0)
1946 sci_start_rx(port);
1947
1948 sci_port_disable(s);
1949 }
1950
1951 static void sci_pm(struct uart_port *port, unsigned int state,
1952 unsigned int oldstate)
1953 {
1954 struct sci_port *sci_port = to_sci_port(port);
1955
1956 switch (state) {
1957 case UART_PM_STATE_OFF:
1958 sci_port_disable(sci_port);
1959 break;
1960 default:
1961 sci_port_enable(sci_port);
1962 break;
1963 }
1964 }
1965
1966 static const char *sci_type(struct uart_port *port)
1967 {
1968 switch (port->type) {
1969 case PORT_IRDA:
1970 return "irda";
1971 case PORT_SCI:
1972 return "sci";
1973 case PORT_SCIF:
1974 return "scif";
1975 case PORT_SCIFA:
1976 return "scifa";
1977 case PORT_SCIFB:
1978 return "scifb";
1979 case PORT_HSCIF:
1980 return "hscif";
1981 }
1982
1983 return NULL;
1984 }
1985
1986 static inline unsigned long sci_port_size(struct uart_port *port)
1987 {
1988 /*
1989 * Pick an arbitrary size that encapsulates all of the base
1990 * registers by default. This can be optimized later, or derived
1991 * from platform resource data at such a time that ports begin to
1992 * behave more erratically.
1993 */
1994 if (port->type == PORT_HSCIF)
1995 return 96;
1996 else
1997 return 64;
1998 }
1999
2000 static int sci_remap_port(struct uart_port *port)
2001 {
2002 unsigned long size = sci_port_size(port);
2003
2004 /*
2005 * Nothing to do if there's already an established membase.
2006 */
2007 if (port->membase)
2008 return 0;
2009
2010 if (port->flags & UPF_IOREMAP) {
2011 port->membase = ioremap_nocache(port->mapbase, size);
2012 if (unlikely(!port->membase)) {
2013 dev_err(port->dev, "can't remap port#%d\n", port->line);
2014 return -ENXIO;
2015 }
2016 } else {
2017 /*
2018 * For the simple (and majority of) cases where we don't
2019 * need to do any remapping, just cast the cookie
2020 * directly.
2021 */
2022 port->membase = (void __iomem *)(uintptr_t)port->mapbase;
2023 }
2024
2025 return 0;
2026 }
2027
2028 static void sci_release_port(struct uart_port *port)
2029 {
2030 if (port->flags & UPF_IOREMAP) {
2031 iounmap(port->membase);
2032 port->membase = NULL;
2033 }
2034
2035 release_mem_region(port->mapbase, sci_port_size(port));
2036 }
2037
2038 static int sci_request_port(struct uart_port *port)
2039 {
2040 unsigned long size = sci_port_size(port);
2041 struct resource *res;
2042 int ret;
2043
2044 res = request_mem_region(port->mapbase, size, dev_name(port->dev));
2045 if (unlikely(res == NULL))
2046 return -EBUSY;
2047
2048 ret = sci_remap_port(port);
2049 if (unlikely(ret != 0)) {
2050 release_resource(res);
2051 return ret;
2052 }
2053
2054 return 0;
2055 }
2056
2057 static void sci_config_port(struct uart_port *port, int flags)
2058 {
2059 if (flags & UART_CONFIG_TYPE) {
2060 struct sci_port *sport = to_sci_port(port);
2061
2062 port->type = sport->cfg->type;
2063 sci_request_port(port);
2064 }
2065 }
2066
2067 static int sci_verify_port(struct uart_port *port, struct serial_struct *ser)
2068 {
2069 if (ser->baud_base < 2400)
2070 /* No paper tape reader for Mitch.. */
2071 return -EINVAL;
2072
2073 return 0;
2074 }
2075
2076 static struct uart_ops sci_uart_ops = {
2077 .tx_empty = sci_tx_empty,
2078 .set_mctrl = sci_set_mctrl,
2079 .get_mctrl = sci_get_mctrl,
2080 .start_tx = sci_start_tx,
2081 .stop_tx = sci_stop_tx,
2082 .stop_rx = sci_stop_rx,
2083 .enable_ms = sci_enable_ms,
2084 .break_ctl = sci_break_ctl,
2085 .startup = sci_startup,
2086 .shutdown = sci_shutdown,
2087 .set_termios = sci_set_termios,
2088 .pm = sci_pm,
2089 .type = sci_type,
2090 .release_port = sci_release_port,
2091 .request_port = sci_request_port,
2092 .config_port = sci_config_port,
2093 .verify_port = sci_verify_port,
2094 #ifdef CONFIG_CONSOLE_POLL
2095 .poll_get_char = sci_poll_get_char,
2096 .poll_put_char = sci_poll_put_char,
2097 #endif
2098 };
2099
2100 static int sci_init_single(struct platform_device *dev,
2101 struct sci_port *sci_port, unsigned int index,
2102 struct plat_sci_port *p, bool early)
2103 {
2104 struct uart_port *port = &sci_port->port;
2105 const struct resource *res;
2106 unsigned int sampling_rate;
2107 unsigned int i;
2108 int ret;
2109
2110 sci_port->cfg = p;
2111
2112 port->ops = &sci_uart_ops;
2113 port->iotype = UPIO_MEM;
2114 port->line = index;
2115
2116 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
2117 if (res == NULL)
2118 return -ENOMEM;
2119
2120 port->mapbase = res->start;
2121
2122 for (i = 0; i < ARRAY_SIZE(sci_port->irqs); ++i)
2123 sci_port->irqs[i] = platform_get_irq(dev, i);
2124
2125 /* The SCI generates several interrupts. They can be muxed together or
2126 * connected to different interrupt lines. In the muxed case only one
2127 * interrupt resource is specified. In the non-muxed case three or four
2128 * interrupt resources are specified, as the BRI interrupt is optional.
2129 */
2130 if (sci_port->irqs[0] < 0)
2131 return -ENXIO;
2132
2133 if (sci_port->irqs[1] < 0) {
2134 sci_port->irqs[1] = sci_port->irqs[0];
2135 sci_port->irqs[2] = sci_port->irqs[0];
2136 sci_port->irqs[3] = sci_port->irqs[0];
2137 }
2138
2139 if (p->regtype == SCIx_PROBE_REGTYPE) {
2140 ret = sci_probe_regmap(p);
2141 if (unlikely(ret))
2142 return ret;
2143 }
2144
2145 switch (p->type) {
2146 case PORT_SCIFB:
2147 port->fifosize = 256;
2148 sci_port->overrun_bit = 9;
2149 sampling_rate = 16;
2150 break;
2151 case PORT_HSCIF:
2152 port->fifosize = 128;
2153 sampling_rate = 0;
2154 sci_port->overrun_bit = 0;
2155 break;
2156 case PORT_SCIFA:
2157 port->fifosize = 64;
2158 sci_port->overrun_bit = 9;
2159 sampling_rate = 16;
2160 break;
2161 case PORT_SCIF:
2162 port->fifosize = 16;
2163 if (p->regtype == SCIx_SH7705_SCIF_REGTYPE) {
2164 sci_port->overrun_bit = 9;
2165 sampling_rate = 16;
2166 } else {
2167 sci_port->overrun_bit = 0;
2168 sampling_rate = 32;
2169 }
2170 break;
2171 default:
2172 port->fifosize = 1;
2173 sci_port->overrun_bit = 5;
2174 sampling_rate = 32;
2175 break;
2176 }
2177
2178 /* SCIFA on sh7723 and sh7724 need a custom sampling rate that doesn't
2179 * match the SoC datasheet, this should be investigated. Let platform
2180 * data override the sampling rate for now.
2181 */
2182 sci_port->sampling_rate = p->sampling_rate ? p->sampling_rate
2183 : sampling_rate;
2184
2185 if (!early) {
2186 sci_port->iclk = clk_get(&dev->dev, "sci_ick");
2187 if (IS_ERR(sci_port->iclk)) {
2188 sci_port->iclk = clk_get(&dev->dev, "peripheral_clk");
2189 if (IS_ERR(sci_port->iclk)) {
2190 dev_err(&dev->dev, "can't get iclk\n");
2191 return PTR_ERR(sci_port->iclk);
2192 }
2193 }
2194
2195 /*
2196 * The function clock is optional, ignore it if we can't
2197 * find it.
2198 */
2199 sci_port->fclk = clk_get(&dev->dev, "sci_fck");
2200 if (IS_ERR(sci_port->fclk))
2201 sci_port->fclk = NULL;
2202
2203 port->dev = &dev->dev;
2204
2205 pm_runtime_enable(&dev->dev);
2206 }
2207
2208 sci_port->break_timer.data = (unsigned long)sci_port;
2209 sci_port->break_timer.function = sci_break_timer;
2210 init_timer(&sci_port->break_timer);
2211
2212 /*
2213 * Establish some sensible defaults for the error detection.
2214 */
2215 sci_port->error_mask = (p->type == PORT_SCI) ?
2216 SCI_DEFAULT_ERROR_MASK : SCIF_DEFAULT_ERROR_MASK;
2217
2218 /*
2219 * Establish sensible defaults for the overrun detection, unless
2220 * the part has explicitly disabled support for it.
2221 */
2222
2223 /*
2224 * Make the error mask inclusive of overrun detection, if
2225 * supported.
2226 */
2227 sci_port->error_mask |= 1 << sci_port->overrun_bit;
2228
2229 port->type = p->type;
2230 port->flags = UPF_FIXED_PORT | p->flags;
2231 port->regshift = p->regshift;
2232
2233 /*
2234 * The UART port needs an IRQ value, so we peg this to the RX IRQ
2235 * for the multi-IRQ ports, which is where we are primarily
2236 * concerned with the shutdown path synchronization.
2237 *
2238 * For the muxed case there's nothing more to do.
2239 */
2240 port->irq = sci_port->irqs[SCIx_RXI_IRQ];
2241 port->irqflags = 0;
2242
2243 port->serial_in = sci_serial_in;
2244 port->serial_out = sci_serial_out;
2245
2246 if (p->dma_slave_tx > 0 && p->dma_slave_rx > 0)
2247 dev_dbg(port->dev, "DMA tx %d, rx %d\n",
2248 p->dma_slave_tx, p->dma_slave_rx);
2249
2250 return 0;
2251 }
2252
2253 static void sci_cleanup_single(struct sci_port *port)
2254 {
2255 clk_put(port->iclk);
2256 clk_put(port->fclk);
2257
2258 pm_runtime_disable(port->port.dev);
2259 }
2260
2261 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2262 static void serial_console_putchar(struct uart_port *port, int ch)
2263 {
2264 sci_poll_put_char(port, ch);
2265 }
2266
2267 /*
2268 * Print a string to the serial port trying not to disturb
2269 * any possible real use of the port...
2270 */
2271 static void serial_console_write(struct console *co, const char *s,
2272 unsigned count)
2273 {
2274 struct sci_port *sci_port = &sci_ports[co->index];
2275 struct uart_port *port = &sci_port->port;
2276 unsigned short bits, ctrl;
2277 unsigned long flags;
2278 int locked = 1;
2279
2280 local_irq_save(flags);
2281 if (port->sysrq)
2282 locked = 0;
2283 else if (oops_in_progress)
2284 locked = spin_trylock(&port->lock);
2285 else
2286 spin_lock(&port->lock);
2287
2288 /* first save the SCSCR then disable the interrupts */
2289 ctrl = serial_port_in(port, SCSCR);
2290 serial_port_out(port, SCSCR, sci_port->cfg->scscr);
2291
2292 uart_console_write(port, s, count, serial_console_putchar);
2293
2294 /* wait until fifo is empty and last bit has been transmitted */
2295 bits = SCxSR_TDxE(port) | SCxSR_TEND(port);
2296 while ((serial_port_in(port, SCxSR) & bits) != bits)
2297 cpu_relax();
2298
2299 /* restore the SCSCR */
2300 serial_port_out(port, SCSCR, ctrl);
2301
2302 if (locked)
2303 spin_unlock(&port->lock);
2304 local_irq_restore(flags);
2305 }
2306
2307 static int serial_console_setup(struct console *co, char *options)
2308 {
2309 struct sci_port *sci_port;
2310 struct uart_port *port;
2311 int baud = 115200;
2312 int bits = 8;
2313 int parity = 'n';
2314 int flow = 'n';
2315 int ret;
2316
2317 /*
2318 * Refuse to handle any bogus ports.
2319 */
2320 if (co->index < 0 || co->index >= SCI_NPORTS)
2321 return -ENODEV;
2322
2323 sci_port = &sci_ports[co->index];
2324 port = &sci_port->port;
2325
2326 /*
2327 * Refuse to handle uninitialized ports.
2328 */
2329 if (!port->ops)
2330 return -ENODEV;
2331
2332 ret = sci_remap_port(port);
2333 if (unlikely(ret != 0))
2334 return ret;
2335
2336 if (options)
2337 uart_parse_options(options, &baud, &parity, &bits, &flow);
2338
2339 return uart_set_options(port, co, baud, parity, bits, flow);
2340 }
2341
2342 static struct console serial_console = {
2343 .name = "ttySC",
2344 .device = uart_console_device,
2345 .write = serial_console_write,
2346 .setup = serial_console_setup,
2347 .flags = CON_PRINTBUFFER,
2348 .index = -1,
2349 .data = &sci_uart_driver,
2350 };
2351
2352 static struct console early_serial_console = {
2353 .name = "early_ttySC",
2354 .write = serial_console_write,
2355 .flags = CON_PRINTBUFFER,
2356 .index = -1,
2357 };
2358
2359 static char early_serial_buf[32];
2360
2361 static int sci_probe_earlyprintk(struct platform_device *pdev)
2362 {
2363 struct plat_sci_port *cfg = dev_get_platdata(&pdev->dev);
2364
2365 if (early_serial_console.data)
2366 return -EEXIST;
2367
2368 early_serial_console.index = pdev->id;
2369
2370 sci_init_single(pdev, &sci_ports[pdev->id], pdev->id, cfg, true);
2371
2372 serial_console_setup(&early_serial_console, early_serial_buf);
2373
2374 if (!strstr(early_serial_buf, "keep"))
2375 early_serial_console.flags |= CON_BOOT;
2376
2377 register_console(&early_serial_console);
2378 return 0;
2379 }
2380
2381 #define SCI_CONSOLE (&serial_console)
2382
2383 #else
2384 static inline int sci_probe_earlyprintk(struct platform_device *pdev)
2385 {
2386 return -EINVAL;
2387 }
2388
2389 #define SCI_CONSOLE NULL
2390
2391 #endif /* CONFIG_SERIAL_SH_SCI_CONSOLE */
2392
2393 static const char banner[] __initconst = "SuperH (H)SCI(F) driver initialized";
2394
2395 static struct uart_driver sci_uart_driver = {
2396 .owner = THIS_MODULE,
2397 .driver_name = "sci",
2398 .dev_name = "ttySC",
2399 .major = SCI_MAJOR,
2400 .minor = SCI_MINOR_START,
2401 .nr = SCI_NPORTS,
2402 .cons = SCI_CONSOLE,
2403 };
2404
2405 static int sci_remove(struct platform_device *dev)
2406 {
2407 struct sci_port *port = platform_get_drvdata(dev);
2408
2409 cpufreq_unregister_notifier(&port->freq_transition,
2410 CPUFREQ_TRANSITION_NOTIFIER);
2411
2412 uart_remove_one_port(&sci_uart_driver, &port->port);
2413
2414 sci_cleanup_single(port);
2415
2416 return 0;
2417 }
2418
2419 struct sci_port_info {
2420 unsigned int type;
2421 unsigned int regtype;
2422 };
2423
2424 static const struct of_device_id of_sci_match[] = {
2425 {
2426 .compatible = "renesas,scif",
2427 .data = &(const struct sci_port_info) {
2428 .type = PORT_SCIF,
2429 .regtype = SCIx_SH4_SCIF_REGTYPE,
2430 },
2431 }, {
2432 .compatible = "renesas,scifa",
2433 .data = &(const struct sci_port_info) {
2434 .type = PORT_SCIFA,
2435 .regtype = SCIx_SCIFA_REGTYPE,
2436 },
2437 }, {
2438 .compatible = "renesas,scifb",
2439 .data = &(const struct sci_port_info) {
2440 .type = PORT_SCIFB,
2441 .regtype = SCIx_SCIFB_REGTYPE,
2442 },
2443 }, {
2444 .compatible = "renesas,hscif",
2445 .data = &(const struct sci_port_info) {
2446 .type = PORT_HSCIF,
2447 .regtype = SCIx_HSCIF_REGTYPE,
2448 },
2449 }, {
2450 /* Terminator */
2451 },
2452 };
2453 MODULE_DEVICE_TABLE(of, of_sci_match);
2454
2455 static struct plat_sci_port *
2456 sci_parse_dt(struct platform_device *pdev, unsigned int *dev_id)
2457 {
2458 struct device_node *np = pdev->dev.of_node;
2459 const struct of_device_id *match;
2460 const struct sci_port_info *info;
2461 struct plat_sci_port *p;
2462 int id;
2463
2464 if (!IS_ENABLED(CONFIG_OF) || !np)
2465 return NULL;
2466
2467 match = of_match_node(of_sci_match, pdev->dev.of_node);
2468 if (!match)
2469 return NULL;
2470
2471 info = match->data;
2472
2473 p = devm_kzalloc(&pdev->dev, sizeof(struct plat_sci_port), GFP_KERNEL);
2474 if (!p) {
2475 dev_err(&pdev->dev, "failed to allocate DT config data\n");
2476 return NULL;
2477 }
2478
2479 /* Get the line number for the aliases node. */
2480 id = of_alias_get_id(np, "serial");
2481 if (id < 0) {
2482 dev_err(&pdev->dev, "failed to get alias id (%d)\n", id);
2483 return NULL;
2484 }
2485
2486 *dev_id = id;
2487
2488 p->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
2489 p->type = info->type;
2490 p->regtype = info->regtype;
2491 p->scscr = SCSCR_RE | SCSCR_TE;
2492
2493 return p;
2494 }
2495
2496 static int sci_probe_single(struct platform_device *dev,
2497 unsigned int index,
2498 struct plat_sci_port *p,
2499 struct sci_port *sciport)
2500 {
2501 int ret;
2502
2503 /* Sanity check */
2504 if (unlikely(index >= SCI_NPORTS)) {
2505 dev_notice(&dev->dev, "Attempting to register port %d when only %d are available\n",
2506 index+1, SCI_NPORTS);
2507 dev_notice(&dev->dev, "Consider bumping CONFIG_SERIAL_SH_SCI_NR_UARTS!\n");
2508 return -EINVAL;
2509 }
2510
2511 ret = sci_init_single(dev, sciport, index, p, false);
2512 if (ret)
2513 return ret;
2514
2515 ret = uart_add_one_port(&sci_uart_driver, &sciport->port);
2516 if (ret) {
2517 sci_cleanup_single(sciport);
2518 return ret;
2519 }
2520
2521 return 0;
2522 }
2523
2524 static int sci_probe(struct platform_device *dev)
2525 {
2526 struct plat_sci_port *p;
2527 struct sci_port *sp;
2528 unsigned int dev_id;
2529 int ret;
2530
2531 /*
2532 * If we've come here via earlyprintk initialization, head off to
2533 * the special early probe. We don't have sufficient device state
2534 * to make it beyond this yet.
2535 */
2536 if (is_early_platform_device(dev))
2537 return sci_probe_earlyprintk(dev);
2538
2539 if (dev->dev.of_node) {
2540 p = sci_parse_dt(dev, &dev_id);
2541 if (p == NULL)
2542 return -EINVAL;
2543 } else {
2544 p = dev->dev.platform_data;
2545 if (p == NULL) {
2546 dev_err(&dev->dev, "no platform data supplied\n");
2547 return -EINVAL;
2548 }
2549
2550 dev_id = dev->id;
2551 }
2552
2553 sp = &sci_ports[dev_id];
2554 platform_set_drvdata(dev, sp);
2555
2556 ret = sci_probe_single(dev, dev_id, p, sp);
2557 if (ret)
2558 return ret;
2559
2560 sp->freq_transition.notifier_call = sci_notifier;
2561
2562 ret = cpufreq_register_notifier(&sp->freq_transition,
2563 CPUFREQ_TRANSITION_NOTIFIER);
2564 if (unlikely(ret < 0)) {
2565 uart_remove_one_port(&sci_uart_driver, &sp->port);
2566 sci_cleanup_single(sp);
2567 return ret;
2568 }
2569
2570 #ifdef CONFIG_SH_STANDARD_BIOS
2571 sh_bios_gdb_detach();
2572 #endif
2573
2574 return 0;
2575 }
2576
2577 static int sci_suspend(struct device *dev)
2578 {
2579 struct sci_port *sport = dev_get_drvdata(dev);
2580
2581 if (sport)
2582 uart_suspend_port(&sci_uart_driver, &sport->port);
2583
2584 return 0;
2585 }
2586
2587 static int sci_resume(struct device *dev)
2588 {
2589 struct sci_port *sport = dev_get_drvdata(dev);
2590
2591 if (sport)
2592 uart_resume_port(&sci_uart_driver, &sport->port);
2593
2594 return 0;
2595 }
2596
2597 static const struct dev_pm_ops sci_dev_pm_ops = {
2598 .suspend = sci_suspend,
2599 .resume = sci_resume,
2600 };
2601
2602 static struct platform_driver sci_driver = {
2603 .probe = sci_probe,
2604 .remove = sci_remove,
2605 .driver = {
2606 .name = "sh-sci",
2607 .owner = THIS_MODULE,
2608 .pm = &sci_dev_pm_ops,
2609 .of_match_table = of_match_ptr(of_sci_match),
2610 },
2611 };
2612
2613 static int __init sci_init(void)
2614 {
2615 int ret;
2616
2617 pr_info("%s\n", banner);
2618
2619 ret = uart_register_driver(&sci_uart_driver);
2620 if (likely(ret == 0)) {
2621 ret = platform_driver_register(&sci_driver);
2622 if (unlikely(ret))
2623 uart_unregister_driver(&sci_uart_driver);
2624 }
2625
2626 return ret;
2627 }
2628
2629 static void __exit sci_exit(void)
2630 {
2631 platform_driver_unregister(&sci_driver);
2632 uart_unregister_driver(&sci_uart_driver);
2633 }
2634
2635 #ifdef CONFIG_SERIAL_SH_SCI_CONSOLE
2636 early_platform_init_buffer("earlyprintk", &sci_driver,
2637 early_serial_buf, ARRAY_SIZE(early_serial_buf));
2638 #endif
2639 module_init(sci_init);
2640 module_exit(sci_exit);
2641
2642 MODULE_LICENSE("GPL");
2643 MODULE_ALIAS("platform:sh-sci");
2644 MODULE_AUTHOR("Paul Mundt");
2645 MODULE_DESCRIPTION("SuperH (H)SCI(F) serial driver");
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