3 * Purpose: Generic MCA handling layer
5 * Updated for latest kernel
6 * Copyright (C) 2003 Hewlett-Packard Co
7 * David Mosberger-Tang <davidm@hpl.hp.com>
9 * Copyright (C) 2002 Dell Inc.
10 * Copyright (C) Matt Domsch (Matt_Domsch@dell.com)
12 * Copyright (C) 2002 Intel
13 * Copyright (C) Jenna Hall (jenna.s.hall@intel.com)
15 * Copyright (C) 2001 Intel
16 * Copyright (C) Fred Lewis (frederick.v.lewis@intel.com)
18 * Copyright (C) 2000 Intel
19 * Copyright (C) Chuck Fleckenstein (cfleck@co.intel.com)
21 * Copyright (C) 1999, 2004 Silicon Graphics, Inc.
22 * Copyright (C) Vijay Chander(vijay@engr.sgi.com)
24 * 03/04/15 D. Mosberger Added INIT backtrace support.
25 * 02/03/25 M. Domsch GUID cleanups
27 * 02/01/04 J. Hall Aligned MCA stack to 16 bytes, added platform vs. CPU
28 * error flag, set SAL default return values, changed
29 * error record structure to linked list, added init call
30 * to sal_get_state_info_size().
32 * 01/01/03 F. Lewis Added setup of CMCI and CPEI IRQs, logging of corrected
33 * platform errors, completed code for logging of
34 * corrected & uncorrected machine check errors, and
35 * updated for conformance with Nov. 2000 revision of the
37 * 00/03/29 C. Fleckenstein Fixed PAL/SAL update issues, began MCA bug fixes, logging issues,
38 * added min save state dump, added INIT handler.
40 * 2003-12-08 Keith Owens <kaos@sgi.com>
41 * smp_call_function() must not be called from interrupt context (can
42 * deadlock on tasklist_lock). Use keventd to call smp_call_function().
44 * 2004-02-01 Keith Owens <kaos@sgi.com>
45 * Avoid deadlock when using printk() for MCA and INIT records.
46 * Delete all record printing code, moved to salinfo_decode in user space.
47 * Mark variables and functions static where possible.
48 * Delete dead variables and functions.
49 * Reorder to remove the need for forward declarations and to consolidate
52 * 2005-08-12 Keith Owens <kaos@sgi.com>
53 * Convert MCA/INIT handlers to use per event stacks and SAL/OS state.
55 * 2005-10-07 Keith Owens <kaos@sgi.com>
56 * Add notify_die() hooks.
58 #include <linux/config.h>
59 #include <linux/types.h>
60 #include <linux/init.h>
61 #include <linux/sched.h>
62 #include <linux/interrupt.h>
63 #include <linux/irq.h>
64 #include <linux/smp_lock.h>
65 #include <linux/bootmem.h>
66 #include <linux/acpi.h>
67 #include <linux/timer.h>
68 #include <linux/module.h>
69 #include <linux/kernel.h>
70 #include <linux/smp.h>
71 #include <linux/workqueue.h>
73 #include <asm/delay.h>
74 #include <asm/kdebug.h>
75 #include <asm/machvec.h>
76 #include <asm/meminit.h>
78 #include <asm/ptrace.h>
79 #include <asm/system.h>
84 #include <asm/hw_irq.h>
88 #if defined(IA64_MCA_DEBUG_INFO)
89 # define IA64_MCA_DEBUG(fmt...) printk(fmt)
91 # define IA64_MCA_DEBUG(fmt...)
94 /* Used by mca_asm.S */
95 u32 ia64_mca_serialize
;
96 DEFINE_PER_CPU(u64
, ia64_mca_data
); /* == __per_cpu_mca[smp_processor_id()] */
97 DEFINE_PER_CPU(u64
, ia64_mca_per_cpu_pte
); /* PTE to map per-CPU area */
98 DEFINE_PER_CPU(u64
, ia64_mca_pal_pte
); /* PTE to map PAL code */
99 DEFINE_PER_CPU(u64
, ia64_mca_pal_base
); /* vaddr PAL code granule */
101 unsigned long __per_cpu_mca
[NR_CPUS
];
104 extern void ia64_os_init_dispatch_monarch (void);
105 extern void ia64_os_init_dispatch_slave (void);
107 static int monarch_cpu
= -1;
109 static ia64_mc_info_t ia64_mc_info
;
111 #define MAX_CPE_POLL_INTERVAL (15*60*HZ) /* 15 minutes */
112 #define MIN_CPE_POLL_INTERVAL (2*60*HZ) /* 2 minutes */
113 #define CMC_POLL_INTERVAL (1*60*HZ) /* 1 minute */
114 #define CPE_HISTORY_LENGTH 5
115 #define CMC_HISTORY_LENGTH 5
117 static struct timer_list cpe_poll_timer
;
118 static struct timer_list cmc_poll_timer
;
120 * This variable tells whether we are currently in polling mode.
121 * Start with this in the wrong state so we won't play w/ timers
122 * before the system is ready.
124 static int cmc_polling_enabled
= 1;
127 * Clearing this variable prevents CPE polling from getting activated
128 * in mca_late_init. Use it if your system doesn't provide a CPEI,
129 * but encounters problems retrieving CPE logs. This should only be
130 * necessary for debugging.
132 static int cpe_poll_enabled
= 1;
134 extern void salinfo_log_wakeup(int type
, u8
*buffer
, u64 size
, int irqsafe
);
140 ia64_mca_spin(const char *func
)
142 printk(KERN_EMERG
"%s: spinning here, not returning to SAL\n", func
);
147 * IA64_MCA log support
149 #define IA64_MAX_LOGS 2 /* Double-buffering for nested MCAs */
150 #define IA64_MAX_LOG_TYPES 4 /* MCA, INIT, CMC, CPE */
152 typedef struct ia64_state_log_s
156 unsigned long isl_count
;
157 ia64_err_rec_t
*isl_log
[IA64_MAX_LOGS
]; /* need space to store header + error log */
160 static ia64_state_log_t ia64_state_log
[IA64_MAX_LOG_TYPES
];
162 #define IA64_LOG_ALLOCATE(it, size) \
163 {ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)] = \
164 (ia64_err_rec_t *)alloc_bootmem(size); \
165 ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)] = \
166 (ia64_err_rec_t *)alloc_bootmem(size);}
167 #define IA64_LOG_LOCK_INIT(it) spin_lock_init(&ia64_state_log[it].isl_lock)
168 #define IA64_LOG_LOCK(it) spin_lock_irqsave(&ia64_state_log[it].isl_lock, s)
169 #define IA64_LOG_UNLOCK(it) spin_unlock_irqrestore(&ia64_state_log[it].isl_lock,s)
170 #define IA64_LOG_NEXT_INDEX(it) ia64_state_log[it].isl_index
171 #define IA64_LOG_CURR_INDEX(it) 1 - ia64_state_log[it].isl_index
172 #define IA64_LOG_INDEX_INC(it) \
173 {ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index; \
174 ia64_state_log[it].isl_count++;}
175 #define IA64_LOG_INDEX_DEC(it) \
176 ia64_state_log[it].isl_index = 1 - ia64_state_log[it].isl_index
177 #define IA64_LOG_NEXT_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_NEXT_INDEX(it)]))
178 #define IA64_LOG_CURR_BUFFER(it) (void *)((ia64_state_log[it].isl_log[IA64_LOG_CURR_INDEX(it)]))
179 #define IA64_LOG_COUNT(it) ia64_state_log[it].isl_count
183 * Reset the OS ia64 log buffer
184 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
188 ia64_log_init(int sal_info_type
)
192 IA64_LOG_NEXT_INDEX(sal_info_type
) = 0;
193 IA64_LOG_LOCK_INIT(sal_info_type
);
195 // SAL will tell us the maximum size of any error record of this type
196 max_size
= ia64_sal_get_state_info_size(sal_info_type
);
198 /* alloc_bootmem() doesn't like zero-sized allocations! */
201 // set up OS data structures to hold error info
202 IA64_LOG_ALLOCATE(sal_info_type
, max_size
);
203 memset(IA64_LOG_CURR_BUFFER(sal_info_type
), 0, max_size
);
204 memset(IA64_LOG_NEXT_BUFFER(sal_info_type
), 0, max_size
);
210 * Get the current MCA log from SAL and copy it into the OS log buffer.
212 * Inputs : info_type (SAL_INFO_TYPE_{MCA,INIT,CMC,CPE})
213 * irq_safe whether you can use printk at this point
214 * Outputs : size (total record length)
215 * *buffer (ptr to error record)
219 ia64_log_get(int sal_info_type
, u8
**buffer
, int irq_safe
)
221 sal_log_record_header_t
*log_buffer
;
225 IA64_LOG_LOCK(sal_info_type
);
227 /* Get the process state information */
228 log_buffer
= IA64_LOG_NEXT_BUFFER(sal_info_type
);
230 total_len
= ia64_sal_get_state_info(sal_info_type
, (u64
*)log_buffer
);
233 IA64_LOG_INDEX_INC(sal_info_type
);
234 IA64_LOG_UNLOCK(sal_info_type
);
236 IA64_MCA_DEBUG("%s: SAL error record type %d retrieved. "
237 "Record length = %ld\n", __FUNCTION__
, sal_info_type
, total_len
);
239 *buffer
= (u8
*) log_buffer
;
242 IA64_LOG_UNLOCK(sal_info_type
);
248 * ia64_mca_log_sal_error_record
250 * This function retrieves a specified error record type from SAL
251 * and wakes up any processes waiting for error records.
253 * Inputs : sal_info_type (Type of error record MCA/CMC/CPE)
254 * FIXME: remove MCA and irq_safe.
257 ia64_mca_log_sal_error_record(int sal_info_type
)
260 sal_log_record_header_t
*rh
;
262 int irq_safe
= sal_info_type
!= SAL_INFO_TYPE_MCA
;
263 #ifdef IA64_MCA_DEBUG_INFO
264 static const char * const rec_name
[] = { "MCA", "INIT", "CMC", "CPE" };
267 size
= ia64_log_get(sal_info_type
, &buffer
, irq_safe
);
271 salinfo_log_wakeup(sal_info_type
, buffer
, size
, irq_safe
);
274 IA64_MCA_DEBUG("CPU %d: SAL log contains %s error record\n",
276 sal_info_type
< ARRAY_SIZE(rec_name
) ? rec_name
[sal_info_type
] : "UNKNOWN");
278 /* Clear logs from corrected errors in case there's no user-level logger */
279 rh
= (sal_log_record_header_t
*)buffer
;
280 if (rh
->severity
== sal_log_severity_corrected
)
281 ia64_sal_clear_state_info(sal_info_type
);
285 * platform dependent error handling
287 #ifndef PLATFORM_MCA_HANDLERS
294 ia64_mca_cpe_int_handler (int cpe_irq
, void *arg
, struct pt_regs
*ptregs
)
296 static unsigned long cpe_history
[CPE_HISTORY_LENGTH
];
298 static DEFINE_SPINLOCK(cpe_history_lock
);
300 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
301 __FUNCTION__
, cpe_irq
, smp_processor_id());
303 /* SAL spec states this should run w/ interrupts enabled */
306 /* Get the CPE error record and log it */
307 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CPE
);
309 spin_lock(&cpe_history_lock
);
310 if (!cpe_poll_enabled
&& cpe_vector
>= 0) {
312 int i
, count
= 1; /* we know 1 happened now */
313 unsigned long now
= jiffies
;
315 for (i
= 0; i
< CPE_HISTORY_LENGTH
; i
++) {
316 if (now
- cpe_history
[i
] <= HZ
)
320 IA64_MCA_DEBUG(KERN_INFO
"CPE threshold %d/%d\n", count
, CPE_HISTORY_LENGTH
);
321 if (count
>= CPE_HISTORY_LENGTH
) {
323 cpe_poll_enabled
= 1;
324 spin_unlock(&cpe_history_lock
);
325 disable_irq_nosync(local_vector_to_irq(IA64_CPE_VECTOR
));
328 * Corrected errors will still be corrected, but
329 * make sure there's a log somewhere that indicates
330 * something is generating more than we can handle.
332 printk(KERN_WARNING
"WARNING: Switching to polling CPE handler; error records may be lost\n");
334 mod_timer(&cpe_poll_timer
, jiffies
+ MIN_CPE_POLL_INTERVAL
);
336 /* lock already released, get out now */
339 cpe_history
[index
++] = now
;
340 if (index
== CPE_HISTORY_LENGTH
)
344 spin_unlock(&cpe_history_lock
);
348 #endif /* CONFIG_ACPI */
352 * ia64_mca_register_cpev
354 * Register the corrected platform error vector with SAL.
357 * cpev Corrected Platform Error Vector number
363 ia64_mca_register_cpev (int cpev
)
365 /* Register the CPE interrupt vector with SAL */
366 struct ia64_sal_retval isrv
;
368 isrv
= ia64_sal_mc_set_params(SAL_MC_PARAM_CPE_INT
, SAL_MC_PARAM_MECHANISM_INT
, cpev
, 0, 0);
370 printk(KERN_ERR
"Failed to register Corrected Platform "
371 "Error interrupt vector with SAL (status %ld)\n", isrv
.status
);
375 IA64_MCA_DEBUG("%s: corrected platform error "
376 "vector %#x registered\n", __FUNCTION__
, cpev
);
378 #endif /* CONFIG_ACPI */
380 #endif /* PLATFORM_MCA_HANDLERS */
383 * ia64_mca_cmc_vector_setup
385 * Setup the corrected machine check vector register in the processor.
386 * (The interrupt is masked on boot. ia64_mca_late_init unmask this.)
387 * This function is invoked on a per-processor basis.
396 ia64_mca_cmc_vector_setup (void)
400 cmcv
.cmcv_regval
= 0;
401 cmcv
.cmcv_mask
= 1; /* Mask/disable interrupt at first */
402 cmcv
.cmcv_vector
= IA64_CMC_VECTOR
;
403 ia64_setreg(_IA64_REG_CR_CMCV
, cmcv
.cmcv_regval
);
405 IA64_MCA_DEBUG("%s: CPU %d corrected "
406 "machine check vector %#x registered.\n",
407 __FUNCTION__
, smp_processor_id(), IA64_CMC_VECTOR
);
409 IA64_MCA_DEBUG("%s: CPU %d CMCV = %#016lx\n",
410 __FUNCTION__
, smp_processor_id(), ia64_getreg(_IA64_REG_CR_CMCV
));
414 * ia64_mca_cmc_vector_disable
416 * Mask the corrected machine check vector register in the processor.
417 * This function is invoked on a per-processor basis.
426 ia64_mca_cmc_vector_disable (void *dummy
)
430 cmcv
.cmcv_regval
= ia64_getreg(_IA64_REG_CR_CMCV
);
432 cmcv
.cmcv_mask
= 1; /* Mask/disable interrupt */
433 ia64_setreg(_IA64_REG_CR_CMCV
, cmcv
.cmcv_regval
);
435 IA64_MCA_DEBUG("%s: CPU %d corrected "
436 "machine check vector %#x disabled.\n",
437 __FUNCTION__
, smp_processor_id(), cmcv
.cmcv_vector
);
441 * ia64_mca_cmc_vector_enable
443 * Unmask the corrected machine check vector register in the processor.
444 * This function is invoked on a per-processor basis.
453 ia64_mca_cmc_vector_enable (void *dummy
)
457 cmcv
.cmcv_regval
= ia64_getreg(_IA64_REG_CR_CMCV
);
459 cmcv
.cmcv_mask
= 0; /* Unmask/enable interrupt */
460 ia64_setreg(_IA64_REG_CR_CMCV
, cmcv
.cmcv_regval
);
462 IA64_MCA_DEBUG("%s: CPU %d corrected "
463 "machine check vector %#x enabled.\n",
464 __FUNCTION__
, smp_processor_id(), cmcv
.cmcv_vector
);
468 * ia64_mca_cmc_vector_disable_keventd
470 * Called via keventd (smp_call_function() is not safe in interrupt context) to
471 * disable the cmc interrupt vector.
474 ia64_mca_cmc_vector_disable_keventd(void *unused
)
476 on_each_cpu(ia64_mca_cmc_vector_disable
, NULL
, 1, 0);
480 * ia64_mca_cmc_vector_enable_keventd
482 * Called via keventd (smp_call_function() is not safe in interrupt context) to
483 * enable the cmc interrupt vector.
486 ia64_mca_cmc_vector_enable_keventd(void *unused
)
488 on_each_cpu(ia64_mca_cmc_vector_enable
, NULL
, 1, 0);
494 * Send an inter-cpu interrupt to wake-up a particular cpu
495 * and mark that cpu to be out of rendez.
501 ia64_mca_wakeup(int cpu
)
503 platform_send_ipi(cpu
, IA64_MCA_WAKEUP_VECTOR
, IA64_IPI_DM_INT
, 0);
504 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
509 * ia64_mca_wakeup_all
511 * Wakeup all the cpus which have rendez'ed previously.
517 ia64_mca_wakeup_all(void)
521 /* Clear the Rendez checkin flag for all cpus */
522 for_each_online_cpu(cpu
) {
523 if (ia64_mc_info
.imi_rendez_checkin
[cpu
] == IA64_MCA_RENDEZ_CHECKIN_DONE
)
524 ia64_mca_wakeup(cpu
);
530 * ia64_mca_rendez_interrupt_handler
532 * This is handler used to put slave processors into spinloop
533 * while the monarch processor does the mca handling and later
534 * wake each slave up once the monarch is done.
540 ia64_mca_rendez_int_handler(int rendez_irq
, void *arg
, struct pt_regs
*regs
)
543 int cpu
= smp_processor_id();
545 /* Mask all interrupts */
546 local_irq_save(flags
);
547 if (notify_die(DIE_MCA_RENDZVOUS_ENTER
, "MCA", regs
, 0, 0, 0)
549 ia64_mca_spin(__FUNCTION__
);
551 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_DONE
;
552 /* Register with the SAL monarch that the slave has
555 ia64_sal_mc_rendez();
557 if (notify_die(DIE_MCA_RENDZVOUS_PROCESS
, "MCA", regs
, 0, 0, 0)
559 ia64_mca_spin(__FUNCTION__
);
561 /* Wait for the monarch cpu to exit. */
562 while (monarch_cpu
!= -1)
563 cpu_relax(); /* spin until monarch leaves */
565 if (notify_die(DIE_MCA_RENDZVOUS_LEAVE
, "MCA", regs
, 0, 0, 0)
567 ia64_mca_spin(__FUNCTION__
);
569 /* Enable all interrupts */
570 local_irq_restore(flags
);
575 * ia64_mca_wakeup_int_handler
577 * The interrupt handler for processing the inter-cpu interrupt to the
578 * slave cpu which was spinning in the rendez loop.
579 * Since this spinning is done by turning off the interrupts and
580 * polling on the wakeup-interrupt bit in the IRR, there is
581 * nothing useful to be done in the handler.
583 * Inputs : wakeup_irq (Wakeup-interrupt bit)
584 * arg (Interrupt handler specific argument)
585 * ptregs (Exception frame at the time of the interrupt)
590 ia64_mca_wakeup_int_handler(int wakeup_irq
, void *arg
, struct pt_regs
*ptregs
)
595 /* Function pointer for extra MCA recovery */
596 int (*ia64_mca_ucmc_extension
)
597 (void*,struct ia64_sal_os_state
*)
601 ia64_reg_MCA_extension(int (*fn
)(void *, struct ia64_sal_os_state
*))
603 if (ia64_mca_ucmc_extension
)
606 ia64_mca_ucmc_extension
= fn
;
611 ia64_unreg_MCA_extension(void)
613 if (ia64_mca_ucmc_extension
)
614 ia64_mca_ucmc_extension
= NULL
;
617 EXPORT_SYMBOL(ia64_reg_MCA_extension
);
618 EXPORT_SYMBOL(ia64_unreg_MCA_extension
);
622 copy_reg(const u64
*fr
, u64 fnat
, u64
*tr
, u64
*tnat
)
624 u64 fslot
, tslot
, nat
;
626 fslot
= ((unsigned long)fr
>> 3) & 63;
627 tslot
= ((unsigned long)tr
>> 3) & 63;
628 *tnat
&= ~(1UL << tslot
);
629 nat
= (fnat
>> fslot
) & 1;
630 *tnat
|= (nat
<< tslot
);
633 /* On entry to this routine, we are running on the per cpu stack, see
634 * mca_asm.h. The original stack has not been touched by this event. Some of
635 * the original stack's registers will be in the RBS on this stack. This stack
636 * also contains a partial pt_regs and switch_stack, the rest of the data is in
639 * The first thing to do is modify the original stack to look like a blocked
640 * task so we can run backtrace on the original task. Also mark the per cpu
641 * stack as current to ensure that we use the correct task state, it also means
642 * that we can do backtrace on the MCA/INIT handler code itself.
646 ia64_mca_modify_original_stack(struct pt_regs
*regs
,
647 const struct switch_stack
*sw
,
648 struct ia64_sal_os_state
*sos
,
651 char *p
, comm
[sizeof(current
->comm
)];
653 extern char ia64_leave_kernel
[]; /* Need asm address, not function descriptor */
654 const pal_min_state_area_t
*ms
= sos
->pal_min_state
;
655 task_t
*previous_current
;
656 struct pt_regs
*old_regs
;
657 struct switch_stack
*old_sw
;
658 unsigned size
= sizeof(struct pt_regs
) +
659 sizeof(struct switch_stack
) + 16;
660 u64
*old_bspstore
, *old_bsp
;
661 u64
*new_bspstore
, *new_bsp
;
662 u64 old_unat
, old_rnat
, new_rnat
, nat
;
663 u64 slots
, loadrs
= regs
->loadrs
;
664 u64 r12
= ms
->pmsa_gr
[12-1], r13
= ms
->pmsa_gr
[13-1];
665 u64 ar_bspstore
= regs
->ar_bspstore
;
666 u64 ar_bsp
= regs
->ar_bspstore
+ (loadrs
>> 16);
669 int cpu
= smp_processor_id();
671 previous_current
= curr_task(cpu
);
672 set_curr_task(cpu
, current
);
673 if ((p
= strchr(current
->comm
, ' ')))
676 /* Best effort attempt to cope with MCA/INIT delivered while in
679 regs
->cr_ipsr
= ms
->pmsa_ipsr
;
680 if (ia64_psr(regs
)->dt
== 0) {
692 if (ia64_psr(regs
)->rt
== 0) {
705 /* mca_asm.S ia64_old_stack() cannot assume that the dirty registers
706 * have been copied to the old stack, the old stack may fail the
707 * validation tests below. So ia64_old_stack() must restore the dirty
708 * registers from the new stack. The old and new bspstore probably
709 * have different alignments, so loadrs calculated on the old bsp
710 * cannot be used to restore from the new bsp. Calculate a suitable
711 * loadrs for the new stack and save it in the new pt_regs, where
712 * ia64_old_stack() can get it.
714 old_bspstore
= (u64
*)ar_bspstore
;
715 old_bsp
= (u64
*)ar_bsp
;
716 slots
= ia64_rse_num_regs(old_bspstore
, old_bsp
);
717 new_bspstore
= (u64
*)((u64
)current
+ IA64_RBS_OFFSET
);
718 new_bsp
= ia64_rse_skip_regs(new_bspstore
, slots
);
719 regs
->loadrs
= (new_bsp
- new_bspstore
) * 8 << 16;
721 /* Verify the previous stack state before we change it */
722 if (user_mode(regs
)) {
723 msg
= "occurred in user space";
726 if (r13
!= sos
->prev_IA64_KR_CURRENT
) {
727 msg
= "inconsistent previous current and r13";
730 if ((r12
- r13
) >= KERNEL_STACK_SIZE
) {
731 msg
= "inconsistent r12 and r13";
734 if ((ar_bspstore
- r13
) >= KERNEL_STACK_SIZE
) {
735 msg
= "inconsistent ar.bspstore and r13";
740 msg
= "old_bspstore is in the wrong region";
743 if ((ar_bsp
- r13
) >= KERNEL_STACK_SIZE
) {
744 msg
= "inconsistent ar.bsp and r13";
747 size
+= (ia64_rse_skip_regs(old_bspstore
, slots
) - old_bspstore
) * 8;
748 if (ar_bspstore
+ size
> r12
) {
749 msg
= "no room for blocked state";
753 /* Change the comm field on the MCA/INT task to include the pid that
754 * was interrupted, it makes for easier debugging. If that pid was 0
755 * (swapper or nested MCA/INIT) then use the start of the previous comm
756 * field suffixed with its cpu.
758 if (previous_current
->pid
)
759 snprintf(comm
, sizeof(comm
), "%s %d",
760 current
->comm
, previous_current
->pid
);
763 if ((p
= strchr(previous_current
->comm
, ' ')))
764 l
= p
- previous_current
->comm
;
766 l
= strlen(previous_current
->comm
);
767 snprintf(comm
, sizeof(comm
), "%s %*s %d",
768 current
->comm
, l
, previous_current
->comm
,
769 task_thread_info(previous_current
)->cpu
);
771 memcpy(current
->comm
, comm
, sizeof(current
->comm
));
773 /* Make the original task look blocked. First stack a struct pt_regs,
774 * describing the state at the time of interrupt. mca_asm.S built a
775 * partial pt_regs, copy it and fill in the blanks using minstate.
777 p
= (char *)r12
- sizeof(*regs
);
778 old_regs
= (struct pt_regs
*)p
;
779 memcpy(old_regs
, regs
, sizeof(*regs
));
780 /* If ipsr.ic then use pmsa_{iip,ipsr,ifs}, else use
781 * pmsa_{xip,xpsr,xfs}
783 if (ia64_psr(regs
)->ic
) {
784 old_regs
->cr_iip
= ms
->pmsa_iip
;
785 old_regs
->cr_ipsr
= ms
->pmsa_ipsr
;
786 old_regs
->cr_ifs
= ms
->pmsa_ifs
;
788 old_regs
->cr_iip
= ms
->pmsa_xip
;
789 old_regs
->cr_ipsr
= ms
->pmsa_xpsr
;
790 old_regs
->cr_ifs
= ms
->pmsa_xfs
;
792 old_regs
->pr
= ms
->pmsa_pr
;
793 old_regs
->b0
= ms
->pmsa_br0
;
794 old_regs
->loadrs
= loadrs
;
795 old_regs
->ar_rsc
= ms
->pmsa_rsc
;
796 old_unat
= old_regs
->ar_unat
;
797 copy_reg(&ms
->pmsa_gr
[1-1], ms
->pmsa_nat_bits
, &old_regs
->r1
, &old_unat
);
798 copy_reg(&ms
->pmsa_gr
[2-1], ms
->pmsa_nat_bits
, &old_regs
->r2
, &old_unat
);
799 copy_reg(&ms
->pmsa_gr
[3-1], ms
->pmsa_nat_bits
, &old_regs
->r3
, &old_unat
);
800 copy_reg(&ms
->pmsa_gr
[8-1], ms
->pmsa_nat_bits
, &old_regs
->r8
, &old_unat
);
801 copy_reg(&ms
->pmsa_gr
[9-1], ms
->pmsa_nat_bits
, &old_regs
->r9
, &old_unat
);
802 copy_reg(&ms
->pmsa_gr
[10-1], ms
->pmsa_nat_bits
, &old_regs
->r10
, &old_unat
);
803 copy_reg(&ms
->pmsa_gr
[11-1], ms
->pmsa_nat_bits
, &old_regs
->r11
, &old_unat
);
804 copy_reg(&ms
->pmsa_gr
[12-1], ms
->pmsa_nat_bits
, &old_regs
->r12
, &old_unat
);
805 copy_reg(&ms
->pmsa_gr
[13-1], ms
->pmsa_nat_bits
, &old_regs
->r13
, &old_unat
);
806 copy_reg(&ms
->pmsa_gr
[14-1], ms
->pmsa_nat_bits
, &old_regs
->r14
, &old_unat
);
807 copy_reg(&ms
->pmsa_gr
[15-1], ms
->pmsa_nat_bits
, &old_regs
->r15
, &old_unat
);
808 if (ia64_psr(old_regs
)->bn
)
809 bank
= ms
->pmsa_bank1_gr
;
811 bank
= ms
->pmsa_bank0_gr
;
812 copy_reg(&bank
[16-16], ms
->pmsa_nat_bits
, &old_regs
->r16
, &old_unat
);
813 copy_reg(&bank
[17-16], ms
->pmsa_nat_bits
, &old_regs
->r17
, &old_unat
);
814 copy_reg(&bank
[18-16], ms
->pmsa_nat_bits
, &old_regs
->r18
, &old_unat
);
815 copy_reg(&bank
[19-16], ms
->pmsa_nat_bits
, &old_regs
->r19
, &old_unat
);
816 copy_reg(&bank
[20-16], ms
->pmsa_nat_bits
, &old_regs
->r20
, &old_unat
);
817 copy_reg(&bank
[21-16], ms
->pmsa_nat_bits
, &old_regs
->r21
, &old_unat
);
818 copy_reg(&bank
[22-16], ms
->pmsa_nat_bits
, &old_regs
->r22
, &old_unat
);
819 copy_reg(&bank
[23-16], ms
->pmsa_nat_bits
, &old_regs
->r23
, &old_unat
);
820 copy_reg(&bank
[24-16], ms
->pmsa_nat_bits
, &old_regs
->r24
, &old_unat
);
821 copy_reg(&bank
[25-16], ms
->pmsa_nat_bits
, &old_regs
->r25
, &old_unat
);
822 copy_reg(&bank
[26-16], ms
->pmsa_nat_bits
, &old_regs
->r26
, &old_unat
);
823 copy_reg(&bank
[27-16], ms
->pmsa_nat_bits
, &old_regs
->r27
, &old_unat
);
824 copy_reg(&bank
[28-16], ms
->pmsa_nat_bits
, &old_regs
->r28
, &old_unat
);
825 copy_reg(&bank
[29-16], ms
->pmsa_nat_bits
, &old_regs
->r29
, &old_unat
);
826 copy_reg(&bank
[30-16], ms
->pmsa_nat_bits
, &old_regs
->r30
, &old_unat
);
827 copy_reg(&bank
[31-16], ms
->pmsa_nat_bits
, &old_regs
->r31
, &old_unat
);
829 /* Next stack a struct switch_stack. mca_asm.S built a partial
830 * switch_stack, copy it and fill in the blanks using pt_regs and
833 * In the synthesized switch_stack, b0 points to ia64_leave_kernel,
834 * ar.pfs is set to 0.
836 * unwind.c::unw_unwind() does special processing for interrupt frames.
837 * It checks if the PRED_NON_SYSCALL predicate is set, if the predicate
838 * is clear then unw_unwind() does _not_ adjust bsp over pt_regs. Not
839 * that this is documented, of course. Set PRED_NON_SYSCALL in the
840 * switch_stack on the original stack so it will unwind correctly when
841 * unwind.c reads pt_regs.
843 * thread.ksp is updated to point to the synthesized switch_stack.
845 p
-= sizeof(struct switch_stack
);
846 old_sw
= (struct switch_stack
*)p
;
847 memcpy(old_sw
, sw
, sizeof(*sw
));
848 old_sw
->caller_unat
= old_unat
;
849 old_sw
->ar_fpsr
= old_regs
->ar_fpsr
;
850 copy_reg(&ms
->pmsa_gr
[4-1], ms
->pmsa_nat_bits
, &old_sw
->r4
, &old_unat
);
851 copy_reg(&ms
->pmsa_gr
[5-1], ms
->pmsa_nat_bits
, &old_sw
->r5
, &old_unat
);
852 copy_reg(&ms
->pmsa_gr
[6-1], ms
->pmsa_nat_bits
, &old_sw
->r6
, &old_unat
);
853 copy_reg(&ms
->pmsa_gr
[7-1], ms
->pmsa_nat_bits
, &old_sw
->r7
, &old_unat
);
854 old_sw
->b0
= (u64
)ia64_leave_kernel
;
855 old_sw
->b1
= ms
->pmsa_br1
;
857 old_sw
->ar_unat
= old_unat
;
858 old_sw
->pr
= old_regs
->pr
| (1UL << PRED_NON_SYSCALL
);
859 previous_current
->thread
.ksp
= (u64
)p
- 16;
861 /* Finally copy the original stack's registers back to its RBS.
862 * Registers from ar.bspstore through ar.bsp at the time of the event
863 * are in the current RBS, copy them back to the original stack. The
864 * copy must be done register by register because the original bspstore
865 * and the current one have different alignments, so the saved RNAT
866 * data occurs at different places.
868 * mca_asm does cover, so the old_bsp already includes all registers at
869 * the time of MCA/INIT. It also does flushrs, so all registers before
870 * this function have been written to backing store on the MCA/INIT
873 new_rnat
= ia64_get_rnat(ia64_rse_rnat_addr(new_bspstore
));
874 old_rnat
= regs
->ar_rnat
;
876 if (ia64_rse_is_rnat_slot(new_bspstore
)) {
877 new_rnat
= ia64_get_rnat(new_bspstore
++);
879 if (ia64_rse_is_rnat_slot(old_bspstore
)) {
880 *old_bspstore
++ = old_rnat
;
883 nat
= (new_rnat
>> ia64_rse_slot_num(new_bspstore
)) & 1UL;
884 old_rnat
&= ~(1UL << ia64_rse_slot_num(old_bspstore
));
885 old_rnat
|= (nat
<< ia64_rse_slot_num(old_bspstore
));
886 *old_bspstore
++ = *new_bspstore
++;
888 old_sw
->ar_bspstore
= (unsigned long)old_bspstore
;
889 old_sw
->ar_rnat
= old_rnat
;
891 sos
->prev_task
= previous_current
;
892 return previous_current
;
895 printk(KERN_INFO
"cpu %d, %s %s, original stack not modified\n",
896 smp_processor_id(), type
, msg
);
897 return previous_current
;
900 /* The monarch/slave interaction is based on monarch_cpu and requires that all
901 * slaves have entered rendezvous before the monarch leaves. If any cpu has
902 * not entered rendezvous yet then wait a bit. The assumption is that any
903 * slave that has not rendezvoused after a reasonable time is never going to do
904 * so. In this context, slave includes cpus that respond to the MCA rendezvous
905 * interrupt, as well as cpus that receive the INIT slave event.
909 ia64_wait_for_slaves(int monarch
)
912 for_each_online_cpu(c
) {
915 if (ia64_mc_info
.imi_rendez_checkin
[c
] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE
) {
916 udelay(1000); /* short wait first */
923 for_each_online_cpu(c
) {
926 if (ia64_mc_info
.imi_rendez_checkin
[c
] == IA64_MCA_RENDEZ_CHECKIN_NOTDONE
) {
927 udelay(5*1000000); /* wait 5 seconds for slaves (arbitrary) */
936 * This is uncorrectable machine check handler called from OS_MCA
937 * dispatch code which is in turn called from SAL_CHECK().
938 * This is the place where the core of OS MCA handling is done.
939 * Right now the logs are extracted and displayed in a well-defined
940 * format. This handler code is supposed to be run only on the
941 * monarch processor. Once the monarch is done with MCA handling
942 * further MCA logging is enabled by clearing logs.
943 * Monarch also has the duty of sending wakeup-IPIs to pull the
944 * slave processors out of rendezvous spinloop.
947 ia64_mca_handler(struct pt_regs
*regs
, struct switch_stack
*sw
,
948 struct ia64_sal_os_state
*sos
)
950 pal_processor_state_info_t
*psp
= (pal_processor_state_info_t
*)
951 &sos
->proc_state_param
;
952 int recover
, cpu
= smp_processor_id();
953 task_t
*previous_current
;
955 oops_in_progress
= 1; /* FIXME: make printk NMI/MCA/INIT safe */
956 previous_current
= ia64_mca_modify_original_stack(regs
, sw
, sos
, "MCA");
958 if (notify_die(DIE_MCA_MONARCH_ENTER
, "MCA", regs
, 0, 0, 0)
960 ia64_mca_spin(__FUNCTION__
);
961 ia64_wait_for_slaves(cpu
);
963 /* Wakeup all the processors which are spinning in the rendezvous loop.
964 * They will leave SAL, then spin in the OS with interrupts disabled
965 * until this monarch cpu leaves the MCA handler. That gets control
966 * back to the OS so we can backtrace the other cpus, backtrace when
967 * spinning in SAL does not work.
969 ia64_mca_wakeup_all();
970 if (notify_die(DIE_MCA_MONARCH_PROCESS
, "MCA", regs
, 0, 0, 0)
972 ia64_mca_spin(__FUNCTION__
);
974 /* Get the MCA error record and log it */
975 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_MCA
);
977 /* TLB error is only exist in this SAL error record */
978 recover
= (psp
->tc
&& !(psp
->cc
|| psp
->bc
|| psp
->rc
|| psp
->uc
))
979 /* other error recovery */
980 || (ia64_mca_ucmc_extension
981 && ia64_mca_ucmc_extension(
982 IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA
),
986 sal_log_record_header_t
*rh
= IA64_LOG_CURR_BUFFER(SAL_INFO_TYPE_MCA
);
987 rh
->severity
= sal_log_severity_corrected
;
988 ia64_sal_clear_state_info(SAL_INFO_TYPE_MCA
);
989 sos
->os_status
= IA64_MCA_CORRECTED
;
991 if (notify_die(DIE_MCA_MONARCH_LEAVE
, "MCA", regs
, 0, 0, recover
)
993 ia64_mca_spin(__FUNCTION__
);
995 set_curr_task(cpu
, previous_current
);
999 static DECLARE_WORK(cmc_disable_work
, ia64_mca_cmc_vector_disable_keventd
, NULL
);
1000 static DECLARE_WORK(cmc_enable_work
, ia64_mca_cmc_vector_enable_keventd
, NULL
);
1003 * ia64_mca_cmc_int_handler
1005 * This is corrected machine check interrupt handler.
1006 * Right now the logs are extracted and displayed in a well-defined
1011 * client data arg ptr
1012 * saved registers ptr
1018 ia64_mca_cmc_int_handler(int cmc_irq
, void *arg
, struct pt_regs
*ptregs
)
1020 static unsigned long cmc_history
[CMC_HISTORY_LENGTH
];
1022 static DEFINE_SPINLOCK(cmc_history_lock
);
1024 IA64_MCA_DEBUG("%s: received interrupt vector = %#x on CPU %d\n",
1025 __FUNCTION__
, cmc_irq
, smp_processor_id());
1027 /* SAL spec states this should run w/ interrupts enabled */
1030 /* Get the CMC error record and log it */
1031 ia64_mca_log_sal_error_record(SAL_INFO_TYPE_CMC
);
1033 spin_lock(&cmc_history_lock
);
1034 if (!cmc_polling_enabled
) {
1035 int i
, count
= 1; /* we know 1 happened now */
1036 unsigned long now
= jiffies
;
1038 for (i
= 0; i
< CMC_HISTORY_LENGTH
; i
++) {
1039 if (now
- cmc_history
[i
] <= HZ
)
1043 IA64_MCA_DEBUG(KERN_INFO
"CMC threshold %d/%d\n", count
, CMC_HISTORY_LENGTH
);
1044 if (count
>= CMC_HISTORY_LENGTH
) {
1046 cmc_polling_enabled
= 1;
1047 spin_unlock(&cmc_history_lock
);
1048 /* If we're being hit with CMC interrupts, we won't
1049 * ever execute the schedule_work() below. Need to
1050 * disable CMC interrupts on this processor now.
1052 ia64_mca_cmc_vector_disable(NULL
);
1053 schedule_work(&cmc_disable_work
);
1056 * Corrected errors will still be corrected, but
1057 * make sure there's a log somewhere that indicates
1058 * something is generating more than we can handle.
1060 printk(KERN_WARNING
"WARNING: Switching to polling CMC handler; error records may be lost\n");
1062 mod_timer(&cmc_poll_timer
, jiffies
+ CMC_POLL_INTERVAL
);
1064 /* lock already released, get out now */
1067 cmc_history
[index
++] = now
;
1068 if (index
== CMC_HISTORY_LENGTH
)
1072 spin_unlock(&cmc_history_lock
);
1077 * ia64_mca_cmc_int_caller
1079 * Triggered by sw interrupt from CMC polling routine. Calls
1080 * real interrupt handler and either triggers a sw interrupt
1081 * on the next cpu or does cleanup at the end.
1085 * client data arg ptr
1086 * saved registers ptr
1091 ia64_mca_cmc_int_caller(int cmc_irq
, void *arg
, struct pt_regs
*ptregs
)
1093 static int start_count
= -1;
1096 cpuid
= smp_processor_id();
1098 /* If first cpu, update count */
1099 if (start_count
== -1)
1100 start_count
= IA64_LOG_COUNT(SAL_INFO_TYPE_CMC
);
1102 ia64_mca_cmc_int_handler(cmc_irq
, arg
, ptregs
);
1104 for (++cpuid
; cpuid
< NR_CPUS
&& !cpu_online(cpuid
) ; cpuid
++);
1106 if (cpuid
< NR_CPUS
) {
1107 platform_send_ipi(cpuid
, IA64_CMCP_VECTOR
, IA64_IPI_DM_INT
, 0);
1109 /* If no log record, switch out of polling mode */
1110 if (start_count
== IA64_LOG_COUNT(SAL_INFO_TYPE_CMC
)) {
1112 printk(KERN_WARNING
"Returning to interrupt driven CMC handler\n");
1113 schedule_work(&cmc_enable_work
);
1114 cmc_polling_enabled
= 0;
1118 mod_timer(&cmc_poll_timer
, jiffies
+ CMC_POLL_INTERVAL
);
1130 * Poll for Corrected Machine Checks (CMCs)
1132 * Inputs : dummy(unused)
1137 ia64_mca_cmc_poll (unsigned long dummy
)
1139 /* Trigger a CMC interrupt cascade */
1140 platform_send_ipi(first_cpu(cpu_online_map
), IA64_CMCP_VECTOR
, IA64_IPI_DM_INT
, 0);
1144 * ia64_mca_cpe_int_caller
1146 * Triggered by sw interrupt from CPE polling routine. Calls
1147 * real interrupt handler and either triggers a sw interrupt
1148 * on the next cpu or does cleanup at the end.
1152 * client data arg ptr
1153 * saved registers ptr
1160 ia64_mca_cpe_int_caller(int cpe_irq
, void *arg
, struct pt_regs
*ptregs
)
1162 static int start_count
= -1;
1163 static int poll_time
= MIN_CPE_POLL_INTERVAL
;
1166 cpuid
= smp_processor_id();
1168 /* If first cpu, update count */
1169 if (start_count
== -1)
1170 start_count
= IA64_LOG_COUNT(SAL_INFO_TYPE_CPE
);
1172 ia64_mca_cpe_int_handler(cpe_irq
, arg
, ptregs
);
1174 for (++cpuid
; cpuid
< NR_CPUS
&& !cpu_online(cpuid
) ; cpuid
++);
1176 if (cpuid
< NR_CPUS
) {
1177 platform_send_ipi(cpuid
, IA64_CPEP_VECTOR
, IA64_IPI_DM_INT
, 0);
1180 * If a log was recorded, increase our polling frequency,
1181 * otherwise, backoff or return to interrupt mode.
1183 if (start_count
!= IA64_LOG_COUNT(SAL_INFO_TYPE_CPE
)) {
1184 poll_time
= max(MIN_CPE_POLL_INTERVAL
, poll_time
/ 2);
1185 } else if (cpe_vector
< 0) {
1186 poll_time
= min(MAX_CPE_POLL_INTERVAL
, poll_time
* 2);
1188 poll_time
= MIN_CPE_POLL_INTERVAL
;
1190 printk(KERN_WARNING
"Returning to interrupt driven CPE handler\n");
1191 enable_irq(local_vector_to_irq(IA64_CPE_VECTOR
));
1192 cpe_poll_enabled
= 0;
1195 if (cpe_poll_enabled
)
1196 mod_timer(&cpe_poll_timer
, jiffies
+ poll_time
);
1206 * Poll for Corrected Platform Errors (CPEs), trigger interrupt
1207 * on first cpu, from there it will trickle through all the cpus.
1209 * Inputs : dummy(unused)
1214 ia64_mca_cpe_poll (unsigned long dummy
)
1216 /* Trigger a CPE interrupt cascade */
1217 platform_send_ipi(first_cpu(cpu_online_map
), IA64_CPEP_VECTOR
, IA64_IPI_DM_INT
, 0);
1220 #endif /* CONFIG_ACPI */
1223 default_monarch_init_process(struct notifier_block
*self
, unsigned long val
, void *data
)
1226 struct task_struct
*g
, *t
;
1227 if (val
!= DIE_INIT_MONARCH_PROCESS
)
1229 printk(KERN_ERR
"Processes interrupted by INIT -");
1230 for_each_online_cpu(c
) {
1231 struct ia64_sal_os_state
*s
;
1232 t
= __va(__per_cpu_mca
[c
] + IA64_MCA_CPU_INIT_STACK_OFFSET
);
1233 s
= (struct ia64_sal_os_state
*)((char *)t
+ MCA_SOS_OFFSET
);
1237 printk(" %d", g
->pid
);
1239 printk(" %d (cpu %d task 0x%p)", g
->pid
, task_cpu(g
), g
);
1243 if (read_trylock(&tasklist_lock
)) {
1244 do_each_thread (g
, t
) {
1245 printk("\nBacktrace of pid %d (%s)\n", t
->pid
, t
->comm
);
1246 show_stack(t
, NULL
);
1247 } while_each_thread (g
, t
);
1248 read_unlock(&tasklist_lock
);
1254 * C portion of the OS INIT handler
1256 * Called from ia64_os_init_dispatch
1258 * Inputs: pointer to pt_regs where processor info was saved. SAL/OS state for
1259 * this event. This code is used for both monarch and slave INIT events, see
1262 * All INIT events switch to the INIT stack and change the previous process to
1263 * blocked status. If one of the INIT events is the monarch then we are
1264 * probably processing the nmi button/command. Use the monarch cpu to dump all
1265 * the processes. The slave INIT events all spin until the monarch cpu
1266 * returns. We can also get INIT slave events for MCA, in which case the MCA
1267 * process is the monarch.
1271 ia64_init_handler(struct pt_regs
*regs
, struct switch_stack
*sw
,
1272 struct ia64_sal_os_state
*sos
)
1274 static atomic_t slaves
;
1275 static atomic_t monarchs
;
1276 task_t
*previous_current
;
1277 int cpu
= smp_processor_id();
1279 oops_in_progress
= 1; /* FIXME: make printk NMI/MCA/INIT safe */
1280 console_loglevel
= 15; /* make sure printks make it to console */
1282 printk(KERN_INFO
"Entered OS INIT handler. PSP=%lx cpu=%d monarch=%ld\n",
1283 sos
->proc_state_param
, cpu
, sos
->monarch
);
1284 salinfo_log_wakeup(SAL_INFO_TYPE_INIT
, NULL
, 0, 0);
1286 previous_current
= ia64_mca_modify_original_stack(regs
, sw
, sos
, "INIT");
1287 sos
->os_status
= IA64_INIT_RESUME
;
1289 /* FIXME: Workaround for broken proms that drive all INIT events as
1290 * slaves. The last slave that enters is promoted to be a monarch.
1291 * Remove this code in September 2006, that gives platforms a year to
1292 * fix their proms and get their customers updated.
1294 if (!sos
->monarch
&& atomic_add_return(1, &slaves
) == num_online_cpus()) {
1295 printk(KERN_WARNING
"%s: Promoting cpu %d to monarch.\n",
1297 atomic_dec(&slaves
);
1301 /* FIXME: Workaround for broken proms that drive all INIT events as
1302 * monarchs. Second and subsequent monarchs are demoted to slaves.
1303 * Remove this code in September 2006, that gives platforms a year to
1304 * fix their proms and get their customers updated.
1306 if (sos
->monarch
&& atomic_add_return(1, &monarchs
) > 1) {
1307 printk(KERN_WARNING
"%s: Demoting cpu %d to slave.\n",
1309 atomic_dec(&monarchs
);
1313 if (!sos
->monarch
) {
1314 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_INIT
;
1315 while (monarch_cpu
== -1)
1316 cpu_relax(); /* spin until monarch enters */
1317 if (notify_die(DIE_INIT_SLAVE_ENTER
, "INIT", regs
, 0, 0, 0)
1319 ia64_mca_spin(__FUNCTION__
);
1320 if (notify_die(DIE_INIT_SLAVE_PROCESS
, "INIT", regs
, 0, 0, 0)
1322 ia64_mca_spin(__FUNCTION__
);
1323 while (monarch_cpu
!= -1)
1324 cpu_relax(); /* spin until monarch leaves */
1325 if (notify_die(DIE_INIT_SLAVE_LEAVE
, "INIT", regs
, 0, 0, 0)
1327 ia64_mca_spin(__FUNCTION__
);
1328 printk("Slave on cpu %d returning to normal service.\n", cpu
);
1329 set_curr_task(cpu
, previous_current
);
1330 ia64_mc_info
.imi_rendez_checkin
[cpu
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
1331 atomic_dec(&slaves
);
1336 if (notify_die(DIE_INIT_MONARCH_ENTER
, "INIT", regs
, 0, 0, 0)
1338 ia64_mca_spin(__FUNCTION__
);
1341 * Wait for a bit. On some machines (e.g., HP's zx2000 and zx6000, INIT can be
1342 * generated via the BMC's command-line interface, but since the console is on the
1343 * same serial line, the user will need some time to switch out of the BMC before
1346 printk("Delaying for 5 seconds...\n");
1348 ia64_wait_for_slaves(cpu
);
1349 /* If nobody intercepts DIE_INIT_MONARCH_PROCESS then we drop through
1350 * to default_monarch_init_process() above and just print all the
1353 if (notify_die(DIE_INIT_MONARCH_PROCESS
, "INIT", regs
, 0, 0, 0)
1355 ia64_mca_spin(__FUNCTION__
);
1356 if (notify_die(DIE_INIT_MONARCH_LEAVE
, "INIT", regs
, 0, 0, 0)
1358 ia64_mca_spin(__FUNCTION__
);
1359 printk("\nINIT dump complete. Monarch on cpu %d returning to normal service.\n", cpu
);
1360 atomic_dec(&monarchs
);
1361 set_curr_task(cpu
, previous_current
);
1367 ia64_mca_disable_cpe_polling(char *str
)
1369 cpe_poll_enabled
= 0;
1373 __setup("disable_cpe_poll", ia64_mca_disable_cpe_polling
);
1375 static struct irqaction cmci_irqaction
= {
1376 .handler
= ia64_mca_cmc_int_handler
,
1377 .flags
= SA_INTERRUPT
,
1381 static struct irqaction cmcp_irqaction
= {
1382 .handler
= ia64_mca_cmc_int_caller
,
1383 .flags
= SA_INTERRUPT
,
1387 static struct irqaction mca_rdzv_irqaction
= {
1388 .handler
= ia64_mca_rendez_int_handler
,
1389 .flags
= SA_INTERRUPT
,
1393 static struct irqaction mca_wkup_irqaction
= {
1394 .handler
= ia64_mca_wakeup_int_handler
,
1395 .flags
= SA_INTERRUPT
,
1400 static struct irqaction mca_cpe_irqaction
= {
1401 .handler
= ia64_mca_cpe_int_handler
,
1402 .flags
= SA_INTERRUPT
,
1406 static struct irqaction mca_cpep_irqaction
= {
1407 .handler
= ia64_mca_cpe_int_caller
,
1408 .flags
= SA_INTERRUPT
,
1411 #endif /* CONFIG_ACPI */
1413 /* Minimal format of the MCA/INIT stacks. The pseudo processes that run on
1414 * these stacks can never sleep, they cannot return from the kernel to user
1415 * space, they do not appear in a normal ps listing. So there is no need to
1416 * format most of the fields.
1420 format_mca_init_stack(void *mca_data
, unsigned long offset
,
1421 const char *type
, int cpu
)
1423 struct task_struct
*p
= (struct task_struct
*)((char *)mca_data
+ offset
);
1424 struct thread_info
*ti
;
1425 memset(p
, 0, KERNEL_STACK_SIZE
);
1426 ti
= task_thread_info(p
);
1427 ti
->flags
= _TIF_MCA_INIT
;
1428 ti
->preempt_count
= 1;
1431 p
->thread_info
= ti
;
1432 p
->state
= TASK_UNINTERRUPTIBLE
;
1433 __set_bit(cpu
, &p
->cpus_allowed
);
1434 INIT_LIST_HEAD(&p
->tasks
);
1435 p
->parent
= p
->real_parent
= p
->group_leader
= p
;
1436 INIT_LIST_HEAD(&p
->children
);
1437 INIT_LIST_HEAD(&p
->sibling
);
1438 strncpy(p
->comm
, type
, sizeof(p
->comm
)-1);
1441 /* Do per-CPU MCA-related initialization. */
1444 ia64_mca_cpu_init(void *cpu_data
)
1448 if (smp_processor_id() == 0) {
1452 mca_data
= alloc_bootmem(sizeof(struct ia64_mca_cpu
)
1453 * NR_CPUS
+ KERNEL_STACK_SIZE
);
1454 mca_data
= (void *)(((unsigned long)mca_data
+
1455 KERNEL_STACK_SIZE
- 1) &
1456 (-KERNEL_STACK_SIZE
));
1457 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1458 format_mca_init_stack(mca_data
,
1459 offsetof(struct ia64_mca_cpu
, mca_stack
),
1461 format_mca_init_stack(mca_data
,
1462 offsetof(struct ia64_mca_cpu
, init_stack
),
1464 __per_cpu_mca
[cpu
] = __pa(mca_data
);
1465 mca_data
+= sizeof(struct ia64_mca_cpu
);
1470 * The MCA info structure was allocated earlier and its
1471 * physical address saved in __per_cpu_mca[cpu]. Copy that
1472 * address * to ia64_mca_data so we can access it as a per-CPU
1475 __get_cpu_var(ia64_mca_data
) = __per_cpu_mca
[smp_processor_id()];
1478 * Stash away a copy of the PTE needed to map the per-CPU page.
1479 * We may need it during MCA recovery.
1481 __get_cpu_var(ia64_mca_per_cpu_pte
) =
1482 pte_val(mk_pte_phys(__pa(cpu_data
), PAGE_KERNEL
));
1485 * Also, stash away a copy of the PAL address and the PTE
1488 pal_vaddr
= efi_get_pal_addr();
1491 __get_cpu_var(ia64_mca_pal_base
) =
1492 GRANULEROUNDDOWN((unsigned long) pal_vaddr
);
1493 __get_cpu_var(ia64_mca_pal_pte
) = pte_val(mk_pte_phys(__pa(pal_vaddr
),
1500 * Do all the system level mca specific initialization.
1502 * 1. Register spinloop and wakeup request interrupt vectors
1504 * 2. Register OS_MCA handler entry point
1506 * 3. Register OS_INIT handler entry point
1508 * 4. Initialize MCA/CMC/INIT related log buffers maintained by the OS.
1510 * Note that this initialization is done very early before some kernel
1511 * services are available.
1520 ia64_fptr_t
*init_hldlr_ptr_monarch
= (ia64_fptr_t
*)ia64_os_init_dispatch_monarch
;
1521 ia64_fptr_t
*init_hldlr_ptr_slave
= (ia64_fptr_t
*)ia64_os_init_dispatch_slave
;
1522 ia64_fptr_t
*mca_hldlr_ptr
= (ia64_fptr_t
*)ia64_os_mca_dispatch
;
1525 struct ia64_sal_retval isrv
;
1526 u64 timeout
= IA64_MCA_RENDEZ_TIMEOUT
; /* platform specific */
1527 static struct notifier_block default_init_monarch_nb
= {
1528 .notifier_call
= default_monarch_init_process
,
1529 .priority
= 0/* we need to notified last */
1532 IA64_MCA_DEBUG("%s: begin\n", __FUNCTION__
);
1534 /* Clear the Rendez checkin flag for all cpus */
1535 for(i
= 0 ; i
< NR_CPUS
; i
++)
1536 ia64_mc_info
.imi_rendez_checkin
[i
] = IA64_MCA_RENDEZ_CHECKIN_NOTDONE
;
1539 * Register the rendezvous spinloop and wakeup mechanism with SAL
1542 /* Register the rendezvous interrupt vector with SAL */
1544 isrv
= ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_INT
,
1545 SAL_MC_PARAM_MECHANISM_INT
,
1546 IA64_MCA_RENDEZ_VECTOR
,
1548 SAL_MC_PARAM_RZ_ALWAYS
);
1553 printk(KERN_INFO
"Increasing MCA rendezvous timeout from "
1554 "%ld to %ld milliseconds\n", timeout
, isrv
.v0
);
1558 printk(KERN_ERR
"Failed to register rendezvous interrupt "
1559 "with SAL (status %ld)\n", rc
);
1563 /* Register the wakeup interrupt vector with SAL */
1564 isrv
= ia64_sal_mc_set_params(SAL_MC_PARAM_RENDEZ_WAKEUP
,
1565 SAL_MC_PARAM_MECHANISM_INT
,
1566 IA64_MCA_WAKEUP_VECTOR
,
1570 printk(KERN_ERR
"Failed to register wakeup interrupt with SAL "
1571 "(status %ld)\n", rc
);
1575 IA64_MCA_DEBUG("%s: registered MCA rendezvous spinloop and wakeup mech.\n", __FUNCTION__
);
1577 ia64_mc_info
.imi_mca_handler
= ia64_tpa(mca_hldlr_ptr
->fp
);
1579 * XXX - disable SAL checksum by setting size to 0; should be
1580 * ia64_tpa(ia64_os_mca_dispatch_end) - ia64_tpa(ia64_os_mca_dispatch);
1582 ia64_mc_info
.imi_mca_handler_size
= 0;
1584 /* Register the os mca handler with SAL */
1585 if ((rc
= ia64_sal_set_vectors(SAL_VECTOR_OS_MCA
,
1586 ia64_mc_info
.imi_mca_handler
,
1587 ia64_tpa(mca_hldlr_ptr
->gp
),
1588 ia64_mc_info
.imi_mca_handler_size
,
1591 printk(KERN_ERR
"Failed to register OS MCA handler with SAL "
1592 "(status %ld)\n", rc
);
1596 IA64_MCA_DEBUG("%s: registered OS MCA handler with SAL at 0x%lx, gp = 0x%lx\n", __FUNCTION__
,
1597 ia64_mc_info
.imi_mca_handler
, ia64_tpa(mca_hldlr_ptr
->gp
));
1600 * XXX - disable SAL checksum by setting size to 0, should be
1601 * size of the actual init handler in mca_asm.S.
1603 ia64_mc_info
.imi_monarch_init_handler
= ia64_tpa(init_hldlr_ptr_monarch
->fp
);
1604 ia64_mc_info
.imi_monarch_init_handler_size
= 0;
1605 ia64_mc_info
.imi_slave_init_handler
= ia64_tpa(init_hldlr_ptr_slave
->fp
);
1606 ia64_mc_info
.imi_slave_init_handler_size
= 0;
1608 IA64_MCA_DEBUG("%s: OS INIT handler at %lx\n", __FUNCTION__
,
1609 ia64_mc_info
.imi_monarch_init_handler
);
1611 /* Register the os init handler with SAL */
1612 if ((rc
= ia64_sal_set_vectors(SAL_VECTOR_OS_INIT
,
1613 ia64_mc_info
.imi_monarch_init_handler
,
1614 ia64_tpa(ia64_getreg(_IA64_REG_GP
)),
1615 ia64_mc_info
.imi_monarch_init_handler_size
,
1616 ia64_mc_info
.imi_slave_init_handler
,
1617 ia64_tpa(ia64_getreg(_IA64_REG_GP
)),
1618 ia64_mc_info
.imi_slave_init_handler_size
)))
1620 printk(KERN_ERR
"Failed to register m/s INIT handlers with SAL "
1621 "(status %ld)\n", rc
);
1624 if (register_die_notifier(&default_init_monarch_nb
)) {
1625 printk(KERN_ERR
"Failed to register default monarch INIT process\n");
1629 IA64_MCA_DEBUG("%s: registered OS INIT handler with SAL\n", __FUNCTION__
);
1632 * Configure the CMCI/P vector and handler. Interrupts for CMC are
1633 * per-processor, so AP CMC interrupts are setup in smp_callin() (smpboot.c).
1635 register_percpu_irq(IA64_CMC_VECTOR
, &cmci_irqaction
);
1636 register_percpu_irq(IA64_CMCP_VECTOR
, &cmcp_irqaction
);
1637 ia64_mca_cmc_vector_setup(); /* Setup vector on BSP */
1639 /* Setup the MCA rendezvous interrupt vector */
1640 register_percpu_irq(IA64_MCA_RENDEZ_VECTOR
, &mca_rdzv_irqaction
);
1642 /* Setup the MCA wakeup interrupt vector */
1643 register_percpu_irq(IA64_MCA_WAKEUP_VECTOR
, &mca_wkup_irqaction
);
1646 /* Setup the CPEI/P handler */
1647 register_percpu_irq(IA64_CPEP_VECTOR
, &mca_cpep_irqaction
);
1650 /* Initialize the areas set aside by the OS to buffer the
1651 * platform/processor error states for MCA/INIT/CMC
1654 ia64_log_init(SAL_INFO_TYPE_MCA
);
1655 ia64_log_init(SAL_INFO_TYPE_INIT
);
1656 ia64_log_init(SAL_INFO_TYPE_CMC
);
1657 ia64_log_init(SAL_INFO_TYPE_CPE
);
1660 printk(KERN_INFO
"MCA related initialization done\n");
1664 * ia64_mca_late_init
1666 * Opportunity to setup things that require initialization later
1667 * than ia64_mca_init. Setup a timer to poll for CPEs if the
1668 * platform doesn't support an interrupt driven mechanism.
1674 ia64_mca_late_init(void)
1679 /* Setup the CMCI/P vector and handler */
1680 init_timer(&cmc_poll_timer
);
1681 cmc_poll_timer
.function
= ia64_mca_cmc_poll
;
1683 /* Unmask/enable the vector */
1684 cmc_polling_enabled
= 0;
1685 schedule_work(&cmc_enable_work
);
1687 IA64_MCA_DEBUG("%s: CMCI/P setup and enabled.\n", __FUNCTION__
);
1690 /* Setup the CPEI/P vector and handler */
1691 cpe_vector
= acpi_request_vector(ACPI_INTERRUPT_CPEI
);
1692 init_timer(&cpe_poll_timer
);
1693 cpe_poll_timer
.function
= ia64_mca_cpe_poll
;
1699 if (cpe_vector
>= 0) {
1700 /* If platform supports CPEI, enable the irq. */
1701 cpe_poll_enabled
= 0;
1702 for (irq
= 0; irq
< NR_IRQS
; ++irq
)
1703 if (irq_to_vector(irq
) == cpe_vector
) {
1704 desc
= irq_descp(irq
);
1705 desc
->status
|= IRQ_PER_CPU
;
1706 setup_irq(irq
, &mca_cpe_irqaction
);
1708 ia64_mca_register_cpev(cpe_vector
);
1709 IA64_MCA_DEBUG("%s: CPEI/P setup and enabled.\n", __FUNCTION__
);
1711 /* If platform doesn't support CPEI, get the timer going. */
1712 if (cpe_poll_enabled
) {
1713 ia64_mca_cpe_poll(0UL);
1714 IA64_MCA_DEBUG("%s: CPEP setup and enabled.\n", __FUNCTION__
);
1723 device_initcall(ia64_mca_late_init
);