1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
4 specification and can be connected in various topologies to suit a particular
5 SoCs tracing needs. These trace components can generally be classified as
6 sinks, links and sources. Trace data produced by one or more sources flows
7 through the intermediate links connecting the source to the currently selected
8 sink. Each CoreSight component device should use these properties to describe
9 its hardware characteristcs.
11 * Required properties for all components *except* non-configurable replicators:
13 * compatible: These have to be supplemented with "arm,primecell" as
14 drivers are using the AMBA bus interface. Possible values include:
15 - "arm,coresight-etb10", "arm,primecell";
16 - "arm,coresight-tpiu", "arm,primecell";
17 - "arm,coresight-tmc", "arm,primecell";
18 - "arm,coresight-funnel", "arm,primecell";
19 - "arm,coresight-etm3x", "arm,primecell";
21 * reg: physical base address and length of the register
22 set(s) of the component.
24 * clocks: the clocks associated to this component.
26 * clock-names: the name of the clocks referenced by the code.
27 Since we are using the AMBA framework, the name of the clock
28 providing the interconnect should be "apb_pclk", and some
29 coresight blocks also have an additional clock "atclk", which
30 clocks the core of that coresight component. The latter clock
33 * port or ports: The representation of the component's port
34 layout using the generic DT graph presentation found in
37 * Required properties for devices that don't show up on the AMBA bus, such as
38 non-configurable replicators:
40 * compatible: Currently supported value is (note the absence of the
42 - "arm,coresight-replicator"
44 * port or ports: same as above.
46 * Optional properties for ETM/PTMs:
48 * arm,cp14: must be present if the system accesses ETM/PTM management
49 registers via co-processor 14.
51 * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
52 source is considered to belong to CPU0.
54 * Optional property for TMC:
56 * arm,buffer-size: size of contiguous buffer space for TMC ETR
57 (embedded trace router)
64 compatible = "arm,coresight-etb10", "arm,primecell";
65 reg = <0 0x20010000 0 0x1000>;
68 clock-names = "apb_pclk";
70 etb_in_port: endpoint@0 {
72 remote-endpoint = <&replicator_out_port0>;
78 compatible = "arm,coresight-tpiu", "arm,primecell";
79 reg = <0 0x20030000 0 0x1000>;
82 clock-names = "apb_pclk";
84 tpiu_in_port: endpoint@0 {
86 remote-endpoint = <&replicator_out_port1>;
93 /* non-configurable replicators don't show up on the
94 * AMBA bus. As such no need to add "arm,primecell".
96 compatible = "arm,coresight-replicator";
102 /* replicator output ports */
105 replicator_out_port0: endpoint {
106 remote-endpoint = <&etb_in_port>;
112 replicator_out_port1: endpoint {
113 remote-endpoint = <&tpiu_in_port>;
117 /* replicator input port */
120 replicator_in_port0: endpoint {
122 remote-endpoint = <&funnel_out_port0>;
129 compatible = "arm,coresight-funnel", "arm,primecell";
130 reg = <0 0x20040000 0 0x1000>;
132 clocks = <&oscclk6a>;
133 clock-names = "apb_pclk";
135 #address-cells = <1>;
138 /* funnel output port */
141 funnel_out_port0: endpoint {
143 <&replicator_in_port0>;
147 /* funnel input ports */
150 funnel_in_port0: endpoint {
152 remote-endpoint = <&ptm0_out_port>;
158 funnel_in_port1: endpoint {
160 remote-endpoint = <&ptm1_out_port>;
166 funnel_in_port2: endpoint {
168 remote-endpoint = <&etm0_out_port>;
177 compatible = "arm,coresight-etm3x", "arm,primecell";
178 reg = <0 0x2201c000 0 0x1000>;
181 clocks = <&oscclk6a>;
182 clock-names = "apb_pclk";
184 ptm0_out_port: endpoint {
185 remote-endpoint = <&funnel_in_port0>;
191 compatible = "arm,coresight-etm3x", "arm,primecell";
192 reg = <0 0x2201d000 0 0x1000>;
195 clocks = <&oscclk6a>;
196 clock-names = "apb_pclk";
198 ptm1_out_port: endpoint {
199 remote-endpoint = <&funnel_in_port1>;