arch/arm/mach-mvebu/coherency.c

   1 /*
   2  * Coherency fabric (Aurora) support for Armada 370, 375, 38x and XP
   3  * platforms.
   4  *
   5  * Copyright (C) 2012 Marvell
   6  *
   7  * Yehuda Yitschak <yehuday@marvell.com>
   8  * Gregory Clement <gregory.clement@free-electrons.com>
   9  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2.  This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  *
  15  * The Armada 370, 375, 38x and XP SOCs have a coherency fabric which is
  16  * responsible for ensuring hardware coherency between all CPUs and between
  17  * CPUs and I/O masters. This file initializes the coherency fabric and
  18  * supplies basic routines for configuring and controlling hardware coherency
  19  */
  20
  21 #define pr_fmt(fmt) "mvebu-coherency: " fmt
  22
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/of_address.h>
  26 #include <linux/io.h>
  27 #include <linux/smp.h>
  28 #include <linux/dma-mapping.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include <linux/mbus.h>
  32 #include <linux/pci.h>
  33 #include <asm/smp_plat.h>
  34 #include <asm/cacheflush.h>
  35 #include <asm/mach/map.h>
  36 #include <asm/dma-mapping.h>
  37 #include "coherency.h"
  38 #include "mvebu-soc-id.h"
  39
  40 unsigned long coherency_phys_base;
  41 void __iomem *coherency_base;
  42 static void __iomem *coherency_cpu_base;
  43 static void __iomem *cpu_config_base;
  44
  45 /* Coherency fabric registers */
  46 #define IO_SYNC_BARRIER_CTL_OFFSET                 0x0
  47
  48 enum {
  49         COHERENCY_FABRIC_TYPE_NONE,
  50         COHERENCY_FABRIC_TYPE_ARMADA_370_XP,
  51         COHERENCY_FABRIC_TYPE_ARMADA_375,
  52         COHERENCY_FABRIC_TYPE_ARMADA_380,
  53 };
  54
  55 static const struct of_device_id of_coherency_table[] = {
  56         {.compatible = "marvell,coherency-fabric",
  57          .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_370_XP },
  58         {.compatible = "marvell,armada-375-coherency-fabric",
  59          .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_375 },
  60         {.compatible = "marvell,armada-380-coherency-fabric",
  61          .data = (void *) COHERENCY_FABRIC_TYPE_ARMADA_380 },
  62         { /* end of list */ },
  63 };
  64
  65 /* Functions defined in coherency_ll.S */
  66 int ll_enable_coherency(void);
  67 void ll_add_cpu_to_smp_group(void);
  68
  69 #define CPU_CONFIG_SHARED_L2 BIT(16)
  70
  71 /*
  72  * Disable the "Shared L2 Present" bit in CPU Configuration register
  73  * on Armada XP.
  74  *
  75  * The "Shared L2 Present" bit affects the "level of coherence" value
  76  * in the clidr CP15 register.  Cache operation functions such as
  77  * "flush all" and "invalidate all" operate on all the cache levels
  78  * that included in the defined level of coherence. When HW I/O
  79  * coherency is used, this bit causes unnecessary flushes of the L2
  80  * cache.
  81  */
  82 static void armada_xp_clear_shared_l2(void)
  83 {
  84         u32 reg;
  85
  86         if (!cpu_config_base)
  87                 return;
  88
  89         reg = readl(cpu_config_base);
  90         reg &= ~CPU_CONFIG_SHARED_L2;
  91         writel(reg, cpu_config_base);
  92 }
  93
  94 static int mvebu_hwcc_notifier(struct notifier_block *nb,
  95                                unsigned long event, void *__dev)
  96 {
  97         struct device *dev = __dev;
  98
  99         if (event != BUS_NOTIFY_ADD_DEVICE)
 100                 return NOTIFY_DONE;
 101         set_dma_ops(dev, &arm_coherent_dma_ops);
 102
 103         return NOTIFY_OK;
 104 }
 105
 106 static struct notifier_block mvebu_hwcc_nb = {
 107         .notifier_call = mvebu_hwcc_notifier,
 108 };
 109
 110 static struct notifier_block mvebu_hwcc_pci_nb __maybe_unused = {
 111         .notifier_call = mvebu_hwcc_notifier,
 112 };
 113
 114 static int armada_xp_clear_l2_starting(unsigned int cpu)
 115 {
 116         armada_xp_clear_shared_l2();
 117         return 0;
 118 }
 119
 120 static void __init armada_370_coherency_init(struct device_node *np)
 121 {
 122         struct resource res;
 123         struct device_node *cpu_config_np;
 124
 125         of_address_to_resource(np, 0, &res);
 126         coherency_phys_base = res.start;
 127         /*
 128          * Ensure secondary CPUs will see the updated value,
 129          * which they read before they join the coherency
 130          * fabric, and therefore before they are coherent with
 131          * the boot CPU cache.
 132          */
 133         sync_cache_w(&coherency_phys_base);
 134         coherency_base = of_iomap(np, 0);
 135         coherency_cpu_base = of_iomap(np, 1);
 136
 137         cpu_config_np = of_find_compatible_node(NULL, NULL,
 138                                                 "marvell,armada-xp-cpu-config");
 139         if (!cpu_config_np)
 140                 goto exit;
 141
 142         cpu_config_base = of_iomap(cpu_config_np, 0);
 143         if (!cpu_config_base) {
 144                 of_node_put(cpu_config_np);
 145                 goto exit;
 146         }
 147
 148         of_node_put(cpu_config_np);
 149
 150         cpuhp_setup_state_nocalls(CPUHP_AP_ARM_MVEBU_COHERENCY,
 151                                   "arm/mvebu/coherency:starting",
 152                                   armada_xp_clear_l2_starting, NULL);
 153 exit:
 154         set_cpu_coherent();
 155 }
 156
 157 /*
 158  * This ioremap hook is used on Armada 375/38x to ensure that all MMIO
 159  * areas are mapped as MT_UNCACHED instead of MT_DEVICE. This is
 160  * needed for the HW I/O coherency mechanism to work properly without
 161  * deadlock.
 162  */
 163 static void __iomem *
 164 armada_wa_ioremap_caller(phys_addr_t phys_addr, size_t size,
 165                          unsigned int mtype, void *caller)
 166 {
 167         mtype = MT_UNCACHED;
 168         return __arm_ioremap_caller(phys_addr, size, mtype, caller);
 169 }
 170
 171 static void __init armada_375_380_coherency_init(struct device_node *np)
 172 {
 173         struct device_node *cache_dn;
 174
 175         coherency_cpu_base = of_iomap(np, 0);
 176         arch_ioremap_caller = armada_wa_ioremap_caller;
 177         pci_ioremap_set_mem_type(MT_UNCACHED);
 178
 179         /*
 180          * We should switch the PL310 to I/O coherency mode only if
 181          * I/O coherency is actually enabled.
 182          */
 183         if (!coherency_available())
 184                 return;
 185
 186         /*
 187          * Add the PL310 property "arm,io-coherent". This makes sure the
 188          * outer sync operation is not used, which allows to
 189          * workaround the system erratum that causes deadlocks when
 190          * doing PCIe in an SMP situation on Armada 375 and Armada
 191          * 38x.
 192          */
 193         for_each_compatible_node(cache_dn, NULL, "arm,pl310-cache") {
 194                 struct property *p;
 195
 196                 p = kzalloc(sizeof(*p), GFP_KERNEL);
 197                 p->name = kstrdup("arm,io-coherent", GFP_KERNEL);
 198                 of_add_property(cache_dn, p);
 199         }
 200 }
 201
 202 static int coherency_type(void)
 203 {
 204         struct device_node *np;
 205         const struct of_device_id *match;
 206         int type;
 207
 208         /*
 209          * The coherency fabric is needed:
 210          * - For coherency between processors on Armada XP, so only
 211          *   when SMP is enabled.
 212          * - For coherency between the processor and I/O devices, but
 213          *   this coherency requires many pre-requisites (write
 214          *   allocate cache policy, shareable pages, SMP bit set) that
 215          *   are only meant in SMP situations.
 216          *
 217          * Note that this means that on Armada 370, there is currently
 218          * no way to use hardware I/O coherency, because even when
 219          * CONFIG_SMP is enabled, is_smp() returns false due to the
 220          * Armada 370 being a single-core processor. To lift this
 221          * limitation, we would have to find a way to make the cache
 222          * policy set to write-allocate (on all Armada SoCs), and to
 223          * set the shareable attribute in page tables (on all Armada
 224          * SoCs except the Armada 370). Unfortunately, such decisions
 225          * are taken very early in the kernel boot process, at a point
 226          * where we don't know yet on which SoC we are running.
 227
 228          */
 229         if (!is_smp())
 230                 return COHERENCY_FABRIC_TYPE_NONE;
 231
 232         np = of_find_matching_node_and_match(NULL, of_coherency_table, &match);
 233         if (!np)
 234                 return COHERENCY_FABRIC_TYPE_NONE;
 235
 236         type = (int) match->data;
 237
 238         of_node_put(np);
 239
 240         return type;
 241 }
 242
 243 int set_cpu_coherent(void)
 244 {
 245         int type = coherency_type();
 246
 247         if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP) {
 248                 if (!coherency_base) {
 249                         pr_warn("Can't make current CPU cache coherent.\n");
 250                         pr_warn("Coherency fabric is not initialized\n");
 251                         return 1;
 252                 }
 253
 254                 armada_xp_clear_shared_l2();
 255                 ll_add_cpu_to_smp_group();
 256                 return ll_enable_coherency();
 257         }
 258
 259         return 0;
 260 }
 261
 262 int coherency_available(void)
 263 {
 264         return coherency_type() != COHERENCY_FABRIC_TYPE_NONE;
 265 }
 266
 267 int __init coherency_init(void)
 268 {
 269         int type = coherency_type();
 270         struct device_node *np;
 271
 272         np = of_find_matching_node(NULL, of_coherency_table);
 273
 274         if (type == COHERENCY_FABRIC_TYPE_ARMADA_370_XP)
 275                 armada_370_coherency_init(np);
 276         else if (type == COHERENCY_FABRIC_TYPE_ARMADA_375 ||
 277                  type == COHERENCY_FABRIC_TYPE_ARMADA_380)
 278                 armada_375_380_coherency_init(np);
 279
 280         of_node_put(np);
 281
 282         return 0;
 283 }
 284
 285 static int __init coherency_late_init(void)
 286 {
 287         if (coherency_available())
 288                 bus_register_notifier(&platform_bus_type,
 289                                       &mvebu_hwcc_nb);
 290         return 0;
 291 }
 292
 293 postcore_initcall(coherency_late_init);
 294
 295 #if IS_ENABLED(CONFIG_PCI)
 296 static int __init coherency_pci_init(void)
 297 {
 298         if (coherency_available())
 299                 bus_register_notifier(&pci_bus_type,
 300                                        &mvebu_hwcc_pci_nb);
 301         return 0;
 302 }
 303
 304 arch_initcall(coherency_pci_init);
 305 #endif