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serial: imx: Enable UCR4_OREN in startup interface
[linux-2.6/btrfs-unstable.git] / drivers / tty / serial / imx.c
blob79f485b99c3fd4d34b9ad7ecf31266a65c8ec1e0
1 /*
2 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
9 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
29
30 #if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31 #define SUPPORT_SYSRQ
32 #endif
33
34 #include <linux/module.h>
35 #include <linux/ioport.h>
36 #include <linux/init.h>
37 #include <linux/console.h>
38 #include <linux/sysrq.h>
39 #include <linux/platform_device.h>
40 #include <linux/tty.h>
41 #include <linux/tty_flip.h>
42 #include <linux/serial_core.h>
43 #include <linux/serial.h>
44 #include <linux/clk.h>
45 #include <linux/delay.h>
46 #include <linux/rational.h>
47 #include <linux/slab.h>
48 #include <linux/of.h>
49 #include <linux/of_device.h>
50 #include <linux/io.h>
51 #include <linux/dma-mapping.h>
52
53 #include <asm/irq.h>
54 #include <linux/platform_data/serial-imx.h>
55 #include <linux/platform_data/dma-imx.h>
56
57 /* Register definitions */
58 #define URXD0 0x0 /* Receiver Register */
59 #define URTX0 0x40 /* Transmitter Register */
60 #define UCR1 0x80 /* Control Register 1 */
61 #define UCR2 0x84 /* Control Register 2 */
62 #define UCR3 0x88 /* Control Register 3 */
63 #define UCR4 0x8c /* Control Register 4 */
64 #define UFCR 0x90 /* FIFO Control Register */
65 #define USR1 0x94 /* Status Register 1 */
66 #define USR2 0x98 /* Status Register 2 */
67 #define UESC 0x9c /* Escape Character Register */
68 #define UTIM 0xa0 /* Escape Timer Register */
69 #define UBIR 0xa4 /* BRM Incremental Register */
70 #define UBMR 0xa8 /* BRM Modulator Register */
71 #define UBRC 0xac /* Baud Rate Count Register */
72 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
73 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
75
76 /* UART Control Register Bit Fields.*/
77 #define URXD_DUMMY_READ (1<<16)
78 #define URXD_CHARRDY (1<<15)
79 #define URXD_ERR (1<<14)
80 #define URXD_OVRRUN (1<<13)
81 #define URXD_FRMERR (1<<12)
82 #define URXD_BRK (1<<11)
83 #define URXD_PRERR (1<<10)
84 #define URXD_RX_DATA (0xFF<<0)
85 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
86 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
87 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
88 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
89 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
90 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
91 #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
92 #define UCR1_IREN (1<<7) /* Infrared interface enable */
93 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
94 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
95 #define UCR1_SNDBRK (1<<4) /* Send break */
96 #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
97 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
98 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
99 #define UCR1_DOZE (1<<1) /* Doze */
100 #define UCR1_UARTEN (1<<0) /* UART enabled */
101 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
102 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
103 #define UCR2_CTSC (1<<13) /* CTS pin control */
104 #define UCR2_CTS (1<<12) /* Clear to send */
105 #define UCR2_ESCEN (1<<11) /* Escape enable */
106 #define UCR2_PREN (1<<8) /* Parity enable */
107 #define UCR2_PROE (1<<7) /* Parity odd/even */
108 #define UCR2_STPB (1<<6) /* Stop */
109 #define UCR2_WS (1<<5) /* Word size */
110 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
111 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
112 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
113 #define UCR2_RXEN (1<<1) /* Receiver enabled */
114 #define UCR2_SRST (1<<0) /* SW reset */
115 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
116 #define UCR3_PARERREN (1<<12) /* Parity enable */
117 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
118 #define UCR3_DSR (1<<10) /* Data set ready */
119 #define UCR3_DCD (1<<9) /* Data carrier detect */
120 #define UCR3_RI (1<<8) /* Ring indicator */
121 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
122 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
123 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
124 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
125 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
126 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
127 #define UCR3_BPEN (1<<0) /* Preset registers enable */
128 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
129 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
130 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
131 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
132 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
133 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
134 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
135 #define UCR4_IRSC (1<<5) /* IR special case */
136 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
137 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
138 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
139 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
140 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
141 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
142 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
143 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
144 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
145 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
146 #define USR1_RTSS (1<<14) /* RTS pin status */
147 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
148 #define USR1_RTSD (1<<12) /* RTS delta */
149 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
150 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
151 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
152 #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
153 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
154 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
155 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
156 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
157 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
158 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
159 #define USR2_IDLE (1<<12) /* Idle condition */
160 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
161 #define USR2_WAKE (1<<7) /* Wake */
162 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
163 #define USR2_TXDC (1<<3) /* Transmitter complete */
164 #define USR2_BRCD (1<<2) /* Break condition */
165 #define USR2_ORE (1<<1) /* Overrun error */
166 #define USR2_RDR (1<<0) /* Recv data ready */
167 #define UTS_FRCPERR (1<<13) /* Force parity error */
168 #define UTS_LOOP (1<<12) /* Loop tx and rx */
169 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
170 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
171 #define UTS_TXFULL (1<<4) /* TxFIFO full */
172 #define UTS_RXFULL (1<<3) /* RxFIFO full */
173 #define UTS_SOFTRST (1<<0) /* Software reset */
174
175 /* We've been assigned a range on the "Low-density serial ports" major */
176 #define SERIAL_IMX_MAJOR 207
177 #define MINOR_START 16
178 #define DEV_NAME "ttymxc"
179
180 /*
181 * This determines how often we check the modem status signals
182 * for any change. They generally aren't connected to an IRQ
183 * so we have to poll them. We also check immediately before
184 * filling the TX fifo incase CTS has been dropped.
185 */
186 #define MCTRL_TIMEOUT (250*HZ/1000)
187
188 #define DRIVER_NAME "IMX-uart"
189
190 #define UART_NR 8
191
192 /* i.mx21 type uart runs on all i.mx except i.mx1 */
193 enum imx_uart_type {
194 IMX1_UART,
195 IMX21_UART,
196 IMX6Q_UART,
197 };
198
199 /* device type dependent stuff */
200 struct imx_uart_data {
201 unsigned uts_reg;
202 enum imx_uart_type devtype;
203 };
204
205 struct imx_port {
206 struct uart_port port;
207 struct timer_list timer;
208 unsigned int old_status;
209 int txirq, rxirq, rtsirq;
210 unsigned int have_rtscts:1;
211 unsigned int dte_mode:1;
212 unsigned int use_irda:1;
213 unsigned int irda_inv_rx:1;
214 unsigned int irda_inv_tx:1;
215 unsigned short trcv_delay; /* transceiver delay */
216 struct clk *clk_ipg;
217 struct clk *clk_per;
218 const struct imx_uart_data *devdata;
219
220 /* DMA fields */
221 unsigned int dma_is_inited:1;
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
227 void *rx_buf;
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 wait_queue_head_t dma_wait;
231 };
232
233 struct imx_port_ucrs {
234 unsigned int ucr1;
235 unsigned int ucr2;
236 unsigned int ucr3;
237 };
238
239 #ifdef CONFIG_IRDA
240 #define USE_IRDA(sport) ((sport)->use_irda)
241 #else
242 #define USE_IRDA(sport) (0)
243 #endif
244
245 static struct imx_uart_data imx_uart_devdata[] = {
246 [IMX1_UART] = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249 },
250 [IMX21_UART] = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
253 },
254 [IMX6Q_UART] = {
255 .uts_reg = IMX21_UTS,
256 .devtype = IMX6Q_UART,
257 },
258 };
259
260 static struct platform_device_id imx_uart_devtype[] = {
261 {
262 .name = "imx1-uart",
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
264 }, {
265 .name = "imx21-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
267 }, {
268 .name = "imx6q-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
270 }, {
271 /* sentinel */
272 }
273 };
274 MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
275
276 static struct of_device_id imx_uart_dt_ids[] = {
277 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 { /* sentinel */ }
281 };
282 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
283
284 static inline unsigned uts_reg(struct imx_port *sport)
285 {
286 return sport->devdata->uts_reg;
287 }
288
289 static inline int is_imx1_uart(struct imx_port *sport)
290 {
291 return sport->devdata->devtype == IMX1_UART;
292 }
293
294 static inline int is_imx21_uart(struct imx_port *sport)
295 {
296 return sport->devdata->devtype == IMX21_UART;
297 }
298
299 static inline int is_imx6q_uart(struct imx_port *sport)
300 {
301 return sport->devdata->devtype == IMX6Q_UART;
302 }
303 /*
304 * Save and restore functions for UCR1, UCR2 and UCR3 registers
305 */
306 #if defined(CONFIG_SERIAL_IMX_CONSOLE)
307 static void imx_port_ucrs_save(struct uart_port *port,
308 struct imx_port_ucrs *ucr)
309 {
310 /* save control registers */
311 ucr->ucr1 = readl(port->membase + UCR1);
312 ucr->ucr2 = readl(port->membase + UCR2);
313 ucr->ucr3 = readl(port->membase + UCR3);
314 }
315
316 static void imx_port_ucrs_restore(struct uart_port *port,
317 struct imx_port_ucrs *ucr)
318 {
319 /* restore control registers */
320 writel(ucr->ucr1, port->membase + UCR1);
321 writel(ucr->ucr2, port->membase + UCR2);
322 writel(ucr->ucr3, port->membase + UCR3);
323 }
324 #endif
325
326 /*
327 * Handle any change of modem status signal since we were last called.
328 */
329 static void imx_mctrl_check(struct imx_port *sport)
330 {
331 unsigned int status, changed;
332
333 status = sport->port.ops->get_mctrl(&sport->port);
334 changed = status ^ sport->old_status;
335
336 if (changed == 0)
337 return;
338
339 sport->old_status = status;
340
341 if (changed & TIOCM_RI)
342 sport->port.icount.rng++;
343 if (changed & TIOCM_DSR)
344 sport->port.icount.dsr++;
345 if (changed & TIOCM_CAR)
346 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
347 if (changed & TIOCM_CTS)
348 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
349
350 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
351 }
352
353 /*
354 * This is our per-port timeout handler, for checking the
355 * modem status signals.
356 */
357 static void imx_timeout(unsigned long data)
358 {
359 struct imx_port *sport = (struct imx_port *)data;
360 unsigned long flags;
361
362 if (sport->port.state) {
363 spin_lock_irqsave(&sport->port.lock, flags);
364 imx_mctrl_check(sport);
365 spin_unlock_irqrestore(&sport->port.lock, flags);
366
367 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
368 }
369 }
370
371 /*
372 * interrupts disabled on entry
373 */
374 static void imx_stop_tx(struct uart_port *port)
375 {
376 struct imx_port *sport = (struct imx_port *)port;
377 unsigned long temp;
378
379 if (USE_IRDA(sport)) {
380 /* half duplex - wait for end of transmission */
381 int n = 256;
382 while ((--n > 0) &&
383 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
384 udelay(5);
385 barrier();
386 }
387 /*
388 * irda transceiver - wait a bit more to avoid
389 * cutoff, hardware dependent
390 */
391 udelay(sport->trcv_delay);
392
393 /*
394 * half duplex - reactivate receive mode,
395 * flush receive pipe echo crap
396 */
397 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
398 temp = readl(sport->port.membase + UCR1);
399 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
400 writel(temp, sport->port.membase + UCR1);
401
402 temp = readl(sport->port.membase + UCR4);
403 temp &= ~(UCR4_TCEN);
404 writel(temp, sport->port.membase + UCR4);
405
406 while (readl(sport->port.membase + URXD0) &
407 URXD_CHARRDY)
408 barrier();
409
410 temp = readl(sport->port.membase + UCR1);
411 temp |= UCR1_RRDYEN;
412 writel(temp, sport->port.membase + UCR1);
413
414 temp = readl(sport->port.membase + UCR4);
415 temp |= UCR4_DREN;
416 writel(temp, sport->port.membase + UCR4);
417 }
418 return;
419 }
420
421 /*
422 * We are maybe in the SMP context, so if the DMA TX thread is running
423 * on other cpu, we have to wait for it to finish.
424 */
425 if (sport->dma_is_enabled && sport->dma_is_txing)
426 return;
427
428 temp = readl(sport->port.membase + UCR1);
429 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
430 }
431
432 /*
433 * interrupts disabled on entry
434 */
435 static void imx_stop_rx(struct uart_port *port)
436 {
437 struct imx_port *sport = (struct imx_port *)port;
438 unsigned long temp;
439
440 if (sport->dma_is_enabled && sport->dma_is_rxing) {
441 if (sport->port.suspended) {
442 dmaengine_terminate_all(sport->dma_chan_rx);
443 sport->dma_is_rxing = 0;
444 } else {
445 return;
446 }
447 }
448
449 temp = readl(sport->port.membase + UCR2);
450 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
451
452 /* disable the `Receiver Ready Interrrupt` */
453 temp = readl(sport->port.membase + UCR1);
454 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
455 }
456
457 /*
458 * Set the modem control timer to fire immediately.
459 */
460 static void imx_enable_ms(struct uart_port *port)
461 {
462 struct imx_port *sport = (struct imx_port *)port;
463
464 mod_timer(&sport->timer, jiffies);
465 }
466
467 static inline void imx_transmit_buffer(struct imx_port *sport)
468 {
469 struct circ_buf *xmit = &sport->port.state->xmit;
470
471 if (sport->port.x_char) {
472 /* Send next char */
473 writel(sport->port.x_char, sport->port.membase + URTX0);
474 return;
475 }
476
477 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
478 imx_stop_tx(&sport->port);
479 return;
480 }
481
482 while (!uart_circ_empty(xmit) &&
483 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
484 /* send xmit->buf[xmit->tail]
485 * out the port here */
486 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
487 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
488 sport->port.icount.tx++;
489 }
490
491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
492 uart_write_wakeup(&sport->port);
493
494 if (uart_circ_empty(xmit))
495 imx_stop_tx(&sport->port);
496 }
497
498 static void imx_dma_tx(struct imx_port *sport);
499 static void dma_tx_callback(void *data)
500 {
501 struct imx_port *sport = data;
502 struct scatterlist *sgl = &sport->tx_sgl[0];
503 struct circ_buf *xmit = &sport->port.state->xmit;
504 unsigned long flags;
505 unsigned long temp;
506
507 spin_lock_irqsave(&sport->port.lock, flags);
508
509 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
510
511 temp = readl(sport->port.membase + UCR1);
512 temp &= ~UCR1_TDMAEN;
513 writel(temp, sport->port.membase + UCR1);
514
515 /* update the stat */
516 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
517 sport->port.icount.tx += sport->tx_bytes;
518
519 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
520
521 sport->dma_is_txing = 0;
522
523 spin_unlock_irqrestore(&sport->port.lock, flags);
524
525 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
526 uart_write_wakeup(&sport->port);
527
528 if (waitqueue_active(&sport->dma_wait)) {
529 wake_up(&sport->dma_wait);
530 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
531 return;
532 }
533
534 spin_lock_irqsave(&sport->port.lock, flags);
535 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
536 imx_dma_tx(sport);
537 spin_unlock_irqrestore(&sport->port.lock, flags);
538 }
539
540 static void imx_dma_tx(struct imx_port *sport)
541 {
542 struct circ_buf *xmit = &sport->port.state->xmit;
543 struct scatterlist *sgl = sport->tx_sgl;
544 struct dma_async_tx_descriptor *desc;
545 struct dma_chan *chan = sport->dma_chan_tx;
546 struct device *dev = sport->port.dev;
547 unsigned long temp;
548 int ret;
549
550 if (sport->dma_is_txing)
551 return;
552
553 sport->tx_bytes = uart_circ_chars_pending(xmit);
554
555 if (xmit->tail < xmit->head) {
556 sport->dma_tx_nents = 1;
557 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
558 } else {
559 sport->dma_tx_nents = 2;
560 sg_init_table(sgl, 2);
561 sg_set_buf(sgl, xmit->buf + xmit->tail,
562 UART_XMIT_SIZE - xmit->tail);
563 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
564 }
565
566 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
567 if (ret == 0) {
568 dev_err(dev, "DMA mapping error for TX.\n");
569 return;
570 }
571 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
572 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
573 if (!desc) {
574 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
575 DMA_TO_DEVICE);
576 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
577 return;
578 }
579 desc->callback = dma_tx_callback;
580 desc->callback_param = sport;
581
582 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
583 uart_circ_chars_pending(xmit));
584
585 temp = readl(sport->port.membase + UCR1);
586 temp |= UCR1_TDMAEN;
587 writel(temp, sport->port.membase + UCR1);
588
589 /* fire it */
590 sport->dma_is_txing = 1;
591 dmaengine_submit(desc);
592 dma_async_issue_pending(chan);
593 return;
594 }
595
596 /*
597 * interrupts disabled on entry
598 */
599 static void imx_start_tx(struct uart_port *port)
600 {
601 struct imx_port *sport = (struct imx_port *)port;
602 unsigned long temp;
603
604 if (USE_IRDA(sport)) {
605 /* half duplex in IrDA mode; have to disable receive mode */
606 temp = readl(sport->port.membase + UCR4);
607 temp &= ~(UCR4_DREN);
608 writel(temp, sport->port.membase + UCR4);
609
610 temp = readl(sport->port.membase + UCR1);
611 temp &= ~(UCR1_RRDYEN);
612 writel(temp, sport->port.membase + UCR1);
613 }
614
615 if (!sport->dma_is_enabled) {
616 temp = readl(sport->port.membase + UCR1);
617 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
618 }
619
620 if (USE_IRDA(sport)) {
621 temp = readl(sport->port.membase + UCR1);
622 temp |= UCR1_TRDYEN;
623 writel(temp, sport->port.membase + UCR1);
624
625 temp = readl(sport->port.membase + UCR4);
626 temp |= UCR4_TCEN;
627 writel(temp, sport->port.membase + UCR4);
628 }
629
630 if (sport->dma_is_enabled) {
631 /* FIXME: port->x_char must be transmitted if != 0 */
632 if (!uart_circ_empty(&port->state->xmit) &&
633 !uart_tx_stopped(port))
634 imx_dma_tx(sport);
635 return;
636 }
637 }
638
639 static irqreturn_t imx_rtsint(int irq, void *dev_id)
640 {
641 struct imx_port *sport = dev_id;
642 unsigned int val;
643 unsigned long flags;
644
645 spin_lock_irqsave(&sport->port.lock, flags);
646
647 writel(USR1_RTSD, sport->port.membase + USR1);
648 val = readl(sport->port.membase + USR1) & USR1_RTSS;
649 uart_handle_cts_change(&sport->port, !!val);
650 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
651
652 spin_unlock_irqrestore(&sport->port.lock, flags);
653 return IRQ_HANDLED;
654 }
655
656 static irqreturn_t imx_txint(int irq, void *dev_id)
657 {
658 struct imx_port *sport = dev_id;
659 unsigned long flags;
660
661 spin_lock_irqsave(&sport->port.lock, flags);
662 imx_transmit_buffer(sport);
663 spin_unlock_irqrestore(&sport->port.lock, flags);
664 return IRQ_HANDLED;
665 }
666
667 static irqreturn_t imx_rxint(int irq, void *dev_id)
668 {
669 struct imx_port *sport = dev_id;
670 unsigned int rx, flg, ignored = 0;
671 struct tty_port *port = &sport->port.state->port;
672 unsigned long flags, temp;
673
674 spin_lock_irqsave(&sport->port.lock, flags);
675
676 while (readl(sport->port.membase + USR2) & USR2_RDR) {
677 flg = TTY_NORMAL;
678 sport->port.icount.rx++;
679
680 rx = readl(sport->port.membase + URXD0);
681
682 temp = readl(sport->port.membase + USR2);
683 if (temp & USR2_BRCD) {
684 writel(USR2_BRCD, sport->port.membase + USR2);
685 if (uart_handle_break(&sport->port))
686 continue;
687 }
688
689 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
690 continue;
691
692 if (unlikely(rx & URXD_ERR)) {
693 if (rx & URXD_BRK)
694 sport->port.icount.brk++;
695 else if (rx & URXD_PRERR)
696 sport->port.icount.parity++;
697 else if (rx & URXD_FRMERR)
698 sport->port.icount.frame++;
699 if (rx & URXD_OVRRUN)
700 sport->port.icount.overrun++;
701
702 if (rx & sport->port.ignore_status_mask) {
703 if (++ignored > 100)
704 goto out;
705 continue;
706 }
707
708 rx &= sport->port.read_status_mask;
709
710 if (rx & URXD_BRK)
711 flg = TTY_BREAK;
712 else if (rx & URXD_PRERR)
713 flg = TTY_PARITY;
714 else if (rx & URXD_FRMERR)
715 flg = TTY_FRAME;
716 if (rx & URXD_OVRRUN)
717 flg = TTY_OVERRUN;
718
719 #ifdef SUPPORT_SYSRQ
720 sport->port.sysrq = 0;
721 #endif
722 }
723
724 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
725 goto out;
726
727 tty_insert_flip_char(port, rx, flg);
728 }
729
730 out:
731 spin_unlock_irqrestore(&sport->port.lock, flags);
732 tty_flip_buffer_push(port);
733 return IRQ_HANDLED;
734 }
735
736 static int start_rx_dma(struct imx_port *sport);
737 /*
738 * If the RXFIFO is filled with some data, and then we
739 * arise a DMA operation to receive them.
740 */
741 static void imx_dma_rxint(struct imx_port *sport)
742 {
743 unsigned long temp;
744 unsigned long flags;
745
746 spin_lock_irqsave(&sport->port.lock, flags);
747
748 temp = readl(sport->port.membase + USR2);
749 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
750 sport->dma_is_rxing = 1;
751
752 /* disable the `Recerver Ready Interrrupt` */
753 temp = readl(sport->port.membase + UCR1);
754 temp &= ~(UCR1_RRDYEN);
755 writel(temp, sport->port.membase + UCR1);
756
757 /* tell the DMA to receive the data. */
758 start_rx_dma(sport);
759 }
760
761 spin_unlock_irqrestore(&sport->port.lock, flags);
762 }
763
764 static irqreturn_t imx_int(int irq, void *dev_id)
765 {
766 struct imx_port *sport = dev_id;
767 unsigned int sts;
768 unsigned int sts2;
769
770 sts = readl(sport->port.membase + USR1);
771
772 if (sts & USR1_RRDY) {
773 if (sport->dma_is_enabled)
774 imx_dma_rxint(sport);
775 else
776 imx_rxint(irq, dev_id);
777 }
778
779 if (sts & USR1_TRDY &&
780 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
781 imx_txint(irq, dev_id);
782
783 if (sts & USR1_RTSD)
784 imx_rtsint(irq, dev_id);
785
786 if (sts & USR1_AWAKE)
787 writel(USR1_AWAKE, sport->port.membase + USR1);
788
789 sts2 = readl(sport->port.membase + USR2);
790 if (sts2 & USR2_ORE) {
791 dev_err(sport->port.dev, "Rx FIFO overrun\n");
792 sport->port.icount.overrun++;
793 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
794 }
795
796 return IRQ_HANDLED;
797 }
798
799 /*
800 * Return TIOCSER_TEMT when transmitter is not busy.
801 */
802 static unsigned int imx_tx_empty(struct uart_port *port)
803 {
804 struct imx_port *sport = (struct imx_port *)port;
805 unsigned int ret;
806
807 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
808
809 /* If the TX DMA is working, return 0. */
810 if (sport->dma_is_enabled && sport->dma_is_txing)
811 ret = 0;
812
813 return ret;
814 }
815
816 /*
817 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
818 */
819 static unsigned int imx_get_mctrl(struct uart_port *port)
820 {
821 struct imx_port *sport = (struct imx_port *)port;
822 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
823
824 if (readl(sport->port.membase + USR1) & USR1_RTSS)
825 tmp |= TIOCM_CTS;
826
827 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
828 tmp |= TIOCM_RTS;
829
830 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
831 tmp |= TIOCM_LOOP;
832
833 return tmp;
834 }
835
836 static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
837 {
838 struct imx_port *sport = (struct imx_port *)port;
839 unsigned long temp;
840
841 temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC);
842 if (mctrl & TIOCM_RTS)
843 temp |= UCR2_CTS | UCR2_CTSC;
844
845 writel(temp, sport->port.membase + UCR2);
846
847 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
848 if (mctrl & TIOCM_LOOP)
849 temp |= UTS_LOOP;
850 writel(temp, sport->port.membase + uts_reg(sport));
851 }
852
853 /*
854 * Interrupts always disabled.
855 */
856 static void imx_break_ctl(struct uart_port *port, int break_state)
857 {
858 struct imx_port *sport = (struct imx_port *)port;
859 unsigned long flags, temp;
860
861 spin_lock_irqsave(&sport->port.lock, flags);
862
863 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
864
865 if (break_state != 0)
866 temp |= UCR1_SNDBRK;
867
868 writel(temp, sport->port.membase + UCR1);
869
870 spin_unlock_irqrestore(&sport->port.lock, flags);
871 }
872
873 #define TXTL 2 /* reset default */
874 #define RXTL 1 /* reset default */
875
876 static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
877 {
878 unsigned int val;
879
880 /* set receiver / transmitter trigger level */
881 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
882 val |= TXTL << UFCR_TXTL_SHF | RXTL;
883 writel(val, sport->port.membase + UFCR);
884 return 0;
885 }
886
887 #define RX_BUF_SIZE (PAGE_SIZE)
888 static void imx_rx_dma_done(struct imx_port *sport)
889 {
890 unsigned long temp;
891 unsigned long flags;
892
893 spin_lock_irqsave(&sport->port.lock, flags);
894
895 /* Enable this interrupt when the RXFIFO is empty. */
896 temp = readl(sport->port.membase + UCR1);
897 temp |= UCR1_RRDYEN;
898 writel(temp, sport->port.membase + UCR1);
899
900 sport->dma_is_rxing = 0;
901
902 /* Is the shutdown waiting for us? */
903 if (waitqueue_active(&sport->dma_wait))
904 wake_up(&sport->dma_wait);
905
906 spin_unlock_irqrestore(&sport->port.lock, flags);
907 }
908
909 /*
910 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
911 * [1] the RX DMA buffer is full.
912 * [2] the Aging timer expires(wait for 8 bytes long)
913 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
914 *
915 * The [2] is trigger when a character was been sitting in the FIFO
916 * meanwhile [3] can wait for 32 bytes long when the RX line is
917 * on IDLE state and RxFIFO is empty.
918 */
919 static void dma_rx_callback(void *data)
920 {
921 struct imx_port *sport = data;
922 struct dma_chan *chan = sport->dma_chan_rx;
923 struct scatterlist *sgl = &sport->rx_sgl;
924 struct tty_port *port = &sport->port.state->port;
925 struct dma_tx_state state;
926 enum dma_status status;
927 unsigned int count;
928
929 /* unmap it first */
930 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
931
932 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
933 count = RX_BUF_SIZE - state.residue;
934 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
935
936 if (count) {
937 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
938 tty_insert_flip_string(port, sport->rx_buf, count);
939 tty_flip_buffer_push(port);
940
941 start_rx_dma(sport);
942 } else if (readl(sport->port.membase + USR2) & USR2_RDR) {
943 /*
944 * start rx_dma directly once data in RXFIFO, more efficient
945 * than before:
946 * 1. call imx_rx_dma_done to stop dma if no data received
947 * 2. wait next RDR interrupt to start dma transfer.
948 */
949 start_rx_dma(sport);
950 } else {
951 /*
952 * stop dma to prevent too many IDLE event trigged if no data
953 * in RXFIFO
954 */
955 imx_rx_dma_done(sport);
956 }
957 }
958
959 static int start_rx_dma(struct imx_port *sport)
960 {
961 struct scatterlist *sgl = &sport->rx_sgl;
962 struct dma_chan *chan = sport->dma_chan_rx;
963 struct device *dev = sport->port.dev;
964 struct dma_async_tx_descriptor *desc;
965 int ret;
966
967 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
968 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
969 if (ret == 0) {
970 dev_err(dev, "DMA mapping error for RX.\n");
971 return -EINVAL;
972 }
973 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
974 DMA_PREP_INTERRUPT);
975 if (!desc) {
976 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
977 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
978 return -EINVAL;
979 }
980 desc->callback = dma_rx_callback;
981 desc->callback_param = sport;
982
983 dev_dbg(dev, "RX: prepare for the DMA.\n");
984 dmaengine_submit(desc);
985 dma_async_issue_pending(chan);
986 return 0;
987 }
988
989 static void imx_uart_dma_exit(struct imx_port *sport)
990 {
991 if (sport->dma_chan_rx) {
992 dma_release_channel(sport->dma_chan_rx);
993 sport->dma_chan_rx = NULL;
994
995 kfree(sport->rx_buf);
996 sport->rx_buf = NULL;
997 }
998
999 if (sport->dma_chan_tx) {
1000 dma_release_channel(sport->dma_chan_tx);
1001 sport->dma_chan_tx = NULL;
1002 }
1003
1004 sport->dma_is_inited = 0;
1005 }
1006
1007 static int imx_uart_dma_init(struct imx_port *sport)
1008 {
1009 struct dma_slave_config slave_config = {};
1010 struct device *dev = sport->port.dev;
1011 int ret;
1012
1013 /* Prepare for RX : */
1014 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1015 if (!sport->dma_chan_rx) {
1016 dev_dbg(dev, "cannot get the DMA channel.\n");
1017 ret = -EINVAL;
1018 goto err;
1019 }
1020
1021 slave_config.direction = DMA_DEV_TO_MEM;
1022 slave_config.src_addr = sport->port.mapbase + URXD0;
1023 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1024 slave_config.src_maxburst = RXTL;
1025 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1026 if (ret) {
1027 dev_err(dev, "error in RX dma configuration.\n");
1028 goto err;
1029 }
1030
1031 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1032 if (!sport->rx_buf) {
1033 ret = -ENOMEM;
1034 goto err;
1035 }
1036
1037 /* Prepare for TX : */
1038 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1039 if (!sport->dma_chan_tx) {
1040 dev_err(dev, "cannot get the TX DMA channel!\n");
1041 ret = -EINVAL;
1042 goto err;
1043 }
1044
1045 slave_config.direction = DMA_MEM_TO_DEV;
1046 slave_config.dst_addr = sport->port.mapbase + URTX0;
1047 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1048 slave_config.dst_maxburst = TXTL;
1049 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1050 if (ret) {
1051 dev_err(dev, "error in TX dma configuration.");
1052 goto err;
1053 }
1054
1055 sport->dma_is_inited = 1;
1056
1057 return 0;
1058 err:
1059 imx_uart_dma_exit(sport);
1060 return ret;
1061 }
1062
1063 static void imx_enable_dma(struct imx_port *sport)
1064 {
1065 unsigned long temp;
1066
1067 init_waitqueue_head(&sport->dma_wait);
1068
1069 /* set UCR1 */
1070 temp = readl(sport->port.membase + UCR1);
1071 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1072 /* wait for 32 idle frames for IDDMA interrupt */
1073 UCR1_ICD_REG(3);
1074 writel(temp, sport->port.membase + UCR1);
1075
1076 /* set UCR4 */
1077 temp = readl(sport->port.membase + UCR4);
1078 temp |= UCR4_IDDMAEN;
1079 writel(temp, sport->port.membase + UCR4);
1080
1081 sport->dma_is_enabled = 1;
1082 }
1083
1084 static void imx_disable_dma(struct imx_port *sport)
1085 {
1086 unsigned long temp;
1087
1088 /* clear UCR1 */
1089 temp = readl(sport->port.membase + UCR1);
1090 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1091 writel(temp, sport->port.membase + UCR1);
1092
1093 /* clear UCR2 */
1094 temp = readl(sport->port.membase + UCR2);
1095 temp &= ~(UCR2_CTSC | UCR2_CTS);
1096 writel(temp, sport->port.membase + UCR2);
1097
1098 /* clear UCR4 */
1099 temp = readl(sport->port.membase + UCR4);
1100 temp &= ~UCR4_IDDMAEN;
1101 writel(temp, sport->port.membase + UCR4);
1102
1103 sport->dma_is_enabled = 0;
1104 }
1105
1106 /* half the RX buffer size */
1107 #define CTSTL 16
1108
1109 static int imx_startup(struct uart_port *port)
1110 {
1111 struct imx_port *sport = (struct imx_port *)port;
1112 int retval, i;
1113 unsigned long flags, temp;
1114
1115 retval = clk_prepare_enable(sport->clk_per);
1116 if (retval)
1117 return retval;
1118 retval = clk_prepare_enable(sport->clk_ipg);
1119 if (retval) {
1120 clk_disable_unprepare(sport->clk_per);
1121 return retval;
1122 }
1123
1124 imx_setup_ufcr(sport, 0);
1125
1126 /* disable the DREN bit (Data Ready interrupt enable) before
1127 * requesting IRQs
1128 */
1129 temp = readl(sport->port.membase + UCR4);
1130
1131 if (USE_IRDA(sport))
1132 temp |= UCR4_IRSC;
1133
1134 /* set the trigger level for CTS */
1135 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1136 temp |= CTSTL << UCR4_CTSTL_SHF;
1137
1138 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
1139
1140 /* Reset fifo's and state machines */
1141 i = 100;
1142
1143 temp = readl(sport->port.membase + UCR2);
1144 temp &= ~UCR2_SRST;
1145 writel(temp, sport->port.membase + UCR2);
1146
1147 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1148 udelay(1);
1149
1150 /* Can we enable the DMA support? */
1151 if (is_imx6q_uart(sport) && !uart_console(port) &&
1152 !sport->dma_is_inited)
1153 imx_uart_dma_init(sport);
1154
1155 spin_lock_irqsave(&sport->port.lock, flags);
1156 /*
1157 * Finally, clear and enable interrupts
1158 */
1159 writel(USR1_RTSD, sport->port.membase + USR1);
1160
1161 if (sport->dma_is_inited && !sport->dma_is_enabled)
1162 imx_enable_dma(sport);
1163
1164 temp = readl(sport->port.membase + UCR1);
1165 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
1166
1167 if (USE_IRDA(sport)) {
1168 temp |= UCR1_IREN;
1169 temp &= ~(UCR1_RTSDEN);
1170 }
1171
1172 writel(temp, sport->port.membase + UCR1);
1173
1174 /* Clear any pending ORE flag before enabling interrupt */
1175 temp = readl(sport->port.membase + USR2);
1176 writel(temp | USR2_ORE, sport->port.membase + USR2);
1177
1178 temp = readl(sport->port.membase + UCR4);
1179 temp |= UCR4_OREN;
1180 writel(temp, sport->port.membase + UCR4);
1181
1182 temp = readl(sport->port.membase + UCR2);
1183 temp |= (UCR2_RXEN | UCR2_TXEN);
1184 if (!sport->have_rtscts)
1185 temp |= UCR2_IRTS;
1186 writel(temp, sport->port.membase + UCR2);
1187
1188 if (!is_imx1_uart(sport)) {
1189 temp = readl(sport->port.membase + UCR3);
1190 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
1191 writel(temp, sport->port.membase + UCR3);
1192 }
1193
1194 if (USE_IRDA(sport)) {
1195 temp = readl(sport->port.membase + UCR4);
1196 if (sport->irda_inv_rx)
1197 temp |= UCR4_INVR;
1198 else
1199 temp &= ~(UCR4_INVR);
1200 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1201
1202 temp = readl(sport->port.membase + UCR3);
1203 if (sport->irda_inv_tx)
1204 temp |= UCR3_INVT;
1205 else
1206 temp &= ~(UCR3_INVT);
1207 writel(temp, sport->port.membase + UCR3);
1208 }
1209
1210 /*
1211 * Enable modem status interrupts
1212 */
1213 imx_enable_ms(&sport->port);
1214 spin_unlock_irqrestore(&sport->port.lock, flags);
1215
1216 if (USE_IRDA(sport)) {
1217 struct imxuart_platform_data *pdata;
1218 pdata = dev_get_platdata(sport->port.dev);
1219 sport->irda_inv_rx = pdata->irda_inv_rx;
1220 sport->irda_inv_tx = pdata->irda_inv_tx;
1221 sport->trcv_delay = pdata->transceiver_delay;
1222 if (pdata->irda_enable)
1223 pdata->irda_enable(1);
1224 }
1225
1226 return 0;
1227 }
1228
1229 static void imx_shutdown(struct uart_port *port)
1230 {
1231 struct imx_port *sport = (struct imx_port *)port;
1232 unsigned long temp;
1233 unsigned long flags;
1234
1235 if (sport->dma_is_enabled) {
1236 int ret;
1237
1238 /* We have to wait for the DMA to finish. */
1239 ret = wait_event_interruptible(sport->dma_wait,
1240 !sport->dma_is_rxing && !sport->dma_is_txing);
1241 if (ret != 0) {
1242 sport->dma_is_rxing = 0;
1243 sport->dma_is_txing = 0;
1244 dmaengine_terminate_all(sport->dma_chan_tx);
1245 dmaengine_terminate_all(sport->dma_chan_rx);
1246 }
1247 spin_lock_irqsave(&sport->port.lock, flags);
1248 imx_stop_tx(port);
1249 imx_stop_rx(port);
1250 imx_disable_dma(sport);
1251 spin_unlock_irqrestore(&sport->port.lock, flags);
1252 imx_uart_dma_exit(sport);
1253 }
1254
1255 spin_lock_irqsave(&sport->port.lock, flags);
1256 temp = readl(sport->port.membase + UCR2);
1257 temp &= ~(UCR2_TXEN);
1258 writel(temp, sport->port.membase + UCR2);
1259 spin_unlock_irqrestore(&sport->port.lock, flags);
1260
1261 if (USE_IRDA(sport)) {
1262 struct imxuart_platform_data *pdata;
1263 pdata = dev_get_platdata(sport->port.dev);
1264 if (pdata->irda_enable)
1265 pdata->irda_enable(0);
1266 }
1267
1268 /*
1269 * Stop our timer.
1270 */
1271 del_timer_sync(&sport->timer);
1272
1273 /*
1274 * Disable all interrupts, port and break condition.
1275 */
1276
1277 spin_lock_irqsave(&sport->port.lock, flags);
1278 temp = readl(sport->port.membase + UCR1);
1279 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
1280 if (USE_IRDA(sport))
1281 temp &= ~(UCR1_IREN);
1282
1283 writel(temp, sport->port.membase + UCR1);
1284 spin_unlock_irqrestore(&sport->port.lock, flags);
1285
1286 clk_disable_unprepare(sport->clk_per);
1287 clk_disable_unprepare(sport->clk_ipg);
1288 }
1289
1290 static void imx_flush_buffer(struct uart_port *port)
1291 {
1292 struct imx_port *sport = (struct imx_port *)port;
1293 struct scatterlist *sgl = &sport->tx_sgl[0];
1294 unsigned long temp;
1295
1296 if (!sport->dma_chan_tx)
1297 return;
1298
1299 sport->tx_bytes = 0;
1300 dmaengine_terminate_all(sport->dma_chan_tx);
1301 if (sport->dma_is_txing) {
1302 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1303 DMA_TO_DEVICE);
1304 temp = readl(sport->port.membase + UCR1);
1305 temp &= ~UCR1_TDMAEN;
1306 writel(temp, sport->port.membase + UCR1);
1307 sport->dma_is_txing = false;
1308 }
1309 }
1310
1311 static void
1312 imx_set_termios(struct uart_port *port, struct ktermios *termios,
1313 struct ktermios *old)
1314 {
1315 struct imx_port *sport = (struct imx_port *)port;
1316 unsigned long flags;
1317 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1318 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1319 unsigned int div, ufcr;
1320 unsigned long num, denom;
1321 uint64_t tdiv64;
1322
1323 /*
1324 * If we don't support modem control lines, don't allow
1325 * these to be set.
1326 */
1327 if (0) {
1328 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1329 termios->c_cflag |= CLOCAL;
1330 }
1331
1332 /*
1333 * We only support CS7 and CS8.
1334 */
1335 while ((termios->c_cflag & CSIZE) != CS7 &&
1336 (termios->c_cflag & CSIZE) != CS8) {
1337 termios->c_cflag &= ~CSIZE;
1338 termios->c_cflag |= old_csize;
1339 old_csize = CS8;
1340 }
1341
1342 if ((termios->c_cflag & CSIZE) == CS8)
1343 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1344 else
1345 ucr2 = UCR2_SRST | UCR2_IRTS;
1346
1347 if (termios->c_cflag & CRTSCTS) {
1348 if (sport->have_rtscts) {
1349 ucr2 &= ~UCR2_IRTS;
1350 ucr2 |= UCR2_CTSC;
1351 } else {
1352 termios->c_cflag &= ~CRTSCTS;
1353 }
1354 }
1355
1356 if (termios->c_cflag & CSTOPB)
1357 ucr2 |= UCR2_STPB;
1358 if (termios->c_cflag & PARENB) {
1359 ucr2 |= UCR2_PREN;
1360 if (termios->c_cflag & PARODD)
1361 ucr2 |= UCR2_PROE;
1362 }
1363
1364 del_timer_sync(&sport->timer);
1365
1366 /*
1367 * Ask the core to calculate the divisor for us.
1368 */
1369 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1370 quot = uart_get_divisor(port, baud);
1371
1372 spin_lock_irqsave(&sport->port.lock, flags);
1373
1374 sport->port.read_status_mask = 0;
1375 if (termios->c_iflag & INPCK)
1376 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1377 if (termios->c_iflag & (BRKINT | PARMRK))
1378 sport->port.read_status_mask |= URXD_BRK;
1379
1380 /*
1381 * Characters to ignore
1382 */
1383 sport->port.ignore_status_mask = 0;
1384 if (termios->c_iflag & IGNPAR)
1385 sport->port.ignore_status_mask |= URXD_PRERR;
1386 if (termios->c_iflag & IGNBRK) {
1387 sport->port.ignore_status_mask |= URXD_BRK;
1388 /*
1389 * If we're ignoring parity and break indicators,
1390 * ignore overruns too (for real raw support).
1391 */
1392 if (termios->c_iflag & IGNPAR)
1393 sport->port.ignore_status_mask |= URXD_OVRRUN;
1394 }
1395
1396 if ((termios->c_cflag & CREAD) == 0)
1397 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1398
1399 /*
1400 * Update the per-port timeout.
1401 */
1402 uart_update_timeout(port, termios->c_cflag, baud);
1403
1404 /*
1405 * disable interrupts and drain transmitter
1406 */
1407 old_ucr1 = readl(sport->port.membase + UCR1);
1408 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1409 sport->port.membase + UCR1);
1410
1411 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
1412 barrier();
1413
1414 /* then, disable everything */
1415 old_txrxen = readl(sport->port.membase + UCR2);
1416 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
1417 sport->port.membase + UCR2);
1418 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
1419
1420 if (USE_IRDA(sport)) {
1421 /*
1422 * use maximum available submodule frequency to
1423 * avoid missing short pulses due to low sampling rate
1424 */
1425 div = 1;
1426 } else {
1427 /* custom-baudrate handling */
1428 div = sport->port.uartclk / (baud * 16);
1429 if (baud == 38400 && quot != div)
1430 baud = sport->port.uartclk / (quot * 16);
1431
1432 div = sport->port.uartclk / (baud * 16);
1433 if (div > 7)
1434 div = 7;
1435 if (!div)
1436 div = 1;
1437 }
1438
1439 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1440 1 << 16, 1 << 16, &num, &denom);
1441
1442 tdiv64 = sport->port.uartclk;
1443 tdiv64 *= num;
1444 do_div(tdiv64, denom * 16 * div);
1445 tty_termios_encode_baud_rate(termios,
1446 (speed_t)tdiv64, (speed_t)tdiv64);
1447
1448 num -= 1;
1449 denom -= 1;
1450
1451 ufcr = readl(sport->port.membase + UFCR);
1452 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1453 if (sport->dte_mode)
1454 ufcr |= UFCR_DCEDTE;
1455 writel(ufcr, sport->port.membase + UFCR);
1456
1457 writel(num, sport->port.membase + UBIR);
1458 writel(denom, sport->port.membase + UBMR);
1459
1460 if (!is_imx1_uart(sport))
1461 writel(sport->port.uartclk / div / 1000,
1462 sport->port.membase + IMX21_ONEMS);
1463
1464 writel(old_ucr1, sport->port.membase + UCR1);
1465
1466 /* set the parity, stop bits and data size */
1467 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
1468
1469 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1470 imx_enable_ms(&sport->port);
1471
1472 spin_unlock_irqrestore(&sport->port.lock, flags);
1473 }
1474
1475 static const char *imx_type(struct uart_port *port)
1476 {
1477 struct imx_port *sport = (struct imx_port *)port;
1478
1479 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1480 }
1481
1482 /*
1483 * Configure/autoconfigure the port.
1484 */
1485 static void imx_config_port(struct uart_port *port, int flags)
1486 {
1487 struct imx_port *sport = (struct imx_port *)port;
1488
1489 if (flags & UART_CONFIG_TYPE)
1490 sport->port.type = PORT_IMX;
1491 }
1492
1493 /*
1494 * Verify the new serial_struct (for TIOCSSERIAL).
1495 * The only change we allow are to the flags and type, and
1496 * even then only between PORT_IMX and PORT_UNKNOWN
1497 */
1498 static int
1499 imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1500 {
1501 struct imx_port *sport = (struct imx_port *)port;
1502 int ret = 0;
1503
1504 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1505 ret = -EINVAL;
1506 if (sport->port.irq != ser->irq)
1507 ret = -EINVAL;
1508 if (ser->io_type != UPIO_MEM)
1509 ret = -EINVAL;
1510 if (sport->port.uartclk / 16 != ser->baud_base)
1511 ret = -EINVAL;
1512 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
1513 ret = -EINVAL;
1514 if (sport->port.iobase != ser->port)
1515 ret = -EINVAL;
1516 if (ser->hub6 != 0)
1517 ret = -EINVAL;
1518 return ret;
1519 }
1520
1521 #if defined(CONFIG_CONSOLE_POLL)
1522
1523 static int imx_poll_init(struct uart_port *port)
1524 {
1525 struct imx_port *sport = (struct imx_port *)port;
1526 unsigned long flags;
1527 unsigned long temp;
1528 int retval;
1529
1530 retval = clk_prepare_enable(sport->clk_ipg);
1531 if (retval)
1532 return retval;
1533 retval = clk_prepare_enable(sport->clk_per);
1534 if (retval)
1535 clk_disable_unprepare(sport->clk_ipg);
1536
1537 imx_setup_ufcr(sport, 0);
1538
1539 spin_lock_irqsave(&sport->port.lock, flags);
1540
1541 temp = readl(sport->port.membase + UCR1);
1542 if (is_imx1_uart(sport))
1543 temp |= IMX1_UCR1_UARTCLKEN;
1544 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1545 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1546 writel(temp, sport->port.membase + UCR1);
1547
1548 temp = readl(sport->port.membase + UCR2);
1549 temp |= UCR2_RXEN;
1550 writel(temp, sport->port.membase + UCR2);
1551
1552 spin_unlock_irqrestore(&sport->port.lock, flags);
1553
1554 return 0;
1555 }
1556
1557 static int imx_poll_get_char(struct uart_port *port)
1558 {
1559 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
1560 return NO_POLL_CHAR;
1561
1562 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
1563 }
1564
1565 static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1566 {
1567 unsigned int status;
1568
1569 /* drain */
1570 do {
1571 status = readl_relaxed(port->membase + USR1);
1572 } while (~status & USR1_TRDY);
1573
1574 /* write */
1575 writel_relaxed(c, port->membase + URTX0);
1576
1577 /* flush */
1578 do {
1579 status = readl_relaxed(port->membase + USR2);
1580 } while (~status & USR2_TXDC);
1581 }
1582 #endif
1583
1584 static struct uart_ops imx_pops = {
1585 .tx_empty = imx_tx_empty,
1586 .set_mctrl = imx_set_mctrl,
1587 .get_mctrl = imx_get_mctrl,
1588 .stop_tx = imx_stop_tx,
1589 .start_tx = imx_start_tx,
1590 .stop_rx = imx_stop_rx,
1591 .enable_ms = imx_enable_ms,
1592 .break_ctl = imx_break_ctl,
1593 .startup = imx_startup,
1594 .shutdown = imx_shutdown,
1595 .flush_buffer = imx_flush_buffer,
1596 .set_termios = imx_set_termios,
1597 .type = imx_type,
1598 .config_port = imx_config_port,
1599 .verify_port = imx_verify_port,
1600 #if defined(CONFIG_CONSOLE_POLL)
1601 .poll_init = imx_poll_init,
1602 .poll_get_char = imx_poll_get_char,
1603 .poll_put_char = imx_poll_put_char,
1604 #endif
1605 };
1606
1607 static struct imx_port *imx_ports[UART_NR];
1608
1609 #ifdef CONFIG_SERIAL_IMX_CONSOLE
1610 static void imx_console_putchar(struct uart_port *port, int ch)
1611 {
1612 struct imx_port *sport = (struct imx_port *)port;
1613
1614 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
1615 barrier();
1616
1617 writel(ch, sport->port.membase + URTX0);
1618 }
1619
1620 /*
1621 * Interrupts are disabled on entering
1622 */
1623 static void
1624 imx_console_write(struct console *co, const char *s, unsigned int count)
1625 {
1626 struct imx_port *sport = imx_ports[co->index];
1627 struct imx_port_ucrs old_ucr;
1628 unsigned int ucr1;
1629 unsigned long flags = 0;
1630 int locked = 1;
1631 int retval;
1632
1633 retval = clk_enable(sport->clk_per);
1634 if (retval)
1635 return;
1636 retval = clk_enable(sport->clk_ipg);
1637 if (retval) {
1638 clk_disable(sport->clk_per);
1639 return;
1640 }
1641
1642 if (sport->port.sysrq)
1643 locked = 0;
1644 else if (oops_in_progress)
1645 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1646 else
1647 spin_lock_irqsave(&sport->port.lock, flags);
1648
1649 /*
1650 * First, save UCR1/2/3 and then disable interrupts
1651 */
1652 imx_port_ucrs_save(&sport->port, &old_ucr);
1653 ucr1 = old_ucr.ucr1;
1654
1655 if (is_imx1_uart(sport))
1656 ucr1 |= IMX1_UCR1_UARTCLKEN;
1657 ucr1 |= UCR1_UARTEN;
1658 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1659
1660 writel(ucr1, sport->port.membase + UCR1);
1661
1662 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
1663
1664 uart_console_write(&sport->port, s, count, imx_console_putchar);
1665
1666 /*
1667 * Finally, wait for transmitter to become empty
1668 * and restore UCR1/2/3
1669 */
1670 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
1671
1672 imx_port_ucrs_restore(&sport->port, &old_ucr);
1673
1674 if (locked)
1675 spin_unlock_irqrestore(&sport->port.lock, flags);
1676
1677 clk_disable(sport->clk_ipg);
1678 clk_disable(sport->clk_per);
1679 }
1680
1681 /*
1682 * If the port was already initialised (eg, by a boot loader),
1683 * try to determine the current setup.
1684 */
1685 static void __init
1686 imx_console_get_options(struct imx_port *sport, int *baud,
1687 int *parity, int *bits)
1688 {
1689
1690 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
1691 /* ok, the port was enabled */
1692 unsigned int ucr2, ubir, ubmr, uartclk;
1693 unsigned int baud_raw;
1694 unsigned int ucfr_rfdiv;
1695
1696 ucr2 = readl(sport->port.membase + UCR2);
1697
1698 *parity = 'n';
1699 if (ucr2 & UCR2_PREN) {
1700 if (ucr2 & UCR2_PROE)
1701 *parity = 'o';
1702 else
1703 *parity = 'e';
1704 }
1705
1706 if (ucr2 & UCR2_WS)
1707 *bits = 8;
1708 else
1709 *bits = 7;
1710
1711 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1712 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
1713
1714 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
1715 if (ucfr_rfdiv == 6)
1716 ucfr_rfdiv = 7;
1717 else
1718 ucfr_rfdiv = 6 - ucfr_rfdiv;
1719
1720 uartclk = clk_get_rate(sport->clk_per);
1721 uartclk /= ucfr_rfdiv;
1722
1723 { /*
1724 * The next code provides exact computation of
1725 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1726 * without need of float support or long long division,
1727 * which would be required to prevent 32bit arithmetic overflow
1728 */
1729 unsigned int mul = ubir + 1;
1730 unsigned int div = 16 * (ubmr + 1);
1731 unsigned int rem = uartclk % div;
1732
1733 baud_raw = (uartclk / div) * mul;
1734 baud_raw += (rem * mul + div / 2) / div;
1735 *baud = (baud_raw + 50) / 100 * 100;
1736 }
1737
1738 if (*baud != baud_raw)
1739 pr_info("Console IMX rounded baud rate from %d to %d\n",
1740 baud_raw, *baud);
1741 }
1742 }
1743
1744 static int __init
1745 imx_console_setup(struct console *co, char *options)
1746 {
1747 struct imx_port *sport;
1748 int baud = 9600;
1749 int bits = 8;
1750 int parity = 'n';
1751 int flow = 'n';
1752 int retval;
1753
1754 /*
1755 * Check whether an invalid uart number has been specified, and
1756 * if so, search for the first available port that does have
1757 * console support.
1758 */
1759 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1760 co->index = 0;
1761 sport = imx_ports[co->index];
1762 if (sport == NULL)
1763 return -ENODEV;
1764
1765 /* For setting the registers, we only need to enable the ipg clock. */
1766 retval = clk_prepare_enable(sport->clk_ipg);
1767 if (retval)
1768 goto error_console;
1769
1770 if (options)
1771 uart_parse_options(options, &baud, &parity, &bits, &flow);
1772 else
1773 imx_console_get_options(sport, &baud, &parity, &bits);
1774
1775 imx_setup_ufcr(sport, 0);
1776
1777 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1778
1779 clk_disable(sport->clk_ipg);
1780 if (retval) {
1781 clk_unprepare(sport->clk_ipg);
1782 goto error_console;
1783 }
1784
1785 retval = clk_prepare(sport->clk_per);
1786 if (retval)
1787 clk_disable_unprepare(sport->clk_ipg);
1788
1789 error_console:
1790 return retval;
1791 }
1792
1793 static struct uart_driver imx_reg;
1794 static struct console imx_console = {
1795 .name = DEV_NAME,
1796 .write = imx_console_write,
1797 .device = uart_console_device,
1798 .setup = imx_console_setup,
1799 .flags = CON_PRINTBUFFER,
1800 .index = -1,
1801 .data = &imx_reg,
1802 };
1803
1804 #define IMX_CONSOLE &imx_console
1805 #else
1806 #define IMX_CONSOLE NULL
1807 #endif
1808
1809 static struct uart_driver imx_reg = {
1810 .owner = THIS_MODULE,
1811 .driver_name = DRIVER_NAME,
1812 .dev_name = DEV_NAME,
1813 .major = SERIAL_IMX_MAJOR,
1814 .minor = MINOR_START,
1815 .nr = ARRAY_SIZE(imx_ports),
1816 .cons = IMX_CONSOLE,
1817 };
1818
1819 static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
1820 {
1821 struct imx_port *sport = platform_get_drvdata(dev);
1822 unsigned int val;
1823
1824 /* enable wakeup from i.MX UART */
1825 val = readl(sport->port.membase + UCR3);
1826 val |= UCR3_AWAKEN;
1827 writel(val, sport->port.membase + UCR3);
1828
1829 uart_suspend_port(&imx_reg, &sport->port);
1830
1831 return 0;
1832 }
1833
1834 static int serial_imx_resume(struct platform_device *dev)
1835 {
1836 struct imx_port *sport = platform_get_drvdata(dev);
1837 unsigned int val;
1838
1839 /* disable wakeup from i.MX UART */
1840 val = readl(sport->port.membase + UCR3);
1841 val &= ~UCR3_AWAKEN;
1842 writel(val, sport->port.membase + UCR3);
1843
1844 uart_resume_port(&imx_reg, &sport->port);
1845
1846 return 0;
1847 }
1848
1849 #ifdef CONFIG_OF
1850 /*
1851 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1852 * could successfully get all information from dt or a negative errno.
1853 */
1854 static int serial_imx_probe_dt(struct imx_port *sport,
1855 struct platform_device *pdev)
1856 {
1857 struct device_node *np = pdev->dev.of_node;
1858 const struct of_device_id *of_id =
1859 of_match_device(imx_uart_dt_ids, &pdev->dev);
1860 int ret;
1861
1862 if (!np)
1863 /* no device tree device */
1864 return 1;
1865
1866 ret = of_alias_get_id(np, "serial");
1867 if (ret < 0) {
1868 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
1869 return ret;
1870 }
1871 sport->port.line = ret;
1872
1873 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1874 sport->have_rtscts = 1;
1875
1876 if (of_get_property(np, "fsl,irda-mode", NULL))
1877 sport->use_irda = 1;
1878
1879 if (of_get_property(np, "fsl,dte-mode", NULL))
1880 sport->dte_mode = 1;
1881
1882 sport->devdata = of_id->data;
1883
1884 return 0;
1885 }
1886 #else
1887 static inline int serial_imx_probe_dt(struct imx_port *sport,
1888 struct platform_device *pdev)
1889 {
1890 return 1;
1891 }
1892 #endif
1893
1894 static void serial_imx_probe_pdata(struct imx_port *sport,
1895 struct platform_device *pdev)
1896 {
1897 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
1898
1899 sport->port.line = pdev->id;
1900 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1901
1902 if (!pdata)
1903 return;
1904
1905 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1906 sport->have_rtscts = 1;
1907
1908 if (pdata->flags & IMXUART_IRDA)
1909 sport->use_irda = 1;
1910 }
1911
1912 static int serial_imx_probe(struct platform_device *pdev)
1913 {
1914 struct imx_port *sport;
1915 void __iomem *base;
1916 int ret = 0;
1917 struct resource *res;
1918
1919 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
1920 if (!sport)
1921 return -ENOMEM;
1922
1923 ret = serial_imx_probe_dt(sport, pdev);
1924 if (ret > 0)
1925 serial_imx_probe_pdata(sport, pdev);
1926 else if (ret < 0)
1927 return ret;
1928
1929 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1930 base = devm_ioremap_resource(&pdev->dev, res);
1931 if (IS_ERR(base))
1932 return PTR_ERR(base);
1933
1934 sport->port.dev = &pdev->dev;
1935 sport->port.mapbase = res->start;
1936 sport->port.membase = base;
1937 sport->port.type = PORT_IMX,
1938 sport->port.iotype = UPIO_MEM;
1939 sport->port.irq = platform_get_irq(pdev, 0);
1940 sport->rxirq = platform_get_irq(pdev, 0);
1941 sport->txirq = platform_get_irq(pdev, 1);
1942 sport->rtsirq = platform_get_irq(pdev, 2);
1943 sport->port.fifosize = 32;
1944 sport->port.ops = &imx_pops;
1945 sport->port.flags = UPF_BOOT_AUTOCONF;
1946 init_timer(&sport->timer);
1947 sport->timer.function = imx_timeout;
1948 sport->timer.data = (unsigned long)sport;
1949
1950 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1951 if (IS_ERR(sport->clk_ipg)) {
1952 ret = PTR_ERR(sport->clk_ipg);
1953 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
1954 return ret;
1955 }
1956
1957 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1958 if (IS_ERR(sport->clk_per)) {
1959 ret = PTR_ERR(sport->clk_per);
1960 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
1961 return ret;
1962 }
1963
1964 sport->port.uartclk = clk_get_rate(sport->clk_per);
1965
1966 /*
1967 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1968 * chips only have one interrupt.
1969 */
1970 if (sport->txirq > 0) {
1971 ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0,
1972 dev_name(&pdev->dev), sport);
1973 if (ret)
1974 return ret;
1975
1976 ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0,
1977 dev_name(&pdev->dev), sport);
1978 if (ret)
1979 return ret;
1980
1981 /* do not use RTS IRQ on IrDA */
1982 if (!USE_IRDA(sport)) {
1983 ret = devm_request_irq(&pdev->dev, sport->rtsirq,
1984 imx_rtsint, 0,
1985 dev_name(&pdev->dev), sport);
1986 if (ret)
1987 return ret;
1988 }
1989 } else {
1990 ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0,
1991 dev_name(&pdev->dev), sport);
1992 if (ret)
1993 return ret;
1994 }
1995
1996 imx_ports[sport->port.line] = sport;
1997
1998 platform_set_drvdata(pdev, sport);
1999
2000 return uart_add_one_port(&imx_reg, &sport->port);
2001 }
2002
2003 static int serial_imx_remove(struct platform_device *pdev)
2004 {
2005 struct imx_port *sport = platform_get_drvdata(pdev);
2006
2007 return uart_remove_one_port(&imx_reg, &sport->port);
2008 }
2009
2010 static struct platform_driver serial_imx_driver = {
2011 .probe = serial_imx_probe,
2012 .remove = serial_imx_remove,
2013
2014 .suspend = serial_imx_suspend,
2015 .resume = serial_imx_resume,
2016 .id_table = imx_uart_devtype,
2017 .driver = {
2018 .name = "imx-uart",
2019 .of_match_table = imx_uart_dt_ids,
2020 },
2021 };
2022
2023 static int __init imx_serial_init(void)
2024 {
2025 int ret = uart_register_driver(&imx_reg);
2026
2027 if (ret)
2028 return ret;
2029
2030 ret = platform_driver_register(&serial_imx_driver);
2031 if (ret != 0)
2032 uart_unregister_driver(&imx_reg);
2033
2034 return ret;
2035 }
2036
2037 static void __exit imx_serial_exit(void)
2038 {
2039 platform_driver_unregister(&serial_imx_driver);
2040 uart_unregister_driver(&imx_reg);
2041 }
2042
2043 module_init(imx_serial_init);
2044 module_exit(imx_serial_exit);
2045
2046 MODULE_AUTHOR("Sascha Hauer");
2047 MODULE_DESCRIPTION("IMX generic serial port driver");
2048 MODULE_LICENSE("GPL");
2049 MODULE_ALIAS("platform:imx-uart");
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