drivers/net/wireless/ath/ath5k/base.h

   1 /*-
   2  * Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer,
  10  *    without modification.
  11  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  12  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
  13  *    redistribution must be conditioned upon including a substantially
  14  *    similar Disclaimer requirement for further binary redistribution.
  15  * 3. Neither the names of the above-listed copyright holders nor the names
  16  *    of any contributors may be used to endorse or promote products derived
  17  *    from this software without specific prior written permission.
  18  *
  19  * Alternatively, this software may be distributed under the terms of the
  20  * GNU General Public License ("GPL") version 2 as published by the Free
  21  * Software Foundation.
  22  *
  23  * NO WARRANTY
  24  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  25  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  26  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
  27  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
  28  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
  29  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  30  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  31  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
  32  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  33  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  34  * THE POSSIBILITY OF SUCH DAMAGES.
  35  *
  36  */
  37
  38 /*
  39  * Defintions for the Atheros Wireless LAN controller driver.
  40  */
  41 #ifndef _DEV_ATH_ATHVAR_H
  42 #define _DEV_ATH_ATHVAR_H
  43
  44 #include <linux/interrupt.h>
  45 #include <linux/list.h>
  46 #include <linux/wireless.h>
  47 #include <linux/if_ether.h>
  48 #include <linux/leds.h>
  49 #include <linux/rfkill.h>
  50
  51 #include "ath5k.h"
  52 #include "debug.h"
  53
  54 #define ATH_RXBUF       40              /* number of RX buffers */
  55 #define ATH_TXBUF       200             /* number of TX buffers */
  56 #define ATH_BCBUF       1               /* number of beacon buffers */
  57
  58 struct ath5k_buf {
  59         struct list_head        list;
  60         struct ath5k_desc       *desc;  /* virtual addr of desc */
  61         dma_addr_t              daddr;  /* physical addr of desc */
  62         struct sk_buff          *skb;   /* skbuff for buf */
  63         dma_addr_t              skbaddr;/* physical addr of skb data */
  64 };
  65
  66 /*
  67  * Data transmit queue state.  One of these exists for each
  68  * hardware transmit queue.  Packets sent to us from above
  69  * are assigned to queues based on their priority.  Not all
  70  * devices support a complete set of hardware transmit queues.
  71  * For those devices the array sc_ac2q will map multiple
  72  * priorities to fewer hardware queues (typically all to one
  73  * hardware queue).
  74  */
  75 struct ath5k_txq {
  76         unsigned int            qnum;   /* hardware q number */
  77         u32                     *link;  /* link ptr in last TX desc */
  78         struct list_head        q;      /* transmit queue */
  79         spinlock_t              lock;   /* lock on q and link */
  80         bool                    setup;
  81 };
  82
  83 #define ATH5K_LED_MAX_NAME_LEN 31
  84
  85 /*
  86  * State for LED triggers
  87  */
  88 struct ath5k_led
  89 {
  90         char name[ATH5K_LED_MAX_NAME_LEN + 1];  /* name of the LED in sysfs */
  91         struct ath5k_softc *sc;                 /* driver state */
  92         struct led_classdev led_dev;            /* led classdev */
  93 };
  94
  95 /* Rfkill */
  96 struct ath5k_rfkill {
  97         /* GPIO PIN for rfkill */
  98         u16 gpio;
  99         /* polarity of rfkill GPIO PIN */
 100         bool polarity;
 101         /* RFKILL toggle tasklet */
 102         struct tasklet_struct toggleq;
 103 };
 104
 105 #if CHAN_DEBUG
 106 #define ATH_CHAN_MAX    (26+26+26+200+200)
 107 #else
 108 #define ATH_CHAN_MAX    (14+14+14+252+20)
 109 #endif
 110
 111 /* Software Carrier, keeps track of the driver state
 112  * associated with an instance of a device */
 113 struct ath5k_softc {
 114         struct pci_dev          *pdev;          /* for dma mapping */
 115         void __iomem            *iobase;        /* address of the device */
 116         struct mutex            lock;           /* dev-level lock */
 117         struct ieee80211_tx_queue_stats tx_stats[AR5K_NUM_TX_QUEUES];
 118         struct ieee80211_low_level_stats ll_stats;
 119         struct ieee80211_hw     *hw;            /* IEEE 802.11 common */
 120         struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
 121         struct ieee80211_channel channels[ATH_CHAN_MAX];
 122         struct ieee80211_rate   rates[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
 123         s8                      rate_idx[IEEE80211_NUM_BANDS][AR5K_MAX_RATES];
 124         enum nl80211_iftype     opmode;
 125         struct ath5k_hw         *ah;            /* Atheros HW */
 126
 127         struct ieee80211_supported_band         *curband;
 128
 129 #ifdef CONFIG_ATH5K_DEBUG
 130         struct ath5k_dbg_info   debug;          /* debug info */
 131 #endif /* CONFIG_ATH5K_DEBUG */
 132
 133         struct ath5k_buf        *bufptr;        /* allocated buffer ptr */
 134         struct ath5k_desc       *desc;          /* TX/RX descriptors */
 135         dma_addr_t              desc_daddr;     /* DMA (physical) address */
 136         size_t                  desc_len;       /* size of TX/RX descriptors */
 137         u16                     cachelsz;       /* cache line size */
 138
 139         DECLARE_BITMAP(status, 5);
 140 #define ATH_STAT_INVALID        0               /* disable hardware accesses */
 141 #define ATH_STAT_MRRETRY        1               /* multi-rate retry support */
 142 #define ATH_STAT_PROMISC        2
 143 #define ATH_STAT_LEDSOFT        3               /* enable LED gpio status */
 144 #define ATH_STAT_STARTED        4               /* opened & irqs enabled */
 145
 146         unsigned int            filter_flags;   /* HW flags, AR5K_RX_FILTER_* */
 147         unsigned int            curmode;        /* current phy mode */
 148         struct ieee80211_channel *curchan;      /* current h/w channel */
 149
 150         struct ieee80211_vif *vif;
 151
 152         enum ath5k_int          imask;          /* interrupt mask copy */
 153
 154         DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */
 155
 156         u8                      bssidmask[ETH_ALEN];
 157
 158         unsigned int            led_pin,        /* GPIO pin for driving LED */
 159                                 led_on;         /* pin setting for LED on */
 160
 161         struct tasklet_struct   restq;          /* reset tasklet */
 162
 163         unsigned int            rxbufsize;      /* rx size based on mtu */
 164         struct list_head        rxbuf;          /* receive buffer */
 165         spinlock_t              rxbuflock;
 166         u32                     *rxlink;        /* link ptr in last RX desc */
 167         struct tasklet_struct   rxtq;           /* rx intr tasklet */
 168         struct ath5k_led        rx_led;         /* rx led */
 169
 170         struct list_head        txbuf;          /* transmit buffer */
 171         spinlock_t              txbuflock;
 172         unsigned int            txbuf_len;      /* buf count in txbuf list */
 173         struct ath5k_txq        txqs[AR5K_NUM_TX_QUEUES];       /* tx queues */
 174         struct ath5k_txq        *txq;           /* main tx queue */
 175         struct tasklet_struct   txtq;           /* tx intr tasklet */
 176         struct ath5k_led        tx_led;         /* tx led */
 177
 178         struct ath5k_rfkill     rf_kill;
 179
 180         struct tasklet_struct   calib;          /* calibration tasklet */
 181
 182         spinlock_t              block;          /* protects beacon */
 183         struct tasklet_struct   beacontq;       /* beacon intr tasklet */
 184         struct ath5k_buf        *bbuf;          /* beacon buffer */
 185         unsigned int            bhalq,          /* SW q for outgoing beacons */
 186                                 bmisscount,     /* missed beacon transmits */
 187                                 bintval,        /* beacon interval in TU */
 188                                 bsent;
 189         unsigned int            nexttbtt;       /* next beacon time in TU */
 190         struct ath5k_txq        *cabq;          /* content after beacon */
 191
 192         int                     power_level;    /* Requested tx power in dbm */
 193         bool                    assoc;          /* assocate state */
 194         bool                    enable_beacon;  /* true if beacons are on */
 195 };
 196
 197 #define ath5k_hw_hasbssidmask(_ah) \
 198         (ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
 199 #define ath5k_hw_hasveol(_ah) \
 200         (ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)
 201
 202 #endif