drivers/gpu/drm/vc4/vc4_hdmi.c

   1 /*
   2  * Copyright (C) 2015 Broadcom
   3  * Copyright (c) 2014 The Linux Foundation. All rights reserved.
   4  * Copyright (C) 2013 Red Hat
   5  * Author: Rob Clark <robdclark@gmail.com>
   6  *
   7  * This program is free software; you can redistribute it and/or modify it
   8  * under the terms of the GNU General Public License version 2 as published by
   9  * the Free Software Foundation.
  10  *
  11  * This program is distributed in the hope that it will be useful, but WITHOUT
  12  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14  * more details.
  15  *
  16  * You should have received a copy of the GNU General Public License along with
  17  * this program.  If not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 /**
  21  * DOC: VC4 Falcon HDMI module
  22  *
  23  * The HDMI core has a state machine and a PHY.  Most of the unit
  24  * operates off of the HSM clock from CPRMAN.  It also internally uses
  25  * the PLLH_PIX clock for the PHY.
  26  */
  27
  28 #include "drm_atomic_helper.h"
  29 #include "drm_crtc_helper.h"
  30 #include "drm_edid.h"
  31 #include "linux/clk.h"
  32 #include "linux/component.h"
  33 #include "linux/i2c.h"
  34 #include "linux/of_gpio.h"
  35 #include "linux/of_platform.h"
  36 #include "vc4_drv.h"
  37 #include "vc4_regs.h"
  38
  39 /* General HDMI hardware state. */
  40 struct vc4_hdmi {
  41         struct platform_device *pdev;
  42
  43         struct drm_encoder *encoder;
  44         struct drm_connector *connector;
  45
  46         struct i2c_adapter *ddc;
  47         void __iomem *hdmicore_regs;
  48         void __iomem *hd_regs;
  49         int hpd_gpio;
  50         bool hpd_active_low;
  51
  52         struct clk *pixel_clock;
  53         struct clk *hsm_clock;
  54 };
  55
  56 #define HDMI_READ(offset) readl(vc4->hdmi->hdmicore_regs + offset)
  57 #define HDMI_WRITE(offset, val) writel(val, vc4->hdmi->hdmicore_regs + offset)
  58 #define HD_READ(offset) readl(vc4->hdmi->hd_regs + offset)
  59 #define HD_WRITE(offset, val) writel(val, vc4->hdmi->hd_regs + offset)
  60
  61 /* VC4 HDMI encoder KMS struct */
  62 struct vc4_hdmi_encoder {
  63         struct vc4_encoder base;
  64         bool hdmi_monitor;
  65 };
  66
  67 static inline struct vc4_hdmi_encoder *
  68 to_vc4_hdmi_encoder(struct drm_encoder *encoder)
  69 {
  70         return container_of(encoder, struct vc4_hdmi_encoder, base.base);
  71 }
  72
  73 /* VC4 HDMI connector KMS struct */
  74 struct vc4_hdmi_connector {
  75         struct drm_connector base;
  76
  77         /* Since the connector is attached to just the one encoder,
  78          * this is the reference to it so we can do the best_encoder()
  79          * hook.
  80          */
  81         struct drm_encoder *encoder;
  82 };
  83
  84 static inline struct vc4_hdmi_connector *
  85 to_vc4_hdmi_connector(struct drm_connector *connector)
  86 {
  87         return container_of(connector, struct vc4_hdmi_connector, base);
  88 }
  89
  90 #define HDMI_REG(reg) { reg, #reg }
  91 static const struct {
  92         u32 reg;
  93         const char *name;
  94 } hdmi_regs[] = {
  95         HDMI_REG(VC4_HDMI_CORE_REV),
  96         HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
  97         HDMI_REG(VC4_HDMI_HOTPLUG_INT),
  98         HDMI_REG(VC4_HDMI_HOTPLUG),
  99         HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
 100         HDMI_REG(VC4_HDMI_HORZA),
 101         HDMI_REG(VC4_HDMI_HORZB),
 102         HDMI_REG(VC4_HDMI_FIFO_CTL),
 103         HDMI_REG(VC4_HDMI_SCHEDULER_CONTROL),
 104         HDMI_REG(VC4_HDMI_VERTA0),
 105         HDMI_REG(VC4_HDMI_VERTA1),
 106         HDMI_REG(VC4_HDMI_VERTB0),
 107         HDMI_REG(VC4_HDMI_VERTB1),
 108         HDMI_REG(VC4_HDMI_TX_PHY_RESET_CTL),
 109 };
 110
 111 static const struct {
 112         u32 reg;
 113         const char *name;
 114 } hd_regs[] = {
 115         HDMI_REG(VC4_HD_M_CTL),
 116         HDMI_REG(VC4_HD_MAI_CTL),
 117         HDMI_REG(VC4_HD_VID_CTL),
 118         HDMI_REG(VC4_HD_CSC_CTL),
 119         HDMI_REG(VC4_HD_FRAME_COUNT),
 120 };
 121
 122 #ifdef CONFIG_DEBUG_FS
 123 int vc4_hdmi_debugfs_regs(struct seq_file *m, void *unused)
 124 {
 125         struct drm_info_node *node = (struct drm_info_node *)m->private;
 126         struct drm_device *dev = node->minor->dev;
 127         struct vc4_dev *vc4 = to_vc4_dev(dev);
 128         int i;
 129
 130         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 131                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 132                            hdmi_regs[i].name, hdmi_regs[i].reg,
 133                            HDMI_READ(hdmi_regs[i].reg));
 134         }
 135
 136         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 137                 seq_printf(m, "%s (0x%04x): 0x%08x\n",
 138                            hd_regs[i].name, hd_regs[i].reg,
 139                            HD_READ(hd_regs[i].reg));
 140         }
 141
 142         return 0;
 143 }
 144 #endif /* CONFIG_DEBUG_FS */
 145
 146 static void vc4_hdmi_dump_regs(struct drm_device *dev)
 147 {
 148         struct vc4_dev *vc4 = to_vc4_dev(dev);
 149         int i;
 150
 151         for (i = 0; i < ARRAY_SIZE(hdmi_regs); i++) {
 152                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 153                          hdmi_regs[i].reg, hdmi_regs[i].name,
 154                          HDMI_READ(hdmi_regs[i].reg));
 155         }
 156         for (i = 0; i < ARRAY_SIZE(hd_regs); i++) {
 157                 DRM_INFO("0x%04x (%s): 0x%08x\n",
 158                          hd_regs[i].reg, hd_regs[i].name,
 159                          HD_READ(hd_regs[i].reg));
 160         }
 161 }
 162
 163 static enum drm_connector_status
 164 vc4_hdmi_connector_detect(struct drm_connector *connector, bool force)
 165 {
 166         struct drm_device *dev = connector->dev;
 167         struct vc4_dev *vc4 = to_vc4_dev(dev);
 168
 169         if (vc4->hdmi->hpd_gpio) {
 170                 if (gpio_get_value_cansleep(vc4->hdmi->hpd_gpio) ^
 171                     vc4->hdmi->hpd_active_low)
 172                         return connector_status_connected;
 173                 else
 174                         return connector_status_disconnected;
 175         }
 176
 177         if (HDMI_READ(VC4_HDMI_HOTPLUG) & VC4_HDMI_HOTPLUG_CONNECTED)
 178                 return connector_status_connected;
 179         else
 180                 return connector_status_disconnected;
 181 }
 182
 183 static void vc4_hdmi_connector_destroy(struct drm_connector *connector)
 184 {
 185         drm_connector_unregister(connector);
 186         drm_connector_cleanup(connector);
 187 }
 188
 189 static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
 190 {
 191         struct vc4_hdmi_connector *vc4_connector =
 192                 to_vc4_hdmi_connector(connector);
 193         struct drm_encoder *encoder = vc4_connector->encoder;
 194         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 195         struct drm_device *dev = connector->dev;
 196         struct vc4_dev *vc4 = to_vc4_dev(dev);
 197         int ret = 0;
 198         struct edid *edid;
 199
 200         edid = drm_get_edid(connector, vc4->hdmi->ddc);
 201         if (!edid)
 202                 return -ENODEV;
 203
 204         vc4_encoder->hdmi_monitor = drm_detect_hdmi_monitor(edid);
 205         drm_mode_connector_update_edid_property(connector, edid);
 206         ret = drm_add_edid_modes(connector, edid);
 207
 208         return ret;
 209 }
 210
 211 /*
 212  * drm_helper_probe_single_connector_modes() applies drm_mode_set_crtcinfo to
 213  * all modes with flag CRTC_INTERLACE_HALVE_V. We don't want this, as it
 214  * screws up vblank timestamping for interlaced modes, so fix it up.
 215  */
 216 static int vc4_hdmi_connector_probe_modes(struct drm_connector *connector,
 217                                           uint32_t maxX, uint32_t maxY)
 218 {
 219         struct drm_display_mode *mode;
 220         int count;
 221
 222         count = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
 223         if (count == 0)
 224                 return 0;
 225
 226         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed adapted modes :\n",
 227                       connector->base.id, connector->name);
 228         list_for_each_entry(mode, &connector->modes, head) {
 229                 drm_mode_set_crtcinfo(mode, 0);
 230                 drm_mode_debug_printmodeline(mode);
 231         }
 232
 233         return count;
 234 }
 235
 236 static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
 237         .dpms = drm_atomic_helper_connector_dpms,
 238         .detect = vc4_hdmi_connector_detect,
 239         .fill_modes = vc4_hdmi_connector_probe_modes,
 240         .destroy = vc4_hdmi_connector_destroy,
 241         .reset = drm_atomic_helper_connector_reset,
 242         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 243         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 244 };
 245
 246 static const struct drm_connector_helper_funcs vc4_hdmi_connector_helper_funcs = {
 247         .get_modes = vc4_hdmi_connector_get_modes,
 248 };
 249
 250 static struct drm_connector *vc4_hdmi_connector_init(struct drm_device *dev,
 251                                                      struct drm_encoder *encoder)
 252 {
 253         struct drm_connector *connector = NULL;
 254         struct vc4_hdmi_connector *hdmi_connector;
 255         int ret = 0;
 256
 257         hdmi_connector = devm_kzalloc(dev->dev, sizeof(*hdmi_connector),
 258                                       GFP_KERNEL);
 259         if (!hdmi_connector) {
 260                 ret = -ENOMEM;
 261                 goto fail;
 262         }
 263         connector = &hdmi_connector->base;
 264
 265         hdmi_connector->encoder = encoder;
 266
 267         drm_connector_init(dev, connector, &vc4_hdmi_connector_funcs,
 268                            DRM_MODE_CONNECTOR_HDMIA);
 269         drm_connector_helper_add(connector, &vc4_hdmi_connector_helper_funcs);
 270
 271         connector->polled = (DRM_CONNECTOR_POLL_CONNECT |
 272                              DRM_CONNECTOR_POLL_DISCONNECT);
 273
 274         connector->interlace_allowed = 1;
 275         connector->doublescan_allowed = 0;
 276
 277         drm_mode_connector_attach_encoder(connector, encoder);
 278
 279         return connector;
 280
 281  fail:
 282         if (connector)
 283                 vc4_hdmi_connector_destroy(connector);
 284
 285         return ERR_PTR(ret);
 286 }
 287
 288 static void vc4_hdmi_encoder_destroy(struct drm_encoder *encoder)
 289 {
 290         drm_encoder_cleanup(encoder);
 291 }
 292
 293 static const struct drm_encoder_funcs vc4_hdmi_encoder_funcs = {
 294         .destroy = vc4_hdmi_encoder_destroy,
 295 };
 296
 297 static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder,
 298                                       struct drm_display_mode *unadjusted_mode,
 299                                       struct drm_display_mode *mode)
 300 {
 301         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 302         struct drm_device *dev = encoder->dev;
 303         struct vc4_dev *vc4 = to_vc4_dev(dev);
 304         bool debug_dump_regs = false;
 305         bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
 306         bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
 307         u32 vactive = (mode->vdisplay >>
 308                        ((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0));
 309         u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
 310                                    VC4_HDMI_VERTA_VSP) |
 311                      VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
 312                                    VC4_HDMI_VERTA_VFP) |
 313                      VC4_SET_FIELD(vactive, VC4_HDMI_VERTA_VAL));
 314         u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
 315                      VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
 316                                    VC4_HDMI_VERTB_VBP));
 317         u32 csc_ctl;
 318
 319         if (debug_dump_regs) {
 320                 DRM_INFO("HDMI regs before:\n");
 321                 vc4_hdmi_dump_regs(dev);
 322         }
 323
 324         HD_WRITE(VC4_HD_VID_CTL, 0);
 325
 326         clk_set_rate(vc4->hdmi->pixel_clock, mode->clock * 1000);
 327
 328         HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 329                    HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 330                    VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT |
 331                    VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS);
 332
 333         HDMI_WRITE(VC4_HDMI_HORZA,
 334                    (vsync_pos ? VC4_HDMI_HORZA_VPOS : 0) |
 335                    (hsync_pos ? VC4_HDMI_HORZA_HPOS : 0) |
 336                    VC4_SET_FIELD(mode->hdisplay, VC4_HDMI_HORZA_HAP));
 337
 338         HDMI_WRITE(VC4_HDMI_HORZB,
 339                    VC4_SET_FIELD(mode->htotal - mode->hsync_end,
 340                                  VC4_HDMI_HORZB_HBP) |
 341                    VC4_SET_FIELD(mode->hsync_end - mode->hsync_start,
 342                                  VC4_HDMI_HORZB_HSP) |
 343                    VC4_SET_FIELD(mode->hsync_start - mode->hdisplay,
 344                                  VC4_HDMI_HORZB_HFP));
 345
 346         HDMI_WRITE(VC4_HDMI_VERTA0, verta);
 347         HDMI_WRITE(VC4_HDMI_VERTA1, verta);
 348
 349         HDMI_WRITE(VC4_HDMI_VERTB0, vertb);
 350         HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
 351
 352         HD_WRITE(VC4_HD_VID_CTL,
 353                  (vsync_pos ? 0 : VC4_HD_VID_CTL_VSYNC_LOW) |
 354                  (hsync_pos ? 0 : VC4_HD_VID_CTL_HSYNC_LOW));
 355
 356         csc_ctl = VC4_SET_FIELD(VC4_HD_CSC_CTL_ORDER_BGR,
 357                                 VC4_HD_CSC_CTL_ORDER);
 358
 359         if (vc4_encoder->hdmi_monitor && drm_match_cea_mode(mode) > 1) {
 360                 /* CEA VICs other than #1 requre limited range RGB
 361                  * output.  Apply a colorspace conversion to squash
 362                  * 0-255 down to 16-235.  The matrix here is:
 363                  *
 364                  * [ 0      0      0.8594 16]
 365                  * [ 0      0.8594 0      16]
 366                  * [ 0.8594 0      0      16]
 367                  * [ 0      0      0       1]
 368                  */
 369                 csc_ctl |= VC4_HD_CSC_CTL_ENABLE;
 370                 csc_ctl |= VC4_HD_CSC_CTL_RGB2YCC;
 371                 csc_ctl |= VC4_SET_FIELD(VC4_HD_CSC_CTL_MODE_CUSTOM,
 372                                          VC4_HD_CSC_CTL_MODE);
 373
 374                 HD_WRITE(VC4_HD_CSC_12_11, (0x000 << 16) | 0x000);
 375                 HD_WRITE(VC4_HD_CSC_14_13, (0x100 << 16) | 0x6e0);
 376                 HD_WRITE(VC4_HD_CSC_22_21, (0x6e0 << 16) | 0x000);
 377                 HD_WRITE(VC4_HD_CSC_24_23, (0x100 << 16) | 0x000);
 378                 HD_WRITE(VC4_HD_CSC_32_31, (0x000 << 16) | 0x6e0);
 379                 HD_WRITE(VC4_HD_CSC_34_33, (0x100 << 16) | 0x000);
 380         }
 381
 382         /* The RGB order applies even when CSC is disabled. */
 383         HD_WRITE(VC4_HD_CSC_CTL, csc_ctl);
 384
 385         HDMI_WRITE(VC4_HDMI_FIFO_CTL, VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N);
 386
 387         if (debug_dump_regs) {
 388                 DRM_INFO("HDMI regs after:\n");
 389                 vc4_hdmi_dump_regs(dev);
 390         }
 391 }
 392
 393 static void vc4_hdmi_encoder_disable(struct drm_encoder *encoder)
 394 {
 395         struct drm_device *dev = encoder->dev;
 396         struct vc4_dev *vc4 = to_vc4_dev(dev);
 397
 398         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 399         HD_WRITE(VC4_HD_VID_CTL,
 400                  HD_READ(VC4_HD_VID_CTL) & ~VC4_HD_VID_CTL_ENABLE);
 401 }
 402
 403 static void vc4_hdmi_encoder_enable(struct drm_encoder *encoder)
 404 {
 405         struct vc4_hdmi_encoder *vc4_encoder = to_vc4_hdmi_encoder(encoder);
 406         struct drm_device *dev = encoder->dev;
 407         struct vc4_dev *vc4 = to_vc4_dev(dev);
 408         int ret;
 409
 410         HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0);
 411
 412         HD_WRITE(VC4_HD_VID_CTL,
 413                  HD_READ(VC4_HD_VID_CTL) |
 414                  VC4_HD_VID_CTL_ENABLE |
 415                  VC4_HD_VID_CTL_UNDERFLOW_ENABLE |
 416                  VC4_HD_VID_CTL_FRAME_COUNTER_RESET);
 417
 418         if (vc4_encoder->hdmi_monitor) {
 419                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 420                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 421                            VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 422
 423                 ret = wait_for(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 424                                VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE, 1);
 425                 WARN_ONCE(ret, "Timeout waiting for "
 426                           "VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 427         } else {
 428                 HDMI_WRITE(VC4_HDMI_RAM_PACKET_CONFIG,
 429                            HDMI_READ(VC4_HDMI_RAM_PACKET_CONFIG) &
 430                            ~(VC4_HDMI_RAM_PACKET_ENABLE));
 431                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 432                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 433                            ~VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI);
 434
 435                 ret = wait_for(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 436                                  VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE), 1);
 437                 WARN_ONCE(ret, "Timeout waiting for "
 438                           "!VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE\n");
 439         }
 440
 441         if (vc4_encoder->hdmi_monitor) {
 442                 u32 drift;
 443
 444                 WARN_ON(!(HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) &
 445                           VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE));
 446                 HDMI_WRITE(VC4_HDMI_SCHEDULER_CONTROL,
 447                            HDMI_READ(VC4_HDMI_SCHEDULER_CONTROL) |
 448                            VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT);
 449
 450                 /* XXX: Set HDMI_RAM_PACKET_CONFIG (1 << 16) and set
 451                  * up the infoframe.
 452                  */
 453
 454                 drift = HDMI_READ(VC4_HDMI_FIFO_CTL);
 455                 drift &= VC4_HDMI_FIFO_VALID_WRITE_MASK;
 456
 457                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 458                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 459                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 460                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 461                 udelay(1000);
 462                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 463                            drift & ~VC4_HDMI_FIFO_CTL_RECENTER);
 464                 HDMI_WRITE(VC4_HDMI_FIFO_CTL,
 465                            drift | VC4_HDMI_FIFO_CTL_RECENTER);
 466
 467                 ret = wait_for(HDMI_READ(VC4_HDMI_FIFO_CTL) &
 468                                VC4_HDMI_FIFO_CTL_RECENTER_DONE, 1);
 469                 WARN_ONCE(ret, "Timeout waiting for "
 470                           "VC4_HDMI_FIFO_CTL_RECENTER_DONE");
 471         }
 472 }
 473
 474 static const struct drm_encoder_helper_funcs vc4_hdmi_encoder_helper_funcs = {
 475         .mode_set = vc4_hdmi_encoder_mode_set,
 476         .disable = vc4_hdmi_encoder_disable,
 477         .enable = vc4_hdmi_encoder_enable,
 478 };
 479
 480 static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
 481 {
 482         struct platform_device *pdev = to_platform_device(dev);
 483         struct drm_device *drm = dev_get_drvdata(master);
 484         struct vc4_dev *vc4 = drm->dev_private;
 485         struct vc4_hdmi *hdmi;
 486         struct vc4_hdmi_encoder *vc4_hdmi_encoder;
 487         struct device_node *ddc_node;
 488         u32 value;
 489         int ret;
 490
 491         hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
 492         if (!hdmi)
 493                 return -ENOMEM;
 494
 495         vc4_hdmi_encoder = devm_kzalloc(dev, sizeof(*vc4_hdmi_encoder),
 496                                         GFP_KERNEL);
 497         if (!vc4_hdmi_encoder)
 498                 return -ENOMEM;
 499         vc4_hdmi_encoder->base.type = VC4_ENCODER_TYPE_HDMI;
 500         hdmi->encoder = &vc4_hdmi_encoder->base.base;
 501
 502         hdmi->pdev = pdev;
 503         hdmi->hdmicore_regs = vc4_ioremap_regs(pdev, 0);
 504         if (IS_ERR(hdmi->hdmicore_regs))
 505                 return PTR_ERR(hdmi->hdmicore_regs);
 506
 507         hdmi->hd_regs = vc4_ioremap_regs(pdev, 1);
 508         if (IS_ERR(hdmi->hd_regs))
 509                 return PTR_ERR(hdmi->hd_regs);
 510
 511         hdmi->pixel_clock = devm_clk_get(dev, "pixel");
 512         if (IS_ERR(hdmi->pixel_clock)) {
 513                 DRM_ERROR("Failed to get pixel clock\n");
 514                 return PTR_ERR(hdmi->pixel_clock);
 515         }
 516         hdmi->hsm_clock = devm_clk_get(dev, "hdmi");
 517         if (IS_ERR(hdmi->hsm_clock)) {
 518                 DRM_ERROR("Failed to get HDMI state machine clock\n");
 519                 return PTR_ERR(hdmi->hsm_clock);
 520         }
 521
 522         ddc_node = of_parse_phandle(dev->of_node, "ddc", 0);
 523         if (!ddc_node) {
 524                 DRM_ERROR("Failed to find ddc node in device tree\n");
 525                 return -ENODEV;
 526         }
 527
 528         hdmi->ddc = of_find_i2c_adapter_by_node(ddc_node);
 529         of_node_put(ddc_node);
 530         if (!hdmi->ddc) {
 531                 DRM_DEBUG("Failed to get ddc i2c adapter by node\n");
 532                 return -EPROBE_DEFER;
 533         }
 534
 535         /* Enable the clocks at startup.  We can't quite recover from
 536          * turning off the pixel clock during disable/enables yet, so
 537          * it's always running.
 538          */
 539         ret = clk_prepare_enable(hdmi->pixel_clock);
 540         if (ret) {
 541                 DRM_ERROR("Failed to turn on pixel clock: %d\n", ret);
 542                 goto err_put_i2c;
 543         }
 544
 545         /* This is the rate that is set by the firmware.  The number
 546          * needs to be a bit higher than the pixel clock rate
 547          * (generally 148.5Mhz).
 548          */
 549         ret = clk_set_rate(hdmi->hsm_clock, 163682864);
 550         if (ret) {
 551                 DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
 552                 goto err_unprepare_pix;
 553         }
 554
 555         ret = clk_prepare_enable(hdmi->hsm_clock);
 556         if (ret) {
 557                 DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
 558                           ret);
 559                 goto err_unprepare_pix;
 560         }
 561
 562         /* Only use the GPIO HPD pin if present in the DT, otherwise
 563          * we'll use the HDMI core's register.
 564          */
 565         if (of_find_property(dev->of_node, "hpd-gpios", &value)) {
 566                 enum of_gpio_flags hpd_gpio_flags;
 567
 568                 hdmi->hpd_gpio = of_get_named_gpio_flags(dev->of_node,
 569                                                          "hpd-gpios", 0,
 570                                                          &hpd_gpio_flags);
 571                 if (hdmi->hpd_gpio < 0) {
 572                         ret = hdmi->hpd_gpio;
 573                         goto err_unprepare_hsm;
 574                 }
 575
 576                 hdmi->hpd_active_low = hpd_gpio_flags & OF_GPIO_ACTIVE_LOW;
 577         }
 578
 579         vc4->hdmi = hdmi;
 580
 581         /* HDMI core must be enabled. */
 582         if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
 583                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
 584                 udelay(1);
 585                 HD_WRITE(VC4_HD_M_CTL, 0);
 586
 587                 HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
 588
 589                 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
 590                            VC4_HDMI_SW_RESET_HDMI |
 591                            VC4_HDMI_SW_RESET_FORMAT_DETECT);
 592
 593                 HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
 594
 595                 /* PHY should be in reset, like
 596                  * vc4_hdmi_encoder_disable() does.
 597                  */
 598                 HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
 599         }
 600
 601         drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
 602                          DRM_MODE_ENCODER_TMDS, NULL);
 603         drm_encoder_helper_add(hdmi->encoder, &vc4_hdmi_encoder_helper_funcs);
 604
 605         hdmi->connector = vc4_hdmi_connector_init(drm, hdmi->encoder);
 606         if (IS_ERR(hdmi->connector)) {
 607                 ret = PTR_ERR(hdmi->connector);
 608                 goto err_destroy_encoder;
 609         }
 610
 611         return 0;
 612
 613 err_destroy_encoder:
 614         vc4_hdmi_encoder_destroy(hdmi->encoder);
 615 err_unprepare_hsm:
 616         clk_disable_unprepare(hdmi->hsm_clock);
 617 err_unprepare_pix:
 618         clk_disable_unprepare(hdmi->pixel_clock);
 619 err_put_i2c:
 620         put_device(&hdmi->ddc->dev);
 621
 622         return ret;
 623 }
 624
 625 static void vc4_hdmi_unbind(struct device *dev, struct device *master,
 626                             void *data)
 627 {
 628         struct drm_device *drm = dev_get_drvdata(master);
 629         struct vc4_dev *vc4 = drm->dev_private;
 630         struct vc4_hdmi *hdmi = vc4->hdmi;
 631
 632         vc4_hdmi_connector_destroy(hdmi->connector);
 633         vc4_hdmi_encoder_destroy(hdmi->encoder);
 634
 635         clk_disable_unprepare(hdmi->pixel_clock);
 636         clk_disable_unprepare(hdmi->hsm_clock);
 637         put_device(&hdmi->ddc->dev);
 638
 639         vc4->hdmi = NULL;
 640 }
 641
 642 static const struct component_ops vc4_hdmi_ops = {
 643         .bind   = vc4_hdmi_bind,
 644         .unbind = vc4_hdmi_unbind,
 645 };
 646
 647 static int vc4_hdmi_dev_probe(struct platform_device *pdev)
 648 {
 649         return component_add(&pdev->dev, &vc4_hdmi_ops);
 650 }
 651
 652 static int vc4_hdmi_dev_remove(struct platform_device *pdev)
 653 {
 654         component_del(&pdev->dev, &vc4_hdmi_ops);
 655         return 0;
 656 }
 657
 658 static const struct of_device_id vc4_hdmi_dt_match[] = {
 659         { .compatible = "brcm,bcm2835-hdmi" },
 660         {}
 661 };
 662
 663 struct platform_driver vc4_hdmi_driver = {
 664         .probe = vc4_hdmi_dev_probe,
 665         .remove = vc4_hdmi_dev_remove,
 666         .driver = {
 667                 .name = "vc4_hdmi",
 668                 .of_match_table = vc4_hdmi_dt_match,
 669         },
 670 };