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Merge remote-tracking branches 'spi/topic/imx', 'spi/topic/init', 'spi/topic/mpc512x...
[linux-2.6/btrfs-unstable.git] / drivers / spi / spi-fsl-espi.c
blob6fb2b75df821e78f80a0f6c1bf4c64e45e4292d5
1 /*
2 * Freescale eSPI controller driver.
3 *
4 * Copyright 2010 Freescale Semiconductor, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11 #include <linux/module.h>
12 #include <linux/delay.h>
13 #include <linux/irq.h>
14 #include <linux/spi/spi.h>
15 #include <linux/platform_device.h>
16 #include <linux/fsl_devices.h>
17 #include <linux/mm.h>
18 #include <linux/of.h>
19 #include <linux/of_address.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_platform.h>
22 #include <linux/interrupt.h>
23 #include <linux/err.h>
24 #include <sysdev/fsl_soc.h>
25
26 #include "spi-fsl-lib.h"
27
28 /* eSPI Controller registers */
29 struct fsl_espi_reg {
30 __be32 mode; /* 0x000 - eSPI mode register */
31 __be32 event; /* 0x004 - eSPI event register */
32 __be32 mask; /* 0x008 - eSPI mask register */
33 __be32 command; /* 0x00c - eSPI command register */
34 __be32 transmit; /* 0x010 - eSPI transmit FIFO access register*/
35 __be32 receive; /* 0x014 - eSPI receive FIFO access register*/
36 u8 res[8]; /* 0x018 - 0x01c reserved */
37 __be32 csmode[4]; /* 0x020 - 0x02c eSPI cs mode register */
38 };
39
40 struct fsl_espi_transfer {
41 const void *tx_buf;
42 void *rx_buf;
43 unsigned len;
44 unsigned n_tx;
45 unsigned n_rx;
46 unsigned actual_length;
47 int status;
48 };
49
50 /* eSPI Controller mode register definitions */
51 #define SPMODE_ENABLE (1 << 31)
52 #define SPMODE_LOOP (1 << 30)
53 #define SPMODE_TXTHR(x) ((x) << 8)
54 #define SPMODE_RXTHR(x) ((x) << 0)
55
56 /* eSPI Controller CS mode register definitions */
57 #define CSMODE_CI_INACTIVEHIGH (1 << 31)
58 #define CSMODE_CP_BEGIN_EDGECLK (1 << 30)
59 #define CSMODE_REV (1 << 29)
60 #define CSMODE_DIV16 (1 << 28)
61 #define CSMODE_PM(x) ((x) << 24)
62 #define CSMODE_POL_1 (1 << 20)
63 #define CSMODE_LEN(x) ((x) << 16)
64 #define CSMODE_BEF(x) ((x) << 12)
65 #define CSMODE_AFT(x) ((x) << 8)
66 #define CSMODE_CG(x) ((x) << 3)
67
68 /* Default mode/csmode for eSPI controller */
69 #define SPMODE_INIT_VAL (SPMODE_TXTHR(4) | SPMODE_RXTHR(3))
70 #define CSMODE_INIT_VAL (CSMODE_POL_1 | CSMODE_BEF(0) \
71 | CSMODE_AFT(0) | CSMODE_CG(1))
72
73 /* SPIE register values */
74 #define SPIE_NE 0x00000200 /* Not empty */
75 #define SPIE_NF 0x00000100 /* Not full */
76
77 /* SPIM register values */
78 #define SPIM_NE 0x00000200 /* Not empty */
79 #define SPIM_NF 0x00000100 /* Not full */
80 #define SPIE_RXCNT(reg) ((reg >> 24) & 0x3F)
81 #define SPIE_TXCNT(reg) ((reg >> 16) & 0x3F)
82
83 /* SPCOM register values */
84 #define SPCOM_CS(x) ((x) << 30)
85 #define SPCOM_TRANLEN(x) ((x) << 0)
86 #define SPCOM_TRANLEN_MAX 0xFFFF /* Max transaction length */
87
88 static void fsl_espi_change_mode(struct spi_device *spi)
89 {
90 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
91 struct spi_mpc8xxx_cs *cs = spi->controller_state;
92 struct fsl_espi_reg *reg_base = mspi->reg_base;
93 __be32 __iomem *mode = &reg_base->csmode[spi->chip_select];
94 __be32 __iomem *espi_mode = &reg_base->mode;
95 u32 tmp;
96 unsigned long flags;
97
98 /* Turn off IRQs locally to minimize time that SPI is disabled. */
99 local_irq_save(flags);
100
101 /* Turn off SPI unit prior changing mode */
102 tmp = mpc8xxx_spi_read_reg(espi_mode);
103 mpc8xxx_spi_write_reg(espi_mode, tmp & ~SPMODE_ENABLE);
104 mpc8xxx_spi_write_reg(mode, cs->hw_mode);
105 mpc8xxx_spi_write_reg(espi_mode, tmp);
106
107 local_irq_restore(flags);
108 }
109
110 static u32 fsl_espi_tx_buf_lsb(struct mpc8xxx_spi *mpc8xxx_spi)
111 {
112 u32 data;
113 u16 data_h;
114 u16 data_l;
115 const u32 *tx = mpc8xxx_spi->tx;
116
117 if (!tx)
118 return 0;
119
120 data = *tx++ << mpc8xxx_spi->tx_shift;
121 data_l = data & 0xffff;
122 data_h = (data >> 16) & 0xffff;
123 swab16s(&data_l);
124 swab16s(&data_h);
125 data = data_h | data_l;
126
127 mpc8xxx_spi->tx = tx;
128 return data;
129 }
130
131 static int fsl_espi_setup_transfer(struct spi_device *spi,
132 struct spi_transfer *t)
133 {
134 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
135 int bits_per_word = 0;
136 u8 pm;
137 u32 hz = 0;
138 struct spi_mpc8xxx_cs *cs = spi->controller_state;
139
140 if (t) {
141 bits_per_word = t->bits_per_word;
142 hz = t->speed_hz;
143 }
144
145 /* spi_transfer level calls that work per-word */
146 if (!bits_per_word)
147 bits_per_word = spi->bits_per_word;
148
149 if (!hz)
150 hz = spi->max_speed_hz;
151
152 cs->rx_shift = 0;
153 cs->tx_shift = 0;
154 cs->get_rx = mpc8xxx_spi_rx_buf_u32;
155 cs->get_tx = mpc8xxx_spi_tx_buf_u32;
156 if (bits_per_word <= 8) {
157 cs->rx_shift = 8 - bits_per_word;
158 } else {
159 cs->rx_shift = 16 - bits_per_word;
160 if (spi->mode & SPI_LSB_FIRST)
161 cs->get_tx = fsl_espi_tx_buf_lsb;
162 }
163
164 mpc8xxx_spi->rx_shift = cs->rx_shift;
165 mpc8xxx_spi->tx_shift = cs->tx_shift;
166 mpc8xxx_spi->get_rx = cs->get_rx;
167 mpc8xxx_spi->get_tx = cs->get_tx;
168
169 bits_per_word = bits_per_word - 1;
170
171 /* mask out bits we are going to set */
172 cs->hw_mode &= ~(CSMODE_LEN(0xF) | CSMODE_DIV16 | CSMODE_PM(0xF));
173
174 cs->hw_mode |= CSMODE_LEN(bits_per_word);
175
176 if ((mpc8xxx_spi->spibrg / hz) > 64) {
177 cs->hw_mode |= CSMODE_DIV16;
178 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 16 * 4);
179
180 WARN_ONCE(pm > 33, "%s: Requested speed is too low: %d Hz. "
181 "Will use %d Hz instead.\n", dev_name(&spi->dev),
182 hz, mpc8xxx_spi->spibrg / (4 * 16 * (32 + 1)));
183 if (pm > 33)
184 pm = 33;
185 } else {
186 pm = DIV_ROUND_UP(mpc8xxx_spi->spibrg, hz * 4);
187 }
188 if (pm)
189 pm--;
190 if (pm < 2)
191 pm = 2;
192
193 cs->hw_mode |= CSMODE_PM(pm);
194
195 fsl_espi_change_mode(spi);
196 return 0;
197 }
198
199 static int fsl_espi_cpu_bufs(struct mpc8xxx_spi *mspi, struct spi_transfer *t,
200 unsigned int len)
201 {
202 u32 word;
203 struct fsl_espi_reg *reg_base = mspi->reg_base;
204
205 mspi->count = len;
206
207 /* enable rx ints */
208 mpc8xxx_spi_write_reg(&reg_base->mask, SPIM_NE);
209
210 /* transmit word */
211 word = mspi->get_tx(mspi);
212 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
213
214 return 0;
215 }
216
217 static int fsl_espi_bufs(struct spi_device *spi, struct spi_transfer *t)
218 {
219 struct mpc8xxx_spi *mpc8xxx_spi = spi_master_get_devdata(spi->master);
220 struct fsl_espi_reg *reg_base = mpc8xxx_spi->reg_base;
221 unsigned int len = t->len;
222 int ret;
223
224 mpc8xxx_spi->len = t->len;
225 len = roundup(len, 4) / 4;
226
227 mpc8xxx_spi->tx = t->tx_buf;
228 mpc8xxx_spi->rx = t->rx_buf;
229
230 reinit_completion(&mpc8xxx_spi->done);
231
232 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */
233 if ((t->len - 1) > SPCOM_TRANLEN_MAX) {
234 dev_err(mpc8xxx_spi->dev, "Transaction length (%d)"
235 " beyond the SPCOM[TRANLEN] field\n", t->len);
236 return -EINVAL;
237 }
238 mpc8xxx_spi_write_reg(&reg_base->command,
239 (SPCOM_CS(spi->chip_select) | SPCOM_TRANLEN(t->len - 1)));
240
241 ret = fsl_espi_cpu_bufs(mpc8xxx_spi, t, len);
242 if (ret)
243 return ret;
244
245 wait_for_completion(&mpc8xxx_spi->done);
246
247 /* disable rx ints */
248 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
249
250 return mpc8xxx_spi->count;
251 }
252
253 static inline void fsl_espi_addr2cmd(unsigned int addr, u8 *cmd)
254 {
255 if (cmd) {
256 cmd[1] = (u8)(addr >> 16);
257 cmd[2] = (u8)(addr >> 8);
258 cmd[3] = (u8)(addr >> 0);
259 }
260 }
261
262 static inline unsigned int fsl_espi_cmd2addr(u8 *cmd)
263 {
264 if (cmd)
265 return cmd[1] << 16 | cmd[2] << 8 | cmd[3] << 0;
266
267 return 0;
268 }
269
270 static void fsl_espi_do_trans(struct spi_message *m,
271 struct fsl_espi_transfer *tr)
272 {
273 struct spi_device *spi = m->spi;
274 struct mpc8xxx_spi *mspi = spi_master_get_devdata(spi->master);
275 struct fsl_espi_transfer *espi_trans = tr;
276 struct spi_message message;
277 struct spi_transfer *t, *first, trans;
278 int status = 0;
279
280 spi_message_init(&message);
281 memset(&trans, 0, sizeof(trans));
282
283 first = list_first_entry(&m->transfers, struct spi_transfer,
284 transfer_list);
285 list_for_each_entry(t, &m->transfers, transfer_list) {
286 if ((first->bits_per_word != t->bits_per_word) ||
287 (first->speed_hz != t->speed_hz)) {
288 espi_trans->status = -EINVAL;
289 dev_err(mspi->dev,
290 "bits_per_word/speed_hz should be same for the same SPI transfer\n");
291 return;
292 }
293
294 trans.speed_hz = t->speed_hz;
295 trans.bits_per_word = t->bits_per_word;
296 trans.delay_usecs = max(first->delay_usecs, t->delay_usecs);
297 }
298
299 trans.len = espi_trans->len;
300 trans.tx_buf = espi_trans->tx_buf;
301 trans.rx_buf = espi_trans->rx_buf;
302 spi_message_add_tail(&trans, &message);
303
304 list_for_each_entry(t, &message.transfers, transfer_list) {
305 if (t->bits_per_word || t->speed_hz) {
306 status = -EINVAL;
307
308 status = fsl_espi_setup_transfer(spi, t);
309 if (status < 0)
310 break;
311 }
312
313 if (t->len)
314 status = fsl_espi_bufs(spi, t);
315
316 if (status) {
317 status = -EMSGSIZE;
318 break;
319 }
320
321 if (t->delay_usecs)
322 udelay(t->delay_usecs);
323 }
324
325 espi_trans->status = status;
326 fsl_espi_setup_transfer(spi, NULL);
327 }
328
329 static void fsl_espi_cmd_trans(struct spi_message *m,
330 struct fsl_espi_transfer *trans, u8 *rx_buff)
331 {
332 struct spi_transfer *t;
333 u8 *local_buf;
334 int i = 0;
335 struct fsl_espi_transfer *espi_trans = trans;
336
337 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
338 if (!local_buf) {
339 espi_trans->status = -ENOMEM;
340 return;
341 }
342
343 list_for_each_entry(t, &m->transfers, transfer_list) {
344 if (t->tx_buf) {
345 memcpy(local_buf + i, t->tx_buf, t->len);
346 i += t->len;
347 }
348 }
349
350 espi_trans->tx_buf = local_buf;
351 espi_trans->rx_buf = local_buf + espi_trans->n_tx;
352 fsl_espi_do_trans(m, espi_trans);
353
354 espi_trans->actual_length = espi_trans->len;
355 kfree(local_buf);
356 }
357
358 static void fsl_espi_rw_trans(struct spi_message *m,
359 struct fsl_espi_transfer *trans, u8 *rx_buff)
360 {
361 struct fsl_espi_transfer *espi_trans = trans;
362 unsigned int n_tx = espi_trans->n_tx;
363 unsigned int n_rx = espi_trans->n_rx;
364 struct spi_transfer *t;
365 u8 *local_buf;
366 u8 *rx_buf = rx_buff;
367 unsigned int trans_len;
368 unsigned int addr;
369 int i, pos, loop;
370
371 local_buf = kzalloc(SPCOM_TRANLEN_MAX, GFP_KERNEL);
372 if (!local_buf) {
373 espi_trans->status = -ENOMEM;
374 return;
375 }
376
377 for (pos = 0, loop = 0; pos < n_rx; pos += trans_len, loop++) {
378 trans_len = n_rx - pos;
379 if (trans_len > SPCOM_TRANLEN_MAX - n_tx)
380 trans_len = SPCOM_TRANLEN_MAX - n_tx;
381
382 i = 0;
383 list_for_each_entry(t, &m->transfers, transfer_list) {
384 if (t->tx_buf) {
385 memcpy(local_buf + i, t->tx_buf, t->len);
386 i += t->len;
387 }
388 }
389
390 if (pos > 0) {
391 addr = fsl_espi_cmd2addr(local_buf);
392 addr += pos;
393 fsl_espi_addr2cmd(addr, local_buf);
394 }
395
396 espi_trans->n_tx = n_tx;
397 espi_trans->n_rx = trans_len;
398 espi_trans->len = trans_len + n_tx;
399 espi_trans->tx_buf = local_buf;
400 espi_trans->rx_buf = local_buf + n_tx;
401 fsl_espi_do_trans(m, espi_trans);
402
403 memcpy(rx_buf + pos, espi_trans->rx_buf + n_tx, trans_len);
404
405 if (loop > 0)
406 espi_trans->actual_length += espi_trans->len - n_tx;
407 else
408 espi_trans->actual_length += espi_trans->len;
409 }
410
411 kfree(local_buf);
412 }
413
414 static void fsl_espi_do_one_msg(struct spi_message *m)
415 {
416 struct spi_transfer *t;
417 u8 *rx_buf = NULL;
418 unsigned int n_tx = 0;
419 unsigned int n_rx = 0;
420 struct fsl_espi_transfer espi_trans;
421
422 list_for_each_entry(t, &m->transfers, transfer_list) {
423 if (t->tx_buf)
424 n_tx += t->len;
425 if (t->rx_buf) {
426 n_rx += t->len;
427 rx_buf = t->rx_buf;
428 }
429 }
430
431 espi_trans.n_tx = n_tx;
432 espi_trans.n_rx = n_rx;
433 espi_trans.len = n_tx + n_rx;
434 espi_trans.actual_length = 0;
435 espi_trans.status = 0;
436
437 if (!rx_buf)
438 fsl_espi_cmd_trans(m, &espi_trans, NULL);
439 else
440 fsl_espi_rw_trans(m, &espi_trans, rx_buf);
441
442 m->actual_length = espi_trans.actual_length;
443 m->status = espi_trans.status;
444 m->complete(m->context);
445 }
446
447 static int fsl_espi_setup(struct spi_device *spi)
448 {
449 struct mpc8xxx_spi *mpc8xxx_spi;
450 struct fsl_espi_reg *reg_base;
451 int retval;
452 u32 hw_mode;
453 u32 loop_mode;
454 struct spi_mpc8xxx_cs *cs = spi->controller_state;
455
456 if (!spi->max_speed_hz)
457 return -EINVAL;
458
459 if (!cs) {
460 cs = kzalloc(sizeof *cs, GFP_KERNEL);
461 if (!cs)
462 return -ENOMEM;
463 spi->controller_state = cs;
464 }
465
466 mpc8xxx_spi = spi_master_get_devdata(spi->master);
467 reg_base = mpc8xxx_spi->reg_base;
468
469 hw_mode = cs->hw_mode; /* Save original settings */
470 cs->hw_mode = mpc8xxx_spi_read_reg(
471 &reg_base->csmode[spi->chip_select]);
472 /* mask out bits we are going to set */
473 cs->hw_mode &= ~(CSMODE_CP_BEGIN_EDGECLK | CSMODE_CI_INACTIVEHIGH
474 | CSMODE_REV);
475
476 if (spi->mode & SPI_CPHA)
477 cs->hw_mode |= CSMODE_CP_BEGIN_EDGECLK;
478 if (spi->mode & SPI_CPOL)
479 cs->hw_mode |= CSMODE_CI_INACTIVEHIGH;
480 if (!(spi->mode & SPI_LSB_FIRST))
481 cs->hw_mode |= CSMODE_REV;
482
483 /* Handle the loop mode */
484 loop_mode = mpc8xxx_spi_read_reg(&reg_base->mode);
485 loop_mode &= ~SPMODE_LOOP;
486 if (spi->mode & SPI_LOOP)
487 loop_mode |= SPMODE_LOOP;
488 mpc8xxx_spi_write_reg(&reg_base->mode, loop_mode);
489
490 retval = fsl_espi_setup_transfer(spi, NULL);
491 if (retval < 0) {
492 cs->hw_mode = hw_mode; /* Restore settings */
493 return retval;
494 }
495 return 0;
496 }
497
498 void fsl_espi_cpu_irq(struct mpc8xxx_spi *mspi, u32 events)
499 {
500 struct fsl_espi_reg *reg_base = mspi->reg_base;
501
502 /* We need handle RX first */
503 if (events & SPIE_NE) {
504 u32 rx_data, tmp;
505 u8 rx_data_8;
506
507 /* Spin until RX is done */
508 while (SPIE_RXCNT(events) < min(4, mspi->len)) {
509 cpu_relax();
510 events = mpc8xxx_spi_read_reg(&reg_base->event);
511 }
512
513 if (mspi->len >= 4) {
514 rx_data = mpc8xxx_spi_read_reg(&reg_base->receive);
515 } else {
516 tmp = mspi->len;
517 rx_data = 0;
518 while (tmp--) {
519 rx_data_8 = in_8((u8 *)&reg_base->receive);
520 rx_data |= (rx_data_8 << (tmp * 8));
521 }
522
523 rx_data <<= (4 - mspi->len) * 8;
524 }
525
526 mspi->len -= 4;
527
528 if (mspi->rx)
529 mspi->get_rx(rx_data, mspi);
530 }
531
532 if (!(events & SPIE_NF)) {
533 int ret;
534
535 /* spin until TX is done */
536 ret = spin_event_timeout(((events = mpc8xxx_spi_read_reg(
537 &reg_base->event)) & SPIE_NF) == 0, 1000, 0);
538 if (!ret) {
539 dev_err(mspi->dev, "tired waiting for SPIE_NF\n");
540 return;
541 }
542 }
543
544 /* Clear the events */
545 mpc8xxx_spi_write_reg(&reg_base->event, events);
546
547 mspi->count -= 1;
548 if (mspi->count) {
549 u32 word = mspi->get_tx(mspi);
550
551 mpc8xxx_spi_write_reg(&reg_base->transmit, word);
552 } else {
553 complete(&mspi->done);
554 }
555 }
556
557 static irqreturn_t fsl_espi_irq(s32 irq, void *context_data)
558 {
559 struct mpc8xxx_spi *mspi = context_data;
560 struct fsl_espi_reg *reg_base = mspi->reg_base;
561 irqreturn_t ret = IRQ_NONE;
562 u32 events;
563
564 /* Get interrupt events(tx/rx) */
565 events = mpc8xxx_spi_read_reg(&reg_base->event);
566 if (events)
567 ret = IRQ_HANDLED;
568
569 dev_vdbg(mspi->dev, "%s: events %x\n", __func__, events);
570
571 fsl_espi_cpu_irq(mspi, events);
572
573 return ret;
574 }
575
576 static void fsl_espi_remove(struct mpc8xxx_spi *mspi)
577 {
578 iounmap(mspi->reg_base);
579 }
580
581 static struct spi_master * fsl_espi_probe(struct device *dev,
582 struct resource *mem, unsigned int irq)
583 {
584 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
585 struct spi_master *master;
586 struct mpc8xxx_spi *mpc8xxx_spi;
587 struct fsl_espi_reg *reg_base;
588 u32 regval;
589 int i, ret = 0;
590
591 master = spi_alloc_master(dev, sizeof(struct mpc8xxx_spi));
592 if (!master) {
593 ret = -ENOMEM;
594 goto err;
595 }
596
597 dev_set_drvdata(dev, master);
598
599 ret = mpc8xxx_spi_probe(dev, mem, irq);
600 if (ret)
601 goto err_probe;
602
603 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
604 master->setup = fsl_espi_setup;
605
606 mpc8xxx_spi = spi_master_get_devdata(master);
607 mpc8xxx_spi->spi_do_one_msg = fsl_espi_do_one_msg;
608 mpc8xxx_spi->spi_remove = fsl_espi_remove;
609
610 mpc8xxx_spi->reg_base = ioremap(mem->start, resource_size(mem));
611 if (!mpc8xxx_spi->reg_base) {
612 ret = -ENOMEM;
613 goto err_probe;
614 }
615
616 reg_base = mpc8xxx_spi->reg_base;
617
618 /* Register for SPI Interrupt */
619 ret = request_irq(mpc8xxx_spi->irq, fsl_espi_irq,
620 0, "fsl_espi", mpc8xxx_spi);
621 if (ret)
622 goto free_irq;
623
624 if (mpc8xxx_spi->flags & SPI_QE_CPU_MODE) {
625 mpc8xxx_spi->rx_shift = 16;
626 mpc8xxx_spi->tx_shift = 24;
627 }
628
629 /* SPI controller initializations */
630 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
631 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
632 mpc8xxx_spi_write_reg(&reg_base->command, 0);
633 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
634
635 /* Init eSPI CS mode register */
636 for (i = 0; i < pdata->max_chipselect; i++)
637 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
638
639 /* Enable SPI interface */
640 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
641
642 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
643
644 ret = spi_register_master(master);
645 if (ret < 0)
646 goto unreg_master;
647
648 dev_info(dev, "at 0x%p (irq = %d)\n", reg_base, mpc8xxx_spi->irq);
649
650 return master;
651
652 unreg_master:
653 free_irq(mpc8xxx_spi->irq, mpc8xxx_spi);
654 free_irq:
655 iounmap(mpc8xxx_spi->reg_base);
656 err_probe:
657 spi_master_put(master);
658 err:
659 return ERR_PTR(ret);
660 }
661
662 static int of_fsl_espi_get_chipselects(struct device *dev)
663 {
664 struct device_node *np = dev->of_node;
665 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
666 const u32 *prop;
667 int len;
668
669 prop = of_get_property(np, "fsl,espi-num-chipselects", &len);
670 if (!prop || len < sizeof(*prop)) {
671 dev_err(dev, "No 'fsl,espi-num-chipselects' property\n");
672 return -EINVAL;
673 }
674
675 pdata->max_chipselect = *prop;
676 pdata->cs_control = NULL;
677
678 return 0;
679 }
680
681 static int of_fsl_espi_probe(struct platform_device *ofdev)
682 {
683 struct device *dev = &ofdev->dev;
684 struct device_node *np = ofdev->dev.of_node;
685 struct spi_master *master;
686 struct resource mem;
687 unsigned int irq;
688 int ret = -ENOMEM;
689
690 ret = of_mpc8xxx_spi_probe(ofdev);
691 if (ret)
692 return ret;
693
694 ret = of_fsl_espi_get_chipselects(dev);
695 if (ret)
696 goto err;
697
698 ret = of_address_to_resource(np, 0, &mem);
699 if (ret)
700 goto err;
701
702 irq = irq_of_parse_and_map(np, 0);
703 if (!irq) {
704 ret = -EINVAL;
705 goto err;
706 }
707
708 master = fsl_espi_probe(dev, &mem, irq);
709 if (IS_ERR(master)) {
710 ret = PTR_ERR(master);
711 goto err;
712 }
713
714 return 0;
715
716 err:
717 return ret;
718 }
719
720 static int of_fsl_espi_remove(struct platform_device *dev)
721 {
722 return mpc8xxx_spi_remove(&dev->dev);
723 }
724
725 #ifdef CONFIG_PM_SLEEP
726 static int of_fsl_espi_suspend(struct device *dev)
727 {
728 struct spi_master *master = dev_get_drvdata(dev);
729 struct mpc8xxx_spi *mpc8xxx_spi;
730 struct fsl_espi_reg *reg_base;
731 u32 regval;
732 int ret;
733
734 mpc8xxx_spi = spi_master_get_devdata(master);
735 reg_base = mpc8xxx_spi->reg_base;
736
737 ret = spi_master_suspend(master);
738 if (ret) {
739 dev_warn(dev, "cannot suspend master\n");
740 return ret;
741 }
742
743 regval = mpc8xxx_spi_read_reg(&reg_base->mode);
744 regval &= ~SPMODE_ENABLE;
745 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
746
747 return 0;
748 }
749
750 static int of_fsl_espi_resume(struct device *dev)
751 {
752 struct fsl_spi_platform_data *pdata = dev_get_platdata(dev);
753 struct spi_master *master = dev_get_drvdata(dev);
754 struct mpc8xxx_spi *mpc8xxx_spi;
755 struct fsl_espi_reg *reg_base;
756 u32 regval;
757 int i;
758
759 mpc8xxx_spi = spi_master_get_devdata(master);
760 reg_base = mpc8xxx_spi->reg_base;
761
762 /* SPI controller initializations */
763 mpc8xxx_spi_write_reg(&reg_base->mode, 0);
764 mpc8xxx_spi_write_reg(&reg_base->mask, 0);
765 mpc8xxx_spi_write_reg(&reg_base->command, 0);
766 mpc8xxx_spi_write_reg(&reg_base->event, 0xffffffff);
767
768 /* Init eSPI CS mode register */
769 for (i = 0; i < pdata->max_chipselect; i++)
770 mpc8xxx_spi_write_reg(&reg_base->csmode[i], CSMODE_INIT_VAL);
771
772 /* Enable SPI interface */
773 regval = pdata->initial_spmode | SPMODE_INIT_VAL | SPMODE_ENABLE;
774
775 mpc8xxx_spi_write_reg(&reg_base->mode, regval);
776
777 return spi_master_resume(master);
778 }
779 #endif /* CONFIG_PM_SLEEP */
780
781 static const struct dev_pm_ops espi_pm = {
782 SET_SYSTEM_SLEEP_PM_OPS(of_fsl_espi_suspend, of_fsl_espi_resume)
783 };
784
785 static const struct of_device_id of_fsl_espi_match[] = {
786 { .compatible = "fsl,mpc8536-espi" },
787 {}
788 };
789 MODULE_DEVICE_TABLE(of, of_fsl_espi_match);
790
791 static struct platform_driver fsl_espi_driver = {
792 .driver = {
793 .name = "fsl_espi",
794 .owner = THIS_MODULE,
795 .of_match_table = of_fsl_espi_match,
796 .pm = &espi_pm,
797 },
798 .probe = of_fsl_espi_probe,
799 .remove = of_fsl_espi_remove,
800 };
801 module_platform_driver(fsl_espi_driver);
802
803 MODULE_AUTHOR("Mingkai Hu");
804 MODULE_DESCRIPTION("Enhanced Freescale SPI Driver");
805 MODULE_LICENSE("GPL");
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