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pinctrl: amd: fix compilation warning
[linux-2.6/btrfs-unstable.git] / drivers / pinctrl / pinctrl-amd.c
blobc2203699f1ab32e51fb7058b04dcafb177cb9cb6
1 /*
2 * GPIO driver for AMD
3 *
4 * Copyright (c) 2014,2015 AMD Corporation.
5 * Authors: Ken Xue <Ken.Xue@amd.com>
6 * Wu, Jeff <Jeff.Wu@amd.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13 #include <linux/err.h>
14 #include <linux/bug.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/spinlock.h>
18 #include <linux/compiler.h>
19 #include <linux/types.h>
20 #include <linux/errno.h>
21 #include <linux/log2.h>
22 #include <linux/io.h>
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/platform_device.h>
26 #include <linux/mutex.h>
27 #include <linux/acpi.h>
28 #include <linux/seq_file.h>
29 #include <linux/interrupt.h>
30 #include <linux/list.h>
31 #include <linux/bitops.h>
32 #include <linux/pinctrl/pinconf.h>
33 #include <linux/pinctrl/pinconf-generic.h>
34
35 #include "pinctrl-utils.h"
36 #include "pinctrl-amd.h"
37
38 static int amd_gpio_direction_input(struct gpio_chip *gc, unsigned offset)
39 {
40 unsigned long flags;
41 u32 pin_reg;
42 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
43
44 spin_lock_irqsave(&gpio_dev->lock, flags);
45 pin_reg = readl(gpio_dev->base + offset * 4);
46 pin_reg &= ~BIT(OUTPUT_ENABLE_OFF);
47 writel(pin_reg, gpio_dev->base + offset * 4);
48 spin_unlock_irqrestore(&gpio_dev->lock, flags);
49
50 return 0;
51 }
52
53 static int amd_gpio_direction_output(struct gpio_chip *gc, unsigned offset,
54 int value)
55 {
56 u32 pin_reg;
57 unsigned long flags;
58 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
59
60 spin_lock_irqsave(&gpio_dev->lock, flags);
61 pin_reg = readl(gpio_dev->base + offset * 4);
62 pin_reg |= BIT(OUTPUT_ENABLE_OFF);
63 if (value)
64 pin_reg |= BIT(OUTPUT_VALUE_OFF);
65 else
66 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
67 writel(pin_reg, gpio_dev->base + offset * 4);
68 spin_unlock_irqrestore(&gpio_dev->lock, flags);
69
70 return 0;
71 }
72
73 static int amd_gpio_get_value(struct gpio_chip *gc, unsigned offset)
74 {
75 u32 pin_reg;
76 unsigned long flags;
77 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
78
79 spin_lock_irqsave(&gpio_dev->lock, flags);
80 pin_reg = readl(gpio_dev->base + offset * 4);
81 spin_unlock_irqrestore(&gpio_dev->lock, flags);
82
83 return !!(pin_reg & BIT(PIN_STS_OFF));
84 }
85
86 static void amd_gpio_set_value(struct gpio_chip *gc, unsigned offset, int value)
87 {
88 u32 pin_reg;
89 unsigned long flags;
90 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
91
92 spin_lock_irqsave(&gpio_dev->lock, flags);
93 pin_reg = readl(gpio_dev->base + offset * 4);
94 if (value)
95 pin_reg |= BIT(OUTPUT_VALUE_OFF);
96 else
97 pin_reg &= ~BIT(OUTPUT_VALUE_OFF);
98 writel(pin_reg, gpio_dev->base + offset * 4);
99 spin_unlock_irqrestore(&gpio_dev->lock, flags);
100 }
101
102 static int amd_gpio_set_debounce(struct gpio_chip *gc, unsigned offset,
103 unsigned debounce)
104 {
105 u32 time;
106 u32 pin_reg;
107 int ret = 0;
108 unsigned long flags;
109 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
110
111 spin_lock_irqsave(&gpio_dev->lock, flags);
112 pin_reg = readl(gpio_dev->base + offset * 4);
113
114 if (debounce) {
115 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
116 pin_reg &= ~DB_TMR_OUT_MASK;
117 /*
118 Debounce Debounce Timer Max
119 TmrLarge TmrOutUnit Unit Debounce
120 Time
121 0 0 61 usec (2 RtcClk) 976 usec
122 0 1 244 usec (8 RtcClk) 3.9 msec
123 1 0 15.6 msec (512 RtcClk) 250 msec
124 1 1 62.5 msec (2048 RtcClk) 1 sec
125 */
126
127 if (debounce < 61) {
128 pin_reg |= 1;
129 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
130 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
131 } else if (debounce < 976) {
132 time = debounce / 61;
133 pin_reg |= time & DB_TMR_OUT_MASK;
134 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
135 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
136 } else if (debounce < 3900) {
137 time = debounce / 244;
138 pin_reg |= time & DB_TMR_OUT_MASK;
139 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
140 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
141 } else if (debounce < 250000) {
142 time = debounce / 15600;
143 pin_reg |= time & DB_TMR_OUT_MASK;
144 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
145 pin_reg |= BIT(DB_TMR_LARGE_OFF);
146 } else if (debounce < 1000000) {
147 time = debounce / 62500;
148 pin_reg |= time & DB_TMR_OUT_MASK;
149 pin_reg |= BIT(DB_TMR_OUT_UNIT_OFF);
150 pin_reg |= BIT(DB_TMR_LARGE_OFF);
151 } else {
152 pin_reg &= ~DB_CNTRl_MASK;
153 ret = -EINVAL;
154 }
155 } else {
156 pin_reg &= ~BIT(DB_TMR_OUT_UNIT_OFF);
157 pin_reg &= ~BIT(DB_TMR_LARGE_OFF);
158 pin_reg &= ~DB_TMR_OUT_MASK;
159 pin_reg &= ~DB_CNTRl_MASK;
160 }
161 writel(pin_reg, gpio_dev->base + offset * 4);
162 spin_unlock_irqrestore(&gpio_dev->lock, flags);
163
164 return ret;
165 }
166
167 #ifdef CONFIG_DEBUG_FS
168 static void amd_gpio_dbg_show(struct seq_file *s, struct gpio_chip *gc)
169 {
170 u32 pin_reg;
171 unsigned long flags;
172 unsigned int bank, i, pin_num;
173 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
174
175 char *level_trig;
176 char *active_level;
177 char *interrupt_enable;
178 char *interrupt_mask;
179 char *wake_cntrl0;
180 char *wake_cntrl1;
181 char *wake_cntrl2;
182 char *pin_sts;
183 char *pull_up_sel;
184 char *pull_up_enable;
185 char *pull_down_enable;
186 char *output_value;
187 char *output_enable;
188
189 for (bank = 0; bank < gpio_dev->hwbank_num; bank++) {
190 seq_printf(s, "GPIO bank%d\t", bank);
191
192 switch (bank) {
193 case 0:
194 i = 0;
195 pin_num = AMD_GPIO_PINS_BANK0;
196 break;
197 case 1:
198 i = 64;
199 pin_num = AMD_GPIO_PINS_BANK1 + i;
200 break;
201 case 2:
202 i = 128;
203 pin_num = AMD_GPIO_PINS_BANK2 + i;
204 break;
205 case 3:
206 i = 192;
207 pin_num = AMD_GPIO_PINS_BANK3 + i;
208 break;
209 default:
210 /* Illegal bank number, ignore */
211 continue;
212 }
213 for (; i < pin_num; i++) {
214 seq_printf(s, "pin%d\t", i);
215 spin_lock_irqsave(&gpio_dev->lock, flags);
216 pin_reg = readl(gpio_dev->base + i * 4);
217 spin_unlock_irqrestore(&gpio_dev->lock, flags);
218
219 if (pin_reg & BIT(INTERRUPT_ENABLE_OFF)) {
220 interrupt_enable = "interrupt is enabled|";
221
222 if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
223 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
224 active_level = "Active low|";
225 else if (pin_reg & BIT(ACTIVE_LEVEL_OFF)
226 && !(pin_reg & BIT(ACTIVE_LEVEL_OFF+1)))
227 active_level = "Active high|";
228 else if (!(pin_reg & BIT(ACTIVE_LEVEL_OFF))
229 && pin_reg & BIT(ACTIVE_LEVEL_OFF+1))
230 active_level = "Active on both|";
231 else
232 active_level = "Unknow Active level|";
233
234 if (pin_reg & BIT(LEVEL_TRIG_OFF))
235 level_trig = "Level trigger|";
236 else
237 level_trig = "Edge trigger|";
238
239 } else {
240 interrupt_enable =
241 "interrupt is disabled|";
242 active_level = " ";
243 level_trig = " ";
244 }
245
246 if (pin_reg & BIT(INTERRUPT_MASK_OFF))
247 interrupt_mask =
248 "interrupt is unmasked|";
249 else
250 interrupt_mask =
251 "interrupt is masked|";
252
253 if (pin_reg & BIT(WAKE_CNTRL_OFF_S0I3))
254 wake_cntrl0 = "enable wakeup in S0i3 state|";
255 else
256 wake_cntrl0 = "disable wakeup in S0i3 state|";
257
258 if (pin_reg & BIT(WAKE_CNTRL_OFF_S3))
259 wake_cntrl1 = "enable wakeup in S3 state|";
260 else
261 wake_cntrl1 = "disable wakeup in S3 state|";
262
263 if (pin_reg & BIT(WAKE_CNTRL_OFF_S4))
264 wake_cntrl2 = "enable wakeup in S4/S5 state|";
265 else
266 wake_cntrl2 = "disable wakeup in S4/S5 state|";
267
268 if (pin_reg & BIT(PULL_UP_ENABLE_OFF)) {
269 pull_up_enable = "pull-up is enabled|";
270 if (pin_reg & BIT(PULL_UP_SEL_OFF))
271 pull_up_sel = "8k pull-up|";
272 else
273 pull_up_sel = "4k pull-up|";
274 } else {
275 pull_up_enable = "pull-up is disabled|";
276 pull_up_sel = " ";
277 }
278
279 if (pin_reg & BIT(PULL_DOWN_ENABLE_OFF))
280 pull_down_enable = "pull-down is enabled|";
281 else
282 pull_down_enable = "Pull-down is disabled|";
283
284 if (pin_reg & BIT(OUTPUT_ENABLE_OFF)) {
285 pin_sts = " ";
286 output_enable = "output is enabled|";
287 if (pin_reg & BIT(OUTPUT_VALUE_OFF))
288 output_value = "output is high|";
289 else
290 output_value = "output is low|";
291 } else {
292 output_enable = "output is disabled|";
293 output_value = " ";
294
295 if (pin_reg & BIT(PIN_STS_OFF))
296 pin_sts = "input is high|";
297 else
298 pin_sts = "input is low|";
299 }
300
301 seq_printf(s, "%s %s %s %s %s %s\n"
302 " %s %s %s %s %s %s %s 0x%x\n",
303 level_trig, active_level, interrupt_enable,
304 interrupt_mask, wake_cntrl0, wake_cntrl1,
305 wake_cntrl2, pin_sts, pull_up_sel,
306 pull_up_enable, pull_down_enable,
307 output_value, output_enable, pin_reg);
308 }
309 }
310 }
311 #else
312 #define amd_gpio_dbg_show NULL
313 #endif
314
315 static void amd_gpio_irq_enable(struct irq_data *d)
316 {
317 u32 pin_reg;
318 unsigned long flags;
319 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
320 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
321
322 spin_lock_irqsave(&gpio_dev->lock, flags);
323 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
324 pin_reg |= BIT(INTERRUPT_ENABLE_OFF);
325 pin_reg |= BIT(INTERRUPT_MASK_OFF);
326 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
327 spin_unlock_irqrestore(&gpio_dev->lock, flags);
328 }
329
330 static void amd_gpio_irq_disable(struct irq_data *d)
331 {
332 u32 pin_reg;
333 unsigned long flags;
334 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
335 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
336
337 spin_lock_irqsave(&gpio_dev->lock, flags);
338 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
339 pin_reg &= ~BIT(INTERRUPT_ENABLE_OFF);
340 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
341 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
342 spin_unlock_irqrestore(&gpio_dev->lock, flags);
343 }
344
345 static void amd_gpio_irq_mask(struct irq_data *d)
346 {
347 u32 pin_reg;
348 unsigned long flags;
349 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
350 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
351
352 spin_lock_irqsave(&gpio_dev->lock, flags);
353 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
354 pin_reg &= ~BIT(INTERRUPT_MASK_OFF);
355 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
356 spin_unlock_irqrestore(&gpio_dev->lock, flags);
357 }
358
359 static void amd_gpio_irq_unmask(struct irq_data *d)
360 {
361 u32 pin_reg;
362 unsigned long flags;
363 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
364 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
365
366 spin_lock_irqsave(&gpio_dev->lock, flags);
367 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
368 pin_reg |= BIT(INTERRUPT_MASK_OFF);
369 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
370 spin_unlock_irqrestore(&gpio_dev->lock, flags);
371 }
372
373 static void amd_gpio_irq_eoi(struct irq_data *d)
374 {
375 u32 reg;
376 unsigned long flags;
377 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
378 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
379
380 spin_lock_irqsave(&gpio_dev->lock, flags);
381 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
382 reg |= EOI_MASK;
383 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
384 spin_unlock_irqrestore(&gpio_dev->lock, flags);
385 }
386
387 static int amd_gpio_irq_set_type(struct irq_data *d, unsigned int type)
388 {
389 int ret = 0;
390 u32 pin_reg;
391 unsigned long flags;
392 bool level_trig;
393 u32 active_level;
394 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
395 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
396
397 spin_lock_irqsave(&gpio_dev->lock, flags);
398 pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
399
400 /*
401 * When level_trig is set EDGE and active_level is set HIGH in BIOS
402 * default settings, ignore incoming settings from client and use
403 * BIOS settings to configure GPIO register.
404 */
405 level_trig = !(pin_reg & (LEVEL_TRIGGER << LEVEL_TRIG_OFF));
406 active_level = pin_reg & (ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
407
408 if(level_trig &&
409 ((active_level >> ACTIVE_LEVEL_OFF) == ACTIVE_HIGH))
410 type = IRQ_TYPE_EDGE_FALLING;
411
412 switch (type & IRQ_TYPE_SENSE_MASK) {
413 case IRQ_TYPE_EDGE_RISING:
414 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
415 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
416 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
417 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
418 irq_set_handler_locked(d, handle_edge_irq);
419 break;
420
421 case IRQ_TYPE_EDGE_FALLING:
422 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
423 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
424 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
425 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
426 irq_set_handler_locked(d, handle_edge_irq);
427 break;
428
429 case IRQ_TYPE_EDGE_BOTH:
430 pin_reg &= ~BIT(LEVEL_TRIG_OFF);
431 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
432 pin_reg |= BOTH_EADGE << ACTIVE_LEVEL_OFF;
433 pin_reg |= DB_TYPE_REMOVE_GLITCH << DB_CNTRL_OFF;
434 irq_set_handler_locked(d, handle_edge_irq);
435 break;
436
437 case IRQ_TYPE_LEVEL_HIGH:
438 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
439 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
440 pin_reg |= ACTIVE_HIGH << ACTIVE_LEVEL_OFF;
441 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
442 pin_reg |= DB_TYPE_PRESERVE_LOW_GLITCH << DB_CNTRL_OFF;
443 irq_set_handler_locked(d, handle_level_irq);
444 break;
445
446 case IRQ_TYPE_LEVEL_LOW:
447 pin_reg |= LEVEL_TRIGGER << LEVEL_TRIG_OFF;
448 pin_reg &= ~(ACTIVE_LEVEL_MASK << ACTIVE_LEVEL_OFF);
449 pin_reg |= ACTIVE_LOW << ACTIVE_LEVEL_OFF;
450 pin_reg &= ~(DB_CNTRl_MASK << DB_CNTRL_OFF);
451 pin_reg |= DB_TYPE_PRESERVE_HIGH_GLITCH << DB_CNTRL_OFF;
452 irq_set_handler_locked(d, handle_level_irq);
453 break;
454
455 case IRQ_TYPE_NONE:
456 break;
457
458 default:
459 dev_err(&gpio_dev->pdev->dev, "Invalid type value\n");
460 ret = -EINVAL;
461 }
462
463 pin_reg |= CLR_INTR_STAT << INTERRUPT_STS_OFF;
464 writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
465 spin_unlock_irqrestore(&gpio_dev->lock, flags);
466
467 return ret;
468 }
469
470 static void amd_irq_ack(struct irq_data *d)
471 {
472 /*
473 * based on HW design,there is no need to ack HW
474 * before handle current irq. But this routine is
475 * necessary for handle_edge_irq
476 */
477 }
478
479 static struct irq_chip amd_gpio_irqchip = {
480 .name = "amd_gpio",
481 .irq_ack = amd_irq_ack,
482 .irq_enable = amd_gpio_irq_enable,
483 .irq_disable = amd_gpio_irq_disable,
484 .irq_mask = amd_gpio_irq_mask,
485 .irq_unmask = amd_gpio_irq_unmask,
486 .irq_eoi = amd_gpio_irq_eoi,
487 .irq_set_type = amd_gpio_irq_set_type,
488 .flags = IRQCHIP_SKIP_SET_WAKE,
489 };
490
491 static void amd_gpio_irq_handler(struct irq_desc *desc)
492 {
493 u32 i;
494 u32 off;
495 u32 reg;
496 u32 pin_reg;
497 u64 reg64;
498 int handled = 0;
499 unsigned int irq;
500 unsigned long flags;
501 struct irq_chip *chip = irq_desc_get_chip(desc);
502 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
503 struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
504
505 chained_irq_enter(chip, desc);
506 /*enable GPIO interrupt again*/
507 spin_lock_irqsave(&gpio_dev->lock, flags);
508 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG1);
509 reg64 = reg;
510 reg64 = reg64 << 32;
511
512 reg = readl(gpio_dev->base + WAKE_INT_STATUS_REG0);
513 reg64 |= reg;
514 spin_unlock_irqrestore(&gpio_dev->lock, flags);
515
516 /*
517 * first 46 bits indicates interrupt status.
518 * one bit represents four interrupt sources.
519 */
520 for (off = 0; off < 46 ; off++) {
521 if (reg64 & BIT(off)) {
522 for (i = 0; i < 4; i++) {
523 pin_reg = readl(gpio_dev->base +
524 (off * 4 + i) * 4);
525 if ((pin_reg & BIT(INTERRUPT_STS_OFF)) ||
526 (pin_reg & BIT(WAKE_STS_OFF))) {
527 irq = irq_find_mapping(gc->irqdomain,
528 off * 4 + i);
529 generic_handle_irq(irq);
530 writel(pin_reg,
531 gpio_dev->base
532 + (off * 4 + i) * 4);
533 handled++;
534 }
535 }
536 }
537 }
538
539 if (handled == 0)
540 handle_bad_irq(desc);
541
542 spin_lock_irqsave(&gpio_dev->lock, flags);
543 reg = readl(gpio_dev->base + WAKE_INT_MASTER_REG);
544 reg |= EOI_MASK;
545 writel(reg, gpio_dev->base + WAKE_INT_MASTER_REG);
546 spin_unlock_irqrestore(&gpio_dev->lock, flags);
547
548 chained_irq_exit(chip, desc);
549 }
550
551 static int amd_get_groups_count(struct pinctrl_dev *pctldev)
552 {
553 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
554
555 return gpio_dev->ngroups;
556 }
557
558 static const char *amd_get_group_name(struct pinctrl_dev *pctldev,
559 unsigned group)
560 {
561 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
562
563 return gpio_dev->groups[group].name;
564 }
565
566 static int amd_get_group_pins(struct pinctrl_dev *pctldev,
567 unsigned group,
568 const unsigned **pins,
569 unsigned *num_pins)
570 {
571 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
572
573 *pins = gpio_dev->groups[group].pins;
574 *num_pins = gpio_dev->groups[group].npins;
575 return 0;
576 }
577
578 static const struct pinctrl_ops amd_pinctrl_ops = {
579 .get_groups_count = amd_get_groups_count,
580 .get_group_name = amd_get_group_name,
581 .get_group_pins = amd_get_group_pins,
582 #ifdef CONFIG_OF
583 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
584 .dt_free_map = pinctrl_utils_free_map,
585 #endif
586 };
587
588 static int amd_pinconf_get(struct pinctrl_dev *pctldev,
589 unsigned int pin,
590 unsigned long *config)
591 {
592 u32 pin_reg;
593 unsigned arg;
594 unsigned long flags;
595 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
596 enum pin_config_param param = pinconf_to_config_param(*config);
597
598 spin_lock_irqsave(&gpio_dev->lock, flags);
599 pin_reg = readl(gpio_dev->base + pin*4);
600 spin_unlock_irqrestore(&gpio_dev->lock, flags);
601 switch (param) {
602 case PIN_CONFIG_INPUT_DEBOUNCE:
603 arg = pin_reg & DB_TMR_OUT_MASK;
604 break;
605
606 case PIN_CONFIG_BIAS_PULL_DOWN:
607 arg = (pin_reg >> PULL_DOWN_ENABLE_OFF) & BIT(0);
608 break;
609
610 case PIN_CONFIG_BIAS_PULL_UP:
611 arg = (pin_reg >> PULL_UP_SEL_OFF) & (BIT(0) | BIT(1));
612 break;
613
614 case PIN_CONFIG_DRIVE_STRENGTH:
615 arg = (pin_reg >> DRV_STRENGTH_SEL_OFF) & DRV_STRENGTH_SEL_MASK;
616 break;
617
618 default:
619 dev_err(&gpio_dev->pdev->dev, "Invalid config param %04x\n",
620 param);
621 return -ENOTSUPP;
622 }
623
624 *config = pinconf_to_config_packed(param, arg);
625
626 return 0;
627 }
628
629 static int amd_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
630 unsigned long *configs, unsigned num_configs)
631 {
632 int i;
633 u32 arg;
634 int ret = 0;
635 u32 pin_reg;
636 unsigned long flags;
637 enum pin_config_param param;
638 struct amd_gpio *gpio_dev = pinctrl_dev_get_drvdata(pctldev);
639
640 spin_lock_irqsave(&gpio_dev->lock, flags);
641 for (i = 0; i < num_configs; i++) {
642 param = pinconf_to_config_param(configs[i]);
643 arg = pinconf_to_config_argument(configs[i]);
644 pin_reg = readl(gpio_dev->base + pin*4);
645
646 switch (param) {
647 case PIN_CONFIG_INPUT_DEBOUNCE:
648 pin_reg &= ~DB_TMR_OUT_MASK;
649 pin_reg |= arg & DB_TMR_OUT_MASK;
650 break;
651
652 case PIN_CONFIG_BIAS_PULL_DOWN:
653 pin_reg &= ~BIT(PULL_DOWN_ENABLE_OFF);
654 pin_reg |= (arg & BIT(0)) << PULL_DOWN_ENABLE_OFF;
655 break;
656
657 case PIN_CONFIG_BIAS_PULL_UP:
658 pin_reg &= ~BIT(PULL_UP_SEL_OFF);
659 pin_reg |= (arg & BIT(0)) << PULL_UP_SEL_OFF;
660 pin_reg &= ~BIT(PULL_UP_ENABLE_OFF);
661 pin_reg |= ((arg>>1) & BIT(0)) << PULL_UP_ENABLE_OFF;
662 break;
663
664 case PIN_CONFIG_DRIVE_STRENGTH:
665 pin_reg &= ~(DRV_STRENGTH_SEL_MASK
666 << DRV_STRENGTH_SEL_OFF);
667 pin_reg |= (arg & DRV_STRENGTH_SEL_MASK)
668 << DRV_STRENGTH_SEL_OFF;
669 break;
670
671 default:
672 dev_err(&gpio_dev->pdev->dev,
673 "Invalid config param %04x\n", param);
674 ret = -ENOTSUPP;
675 }
676
677 writel(pin_reg, gpio_dev->base + pin*4);
678 }
679 spin_unlock_irqrestore(&gpio_dev->lock, flags);
680
681 return ret;
682 }
683
684 static int amd_pinconf_group_get(struct pinctrl_dev *pctldev,
685 unsigned int group,
686 unsigned long *config)
687 {
688 const unsigned *pins;
689 unsigned npins;
690 int ret;
691
692 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
693 if (ret)
694 return ret;
695
696 if (amd_pinconf_get(pctldev, pins[0], config))
697 return -ENOTSUPP;
698
699 return 0;
700 }
701
702 static int amd_pinconf_group_set(struct pinctrl_dev *pctldev,
703 unsigned group, unsigned long *configs,
704 unsigned num_configs)
705 {
706 const unsigned *pins;
707 unsigned npins;
708 int i, ret;
709
710 ret = amd_get_group_pins(pctldev, group, &pins, &npins);
711 if (ret)
712 return ret;
713 for (i = 0; i < npins; i++) {
714 if (amd_pinconf_set(pctldev, pins[i], configs, num_configs))
715 return -ENOTSUPP;
716 }
717 return 0;
718 }
719
720 static const struct pinconf_ops amd_pinconf_ops = {
721 .pin_config_get = amd_pinconf_get,
722 .pin_config_set = amd_pinconf_set,
723 .pin_config_group_get = amd_pinconf_group_get,
724 .pin_config_group_set = amd_pinconf_group_set,
725 };
726
727 static struct pinctrl_desc amd_pinctrl_desc = {
728 .pins = kerncz_pins,
729 .npins = ARRAY_SIZE(kerncz_pins),
730 .pctlops = &amd_pinctrl_ops,
731 .confops = &amd_pinconf_ops,
732 .owner = THIS_MODULE,
733 };
734
735 static int amd_gpio_probe(struct platform_device *pdev)
736 {
737 int ret = 0;
738 int irq_base;
739 struct resource *res;
740 struct amd_gpio *gpio_dev;
741
742 gpio_dev = devm_kzalloc(&pdev->dev,
743 sizeof(struct amd_gpio), GFP_KERNEL);
744 if (!gpio_dev)
745 return -ENOMEM;
746
747 spin_lock_init(&gpio_dev->lock);
748
749 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
750 if (!res) {
751 dev_err(&pdev->dev, "Failed to get gpio io resource.\n");
752 return -EINVAL;
753 }
754
755 gpio_dev->base = devm_ioremap_nocache(&pdev->dev, res->start,
756 resource_size(res));
757 if (!gpio_dev->base)
758 return -ENOMEM;
759
760 irq_base = platform_get_irq(pdev, 0);
761 if (irq_base < 0) {
762 dev_err(&pdev->dev, "Failed to get gpio IRQ.\n");
763 return -EINVAL;
764 }
765
766 gpio_dev->pdev = pdev;
767 gpio_dev->gc.direction_input = amd_gpio_direction_input;
768 gpio_dev->gc.direction_output = amd_gpio_direction_output;
769 gpio_dev->gc.get = amd_gpio_get_value;
770 gpio_dev->gc.set = amd_gpio_set_value;
771 gpio_dev->gc.set_debounce = amd_gpio_set_debounce;
772 gpio_dev->gc.dbg_show = amd_gpio_dbg_show;
773
774 gpio_dev->gc.base = -1;
775 gpio_dev->gc.label = pdev->name;
776 gpio_dev->gc.owner = THIS_MODULE;
777 gpio_dev->gc.parent = &pdev->dev;
778 gpio_dev->gc.ngpio = resource_size(res) / 4;
779 #if defined(CONFIG_OF_GPIO)
780 gpio_dev->gc.of_node = pdev->dev.of_node;
781 #endif
782
783 gpio_dev->hwbank_num = gpio_dev->gc.ngpio / 64;
784 gpio_dev->groups = kerncz_groups;
785 gpio_dev->ngroups = ARRAY_SIZE(kerncz_groups);
786
787 amd_pinctrl_desc.name = dev_name(&pdev->dev);
788 gpio_dev->pctrl = devm_pinctrl_register(&pdev->dev, &amd_pinctrl_desc,
789 gpio_dev);
790 if (IS_ERR(gpio_dev->pctrl)) {
791 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
792 return PTR_ERR(gpio_dev->pctrl);
793 }
794
795 ret = gpiochip_add_data(&gpio_dev->gc, gpio_dev);
796 if (ret)
797 return ret;
798
799 ret = gpiochip_add_pin_range(&gpio_dev->gc, dev_name(&pdev->dev),
800 0, 0, gpio_dev->gc.ngpio);
801 if (ret) {
802 dev_err(&pdev->dev, "Failed to add pin range\n");
803 goto out2;
804 }
805
806 ret = gpiochip_irqchip_add(&gpio_dev->gc,
807 &amd_gpio_irqchip,
808 0,
809 handle_simple_irq,
810 IRQ_TYPE_NONE);
811 if (ret) {
812 dev_err(&pdev->dev, "could not add irqchip\n");
813 ret = -ENODEV;
814 goto out2;
815 }
816
817 gpiochip_set_chained_irqchip(&gpio_dev->gc,
818 &amd_gpio_irqchip,
819 irq_base,
820 amd_gpio_irq_handler);
821 platform_set_drvdata(pdev, gpio_dev);
822
823 dev_dbg(&pdev->dev, "amd gpio driver loaded\n");
824 return ret;
825
826 out2:
827 gpiochip_remove(&gpio_dev->gc);
828
829 return ret;
830 }
831
832 static int amd_gpio_remove(struct platform_device *pdev)
833 {
834 struct amd_gpio *gpio_dev;
835
836 gpio_dev = platform_get_drvdata(pdev);
837
838 gpiochip_remove(&gpio_dev->gc);
839 pinctrl_unregister(gpio_dev->pctrl);
840
841 return 0;
842 }
843
844 static const struct acpi_device_id amd_gpio_acpi_match[] = {
845 { "AMD0030", 0 },
846 { "AMDI0030", 0},
847 { },
848 };
849 MODULE_DEVICE_TABLE(acpi, amd_gpio_acpi_match);
850
851 static struct platform_driver amd_gpio_driver = {
852 .driver = {
853 .name = "amd_gpio",
854 .acpi_match_table = ACPI_PTR(amd_gpio_acpi_match),
855 },
856 .probe = amd_gpio_probe,
857 .remove = amd_gpio_remove,
858 };
859
860 module_platform_driver(amd_gpio_driver);
861
862 MODULE_LICENSE("GPL v2");
863 MODULE_AUTHOR("Ken Xue <Ken.Xue@amd.com>, Jeff Wu <Jeff.Wu@amd.com>");
864 MODULE_DESCRIPTION("AMD GPIO pinctrl driver");
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