1 /* Driver for Realtek PCI-Express card reader
3 * Copyright(c) 2009 Realtek Semiconductor Corp. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2, or (at your option) any
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License along
16 * with this program; if not, see <http://www.gnu.org/licenses/>.
19 * Wei WANG <wei_wang@realsil.com.cn>
20 * No. 450, Shenhu Road, Suzhou Industry Park, Suzhou, China
23 #include <linux/pci.h>
24 #include <linux/module.h>
25 #include <linux/slab.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/highmem.h>
28 #include <linux/interrupt.h>
29 #include <linux/delay.h>
30 #include <linux/idr.h>
31 #include <linux/platform_device.h>
32 #include <linux/mfd/core.h>
33 #include <linux/mfd/rtsx_pci.h>
34 #include <asm/unaligned.h>
38 static bool msi_en
= true;
39 module_param(msi_en
, bool, S_IRUGO
| S_IWUSR
);
40 MODULE_PARM_DESC(msi_en
, "Enable MSI");
42 static DEFINE_IDR(rtsx_pci_idr
);
43 static DEFINE_SPINLOCK(rtsx_pci_lock
);
45 static struct mfd_cell rtsx_pcr_cells
[] = {
47 .name
= DRV_NAME_RTSX_PCI_SDMMC
,
50 .name
= DRV_NAME_RTSX_PCI_MS
,
54 static DEFINE_PCI_DEVICE_TABLE(rtsx_pci_ids
) = {
55 { PCI_DEVICE(0x10EC, 0x5209), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
56 { PCI_DEVICE(0x10EC, 0x5229), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
57 { PCI_DEVICE(0x10EC, 0x5289), PCI_CLASS_OTHERS
<< 16, 0xFF0000 },
61 MODULE_DEVICE_TABLE(pci
, rtsx_pci_ids
);
63 void rtsx_pci_start_run(struct rtsx_pcr
*pcr
)
65 /* If pci device removed, don't queue idle work any more */
69 if (pcr
->state
!= PDEV_STAT_RUN
) {
70 pcr
->state
= PDEV_STAT_RUN
;
71 if (pcr
->ops
->enable_auto_blink
)
72 pcr
->ops
->enable_auto_blink(pcr
);
75 mod_delayed_work(system_wq
, &pcr
->idle_work
, msecs_to_jiffies(200));
77 EXPORT_SYMBOL_GPL(rtsx_pci_start_run
);
79 int rtsx_pci_write_register(struct rtsx_pcr
*pcr
, u16 addr
, u8 mask
, u8 data
)
82 u32 val
= HAIMR_WRITE_START
;
84 val
|= (u32
)(addr
& 0x3FFF) << 16;
85 val
|= (u32
)mask
<< 8;
88 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
90 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
91 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
92 if ((val
& HAIMR_TRANS_END
) == 0) {
101 EXPORT_SYMBOL_GPL(rtsx_pci_write_register
);
103 int rtsx_pci_read_register(struct rtsx_pcr
*pcr
, u16 addr
, u8
*data
)
105 u32 val
= HAIMR_READ_START
;
108 val
|= (u32
)(addr
& 0x3FFF) << 16;
109 rtsx_pci_writel(pcr
, RTSX_HAIMR
, val
);
111 for (i
= 0; i
< MAX_RW_REG_CNT
; i
++) {
112 val
= rtsx_pci_readl(pcr
, RTSX_HAIMR
);
113 if ((val
& HAIMR_TRANS_END
) == 0)
117 if (i
>= MAX_RW_REG_CNT
)
121 *data
= (u8
)(val
& 0xFF);
125 EXPORT_SYMBOL_GPL(rtsx_pci_read_register
);
127 int rtsx_pci_write_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16 val
)
129 int err
, i
, finished
= 0;
132 rtsx_pci_init_cmd(pcr
);
134 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA0
, 0xFF, (u8
)val
);
135 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYDATA1
, 0xFF, (u8
)(val
>> 8));
136 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
137 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x81);
139 err
= rtsx_pci_send_cmd(pcr
, 100);
143 for (i
= 0; i
< 100000; i
++) {
144 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
159 EXPORT_SYMBOL_GPL(rtsx_pci_write_phy_register
);
161 int rtsx_pci_read_phy_register(struct rtsx_pcr
*pcr
, u8 addr
, u16
*val
)
163 int err
, i
, finished
= 0;
167 rtsx_pci_init_cmd(pcr
);
169 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYADDR
, 0xFF, addr
);
170 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PHYRWCTL
, 0xFF, 0x80);
172 err
= rtsx_pci_send_cmd(pcr
, 100);
176 for (i
= 0; i
< 100000; i
++) {
177 err
= rtsx_pci_read_register(pcr
, PHYRWCTL
, &tmp
);
190 rtsx_pci_init_cmd(pcr
);
192 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA0
, 0, 0);
193 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, PHYDATA1
, 0, 0);
195 err
= rtsx_pci_send_cmd(pcr
, 100);
199 ptr
= rtsx_pci_get_cmd_data(pcr
);
200 data
= ((u16
)ptr
[1] << 8) | ptr
[0];
207 EXPORT_SYMBOL_GPL(rtsx_pci_read_phy_register
);
209 void rtsx_pci_stop_cmd(struct rtsx_pcr
*pcr
)
211 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, STOP_CMD
);
212 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, STOP_DMA
);
214 rtsx_pci_write_register(pcr
, DMACTL
, 0x80, 0x80);
215 rtsx_pci_write_register(pcr
, RBCTL
, 0x80, 0x80);
217 EXPORT_SYMBOL_GPL(rtsx_pci_stop_cmd
);
219 void rtsx_pci_add_cmd(struct rtsx_pcr
*pcr
,
220 u8 cmd_type
, u16 reg_addr
, u8 mask
, u8 data
)
224 u32
*ptr
= (u32
*)(pcr
->host_cmds_ptr
);
226 val
|= (u32
)(cmd_type
& 0x03) << 30;
227 val
|= (u32
)(reg_addr
& 0x3FFF) << 16;
228 val
|= (u32
)mask
<< 8;
231 spin_lock_irqsave(&pcr
->lock
, flags
);
233 if (pcr
->ci
< (HOST_CMDS_BUF_LEN
/ 4)) {
234 put_unaligned_le32(val
, ptr
);
238 spin_unlock_irqrestore(&pcr
->lock
, flags
);
240 EXPORT_SYMBOL_GPL(rtsx_pci_add_cmd
);
242 void rtsx_pci_send_cmd_no_wait(struct rtsx_pcr
*pcr
)
246 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
248 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
249 /* Hardware Auto Response */
251 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
253 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd_no_wait
);
255 int rtsx_pci_send_cmd(struct rtsx_pcr
*pcr
, int timeout
)
257 struct completion trans_done
;
263 spin_lock_irqsave(&pcr
->lock
, flags
);
265 /* set up data structures for the wakeup system */
266 pcr
->done
= &trans_done
;
267 pcr
->trans_result
= TRANS_NOT_READY
;
268 init_completion(&trans_done
);
270 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
272 val
|= (u32
)(pcr
->ci
* 4) & 0x00FFFFFF;
273 /* Hardware Auto Response */
275 rtsx_pci_writel(pcr
, RTSX_HCBCTLR
, val
);
277 spin_unlock_irqrestore(&pcr
->lock
, flags
);
279 /* Wait for TRANS_OK_INT */
280 timeleft
= wait_for_completion_interruptible_timeout(
281 &trans_done
, msecs_to_jiffies(timeout
));
283 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
286 goto finish_send_cmd
;
289 spin_lock_irqsave(&pcr
->lock
, flags
);
290 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
292 else if (pcr
->trans_result
== TRANS_RESULT_OK
)
294 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
296 spin_unlock_irqrestore(&pcr
->lock
, flags
);
299 spin_lock_irqsave(&pcr
->lock
, flags
);
301 spin_unlock_irqrestore(&pcr
->lock
, flags
);
303 if ((err
< 0) && (err
!= -ENODEV
))
304 rtsx_pci_stop_cmd(pcr
);
307 complete(pcr
->finish_me
);
311 EXPORT_SYMBOL_GPL(rtsx_pci_send_cmd
);
313 static void rtsx_pci_add_sg_tbl(struct rtsx_pcr
*pcr
,
314 dma_addr_t addr
, unsigned int len
, int end
)
316 u64
*ptr
= (u64
*)(pcr
->host_sg_tbl_ptr
) + pcr
->sgi
;
318 u8 option
= SG_VALID
| SG_TRANS_DATA
;
320 dev_dbg(&(pcr
->pci
->dev
), "DMA addr: 0x%x, Len: 0x%x\n",
321 (unsigned int)addr
, len
);
325 val
= ((u64
)addr
<< 32) | ((u64
)len
<< 12) | option
;
327 put_unaligned_le64(val
, ptr
);
332 int rtsx_pci_transfer_data(struct rtsx_pcr
*pcr
, struct scatterlist
*sglist
,
333 int num_sg
, bool read
, int timeout
)
335 struct completion trans_done
;
337 int err
= 0, i
, count
;
340 struct scatterlist
*sg
;
341 enum dma_data_direction dma_dir
;
346 dev_dbg(&(pcr
->pci
->dev
), "--> %s: num_sg = %d\n", __func__
, num_sg
);
348 /* don't transfer data during abort processing */
352 if ((sglist
== NULL
) || (num_sg
<= 0))
356 dir
= DEVICE_TO_HOST
;
357 dma_dir
= DMA_FROM_DEVICE
;
359 dir
= HOST_TO_DEVICE
;
360 dma_dir
= DMA_TO_DEVICE
;
363 count
= dma_map_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dma_dir
);
365 dev_err(&(pcr
->pci
->dev
), "scatterlist map failed\n");
368 dev_dbg(&(pcr
->pci
->dev
), "DMA mapping count: %d\n", count
);
370 val
= ((u32
)(dir
& 0x01) << 29) | TRIG_DMA
| ADMA_MODE
;
372 for_each_sg(sglist
, sg
, count
, i
) {
373 addr
= sg_dma_address(sg
);
374 len
= sg_dma_len(sg
);
375 rtsx_pci_add_sg_tbl(pcr
, addr
, len
, i
== count
- 1);
378 spin_lock_irqsave(&pcr
->lock
, flags
);
380 pcr
->done
= &trans_done
;
381 pcr
->trans_result
= TRANS_NOT_READY
;
382 init_completion(&trans_done
);
383 rtsx_pci_writel(pcr
, RTSX_HDBAR
, pcr
->host_sg_tbl_addr
);
384 rtsx_pci_writel(pcr
, RTSX_HDBCTLR
, val
);
386 spin_unlock_irqrestore(&pcr
->lock
, flags
);
388 timeleft
= wait_for_completion_interruptible_timeout(
389 &trans_done
, msecs_to_jiffies(timeout
));
391 dev_dbg(&(pcr
->pci
->dev
), "Timeout (%s %d)\n",
397 spin_lock_irqsave(&pcr
->lock
, flags
);
399 if (pcr
->trans_result
== TRANS_RESULT_FAIL
)
401 else if (pcr
->trans_result
== TRANS_NO_DEVICE
)
404 spin_unlock_irqrestore(&pcr
->lock
, flags
);
407 spin_lock_irqsave(&pcr
->lock
, flags
);
409 spin_unlock_irqrestore(&pcr
->lock
, flags
);
411 dma_unmap_sg(&(pcr
->pci
->dev
), sglist
, num_sg
, dma_dir
);
413 if ((err
< 0) && (err
!= -ENODEV
))
414 rtsx_pci_stop_cmd(pcr
);
417 complete(pcr
->finish_me
);
421 EXPORT_SYMBOL_GPL(rtsx_pci_transfer_data
);
423 int rtsx_pci_read_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
435 for (i
= 0; i
< buf_len
/ 256; i
++) {
436 rtsx_pci_init_cmd(pcr
);
438 for (j
= 0; j
< 256; j
++)
439 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
441 err
= rtsx_pci_send_cmd(pcr
, 250);
445 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), 256);
450 rtsx_pci_init_cmd(pcr
);
452 for (j
= 0; j
< buf_len
% 256; j
++)
453 rtsx_pci_add_cmd(pcr
, READ_REG_CMD
, reg
++, 0, 0);
455 err
= rtsx_pci_send_cmd(pcr
, 250);
460 memcpy(ptr
, rtsx_pci_get_cmd_data(pcr
), buf_len
% 256);
464 EXPORT_SYMBOL_GPL(rtsx_pci_read_ppbuf
);
466 int rtsx_pci_write_ppbuf(struct rtsx_pcr
*pcr
, u8
*buf
, int buf_len
)
478 for (i
= 0; i
< buf_len
/ 256; i
++) {
479 rtsx_pci_init_cmd(pcr
);
481 for (j
= 0; j
< 256; j
++) {
482 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
487 err
= rtsx_pci_send_cmd(pcr
, 250);
493 rtsx_pci_init_cmd(pcr
);
495 for (j
= 0; j
< buf_len
% 256; j
++) {
496 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
501 err
= rtsx_pci_send_cmd(pcr
, 250);
508 EXPORT_SYMBOL_GPL(rtsx_pci_write_ppbuf
);
510 static int rtsx_pci_set_pull_ctl(struct rtsx_pcr
*pcr
, const u32
*tbl
)
514 rtsx_pci_init_cmd(pcr
);
516 while (*tbl
& 0xFFFF0000) {
517 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
,
518 (u16
)(*tbl
>> 16), 0xFF, (u8
)(*tbl
));
522 err
= rtsx_pci_send_cmd(pcr
, 100);
529 int rtsx_pci_card_pull_ctl_enable(struct rtsx_pcr
*pcr
, int card
)
533 if (card
== RTSX_SD_CARD
)
534 tbl
= pcr
->sd_pull_ctl_enable_tbl
;
535 else if (card
== RTSX_MS_CARD
)
536 tbl
= pcr
->ms_pull_ctl_enable_tbl
;
540 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
542 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_enable
);
544 int rtsx_pci_card_pull_ctl_disable(struct rtsx_pcr
*pcr
, int card
)
548 if (card
== RTSX_SD_CARD
)
549 tbl
= pcr
->sd_pull_ctl_disable_tbl
;
550 else if (card
== RTSX_MS_CARD
)
551 tbl
= pcr
->ms_pull_ctl_disable_tbl
;
556 return rtsx_pci_set_pull_ctl(pcr
, tbl
);
558 EXPORT_SYMBOL_GPL(rtsx_pci_card_pull_ctl_disable
);
560 static void rtsx_pci_enable_bus_int(struct rtsx_pcr
*pcr
)
562 pcr
->bier
= TRANS_OK_INT_EN
| TRANS_FAIL_INT_EN
| SD_INT_EN
;
564 if (pcr
->num_slots
> 1)
565 pcr
->bier
|= MS_INT_EN
;
567 /* Enable Bus Interrupt */
568 rtsx_pci_writel(pcr
, RTSX_BIER
, pcr
->bier
);
570 dev_dbg(&(pcr
->pci
->dev
), "RTSX_BIER: 0x%08x\n", pcr
->bier
);
573 static inline u8
double_ssc_depth(u8 depth
)
575 return ((depth
> 1) ? (depth
- 1) : depth
);
578 static u8
revise_ssc_depth(u8 ssc_depth
, u8 div
)
580 if (div
> CLK_DIV_1
) {
581 if (ssc_depth
> (div
- 1))
582 ssc_depth
-= (div
- 1);
584 ssc_depth
= SSC_DEPTH_4M
;
590 int rtsx_pci_switch_clock(struct rtsx_pcr
*pcr
, unsigned int card_clock
,
591 u8 ssc_depth
, bool initial_mode
, bool double_clk
, bool vpclk
)
594 u8 N
, min_N
, max_N
, clk_divider
;
595 u8 mcu_cnt
, div
, max_div
;
597 [RTSX_SSC_DEPTH_4M
] = SSC_DEPTH_4M
,
598 [RTSX_SSC_DEPTH_2M
] = SSC_DEPTH_2M
,
599 [RTSX_SSC_DEPTH_1M
] = SSC_DEPTH_1M
,
600 [RTSX_SSC_DEPTH_500K
] = SSC_DEPTH_500K
,
601 [RTSX_SSC_DEPTH_250K
] = SSC_DEPTH_250K
,
605 /* We use 250k(around) here, in initial stage */
606 clk_divider
= SD_CLK_DIVIDE_128
;
607 card_clock
= 30000000;
609 clk_divider
= SD_CLK_DIVIDE_0
;
611 err
= rtsx_pci_write_register(pcr
, SD_CFG1
,
612 SD_CLK_DIVIDE_MASK
, clk_divider
);
616 card_clock
/= 1000000;
617 dev_dbg(&(pcr
->pci
->dev
), "Switch card clock to %dMHz\n", card_clock
);
624 if (!initial_mode
&& double_clk
)
625 clk
= card_clock
* 2;
626 dev_dbg(&(pcr
->pci
->dev
),
627 "Internal SSC clock: %dMHz (cur_clock = %d)\n",
628 clk
, pcr
->cur_clock
);
630 if (clk
== pcr
->cur_clock
)
634 if ((clk
<= 2) || (N
> max_N
))
637 mcu_cnt
= (u8
)(125/clk
+ 3);
641 /* Make sure that the SSC clock div_n is equal or greater than min_N */
643 while ((N
< min_N
) && (div
< max_div
)) {
647 dev_dbg(&(pcr
->pci
->dev
), "N = %d, div = %d\n", N
, div
);
649 ssc_depth
= depth
[ssc_depth
];
651 ssc_depth
= double_ssc_depth(ssc_depth
);
653 ssc_depth
= revise_ssc_depth(ssc_depth
, div
);
654 dev_dbg(&(pcr
->pci
->dev
), "ssc_depth = %d\n", ssc_depth
);
656 rtsx_pci_init_cmd(pcr
);
657 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_CTL
,
658 CLK_LOW_FREQ
, CLK_LOW_FREQ
);
659 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
,
660 0xFF, (div
<< 4) | mcu_cnt
);
661 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, 0);
662 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
,
663 SSC_DEPTH_MASK
, ssc_depth
);
664 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_DIV_N_0
, 0xFF, N
);
665 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
, SSC_RSTB
, SSC_RSTB
);
667 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
669 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD_VPCLK0_CTL
,
670 PHASE_NOT_RESET
, PHASE_NOT_RESET
);
673 err
= rtsx_pci_send_cmd(pcr
, 2000);
677 /* Wait SSC clock stable */
679 err
= rtsx_pci_write_register(pcr
, CLK_CTL
, CLK_LOW_FREQ
, 0);
683 pcr
->cur_clock
= clk
;
686 EXPORT_SYMBOL_GPL(rtsx_pci_switch_clock
);
688 int rtsx_pci_card_power_on(struct rtsx_pcr
*pcr
, int card
)
690 if (pcr
->ops
->card_power_on
)
691 return pcr
->ops
->card_power_on(pcr
, card
);
695 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_on
);
697 int rtsx_pci_card_power_off(struct rtsx_pcr
*pcr
, int card
)
699 if (pcr
->ops
->card_power_off
)
700 return pcr
->ops
->card_power_off(pcr
, card
);
704 EXPORT_SYMBOL_GPL(rtsx_pci_card_power_off
);
706 unsigned int rtsx_pci_card_exist(struct rtsx_pcr
*pcr
)
710 val
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
711 if (pcr
->ops
->cd_deglitch
)
712 val
= pcr
->ops
->cd_deglitch(pcr
);
716 EXPORT_SYMBOL_GPL(rtsx_pci_card_exist
);
718 void rtsx_pci_complete_unfinished_transfer(struct rtsx_pcr
*pcr
)
720 struct completion finish
;
722 pcr
->finish_me
= &finish
;
723 init_completion(&finish
);
728 if (!pcr
->remove_pci
)
729 rtsx_pci_stop_cmd(pcr
);
731 wait_for_completion_interruptible_timeout(&finish
,
732 msecs_to_jiffies(2));
733 pcr
->finish_me
= NULL
;
735 EXPORT_SYMBOL_GPL(rtsx_pci_complete_unfinished_transfer
);
737 static void rtsx_pci_card_detect(struct work_struct
*work
)
739 struct delayed_work
*dwork
;
740 struct rtsx_pcr
*pcr
;
742 unsigned int card_detect
= 0;
745 dwork
= to_delayed_work(work
);
746 pcr
= container_of(dwork
, struct rtsx_pcr
, carddet_work
);
748 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
750 spin_lock_irqsave(&pcr
->lock
, flags
);
752 irq_status
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
753 dev_dbg(&(pcr
->pci
->dev
), "irq_status: 0x%08x\n", irq_status
);
755 if (pcr
->card_inserted
|| pcr
->card_removed
) {
756 dev_dbg(&(pcr
->pci
->dev
),
757 "card_inserted: 0x%x, card_removed: 0x%x\n",
758 pcr
->card_inserted
, pcr
->card_removed
);
760 if (pcr
->ops
->cd_deglitch
)
761 pcr
->card_inserted
= pcr
->ops
->cd_deglitch(pcr
);
763 card_detect
= pcr
->card_inserted
| pcr
->card_removed
;
764 pcr
->card_inserted
= 0;
765 pcr
->card_removed
= 0;
768 spin_unlock_irqrestore(&pcr
->lock
, flags
);
770 if (card_detect
& SD_EXIST
)
771 pcr
->slots
[RTSX_SD_CARD
].card_event(
772 pcr
->slots
[RTSX_SD_CARD
].p_dev
);
773 if (card_detect
& MS_EXIST
)
774 pcr
->slots
[RTSX_MS_CARD
].card_event(
775 pcr
->slots
[RTSX_MS_CARD
].p_dev
);
778 static irqreturn_t
rtsx_pci_isr(int irq
, void *dev_id
)
780 struct rtsx_pcr
*pcr
= dev_id
;
786 spin_lock(&pcr
->lock
);
788 int_reg
= rtsx_pci_readl(pcr
, RTSX_BIPR
);
789 /* Clear interrupt flag */
790 rtsx_pci_writel(pcr
, RTSX_BIPR
, int_reg
);
791 if ((int_reg
& pcr
->bier
) == 0) {
792 spin_unlock(&pcr
->lock
);
795 if (int_reg
== 0xFFFFFFFF) {
796 spin_unlock(&pcr
->lock
);
800 int_reg
&= (pcr
->bier
| 0x7FFFFF);
802 if (int_reg
& SD_INT
) {
803 if (int_reg
& SD_EXIST
) {
804 pcr
->card_inserted
|= SD_EXIST
;
806 pcr
->card_removed
|= SD_EXIST
;
807 pcr
->card_inserted
&= ~SD_EXIST
;
811 if (int_reg
& MS_INT
) {
812 if (int_reg
& MS_EXIST
) {
813 pcr
->card_inserted
|= MS_EXIST
;
815 pcr
->card_removed
|= MS_EXIST
;
816 pcr
->card_inserted
&= ~MS_EXIST
;
820 if (pcr
->card_inserted
|| pcr
->card_removed
)
821 schedule_delayed_work(&pcr
->carddet_work
,
822 msecs_to_jiffies(200));
824 if (int_reg
& (NEED_COMPLETE_INT
| DELINK_INT
)) {
825 if (int_reg
& (TRANS_FAIL_INT
| DELINK_INT
)) {
826 pcr
->trans_result
= TRANS_RESULT_FAIL
;
829 } else if (int_reg
& TRANS_OK_INT
) {
830 pcr
->trans_result
= TRANS_RESULT_OK
;
836 spin_unlock(&pcr
->lock
);
840 static int rtsx_pci_acquire_irq(struct rtsx_pcr
*pcr
)
842 dev_info(&(pcr
->pci
->dev
), "%s: pcr->msi_en = %d, pci->irq = %d\n",
843 __func__
, pcr
->msi_en
, pcr
->pci
->irq
);
845 if (request_irq(pcr
->pci
->irq
, rtsx_pci_isr
,
846 pcr
->msi_en
? 0 : IRQF_SHARED
,
847 DRV_NAME_RTSX_PCI
, pcr
)) {
848 dev_err(&(pcr
->pci
->dev
),
849 "rtsx_sdmmc: unable to grab IRQ %d, disabling device\n",
854 pcr
->irq
= pcr
->pci
->irq
;
855 pci_intx(pcr
->pci
, !pcr
->msi_en
);
860 static void rtsx_pci_idle_work(struct work_struct
*work
)
862 struct delayed_work
*dwork
= to_delayed_work(work
);
863 struct rtsx_pcr
*pcr
= container_of(dwork
, struct rtsx_pcr
, idle_work
);
865 dev_dbg(&(pcr
->pci
->dev
), "--> %s\n", __func__
);
867 mutex_lock(&pcr
->pcr_mutex
);
869 pcr
->state
= PDEV_STAT_IDLE
;
871 if (pcr
->ops
->disable_auto_blink
)
872 pcr
->ops
->disable_auto_blink(pcr
);
873 if (pcr
->ops
->turn_off_led
)
874 pcr
->ops
->turn_off_led(pcr
);
876 mutex_unlock(&pcr
->pcr_mutex
);
879 static int rtsx_pci_init_hw(struct rtsx_pcr
*pcr
)
883 rtsx_pci_writel(pcr
, RTSX_HCBAR
, pcr
->host_cmds_addr
);
885 rtsx_pci_enable_bus_int(pcr
);
888 err
= rtsx_pci_write_register(pcr
, FPDCTL
, SSC_POWER_DOWN
, 0);
892 /* Wait SSC power stable */
895 if (pcr
->ops
->optimize_phy
) {
896 err
= pcr
->ops
->optimize_phy(pcr
);
901 rtsx_pci_init_cmd(pcr
);
903 /* Set mcu_cnt to 7 to ensure data can be sampled properly */
904 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CLK_DIV
, 0x07, 0x07);
906 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, HOST_SLEEP_STATE
, 0x03, 0x00);
907 /* Disable card clock */
908 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CARD_CLK_EN
, 0x1E, 0);
909 /* Reset ASPM state to default value */
910 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, ASPM_FORCE_CTL
, 0x3F, 0);
911 /* Reset delink mode */
912 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x0A, 0);
913 /* Card driving select */
914 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SD30_DRIVE_SEL
,
915 0x07, DRIVER_TYPE_D
);
916 /* Enable SSC Clock */
917 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL1
,
918 0xFF, SSC_8X_EN
| SSC_SEL_4M
);
919 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, SSC_CTL2
, 0xFF, 0x12);
920 /* Disable cd_pwr_save */
921 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, CHANGE_LINK_STATE
, 0x16, 0x10);
922 /* Clear Link Ready Interrupt */
923 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, IRQSTAT0
,
924 LINK_RDY_INT
, LINK_RDY_INT
);
925 /* Enlarge the estimation window of PERST# glitch
926 * to reduce the chance of invalid card interrupt
928 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PERST_GLITCH_WIDTH
, 0xFF, 0x80);
929 /* Update RC oscillator to 400k
930 * bit[0] F_HIGH: for RC oscillator, Rst_value is 1'b1
933 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, RCCTL
, 0x01, 0x00);
934 /* Set interrupt write clear
935 * bit 1: U_elbi_if_rd_clr_en
936 * 1: Enable ELBI interrupt[31:22] & [7:0] flag read clear
937 * 0: ELBI interrupt flag[31:22] & [7:0] only can be write clear
939 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, NFTS_TX_CTRL
, 0x02, 0);
940 /* Force CLKREQ# PIN to drive 0 to request clock */
941 rtsx_pci_add_cmd(pcr
, WRITE_REG_CMD
, PETXCFG
, 0x08, 0x08);
943 err
= rtsx_pci_send_cmd(pcr
, 100);
947 /* Enable clk_request_n to enable clock power management */
948 rtsx_pci_write_config_byte(pcr
, 0x81, 1);
949 /* Enter L1 when host tx idle */
950 rtsx_pci_write_config_byte(pcr
, 0x70F, 0x5B);
952 if (pcr
->ops
->extra_init_hw
) {
953 err
= pcr
->ops
->extra_init_hw(pcr
);
961 static int rtsx_pci_init_chip(struct rtsx_pcr
*pcr
)
965 spin_lock_init(&pcr
->lock
);
966 mutex_init(&pcr
->pcr_mutex
);
968 switch (PCI_PID(pcr
)) {
971 rts5209_init_params(pcr
);
975 rts5229_init_params(pcr
);
979 rtl8411_init_params(pcr
);
983 dev_dbg(&(pcr
->pci
->dev
), "PID: 0x%04x, IC version: 0x%02x\n",
984 PCI_PID(pcr
), pcr
->ic_version
);
986 pcr
->slots
= kcalloc(pcr
->num_slots
, sizeof(struct rtsx_slot
),
991 pcr
->state
= PDEV_STAT_IDLE
;
992 err
= rtsx_pci_init_hw(pcr
);
1001 static int rtsx_pci_probe(struct pci_dev
*pcidev
,
1002 const struct pci_device_id
*id
)
1004 struct rtsx_pcr
*pcr
;
1005 struct pcr_handle
*handle
;
1009 dev_dbg(&(pcidev
->dev
),
1010 ": Realtek PCI-E Card Reader found at %s [%04x:%04x] (rev %x)\n",
1011 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
,
1012 (int)pcidev
->revision
);
1014 ret
= pci_enable_device(pcidev
);
1018 ret
= pci_request_regions(pcidev
, DRV_NAME_RTSX_PCI
);
1022 pcr
= kzalloc(sizeof(*pcr
), GFP_KERNEL
);
1028 handle
= kzalloc(sizeof(*handle
), GFP_KERNEL
);
1035 if (!idr_pre_get(&rtsx_pci_idr
, GFP_KERNEL
)) {
1040 spin_lock(&rtsx_pci_lock
);
1041 ret
= idr_get_new(&rtsx_pci_idr
, pcr
, &pcr
->id
);
1042 spin_unlock(&rtsx_pci_lock
);
1047 dev_set_drvdata(&pcidev
->dev
, handle
);
1049 len
= pci_resource_len(pcidev
, 0);
1050 base
= pci_resource_start(pcidev
, 0);
1051 pcr
->remap_addr
= ioremap_nocache(base
, len
);
1052 if (!pcr
->remap_addr
) {
1057 pcr
->rtsx_resv_buf
= dma_alloc_coherent(&(pcidev
->dev
),
1058 RTSX_RESV_BUF_LEN
, &(pcr
->rtsx_resv_buf_addr
),
1060 if (pcr
->rtsx_resv_buf
== NULL
) {
1064 pcr
->host_cmds_ptr
= pcr
->rtsx_resv_buf
;
1065 pcr
->host_cmds_addr
= pcr
->rtsx_resv_buf_addr
;
1066 pcr
->host_sg_tbl_ptr
= pcr
->rtsx_resv_buf
+ HOST_CMDS_BUF_LEN
;
1067 pcr
->host_sg_tbl_addr
= pcr
->rtsx_resv_buf_addr
+ HOST_CMDS_BUF_LEN
;
1069 pcr
->card_inserted
= 0;
1070 pcr
->card_removed
= 0;
1071 INIT_DELAYED_WORK(&pcr
->carddet_work
, rtsx_pci_card_detect
);
1072 INIT_DELAYED_WORK(&pcr
->idle_work
, rtsx_pci_idle_work
);
1074 pcr
->msi_en
= msi_en
;
1076 ret
= pci_enable_msi(pcidev
);
1078 pcr
->msi_en
= false;
1081 ret
= rtsx_pci_acquire_irq(pcr
);
1085 pci_set_master(pcidev
);
1086 synchronize_irq(pcr
->irq
);
1088 ret
= rtsx_pci_init_chip(pcr
);
1092 for (i
= 0; i
< ARRAY_SIZE(rtsx_pcr_cells
); i
++) {
1093 rtsx_pcr_cells
[i
].platform_data
= handle
;
1094 rtsx_pcr_cells
[i
].pdata_size
= sizeof(*handle
);
1096 ret
= mfd_add_devices(&pcidev
->dev
, pcr
->id
, rtsx_pcr_cells
,
1097 ARRAY_SIZE(rtsx_pcr_cells
), NULL
, 0, NULL
);
1101 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1106 free_irq(pcr
->irq
, (void *)pcr
);
1108 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1109 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1111 iounmap(pcr
->remap_addr
);
1113 dev_set_drvdata(&pcidev
->dev
, NULL
);
1119 pci_release_regions(pcidev
);
1121 pci_disable_device(pcidev
);
1126 static void rtsx_pci_remove(struct pci_dev
*pcidev
)
1128 struct pcr_handle
*handle
= pci_get_drvdata(pcidev
);
1129 struct rtsx_pcr
*pcr
= handle
->pcr
;
1131 pcr
->remove_pci
= true;
1133 cancel_delayed_work(&pcr
->carddet_work
);
1134 cancel_delayed_work(&pcr
->idle_work
);
1136 mfd_remove_devices(&pcidev
->dev
);
1138 dma_free_coherent(&(pcr
->pci
->dev
), RTSX_RESV_BUF_LEN
,
1139 pcr
->rtsx_resv_buf
, pcr
->rtsx_resv_buf_addr
);
1140 free_irq(pcr
->irq
, (void *)pcr
);
1142 pci_disable_msi(pcr
->pci
);
1143 iounmap(pcr
->remap_addr
);
1145 dev_set_drvdata(&pcidev
->dev
, NULL
);
1146 pci_release_regions(pcidev
);
1147 pci_disable_device(pcidev
);
1149 spin_lock(&rtsx_pci_lock
);
1150 idr_remove(&rtsx_pci_idr
, pcr
->id
);
1151 spin_unlock(&rtsx_pci_lock
);
1157 dev_dbg(&(pcidev
->dev
),
1158 ": Realtek PCI-E Card Reader at %s [%04x:%04x] has been removed\n",
1159 pci_name(pcidev
), (int)pcidev
->vendor
, (int)pcidev
->device
);
1164 static int rtsx_pci_suspend(struct pci_dev
*pcidev
, pm_message_t state
)
1166 struct pcr_handle
*handle
;
1167 struct rtsx_pcr
*pcr
;
1170 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1172 handle
= pci_get_drvdata(pcidev
);
1175 cancel_delayed_work(&pcr
->carddet_work
);
1176 cancel_delayed_work(&pcr
->idle_work
);
1178 mutex_lock(&pcr
->pcr_mutex
);
1180 if (pcr
->ops
->turn_off_led
)
1181 pcr
->ops
->turn_off_led(pcr
);
1183 rtsx_pci_writel(pcr
, RTSX_BIER
, 0);
1186 rtsx_pci_write_register(pcr
, PETXCFG
, 0x08, 0x08);
1187 rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, 0x02);
1189 pci_save_state(pcidev
);
1190 pci_enable_wake(pcidev
, pci_choose_state(pcidev
, state
), 0);
1191 pci_disable_device(pcidev
);
1192 pci_set_power_state(pcidev
, pci_choose_state(pcidev
, state
));
1194 mutex_unlock(&pcr
->pcr_mutex
);
1198 static int rtsx_pci_resume(struct pci_dev
*pcidev
)
1200 struct pcr_handle
*handle
;
1201 struct rtsx_pcr
*pcr
;
1204 dev_dbg(&(pcidev
->dev
), "--> %s\n", __func__
);
1206 handle
= pci_get_drvdata(pcidev
);
1209 mutex_lock(&pcr
->pcr_mutex
);
1211 pci_set_power_state(pcidev
, PCI_D0
);
1212 pci_restore_state(pcidev
);
1213 ret
= pci_enable_device(pcidev
);
1216 pci_set_master(pcidev
);
1218 ret
= rtsx_pci_write_register(pcr
, HOST_SLEEP_STATE
, 0x03, 0x00);
1222 ret
= rtsx_pci_init_hw(pcr
);
1226 schedule_delayed_work(&pcr
->idle_work
, msecs_to_jiffies(200));
1229 mutex_unlock(&pcr
->pcr_mutex
);
1233 #else /* CONFIG_PM */
1235 #define rtsx_pci_suspend NULL
1236 #define rtsx_pci_resume NULL
1238 #endif /* CONFIG_PM */
1240 static struct pci_driver rtsx_pci_driver
= {
1241 .name
= DRV_NAME_RTSX_PCI
,
1242 .id_table
= rtsx_pci_ids
,
1243 .probe
= rtsx_pci_probe
,
1244 .remove
= rtsx_pci_remove
,
1245 .suspend
= rtsx_pci_suspend
,
1246 .resume
= rtsx_pci_resume
,
1248 module_pci_driver(rtsx_pci_driver
);
1250 MODULE_LICENSE("GPL");
1251 MODULE_AUTHOR("Wei WANG <wei_wang@realsil.com.cn>");
1252 MODULE_DESCRIPTION("Realtek PCI-E Card Reader Driver");