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ath9k_hw: add pcieSerDesWrite to disable SERDES ASPM tweaks
[linux-2.6/btrfs-unstable.git] / drivers / net / wireless / ath / ath9k / hw.h
blobe9578a4c912f510b713f4e6248dbbfd7eb06ca97
1 /*
2 * Copyright (c) 2008-2010 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #ifndef HW_H
18 #define HW_H
19
20 #include <linux/if_ether.h>
21 #include <linux/delay.h>
22 #include <linux/io.h>
23
24 #include "mac.h"
25 #include "ani.h"
26 #include "eeprom.h"
27 #include "calib.h"
28 #include "reg.h"
29 #include "phy.h"
30 #include "btcoex.h"
31
32 #include "../regd.h"
33 #include "../debug.h"
34
35 #define ATHEROS_VENDOR_ID 0x168c
36
37 #define AR5416_DEVID_PCI 0x0023
38 #define AR5416_DEVID_PCIE 0x0024
39 #define AR9160_DEVID_PCI 0x0027
40 #define AR9280_DEVID_PCI 0x0029
41 #define AR9280_DEVID_PCIE 0x002a
42 #define AR9285_DEVID_PCIE 0x002b
43 #define AR2427_DEVID_PCIE 0x002c
44 #define AR9287_DEVID_PCI 0x002d
45 #define AR9287_DEVID_PCIE 0x002e
46 #define AR9300_DEVID_PCIE 0x0030
47
48 #define AR5416_AR9100_DEVID 0x000b
49
50 #define AR_SUBVENDOR_ID_NOG 0x0e11
51 #define AR_SUBVENDOR_ID_NEW_A 0x7065
52 #define AR5416_MAGIC 0x19641014
53
54 #define AR9280_COEX2WIRE_SUBSYSID 0x309b
55 #define AT9285_COEX3WIRE_SA_SUBSYSID 0x30aa
56 #define AT9285_COEX3WIRE_DA_SUBSYSID 0x30ab
57
58 #define ATH_AMPDU_LIMIT_MAX (64 * 1024 - 1)
59
60 #define ATH_DEFAULT_NOISE_FLOOR -95
61
62 #define ATH9K_RSSI_BAD -128
63
64 /* Register read/write primitives */
65 #define REG_WRITE(_ah, _reg, _val) \
66 ath9k_hw_common(_ah)->ops->write((_ah), (_val), (_reg))
67
68 #define REG_READ(_ah, _reg) \
69 ath9k_hw_common(_ah)->ops->read((_ah), (_reg))
70
71 #define ENABLE_REGWRITE_BUFFER(_ah) \
72 do { \
73 if (AR_SREV_9271(_ah)) \
74 ath9k_hw_common(_ah)->ops->enable_write_buffer((_ah)); \
75 } while (0)
76
77 #define DISABLE_REGWRITE_BUFFER(_ah) \
78 do { \
79 if (AR_SREV_9271(_ah)) \
80 ath9k_hw_common(_ah)->ops->disable_write_buffer((_ah)); \
81 } while (0)
82
83 #define REGWRITE_BUFFER_FLUSH(_ah) \
84 do { \
85 if (AR_SREV_9271(_ah)) \
86 ath9k_hw_common(_ah)->ops->write_flush((_ah)); \
87 } while (0)
88
89 #define SM(_v, _f) (((_v) << _f##_S) & _f)
90 #define MS(_v, _f) (((_v) & _f) >> _f##_S)
91 #define REG_RMW(_a, _r, _set, _clr) \
92 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
93 #define REG_RMW_FIELD(_a, _r, _f, _v) \
94 REG_WRITE(_a, _r, \
95 (REG_READ(_a, _r) & ~_f) | (((_v) << _f##_S) & _f))
96 #define REG_READ_FIELD(_a, _r, _f) \
97 (((REG_READ(_a, _r) & _f) >> _f##_S))
98 #define REG_SET_BIT(_a, _r, _f) \
99 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
100 #define REG_CLR_BIT(_a, _r, _f) \
101 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
102
103 #define DO_DELAY(x) do { \
104 if ((++(x) % 64) == 0) \
105 udelay(1); \
106 } while (0)
107
108 #define REG_WRITE_ARRAY(iniarray, column, regWr) do { \
109 int r; \
110 for (r = 0; r < ((iniarray)->ia_rows); r++) { \
111 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
112 INI_RA((iniarray), r, (column))); \
113 DO_DELAY(regWr); \
114 } \
115 } while (0)
116
117 #define AR_GPIO_OUTPUT_MUX_AS_OUTPUT 0
118 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED 1
119 #define AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED 2
120 #define AR_GPIO_OUTPUT_MUX_AS_TX_FRAME 3
121 #define AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL 4
122 #define AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED 5
123 #define AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED 6
124
125 #define AR_GPIOD_MASK 0x00001FFF
126 #define AR_GPIO_BIT(_gpio) (1 << (_gpio))
127
128 #define BASE_ACTIVATE_DELAY 100
129 #define RTC_PLL_SETTLE_DELAY 100
130 #define COEF_SCALE_S 24
131 #define HT40_CHANNEL_CENTER_SHIFT 10
132
133 #define ATH9K_ANTENNA0_CHAINMASK 0x1
134 #define ATH9K_ANTENNA1_CHAINMASK 0x2
135
136 #define ATH9K_NUM_DMA_DEBUG_REGS 8
137 #define ATH9K_NUM_QUEUES 10
138
139 #define MAX_RATE_POWER 63
140 #define AH_WAIT_TIMEOUT 100000 /* (us) */
141 #define AH_TSF_WRITE_TIMEOUT 100 /* (us) */
142 #define AH_TIME_QUANTUM 10
143 #define AR_KEYTABLE_SIZE 128
144 #define POWER_UP_TIME 10000
145 #define SPUR_RSSI_THRESH 40
146
147 #define CAB_TIMEOUT_VAL 10
148 #define BEACON_TIMEOUT_VAL 10
149 #define MIN_BEACON_TIMEOUT_VAL 1
150 #define SLEEP_SLOP 3
151
152 #define INIT_CONFIG_STATUS 0x00000000
153 #define INIT_RSSI_THR 0x00000700
154 #define INIT_BCON_CNTRL_REG 0x00000000
155
156 #define TU_TO_USEC(_tu) ((_tu) << 10)
157
158 #define ATH9K_HW_RX_HP_QDEPTH 16
159 #define ATH9K_HW_RX_LP_QDEPTH 128
160
161 #define PAPRD_GAIN_TABLE_ENTRIES 32
162 #define PAPRD_TABLE_SZ 24
163
164 enum ath_ini_subsys {
165 ATH_INI_PRE = 0,
166 ATH_INI_CORE,
167 ATH_INI_POST,
168 ATH_INI_NUM_SPLIT,
169 };
170
171 enum wireless_mode {
172 ATH9K_MODE_11A = 0,
173 ATH9K_MODE_11G,
174 ATH9K_MODE_11NA_HT20,
175 ATH9K_MODE_11NG_HT20,
176 ATH9K_MODE_11NA_HT40PLUS,
177 ATH9K_MODE_11NA_HT40MINUS,
178 ATH9K_MODE_11NG_HT40PLUS,
179 ATH9K_MODE_11NG_HT40MINUS,
180 ATH9K_MODE_MAX,
181 };
182
183 enum ath9k_hw_caps {
184 ATH9K_HW_CAP_MIC_AESCCM = BIT(0),
185 ATH9K_HW_CAP_MIC_CKIP = BIT(1),
186 ATH9K_HW_CAP_MIC_TKIP = BIT(2),
187 ATH9K_HW_CAP_CIPHER_AESCCM = BIT(3),
188 ATH9K_HW_CAP_CIPHER_CKIP = BIT(4),
189 ATH9K_HW_CAP_CIPHER_TKIP = BIT(5),
190 ATH9K_HW_CAP_VEOL = BIT(6),
191 ATH9K_HW_CAP_BSSIDMASK = BIT(7),
192 ATH9K_HW_CAP_MCAST_KEYSEARCH = BIT(8),
193 ATH9K_HW_CAP_HT = BIT(9),
194 ATH9K_HW_CAP_GTT = BIT(10),
195 ATH9K_HW_CAP_FASTCC = BIT(11),
196 ATH9K_HW_CAP_RFSILENT = BIT(12),
197 ATH9K_HW_CAP_CST = BIT(13),
198 ATH9K_HW_CAP_ENHANCEDPM = BIT(14),
199 ATH9K_HW_CAP_AUTOSLEEP = BIT(15),
200 ATH9K_HW_CAP_4KB_SPLITTRANS = BIT(16),
201 ATH9K_HW_CAP_EDMA = BIT(17),
202 ATH9K_HW_CAP_RAC_SUPPORTED = BIT(18),
203 ATH9K_HW_CAP_LDPC = BIT(19),
204 ATH9K_HW_CAP_FASTCLOCK = BIT(20),
205 ATH9K_HW_CAP_SGI_20 = BIT(21),
206 ATH9K_HW_CAP_PAPRD = BIT(22),
207 };
208
209 struct ath9k_hw_capabilities {
210 u32 hw_caps; /* ATH9K_HW_CAP_* from ath9k_hw_caps */
211 DECLARE_BITMAP(wireless_modes, ATH9K_MODE_MAX); /* ATH9K_MODE_* */
212 u16 total_queues;
213 u16 keycache_size;
214 u16 low_5ghz_chan, high_5ghz_chan;
215 u16 low_2ghz_chan, high_2ghz_chan;
216 u16 rts_aggr_limit;
217 u8 tx_chainmask;
218 u8 rx_chainmask;
219 u16 tx_triglevel_max;
220 u16 reg_cap;
221 u8 num_gpio_pins;
222 u8 num_antcfg_2ghz;
223 u8 num_antcfg_5ghz;
224 u8 rx_hp_qdepth;
225 u8 rx_lp_qdepth;
226 u8 rx_status_len;
227 u8 tx_desc_len;
228 u8 txs_len;
229 };
230
231 struct ath9k_ops_config {
232 int dma_beacon_response_time;
233 int sw_beacon_response_time;
234 int additional_swba_backoff;
235 int ack_6mb;
236 u32 cwm_ignore_extcca;
237 u8 pcie_powersave_enable;
238 bool pcieSerDesWrite;
239 u8 pcie_clock_req;
240 u32 pcie_waen;
241 u8 analog_shiftreg;
242 u8 ht_enable;
243 u32 ofdm_trig_low;
244 u32 ofdm_trig_high;
245 u32 cck_trig_high;
246 u32 cck_trig_low;
247 u32 enable_ani;
248 int serialize_regmode;
249 bool rx_intr_mitigation;
250 bool tx_intr_mitigation;
251 #define SPUR_DISABLE 0
252 #define SPUR_ENABLE_IOCTL 1
253 #define SPUR_ENABLE_EEPROM 2
254 #define AR_EEPROM_MODAL_SPURS 5
255 #define AR_SPUR_5413_1 1640
256 #define AR_SPUR_5413_2 1200
257 #define AR_NO_SPUR 0x8000
258 #define AR_BASE_FREQ_2GHZ 2300
259 #define AR_BASE_FREQ_5GHZ 4900
260 #define AR_SPUR_FEEQ_BOUND_HT40 19
261 #define AR_SPUR_FEEQ_BOUND_HT20 10
262 int spurmode;
263 u16 spurchans[AR_EEPROM_MODAL_SPURS][2];
264 u8 max_txtrig_level;
265 u16 ani_poll_interval; /* ANI poll interval in ms */
266 };
267
268 enum ath9k_int {
269 ATH9K_INT_RX = 0x00000001,
270 ATH9K_INT_RXDESC = 0x00000002,
271 ATH9K_INT_RXHP = 0x00000001,
272 ATH9K_INT_RXLP = 0x00000002,
273 ATH9K_INT_RXNOFRM = 0x00000008,
274 ATH9K_INT_RXEOL = 0x00000010,
275 ATH9K_INT_RXORN = 0x00000020,
276 ATH9K_INT_TX = 0x00000040,
277 ATH9K_INT_TXDESC = 0x00000080,
278 ATH9K_INT_TIM_TIMER = 0x00000100,
279 ATH9K_INT_BB_WATCHDOG = 0x00000400,
280 ATH9K_INT_TXURN = 0x00000800,
281 ATH9K_INT_MIB = 0x00001000,
282 ATH9K_INT_RXPHY = 0x00004000,
283 ATH9K_INT_RXKCM = 0x00008000,
284 ATH9K_INT_SWBA = 0x00010000,
285 ATH9K_INT_BMISS = 0x00040000,
286 ATH9K_INT_BNR = 0x00100000,
287 ATH9K_INT_TIM = 0x00200000,
288 ATH9K_INT_DTIM = 0x00400000,
289 ATH9K_INT_DTIMSYNC = 0x00800000,
290 ATH9K_INT_GPIO = 0x01000000,
291 ATH9K_INT_CABEND = 0x02000000,
292 ATH9K_INT_TSFOOR = 0x04000000,
293 ATH9K_INT_GENTIMER = 0x08000000,
294 ATH9K_INT_CST = 0x10000000,
295 ATH9K_INT_GTT = 0x20000000,
296 ATH9K_INT_FATAL = 0x40000000,
297 ATH9K_INT_GLOBAL = 0x80000000,
298 ATH9K_INT_BMISC = ATH9K_INT_TIM |
299 ATH9K_INT_DTIM |
300 ATH9K_INT_DTIMSYNC |
301 ATH9K_INT_TSFOOR |
302 ATH9K_INT_CABEND,
303 ATH9K_INT_COMMON = ATH9K_INT_RXNOFRM |
304 ATH9K_INT_RXDESC |
305 ATH9K_INT_RXEOL |
306 ATH9K_INT_RXORN |
307 ATH9K_INT_TXURN |
308 ATH9K_INT_TXDESC |
309 ATH9K_INT_MIB |
310 ATH9K_INT_RXPHY |
311 ATH9K_INT_RXKCM |
312 ATH9K_INT_SWBA |
313 ATH9K_INT_BMISS |
314 ATH9K_INT_GPIO,
315 ATH9K_INT_NOCARD = 0xffffffff
316 };
317
318 #define CHANNEL_CW_INT 0x00002
319 #define CHANNEL_CCK 0x00020
320 #define CHANNEL_OFDM 0x00040
321 #define CHANNEL_2GHZ 0x00080
322 #define CHANNEL_5GHZ 0x00100
323 #define CHANNEL_PASSIVE 0x00200
324 #define CHANNEL_DYN 0x00400
325 #define CHANNEL_HALF 0x04000
326 #define CHANNEL_QUARTER 0x08000
327 #define CHANNEL_HT20 0x10000
328 #define CHANNEL_HT40PLUS 0x20000
329 #define CHANNEL_HT40MINUS 0x40000
330
331 #define CHANNEL_A (CHANNEL_5GHZ|CHANNEL_OFDM)
332 #define CHANNEL_B (CHANNEL_2GHZ|CHANNEL_CCK)
333 #define CHANNEL_G (CHANNEL_2GHZ|CHANNEL_OFDM)
334 #define CHANNEL_G_HT20 (CHANNEL_2GHZ|CHANNEL_HT20)
335 #define CHANNEL_A_HT20 (CHANNEL_5GHZ|CHANNEL_HT20)
336 #define CHANNEL_G_HT40PLUS (CHANNEL_2GHZ|CHANNEL_HT40PLUS)
337 #define CHANNEL_G_HT40MINUS (CHANNEL_2GHZ|CHANNEL_HT40MINUS)
338 #define CHANNEL_A_HT40PLUS (CHANNEL_5GHZ|CHANNEL_HT40PLUS)
339 #define CHANNEL_A_HT40MINUS (CHANNEL_5GHZ|CHANNEL_HT40MINUS)
340 #define CHANNEL_ALL \
341 (CHANNEL_OFDM| \
342 CHANNEL_CCK| \
343 CHANNEL_2GHZ | \
344 CHANNEL_5GHZ | \
345 CHANNEL_HT20 | \
346 CHANNEL_HT40PLUS | \
347 CHANNEL_HT40MINUS)
348
349 struct ath9k_channel {
350 struct ieee80211_channel *chan;
351 u16 channel;
352 u32 channelFlags;
353 u32 chanmode;
354 int32_t CalValid;
355 bool oneTimeCalsDone;
356 int8_t iCoff;
357 int8_t qCoff;
358 int16_t rawNoiseFloor;
359 bool paprd_done;
360 u16 small_signal_gain[AR9300_MAX_CHAINS];
361 u32 pa_table[AR9300_MAX_CHAINS][PAPRD_TABLE_SZ];
362 };
363
364 #define IS_CHAN_G(_c) ((((_c)->channelFlags & (CHANNEL_G)) == CHANNEL_G) || \
365 (((_c)->channelFlags & CHANNEL_G_HT20) == CHANNEL_G_HT20) || \
366 (((_c)->channelFlags & CHANNEL_G_HT40PLUS) == CHANNEL_G_HT40PLUS) || \
367 (((_c)->channelFlags & CHANNEL_G_HT40MINUS) == CHANNEL_G_HT40MINUS))
368 #define IS_CHAN_OFDM(_c) (((_c)->channelFlags & CHANNEL_OFDM) != 0)
369 #define IS_CHAN_5GHZ(_c) (((_c)->channelFlags & CHANNEL_5GHZ) != 0)
370 #define IS_CHAN_2GHZ(_c) (((_c)->channelFlags & CHANNEL_2GHZ) != 0)
371 #define IS_CHAN_HALF_RATE(_c) (((_c)->channelFlags & CHANNEL_HALF) != 0)
372 #define IS_CHAN_QUARTER_RATE(_c) (((_c)->channelFlags & CHANNEL_QUARTER) != 0)
373 #define IS_CHAN_A_FAST_CLOCK(_ah, _c) \
374 ((((_c)->channelFlags & CHANNEL_5GHZ) != 0) && \
375 ((_ah)->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK))
376
377 /* These macros check chanmode and not channelFlags */
378 #define IS_CHAN_B(_c) ((_c)->chanmode == CHANNEL_B)
379 #define IS_CHAN_HT20(_c) (((_c)->chanmode == CHANNEL_A_HT20) || \
380 ((_c)->chanmode == CHANNEL_G_HT20))
381 #define IS_CHAN_HT40(_c) (((_c)->chanmode == CHANNEL_A_HT40PLUS) || \
382 ((_c)->chanmode == CHANNEL_A_HT40MINUS) || \
383 ((_c)->chanmode == CHANNEL_G_HT40PLUS) || \
384 ((_c)->chanmode == CHANNEL_G_HT40MINUS))
385 #define IS_CHAN_HT(_c) (IS_CHAN_HT20((_c)) || IS_CHAN_HT40((_c)))
386
387 enum ath9k_power_mode {
388 ATH9K_PM_AWAKE = 0,
389 ATH9K_PM_FULL_SLEEP,
390 ATH9K_PM_NETWORK_SLEEP,
391 ATH9K_PM_UNDEFINED
392 };
393
394 enum ath9k_tp_scale {
395 ATH9K_TP_SCALE_MAX = 0,
396 ATH9K_TP_SCALE_50,
397 ATH9K_TP_SCALE_25,
398 ATH9K_TP_SCALE_12,
399 ATH9K_TP_SCALE_MIN
400 };
401
402 enum ser_reg_mode {
403 SER_REG_MODE_OFF = 0,
404 SER_REG_MODE_ON = 1,
405 SER_REG_MODE_AUTO = 2,
406 };
407
408 enum ath9k_rx_qtype {
409 ATH9K_RX_QUEUE_HP,
410 ATH9K_RX_QUEUE_LP,
411 ATH9K_RX_QUEUE_MAX,
412 };
413
414 struct ath9k_beacon_state {
415 u32 bs_nexttbtt;
416 u32 bs_nextdtim;
417 u32 bs_intval;
418 #define ATH9K_BEACON_PERIOD 0x0000ffff
419 #define ATH9K_BEACON_ENA 0x00800000
420 #define ATH9K_BEACON_RESET_TSF 0x01000000
421 #define ATH9K_TSFOOR_THRESHOLD 0x00004240 /* 16k us */
422 u32 bs_dtimperiod;
423 u16 bs_cfpperiod;
424 u16 bs_cfpmaxduration;
425 u32 bs_cfpnext;
426 u16 bs_timoffset;
427 u16 bs_bmissthreshold;
428 u32 bs_sleepduration;
429 u32 bs_tsfoor_threshold;
430 };
431
432 struct chan_centers {
433 u16 synth_center;
434 u16 ctl_center;
435 u16 ext_center;
436 };
437
438 enum {
439 ATH9K_RESET_POWER_ON,
440 ATH9K_RESET_WARM,
441 ATH9K_RESET_COLD,
442 };
443
444 struct ath9k_hw_version {
445 u32 magic;
446 u16 devid;
447 u16 subvendorid;
448 u32 macVersion;
449 u16 macRev;
450 u16 phyRev;
451 u16 analog5GhzRev;
452 u16 analog2GhzRev;
453 u16 subsysid;
454 };
455
456 /* Generic TSF timer definitions */
457
458 #define ATH_MAX_GEN_TIMER 16
459
460 #define AR_GENTMR_BIT(_index) (1 << (_index))
461
462 /*
463 * Using de Bruijin sequence to look up 1's index in a 32 bit number
464 * debruijn32 = 0000 0111 0111 1100 1011 0101 0011 0001
465 */
466 #define debruijn32 0x077CB531U
467
468 struct ath_gen_timer_configuration {
469 u32 next_addr;
470 u32 period_addr;
471 u32 mode_addr;
472 u32 mode_mask;
473 };
474
475 struct ath_gen_timer {
476 void (*trigger)(void *arg);
477 void (*overflow)(void *arg);
478 void *arg;
479 u8 index;
480 };
481
482 struct ath_gen_timer_table {
483 u32 gen_timer_index[32];
484 struct ath_gen_timer *timers[ATH_MAX_GEN_TIMER];
485 union {
486 unsigned long timer_bits;
487 u16 val;
488 } timer_mask;
489 };
490
491 /**
492 * struct ath_hw_private_ops - callbacks used internally by hardware code
493 *
494 * This structure contains private callbacks designed to only be used internally
495 * by the hardware core.
496 *
497 * @init_cal_settings: setup types of calibrations supported
498 * @init_cal: starts actual calibration
499 *
500 * @init_mode_regs: Initializes mode registers
501 * @init_mode_gain_regs: Initialize TX/RX gain registers
502 * @macversion_supported: If this specific mac revision is supported
503 *
504 * @rf_set_freq: change frequency
505 * @spur_mitigate_freq: spur mitigation
506 * @rf_alloc_ext_banks:
507 * @rf_free_ext_banks:
508 * @set_rf_regs:
509 * @compute_pll_control: compute the PLL control value to use for
510 * AR_RTC_PLL_CONTROL for a given channel
511 * @setup_calibration: set up calibration
512 * @iscal_supported: used to query if a type of calibration is supported
513 * @loadnf: load noise floor read from each chain on the CCA registers
514 *
515 * @ani_reset: reset ANI parameters to default values
516 * @ani_lower_immunity: lower the noise immunity level. The level controls
517 * the power-based packet detection on hardware. If a power jump is
518 * detected the adapter takes it as an indication that a packet has
519 * arrived. The level ranges from 0-5. Each level corresponds to a
520 * few dB more of noise immunity. If you have a strong time-varying
521 * interference that is causing false detections (OFDM timing errors or
522 * CCK timing errors) the level can be increased.
523 * @ani_cache_ini_regs: cache the values for ANI from the initial
524 * register settings through the register initialization.
525 */
526 struct ath_hw_private_ops {
527 /* Calibration ops */
528 void (*init_cal_settings)(struct ath_hw *ah);
529 bool (*init_cal)(struct ath_hw *ah, struct ath9k_channel *chan);
530
531 void (*init_mode_regs)(struct ath_hw *ah);
532 void (*init_mode_gain_regs)(struct ath_hw *ah);
533 bool (*macversion_supported)(u32 macversion);
534 void (*setup_calibration)(struct ath_hw *ah,
535 struct ath9k_cal_list *currCal);
536 bool (*iscal_supported)(struct ath_hw *ah,
537 enum ath9k_cal_types calType);
538
539 /* PHY ops */
540 int (*rf_set_freq)(struct ath_hw *ah,
541 struct ath9k_channel *chan);
542 void (*spur_mitigate_freq)(struct ath_hw *ah,
543 struct ath9k_channel *chan);
544 int (*rf_alloc_ext_banks)(struct ath_hw *ah);
545 void (*rf_free_ext_banks)(struct ath_hw *ah);
546 bool (*set_rf_regs)(struct ath_hw *ah,
547 struct ath9k_channel *chan,
548 u16 modesIndex);
549 void (*set_channel_regs)(struct ath_hw *ah, struct ath9k_channel *chan);
550 void (*init_bb)(struct ath_hw *ah,
551 struct ath9k_channel *chan);
552 int (*process_ini)(struct ath_hw *ah, struct ath9k_channel *chan);
553 void (*olc_init)(struct ath_hw *ah);
554 void (*set_rfmode)(struct ath_hw *ah, struct ath9k_channel *chan);
555 void (*mark_phy_inactive)(struct ath_hw *ah);
556 void (*set_delta_slope)(struct ath_hw *ah, struct ath9k_channel *chan);
557 bool (*rfbus_req)(struct ath_hw *ah);
558 void (*rfbus_done)(struct ath_hw *ah);
559 void (*enable_rfkill)(struct ath_hw *ah);
560 void (*restore_chainmask)(struct ath_hw *ah);
561 void (*set_diversity)(struct ath_hw *ah, bool value);
562 u32 (*compute_pll_control)(struct ath_hw *ah,
563 struct ath9k_channel *chan);
564 bool (*ani_control)(struct ath_hw *ah, enum ath9k_ani_cmd cmd,
565 int param);
566 void (*do_getnf)(struct ath_hw *ah, int16_t nfarray[NUM_NF_READINGS]);
567 void (*loadnf)(struct ath_hw *ah, struct ath9k_channel *chan);
568
569 /* ANI */
570 void (*ani_reset)(struct ath_hw *ah, bool is_scanning);
571 void (*ani_lower_immunity)(struct ath_hw *ah);
572 void (*ani_cache_ini_regs)(struct ath_hw *ah);
573 };
574
575 /**
576 * struct ath_hw_ops - callbacks used by hardware code and driver code
577 *
578 * This structure contains callbacks designed to to be used internally by
579 * hardware code and also by the lower level driver.
580 *
581 * @config_pci_powersave:
582 * @calibrate: periodic calibration for NF, ANI, IQ, ADC gain, ADC-DC
583 *
584 * @ani_proc_mib_event: process MIB events, this would happen upon specific ANI
585 * thresholds being reached or having overflowed.
586 * @ani_monitor: called periodically by the core driver to collect
587 * MIB stats and adjust ANI if specific thresholds have been reached.
588 */
589 struct ath_hw_ops {
590 void (*config_pci_powersave)(struct ath_hw *ah,
591 int restore,
592 int power_off);
593 void (*rx_enable)(struct ath_hw *ah);
594 void (*set_desc_link)(void *ds, u32 link);
595 void (*get_desc_link)(void *ds, u32 **link);
596 bool (*calibrate)(struct ath_hw *ah,
597 struct ath9k_channel *chan,
598 u8 rxchainmask,
599 bool longcal);
600 bool (*get_isr)(struct ath_hw *ah, enum ath9k_int *masked);
601 void (*fill_txdesc)(struct ath_hw *ah, void *ds, u32 seglen,
602 bool is_firstseg, bool is_is_lastseg,
603 const void *ds0, dma_addr_t buf_addr,
604 unsigned int qcu);
605 int (*proc_txdesc)(struct ath_hw *ah, void *ds,
606 struct ath_tx_status *ts);
607 void (*set11n_txdesc)(struct ath_hw *ah, void *ds,
608 u32 pktLen, enum ath9k_pkt_type type,
609 u32 txPower, u32 keyIx,
610 enum ath9k_key_type keyType,
611 u32 flags);
612 void (*set11n_ratescenario)(struct ath_hw *ah, void *ds,
613 void *lastds,
614 u32 durUpdateEn, u32 rtsctsRate,
615 u32 rtsctsDuration,
616 struct ath9k_11n_rate_series series[],
617 u32 nseries, u32 flags);
618 void (*set11n_aggr_first)(struct ath_hw *ah, void *ds,
619 u32 aggrLen);
620 void (*set11n_aggr_middle)(struct ath_hw *ah, void *ds,
621 u32 numDelims);
622 void (*set11n_aggr_last)(struct ath_hw *ah, void *ds);
623 void (*clr11n_aggr)(struct ath_hw *ah, void *ds);
624 void (*set11n_burstduration)(struct ath_hw *ah, void *ds,
625 u32 burstDuration);
626 void (*set11n_virtualmorefrag)(struct ath_hw *ah, void *ds,
627 u32 vmf);
628
629 void (*ani_proc_mib_event)(struct ath_hw *ah);
630 void (*ani_monitor)(struct ath_hw *ah, struct ath9k_channel *chan);
631 };
632
633 struct ath_hw {
634 struct ieee80211_hw *hw;
635 struct ath_common common;
636 struct ath9k_hw_version hw_version;
637 struct ath9k_ops_config config;
638 struct ath9k_hw_capabilities caps;
639 struct ath9k_channel channels[38];
640 struct ath9k_channel *curchan;
641
642 union {
643 struct ar5416_eeprom_def def;
644 struct ar5416_eeprom_4k map4k;
645 struct ar9287_eeprom map9287;
646 struct ar9300_eeprom ar9300_eep;
647 } eeprom;
648 const struct eeprom_ops *eep_ops;
649
650 bool sw_mgmt_crypto;
651 bool is_pciexpress;
652 bool need_an_top2_fixup;
653 u16 tx_trig_level;
654 s16 nf_2g_max;
655 s16 nf_2g_min;
656 s16 nf_5g_max;
657 s16 nf_5g_min;
658 u16 rfsilent;
659 u32 rfkill_gpio;
660 u32 rfkill_polarity;
661 u32 ah_flags;
662
663 bool htc_reset_init;
664
665 enum nl80211_iftype opmode;
666 enum ath9k_power_mode power_mode;
667
668 struct ath9k_nfcal_hist nfCalHist[NUM_NF_READINGS];
669 struct ath9k_pacal_info pacal_info;
670 struct ar5416Stats stats;
671 struct ath9k_tx_queue_info txq[ATH9K_NUM_TX_QUEUES];
672
673 int16_t curchan_rad_index;
674 enum ath9k_int imask;
675 u32 imrs2_reg;
676 u32 txok_interrupt_mask;
677 u32 txerr_interrupt_mask;
678 u32 txdesc_interrupt_mask;
679 u32 txeol_interrupt_mask;
680 u32 txurn_interrupt_mask;
681 bool chip_fullsleep;
682 u32 atim_window;
683
684 /* Calibration */
685 enum ath9k_cal_types supp_cals;
686 struct ath9k_cal_list iq_caldata;
687 struct ath9k_cal_list adcgain_caldata;
688 struct ath9k_cal_list adcdc_calinitdata;
689 struct ath9k_cal_list adcdc_caldata;
690 struct ath9k_cal_list tempCompCalData;
691 struct ath9k_cal_list *cal_list;
692 struct ath9k_cal_list *cal_list_last;
693 struct ath9k_cal_list *cal_list_curr;
694 #define totalPowerMeasI meas0.unsign
695 #define totalPowerMeasQ meas1.unsign
696 #define totalIqCorrMeas meas2.sign
697 #define totalAdcIOddPhase meas0.unsign
698 #define totalAdcIEvenPhase meas1.unsign
699 #define totalAdcQOddPhase meas2.unsign
700 #define totalAdcQEvenPhase meas3.unsign
701 #define totalAdcDcOffsetIOddPhase meas0.sign
702 #define totalAdcDcOffsetIEvenPhase meas1.sign
703 #define totalAdcDcOffsetQOddPhase meas2.sign
704 #define totalAdcDcOffsetQEvenPhase meas3.sign
705 union {
706 u32 unsign[AR5416_MAX_CHAINS];
707 int32_t sign[AR5416_MAX_CHAINS];
708 } meas0;
709 union {
710 u32 unsign[AR5416_MAX_CHAINS];
711 int32_t sign[AR5416_MAX_CHAINS];
712 } meas1;
713 union {
714 u32 unsign[AR5416_MAX_CHAINS];
715 int32_t sign[AR5416_MAX_CHAINS];
716 } meas2;
717 union {
718 u32 unsign[AR5416_MAX_CHAINS];
719 int32_t sign[AR5416_MAX_CHAINS];
720 } meas3;
721 u16 cal_samples;
722
723 u32 sta_id1_defaults;
724 u32 misc_mode;
725 enum {
726 AUTO_32KHZ,
727 USE_32KHZ,
728 DONT_USE_32KHZ,
729 } enable_32kHz_clock;
730
731 /* Private to hardware code */
732 struct ath_hw_private_ops private_ops;
733 /* Accessed by the lower level driver */
734 struct ath_hw_ops ops;
735
736 /* Used to program the radio on non single-chip devices */
737 u32 *analogBank0Data;
738 u32 *analogBank1Data;
739 u32 *analogBank2Data;
740 u32 *analogBank3Data;
741 u32 *analogBank6Data;
742 u32 *analogBank6TPCData;
743 u32 *analogBank7Data;
744 u32 *addac5416_21;
745 u32 *bank6Temp;
746
747 u8 txpower_limit;
748 int16_t txpower_indexoffset;
749 int coverage_class;
750 u32 beacon_interval;
751 u32 slottime;
752 u32 globaltxtimeout;
753
754 /* ANI */
755 u32 proc_phyerr;
756 u32 aniperiod;
757 struct ar5416AniState *curani;
758 struct ar5416AniState ani[255];
759 int totalSizeDesired[5];
760 int coarse_high[5];
761 int coarse_low[5];
762 int firpwr[5];
763 enum ath9k_ani_cmd ani_function;
764
765 /* Bluetooth coexistance */
766 struct ath_btcoex_hw btcoex_hw;
767
768 u32 intr_txqs;
769 u8 txchainmask;
770 u8 rxchainmask;
771
772 u32 originalGain[22];
773 int initPDADC;
774 int PDADCdelta;
775 u8 led_pin;
776
777 struct ar5416IniArray iniModes;
778 struct ar5416IniArray iniCommon;
779 struct ar5416IniArray iniBank0;
780 struct ar5416IniArray iniBB_RfGain;
781 struct ar5416IniArray iniBank1;
782 struct ar5416IniArray iniBank2;
783 struct ar5416IniArray iniBank3;
784 struct ar5416IniArray iniBank6;
785 struct ar5416IniArray iniBank6TPC;
786 struct ar5416IniArray iniBank7;
787 struct ar5416IniArray iniAddac;
788 struct ar5416IniArray iniPcieSerdes;
789 struct ar5416IniArray iniPcieSerdesLowPower;
790 struct ar5416IniArray iniModesAdditional;
791 struct ar5416IniArray iniModesRxGain;
792 struct ar5416IniArray iniModesTxGain;
793 struct ar5416IniArray iniModes_9271_1_0_only;
794 struct ar5416IniArray iniCckfirNormal;
795 struct ar5416IniArray iniCckfirJapan2484;
796 struct ar5416IniArray iniCommon_normal_cck_fir_coeff_9271;
797 struct ar5416IniArray iniCommon_japan_2484_cck_fir_coeff_9271;
798 struct ar5416IniArray iniModes_9271_ANI_reg;
799 struct ar5416IniArray iniModes_high_power_tx_gain_9271;
800 struct ar5416IniArray iniModes_normal_power_tx_gain_9271;
801
802 struct ar5416IniArray iniMac[ATH_INI_NUM_SPLIT];
803 struct ar5416IniArray iniBB[ATH_INI_NUM_SPLIT];
804 struct ar5416IniArray iniRadio[ATH_INI_NUM_SPLIT];
805 struct ar5416IniArray iniSOC[ATH_INI_NUM_SPLIT];
806
807 u32 intr_gen_timer_trigger;
808 u32 intr_gen_timer_thresh;
809 struct ath_gen_timer_table hw_gen_timers;
810
811 struct ar9003_txs *ts_ring;
812 void *ts_start;
813 u32 ts_paddr_start;
814 u32 ts_paddr_end;
815 u16 ts_tail;
816 u8 ts_size;
817
818 u32 bb_watchdog_last_status;
819 u32 bb_watchdog_timeout_ms; /* in ms, 0 to disable */
820
821 u32 paprd_gain_table_entries[PAPRD_GAIN_TABLE_ENTRIES];
822 u8 paprd_gain_table_index[PAPRD_GAIN_TABLE_ENTRIES];
823 /*
824 * Store the permanent value of Reg 0x4004in WARegVal
825 * so we dont have to R/M/W. We should not be reading
826 * this register when in sleep states.
827 */
828 u32 WARegVal;
829 };
830
831 static inline struct ath_common *ath9k_hw_common(struct ath_hw *ah)
832 {
833 return &ah->common;
834 }
835
836 static inline struct ath_regulatory *ath9k_hw_regulatory(struct ath_hw *ah)
837 {
838 return &(ath9k_hw_common(ah)->regulatory);
839 }
840
841 static inline struct ath_hw_private_ops *ath9k_hw_private_ops(struct ath_hw *ah)
842 {
843 return &ah->private_ops;
844 }
845
846 static inline struct ath_hw_ops *ath9k_hw_ops(struct ath_hw *ah)
847 {
848 return &ah->ops;
849 }
850
851 /* Initialization, Detach, Reset */
852 const char *ath9k_hw_probe(u16 vendorid, u16 devid);
853 void ath9k_hw_deinit(struct ath_hw *ah);
854 int ath9k_hw_init(struct ath_hw *ah);
855 int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
856 bool bChannelChange);
857 int ath9k_hw_fill_cap_info(struct ath_hw *ah);
858 u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan);
859
860 /* Key Cache Management */
861 bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry);
862 bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac);
863 bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
864 const struct ath9k_keyval *k,
865 const u8 *mac);
866 bool ath9k_hw_keyisvalid(struct ath_hw *ah, u16 entry);
867
868 /* GPIO / RFKILL / Antennae */
869 void ath9k_hw_cfg_gpio_input(struct ath_hw *ah, u32 gpio);
870 u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio);
871 void ath9k_hw_cfg_output(struct ath_hw *ah, u32 gpio,
872 u32 ah_signal_type);
873 void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val);
874 u32 ath9k_hw_getdefantenna(struct ath_hw *ah);
875 void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna);
876
877 /* General Operation */
878 bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout);
879 u32 ath9k_hw_reverse_bits(u32 val, u32 n);
880 bool ath9k_get_channel_edges(struct ath_hw *ah, u16 flags, u16 *low, u16 *high);
881 u16 ath9k_hw_computetxtime(struct ath_hw *ah,
882 u8 phy, int kbps,
883 u32 frameLen, u16 rateix, bool shortPreamble);
884 void ath9k_hw_get_channel_centers(struct ath_hw *ah,
885 struct ath9k_channel *chan,
886 struct chan_centers *centers);
887 u32 ath9k_hw_getrxfilter(struct ath_hw *ah);
888 void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits);
889 bool ath9k_hw_phy_disable(struct ath_hw *ah);
890 bool ath9k_hw_disable(struct ath_hw *ah);
891 void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit);
892 void ath9k_hw_setopmode(struct ath_hw *ah);
893 void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1);
894 void ath9k_hw_setbssidmask(struct ath_hw *ah);
895 void ath9k_hw_write_associd(struct ath_hw *ah);
896 u64 ath9k_hw_gettsf64(struct ath_hw *ah);
897 void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64);
898 void ath9k_hw_reset_tsf(struct ath_hw *ah);
899 void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting);
900 void ath9k_hw_init_global_settings(struct ath_hw *ah);
901 void ath9k_hw_set11nmac2040(struct ath_hw *ah);
902 void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period);
903 void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
904 const struct ath9k_beacon_state *bs);
905 bool ath9k_hw_check_alive(struct ath_hw *ah);
906
907 bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode);
908
909 /* Generic hw timer primitives */
910 struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
911 void (*trigger)(void *),
912 void (*overflow)(void *),
913 void *arg,
914 u8 timer_index);
915 void ath9k_hw_gen_timer_start(struct ath_hw *ah,
916 struct ath_gen_timer *timer,
917 u32 timer_next,
918 u32 timer_period);
919 void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer);
920
921 void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer);
922 void ath_gen_timer_isr(struct ath_hw *hw);
923 u32 ath9k_hw_gettsf32(struct ath_hw *ah);
924
925 void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len);
926
927 /* HTC */
928 void ath9k_hw_htc_resetinit(struct ath_hw *ah);
929
930 /* PHY */
931 void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
932 u32 *coef_mantissa, u32 *coef_exponent);
933
934 /*
935 * Code Specific to AR5008, AR9001 or AR9002,
936 * we stuff these here to avoid callbacks for AR9003.
937 */
938 void ar9002_hw_cck_chan14_spread(struct ath_hw *ah);
939 int ar9002_hw_rf_claim(struct ath_hw *ah);
940 void ar9002_hw_enable_async_fifo(struct ath_hw *ah);
941 void ar9002_hw_update_async_fifo(struct ath_hw *ah);
942 void ar9002_hw_enable_wep_aggregation(struct ath_hw *ah);
943
944 /*
945 * Code specific to AR9003, we stuff these here to avoid callbacks
946 * for older families
947 */
948 void ar9003_hw_set_nf_limits(struct ath_hw *ah);
949 void ar9003_hw_bb_watchdog_config(struct ath_hw *ah);
950 void ar9003_hw_bb_watchdog_read(struct ath_hw *ah);
951 void ar9003_hw_bb_watchdog_dbg_info(struct ath_hw *ah);
952 void ar9003_paprd_enable(struct ath_hw *ah, bool val);
953 void ar9003_paprd_populate_single_table(struct ath_hw *ah,
954 struct ath9k_channel *chan, int chain);
955 int ar9003_paprd_create_curve(struct ath_hw *ah, struct ath9k_channel *chan,
956 int chain);
957 int ar9003_paprd_setup_gain_table(struct ath_hw *ah, int chain);
958 int ar9003_paprd_init_table(struct ath_hw *ah);
959 bool ar9003_paprd_is_done(struct ath_hw *ah);
960 void ar9003_hw_set_paprd_txdesc(struct ath_hw *ah, void *ds, u8 chains);
961
962 /* Hardware family op attach helpers */
963 void ar5008_hw_attach_phy_ops(struct ath_hw *ah);
964 void ar9002_hw_attach_phy_ops(struct ath_hw *ah);
965 void ar9003_hw_attach_phy_ops(struct ath_hw *ah);
966
967 void ar9002_hw_attach_calib_ops(struct ath_hw *ah);
968 void ar9003_hw_attach_calib_ops(struct ath_hw *ah);
969
970 void ar9002_hw_attach_ops(struct ath_hw *ah);
971 void ar9003_hw_attach_ops(struct ath_hw *ah);
972
973 /*
974 * ANI work can be shared between all families but a next
975 * generation implementation of ANI will be used only for AR9003 only
976 * for now as the other families still need to be tested with the same
977 * next generation ANI. Feel free to start testing it though for the
978 * older families (AR5008, AR9001, AR9002) by using modparam_force_new_ani.
979 */
980 extern int modparam_force_new_ani;
981 void ath9k_hw_attach_ani_ops_old(struct ath_hw *ah);
982 void ath9k_hw_attach_ani_ops_new(struct ath_hw *ah);
983
984 #define ATH_PCIE_CAP_LINK_CTRL 0x70
985 #define ATH_PCIE_CAP_LINK_L0S 1
986 #define ATH_PCIE_CAP_LINK_L1 2
987
988 #define ATH9K_CLOCK_RATE_CCK 22
989 #define ATH9K_CLOCK_RATE_5GHZ_OFDM 40
990 #define ATH9K_CLOCK_RATE_2GHZ_OFDM 44
991 #define ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM 44
992
993 #endif
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