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KVM: VMX: EPT misconfiguration handler
[linux-2.6/btrfs-unstable.git] / arch / x86 / kvm / vmx.c
blob94c07ada103e96f6ee3a9e43cbe8c3b87d00118a
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
8 *
9 * Authors:
10 * Avi Kivity <avi@qumranet.com>
11 * Yaniv Kamay <yaniv@qumranet.com>
12 *
13 * This work is licensed under the terms of the GNU GPL, version 2. See
14 * the COPYING file in the top-level directory.
15 *
16 */
17
18 #include "irq.h"
19 #include "mmu.h"
20
21 #include <linux/kvm_host.h>
22 #include <linux/module.h>
23 #include <linux/kernel.h>
24 #include <linux/mm.h>
25 #include <linux/highmem.h>
26 #include <linux/sched.h>
27 #include <linux/moduleparam.h>
28 #include "kvm_cache_regs.h"
29 #include "x86.h"
30
31 #include <asm/io.h>
32 #include <asm/desc.h>
33 #include <asm/vmx.h>
34 #include <asm/virtext.h>
35 #include <asm/mce.h>
36
37 #define __ex(x) __kvm_handle_fault_on_reboot(x)
38
39 MODULE_AUTHOR("Qumranet");
40 MODULE_LICENSE("GPL");
41
42 static int __read_mostly bypass_guest_pf = 1;
43 module_param(bypass_guest_pf, bool, S_IRUGO);
44
45 static int __read_mostly enable_vpid = 1;
46 module_param_named(vpid, enable_vpid, bool, 0444);
47
48 static int __read_mostly flexpriority_enabled = 1;
49 module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
50
51 static int __read_mostly enable_ept = 1;
52 module_param_named(ept, enable_ept, bool, S_IRUGO);
53
54 static int __read_mostly enable_unrestricted_guest = 1;
55 module_param_named(unrestricted_guest,
56 enable_unrestricted_guest, bool, S_IRUGO);
57
58 static int __read_mostly emulate_invalid_guest_state = 0;
59 module_param(emulate_invalid_guest_state, bool, S_IRUGO);
60
61 struct vmcs {
62 u32 revision_id;
63 u32 abort;
64 char data[0];
65 };
66
67 struct vcpu_vmx {
68 struct kvm_vcpu vcpu;
69 struct list_head local_vcpus_link;
70 unsigned long host_rsp;
71 int launched;
72 u8 fail;
73 u32 idt_vectoring_info;
74 struct kvm_msr_entry *guest_msrs;
75 struct kvm_msr_entry *host_msrs;
76 int nmsrs;
77 int save_nmsrs;
78 int msr_offset_efer;
79 #ifdef CONFIG_X86_64
80 int msr_offset_kernel_gs_base;
81 #endif
82 struct vmcs *vmcs;
83 struct {
84 int loaded;
85 u16 fs_sel, gs_sel, ldt_sel;
86 int gs_ldt_reload_needed;
87 int fs_reload_needed;
88 int guest_efer_loaded;
89 } host_state;
90 struct {
91 int vm86_active;
92 u8 save_iopl;
93 struct kvm_save_segment {
94 u16 selector;
95 unsigned long base;
96 u32 limit;
97 u32 ar;
98 } tr, es, ds, fs, gs;
99 struct {
100 bool pending;
101 u8 vector;
102 unsigned rip;
103 } irq;
104 } rmode;
105 int vpid;
106 bool emulation_required;
107 enum emulation_result invalid_state_emulation_result;
108
109 /* Support for vnmi-less CPUs */
110 int soft_vnmi_blocked;
111 ktime_t entry_time;
112 s64 vnmi_blocked_time;
113 u32 exit_reason;
114 };
115
116 static inline struct vcpu_vmx *to_vmx(struct kvm_vcpu *vcpu)
117 {
118 return container_of(vcpu, struct vcpu_vmx, vcpu);
119 }
120
121 static int init_rmode(struct kvm *kvm);
122 static u64 construct_eptp(unsigned long root_hpa);
123
124 static DEFINE_PER_CPU(struct vmcs *, vmxarea);
125 static DEFINE_PER_CPU(struct vmcs *, current_vmcs);
126 static DEFINE_PER_CPU(struct list_head, vcpus_on_cpu);
127
128 static unsigned long *vmx_io_bitmap_a;
129 static unsigned long *vmx_io_bitmap_b;
130 static unsigned long *vmx_msr_bitmap_legacy;
131 static unsigned long *vmx_msr_bitmap_longmode;
132
133 static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
134 static DEFINE_SPINLOCK(vmx_vpid_lock);
135
136 static struct vmcs_config {
137 int size;
138 int order;
139 u32 revision_id;
140 u32 pin_based_exec_ctrl;
141 u32 cpu_based_exec_ctrl;
142 u32 cpu_based_2nd_exec_ctrl;
143 u32 vmexit_ctrl;
144 u32 vmentry_ctrl;
145 } vmcs_config;
146
147 static struct vmx_capability {
148 u32 ept;
149 u32 vpid;
150 } vmx_capability;
151
152 #define VMX_SEGMENT_FIELD(seg) \
153 [VCPU_SREG_##seg] = { \
154 .selector = GUEST_##seg##_SELECTOR, \
155 .base = GUEST_##seg##_BASE, \
156 .limit = GUEST_##seg##_LIMIT, \
157 .ar_bytes = GUEST_##seg##_AR_BYTES, \
158 }
159
160 static struct kvm_vmx_segment_field {
161 unsigned selector;
162 unsigned base;
163 unsigned limit;
164 unsigned ar_bytes;
165 } kvm_vmx_segment_fields[] = {
166 VMX_SEGMENT_FIELD(CS),
167 VMX_SEGMENT_FIELD(DS),
168 VMX_SEGMENT_FIELD(ES),
169 VMX_SEGMENT_FIELD(FS),
170 VMX_SEGMENT_FIELD(GS),
171 VMX_SEGMENT_FIELD(SS),
172 VMX_SEGMENT_FIELD(TR),
173 VMX_SEGMENT_FIELD(LDTR),
174 };
175
176 static void ept_save_pdptrs(struct kvm_vcpu *vcpu);
177
178 /*
179 * Keep MSR_K6_STAR at the end, as setup_msrs() will try to optimize it
180 * away by decrementing the array size.
181 */
182 static const u32 vmx_msr_index[] = {
183 #ifdef CONFIG_X86_64
184 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR, MSR_KERNEL_GS_BASE,
185 #endif
186 MSR_EFER, MSR_K6_STAR,
187 };
188 #define NR_VMX_MSR ARRAY_SIZE(vmx_msr_index)
189
190 static void load_msrs(struct kvm_msr_entry *e, int n)
191 {
192 int i;
193
194 for (i = 0; i < n; ++i)
195 wrmsrl(e[i].index, e[i].data);
196 }
197
198 static void save_msrs(struct kvm_msr_entry *e, int n)
199 {
200 int i;
201
202 for (i = 0; i < n; ++i)
203 rdmsrl(e[i].index, e[i].data);
204 }
205
206 static inline int is_page_fault(u32 intr_info)
207 {
208 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
209 INTR_INFO_VALID_MASK)) ==
210 (INTR_TYPE_HARD_EXCEPTION | PF_VECTOR | INTR_INFO_VALID_MASK);
211 }
212
213 static inline int is_no_device(u32 intr_info)
214 {
215 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
216 INTR_INFO_VALID_MASK)) ==
217 (INTR_TYPE_HARD_EXCEPTION | NM_VECTOR | INTR_INFO_VALID_MASK);
218 }
219
220 static inline int is_invalid_opcode(u32 intr_info)
221 {
222 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
223 INTR_INFO_VALID_MASK)) ==
224 (INTR_TYPE_HARD_EXCEPTION | UD_VECTOR | INTR_INFO_VALID_MASK);
225 }
226
227 static inline int is_external_interrupt(u32 intr_info)
228 {
229 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VALID_MASK))
230 == (INTR_TYPE_EXT_INTR | INTR_INFO_VALID_MASK);
231 }
232
233 static inline int is_machine_check(u32 intr_info)
234 {
235 return (intr_info & (INTR_INFO_INTR_TYPE_MASK | INTR_INFO_VECTOR_MASK |
236 INTR_INFO_VALID_MASK)) ==
237 (INTR_TYPE_HARD_EXCEPTION | MC_VECTOR | INTR_INFO_VALID_MASK);
238 }
239
240 static inline int cpu_has_vmx_msr_bitmap(void)
241 {
242 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_USE_MSR_BITMAPS;
243 }
244
245 static inline int cpu_has_vmx_tpr_shadow(void)
246 {
247 return vmcs_config.cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW;
248 }
249
250 static inline int vm_need_tpr_shadow(struct kvm *kvm)
251 {
252 return (cpu_has_vmx_tpr_shadow()) && (irqchip_in_kernel(kvm));
253 }
254
255 static inline int cpu_has_secondary_exec_ctrls(void)
256 {
257 return vmcs_config.cpu_based_exec_ctrl &
258 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
259 }
260
261 static inline bool cpu_has_vmx_virtualize_apic_accesses(void)
262 {
263 return vmcs_config.cpu_based_2nd_exec_ctrl &
264 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
265 }
266
267 static inline bool cpu_has_vmx_flexpriority(void)
268 {
269 return cpu_has_vmx_tpr_shadow() &&
270 cpu_has_vmx_virtualize_apic_accesses();
271 }
272
273 static inline bool cpu_has_vmx_ept_execute_only(void)
274 {
275 return !!(vmx_capability.ept & VMX_EPT_EXECUTE_ONLY_BIT);
276 }
277
278 static inline bool cpu_has_vmx_eptp_uncacheable(void)
279 {
280 return !!(vmx_capability.ept & VMX_EPTP_UC_BIT);
281 }
282
283 static inline bool cpu_has_vmx_eptp_writeback(void)
284 {
285 return !!(vmx_capability.ept & VMX_EPTP_WB_BIT);
286 }
287
288 static inline bool cpu_has_vmx_ept_2m_page(void)
289 {
290 return !!(vmx_capability.ept & VMX_EPT_2MB_PAGE_BIT);
291 }
292
293 static inline int cpu_has_vmx_invept_individual_addr(void)
294 {
295 return !!(vmx_capability.ept & VMX_EPT_EXTENT_INDIVIDUAL_BIT);
296 }
297
298 static inline int cpu_has_vmx_invept_context(void)
299 {
300 return !!(vmx_capability.ept & VMX_EPT_EXTENT_CONTEXT_BIT);
301 }
302
303 static inline int cpu_has_vmx_invept_global(void)
304 {
305 return !!(vmx_capability.ept & VMX_EPT_EXTENT_GLOBAL_BIT);
306 }
307
308 static inline int cpu_has_vmx_ept(void)
309 {
310 return vmcs_config.cpu_based_2nd_exec_ctrl &
311 SECONDARY_EXEC_ENABLE_EPT;
312 }
313
314 static inline int cpu_has_vmx_unrestricted_guest(void)
315 {
316 return vmcs_config.cpu_based_2nd_exec_ctrl &
317 SECONDARY_EXEC_UNRESTRICTED_GUEST;
318 }
319
320 static inline int vm_need_virtualize_apic_accesses(struct kvm *kvm)
321 {
322 return flexpriority_enabled &&
323 (cpu_has_vmx_virtualize_apic_accesses()) &&
324 (irqchip_in_kernel(kvm));
325 }
326
327 static inline int cpu_has_vmx_vpid(void)
328 {
329 return vmcs_config.cpu_based_2nd_exec_ctrl &
330 SECONDARY_EXEC_ENABLE_VPID;
331 }
332
333 static inline int cpu_has_virtual_nmis(void)
334 {
335 return vmcs_config.pin_based_exec_ctrl & PIN_BASED_VIRTUAL_NMIS;
336 }
337
338 static inline bool report_flexpriority(void)
339 {
340 return flexpriority_enabled;
341 }
342
343 static int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
344 {
345 int i;
346
347 for (i = 0; i < vmx->nmsrs; ++i)
348 if (vmx->guest_msrs[i].index == msr)
349 return i;
350 return -1;
351 }
352
353 static inline void __invvpid(int ext, u16 vpid, gva_t gva)
354 {
355 struct {
356 u64 vpid : 16;
357 u64 rsvd : 48;
358 u64 gva;
359 } operand = { vpid, 0, gva };
360
361 asm volatile (__ex(ASM_VMX_INVVPID)
362 /* CF==1 or ZF==1 --> rc = -1 */
363 "; ja 1f ; ud2 ; 1:"
364 : : "a"(&operand), "c"(ext) : "cc", "memory");
365 }
366
367 static inline void __invept(int ext, u64 eptp, gpa_t gpa)
368 {
369 struct {
370 u64 eptp, gpa;
371 } operand = {eptp, gpa};
372
373 asm volatile (__ex(ASM_VMX_INVEPT)
374 /* CF==1 or ZF==1 --> rc = -1 */
375 "; ja 1f ; ud2 ; 1:\n"
376 : : "a" (&operand), "c" (ext) : "cc", "memory");
377 }
378
379 static struct kvm_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
380 {
381 int i;
382
383 i = __find_msr_index(vmx, msr);
384 if (i >= 0)
385 return &vmx->guest_msrs[i];
386 return NULL;
387 }
388
389 static void vmcs_clear(struct vmcs *vmcs)
390 {
391 u64 phys_addr = __pa(vmcs);
392 u8 error;
393
394 asm volatile (__ex(ASM_VMX_VMCLEAR_RAX) "; setna %0"
395 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
396 : "cc", "memory");
397 if (error)
398 printk(KERN_ERR "kvm: vmclear fail: %p/%llx\n",
399 vmcs, phys_addr);
400 }
401
402 static void __vcpu_clear(void *arg)
403 {
404 struct vcpu_vmx *vmx = arg;
405 int cpu = raw_smp_processor_id();
406
407 if (vmx->vcpu.cpu == cpu)
408 vmcs_clear(vmx->vmcs);
409 if (per_cpu(current_vmcs, cpu) == vmx->vmcs)
410 per_cpu(current_vmcs, cpu) = NULL;
411 rdtscll(vmx->vcpu.arch.host_tsc);
412 list_del(&vmx->local_vcpus_link);
413 vmx->vcpu.cpu = -1;
414 vmx->launched = 0;
415 }
416
417 static void vcpu_clear(struct vcpu_vmx *vmx)
418 {
419 if (vmx->vcpu.cpu == -1)
420 return;
421 smp_call_function_single(vmx->vcpu.cpu, __vcpu_clear, vmx, 1);
422 }
423
424 static inline void vpid_sync_vcpu_all(struct vcpu_vmx *vmx)
425 {
426 if (vmx->vpid == 0)
427 return;
428
429 __invvpid(VMX_VPID_EXTENT_SINGLE_CONTEXT, vmx->vpid, 0);
430 }
431
432 static inline void ept_sync_global(void)
433 {
434 if (cpu_has_vmx_invept_global())
435 __invept(VMX_EPT_EXTENT_GLOBAL, 0, 0);
436 }
437
438 static inline void ept_sync_context(u64 eptp)
439 {
440 if (enable_ept) {
441 if (cpu_has_vmx_invept_context())
442 __invept(VMX_EPT_EXTENT_CONTEXT, eptp, 0);
443 else
444 ept_sync_global();
445 }
446 }
447
448 static inline void ept_sync_individual_addr(u64 eptp, gpa_t gpa)
449 {
450 if (enable_ept) {
451 if (cpu_has_vmx_invept_individual_addr())
452 __invept(VMX_EPT_EXTENT_INDIVIDUAL_ADDR,
453 eptp, gpa);
454 else
455 ept_sync_context(eptp);
456 }
457 }
458
459 static unsigned long vmcs_readl(unsigned long field)
460 {
461 unsigned long value;
462
463 asm volatile (__ex(ASM_VMX_VMREAD_RDX_RAX)
464 : "=a"(value) : "d"(field) : "cc");
465 return value;
466 }
467
468 static u16 vmcs_read16(unsigned long field)
469 {
470 return vmcs_readl(field);
471 }
472
473 static u32 vmcs_read32(unsigned long field)
474 {
475 return vmcs_readl(field);
476 }
477
478 static u64 vmcs_read64(unsigned long field)
479 {
480 #ifdef CONFIG_X86_64
481 return vmcs_readl(field);
482 #else
483 return vmcs_readl(field) | ((u64)vmcs_readl(field+1) << 32);
484 #endif
485 }
486
487 static noinline void vmwrite_error(unsigned long field, unsigned long value)
488 {
489 printk(KERN_ERR "vmwrite error: reg %lx value %lx (err %d)\n",
490 field, value, vmcs_read32(VM_INSTRUCTION_ERROR));
491 dump_stack();
492 }
493
494 static void vmcs_writel(unsigned long field, unsigned long value)
495 {
496 u8 error;
497
498 asm volatile (__ex(ASM_VMX_VMWRITE_RAX_RDX) "; setna %0"
499 : "=q"(error) : "a"(value), "d"(field) : "cc");
500 if (unlikely(error))
501 vmwrite_error(field, value);
502 }
503
504 static void vmcs_write16(unsigned long field, u16 value)
505 {
506 vmcs_writel(field, value);
507 }
508
509 static void vmcs_write32(unsigned long field, u32 value)
510 {
511 vmcs_writel(field, value);
512 }
513
514 static void vmcs_write64(unsigned long field, u64 value)
515 {
516 vmcs_writel(field, value);
517 #ifndef CONFIG_X86_64
518 asm volatile ("");
519 vmcs_writel(field+1, value >> 32);
520 #endif
521 }
522
523 static void vmcs_clear_bits(unsigned long field, u32 mask)
524 {
525 vmcs_writel(field, vmcs_readl(field) & ~mask);
526 }
527
528 static void vmcs_set_bits(unsigned long field, u32 mask)
529 {
530 vmcs_writel(field, vmcs_readl(field) | mask);
531 }
532
533 static void update_exception_bitmap(struct kvm_vcpu *vcpu)
534 {
535 u32 eb;
536
537 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR);
538 if (!vcpu->fpu_active)
539 eb |= 1u << NM_VECTOR;
540 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
541 if (vcpu->guest_debug &
542 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
543 eb |= 1u << DB_VECTOR;
544 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
545 eb |= 1u << BP_VECTOR;
546 }
547 if (to_vmx(vcpu)->rmode.vm86_active)
548 eb = ~0;
549 if (enable_ept)
550 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
551 vmcs_write32(EXCEPTION_BITMAP, eb);
552 }
553
554 static void reload_tss(void)
555 {
556 /*
557 * VT restores TR but not its size. Useless.
558 */
559 struct descriptor_table gdt;
560 struct desc_struct *descs;
561
562 kvm_get_gdt(&gdt);
563 descs = (void *)gdt.base;
564 descs[GDT_ENTRY_TSS].type = 9; /* available TSS */
565 load_TR_desc();
566 }
567
568 static void load_transition_efer(struct vcpu_vmx *vmx)
569 {
570 int efer_offset = vmx->msr_offset_efer;
571 u64 host_efer = vmx->host_msrs[efer_offset].data;
572 u64 guest_efer = vmx->guest_msrs[efer_offset].data;
573 u64 ignore_bits;
574
575 if (efer_offset < 0)
576 return;
577 /*
578 * NX is emulated; LMA and LME handled by hardware; SCE meaninless
579 * outside long mode
580 */
581 ignore_bits = EFER_NX | EFER_SCE;
582 #ifdef CONFIG_X86_64
583 ignore_bits |= EFER_LMA | EFER_LME;
584 /* SCE is meaningful only in long mode on Intel */
585 if (guest_efer & EFER_LMA)
586 ignore_bits &= ~(u64)EFER_SCE;
587 #endif
588 if ((guest_efer & ~ignore_bits) == (host_efer & ~ignore_bits))
589 return;
590
591 vmx->host_state.guest_efer_loaded = 1;
592 guest_efer &= ~ignore_bits;
593 guest_efer |= host_efer & ignore_bits;
594 wrmsrl(MSR_EFER, guest_efer);
595 vmx->vcpu.stat.efer_reload++;
596 }
597
598 static void reload_host_efer(struct vcpu_vmx *vmx)
599 {
600 if (vmx->host_state.guest_efer_loaded) {
601 vmx->host_state.guest_efer_loaded = 0;
602 load_msrs(vmx->host_msrs + vmx->msr_offset_efer, 1);
603 }
604 }
605
606 static void vmx_save_host_state(struct kvm_vcpu *vcpu)
607 {
608 struct vcpu_vmx *vmx = to_vmx(vcpu);
609
610 if (vmx->host_state.loaded)
611 return;
612
613 vmx->host_state.loaded = 1;
614 /*
615 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
616 * allow segment selectors with cpl > 0 or ti == 1.
617 */
618 vmx->host_state.ldt_sel = kvm_read_ldt();
619 vmx->host_state.gs_ldt_reload_needed = vmx->host_state.ldt_sel;
620 vmx->host_state.fs_sel = kvm_read_fs();
621 if (!(vmx->host_state.fs_sel & 7)) {
622 vmcs_write16(HOST_FS_SELECTOR, vmx->host_state.fs_sel);
623 vmx->host_state.fs_reload_needed = 0;
624 } else {
625 vmcs_write16(HOST_FS_SELECTOR, 0);
626 vmx->host_state.fs_reload_needed = 1;
627 }
628 vmx->host_state.gs_sel = kvm_read_gs();
629 if (!(vmx->host_state.gs_sel & 7))
630 vmcs_write16(HOST_GS_SELECTOR, vmx->host_state.gs_sel);
631 else {
632 vmcs_write16(HOST_GS_SELECTOR, 0);
633 vmx->host_state.gs_ldt_reload_needed = 1;
634 }
635
636 #ifdef CONFIG_X86_64
637 vmcs_writel(HOST_FS_BASE, read_msr(MSR_FS_BASE));
638 vmcs_writel(HOST_GS_BASE, read_msr(MSR_GS_BASE));
639 #else
640 vmcs_writel(HOST_FS_BASE, segment_base(vmx->host_state.fs_sel));
641 vmcs_writel(HOST_GS_BASE, segment_base(vmx->host_state.gs_sel));
642 #endif
643
644 #ifdef CONFIG_X86_64
645 if (is_long_mode(&vmx->vcpu))
646 save_msrs(vmx->host_msrs +
647 vmx->msr_offset_kernel_gs_base, 1);
648
649 #endif
650 load_msrs(vmx->guest_msrs, vmx->save_nmsrs);
651 load_transition_efer(vmx);
652 }
653
654 static void __vmx_load_host_state(struct vcpu_vmx *vmx)
655 {
656 unsigned long flags;
657
658 if (!vmx->host_state.loaded)
659 return;
660
661 ++vmx->vcpu.stat.host_state_reload;
662 vmx->host_state.loaded = 0;
663 if (vmx->host_state.fs_reload_needed)
664 kvm_load_fs(vmx->host_state.fs_sel);
665 if (vmx->host_state.gs_ldt_reload_needed) {
666 kvm_load_ldt(vmx->host_state.ldt_sel);
667 /*
668 * If we have to reload gs, we must take care to
669 * preserve our gs base.
670 */
671 local_irq_save(flags);
672 kvm_load_gs(vmx->host_state.gs_sel);
673 #ifdef CONFIG_X86_64
674 wrmsrl(MSR_GS_BASE, vmcs_readl(HOST_GS_BASE));
675 #endif
676 local_irq_restore(flags);
677 }
678 reload_tss();
679 save_msrs(vmx->guest_msrs, vmx->save_nmsrs);
680 load_msrs(vmx->host_msrs, vmx->save_nmsrs);
681 reload_host_efer(vmx);
682 }
683
684 static void vmx_load_host_state(struct vcpu_vmx *vmx)
685 {
686 preempt_disable();
687 __vmx_load_host_state(vmx);
688 preempt_enable();
689 }
690
691 /*
692 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
693 * vcpu mutex is already taken.
694 */
695 static void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
696 {
697 struct vcpu_vmx *vmx = to_vmx(vcpu);
698 u64 phys_addr = __pa(vmx->vmcs);
699 u64 tsc_this, delta, new_offset;
700
701 if (vcpu->cpu != cpu) {
702 vcpu_clear(vmx);
703 kvm_migrate_timers(vcpu);
704 vpid_sync_vcpu_all(vmx);
705 local_irq_disable();
706 list_add(&vmx->local_vcpus_link,
707 &per_cpu(vcpus_on_cpu, cpu));
708 local_irq_enable();
709 }
710
711 if (per_cpu(current_vmcs, cpu) != vmx->vmcs) {
712 u8 error;
713
714 per_cpu(current_vmcs, cpu) = vmx->vmcs;
715 asm volatile (__ex(ASM_VMX_VMPTRLD_RAX) "; setna %0"
716 : "=g"(error) : "a"(&phys_addr), "m"(phys_addr)
717 : "cc");
718 if (error)
719 printk(KERN_ERR "kvm: vmptrld %p/%llx fail\n",
720 vmx->vmcs, phys_addr);
721 }
722
723 if (vcpu->cpu != cpu) {
724 struct descriptor_table dt;
725 unsigned long sysenter_esp;
726
727 vcpu->cpu = cpu;
728 /*
729 * Linux uses per-cpu TSS and GDT, so set these when switching
730 * processors.
731 */
732 vmcs_writel(HOST_TR_BASE, kvm_read_tr_base()); /* 22.2.4 */
733 kvm_get_gdt(&dt);
734 vmcs_writel(HOST_GDTR_BASE, dt.base); /* 22.2.4 */
735
736 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
737 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
738
739 /*
740 * Make sure the time stamp counter is monotonous.
741 */
742 rdtscll(tsc_this);
743 if (tsc_this < vcpu->arch.host_tsc) {
744 delta = vcpu->arch.host_tsc - tsc_this;
745 new_offset = vmcs_read64(TSC_OFFSET) + delta;
746 vmcs_write64(TSC_OFFSET, new_offset);
747 }
748 }
749 }
750
751 static void vmx_vcpu_put(struct kvm_vcpu *vcpu)
752 {
753 __vmx_load_host_state(to_vmx(vcpu));
754 }
755
756 static void vmx_fpu_activate(struct kvm_vcpu *vcpu)
757 {
758 if (vcpu->fpu_active)
759 return;
760 vcpu->fpu_active = 1;
761 vmcs_clear_bits(GUEST_CR0, X86_CR0_TS);
762 if (vcpu->arch.cr0 & X86_CR0_TS)
763 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
764 update_exception_bitmap(vcpu);
765 }
766
767 static void vmx_fpu_deactivate(struct kvm_vcpu *vcpu)
768 {
769 if (!vcpu->fpu_active)
770 return;
771 vcpu->fpu_active = 0;
772 vmcs_set_bits(GUEST_CR0, X86_CR0_TS);
773 update_exception_bitmap(vcpu);
774 }
775
776 static unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
777 {
778 return vmcs_readl(GUEST_RFLAGS);
779 }
780
781 static void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
782 {
783 if (to_vmx(vcpu)->rmode.vm86_active)
784 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
785 vmcs_writel(GUEST_RFLAGS, rflags);
786 }
787
788 static u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
789 {
790 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
791 int ret = 0;
792
793 if (interruptibility & GUEST_INTR_STATE_STI)
794 ret |= X86_SHADOW_INT_STI;
795 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
796 ret |= X86_SHADOW_INT_MOV_SS;
797
798 return ret & mask;
799 }
800
801 static void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
802 {
803 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
804 u32 interruptibility = interruptibility_old;
805
806 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
807
808 if (mask & X86_SHADOW_INT_MOV_SS)
809 interruptibility |= GUEST_INTR_STATE_MOV_SS;
810 if (mask & X86_SHADOW_INT_STI)
811 interruptibility |= GUEST_INTR_STATE_STI;
812
813 if ((interruptibility != interruptibility_old))
814 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
815 }
816
817 static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
818 {
819 unsigned long rip;
820
821 rip = kvm_rip_read(vcpu);
822 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
823 kvm_rip_write(vcpu, rip);
824
825 /* skipping an emulated instruction also counts */
826 vmx_set_interrupt_shadow(vcpu, 0);
827 }
828
829 static void vmx_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
830 bool has_error_code, u32 error_code)
831 {
832 struct vcpu_vmx *vmx = to_vmx(vcpu);
833 u32 intr_info = nr | INTR_INFO_VALID_MASK;
834
835 if (has_error_code) {
836 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
837 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
838 }
839
840 if (vmx->rmode.vm86_active) {
841 vmx->rmode.irq.pending = true;
842 vmx->rmode.irq.vector = nr;
843 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
844 if (kvm_exception_is_soft(nr))
845 vmx->rmode.irq.rip +=
846 vmx->vcpu.arch.event_exit_inst_len;
847 intr_info |= INTR_TYPE_SOFT_INTR;
848 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
849 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
850 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
851 return;
852 }
853
854 if (kvm_exception_is_soft(nr)) {
855 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
856 vmx->vcpu.arch.event_exit_inst_len);
857 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
858 } else
859 intr_info |= INTR_TYPE_HARD_EXCEPTION;
860
861 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
862 }
863
864 /*
865 * Swap MSR entry in host/guest MSR entry array.
866 */
867 #ifdef CONFIG_X86_64
868 static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
869 {
870 struct kvm_msr_entry tmp;
871
872 tmp = vmx->guest_msrs[to];
873 vmx->guest_msrs[to] = vmx->guest_msrs[from];
874 vmx->guest_msrs[from] = tmp;
875 tmp = vmx->host_msrs[to];
876 vmx->host_msrs[to] = vmx->host_msrs[from];
877 vmx->host_msrs[from] = tmp;
878 }
879 #endif
880
881 /*
882 * Set up the vmcs to automatically save and restore system
883 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
884 * mode, as fiddling with msrs is very expensive.
885 */
886 static void setup_msrs(struct vcpu_vmx *vmx)
887 {
888 int save_nmsrs;
889 unsigned long *msr_bitmap;
890
891 vmx_load_host_state(vmx);
892 save_nmsrs = 0;
893 #ifdef CONFIG_X86_64
894 if (is_long_mode(&vmx->vcpu)) {
895 int index;
896
897 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
898 if (index >= 0)
899 move_msr_up(vmx, index, save_nmsrs++);
900 index = __find_msr_index(vmx, MSR_LSTAR);
901 if (index >= 0)
902 move_msr_up(vmx, index, save_nmsrs++);
903 index = __find_msr_index(vmx, MSR_CSTAR);
904 if (index >= 0)
905 move_msr_up(vmx, index, save_nmsrs++);
906 index = __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
907 if (index >= 0)
908 move_msr_up(vmx, index, save_nmsrs++);
909 /*
910 * MSR_K6_STAR is only needed on long mode guests, and only
911 * if efer.sce is enabled.
912 */
913 index = __find_msr_index(vmx, MSR_K6_STAR);
914 if ((index >= 0) && (vmx->vcpu.arch.shadow_efer & EFER_SCE))
915 move_msr_up(vmx, index, save_nmsrs++);
916 }
917 #endif
918 vmx->save_nmsrs = save_nmsrs;
919
920 #ifdef CONFIG_X86_64
921 vmx->msr_offset_kernel_gs_base =
922 __find_msr_index(vmx, MSR_KERNEL_GS_BASE);
923 #endif
924 vmx->msr_offset_efer = __find_msr_index(vmx, MSR_EFER);
925
926 if (cpu_has_vmx_msr_bitmap()) {
927 if (is_long_mode(&vmx->vcpu))
928 msr_bitmap = vmx_msr_bitmap_longmode;
929 else
930 msr_bitmap = vmx_msr_bitmap_legacy;
931
932 vmcs_write64(MSR_BITMAP, __pa(msr_bitmap));
933 }
934 }
935
936 /*
937 * reads and returns guest's timestamp counter "register"
938 * guest_tsc = host_tsc + tsc_offset -- 21.3
939 */
940 static u64 guest_read_tsc(void)
941 {
942 u64 host_tsc, tsc_offset;
943
944 rdtscll(host_tsc);
945 tsc_offset = vmcs_read64(TSC_OFFSET);
946 return host_tsc + tsc_offset;
947 }
948
949 /*
950 * writes 'guest_tsc' into guest's timestamp counter "register"
951 * guest_tsc = host_tsc + tsc_offset ==> tsc_offset = guest_tsc - host_tsc
952 */
953 static void guest_write_tsc(u64 guest_tsc, u64 host_tsc)
954 {
955 vmcs_write64(TSC_OFFSET, guest_tsc - host_tsc);
956 }
957
958 /*
959 * Reads an msr value (of 'msr_index') into 'pdata'.
960 * Returns 0 on success, non-0 otherwise.
961 * Assumes vcpu_load() was already called.
962 */
963 static int vmx_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
964 {
965 u64 data;
966 struct kvm_msr_entry *msr;
967
968 if (!pdata) {
969 printk(KERN_ERR "BUG: get_msr called with NULL pdata\n");
970 return -EINVAL;
971 }
972
973 switch (msr_index) {
974 #ifdef CONFIG_X86_64
975 case MSR_FS_BASE:
976 data = vmcs_readl(GUEST_FS_BASE);
977 break;
978 case MSR_GS_BASE:
979 data = vmcs_readl(GUEST_GS_BASE);
980 break;
981 case MSR_EFER:
982 return kvm_get_msr_common(vcpu, msr_index, pdata);
983 #endif
984 case MSR_IA32_TSC:
985 data = guest_read_tsc();
986 break;
987 case MSR_IA32_SYSENTER_CS:
988 data = vmcs_read32(GUEST_SYSENTER_CS);
989 break;
990 case MSR_IA32_SYSENTER_EIP:
991 data = vmcs_readl(GUEST_SYSENTER_EIP);
992 break;
993 case MSR_IA32_SYSENTER_ESP:
994 data = vmcs_readl(GUEST_SYSENTER_ESP);
995 break;
996 default:
997 vmx_load_host_state(to_vmx(vcpu));
998 msr = find_msr_entry(to_vmx(vcpu), msr_index);
999 if (msr) {
1000 data = msr->data;
1001 break;
1002 }
1003 return kvm_get_msr_common(vcpu, msr_index, pdata);
1004 }
1005
1006 *pdata = data;
1007 return 0;
1008 }
1009
1010 /*
1011 * Writes msr value into into the appropriate "register".
1012 * Returns 0 on success, non-0 otherwise.
1013 * Assumes vcpu_load() was already called.
1014 */
1015 static int vmx_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
1016 {
1017 struct vcpu_vmx *vmx = to_vmx(vcpu);
1018 struct kvm_msr_entry *msr;
1019 u64 host_tsc;
1020 int ret = 0;
1021
1022 switch (msr_index) {
1023 case MSR_EFER:
1024 vmx_load_host_state(vmx);
1025 ret = kvm_set_msr_common(vcpu, msr_index, data);
1026 break;
1027 #ifdef CONFIG_X86_64
1028 case MSR_FS_BASE:
1029 vmcs_writel(GUEST_FS_BASE, data);
1030 break;
1031 case MSR_GS_BASE:
1032 vmcs_writel(GUEST_GS_BASE, data);
1033 break;
1034 #endif
1035 case MSR_IA32_SYSENTER_CS:
1036 vmcs_write32(GUEST_SYSENTER_CS, data);
1037 break;
1038 case MSR_IA32_SYSENTER_EIP:
1039 vmcs_writel(GUEST_SYSENTER_EIP, data);
1040 break;
1041 case MSR_IA32_SYSENTER_ESP:
1042 vmcs_writel(GUEST_SYSENTER_ESP, data);
1043 break;
1044 case MSR_IA32_TSC:
1045 rdtscll(host_tsc);
1046 guest_write_tsc(data, host_tsc);
1047 break;
1048 case MSR_IA32_CR_PAT:
1049 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
1050 vmcs_write64(GUEST_IA32_PAT, data);
1051 vcpu->arch.pat = data;
1052 break;
1053 }
1054 /* Otherwise falls through to kvm_set_msr_common */
1055 default:
1056 vmx_load_host_state(vmx);
1057 msr = find_msr_entry(vmx, msr_index);
1058 if (msr) {
1059 msr->data = data;
1060 break;
1061 }
1062 ret = kvm_set_msr_common(vcpu, msr_index, data);
1063 }
1064
1065 return ret;
1066 }
1067
1068 static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1069 {
1070 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1071 switch (reg) {
1072 case VCPU_REGS_RSP:
1073 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1074 break;
1075 case VCPU_REGS_RIP:
1076 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1077 break;
1078 case VCPU_EXREG_PDPTR:
1079 if (enable_ept)
1080 ept_save_pdptrs(vcpu);
1081 break;
1082 default:
1083 break;
1084 }
1085 }
1086
1087 static int set_guest_debug(struct kvm_vcpu *vcpu, struct kvm_guest_debug *dbg)
1088 {
1089 int old_debug = vcpu->guest_debug;
1090 unsigned long flags;
1091
1092 vcpu->guest_debug = dbg->control;
1093 if (!(vcpu->guest_debug & KVM_GUESTDBG_ENABLE))
1094 vcpu->guest_debug = 0;
1095
1096 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)
1097 vmcs_writel(GUEST_DR7, dbg->arch.debugreg[7]);
1098 else
1099 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
1100
1101 flags = vmcs_readl(GUEST_RFLAGS);
1102 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
1103 flags |= X86_EFLAGS_TF | X86_EFLAGS_RF;
1104 else if (old_debug & KVM_GUESTDBG_SINGLESTEP)
1105 flags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
1106 vmcs_writel(GUEST_RFLAGS, flags);
1107
1108 update_exception_bitmap(vcpu);
1109
1110 return 0;
1111 }
1112
1113 static __init int cpu_has_kvm_support(void)
1114 {
1115 return cpu_has_vmx();
1116 }
1117
1118 static __init int vmx_disabled_by_bios(void)
1119 {
1120 u64 msr;
1121
1122 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1123 return (msr & (FEATURE_CONTROL_LOCKED |
1124 FEATURE_CONTROL_VMXON_ENABLED))
1125 == FEATURE_CONTROL_LOCKED;
1126 /* locked but not enabled */
1127 }
1128
1129 static void hardware_enable(void *garbage)
1130 {
1131 int cpu = raw_smp_processor_id();
1132 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
1133 u64 old;
1134
1135 INIT_LIST_HEAD(&per_cpu(vcpus_on_cpu, cpu));
1136 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
1137 if ((old & (FEATURE_CONTROL_LOCKED |
1138 FEATURE_CONTROL_VMXON_ENABLED))
1139 != (FEATURE_CONTROL_LOCKED |
1140 FEATURE_CONTROL_VMXON_ENABLED))
1141 /* enable and lock */
1142 wrmsrl(MSR_IA32_FEATURE_CONTROL, old |
1143 FEATURE_CONTROL_LOCKED |
1144 FEATURE_CONTROL_VMXON_ENABLED);
1145 write_cr4(read_cr4() | X86_CR4_VMXE); /* FIXME: not cpu hotplug safe */
1146 asm volatile (ASM_VMX_VMXON_RAX
1147 : : "a"(&phys_addr), "m"(phys_addr)
1148 : "memory", "cc");
1149 }
1150
1151 static void vmclear_local_vcpus(void)
1152 {
1153 int cpu = raw_smp_processor_id();
1154 struct vcpu_vmx *vmx, *n;
1155
1156 list_for_each_entry_safe(vmx, n, &per_cpu(vcpus_on_cpu, cpu),
1157 local_vcpus_link)
1158 __vcpu_clear(vmx);
1159 }
1160
1161
1162 /* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1163 * tricks.
1164 */
1165 static void kvm_cpu_vmxoff(void)
1166 {
1167 asm volatile (__ex(ASM_VMX_VMXOFF) : : : "cc");
1168 write_cr4(read_cr4() & ~X86_CR4_VMXE);
1169 }
1170
1171 static void hardware_disable(void *garbage)
1172 {
1173 vmclear_local_vcpus();
1174 kvm_cpu_vmxoff();
1175 }
1176
1177 static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
1178 u32 msr, u32 *result)
1179 {
1180 u32 vmx_msr_low, vmx_msr_high;
1181 u32 ctl = ctl_min | ctl_opt;
1182
1183 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1184
1185 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1186 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1187
1188 /* Ensure minimum (required) set of control bits are supported. */
1189 if (ctl_min & ~ctl)
1190 return -EIO;
1191
1192 *result = ctl;
1193 return 0;
1194 }
1195
1196 static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf)
1197 {
1198 u32 vmx_msr_low, vmx_msr_high;
1199 u32 min, opt, min2, opt2;
1200 u32 _pin_based_exec_control = 0;
1201 u32 _cpu_based_exec_control = 0;
1202 u32 _cpu_based_2nd_exec_control = 0;
1203 u32 _vmexit_control = 0;
1204 u32 _vmentry_control = 0;
1205
1206 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
1207 opt = PIN_BASED_VIRTUAL_NMIS;
1208 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
1209 &_pin_based_exec_control) < 0)
1210 return -EIO;
1211
1212 min = CPU_BASED_HLT_EXITING |
1213 #ifdef CONFIG_X86_64
1214 CPU_BASED_CR8_LOAD_EXITING |
1215 CPU_BASED_CR8_STORE_EXITING |
1216 #endif
1217 CPU_BASED_CR3_LOAD_EXITING |
1218 CPU_BASED_CR3_STORE_EXITING |
1219 CPU_BASED_USE_IO_BITMAPS |
1220 CPU_BASED_MOV_DR_EXITING |
1221 CPU_BASED_USE_TSC_OFFSETING |
1222 CPU_BASED_INVLPG_EXITING;
1223 opt = CPU_BASED_TPR_SHADOW |
1224 CPU_BASED_USE_MSR_BITMAPS |
1225 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1226 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1227 &_cpu_based_exec_control) < 0)
1228 return -EIO;
1229 #ifdef CONFIG_X86_64
1230 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1231 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1232 ~CPU_BASED_CR8_STORE_EXITING;
1233 #endif
1234 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
1235 min2 = 0;
1236 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
1237 SECONDARY_EXEC_WBINVD_EXITING |
1238 SECONDARY_EXEC_ENABLE_VPID |
1239 SECONDARY_EXEC_ENABLE_EPT |
1240 SECONDARY_EXEC_UNRESTRICTED_GUEST;
1241 if (adjust_vmx_controls(min2, opt2,
1242 MSR_IA32_VMX_PROCBASED_CTLS2,
1243 &_cpu_based_2nd_exec_control) < 0)
1244 return -EIO;
1245 }
1246 #ifndef CONFIG_X86_64
1247 if (!(_cpu_based_2nd_exec_control &
1248 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1249 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1250 #endif
1251 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
1252 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
1253 enabled */
1254 min &= ~(CPU_BASED_CR3_LOAD_EXITING |
1255 CPU_BASED_CR3_STORE_EXITING |
1256 CPU_BASED_INVLPG_EXITING);
1257 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1258 &_cpu_based_exec_control) < 0)
1259 return -EIO;
1260 rdmsr(MSR_IA32_VMX_EPT_VPID_CAP,
1261 vmx_capability.ept, vmx_capability.vpid);
1262 }
1263
1264 min = 0;
1265 #ifdef CONFIG_X86_64
1266 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
1267 #endif
1268 opt = VM_EXIT_SAVE_IA32_PAT | VM_EXIT_LOAD_IA32_PAT;
1269 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
1270 &_vmexit_control) < 0)
1271 return -EIO;
1272
1273 min = 0;
1274 opt = VM_ENTRY_LOAD_IA32_PAT;
1275 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
1276 &_vmentry_control) < 0)
1277 return -EIO;
1278
1279 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1280
1281 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
1282 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
1283 return -EIO;
1284
1285 #ifdef CONFIG_X86_64
1286 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
1287 if (vmx_msr_high & (1u<<16))
1288 return -EIO;
1289 #endif
1290
1291 /* Require Write-Back (WB) memory type for VMCS accesses. */
1292 if (((vmx_msr_high >> 18) & 15) != 6)
1293 return -EIO;
1294
1295 vmcs_conf->size = vmx_msr_high & 0x1fff;
1296 vmcs_conf->order = get_order(vmcs_config.size);
1297 vmcs_conf->revision_id = vmx_msr_low;
1298
1299 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
1300 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
1301 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
1302 vmcs_conf->vmexit_ctrl = _vmexit_control;
1303 vmcs_conf->vmentry_ctrl = _vmentry_control;
1304
1305 return 0;
1306 }
1307
1308 static struct vmcs *alloc_vmcs_cpu(int cpu)
1309 {
1310 int node = cpu_to_node(cpu);
1311 struct page *pages;
1312 struct vmcs *vmcs;
1313
1314 pages = alloc_pages_exact_node(node, GFP_KERNEL, vmcs_config.order);
1315 if (!pages)
1316 return NULL;
1317 vmcs = page_address(pages);
1318 memset(vmcs, 0, vmcs_config.size);
1319 vmcs->revision_id = vmcs_config.revision_id; /* vmcs revision id */
1320 return vmcs;
1321 }
1322
1323 static struct vmcs *alloc_vmcs(void)
1324 {
1325 return alloc_vmcs_cpu(raw_smp_processor_id());
1326 }
1327
1328 static void free_vmcs(struct vmcs *vmcs)
1329 {
1330 free_pages((unsigned long)vmcs, vmcs_config.order);
1331 }
1332
1333 static void free_kvm_area(void)
1334 {
1335 int cpu;
1336
1337 for_each_online_cpu(cpu)
1338 free_vmcs(per_cpu(vmxarea, cpu));
1339 }
1340
1341 static __init int alloc_kvm_area(void)
1342 {
1343 int cpu;
1344
1345 for_each_online_cpu(cpu) {
1346 struct vmcs *vmcs;
1347
1348 vmcs = alloc_vmcs_cpu(cpu);
1349 if (!vmcs) {
1350 free_kvm_area();
1351 return -ENOMEM;
1352 }
1353
1354 per_cpu(vmxarea, cpu) = vmcs;
1355 }
1356 return 0;
1357 }
1358
1359 static __init int hardware_setup(void)
1360 {
1361 if (setup_vmcs_config(&vmcs_config) < 0)
1362 return -EIO;
1363
1364 if (boot_cpu_has(X86_FEATURE_NX))
1365 kvm_enable_efer_bits(EFER_NX);
1366
1367 if (!cpu_has_vmx_vpid())
1368 enable_vpid = 0;
1369
1370 if (!cpu_has_vmx_ept()) {
1371 enable_ept = 0;
1372 enable_unrestricted_guest = 0;
1373 }
1374
1375 if (!cpu_has_vmx_unrestricted_guest())
1376 enable_unrestricted_guest = 0;
1377
1378 if (!cpu_has_vmx_flexpriority())
1379 flexpriority_enabled = 0;
1380
1381 if (!cpu_has_vmx_tpr_shadow())
1382 kvm_x86_ops->update_cr8_intercept = NULL;
1383
1384 return alloc_kvm_area();
1385 }
1386
1387 static __exit void hardware_unsetup(void)
1388 {
1389 free_kvm_area();
1390 }
1391
1392 static void fix_pmode_dataseg(int seg, struct kvm_save_segment *save)
1393 {
1394 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1395
1396 if (vmcs_readl(sf->base) == save->base && (save->base & AR_S_MASK)) {
1397 vmcs_write16(sf->selector, save->selector);
1398 vmcs_writel(sf->base, save->base);
1399 vmcs_write32(sf->limit, save->limit);
1400 vmcs_write32(sf->ar_bytes, save->ar);
1401 } else {
1402 u32 dpl = (vmcs_read16(sf->selector) & SELECTOR_RPL_MASK)
1403 << AR_DPL_SHIFT;
1404 vmcs_write32(sf->ar_bytes, 0x93 | dpl);
1405 }
1406 }
1407
1408 static void enter_pmode(struct kvm_vcpu *vcpu)
1409 {
1410 unsigned long flags;
1411 struct vcpu_vmx *vmx = to_vmx(vcpu);
1412
1413 vmx->emulation_required = 1;
1414 vmx->rmode.vm86_active = 0;
1415
1416 vmcs_writel(GUEST_TR_BASE, vmx->rmode.tr.base);
1417 vmcs_write32(GUEST_TR_LIMIT, vmx->rmode.tr.limit);
1418 vmcs_write32(GUEST_TR_AR_BYTES, vmx->rmode.tr.ar);
1419
1420 flags = vmcs_readl(GUEST_RFLAGS);
1421 flags &= ~(X86_EFLAGS_IOPL | X86_EFLAGS_VM);
1422 flags |= (vmx->rmode.save_iopl << IOPL_SHIFT);
1423 vmcs_writel(GUEST_RFLAGS, flags);
1424
1425 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
1426 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
1427
1428 update_exception_bitmap(vcpu);
1429
1430 if (emulate_invalid_guest_state)
1431 return;
1432
1433 fix_pmode_dataseg(VCPU_SREG_ES, &vmx->rmode.es);
1434 fix_pmode_dataseg(VCPU_SREG_DS, &vmx->rmode.ds);
1435 fix_pmode_dataseg(VCPU_SREG_GS, &vmx->rmode.gs);
1436 fix_pmode_dataseg(VCPU_SREG_FS, &vmx->rmode.fs);
1437
1438 vmcs_write16(GUEST_SS_SELECTOR, 0);
1439 vmcs_write32(GUEST_SS_AR_BYTES, 0x93);
1440
1441 vmcs_write16(GUEST_CS_SELECTOR,
1442 vmcs_read16(GUEST_CS_SELECTOR) & ~SELECTOR_RPL_MASK);
1443 vmcs_write32(GUEST_CS_AR_BYTES, 0x9b);
1444 }
1445
1446 static gva_t rmode_tss_base(struct kvm *kvm)
1447 {
1448 if (!kvm->arch.tss_addr) {
1449 gfn_t base_gfn = kvm->memslots[0].base_gfn +
1450 kvm->memslots[0].npages - 3;
1451 return base_gfn << PAGE_SHIFT;
1452 }
1453 return kvm->arch.tss_addr;
1454 }
1455
1456 static void fix_rmode_seg(int seg, struct kvm_save_segment *save)
1457 {
1458 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1459
1460 save->selector = vmcs_read16(sf->selector);
1461 save->base = vmcs_readl(sf->base);
1462 save->limit = vmcs_read32(sf->limit);
1463 save->ar = vmcs_read32(sf->ar_bytes);
1464 vmcs_write16(sf->selector, save->base >> 4);
1465 vmcs_write32(sf->base, save->base & 0xfffff);
1466 vmcs_write32(sf->limit, 0xffff);
1467 vmcs_write32(sf->ar_bytes, 0xf3);
1468 }
1469
1470 static void enter_rmode(struct kvm_vcpu *vcpu)
1471 {
1472 unsigned long flags;
1473 struct vcpu_vmx *vmx = to_vmx(vcpu);
1474
1475 if (enable_unrestricted_guest)
1476 return;
1477
1478 vmx->emulation_required = 1;
1479 vmx->rmode.vm86_active = 1;
1480
1481 vmx->rmode.tr.base = vmcs_readl(GUEST_TR_BASE);
1482 vmcs_writel(GUEST_TR_BASE, rmode_tss_base(vcpu->kvm));
1483
1484 vmx->rmode.tr.limit = vmcs_read32(GUEST_TR_LIMIT);
1485 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
1486
1487 vmx->rmode.tr.ar = vmcs_read32(GUEST_TR_AR_BYTES);
1488 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
1489
1490 flags = vmcs_readl(GUEST_RFLAGS);
1491 vmx->rmode.save_iopl
1492 = (flags & X86_EFLAGS_IOPL) >> IOPL_SHIFT;
1493
1494 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
1495
1496 vmcs_writel(GUEST_RFLAGS, flags);
1497 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
1498 update_exception_bitmap(vcpu);
1499
1500 if (emulate_invalid_guest_state)
1501 goto continue_rmode;
1502
1503 vmcs_write16(GUEST_SS_SELECTOR, vmcs_readl(GUEST_SS_BASE) >> 4);
1504 vmcs_write32(GUEST_SS_LIMIT, 0xffff);
1505 vmcs_write32(GUEST_SS_AR_BYTES, 0xf3);
1506
1507 vmcs_write32(GUEST_CS_AR_BYTES, 0xf3);
1508 vmcs_write32(GUEST_CS_LIMIT, 0xffff);
1509 if (vmcs_readl(GUEST_CS_BASE) == 0xffff0000)
1510 vmcs_writel(GUEST_CS_BASE, 0xf0000);
1511 vmcs_write16(GUEST_CS_SELECTOR, vmcs_readl(GUEST_CS_BASE) >> 4);
1512
1513 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.es);
1514 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.ds);
1515 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.gs);
1516 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.fs);
1517
1518 continue_rmode:
1519 kvm_mmu_reset_context(vcpu);
1520 init_rmode(vcpu->kvm);
1521 }
1522
1523 static void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
1524 {
1525 struct vcpu_vmx *vmx = to_vmx(vcpu);
1526 struct kvm_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
1527
1528 vcpu->arch.shadow_efer = efer;
1529 if (!msr)
1530 return;
1531 if (efer & EFER_LMA) {
1532 vmcs_write32(VM_ENTRY_CONTROLS,
1533 vmcs_read32(VM_ENTRY_CONTROLS) |
1534 VM_ENTRY_IA32E_MODE);
1535 msr->data = efer;
1536 } else {
1537 vmcs_write32(VM_ENTRY_CONTROLS,
1538 vmcs_read32(VM_ENTRY_CONTROLS) &
1539 ~VM_ENTRY_IA32E_MODE);
1540
1541 msr->data = efer & ~EFER_LME;
1542 }
1543 setup_msrs(vmx);
1544 }
1545
1546 #ifdef CONFIG_X86_64
1547
1548 static void enter_lmode(struct kvm_vcpu *vcpu)
1549 {
1550 u32 guest_tr_ar;
1551
1552 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
1553 if ((guest_tr_ar & AR_TYPE_MASK) != AR_TYPE_BUSY_64_TSS) {
1554 printk(KERN_DEBUG "%s: tss fixup for long mode. \n",
1555 __func__);
1556 vmcs_write32(GUEST_TR_AR_BYTES,
1557 (guest_tr_ar & ~AR_TYPE_MASK)
1558 | AR_TYPE_BUSY_64_TSS);
1559 }
1560 vcpu->arch.shadow_efer |= EFER_LMA;
1561 vmx_set_efer(vcpu, vcpu->arch.shadow_efer);
1562 }
1563
1564 static void exit_lmode(struct kvm_vcpu *vcpu)
1565 {
1566 vcpu->arch.shadow_efer &= ~EFER_LMA;
1567
1568 vmcs_write32(VM_ENTRY_CONTROLS,
1569 vmcs_read32(VM_ENTRY_CONTROLS)
1570 & ~VM_ENTRY_IA32E_MODE);
1571 }
1572
1573 #endif
1574
1575 static void vmx_flush_tlb(struct kvm_vcpu *vcpu)
1576 {
1577 vpid_sync_vcpu_all(to_vmx(vcpu));
1578 if (enable_ept)
1579 ept_sync_context(construct_eptp(vcpu->arch.mmu.root_hpa));
1580 }
1581
1582 static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
1583 {
1584 vcpu->arch.cr4 &= KVM_GUEST_CR4_MASK;
1585 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & ~KVM_GUEST_CR4_MASK;
1586 }
1587
1588 static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
1589 {
1590 if (!test_bit(VCPU_EXREG_PDPTR,
1591 (unsigned long *)&vcpu->arch.regs_dirty))
1592 return;
1593
1594 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1595 vmcs_write64(GUEST_PDPTR0, vcpu->arch.pdptrs[0]);
1596 vmcs_write64(GUEST_PDPTR1, vcpu->arch.pdptrs[1]);
1597 vmcs_write64(GUEST_PDPTR2, vcpu->arch.pdptrs[2]);
1598 vmcs_write64(GUEST_PDPTR3, vcpu->arch.pdptrs[3]);
1599 }
1600 }
1601
1602 static void ept_save_pdptrs(struct kvm_vcpu *vcpu)
1603 {
1604 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
1605 vcpu->arch.pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
1606 vcpu->arch.pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
1607 vcpu->arch.pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
1608 vcpu->arch.pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
1609 }
1610
1611 __set_bit(VCPU_EXREG_PDPTR,
1612 (unsigned long *)&vcpu->arch.regs_avail);
1613 __set_bit(VCPU_EXREG_PDPTR,
1614 (unsigned long *)&vcpu->arch.regs_dirty);
1615 }
1616
1617 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4);
1618
1619 static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
1620 unsigned long cr0,
1621 struct kvm_vcpu *vcpu)
1622 {
1623 if (!(cr0 & X86_CR0_PG)) {
1624 /* From paging/starting to nonpaging */
1625 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1626 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1627 (CPU_BASED_CR3_LOAD_EXITING |
1628 CPU_BASED_CR3_STORE_EXITING));
1629 vcpu->arch.cr0 = cr0;
1630 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1631 *hw_cr0 &= ~X86_CR0_WP;
1632 } else if (!is_paging(vcpu)) {
1633 /* From nonpaging to paging */
1634 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
1635 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1636 ~(CPU_BASED_CR3_LOAD_EXITING |
1637 CPU_BASED_CR3_STORE_EXITING));
1638 vcpu->arch.cr0 = cr0;
1639 vmx_set_cr4(vcpu, vcpu->arch.cr4);
1640 if (!(vcpu->arch.cr0 & X86_CR0_WP))
1641 *hw_cr0 &= ~X86_CR0_WP;
1642 }
1643 }
1644
1645 static void ept_update_paging_mode_cr4(unsigned long *hw_cr4,
1646 struct kvm_vcpu *vcpu)
1647 {
1648 if (!is_paging(vcpu)) {
1649 *hw_cr4 &= ~X86_CR4_PAE;
1650 *hw_cr4 |= X86_CR4_PSE;
1651 } else if (!(vcpu->arch.cr4 & X86_CR4_PAE))
1652 *hw_cr4 &= ~X86_CR4_PAE;
1653 }
1654
1655 static void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1656 {
1657 struct vcpu_vmx *vmx = to_vmx(vcpu);
1658 unsigned long hw_cr0;
1659
1660 if (enable_unrestricted_guest)
1661 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK_UNRESTRICTED_GUEST)
1662 | KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
1663 else
1664 hw_cr0 = (cr0 & ~KVM_GUEST_CR0_MASK) | KVM_VM_CR0_ALWAYS_ON;
1665
1666 vmx_fpu_deactivate(vcpu);
1667
1668 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
1669 enter_pmode(vcpu);
1670
1671 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
1672 enter_rmode(vcpu);
1673
1674 #ifdef CONFIG_X86_64
1675 if (vcpu->arch.shadow_efer & EFER_LME) {
1676 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
1677 enter_lmode(vcpu);
1678 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
1679 exit_lmode(vcpu);
1680 }
1681 #endif
1682
1683 if (enable_ept)
1684 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
1685
1686 vmcs_writel(CR0_READ_SHADOW, cr0);
1687 vmcs_writel(GUEST_CR0, hw_cr0);
1688 vcpu->arch.cr0 = cr0;
1689
1690 if (!(cr0 & X86_CR0_TS) || !(cr0 & X86_CR0_PE))
1691 vmx_fpu_activate(vcpu);
1692 }
1693
1694 static u64 construct_eptp(unsigned long root_hpa)
1695 {
1696 u64 eptp;
1697
1698 /* TODO write the value reading from MSR */
1699 eptp = VMX_EPT_DEFAULT_MT |
1700 VMX_EPT_DEFAULT_GAW << VMX_EPT_GAW_EPTP_SHIFT;
1701 eptp |= (root_hpa & PAGE_MASK);
1702
1703 return eptp;
1704 }
1705
1706 static void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1707 {
1708 unsigned long guest_cr3;
1709 u64 eptp;
1710
1711 guest_cr3 = cr3;
1712 if (enable_ept) {
1713 eptp = construct_eptp(cr3);
1714 vmcs_write64(EPT_POINTER, eptp);
1715 guest_cr3 = is_paging(vcpu) ? vcpu->arch.cr3 :
1716 VMX_EPT_IDENTITY_PAGETABLE_ADDR;
1717 }
1718
1719 vmx_flush_tlb(vcpu);
1720 vmcs_writel(GUEST_CR3, guest_cr3);
1721 if (vcpu->arch.cr0 & X86_CR0_PE)
1722 vmx_fpu_deactivate(vcpu);
1723 }
1724
1725 static void vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1726 {
1727 unsigned long hw_cr4 = cr4 | (to_vmx(vcpu)->rmode.vm86_active ?
1728 KVM_RMODE_VM_CR4_ALWAYS_ON : KVM_PMODE_VM_CR4_ALWAYS_ON);
1729
1730 vcpu->arch.cr4 = cr4;
1731 if (enable_ept)
1732 ept_update_paging_mode_cr4(&hw_cr4, vcpu);
1733
1734 vmcs_writel(CR4_READ_SHADOW, cr4);
1735 vmcs_writel(GUEST_CR4, hw_cr4);
1736 }
1737
1738 static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1739 {
1740 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1741
1742 return vmcs_readl(sf->base);
1743 }
1744
1745 static void vmx_get_segment(struct kvm_vcpu *vcpu,
1746 struct kvm_segment *var, int seg)
1747 {
1748 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1749 u32 ar;
1750
1751 var->base = vmcs_readl(sf->base);
1752 var->limit = vmcs_read32(sf->limit);
1753 var->selector = vmcs_read16(sf->selector);
1754 ar = vmcs_read32(sf->ar_bytes);
1755 if ((ar & AR_UNUSABLE_MASK) && !emulate_invalid_guest_state)
1756 ar = 0;
1757 var->type = ar & 15;
1758 var->s = (ar >> 4) & 1;
1759 var->dpl = (ar >> 5) & 3;
1760 var->present = (ar >> 7) & 1;
1761 var->avl = (ar >> 12) & 1;
1762 var->l = (ar >> 13) & 1;
1763 var->db = (ar >> 14) & 1;
1764 var->g = (ar >> 15) & 1;
1765 var->unusable = (ar >> 16) & 1;
1766 }
1767
1768 static int vmx_get_cpl(struct kvm_vcpu *vcpu)
1769 {
1770 struct kvm_segment kvm_seg;
1771
1772 if (!(vcpu->arch.cr0 & X86_CR0_PE)) /* if real mode */
1773 return 0;
1774
1775 if (vmx_get_rflags(vcpu) & X86_EFLAGS_VM) /* if virtual 8086 */
1776 return 3;
1777
1778 vmx_get_segment(vcpu, &kvm_seg, VCPU_SREG_CS);
1779 return kvm_seg.selector & 3;
1780 }
1781
1782 static u32 vmx_segment_access_rights(struct kvm_segment *var)
1783 {
1784 u32 ar;
1785
1786 if (var->unusable)
1787 ar = 1 << 16;
1788 else {
1789 ar = var->type & 15;
1790 ar |= (var->s & 1) << 4;
1791 ar |= (var->dpl & 3) << 5;
1792 ar |= (var->present & 1) << 7;
1793 ar |= (var->avl & 1) << 12;
1794 ar |= (var->l & 1) << 13;
1795 ar |= (var->db & 1) << 14;
1796 ar |= (var->g & 1) << 15;
1797 }
1798 if (ar == 0) /* a 0 value means unusable */
1799 ar = AR_UNUSABLE_MASK;
1800
1801 return ar;
1802 }
1803
1804 static void vmx_set_segment(struct kvm_vcpu *vcpu,
1805 struct kvm_segment *var, int seg)
1806 {
1807 struct vcpu_vmx *vmx = to_vmx(vcpu);
1808 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
1809 u32 ar;
1810
1811 if (vmx->rmode.vm86_active && seg == VCPU_SREG_TR) {
1812 vmx->rmode.tr.selector = var->selector;
1813 vmx->rmode.tr.base = var->base;
1814 vmx->rmode.tr.limit = var->limit;
1815 vmx->rmode.tr.ar = vmx_segment_access_rights(var);
1816 return;
1817 }
1818 vmcs_writel(sf->base, var->base);
1819 vmcs_write32(sf->limit, var->limit);
1820 vmcs_write16(sf->selector, var->selector);
1821 if (vmx->rmode.vm86_active && var->s) {
1822 /*
1823 * Hack real-mode segments into vm86 compatibility.
1824 */
1825 if (var->base == 0xffff0000 && var->selector == 0xf000)
1826 vmcs_writel(sf->base, 0xf0000);
1827 ar = 0xf3;
1828 } else
1829 ar = vmx_segment_access_rights(var);
1830
1831 /*
1832 * Fix the "Accessed" bit in AR field of segment registers for older
1833 * qemu binaries.
1834 * IA32 arch specifies that at the time of processor reset the
1835 * "Accessed" bit in the AR field of segment registers is 1. And qemu
1836 * is setting it to 0 in the usedland code. This causes invalid guest
1837 * state vmexit when "unrestricted guest" mode is turned on.
1838 * Fix for this setup issue in cpu_reset is being pushed in the qemu
1839 * tree. Newer qemu binaries with that qemu fix would not need this
1840 * kvm hack.
1841 */
1842 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
1843 ar |= 0x1; /* Accessed */
1844
1845 vmcs_write32(sf->ar_bytes, ar);
1846 }
1847
1848 static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1849 {
1850 u32 ar = vmcs_read32(GUEST_CS_AR_BYTES);
1851
1852 *db = (ar >> 14) & 1;
1853 *l = (ar >> 13) & 1;
1854 }
1855
1856 static void vmx_get_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1857 {
1858 dt->limit = vmcs_read32(GUEST_IDTR_LIMIT);
1859 dt->base = vmcs_readl(GUEST_IDTR_BASE);
1860 }
1861
1862 static void vmx_set_idt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1863 {
1864 vmcs_write32(GUEST_IDTR_LIMIT, dt->limit);
1865 vmcs_writel(GUEST_IDTR_BASE, dt->base);
1866 }
1867
1868 static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1869 {
1870 dt->limit = vmcs_read32(GUEST_GDTR_LIMIT);
1871 dt->base = vmcs_readl(GUEST_GDTR_BASE);
1872 }
1873
1874 static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct descriptor_table *dt)
1875 {
1876 vmcs_write32(GUEST_GDTR_LIMIT, dt->limit);
1877 vmcs_writel(GUEST_GDTR_BASE, dt->base);
1878 }
1879
1880 static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
1881 {
1882 struct kvm_segment var;
1883 u32 ar;
1884
1885 vmx_get_segment(vcpu, &var, seg);
1886 ar = vmx_segment_access_rights(&var);
1887
1888 if (var.base != (var.selector << 4))
1889 return false;
1890 if (var.limit != 0xffff)
1891 return false;
1892 if (ar != 0xf3)
1893 return false;
1894
1895 return true;
1896 }
1897
1898 static bool code_segment_valid(struct kvm_vcpu *vcpu)
1899 {
1900 struct kvm_segment cs;
1901 unsigned int cs_rpl;
1902
1903 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
1904 cs_rpl = cs.selector & SELECTOR_RPL_MASK;
1905
1906 if (cs.unusable)
1907 return false;
1908 if (~cs.type & (AR_TYPE_CODE_MASK|AR_TYPE_ACCESSES_MASK))
1909 return false;
1910 if (!cs.s)
1911 return false;
1912 if (cs.type & AR_TYPE_WRITEABLE_MASK) {
1913 if (cs.dpl > cs_rpl)
1914 return false;
1915 } else {
1916 if (cs.dpl != cs_rpl)
1917 return false;
1918 }
1919 if (!cs.present)
1920 return false;
1921
1922 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
1923 return true;
1924 }
1925
1926 static bool stack_segment_valid(struct kvm_vcpu *vcpu)
1927 {
1928 struct kvm_segment ss;
1929 unsigned int ss_rpl;
1930
1931 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
1932 ss_rpl = ss.selector & SELECTOR_RPL_MASK;
1933
1934 if (ss.unusable)
1935 return true;
1936 if (ss.type != 3 && ss.type != 7)
1937 return false;
1938 if (!ss.s)
1939 return false;
1940 if (ss.dpl != ss_rpl) /* DPL != RPL */
1941 return false;
1942 if (!ss.present)
1943 return false;
1944
1945 return true;
1946 }
1947
1948 static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
1949 {
1950 struct kvm_segment var;
1951 unsigned int rpl;
1952
1953 vmx_get_segment(vcpu, &var, seg);
1954 rpl = var.selector & SELECTOR_RPL_MASK;
1955
1956 if (var.unusable)
1957 return true;
1958 if (!var.s)
1959 return false;
1960 if (!var.present)
1961 return false;
1962 if (~var.type & (AR_TYPE_CODE_MASK|AR_TYPE_WRITEABLE_MASK)) {
1963 if (var.dpl < rpl) /* DPL < RPL */
1964 return false;
1965 }
1966
1967 /* TODO: Add other members to kvm_segment_field to allow checking for other access
1968 * rights flags
1969 */
1970 return true;
1971 }
1972
1973 static bool tr_valid(struct kvm_vcpu *vcpu)
1974 {
1975 struct kvm_segment tr;
1976
1977 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
1978
1979 if (tr.unusable)
1980 return false;
1981 if (tr.selector & SELECTOR_TI_MASK) /* TI = 1 */
1982 return false;
1983 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
1984 return false;
1985 if (!tr.present)
1986 return false;
1987
1988 return true;
1989 }
1990
1991 static bool ldtr_valid(struct kvm_vcpu *vcpu)
1992 {
1993 struct kvm_segment ldtr;
1994
1995 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
1996
1997 if (ldtr.unusable)
1998 return true;
1999 if (ldtr.selector & SELECTOR_TI_MASK) /* TI = 1 */
2000 return false;
2001 if (ldtr.type != 2)
2002 return false;
2003 if (!ldtr.present)
2004 return false;
2005
2006 return true;
2007 }
2008
2009 static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2010 {
2011 struct kvm_segment cs, ss;
2012
2013 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2014 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2015
2016 return ((cs.selector & SELECTOR_RPL_MASK) ==
2017 (ss.selector & SELECTOR_RPL_MASK));
2018 }
2019
2020 /*
2021 * Check if guest state is valid. Returns true if valid, false if
2022 * not.
2023 * We assume that registers are always usable
2024 */
2025 static bool guest_state_valid(struct kvm_vcpu *vcpu)
2026 {
2027 /* real mode guest state checks */
2028 if (!(vcpu->arch.cr0 & X86_CR0_PE)) {
2029 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2030 return false;
2031 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2032 return false;
2033 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2034 return false;
2035 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2036 return false;
2037 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2038 return false;
2039 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2040 return false;
2041 } else {
2042 /* protected mode guest state checks */
2043 if (!cs_ss_rpl_check(vcpu))
2044 return false;
2045 if (!code_segment_valid(vcpu))
2046 return false;
2047 if (!stack_segment_valid(vcpu))
2048 return false;
2049 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
2050 return false;
2051 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
2052 return false;
2053 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
2054 return false;
2055 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
2056 return false;
2057 if (!tr_valid(vcpu))
2058 return false;
2059 if (!ldtr_valid(vcpu))
2060 return false;
2061 }
2062 /* TODO:
2063 * - Add checks on RIP
2064 * - Add checks on RFLAGS
2065 */
2066
2067 return true;
2068 }
2069
2070 static int init_rmode_tss(struct kvm *kvm)
2071 {
2072 gfn_t fn = rmode_tss_base(kvm) >> PAGE_SHIFT;
2073 u16 data = 0;
2074 int ret = 0;
2075 int r;
2076
2077 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2078 if (r < 0)
2079 goto out;
2080 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
2081 r = kvm_write_guest_page(kvm, fn++, &data,
2082 TSS_IOPB_BASE_OFFSET, sizeof(u16));
2083 if (r < 0)
2084 goto out;
2085 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
2086 if (r < 0)
2087 goto out;
2088 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
2089 if (r < 0)
2090 goto out;
2091 data = ~0;
2092 r = kvm_write_guest_page(kvm, fn, &data,
2093 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
2094 sizeof(u8));
2095 if (r < 0)
2096 goto out;
2097
2098 ret = 1;
2099 out:
2100 return ret;
2101 }
2102
2103 static int init_rmode_identity_map(struct kvm *kvm)
2104 {
2105 int i, r, ret;
2106 pfn_t identity_map_pfn;
2107 u32 tmp;
2108
2109 if (!enable_ept)
2110 return 1;
2111 if (unlikely(!kvm->arch.ept_identity_pagetable)) {
2112 printk(KERN_ERR "EPT: identity-mapping pagetable "
2113 "haven't been allocated!\n");
2114 return 0;
2115 }
2116 if (likely(kvm->arch.ept_identity_pagetable_done))
2117 return 1;
2118 ret = 0;
2119 identity_map_pfn = VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT;
2120 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
2121 if (r < 0)
2122 goto out;
2123 /* Set up identity-mapping pagetable for EPT in real mode */
2124 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
2125 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
2126 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
2127 r = kvm_write_guest_page(kvm, identity_map_pfn,
2128 &tmp, i * sizeof(tmp), sizeof(tmp));
2129 if (r < 0)
2130 goto out;
2131 }
2132 kvm->arch.ept_identity_pagetable_done = true;
2133 ret = 1;
2134 out:
2135 return ret;
2136 }
2137
2138 static void seg_setup(int seg)
2139 {
2140 struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
2141 unsigned int ar;
2142
2143 vmcs_write16(sf->selector, 0);
2144 vmcs_writel(sf->base, 0);
2145 vmcs_write32(sf->limit, 0xffff);
2146 if (enable_unrestricted_guest) {
2147 ar = 0x93;
2148 if (seg == VCPU_SREG_CS)
2149 ar |= 0x08; /* code segment */
2150 } else
2151 ar = 0xf3;
2152
2153 vmcs_write32(sf->ar_bytes, ar);
2154 }
2155
2156 static int alloc_apic_access_page(struct kvm *kvm)
2157 {
2158 struct kvm_userspace_memory_region kvm_userspace_mem;
2159 int r = 0;
2160
2161 down_write(&kvm->slots_lock);
2162 if (kvm->arch.apic_access_page)
2163 goto out;
2164 kvm_userspace_mem.slot = APIC_ACCESS_PAGE_PRIVATE_MEMSLOT;
2165 kvm_userspace_mem.flags = 0;
2166 kvm_userspace_mem.guest_phys_addr = 0xfee00000ULL;
2167 kvm_userspace_mem.memory_size = PAGE_SIZE;
2168 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2169 if (r)
2170 goto out;
2171
2172 kvm->arch.apic_access_page = gfn_to_page(kvm, 0xfee00);
2173 out:
2174 up_write(&kvm->slots_lock);
2175 return r;
2176 }
2177
2178 static int alloc_identity_pagetable(struct kvm *kvm)
2179 {
2180 struct kvm_userspace_memory_region kvm_userspace_mem;
2181 int r = 0;
2182
2183 down_write(&kvm->slots_lock);
2184 if (kvm->arch.ept_identity_pagetable)
2185 goto out;
2186 kvm_userspace_mem.slot = IDENTITY_PAGETABLE_PRIVATE_MEMSLOT;
2187 kvm_userspace_mem.flags = 0;
2188 kvm_userspace_mem.guest_phys_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
2189 kvm_userspace_mem.memory_size = PAGE_SIZE;
2190 r = __kvm_set_memory_region(kvm, &kvm_userspace_mem, 0);
2191 if (r)
2192 goto out;
2193
2194 kvm->arch.ept_identity_pagetable = gfn_to_page(kvm,
2195 VMX_EPT_IDENTITY_PAGETABLE_ADDR >> PAGE_SHIFT);
2196 out:
2197 up_write(&kvm->slots_lock);
2198 return r;
2199 }
2200
2201 static void allocate_vpid(struct vcpu_vmx *vmx)
2202 {
2203 int vpid;
2204
2205 vmx->vpid = 0;
2206 if (!enable_vpid)
2207 return;
2208 spin_lock(&vmx_vpid_lock);
2209 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
2210 if (vpid < VMX_NR_VPIDS) {
2211 vmx->vpid = vpid;
2212 __set_bit(vpid, vmx_vpid_bitmap);
2213 }
2214 spin_unlock(&vmx_vpid_lock);
2215 }
2216
2217 static void __vmx_disable_intercept_for_msr(unsigned long *msr_bitmap, u32 msr)
2218 {
2219 int f = sizeof(unsigned long);
2220
2221 if (!cpu_has_vmx_msr_bitmap())
2222 return;
2223
2224 /*
2225 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
2226 * have the write-low and read-high bitmap offsets the wrong way round.
2227 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
2228 */
2229 if (msr <= 0x1fff) {
2230 __clear_bit(msr, msr_bitmap + 0x000 / f); /* read-low */
2231 __clear_bit(msr, msr_bitmap + 0x800 / f); /* write-low */
2232 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
2233 msr &= 0x1fff;
2234 __clear_bit(msr, msr_bitmap + 0x400 / f); /* read-high */
2235 __clear_bit(msr, msr_bitmap + 0xc00 / f); /* write-high */
2236 }
2237 }
2238
2239 static void vmx_disable_intercept_for_msr(u32 msr, bool longmode_only)
2240 {
2241 if (!longmode_only)
2242 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_legacy, msr);
2243 __vmx_disable_intercept_for_msr(vmx_msr_bitmap_longmode, msr);
2244 }
2245
2246 /*
2247 * Sets up the vmcs for emulated real mode.
2248 */
2249 static int vmx_vcpu_setup(struct vcpu_vmx *vmx)
2250 {
2251 u32 host_sysenter_cs, msr_low, msr_high;
2252 u32 junk;
2253 u64 host_pat, tsc_this, tsc_base;
2254 unsigned long a;
2255 struct descriptor_table dt;
2256 int i;
2257 unsigned long kvm_vmx_return;
2258 u32 exec_control;
2259
2260 /* I/O */
2261 vmcs_write64(IO_BITMAP_A, __pa(vmx_io_bitmap_a));
2262 vmcs_write64(IO_BITMAP_B, __pa(vmx_io_bitmap_b));
2263
2264 if (cpu_has_vmx_msr_bitmap())
2265 vmcs_write64(MSR_BITMAP, __pa(vmx_msr_bitmap_legacy));
2266
2267 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
2268
2269 /* Control */
2270 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL,
2271 vmcs_config.pin_based_exec_ctrl);
2272
2273 exec_control = vmcs_config.cpu_based_exec_ctrl;
2274 if (!vm_need_tpr_shadow(vmx->vcpu.kvm)) {
2275 exec_control &= ~CPU_BASED_TPR_SHADOW;
2276 #ifdef CONFIG_X86_64
2277 exec_control |= CPU_BASED_CR8_STORE_EXITING |
2278 CPU_BASED_CR8_LOAD_EXITING;
2279 #endif
2280 }
2281 if (!enable_ept)
2282 exec_control |= CPU_BASED_CR3_STORE_EXITING |
2283 CPU_BASED_CR3_LOAD_EXITING |
2284 CPU_BASED_INVLPG_EXITING;
2285 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, exec_control);
2286
2287 if (cpu_has_secondary_exec_ctrls()) {
2288 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
2289 if (!vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2290 exec_control &=
2291 ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
2292 if (vmx->vpid == 0)
2293 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
2294 if (!enable_ept)
2295 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
2296 if (!enable_unrestricted_guest)
2297 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
2298 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, exec_control);
2299 }
2300
2301 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, !!bypass_guest_pf);
2302 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, !!bypass_guest_pf);
2303 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
2304
2305 vmcs_writel(HOST_CR0, read_cr0()); /* 22.2.3 */
2306 vmcs_writel(HOST_CR4, read_cr4()); /* 22.2.3, 22.2.5 */
2307 vmcs_writel(HOST_CR3, read_cr3()); /* 22.2.3 FIXME: shadow tables */
2308
2309 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
2310 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2311 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2312 vmcs_write16(HOST_FS_SELECTOR, kvm_read_fs()); /* 22.2.4 */
2313 vmcs_write16(HOST_GS_SELECTOR, kvm_read_gs()); /* 22.2.4 */
2314 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
2315 #ifdef CONFIG_X86_64
2316 rdmsrl(MSR_FS_BASE, a);
2317 vmcs_writel(HOST_FS_BASE, a); /* 22.2.4 */
2318 rdmsrl(MSR_GS_BASE, a);
2319 vmcs_writel(HOST_GS_BASE, a); /* 22.2.4 */
2320 #else
2321 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
2322 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
2323 #endif
2324
2325 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
2326
2327 kvm_get_idt(&dt);
2328 vmcs_writel(HOST_IDTR_BASE, dt.base); /* 22.2.4 */
2329
2330 asm("mov $.Lkvm_vmx_return, %0" : "=r"(kvm_vmx_return));
2331 vmcs_writel(HOST_RIP, kvm_vmx_return); /* 22.2.5 */
2332 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
2333 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
2334 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
2335
2336 rdmsr(MSR_IA32_SYSENTER_CS, host_sysenter_cs, junk);
2337 vmcs_write32(HOST_IA32_SYSENTER_CS, host_sysenter_cs);
2338 rdmsrl(MSR_IA32_SYSENTER_ESP, a);
2339 vmcs_writel(HOST_IA32_SYSENTER_ESP, a); /* 22.2.3 */
2340 rdmsrl(MSR_IA32_SYSENTER_EIP, a);
2341 vmcs_writel(HOST_IA32_SYSENTER_EIP, a); /* 22.2.3 */
2342
2343 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
2344 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2345 host_pat = msr_low | ((u64) msr_high << 32);
2346 vmcs_write64(HOST_IA32_PAT, host_pat);
2347 }
2348 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
2349 rdmsr(MSR_IA32_CR_PAT, msr_low, msr_high);
2350 host_pat = msr_low | ((u64) msr_high << 32);
2351 /* Write the default value follow host pat */
2352 vmcs_write64(GUEST_IA32_PAT, host_pat);
2353 /* Keep arch.pat sync with GUEST_IA32_PAT */
2354 vmx->vcpu.arch.pat = host_pat;
2355 }
2356
2357 for (i = 0; i < NR_VMX_MSR; ++i) {
2358 u32 index = vmx_msr_index[i];
2359 u32 data_low, data_high;
2360 u64 data;
2361 int j = vmx->nmsrs;
2362
2363 if (rdmsr_safe(index, &data_low, &data_high) < 0)
2364 continue;
2365 if (wrmsr_safe(index, data_low, data_high) < 0)
2366 continue;
2367 data = data_low | ((u64)data_high << 32);
2368 vmx->host_msrs[j].index = index;
2369 vmx->host_msrs[j].reserved = 0;
2370 vmx->host_msrs[j].data = data;
2371 vmx->guest_msrs[j] = vmx->host_msrs[j];
2372 ++vmx->nmsrs;
2373 }
2374
2375 vmcs_write32(VM_EXIT_CONTROLS, vmcs_config.vmexit_ctrl);
2376
2377 /* 22.2.1, 20.8.1 */
2378 vmcs_write32(VM_ENTRY_CONTROLS, vmcs_config.vmentry_ctrl);
2379
2380 vmcs_writel(CR0_GUEST_HOST_MASK, ~0UL);
2381 vmcs_writel(CR4_GUEST_HOST_MASK, KVM_GUEST_CR4_MASK);
2382
2383 tsc_base = vmx->vcpu.kvm->arch.vm_init_tsc;
2384 rdtscll(tsc_this);
2385 if (tsc_this < vmx->vcpu.kvm->arch.vm_init_tsc)
2386 tsc_base = tsc_this;
2387
2388 guest_write_tsc(0, tsc_base);
2389
2390 return 0;
2391 }
2392
2393 static int init_rmode(struct kvm *kvm)
2394 {
2395 if (!init_rmode_tss(kvm))
2396 return 0;
2397 if (!init_rmode_identity_map(kvm))
2398 return 0;
2399 return 1;
2400 }
2401
2402 static int vmx_vcpu_reset(struct kvm_vcpu *vcpu)
2403 {
2404 struct vcpu_vmx *vmx = to_vmx(vcpu);
2405 u64 msr;
2406 int ret;
2407
2408 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP));
2409 down_read(&vcpu->kvm->slots_lock);
2410 if (!init_rmode(vmx->vcpu.kvm)) {
2411 ret = -ENOMEM;
2412 goto out;
2413 }
2414
2415 vmx->rmode.vm86_active = 0;
2416
2417 vmx->soft_vnmi_blocked = 0;
2418
2419 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
2420 kvm_set_cr8(&vmx->vcpu, 0);
2421 msr = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
2422 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2423 msr |= MSR_IA32_APICBASE_BSP;
2424 kvm_set_apic_base(&vmx->vcpu, msr);
2425
2426 fx_init(&vmx->vcpu);
2427
2428 seg_setup(VCPU_SREG_CS);
2429 /*
2430 * GUEST_CS_BASE should really be 0xffff0000, but VT vm86 mode
2431 * insists on having GUEST_CS_BASE == GUEST_CS_SELECTOR << 4. Sigh.
2432 */
2433 if (kvm_vcpu_is_bsp(&vmx->vcpu)) {
2434 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
2435 vmcs_writel(GUEST_CS_BASE, 0x000f0000);
2436 } else {
2437 vmcs_write16(GUEST_CS_SELECTOR, vmx->vcpu.arch.sipi_vector << 8);
2438 vmcs_writel(GUEST_CS_BASE, vmx->vcpu.arch.sipi_vector << 12);
2439 }
2440
2441 seg_setup(VCPU_SREG_DS);
2442 seg_setup(VCPU_SREG_ES);
2443 seg_setup(VCPU_SREG_FS);
2444 seg_setup(VCPU_SREG_GS);
2445 seg_setup(VCPU_SREG_SS);
2446
2447 vmcs_write16(GUEST_TR_SELECTOR, 0);
2448 vmcs_writel(GUEST_TR_BASE, 0);
2449 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
2450 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2451
2452 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
2453 vmcs_writel(GUEST_LDTR_BASE, 0);
2454 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
2455 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
2456
2457 vmcs_write32(GUEST_SYSENTER_CS, 0);
2458 vmcs_writel(GUEST_SYSENTER_ESP, 0);
2459 vmcs_writel(GUEST_SYSENTER_EIP, 0);
2460
2461 vmcs_writel(GUEST_RFLAGS, 0x02);
2462 if (kvm_vcpu_is_bsp(&vmx->vcpu))
2463 kvm_rip_write(vcpu, 0xfff0);
2464 else
2465 kvm_rip_write(vcpu, 0);
2466 kvm_register_write(vcpu, VCPU_REGS_RSP, 0);
2467
2468 vmcs_writel(GUEST_DR7, 0x400);
2469
2470 vmcs_writel(GUEST_GDTR_BASE, 0);
2471 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
2472
2473 vmcs_writel(GUEST_IDTR_BASE, 0);
2474 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
2475
2476 vmcs_write32(GUEST_ACTIVITY_STATE, 0);
2477 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
2478 vmcs_write32(GUEST_PENDING_DBG_EXCEPTIONS, 0);
2479
2480 /* Special registers */
2481 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
2482
2483 setup_msrs(vmx);
2484
2485 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
2486
2487 if (cpu_has_vmx_tpr_shadow()) {
2488 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
2489 if (vm_need_tpr_shadow(vmx->vcpu.kvm))
2490 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
2491 page_to_phys(vmx->vcpu.arch.apic->regs_page));
2492 vmcs_write32(TPR_THRESHOLD, 0);
2493 }
2494
2495 if (vm_need_virtualize_apic_accesses(vmx->vcpu.kvm))
2496 vmcs_write64(APIC_ACCESS_ADDR,
2497 page_to_phys(vmx->vcpu.kvm->arch.apic_access_page));
2498
2499 if (vmx->vpid != 0)
2500 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
2501
2502 vmx->vcpu.arch.cr0 = 0x60000010;
2503 vmx_set_cr0(&vmx->vcpu, vmx->vcpu.arch.cr0); /* enter rmode */
2504 vmx_set_cr4(&vmx->vcpu, 0);
2505 vmx_set_efer(&vmx->vcpu, 0);
2506 vmx_fpu_activate(&vmx->vcpu);
2507 update_exception_bitmap(&vmx->vcpu);
2508
2509 vpid_sync_vcpu_all(vmx);
2510
2511 ret = 0;
2512
2513 /* HACK: Don't enable emulation on guest boot/reset */
2514 vmx->emulation_required = 0;
2515
2516 out:
2517 up_read(&vcpu->kvm->slots_lock);
2518 return ret;
2519 }
2520
2521 static void enable_irq_window(struct kvm_vcpu *vcpu)
2522 {
2523 u32 cpu_based_vm_exec_control;
2524
2525 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2526 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_INTR_PENDING;
2527 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2528 }
2529
2530 static void enable_nmi_window(struct kvm_vcpu *vcpu)
2531 {
2532 u32 cpu_based_vm_exec_control;
2533
2534 if (!cpu_has_virtual_nmis()) {
2535 enable_irq_window(vcpu);
2536 return;
2537 }
2538
2539 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
2540 cpu_based_vm_exec_control |= CPU_BASED_VIRTUAL_NMI_PENDING;
2541 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
2542 }
2543
2544 static void vmx_inject_irq(struct kvm_vcpu *vcpu)
2545 {
2546 struct vcpu_vmx *vmx = to_vmx(vcpu);
2547 uint32_t intr;
2548 int irq = vcpu->arch.interrupt.nr;
2549
2550 KVMTRACE_1D(INJ_VIRQ, vcpu, (u32)irq, handler);
2551
2552 ++vcpu->stat.irq_injections;
2553 if (vmx->rmode.vm86_active) {
2554 vmx->rmode.irq.pending = true;
2555 vmx->rmode.irq.vector = irq;
2556 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2557 if (vcpu->arch.interrupt.soft)
2558 vmx->rmode.irq.rip +=
2559 vmx->vcpu.arch.event_exit_inst_len;
2560 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2561 irq | INTR_TYPE_SOFT_INTR | INTR_INFO_VALID_MASK);
2562 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2563 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2564 return;
2565 }
2566 intr = irq | INTR_INFO_VALID_MASK;
2567 if (vcpu->arch.interrupt.soft) {
2568 intr |= INTR_TYPE_SOFT_INTR;
2569 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
2570 vmx->vcpu.arch.event_exit_inst_len);
2571 } else
2572 intr |= INTR_TYPE_EXT_INTR;
2573 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
2574 }
2575
2576 static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
2577 {
2578 struct vcpu_vmx *vmx = to_vmx(vcpu);
2579
2580 if (!cpu_has_virtual_nmis()) {
2581 /*
2582 * Tracking the NMI-blocked state in software is built upon
2583 * finding the next open IRQ window. This, in turn, depends on
2584 * well-behaving guests: They have to keep IRQs disabled at
2585 * least as long as the NMI handler runs. Otherwise we may
2586 * cause NMI nesting, maybe breaking the guest. But as this is
2587 * highly unlikely, we can live with the residual risk.
2588 */
2589 vmx->soft_vnmi_blocked = 1;
2590 vmx->vnmi_blocked_time = 0;
2591 }
2592
2593 ++vcpu->stat.nmi_injections;
2594 if (vmx->rmode.vm86_active) {
2595 vmx->rmode.irq.pending = true;
2596 vmx->rmode.irq.vector = NMI_VECTOR;
2597 vmx->rmode.irq.rip = kvm_rip_read(vcpu);
2598 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2599 NMI_VECTOR | INTR_TYPE_SOFT_INTR |
2600 INTR_INFO_VALID_MASK);
2601 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN, 1);
2602 kvm_rip_write(vcpu, vmx->rmode.irq.rip - 1);
2603 return;
2604 }
2605 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
2606 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
2607 }
2608
2609 static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
2610 {
2611 if (!cpu_has_virtual_nmis() && to_vmx(vcpu)->soft_vnmi_blocked)
2612 return 0;
2613
2614 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2615 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS |
2616 GUEST_INTR_STATE_NMI));
2617 }
2618
2619 static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
2620 {
2621 return (vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
2622 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
2623 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
2624 }
2625
2626 static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
2627 {
2628 int ret;
2629 struct kvm_userspace_memory_region tss_mem = {
2630 .slot = TSS_PRIVATE_MEMSLOT,
2631 .guest_phys_addr = addr,
2632 .memory_size = PAGE_SIZE * 3,
2633 .flags = 0,
2634 };
2635
2636 ret = kvm_set_memory_region(kvm, &tss_mem, 0);
2637 if (ret)
2638 return ret;
2639 kvm->arch.tss_addr = addr;
2640 return 0;
2641 }
2642
2643 static int handle_rmode_exception(struct kvm_vcpu *vcpu,
2644 int vec, u32 err_code)
2645 {
2646 /*
2647 * Instruction with address size override prefix opcode 0x67
2648 * Cause the #SS fault with 0 error code in VM86 mode.
2649 */
2650 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0)
2651 if (emulate_instruction(vcpu, NULL, 0, 0, 0) == EMULATE_DONE)
2652 return 1;
2653 /*
2654 * Forward all other exceptions that are valid in real mode.
2655 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
2656 * the required debugging infrastructure rework.
2657 */
2658 switch (vec) {
2659 case DB_VECTOR:
2660 if (vcpu->guest_debug &
2661 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
2662 return 0;
2663 kvm_queue_exception(vcpu, vec);
2664 return 1;
2665 case BP_VECTOR:
2666 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
2667 return 0;
2668 /* fall through */
2669 case DE_VECTOR:
2670 case OF_VECTOR:
2671 case BR_VECTOR:
2672 case UD_VECTOR:
2673 case DF_VECTOR:
2674 case SS_VECTOR:
2675 case GP_VECTOR:
2676 case MF_VECTOR:
2677 kvm_queue_exception(vcpu, vec);
2678 return 1;
2679 }
2680 return 0;
2681 }
2682
2683 /*
2684 * Trigger machine check on the host. We assume all the MSRs are already set up
2685 * by the CPU and that we still run on the same CPU as the MCE occurred on.
2686 * We pass a fake environment to the machine check handler because we want
2687 * the guest to be always treated like user space, no matter what context
2688 * it used internally.
2689 */
2690 static void kvm_machine_check(void)
2691 {
2692 #if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
2693 struct pt_regs regs = {
2694 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
2695 .flags = X86_EFLAGS_IF,
2696 };
2697
2698 do_machine_check(&regs, 0);
2699 #endif
2700 }
2701
2702 static int handle_machine_check(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2703 {
2704 /* already handled by vcpu_run */
2705 return 1;
2706 }
2707
2708 static int handle_exception(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2709 {
2710 struct vcpu_vmx *vmx = to_vmx(vcpu);
2711 u32 intr_info, ex_no, error_code;
2712 unsigned long cr2, rip, dr6;
2713 u32 vect_info;
2714 enum emulation_result er;
2715
2716 vect_info = vmx->idt_vectoring_info;
2717 intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
2718
2719 if (is_machine_check(intr_info))
2720 return handle_machine_check(vcpu, kvm_run);
2721
2722 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
2723 !is_page_fault(intr_info))
2724 printk(KERN_ERR "%s: unexpected, vectoring info 0x%x "
2725 "intr info 0x%x\n", __func__, vect_info, intr_info);
2726
2727 if ((intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR)
2728 return 1; /* already handled by vmx_vcpu_run() */
2729
2730 if (is_no_device(intr_info)) {
2731 vmx_fpu_activate(vcpu);
2732 return 1;
2733 }
2734
2735 if (is_invalid_opcode(intr_info)) {
2736 er = emulate_instruction(vcpu, kvm_run, 0, 0, EMULTYPE_TRAP_UD);
2737 if (er != EMULATE_DONE)
2738 kvm_queue_exception(vcpu, UD_VECTOR);
2739 return 1;
2740 }
2741
2742 error_code = 0;
2743 rip = kvm_rip_read(vcpu);
2744 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
2745 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
2746 if (is_page_fault(intr_info)) {
2747 /* EPT won't cause page fault directly */
2748 if (enable_ept)
2749 BUG();
2750 cr2 = vmcs_readl(EXIT_QUALIFICATION);
2751 KVMTRACE_3D(PAGE_FAULT, vcpu, error_code, (u32)cr2,
2752 (u32)((u64)cr2 >> 32), handler);
2753 if (kvm_event_needs_reinjection(vcpu))
2754 kvm_mmu_unprotect_page_virt(vcpu, cr2);
2755 return kvm_mmu_page_fault(vcpu, cr2, error_code);
2756 }
2757
2758 if (vmx->rmode.vm86_active &&
2759 handle_rmode_exception(vcpu, intr_info & INTR_INFO_VECTOR_MASK,
2760 error_code)) {
2761 if (vcpu->arch.halt_request) {
2762 vcpu->arch.halt_request = 0;
2763 return kvm_emulate_halt(vcpu);
2764 }
2765 return 1;
2766 }
2767
2768 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
2769 switch (ex_no) {
2770 case DB_VECTOR:
2771 dr6 = vmcs_readl(EXIT_QUALIFICATION);
2772 if (!(vcpu->guest_debug &
2773 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
2774 vcpu->arch.dr6 = dr6 | DR6_FIXED_1;
2775 kvm_queue_exception(vcpu, DB_VECTOR);
2776 return 1;
2777 }
2778 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
2779 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
2780 /* fall through */
2781 case BP_VECTOR:
2782 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2783 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
2784 kvm_run->debug.arch.exception = ex_no;
2785 break;
2786 default:
2787 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
2788 kvm_run->ex.exception = ex_no;
2789 kvm_run->ex.error_code = error_code;
2790 break;
2791 }
2792 return 0;
2793 }
2794
2795 static int handle_external_interrupt(struct kvm_vcpu *vcpu,
2796 struct kvm_run *kvm_run)
2797 {
2798 ++vcpu->stat.irq_exits;
2799 KVMTRACE_1D(INTR, vcpu, vmcs_read32(VM_EXIT_INTR_INFO), handler);
2800 return 1;
2801 }
2802
2803 static int handle_triple_fault(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2804 {
2805 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2806 return 0;
2807 }
2808
2809 static int handle_io(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2810 {
2811 unsigned long exit_qualification;
2812 int size, in, string;
2813 unsigned port;
2814
2815 ++vcpu->stat.io_exits;
2816 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2817 string = (exit_qualification & 16) != 0;
2818
2819 if (string) {
2820 if (emulate_instruction(vcpu,
2821 kvm_run, 0, 0, 0) == EMULATE_DO_MMIO)
2822 return 0;
2823 return 1;
2824 }
2825
2826 size = (exit_qualification & 7) + 1;
2827 in = (exit_qualification & 8) != 0;
2828 port = exit_qualification >> 16;
2829
2830 skip_emulated_instruction(vcpu);
2831 return kvm_emulate_pio(vcpu, kvm_run, in, size, port);
2832 }
2833
2834 static void
2835 vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
2836 {
2837 /*
2838 * Patch in the VMCALL instruction:
2839 */
2840 hypercall[0] = 0x0f;
2841 hypercall[1] = 0x01;
2842 hypercall[2] = 0xc1;
2843 }
2844
2845 static int handle_cr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2846 {
2847 unsigned long exit_qualification;
2848 int cr;
2849 int reg;
2850
2851 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2852 cr = exit_qualification & 15;
2853 reg = (exit_qualification >> 8) & 15;
2854 switch ((exit_qualification >> 4) & 3) {
2855 case 0: /* mov to cr */
2856 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr,
2857 (u32)kvm_register_read(vcpu, reg),
2858 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2859 handler);
2860 switch (cr) {
2861 case 0:
2862 kvm_set_cr0(vcpu, kvm_register_read(vcpu, reg));
2863 skip_emulated_instruction(vcpu);
2864 return 1;
2865 case 3:
2866 kvm_set_cr3(vcpu, kvm_register_read(vcpu, reg));
2867 skip_emulated_instruction(vcpu);
2868 return 1;
2869 case 4:
2870 kvm_set_cr4(vcpu, kvm_register_read(vcpu, reg));
2871 skip_emulated_instruction(vcpu);
2872 return 1;
2873 case 8: {
2874 u8 cr8_prev = kvm_get_cr8(vcpu);
2875 u8 cr8 = kvm_register_read(vcpu, reg);
2876 kvm_set_cr8(vcpu, cr8);
2877 skip_emulated_instruction(vcpu);
2878 if (irqchip_in_kernel(vcpu->kvm))
2879 return 1;
2880 if (cr8_prev <= cr8)
2881 return 1;
2882 kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2883 return 0;
2884 }
2885 };
2886 break;
2887 case 2: /* clts */
2888 vmx_fpu_deactivate(vcpu);
2889 vcpu->arch.cr0 &= ~X86_CR0_TS;
2890 vmcs_writel(CR0_READ_SHADOW, vcpu->arch.cr0);
2891 vmx_fpu_activate(vcpu);
2892 KVMTRACE_0D(CLTS, vcpu, handler);
2893 skip_emulated_instruction(vcpu);
2894 return 1;
2895 case 1: /*mov from cr*/
2896 switch (cr) {
2897 case 3:
2898 kvm_register_write(vcpu, reg, vcpu->arch.cr3);
2899 KVMTRACE_3D(CR_READ, vcpu, (u32)cr,
2900 (u32)kvm_register_read(vcpu, reg),
2901 (u32)((u64)kvm_register_read(vcpu, reg) >> 32),
2902 handler);
2903 skip_emulated_instruction(vcpu);
2904 return 1;
2905 case 8:
2906 kvm_register_write(vcpu, reg, kvm_get_cr8(vcpu));
2907 KVMTRACE_2D(CR_READ, vcpu, (u32)cr,
2908 (u32)kvm_register_read(vcpu, reg), handler);
2909 skip_emulated_instruction(vcpu);
2910 return 1;
2911 }
2912 break;
2913 case 3: /* lmsw */
2914 kvm_lmsw(vcpu, (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f);
2915
2916 skip_emulated_instruction(vcpu);
2917 return 1;
2918 default:
2919 break;
2920 }
2921 kvm_run->exit_reason = 0;
2922 pr_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
2923 (int)(exit_qualification >> 4) & 3, cr);
2924 return 0;
2925 }
2926
2927 static int handle_dr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
2928 {
2929 unsigned long exit_qualification;
2930 unsigned long val;
2931 int dr, reg;
2932
2933 dr = vmcs_readl(GUEST_DR7);
2934 if (dr & DR7_GD) {
2935 /*
2936 * As the vm-exit takes precedence over the debug trap, we
2937 * need to emulate the latter, either for the host or the
2938 * guest debugging itself.
2939 */
2940 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
2941 kvm_run->debug.arch.dr6 = vcpu->arch.dr6;
2942 kvm_run->debug.arch.dr7 = dr;
2943 kvm_run->debug.arch.pc =
2944 vmcs_readl(GUEST_CS_BASE) +
2945 vmcs_readl(GUEST_RIP);
2946 kvm_run->debug.arch.exception = DB_VECTOR;
2947 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2948 return 0;
2949 } else {
2950 vcpu->arch.dr7 &= ~DR7_GD;
2951 vcpu->arch.dr6 |= DR6_BD;
2952 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
2953 kvm_queue_exception(vcpu, DB_VECTOR);
2954 return 1;
2955 }
2956 }
2957
2958 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
2959 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
2960 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
2961 if (exit_qualification & TYPE_MOV_FROM_DR) {
2962 switch (dr) {
2963 case 0 ... 3:
2964 val = vcpu->arch.db[dr];
2965 break;
2966 case 6:
2967 val = vcpu->arch.dr6;
2968 break;
2969 case 7:
2970 val = vcpu->arch.dr7;
2971 break;
2972 default:
2973 val = 0;
2974 }
2975 kvm_register_write(vcpu, reg, val);
2976 KVMTRACE_2D(DR_READ, vcpu, (u32)dr, (u32)val, handler);
2977 } else {
2978 val = vcpu->arch.regs[reg];
2979 switch (dr) {
2980 case 0 ... 3:
2981 vcpu->arch.db[dr] = val;
2982 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP))
2983 vcpu->arch.eff_db[dr] = val;
2984 break;
2985 case 4 ... 5:
2986 if (vcpu->arch.cr4 & X86_CR4_DE)
2987 kvm_queue_exception(vcpu, UD_VECTOR);
2988 break;
2989 case 6:
2990 if (val & 0xffffffff00000000ULL) {
2991 kvm_queue_exception(vcpu, GP_VECTOR);
2992 break;
2993 }
2994 vcpu->arch.dr6 = (val & DR6_VOLATILE) | DR6_FIXED_1;
2995 break;
2996 case 7:
2997 if (val & 0xffffffff00000000ULL) {
2998 kvm_queue_exception(vcpu, GP_VECTOR);
2999 break;
3000 }
3001 vcpu->arch.dr7 = (val & DR7_VOLATILE) | DR7_FIXED_1;
3002 if (!(vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP)) {
3003 vmcs_writel(GUEST_DR7, vcpu->arch.dr7);
3004 vcpu->arch.switch_db_regs =
3005 (val & DR7_BP_EN_MASK);
3006 }
3007 break;
3008 }
3009 KVMTRACE_2D(DR_WRITE, vcpu, (u32)dr, (u32)val, handler);
3010 }
3011 skip_emulated_instruction(vcpu);
3012 return 1;
3013 }
3014
3015 static int handle_cpuid(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3016 {
3017 kvm_emulate_cpuid(vcpu);
3018 return 1;
3019 }
3020
3021 static int handle_rdmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3022 {
3023 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3024 u64 data;
3025
3026 if (vmx_get_msr(vcpu, ecx, &data)) {
3027 kvm_inject_gp(vcpu, 0);
3028 return 1;
3029 }
3030
3031 KVMTRACE_3D(MSR_READ, vcpu, ecx, (u32)data, (u32)(data >> 32),
3032 handler);
3033
3034 /* FIXME: handling of bits 32:63 of rax, rdx */
3035 vcpu->arch.regs[VCPU_REGS_RAX] = data & -1u;
3036 vcpu->arch.regs[VCPU_REGS_RDX] = (data >> 32) & -1u;
3037 skip_emulated_instruction(vcpu);
3038 return 1;
3039 }
3040
3041 static int handle_wrmsr(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3042 {
3043 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
3044 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
3045 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
3046
3047 KVMTRACE_3D(MSR_WRITE, vcpu, ecx, (u32)data, (u32)(data >> 32),
3048 handler);
3049
3050 if (vmx_set_msr(vcpu, ecx, data) != 0) {
3051 kvm_inject_gp(vcpu, 0);
3052 return 1;
3053 }
3054
3055 skip_emulated_instruction(vcpu);
3056 return 1;
3057 }
3058
3059 static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu,
3060 struct kvm_run *kvm_run)
3061 {
3062 return 1;
3063 }
3064
3065 static int handle_interrupt_window(struct kvm_vcpu *vcpu,
3066 struct kvm_run *kvm_run)
3067 {
3068 u32 cpu_based_vm_exec_control;
3069
3070 /* clear pending irq */
3071 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3072 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_INTR_PENDING;
3073 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3074
3075 KVMTRACE_0D(PEND_INTR, vcpu, handler);
3076 ++vcpu->stat.irq_window_exits;
3077
3078 /*
3079 * If the user space waits to inject interrupts, exit as soon as
3080 * possible
3081 */
3082 if (!irqchip_in_kernel(vcpu->kvm) &&
3083 kvm_run->request_interrupt_window &&
3084 !kvm_cpu_has_interrupt(vcpu)) {
3085 kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
3086 return 0;
3087 }
3088 return 1;
3089 }
3090
3091 static int handle_halt(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3092 {
3093 skip_emulated_instruction(vcpu);
3094 return kvm_emulate_halt(vcpu);
3095 }
3096
3097 static int handle_vmcall(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3098 {
3099 skip_emulated_instruction(vcpu);
3100 kvm_emulate_hypercall(vcpu);
3101 return 1;
3102 }
3103
3104 static int handle_vmx_insn(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3105 {
3106 kvm_queue_exception(vcpu, UD_VECTOR);
3107 return 1;
3108 }
3109
3110 static int handle_invlpg(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3111 {
3112 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3113
3114 kvm_mmu_invlpg(vcpu, exit_qualification);
3115 skip_emulated_instruction(vcpu);
3116 return 1;
3117 }
3118
3119 static int handle_wbinvd(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3120 {
3121 skip_emulated_instruction(vcpu);
3122 /* TODO: Add support for VT-d/pass-through device */
3123 return 1;
3124 }
3125
3126 static int handle_apic_access(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3127 {
3128 unsigned long exit_qualification;
3129 enum emulation_result er;
3130 unsigned long offset;
3131
3132 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3133 offset = exit_qualification & 0xffful;
3134
3135 er = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3136
3137 if (er != EMULATE_DONE) {
3138 printk(KERN_ERR
3139 "Fail to handle apic access vmexit! Offset is 0x%lx\n",
3140 offset);
3141 return -ENOTSUPP;
3142 }
3143 return 1;
3144 }
3145
3146 static int handle_task_switch(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3147 {
3148 struct vcpu_vmx *vmx = to_vmx(vcpu);
3149 unsigned long exit_qualification;
3150 u16 tss_selector;
3151 int reason, type, idt_v;
3152
3153 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
3154 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
3155
3156 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3157
3158 reason = (u32)exit_qualification >> 30;
3159 if (reason == TASK_SWITCH_GATE && idt_v) {
3160 switch (type) {
3161 case INTR_TYPE_NMI_INTR:
3162 vcpu->arch.nmi_injected = false;
3163 if (cpu_has_virtual_nmis())
3164 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3165 GUEST_INTR_STATE_NMI);
3166 break;
3167 case INTR_TYPE_EXT_INTR:
3168 case INTR_TYPE_SOFT_INTR:
3169 kvm_clear_interrupt_queue(vcpu);
3170 break;
3171 case INTR_TYPE_HARD_EXCEPTION:
3172 case INTR_TYPE_SOFT_EXCEPTION:
3173 kvm_clear_exception_queue(vcpu);
3174 break;
3175 default:
3176 break;
3177 }
3178 }
3179 tss_selector = exit_qualification;
3180
3181 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
3182 type != INTR_TYPE_EXT_INTR &&
3183 type != INTR_TYPE_NMI_INTR))
3184 skip_emulated_instruction(vcpu);
3185
3186 if (!kvm_task_switch(vcpu, tss_selector, reason))
3187 return 0;
3188
3189 /* clear all local breakpoint enable flags */
3190 vmcs_writel(GUEST_DR7, vmcs_readl(GUEST_DR7) & ~55);
3191
3192 /*
3193 * TODO: What about debug traps on tss switch?
3194 * Are we supposed to inject them and update dr6?
3195 */
3196
3197 return 1;
3198 }
3199
3200 static int handle_ept_violation(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3201 {
3202 unsigned long exit_qualification;
3203 gpa_t gpa;
3204 int gla_validity;
3205
3206 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
3207
3208 if (exit_qualification & (1 << 6)) {
3209 printk(KERN_ERR "EPT: GPA exceeds GAW!\n");
3210 return -ENOTSUPP;
3211 }
3212
3213 gla_validity = (exit_qualification >> 7) & 0x3;
3214 if (gla_validity != 0x3 && gla_validity != 0x1 && gla_validity != 0) {
3215 printk(KERN_ERR "EPT: Handling EPT violation failed!\n");
3216 printk(KERN_ERR "EPT: GPA: 0x%lx, GVA: 0x%lx\n",
3217 (long unsigned int)vmcs_read64(GUEST_PHYSICAL_ADDRESS),
3218 vmcs_readl(GUEST_LINEAR_ADDRESS));
3219 printk(KERN_ERR "EPT: Exit qualification is 0x%lx\n",
3220 (long unsigned int)exit_qualification);
3221 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3222 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_VIOLATION;
3223 return 0;
3224 }
3225
3226 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3227 return kvm_mmu_page_fault(vcpu, gpa & PAGE_MASK, 0);
3228 }
3229
3230 static u64 ept_rsvd_mask(u64 spte, int level)
3231 {
3232 int i;
3233 u64 mask = 0;
3234
3235 for (i = 51; i > boot_cpu_data.x86_phys_bits; i--)
3236 mask |= (1ULL << i);
3237
3238 if (level > 2)
3239 /* bits 7:3 reserved */
3240 mask |= 0xf8;
3241 else if (level == 2) {
3242 if (spte & (1ULL << 7))
3243 /* 2MB ref, bits 20:12 reserved */
3244 mask |= 0x1ff000;
3245 else
3246 /* bits 6:3 reserved */
3247 mask |= 0x78;
3248 }
3249
3250 return mask;
3251 }
3252
3253 static void ept_misconfig_inspect_spte(struct kvm_vcpu *vcpu, u64 spte,
3254 int level)
3255 {
3256 printk(KERN_ERR "%s: spte 0x%llx level %d\n", __func__, spte, level);
3257
3258 /* 010b (write-only) */
3259 WARN_ON((spte & 0x7) == 0x2);
3260
3261 /* 110b (write/execute) */
3262 WARN_ON((spte & 0x7) == 0x6);
3263
3264 /* 100b (execute-only) and value not supported by logical processor */
3265 if (!cpu_has_vmx_ept_execute_only())
3266 WARN_ON((spte & 0x7) == 0x4);
3267
3268 /* not 000b */
3269 if ((spte & 0x7)) {
3270 u64 rsvd_bits = spte & ept_rsvd_mask(spte, level);
3271
3272 if (rsvd_bits != 0) {
3273 printk(KERN_ERR "%s: rsvd_bits = 0x%llx\n",
3274 __func__, rsvd_bits);
3275 WARN_ON(1);
3276 }
3277
3278 if (level == 1 || (level == 2 && (spte & (1ULL << 7)))) {
3279 u64 ept_mem_type = (spte & 0x38) >> 3;
3280
3281 if (ept_mem_type == 2 || ept_mem_type == 3 ||
3282 ept_mem_type == 7) {
3283 printk(KERN_ERR "%s: ept_mem_type=0x%llx\n",
3284 __func__, ept_mem_type);
3285 WARN_ON(1);
3286 }
3287 }
3288 }
3289 }
3290
3291 static int handle_ept_misconfig(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3292 {
3293 u64 sptes[4];
3294 int nr_sptes, i;
3295 gpa_t gpa;
3296
3297 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
3298
3299 printk(KERN_ERR "EPT: Misconfiguration.\n");
3300 printk(KERN_ERR "EPT: GPA: 0x%llx\n", gpa);
3301
3302 nr_sptes = kvm_mmu_get_spte_hierarchy(vcpu, gpa, sptes);
3303
3304 for (i = PT64_ROOT_LEVEL; i > PT64_ROOT_LEVEL - nr_sptes; --i)
3305 ept_misconfig_inspect_spte(vcpu, sptes[i-1], i);
3306
3307 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3308 kvm_run->hw.hardware_exit_reason = EXIT_REASON_EPT_MISCONFIG;
3309
3310 return 0;
3311 }
3312
3313 static int handle_nmi_window(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3314 {
3315 u32 cpu_based_vm_exec_control;
3316
3317 /* clear pending NMI */
3318 cpu_based_vm_exec_control = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
3319 cpu_based_vm_exec_control &= ~CPU_BASED_VIRTUAL_NMI_PENDING;
3320 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, cpu_based_vm_exec_control);
3321 ++vcpu->stat.nmi_window_exits;
3322
3323 return 1;
3324 }
3325
3326 static void handle_invalid_guest_state(struct kvm_vcpu *vcpu,
3327 struct kvm_run *kvm_run)
3328 {
3329 struct vcpu_vmx *vmx = to_vmx(vcpu);
3330 enum emulation_result err = EMULATE_DONE;
3331
3332 local_irq_enable();
3333 preempt_enable();
3334
3335 while (!guest_state_valid(vcpu)) {
3336 err = emulate_instruction(vcpu, kvm_run, 0, 0, 0);
3337
3338 if (err == EMULATE_DO_MMIO)
3339 break;
3340
3341 if (err != EMULATE_DONE) {
3342 kvm_report_emulation_failure(vcpu, "emulation failure");
3343 break;
3344 }
3345
3346 if (signal_pending(current))
3347 break;
3348 if (need_resched())
3349 schedule();
3350 }
3351
3352 preempt_disable();
3353 local_irq_disable();
3354
3355 vmx->invalid_state_emulation_result = err;
3356 }
3357
3358 /*
3359 * The exit handlers return 1 if the exit was handled fully and guest execution
3360 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
3361 * to be done to userspace and return 0.
3362 */
3363 static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu,
3364 struct kvm_run *kvm_run) = {
3365 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
3366 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
3367 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
3368 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
3369 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
3370 [EXIT_REASON_CR_ACCESS] = handle_cr,
3371 [EXIT_REASON_DR_ACCESS] = handle_dr,
3372 [EXIT_REASON_CPUID] = handle_cpuid,
3373 [EXIT_REASON_MSR_READ] = handle_rdmsr,
3374 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
3375 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
3376 [EXIT_REASON_HLT] = handle_halt,
3377 [EXIT_REASON_INVLPG] = handle_invlpg,
3378 [EXIT_REASON_VMCALL] = handle_vmcall,
3379 [EXIT_REASON_VMCLEAR] = handle_vmx_insn,
3380 [EXIT_REASON_VMLAUNCH] = handle_vmx_insn,
3381 [EXIT_REASON_VMPTRLD] = handle_vmx_insn,
3382 [EXIT_REASON_VMPTRST] = handle_vmx_insn,
3383 [EXIT_REASON_VMREAD] = handle_vmx_insn,
3384 [EXIT_REASON_VMRESUME] = handle_vmx_insn,
3385 [EXIT_REASON_VMWRITE] = handle_vmx_insn,
3386 [EXIT_REASON_VMOFF] = handle_vmx_insn,
3387 [EXIT_REASON_VMON] = handle_vmx_insn,
3388 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
3389 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
3390 [EXIT_REASON_WBINVD] = handle_wbinvd,
3391 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
3392 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
3393 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
3394 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
3395 };
3396
3397 static const int kvm_vmx_max_exit_handlers =
3398 ARRAY_SIZE(kvm_vmx_exit_handlers);
3399
3400 /*
3401 * The guest has exited. See if we can fix it or if we need userspace
3402 * assistance.
3403 */
3404 static int vmx_handle_exit(struct kvm_run *kvm_run, struct kvm_vcpu *vcpu)
3405 {
3406 struct vcpu_vmx *vmx = to_vmx(vcpu);
3407 u32 exit_reason = vmx->exit_reason;
3408 u32 vectoring_info = vmx->idt_vectoring_info;
3409
3410 KVMTRACE_3D(VMEXIT, vcpu, exit_reason, (u32)kvm_rip_read(vcpu),
3411 (u32)((u64)kvm_rip_read(vcpu) >> 32), entryexit);
3412
3413 /* If we need to emulate an MMIO from handle_invalid_guest_state
3414 * we just return 0 */
3415 if (vmx->emulation_required && emulate_invalid_guest_state) {
3416 if (guest_state_valid(vcpu))
3417 vmx->emulation_required = 0;
3418 return vmx->invalid_state_emulation_result != EMULATE_DO_MMIO;
3419 }
3420
3421 /* Access CR3 don't cause VMExit in paging mode, so we need
3422 * to sync with guest real CR3. */
3423 if (enable_ept && is_paging(vcpu))
3424 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
3425
3426 if (unlikely(vmx->fail)) {
3427 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3428 kvm_run->fail_entry.hardware_entry_failure_reason
3429 = vmcs_read32(VM_INSTRUCTION_ERROR);
3430 return 0;
3431 }
3432
3433 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
3434 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
3435 exit_reason != EXIT_REASON_EPT_VIOLATION &&
3436 exit_reason != EXIT_REASON_TASK_SWITCH))
3437 printk(KERN_WARNING "%s: unexpected, valid vectoring info "
3438 "(0x%x) and exit reason is 0x%x\n",
3439 __func__, vectoring_info, exit_reason);
3440
3441 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked)) {
3442 if (vmx_interrupt_allowed(vcpu)) {
3443 vmx->soft_vnmi_blocked = 0;
3444 } else if (vmx->vnmi_blocked_time > 1000000000LL &&
3445 vcpu->arch.nmi_pending) {
3446 /*
3447 * This CPU don't support us in finding the end of an
3448 * NMI-blocked window if the guest runs with IRQs
3449 * disabled. So we pull the trigger after 1 s of
3450 * futile waiting, but inform the user about this.
3451 */
3452 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
3453 "state on VCPU %d after 1 s timeout\n",
3454 __func__, vcpu->vcpu_id);
3455 vmx->soft_vnmi_blocked = 0;
3456 }
3457 }
3458
3459 if (exit_reason < kvm_vmx_max_exit_handlers
3460 && kvm_vmx_exit_handlers[exit_reason])
3461 return kvm_vmx_exit_handlers[exit_reason](vcpu, kvm_run);
3462 else {
3463 kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
3464 kvm_run->hw.hardware_exit_reason = exit_reason;
3465 }
3466 return 0;
3467 }
3468
3469 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3470 {
3471 if (irr == -1 || tpr < irr) {
3472 vmcs_write32(TPR_THRESHOLD, 0);
3473 return;
3474 }
3475
3476 vmcs_write32(TPR_THRESHOLD, irr);
3477 }
3478
3479 static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
3480 {
3481 u32 exit_intr_info;
3482 u32 idt_vectoring_info = vmx->idt_vectoring_info;
3483 bool unblock_nmi;
3484 u8 vector;
3485 int type;
3486 bool idtv_info_valid;
3487
3488 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
3489
3490 vmx->exit_reason = vmcs_read32(VM_EXIT_REASON);
3491
3492 /* Handle machine checks before interrupts are enabled */
3493 if ((vmx->exit_reason == EXIT_REASON_MCE_DURING_VMENTRY)
3494 || (vmx->exit_reason == EXIT_REASON_EXCEPTION_NMI
3495 && is_machine_check(exit_intr_info)))
3496 kvm_machine_check();
3497
3498 /* We need to handle NMIs before interrupts are enabled */
3499 if ((exit_intr_info & INTR_INFO_INTR_TYPE_MASK) == INTR_TYPE_NMI_INTR &&
3500 (exit_intr_info & INTR_INFO_VALID_MASK)) {
3501 KVMTRACE_0D(NMI, &vmx->vcpu, handler);
3502 asm("int $2");
3503 }
3504
3505 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
3506
3507 if (cpu_has_virtual_nmis()) {
3508 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
3509 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
3510 /*
3511 * SDM 3: 27.7.1.2 (September 2008)
3512 * Re-set bit "block by NMI" before VM entry if vmexit caused by
3513 * a guest IRET fault.
3514 * SDM 3: 23.2.2 (September 2008)
3515 * Bit 12 is undefined in any of the following cases:
3516 * If the VM exit sets the valid bit in the IDT-vectoring
3517 * information field.
3518 * If the VM exit is due to a double fault.
3519 */
3520 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
3521 vector != DF_VECTOR && !idtv_info_valid)
3522 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
3523 GUEST_INTR_STATE_NMI);
3524 } else if (unlikely(vmx->soft_vnmi_blocked))
3525 vmx->vnmi_blocked_time +=
3526 ktime_to_ns(ktime_sub(ktime_get(), vmx->entry_time));
3527
3528 vmx->vcpu.arch.nmi_injected = false;
3529 kvm_clear_exception_queue(&vmx->vcpu);
3530 kvm_clear_interrupt_queue(&vmx->vcpu);
3531
3532 if (!idtv_info_valid)
3533 return;
3534
3535 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
3536 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
3537
3538 switch (type) {
3539 case INTR_TYPE_NMI_INTR:
3540 vmx->vcpu.arch.nmi_injected = true;
3541 /*
3542 * SDM 3: 27.7.1.2 (September 2008)
3543 * Clear bit "block by NMI" before VM entry if a NMI
3544 * delivery faulted.
3545 */
3546 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
3547 GUEST_INTR_STATE_NMI);
3548 break;
3549 case INTR_TYPE_SOFT_EXCEPTION:
3550 vmx->vcpu.arch.event_exit_inst_len =
3551 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3552 /* fall through */
3553 case INTR_TYPE_HARD_EXCEPTION:
3554 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
3555 u32 err = vmcs_read32(IDT_VECTORING_ERROR_CODE);
3556 kvm_queue_exception_e(&vmx->vcpu, vector, err);
3557 } else
3558 kvm_queue_exception(&vmx->vcpu, vector);
3559 break;
3560 case INTR_TYPE_SOFT_INTR:
3561 vmx->vcpu.arch.event_exit_inst_len =
3562 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
3563 /* fall through */
3564 case INTR_TYPE_EXT_INTR:
3565 kvm_queue_interrupt(&vmx->vcpu, vector,
3566 type == INTR_TYPE_SOFT_INTR);
3567 break;
3568 default:
3569 break;
3570 }
3571 }
3572
3573 /*
3574 * Failure to inject an interrupt should give us the information
3575 * in IDT_VECTORING_INFO_FIELD. However, if the failure occurs
3576 * when fetching the interrupt redirection bitmap in the real-mode
3577 * tss, this doesn't happen. So we do it ourselves.
3578 */
3579 static void fixup_rmode_irq(struct vcpu_vmx *vmx)
3580 {
3581 vmx->rmode.irq.pending = 0;
3582 if (kvm_rip_read(&vmx->vcpu) + 1 != vmx->rmode.irq.rip)
3583 return;
3584 kvm_rip_write(&vmx->vcpu, vmx->rmode.irq.rip);
3585 if (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK) {
3586 vmx->idt_vectoring_info &= ~VECTORING_INFO_TYPE_MASK;
3587 vmx->idt_vectoring_info |= INTR_TYPE_EXT_INTR;
3588 return;
3589 }
3590 vmx->idt_vectoring_info =
3591 VECTORING_INFO_VALID_MASK
3592 | INTR_TYPE_EXT_INTR
3593 | vmx->rmode.irq.vector;
3594 }
3595
3596 #ifdef CONFIG_X86_64
3597 #define R "r"
3598 #define Q "q"
3599 #else
3600 #define R "e"
3601 #define Q "l"
3602 #endif
3603
3604 static void vmx_vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3605 {
3606 struct vcpu_vmx *vmx = to_vmx(vcpu);
3607
3608 if (enable_ept && is_paging(vcpu)) {
3609 vmcs_writel(GUEST_CR3, vcpu->arch.cr3);
3610 ept_load_pdptrs(vcpu);
3611 }
3612 /* Record the guest's net vcpu time for enforced NMI injections. */
3613 if (unlikely(!cpu_has_virtual_nmis() && vmx->soft_vnmi_blocked))
3614 vmx->entry_time = ktime_get();
3615
3616 /* Handle invalid guest state instead of entering VMX */
3617 if (vmx->emulation_required && emulate_invalid_guest_state) {
3618 handle_invalid_guest_state(vcpu, kvm_run);
3619 return;
3620 }
3621
3622 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
3623 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
3624 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
3625 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
3626
3627 /* When single-stepping over STI and MOV SS, we must clear the
3628 * corresponding interruptibility bits in the guest state. Otherwise
3629 * vmentry fails as it then expects bit 14 (BS) in pending debug
3630 * exceptions being set, but that's not correct for the guest debugging
3631 * case. */
3632 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
3633 vmx_set_interrupt_shadow(vcpu, 0);
3634
3635 /*
3636 * Loading guest fpu may have cleared host cr0.ts
3637 */
3638 vmcs_writel(HOST_CR0, read_cr0());
3639
3640 set_debugreg(vcpu->arch.dr6, 6);
3641
3642 asm(
3643 /* Store host registers */
3644 "push %%"R"dx; push %%"R"bp;"
3645 "push %%"R"cx \n\t"
3646 "cmp %%"R"sp, %c[host_rsp](%0) \n\t"
3647 "je 1f \n\t"
3648 "mov %%"R"sp, %c[host_rsp](%0) \n\t"
3649 __ex(ASM_VMX_VMWRITE_RSP_RDX) "\n\t"
3650 "1: \n\t"
3651 /* Check if vmlaunch of vmresume is needed */
3652 "cmpl $0, %c[launched](%0) \n\t"
3653 /* Load guest registers. Don't clobber flags. */
3654 "mov %c[cr2](%0), %%"R"ax \n\t"
3655 "mov %%"R"ax, %%cr2 \n\t"
3656 "mov %c[rax](%0), %%"R"ax \n\t"
3657 "mov %c[rbx](%0), %%"R"bx \n\t"
3658 "mov %c[rdx](%0), %%"R"dx \n\t"
3659 "mov %c[rsi](%0), %%"R"si \n\t"
3660 "mov %c[rdi](%0), %%"R"di \n\t"
3661 "mov %c[rbp](%0), %%"R"bp \n\t"
3662 #ifdef CONFIG_X86_64
3663 "mov %c[r8](%0), %%r8 \n\t"
3664 "mov %c[r9](%0), %%r9 \n\t"
3665 "mov %c[r10](%0), %%r10 \n\t"
3666 "mov %c[r11](%0), %%r11 \n\t"
3667 "mov %c[r12](%0), %%r12 \n\t"
3668 "mov %c[r13](%0), %%r13 \n\t"
3669 "mov %c[r14](%0), %%r14 \n\t"
3670 "mov %c[r15](%0), %%r15 \n\t"
3671 #endif
3672 "mov %c[rcx](%0), %%"R"cx \n\t" /* kills %0 (ecx) */
3673
3674 /* Enter guest mode */
3675 "jne .Llaunched \n\t"
3676 __ex(ASM_VMX_VMLAUNCH) "\n\t"
3677 "jmp .Lkvm_vmx_return \n\t"
3678 ".Llaunched: " __ex(ASM_VMX_VMRESUME) "\n\t"
3679 ".Lkvm_vmx_return: "
3680 /* Save guest registers, load host registers, keep flags */
3681 "xchg %0, (%%"R"sp) \n\t"
3682 "mov %%"R"ax, %c[rax](%0) \n\t"
3683 "mov %%"R"bx, %c[rbx](%0) \n\t"
3684 "push"Q" (%%"R"sp); pop"Q" %c[rcx](%0) \n\t"
3685 "mov %%"R"dx, %c[rdx](%0) \n\t"
3686 "mov %%"R"si, %c[rsi](%0) \n\t"
3687 "mov %%"R"di, %c[rdi](%0) \n\t"
3688 "mov %%"R"bp, %c[rbp](%0) \n\t"
3689 #ifdef CONFIG_X86_64
3690 "mov %%r8, %c[r8](%0) \n\t"
3691 "mov %%r9, %c[r9](%0) \n\t"
3692 "mov %%r10, %c[r10](%0) \n\t"
3693 "mov %%r11, %c[r11](%0) \n\t"
3694 "mov %%r12, %c[r12](%0) \n\t"
3695 "mov %%r13, %c[r13](%0) \n\t"
3696 "mov %%r14, %c[r14](%0) \n\t"
3697 "mov %%r15, %c[r15](%0) \n\t"
3698 #endif
3699 "mov %%cr2, %%"R"ax \n\t"
3700 "mov %%"R"ax, %c[cr2](%0) \n\t"
3701
3702 "pop %%"R"bp; pop %%"R"bp; pop %%"R"dx \n\t"
3703 "setbe %c[fail](%0) \n\t"
3704 : : "c"(vmx), "d"((unsigned long)HOST_RSP),
3705 [launched]"i"(offsetof(struct vcpu_vmx, launched)),
3706 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
3707 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
3708 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
3709 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
3710 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
3711 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
3712 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
3713 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
3714 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
3715 #ifdef CONFIG_X86_64
3716 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
3717 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
3718 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
3719 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
3720 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
3721 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
3722 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
3723 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
3724 #endif
3725 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2))
3726 : "cc", "memory"
3727 , R"bx", R"di", R"si"
3728 #ifdef CONFIG_X86_64
3729 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
3730 #endif
3731 );
3732
3733 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
3734 | (1 << VCPU_EXREG_PDPTR));
3735 vcpu->arch.regs_dirty = 0;
3736
3737 get_debugreg(vcpu->arch.dr6, 6);
3738
3739 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
3740 if (vmx->rmode.irq.pending)
3741 fixup_rmode_irq(vmx);
3742
3743 asm("mov %0, %%ds; mov %0, %%es" : : "r"(__USER_DS));
3744 vmx->launched = 1;
3745
3746 vmx_complete_interrupts(vmx);
3747 }
3748
3749 #undef R
3750 #undef Q
3751
3752 static void vmx_free_vmcs(struct kvm_vcpu *vcpu)
3753 {
3754 struct vcpu_vmx *vmx = to_vmx(vcpu);
3755
3756 if (vmx->vmcs) {
3757 vcpu_clear(vmx);
3758 free_vmcs(vmx->vmcs);
3759 vmx->vmcs = NULL;
3760 }
3761 }
3762
3763 static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
3764 {
3765 struct vcpu_vmx *vmx = to_vmx(vcpu);
3766
3767 spin_lock(&vmx_vpid_lock);
3768 if (vmx->vpid != 0)
3769 __clear_bit(vmx->vpid, vmx_vpid_bitmap);
3770 spin_unlock(&vmx_vpid_lock);
3771 vmx_free_vmcs(vcpu);
3772 kfree(vmx->host_msrs);
3773 kfree(vmx->guest_msrs);
3774 kvm_vcpu_uninit(vcpu);
3775 kmem_cache_free(kvm_vcpu_cache, vmx);
3776 }
3777
3778 static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
3779 {
3780 int err;
3781 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
3782 int cpu;
3783
3784 if (!vmx)
3785 return ERR_PTR(-ENOMEM);
3786
3787 allocate_vpid(vmx);
3788
3789 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
3790 if (err)
3791 goto free_vcpu;
3792
3793 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3794 if (!vmx->guest_msrs) {
3795 err = -ENOMEM;
3796 goto uninit_vcpu;
3797 }
3798
3799 vmx->host_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
3800 if (!vmx->host_msrs)
3801 goto free_guest_msrs;
3802
3803 vmx->vmcs = alloc_vmcs();
3804 if (!vmx->vmcs)
3805 goto free_msrs;
3806
3807 vmcs_clear(vmx->vmcs);
3808
3809 cpu = get_cpu();
3810 vmx_vcpu_load(&vmx->vcpu, cpu);
3811 err = vmx_vcpu_setup(vmx);
3812 vmx_vcpu_put(&vmx->vcpu);
3813 put_cpu();
3814 if (err)
3815 goto free_vmcs;
3816 if (vm_need_virtualize_apic_accesses(kvm))
3817 if (alloc_apic_access_page(kvm) != 0)
3818 goto free_vmcs;
3819
3820 if (enable_ept)
3821 if (alloc_identity_pagetable(kvm) != 0)
3822 goto free_vmcs;
3823
3824 return &vmx->vcpu;
3825
3826 free_vmcs:
3827 free_vmcs(vmx->vmcs);
3828 free_msrs:
3829 kfree(vmx->host_msrs);
3830 free_guest_msrs:
3831 kfree(vmx->guest_msrs);
3832 uninit_vcpu:
3833 kvm_vcpu_uninit(&vmx->vcpu);
3834 free_vcpu:
3835 kmem_cache_free(kvm_vcpu_cache, vmx);
3836 return ERR_PTR(err);
3837 }
3838
3839 static void __init vmx_check_processor_compat(void *rtn)
3840 {
3841 struct vmcs_config vmcs_conf;
3842
3843 *(int *)rtn = 0;
3844 if (setup_vmcs_config(&vmcs_conf) < 0)
3845 *(int *)rtn = -EIO;
3846 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
3847 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
3848 smp_processor_id());
3849 *(int *)rtn = -EIO;
3850 }
3851 }
3852
3853 static int get_ept_level(void)
3854 {
3855 return VMX_EPT_DEFAULT_GAW + 1;
3856 }
3857
3858 static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3859 {
3860 u64 ret;
3861
3862 /* For VT-d and EPT combination
3863 * 1. MMIO: always map as UC
3864 * 2. EPT with VT-d:
3865 * a. VT-d without snooping control feature: can't guarantee the
3866 * result, try to trust guest.
3867 * b. VT-d with snooping control feature: snooping control feature of
3868 * VT-d engine can guarantee the cache correctness. Just set it
3869 * to WB to keep consistent with host. So the same as item 3.
3870 * 3. EPT without VT-d: always map as WB and set IGMT=1 to keep
3871 * consistent with host MTRR
3872 */
3873 if (is_mmio)
3874 ret = MTRR_TYPE_UNCACHABLE << VMX_EPT_MT_EPTE_SHIFT;
3875 else if (vcpu->kvm->arch.iommu_domain &&
3876 !(vcpu->kvm->arch.iommu_flags & KVM_IOMMU_CACHE_COHERENCY))
3877 ret = kvm_get_guest_memory_type(vcpu, gfn) <<
3878 VMX_EPT_MT_EPTE_SHIFT;
3879 else
3880 ret = (MTRR_TYPE_WRBACK << VMX_EPT_MT_EPTE_SHIFT)
3881 | VMX_EPT_IGMT_BIT;
3882
3883 return ret;
3884 }
3885
3886 static struct kvm_x86_ops vmx_x86_ops = {
3887 .cpu_has_kvm_support = cpu_has_kvm_support,
3888 .disabled_by_bios = vmx_disabled_by_bios,
3889 .hardware_setup = hardware_setup,
3890 .hardware_unsetup = hardware_unsetup,
3891 .check_processor_compatibility = vmx_check_processor_compat,
3892 .hardware_enable = hardware_enable,
3893 .hardware_disable = hardware_disable,
3894 .cpu_has_accelerated_tpr = report_flexpriority,
3895
3896 .vcpu_create = vmx_create_vcpu,
3897 .vcpu_free = vmx_free_vcpu,
3898 .vcpu_reset = vmx_vcpu_reset,
3899
3900 .prepare_guest_switch = vmx_save_host_state,
3901 .vcpu_load = vmx_vcpu_load,
3902 .vcpu_put = vmx_vcpu_put,
3903
3904 .set_guest_debug = set_guest_debug,
3905 .get_msr = vmx_get_msr,
3906 .set_msr = vmx_set_msr,
3907 .get_segment_base = vmx_get_segment_base,
3908 .get_segment = vmx_get_segment,
3909 .set_segment = vmx_set_segment,
3910 .get_cpl = vmx_get_cpl,
3911 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
3912 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
3913 .set_cr0 = vmx_set_cr0,
3914 .set_cr3 = vmx_set_cr3,
3915 .set_cr4 = vmx_set_cr4,
3916 .set_efer = vmx_set_efer,
3917 .get_idt = vmx_get_idt,
3918 .set_idt = vmx_set_idt,
3919 .get_gdt = vmx_get_gdt,
3920 .set_gdt = vmx_set_gdt,
3921 .cache_reg = vmx_cache_reg,
3922 .get_rflags = vmx_get_rflags,
3923 .set_rflags = vmx_set_rflags,
3924
3925 .tlb_flush = vmx_flush_tlb,
3926
3927 .run = vmx_vcpu_run,
3928 .handle_exit = vmx_handle_exit,
3929 .skip_emulated_instruction = skip_emulated_instruction,
3930 .set_interrupt_shadow = vmx_set_interrupt_shadow,
3931 .get_interrupt_shadow = vmx_get_interrupt_shadow,
3932 .patch_hypercall = vmx_patch_hypercall,
3933 .set_irq = vmx_inject_irq,
3934 .set_nmi = vmx_inject_nmi,
3935 .queue_exception = vmx_queue_exception,
3936 .interrupt_allowed = vmx_interrupt_allowed,
3937 .nmi_allowed = vmx_nmi_allowed,
3938 .enable_nmi_window = enable_nmi_window,
3939 .enable_irq_window = enable_irq_window,
3940 .update_cr8_intercept = update_cr8_intercept,
3941
3942 .set_tss_addr = vmx_set_tss_addr,
3943 .get_tdp_level = get_ept_level,
3944 .get_mt_mask = vmx_get_mt_mask,
3945 };
3946
3947 static int __init vmx_init(void)
3948 {
3949 int r;
3950
3951 vmx_io_bitmap_a = (unsigned long *)__get_free_page(GFP_KERNEL);
3952 if (!vmx_io_bitmap_a)
3953 return -ENOMEM;
3954
3955 vmx_io_bitmap_b = (unsigned long *)__get_free_page(GFP_KERNEL);
3956 if (!vmx_io_bitmap_b) {
3957 r = -ENOMEM;
3958 goto out;
3959 }
3960
3961 vmx_msr_bitmap_legacy = (unsigned long *)__get_free_page(GFP_KERNEL);
3962 if (!vmx_msr_bitmap_legacy) {
3963 r = -ENOMEM;
3964 goto out1;
3965 }
3966
3967 vmx_msr_bitmap_longmode = (unsigned long *)__get_free_page(GFP_KERNEL);
3968 if (!vmx_msr_bitmap_longmode) {
3969 r = -ENOMEM;
3970 goto out2;
3971 }
3972
3973 /*
3974 * Allow direct access to the PC debug port (it is often used for I/O
3975 * delays, but the vmexits simply slow things down).
3976 */
3977 memset(vmx_io_bitmap_a, 0xff, PAGE_SIZE);
3978 clear_bit(0x80, vmx_io_bitmap_a);
3979
3980 memset(vmx_io_bitmap_b, 0xff, PAGE_SIZE);
3981
3982 memset(vmx_msr_bitmap_legacy, 0xff, PAGE_SIZE);
3983 memset(vmx_msr_bitmap_longmode, 0xff, PAGE_SIZE);
3984
3985 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
3986
3987 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx), THIS_MODULE);
3988 if (r)
3989 goto out3;
3990
3991 vmx_disable_intercept_for_msr(MSR_FS_BASE, false);
3992 vmx_disable_intercept_for_msr(MSR_GS_BASE, false);
3993 vmx_disable_intercept_for_msr(MSR_KERNEL_GS_BASE, true);
3994 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_CS, false);
3995 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_ESP, false);
3996 vmx_disable_intercept_for_msr(MSR_IA32_SYSENTER_EIP, false);
3997
3998 if (enable_ept) {
3999 bypass_guest_pf = 0;
4000 kvm_mmu_set_base_ptes(VMX_EPT_READABLE_MASK |
4001 VMX_EPT_WRITABLE_MASK);
4002 kvm_mmu_set_mask_ptes(0ull, 0ull, 0ull, 0ull,
4003 VMX_EPT_EXECUTABLE_MASK);
4004 kvm_enable_tdp();
4005 } else
4006 kvm_disable_tdp();
4007
4008 if (bypass_guest_pf)
4009 kvm_mmu_set_nonpresent_ptes(~0xffeull, 0ull);
4010
4011 ept_sync_global();
4012
4013 return 0;
4014
4015 out3:
4016 free_page((unsigned long)vmx_msr_bitmap_longmode);
4017 out2:
4018 free_page((unsigned long)vmx_msr_bitmap_legacy);
4019 out1:
4020 free_page((unsigned long)vmx_io_bitmap_b);
4021 out:
4022 free_page((unsigned long)vmx_io_bitmap_a);
4023 return r;
4024 }
4025
4026 static void __exit vmx_exit(void)
4027 {
4028 free_page((unsigned long)vmx_msr_bitmap_legacy);
4029 free_page((unsigned long)vmx_msr_bitmap_longmode);
4030 free_page((unsigned long)vmx_io_bitmap_b);
4031 free_page((unsigned long)vmx_io_bitmap_a);
4032
4033 kvm_exit();
4034 }
4035
4036 module_init(vmx_init)
4037 module_exit(vmx_exit)
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