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i2c: move OF helpers into the core
[linux-2.6/btrfs-unstable.git] / drivers / i2c / busses / i2c-mpc.c
blobf4060939e9593874e743a1406aa1d51f097984dd
1 /*
2 * (C) Copyright 2003-2004
3 * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
4
5 * This is a combined i2c adapter and algorithm driver for the
6 * MPC107/Tsi107 PowerPC northbridge and processors that include
7 * the same I2C unit (8240, 8245, 85xx).
8 *
9 * Release 0.8
10 *
11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/sched.h>
19 #include <linux/init.h>
20 #include <linux/of_platform.h>
21 #include <linux/slab.h>
22
23 #include <linux/io.h>
24 #include <linux/fsl_devices.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
27 #include <linux/delay.h>
28
29 #include <asm/mpc52xx.h>
30 #include <sysdev/fsl_soc.h>
31
32 #define DRV_NAME "mpc-i2c"
33
34 #define MPC_I2C_CLOCK_LEGACY 0
35 #define MPC_I2C_CLOCK_PRESERVE (~0U)
36
37 #define MPC_I2C_FDR 0x04
38 #define MPC_I2C_CR 0x08
39 #define MPC_I2C_SR 0x0c
40 #define MPC_I2C_DR 0x10
41 #define MPC_I2C_DFSRR 0x14
42
43 #define CCR_MEN 0x80
44 #define CCR_MIEN 0x40
45 #define CCR_MSTA 0x20
46 #define CCR_MTX 0x10
47 #define CCR_TXAK 0x08
48 #define CCR_RSTA 0x04
49
50 #define CSR_MCF 0x80
51 #define CSR_MAAS 0x40
52 #define CSR_MBB 0x20
53 #define CSR_MAL 0x10
54 #define CSR_SRW 0x04
55 #define CSR_MIF 0x02
56 #define CSR_RXAK 0x01
57
58 struct mpc_i2c {
59 struct device *dev;
60 void __iomem *base;
61 u32 interrupt;
62 wait_queue_head_t queue;
63 struct i2c_adapter adap;
64 int irq;
65 u32 real_clk;
66 #ifdef CONFIG_PM_SLEEP
67 u8 fdr, dfsrr;
68 #endif
69 };
70
71 struct mpc_i2c_divider {
72 u16 divider;
73 u16 fdr; /* including dfsrr */
74 };
75
76 struct mpc_i2c_data {
77 void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
78 u32 clock, u32 prescaler);
79 u32 prescaler;
80 };
81
82 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
83 {
84 writeb(x, i2c->base + MPC_I2C_CR);
85 }
86
87 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
88 {
89 struct mpc_i2c *i2c = dev_id;
90 if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
91 /* Read again to allow register to stabilise */
92 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
93 writeb(0, i2c->base + MPC_I2C_SR);
94 wake_up(&i2c->queue);
95 }
96 return IRQ_HANDLED;
97 }
98
99 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
100 * the bus, because it wants to send ACK.
101 * Following sequence of enabling/disabling and sending start/stop generates
102 * the 9 pulses, so it's all OK.
103 */
104 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
105 {
106 int k;
107 u32 delay_val = 1000000 / i2c->real_clk + 1;
108
109 if (delay_val < 2)
110 delay_val = 2;
111
112 for (k = 9; k; k--) {
113 writeccr(i2c, 0);
114 writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
115 udelay(delay_val);
116 writeccr(i2c, CCR_MEN);
117 udelay(delay_val << 1);
118 }
119 }
120
121 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
122 {
123 unsigned long orig_jiffies = jiffies;
124 u32 x;
125 int result = 0;
126
127 if (!i2c->irq) {
128 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
129 schedule();
130 if (time_after(jiffies, orig_jiffies + timeout)) {
131 dev_dbg(i2c->dev, "timeout\n");
132 writeccr(i2c, 0);
133 result = -EIO;
134 break;
135 }
136 }
137 x = readb(i2c->base + MPC_I2C_SR);
138 writeb(0, i2c->base + MPC_I2C_SR);
139 } else {
140 /* Interrupt mode */
141 result = wait_event_timeout(i2c->queue,
142 (i2c->interrupt & CSR_MIF), timeout);
143
144 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
145 dev_dbg(i2c->dev, "wait timeout\n");
146 writeccr(i2c, 0);
147 result = -ETIMEDOUT;
148 }
149
150 x = i2c->interrupt;
151 i2c->interrupt = 0;
152 }
153
154 if (result < 0)
155 return result;
156
157 if (!(x & CSR_MCF)) {
158 dev_dbg(i2c->dev, "unfinished\n");
159 return -EIO;
160 }
161
162 if (x & CSR_MAL) {
163 dev_dbg(i2c->dev, "MAL\n");
164 return -EIO;
165 }
166
167 if (writing && (x & CSR_RXAK)) {
168 dev_dbg(i2c->dev, "No RXAK\n");
169 /* generate stop */
170 writeccr(i2c, CCR_MEN);
171 return -EIO;
172 }
173 return 0;
174 }
175
176 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
177 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] = {
178 {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
179 {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
180 {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
181 {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
182 {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
183 {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
184 {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
185 {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
186 {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
187 {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
188 {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
189 {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
190 {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
191 {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
192 {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
193 {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
194 {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
195 {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
196 };
197
198 static int mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
199 int prescaler, u32 *real_clk)
200 {
201 const struct mpc_i2c_divider *div = NULL;
202 unsigned int pvr = mfspr(SPRN_PVR);
203 u32 divider;
204 int i;
205
206 if (clock == MPC_I2C_CLOCK_LEGACY) {
207 /* see below - default fdr = 0x3f -> div = 2048 */
208 *real_clk = mpc5xxx_get_bus_frequency(node) / 2048;
209 return -EINVAL;
210 }
211
212 /* Determine divider value */
213 divider = mpc5xxx_get_bus_frequency(node) / clock;
214
215 /*
216 * We want to choose an FDR/DFSR that generates an I2C bus speed that
217 * is equal to or lower than the requested speed.
218 */
219 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
220 div = &mpc_i2c_dividers_52xx[i];
221 /* Old MPC5200 rev A CPUs do not support the high bits */
222 if (div->fdr & 0xc0 && pvr == 0x80822011)
223 continue;
224 if (div->divider >= divider)
225 break;
226 }
227
228 *real_clk = mpc5xxx_get_bus_frequency(node) / div->divider;
229 return (int)div->fdr;
230 }
231
232 static void mpc_i2c_setup_52xx(struct device_node *node,
233 struct mpc_i2c *i2c,
234 u32 clock, u32 prescaler)
235 {
236 int ret, fdr;
237
238 if (clock == MPC_I2C_CLOCK_PRESERVE) {
239 dev_dbg(i2c->dev, "using fdr %d\n",
240 readb(i2c->base + MPC_I2C_FDR));
241 return;
242 }
243
244 ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler, &i2c->real_clk);
245 fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
246
247 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
248
249 if (ret >= 0)
250 dev_info(i2c->dev, "clock %u Hz (fdr=%d)\n", i2c->real_clk,
251 fdr);
252 }
253 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
254 static void mpc_i2c_setup_52xx(struct device_node *node,
255 struct mpc_i2c *i2c,
256 u32 clock, u32 prescaler)
257 {
258 }
259 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
260
261 #ifdef CONFIG_PPC_MPC512x
262 static void mpc_i2c_setup_512x(struct device_node *node,
263 struct mpc_i2c *i2c,
264 u32 clock, u32 prescaler)
265 {
266 struct device_node *node_ctrl;
267 void __iomem *ctrl;
268 const u32 *pval;
269 u32 idx;
270
271 /* Enable I2C interrupts for mpc5121 */
272 node_ctrl = of_find_compatible_node(NULL, NULL,
273 "fsl,mpc5121-i2c-ctrl");
274 if (node_ctrl) {
275 ctrl = of_iomap(node_ctrl, 0);
276 if (ctrl) {
277 /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
278 pval = of_get_property(node, "reg", NULL);
279 idx = (*pval & 0xff) / 0x20;
280 setbits32(ctrl, 1 << (24 + idx * 2));
281 iounmap(ctrl);
282 }
283 of_node_put(node_ctrl);
284 }
285
286 /* The clock setup for the 52xx works also fine for the 512x */
287 mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
288 }
289 #else /* CONFIG_PPC_MPC512x */
290 static void mpc_i2c_setup_512x(struct device_node *node,
291 struct mpc_i2c *i2c,
292 u32 clock, u32 prescaler)
293 {
294 }
295 #endif /* CONFIG_PPC_MPC512x */
296
297 #ifdef CONFIG_FSL_SOC
298 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] = {
299 {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
300 {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
301 {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
302 {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
303 {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
304 {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
305 {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
306 {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
307 {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
308 {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
309 {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
310 {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
311 {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
312 {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
313 {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
314 {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
315 {49152, 0x011e}, {61440, 0x011f}
316 };
317
318 static u32 mpc_i2c_get_sec_cfg_8xxx(void)
319 {
320 struct device_node *node = NULL;
321 u32 __iomem *reg;
322 u32 val = 0;
323
324 node = of_find_node_by_name(NULL, "global-utilities");
325 if (node) {
326 const u32 *prop = of_get_property(node, "reg", NULL);
327 if (prop) {
328 /*
329 * Map and check POR Device Status Register 2
330 * (PORDEVSR2) at 0xE0014
331 */
332 reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
333 if (!reg)
334 printk(KERN_ERR
335 "Error: couldn't map PORDEVSR2\n");
336 else
337 val = in_be32(reg) & 0x00000080; /* sec-cfg */
338 iounmap(reg);
339 }
340 }
341 if (node)
342 of_node_put(node);
343
344 return val;
345 }
346
347 static int mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
348 u32 prescaler, u32 *real_clk)
349 {
350 const struct mpc_i2c_divider *div = NULL;
351 u32 divider;
352 int i;
353
354 if (clock == MPC_I2C_CLOCK_LEGACY) {
355 /* see below - default fdr = 0x1031 -> div = 16 * 3072 */
356 *real_clk = fsl_get_sys_freq() / prescaler / (16 * 3072);
357 return -EINVAL;
358 }
359
360 /* Determine proper divider value */
361 if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
362 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
363 if (!prescaler)
364 prescaler = 1;
365
366 divider = fsl_get_sys_freq() / clock / prescaler;
367
368 pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
369 fsl_get_sys_freq(), clock, divider);
370
371 /*
372 * We want to choose an FDR/DFSR that generates an I2C bus speed that
373 * is equal to or lower than the requested speed.
374 */
375 for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
376 div = &mpc_i2c_dividers_8xxx[i];
377 if (div->divider >= divider)
378 break;
379 }
380
381 *real_clk = fsl_get_sys_freq() / prescaler / div->divider;
382 return div ? (int)div->fdr : -EINVAL;
383 }
384
385 static void mpc_i2c_setup_8xxx(struct device_node *node,
386 struct mpc_i2c *i2c,
387 u32 clock, u32 prescaler)
388 {
389 int ret, fdr;
390
391 if (clock == MPC_I2C_CLOCK_PRESERVE) {
392 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
393 readb(i2c->base + MPC_I2C_DFSRR),
394 readb(i2c->base + MPC_I2C_FDR));
395 return;
396 }
397
398 ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler, &i2c->real_clk);
399 fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
400
401 writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
402 writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
403
404 if (ret >= 0)
405 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
406 i2c->real_clk, fdr >> 8, fdr & 0xff);
407 }
408
409 #else /* !CONFIG_FSL_SOC */
410 static void mpc_i2c_setup_8xxx(struct device_node *node,
411 struct mpc_i2c *i2c,
412 u32 clock, u32 prescaler)
413 {
414 }
415 #endif /* CONFIG_FSL_SOC */
416
417 static void mpc_i2c_start(struct mpc_i2c *i2c)
418 {
419 /* Clear arbitration */
420 writeb(0, i2c->base + MPC_I2C_SR);
421 /* Start with MEN */
422 writeccr(i2c, CCR_MEN);
423 }
424
425 static void mpc_i2c_stop(struct mpc_i2c *i2c)
426 {
427 writeccr(i2c, CCR_MEN);
428 }
429
430 static int mpc_write(struct mpc_i2c *i2c, int target,
431 const u8 *data, int length, int restart)
432 {
433 int i, result;
434 unsigned timeout = i2c->adap.timeout;
435 u32 flags = restart ? CCR_RSTA : 0;
436
437 /* Start as master */
438 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
439 /* Write target byte */
440 writeb((target << 1), i2c->base + MPC_I2C_DR);
441
442 result = i2c_wait(i2c, timeout, 1);
443 if (result < 0)
444 return result;
445
446 for (i = 0; i < length; i++) {
447 /* Write data byte */
448 writeb(data[i], i2c->base + MPC_I2C_DR);
449
450 result = i2c_wait(i2c, timeout, 1);
451 if (result < 0)
452 return result;
453 }
454
455 return 0;
456 }
457
458 static int mpc_read(struct mpc_i2c *i2c, int target,
459 u8 *data, int length, int restart, bool recv_len)
460 {
461 unsigned timeout = i2c->adap.timeout;
462 int i, result;
463 u32 flags = restart ? CCR_RSTA : 0;
464
465 /* Switch to read - restart */
466 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
467 /* Write target address byte - this time with the read flag set */
468 writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
469
470 result = i2c_wait(i2c, timeout, 1);
471 if (result < 0)
472 return result;
473
474 if (length) {
475 if (length == 1 && !recv_len)
476 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
477 else
478 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
479 /* Dummy read */
480 readb(i2c->base + MPC_I2C_DR);
481 }
482
483 for (i = 0; i < length; i++) {
484 u8 byte;
485
486 result = i2c_wait(i2c, timeout, 0);
487 if (result < 0)
488 return result;
489
490 /*
491 * For block reads, we have to know the total length (1st byte)
492 * before we can determine if we are done.
493 */
494 if (i || !recv_len) {
495 /* Generate txack on next to last byte */
496 if (i == length - 2)
497 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
498 | CCR_TXAK);
499 /* Do not generate stop on last byte */
500 if (i == length - 1)
501 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
502 | CCR_MTX);
503 }
504
505 byte = readb(i2c->base + MPC_I2C_DR);
506
507 /*
508 * Adjust length if first received byte is length.
509 * The length is 1 length byte plus actually data length
510 */
511 if (i == 0 && recv_len) {
512 if (byte == 0 || byte > I2C_SMBUS_BLOCK_MAX)
513 return -EPROTO;
514 length += byte;
515 /*
516 * For block reads, generate txack here if data length
517 * is 1 byte (total length is 2 bytes).
518 */
519 if (length == 2)
520 writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA
521 | CCR_TXAK);
522 }
523 data[i] = byte;
524 }
525
526 return length;
527 }
528
529 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
530 {
531 struct i2c_msg *pmsg;
532 int i;
533 int ret = 0;
534 unsigned long orig_jiffies = jiffies;
535 struct mpc_i2c *i2c = i2c_get_adapdata(adap);
536
537 mpc_i2c_start(i2c);
538
539 /* Allow bus up to 1s to become not busy */
540 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
541 if (signal_pending(current)) {
542 dev_dbg(i2c->dev, "Interrupted\n");
543 writeccr(i2c, 0);
544 return -EINTR;
545 }
546 if (time_after(jiffies, orig_jiffies + HZ)) {
547 u8 status = readb(i2c->base + MPC_I2C_SR);
548
549 dev_dbg(i2c->dev, "timeout\n");
550 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
551 writeb(status & ~CSR_MAL,
552 i2c->base + MPC_I2C_SR);
553 mpc_i2c_fixup(i2c);
554 }
555 return -EIO;
556 }
557 schedule();
558 }
559
560 for (i = 0; ret >= 0 && i < num; i++) {
561 pmsg = &msgs[i];
562 dev_dbg(i2c->dev,
563 "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
564 pmsg->flags & I2C_M_RD ? "read" : "write",
565 pmsg->len, pmsg->addr, i + 1, num);
566 if (pmsg->flags & I2C_M_RD) {
567 bool recv_len = pmsg->flags & I2C_M_RECV_LEN;
568
569 ret = mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i,
570 recv_len);
571 if (recv_len && ret > 0)
572 pmsg->len = ret;
573 } else {
574 ret =
575 mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
576 }
577 }
578 mpc_i2c_stop(i2c); /* Initiate STOP */
579 orig_jiffies = jiffies;
580 /* Wait until STOP is seen, allow up to 1 s */
581 while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
582 if (time_after(jiffies, orig_jiffies + HZ)) {
583 u8 status = readb(i2c->base + MPC_I2C_SR);
584
585 dev_dbg(i2c->dev, "timeout\n");
586 if ((status & (CSR_MCF | CSR_MBB | CSR_RXAK)) != 0) {
587 writeb(status & ~CSR_MAL,
588 i2c->base + MPC_I2C_SR);
589 mpc_i2c_fixup(i2c);
590 }
591 return -EIO;
592 }
593 cond_resched();
594 }
595 return (ret < 0) ? ret : num;
596 }
597
598 static u32 mpc_functionality(struct i2c_adapter *adap)
599 {
600 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
601 | I2C_FUNC_SMBUS_READ_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL;
602 }
603
604 static const struct i2c_algorithm mpc_algo = {
605 .master_xfer = mpc_xfer,
606 .functionality = mpc_functionality,
607 };
608
609 static struct i2c_adapter mpc_ops = {
610 .owner = THIS_MODULE,
611 .algo = &mpc_algo,
612 .timeout = HZ,
613 };
614
615 static const struct of_device_id mpc_i2c_of_match[];
616 static int fsl_i2c_probe(struct platform_device *op)
617 {
618 const struct of_device_id *match;
619 struct mpc_i2c *i2c;
620 const u32 *prop;
621 u32 clock = MPC_I2C_CLOCK_LEGACY;
622 int result = 0;
623 int plen;
624 struct resource res;
625
626 match = of_match_device(mpc_i2c_of_match, &op->dev);
627 if (!match)
628 return -EINVAL;
629
630 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
631 if (!i2c)
632 return -ENOMEM;
633
634 i2c->dev = &op->dev; /* for debug and error output */
635
636 init_waitqueue_head(&i2c->queue);
637
638 i2c->base = of_iomap(op->dev.of_node, 0);
639 if (!i2c->base) {
640 dev_err(i2c->dev, "failed to map controller\n");
641 result = -ENOMEM;
642 goto fail_map;
643 }
644
645 i2c->irq = irq_of_parse_and_map(op->dev.of_node, 0);
646 if (i2c->irq) { /* no i2c->irq implies polling */
647 result = request_irq(i2c->irq, mpc_i2c_isr,
648 IRQF_SHARED, "i2c-mpc", i2c);
649 if (result < 0) {
650 dev_err(i2c->dev, "failed to attach interrupt\n");
651 goto fail_request;
652 }
653 }
654
655 if (of_get_property(op->dev.of_node, "fsl,preserve-clocking", NULL)) {
656 clock = MPC_I2C_CLOCK_PRESERVE;
657 } else {
658 prop = of_get_property(op->dev.of_node, "clock-frequency",
659 &plen);
660 if (prop && plen == sizeof(u32))
661 clock = *prop;
662 }
663
664 if (match->data) {
665 const struct mpc_i2c_data *data = match->data;
666 data->setup(op->dev.of_node, i2c, clock, data->prescaler);
667 } else {
668 /* Backwards compatibility */
669 if (of_get_property(op->dev.of_node, "dfsrr", NULL))
670 mpc_i2c_setup_8xxx(op->dev.of_node, i2c, clock, 0);
671 }
672
673 prop = of_get_property(op->dev.of_node, "fsl,timeout", &plen);
674 if (prop && plen == sizeof(u32)) {
675 mpc_ops.timeout = *prop * HZ / 1000000;
676 if (mpc_ops.timeout < 5)
677 mpc_ops.timeout = 5;
678 }
679 dev_info(i2c->dev, "timeout %u us\n", mpc_ops.timeout * 1000000 / HZ);
680
681 platform_set_drvdata(op, i2c);
682
683 i2c->adap = mpc_ops;
684 of_address_to_resource(op->dev.of_node, 0, &res);
685 scnprintf(i2c->adap.name, sizeof(i2c->adap.name),
686 "MPC adapter at 0x%llx", (unsigned long long)res.start);
687 i2c_set_adapdata(&i2c->adap, i2c);
688 i2c->adap.dev.parent = &op->dev;
689 i2c->adap.dev.of_node = of_node_get(op->dev.of_node);
690
691 result = i2c_add_adapter(&i2c->adap);
692 if (result < 0) {
693 dev_err(i2c->dev, "failed to add adapter\n");
694 goto fail_add;
695 }
696
697 return result;
698
699 fail_add:
700 free_irq(i2c->irq, i2c);
701 fail_request:
702 irq_dispose_mapping(i2c->irq);
703 iounmap(i2c->base);
704 fail_map:
705 kfree(i2c);
706 return result;
707 };
708
709 static int fsl_i2c_remove(struct platform_device *op)
710 {
711 struct mpc_i2c *i2c = platform_get_drvdata(op);
712
713 i2c_del_adapter(&i2c->adap);
714
715 if (i2c->irq)
716 free_irq(i2c->irq, i2c);
717
718 irq_dispose_mapping(i2c->irq);
719 iounmap(i2c->base);
720 kfree(i2c);
721 return 0;
722 };
723
724 #ifdef CONFIG_PM_SLEEP
725 static int mpc_i2c_suspend(struct device *dev)
726 {
727 struct mpc_i2c *i2c = dev_get_drvdata(dev);
728
729 i2c->fdr = readb(i2c->base + MPC_I2C_FDR);
730 i2c->dfsrr = readb(i2c->base + MPC_I2C_DFSRR);
731
732 return 0;
733 }
734
735 static int mpc_i2c_resume(struct device *dev)
736 {
737 struct mpc_i2c *i2c = dev_get_drvdata(dev);
738
739 writeb(i2c->fdr, i2c->base + MPC_I2C_FDR);
740 writeb(i2c->dfsrr, i2c->base + MPC_I2C_DFSRR);
741
742 return 0;
743 }
744
745 static SIMPLE_DEV_PM_OPS(mpc_i2c_pm_ops, mpc_i2c_suspend, mpc_i2c_resume);
746 #define MPC_I2C_PM_OPS (&mpc_i2c_pm_ops)
747 #else
748 #define MPC_I2C_PM_OPS NULL
749 #endif
750
751 static const struct mpc_i2c_data mpc_i2c_data_512x = {
752 .setup = mpc_i2c_setup_512x,
753 };
754
755 static const struct mpc_i2c_data mpc_i2c_data_52xx = {
756 .setup = mpc_i2c_setup_52xx,
757 };
758
759 static const struct mpc_i2c_data mpc_i2c_data_8313 = {
760 .setup = mpc_i2c_setup_8xxx,
761 };
762
763 static const struct mpc_i2c_data mpc_i2c_data_8543 = {
764 .setup = mpc_i2c_setup_8xxx,
765 .prescaler = 2,
766 };
767
768 static const struct mpc_i2c_data mpc_i2c_data_8544 = {
769 .setup = mpc_i2c_setup_8xxx,
770 .prescaler = 3,
771 };
772
773 static const struct of_device_id mpc_i2c_of_match[] = {
774 {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
775 {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
776 {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
777 {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
778 {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
779 {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
780 {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
781 /* Backward compatibility */
782 {.compatible = "fsl-i2c", },
783 {},
784 };
785 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
786
787 /* Structure for a device driver */
788 static struct platform_driver mpc_i2c_driver = {
789 .probe = fsl_i2c_probe,
790 .remove = fsl_i2c_remove,
791 .driver = {
792 .owner = THIS_MODULE,
793 .name = DRV_NAME,
794 .of_match_table = mpc_i2c_of_match,
795 .pm = MPC_I2C_PM_OPS,
796 },
797 };
798
799 module_platform_driver(mpc_i2c_driver);
800
801 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
802 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
803 "MPC824x/83xx/85xx/86xx/512x/52xx processors");
804 MODULE_LICENSE("GPL");
(deprecated) Btrfs devel tree