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Staging: et131x: kill RX_DMA_MAX_PKT_TIME
[linux-2.6/btrfs-unstable.git] / drivers / staging / et131x / et1310_address_map.h
blobc447e9a3ed929b9ea909ec9dc53b4eaef3c9f725
1 /*
2 * Agere Systems Inc.
3 * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
4 *
5 * Copyright © 2005 Agere Systems Inc.
6 * All rights reserved.
7 * http://www.agere.com
8 *
9 *------------------------------------------------------------------------------
10 *
11 * et1310_address_map.h - Contains the register mapping for the ET1310
12 *
13 *------------------------------------------------------------------------------
14 *
15 * SOFTWARE LICENSE
16 *
17 * This software is provided subject to the following terms and conditions,
18 * which you should read carefully before using the software. Using this
19 * software indicates your acceptance of these terms and conditions. If you do
20 * not agree with these terms and conditions, do not use the software.
21 *
22 * Copyright © 2005 Agere Systems Inc.
23 * All rights reserved.
24 *
25 * Redistribution and use in source or binary forms, with or without
26 * modifications, are permitted provided that the following conditions are met:
27 *
28 * . Redistributions of source code must retain the above copyright notice, this
29 * list of conditions and the following Disclaimer as comments in the code as
30 * well as in the documentation and/or other materials provided with the
31 * distribution.
32 *
33 * . Redistributions in binary form must reproduce the above copyright notice,
34 * this list of conditions and the following Disclaimer in the documentation
35 * and/or other materials provided with the distribution.
36 *
37 * . Neither the name of Agere Systems Inc. nor the names of the contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * Disclaimer
42 *
43 * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
44 * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
45 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
46 * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
47 * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
48 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
49 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
50 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
51 * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
53 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
54 * DAMAGE.
55 *
56 */
57
58 #ifndef _ET1310_ADDRESS_MAP_H_
59 #define _ET1310_ADDRESS_MAP_H_
60
61
62 /* START OF GLOBAL REGISTER ADDRESS MAP */
63
64 /*
65 * 10bit registers
66 *
67 * Tx queue start address reg in global address map at address 0x0000
68 * tx queue end address reg in global address map at address 0x0004
69 * rx queue start address reg in global address map at address 0x0008
70 * rx queue end address reg in global address map at address 0x000C
71 */
72
73 /*
74 * structure for power management control status reg in global address map
75 * located at address 0x0010
76 * jagcore_rx_rdy bit 9
77 * jagcore_tx_rdy bit 8
78 * phy_lped_en bit 7
79 * phy_sw_coma bit 6
80 * rxclk_gate bit 5
81 * txclk_gate bit 4
82 * sysclk_gate bit 3
83 * jagcore_rx_en bit 2
84 * jagcore_tx_en bit 1
85 * gigephy_en bit 0
86 */
87
88 #define ET_PM_PHY_SW_COMA 0x40
89 #define ET_PMCSR_INIT 0x38
90
91 /*
92 * Interrupt status reg at address 0x0018
93 */
94
95 #define ET_INTR_TXDMA_ISR 0x00000008
96 #define ET_INTR_TXDMA_ERR 0x00000010
97 #define ET_INTR_RXDMA_XFR_DONE 0x00000020
98 #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
99 #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
100 #define ET_INTR_RXDMA_STAT_LOW 0x00000100
101 #define ET_INTR_RXDMA_ERR 0x00000200
102 #define ET_INTR_WATCHDOG 0x00004000
103 #define ET_INTR_WOL 0x00008000
104 #define ET_INTR_PHY 0x00010000
105 #define ET_INTR_TXMAC 0x00020000
106 #define ET_INTR_RXMAC 0x00040000
107 #define ET_INTR_MAC_STAT 0x00080000
108 #define ET_INTR_SLV_TIMEOUT 0x00100000
109
110 /*
111 * Interrupt mask register at address 0x001C
112 * Interrupt alias clear mask reg at address 0x0020
113 * Interrupt status alias reg at address 0x0024
114 *
115 * Same masks as above
116 */
117
118 /*
119 * Software reset reg at address 0x0028
120 * 0: txdma_sw_reset
121 * 1: rxdma_sw_reset
122 * 2: txmac_sw_reset
123 * 3: rxmac_sw_reset
124 * 4: mac_sw_reset
125 * 5: mac_stat_sw_reset
126 * 6: mmc_sw_reset
127 *31: selfclr_disable
128 */
129
130 /*
131 * SLV Timer reg at address 0x002C (low 24 bits)
132 */
133
134 /*
135 * MSI Configuration reg at address 0x0030
136 */
137
138 #define ET_MSI_VECTOR 0x0000001F
139 #define ET_MSI_TC 0x00070000
140
141 /*
142 * Loopback reg located at address 0x0034
143 */
144
145 #define ET_LOOP_MAC 0x00000001
146 #define ET_LOOP_DMA 0x00000002
147
148 /*
149 * GLOBAL Module of JAGCore Address Mapping
150 * Located at address 0x0000
151 */
152 typedef struct _GLOBAL_t { /* Location: */
153 u32 txq_start_addr; /* 0x0000 */
154 u32 txq_end_addr; /* 0x0004 */
155 u32 rxq_start_addr; /* 0x0008 */
156 u32 rxq_end_addr; /* 0x000C */
157 u32 pm_csr; /* 0x0010 */
158 u32 unused; /* 0x0014 */
159 u32 int_status; /* 0x0018 */
160 u32 int_mask; /* 0x001C */
161 u32 int_alias_clr_en; /* 0x0020 */
162 u32 int_status_alias; /* 0x0024 */
163 u32 sw_reset; /* 0x0028 */
164 u32 slv_timer; /* 0x002C */
165 u32 msi_config; /* 0x0030 */
166 u32 loopback; /* 0x0034 */
167 u32 watchdog_timer; /* 0x0038 */
168 } GLOBAL_t, *PGLOBAL_t;
169
170 /* END OF GLOBAL REGISTER ADDRESS MAP */
171
172
173 /* START OF TXDMA REGISTER ADDRESS MAP */
174
175 /*
176 * txdma control status reg at address 0x1000
177 */
178
179 #define ET_TXDMA_CSR_HALT 0x00000001
180 #define ET_TXDMA_DROP_TLP 0x00000002
181 #define ET_TXDMA_CACHE_THRS 0x000000F0
182 #define ET_TXDMA_CACHE_SHIFT 4
183 #define ET_TXDMA_SNGL_EPKT 0x00000100
184 #define ET_TXDMA_CLASS 0x00001E00
185
186 /*
187 * structure for txdma packet ring base address hi reg in txdma address map
188 * located at address 0x1004
189 * Defined earlier (u32)
190 */
191
192 /*
193 * structure for txdma packet ring base address low reg in txdma address map
194 * located at address 0x1008
195 * Defined earlier (u32)
196 */
197
198 /*
199 * structure for txdma packet ring number of descriptor reg in txdma address
200 * map. Located at address 0x100C
201 *
202 * 31-10: unused
203 * 9-0: pr ndes
204 */
205
206 #define ET_DMA10_MASK 0x3FF /* 10 bit mask for DMA10W types */
207 #define ET_DMA10_WRAP 0x400
208 #define ET_DMA4_MASK 0x00F /* 4 bit mask for DMA4W types */
209 #define ET_DMA4_WRAP 0x010
210
211 #define INDEX10(x) ((x) & ET_DMA10_MASK)
212 #define INDEX4(x) ((x) & ET_DMA4_MASK)
213
214 extern inline void add_10bit(u32 *v, int n)
215 {
216 *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
217 }
218
219 /*
220 * 10bit DMA with wrap
221 * txdma tx queue write address reg in txdma address map at 0x1010
222 * txdma tx queue write address external reg in txdma address map at 0x1014
223 * txdma tx queue read address reg in txdma address map at 0x1018
224 *
225 * u32
226 * txdma status writeback address hi reg in txdma address map at0x101C
227 * txdma status writeback address lo reg in txdma address map at 0x1020
228 *
229 * 10bit DMA with wrap
230 * txdma service request reg in txdma address map at 0x1024
231 * structure for txdma service complete reg in txdma address map at 0x1028
232 *
233 * 4bit DMA with wrap
234 * txdma tx descriptor cache read index reg in txdma address map at 0x102C
235 * txdma tx descriptor cache write index reg in txdma address map at 0x1030
236 *
237 * txdma error reg in txdma address map at address 0x1034
238 * 0: PyldResend
239 * 1: PyldRewind
240 * 4: DescrResend
241 * 5: DescrRewind
242 * 8: WrbkResend
243 * 9: WrbkRewind
244 */
245
246 /*
247 * Tx DMA Module of JAGCore Address Mapping
248 * Located at address 0x1000
249 */
250 typedef struct _TXDMA_t { /* Location: */
251 u32 csr; /* 0x1000 */
252 u32 pr_base_hi; /* 0x1004 */
253 u32 pr_base_lo; /* 0x1008 */
254 u32 pr_num_des; /* 0x100C */
255 u32 txq_wr_addr; /* 0x1010 */
256 u32 txq_wr_addr_ext; /* 0x1014 */
257 u32 txq_rd_addr; /* 0x1018 */
258 u32 dma_wb_base_hi; /* 0x101C */
259 u32 dma_wb_base_lo; /* 0x1020 */
260 u32 service_request; /* 0x1024 */
261 u32 service_complete; /* 0x1028 */
262 u32 cache_rd_index; /* 0x102C */
263 u32 cache_wr_index; /* 0x1030 */
264 u32 TxDmaError; /* 0x1034 */
265 u32 DescAbortCount; /* 0x1038 */
266 u32 PayloadAbortCnt; /* 0x103c */
267 u32 WriteBackAbortCnt; /* 0x1040 */
268 u32 DescTimeoutCnt; /* 0x1044 */
269 u32 PayloadTimeoutCnt; /* 0x1048 */
270 u32 WriteBackTimeoutCnt; /* 0x104c */
271 u32 DescErrorCount; /* 0x1050 */
272 u32 PayloadErrorCnt; /* 0x1054 */
273 u32 WriteBackErrorCnt; /* 0x1058 */
274 u32 DroppedTLPCount; /* 0x105c */
275 u32 NewServiceComplete; /* 0x1060 */
276 u32 EthernetPacketCount; /* 0x1064 */
277 } TXDMA_t, *PTXDMA_t;
278
279 /* END OF TXDMA REGISTER ADDRESS MAP */
280
281
282 /* START OF RXDMA REGISTER ADDRESS MAP */
283
284 /*
285 * structure for control status reg in rxdma address map
286 * Located at address 0x2000
287 */
288 typedef union _RXDMA_CSR_t {
289 u32 value;
290 struct {
291 #ifdef _BIT_FIELDS_HTOL
292 u32 unused2:14; /* bits 18-31 */
293 u32 halt_status:1; /* bit 17 */
294 u32 pkt_done_flush:1; /* bit 16 */
295 u32 pkt_drop_disable:1; /* bit 15 */
296 u32 unused1:1; /* bit 14 */
297 u32 fbr1_enable:1; /* bit 13 */
298 u32 fbr1_size:2; /* bits 11-12 */
299 u32 fbr0_enable:1; /* bit 10 */
300 u32 fbr0_size:2; /* bits 8-9 */
301 u32 dma_big_endian:1; /* bit 7 */
302 u32 pkt_big_endian:1; /* bit 6 */
303 u32 psr_big_endian:1; /* bit 5 */
304 u32 fbr_big_endian:1; /* bit 4 */
305 u32 tc:3; /* bits 1-3 */
306 u32 halt:1; /* bit 0 */
307 #else
308 u32 halt:1; /* bit 0 */
309 u32 tc:3; /* bits 1-3 */
310 u32 fbr_big_endian:1; /* bit 4 */
311 u32 psr_big_endian:1; /* bit 5 */
312 u32 pkt_big_endian:1; /* bit 6 */
313 u32 dma_big_endian:1; /* bit 7 */
314 u32 fbr0_size:2; /* bits 8-9 */
315 u32 fbr0_enable:1; /* bit 10 */
316 u32 fbr1_size:2; /* bits 11-12 */
317 u32 fbr1_enable:1; /* bit 13 */
318 u32 unused1:1; /* bit 14 */
319 u32 pkt_drop_disable:1; /* bit 15 */
320 u32 pkt_done_flush:1; /* bit 16 */
321 u32 halt_status:1; /* bit 17 */
322 u32 unused2:14; /* bits 18-31 */
323 #endif
324 } bits;
325 } RXDMA_CSR_t, *PRXDMA_CSR_t;
326
327 /*
328 * structure for dma writeback lo reg in rxdma address map
329 * located at address 0x2004
330 * Defined earlier (u32)
331 */
332
333 /*
334 * structure for dma writeback hi reg in rxdma address map
335 * located at address 0x2008
336 * Defined earlier (u32)
337 */
338
339 /*
340 * structure for number of packets done reg in rxdma address map
341 * located at address 0x200C
342 */
343 typedef union _RXDMA_NUM_PKT_DONE_t {
344 u32 value;
345 struct {
346 #ifdef _BIT_FIELDS_HTOL
347 u32 unused:24; /* bits 8-31 */
348 u32 num_done:8; /* bits 0-7 */
349 #else
350 u32 num_done:8; /* bits 0-7 */
351 u32 unused:24; /* bits 8-31 */
352 #endif
353 } bits;
354 } RXDMA_NUM_PKT_DONE_t, *PRXDMA_NUM_PKT_DONE_t;
355
356 /*
357 * structure for max packet time reg in rxdma address map
358 * located at address 0x2010
359 *
360 * 31-18: unused
361 * 17-0: time done
362 */
363
364 /*
365 * structure for rx queue read address reg in rxdma address map
366 * located at address 0x2014
367 * Defined earlier (u32)
368 */
369
370 /*
371 * structure for rx queue read address external reg in rxdma address map
372 * located at address 0x2018
373 * Defined earlier (u32)
374 */
375
376 /*
377 * structure for rx queue write address reg in rxdma address map
378 * located at address 0x201C
379 * Defined earlier (u32)
380 */
381
382 /*
383 * structure for packet status ring base address lo reg in rxdma address map
384 * located at address 0x2020
385 * Defined earlier (u32)
386 */
387
388 /*
389 * structure for packet status ring base address hi reg in rxdma address map
390 * located at address 0x2024
391 * Defined earlier (u32)
392 */
393
394 /*
395 * structure for packet status ring number of descriptors reg in rxdma address
396 * map. Located at address 0x2028
397 */
398 typedef union _RXDMA_PSR_NUM_DES_t {
399 u32 value;
400 struct {
401 #ifdef _BIT_FIELDS_HTOL
402 u32 unused:20; /* bits 12-31 */
403 u32 psr_ndes:12; /* bit 0-11 */
404 #else
405 u32 psr_ndes:12; /* bit 0-11 */
406 u32 unused:20; /* bits 12-31 */
407 #endif
408 } bits;
409 } RXDMA_PSR_NUM_DES_t, *PRXDMA_PSR_NUM_DES_t;
410
411 /*
412 * structure for packet status ring available offset reg in rxdma address map
413 * located at address 0x202C
414 */
415 typedef union _RXDMA_PSR_AVAIL_OFFSET_t {
416 u32 value;
417 struct {
418 #ifdef _BIT_FIELDS_HTOL
419 u32 unused:19; /* bits 13-31 */
420 u32 psr_avail_wrap:1; /* bit 12 */
421 u32 psr_avail:12; /* bit 0-11 */
422 #else
423 u32 psr_avail:12; /* bit 0-11 */
424 u32 psr_avail_wrap:1; /* bit 12 */
425 u32 unused:19; /* bits 13-31 */
426 #endif
427 } bits;
428 } RXDMA_PSR_AVAIL_OFFSET_t, *PRXDMA_PSR_AVAIL_OFFSET_t;
429
430 /*
431 * structure for packet status ring full offset reg in rxdma address map
432 * located at address 0x2030
433 */
434 typedef union _RXDMA_PSR_FULL_OFFSET_t {
435 u32 value;
436 struct {
437 #ifdef _BIT_FIELDS_HTOL
438 u32 unused:19; /* bits 13-31 */
439 u32 psr_full_wrap:1; /* bit 12 */
440 u32 psr_full:12; /* bit 0-11 */
441 #else
442 u32 psr_full:12; /* bit 0-11 */
443 u32 psr_full_wrap:1; /* bit 12 */
444 u32 unused:19; /* bits 13-31 */
445 #endif
446 } bits;
447 } RXDMA_PSR_FULL_OFFSET_t, *PRXDMA_PSR_FULL_OFFSET_t;
448
449 /*
450 * structure for packet status ring access index reg in rxdma address map
451 * located at address 0x2034
452 */
453 typedef union _RXDMA_PSR_ACCESS_INDEX_t {
454 u32 value;
455 struct {
456 #ifdef _BIT_FIELDS_HTOL
457 u32 unused:27; /* bits 5-31 */
458 u32 psr_ai:5; /* bits 0-4 */
459 #else
460 u32 psr_ai:5; /* bits 0-4 */
461 u32 unused:27; /* bits 5-31 */
462 #endif
463 } bits;
464 } RXDMA_PSR_ACCESS_INDEX_t, *PRXDMA_PSR_ACCESS_INDEX_t;
465
466 /*
467 * structure for packet status ring minimum descriptors reg in rxdma address
468 * map. Located at address 0x2038
469 */
470 typedef union _RXDMA_PSR_MIN_DES_t {
471 u32 value;
472 struct {
473 #ifdef _BIT_FIELDS_HTOL
474 u32 unused:20; /* bits 12-31 */
475 u32 psr_min:12; /* bits 0-11 */
476 #else
477 u32 psr_min:12; /* bits 0-11 */
478 u32 unused:20; /* bits 12-31 */
479 #endif
480 } bits;
481 } RXDMA_PSR_MIN_DES_t, *PRXDMA_PSR_MIN_DES_t;
482
483 /*
484 * structure for free buffer ring base lo address reg in rxdma address map
485 * located at address 0x203C
486 * Defined earlier (u32)
487 */
488
489 /*
490 * structure for free buffer ring base hi address reg in rxdma address map
491 * located at address 0x2040
492 * Defined earlier (u32)
493 */
494
495 /*
496 * structure for free buffer ring number of descriptors reg in rxdma address
497 * map. Located at address 0x2044
498 */
499 typedef union _RXDMA_FBR_NUM_DES_t {
500 u32 value;
501 struct {
502 #ifdef _BIT_FIELDS_HTOL
503 u32 unused:22; /* bits 10-31 */
504 u32 fbr_ndesc:10; /* bits 0-9 */
505 #else
506 u32 fbr_ndesc:10; /* bits 0-9 */
507 u32 unused:22; /* bits 10-31 */
508 #endif
509 } bits;
510 } RXDMA_FBR_NUM_DES_t, *PRXDMA_FBR_NUM_DES_t;
511
512 /*
513 * structure for free buffer ring 0 available offset reg in rxdma address map
514 * located at address 0x2048
515 * Defined earlier (u32)
516 */
517
518 /*
519 * structure for free buffer ring 0 full offset reg in rxdma address map
520 * located at address 0x204C
521 * Defined earlier (u32)
522 */
523
524 /*
525 * structure for free buffer cache 0 full offset reg in rxdma address map
526 * located at address 0x2050
527 */
528 typedef union _RXDMA_FBC_RD_INDEX_t {
529 u32 value;
530 struct {
531 #ifdef _BIT_FIELDS_HTOL
532 u32 unused:27; /* bits 5-31 */
533 u32 fbc_rdi:5; /* bit 0-4 */
534 #else
535 u32 fbc_rdi:5; /* bit 0-4 */
536 u32 unused:27; /* bits 5-31 */
537 #endif
538 } bits;
539 } RXDMA_FBC_RD_INDEX_t, *PRXDMA_FBC_RD_INDEX_t;
540
541 /*
542 * structure for free buffer ring 0 minimum descriptor reg in rxdma address map
543 * located at address 0x2054
544 */
545 typedef union _RXDMA_FBR_MIN_DES_t {
546 u32 value;
547 struct {
548 #ifdef _BIT_FIELDS_HTOL
549 u32 unused:22; /* bits 10-31 */
550 u32 fbr_min:10; /* bits 0-9 */
551 #else
552 u32 fbr_min:10; /* bits 0-9 */
553 u32 unused:22; /* bits 10-31 */
554 #endif
555 } bits;
556 } RXDMA_FBR_MIN_DES_t, *PRXDMA_FBR_MIN_DES_t;
557
558 /*
559 * structure for free buffer ring 1 base address lo reg in rxdma address map
560 * located at address 0x2058 - 0x205C
561 * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
562 */
563
564 /*
565 * structure for free buffer ring 1 number of descriptors reg in rxdma address
566 * map. Located at address 0x2060
567 * Defined earlier (RXDMA_FBR_NUM_DES_t)
568 */
569
570 /*
571 * structure for free buffer ring 1 available offset reg in rxdma address map
572 * located at address 0x2064
573 * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
574 */
575
576 /*
577 * structure for free buffer ring 1 full offset reg in rxdma address map
578 * located at address 0x2068
579 * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
580 */
581
582 /*
583 * structure for free buffer cache 1 read index reg in rxdma address map
584 * located at address 0x206C
585 * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
586 */
587
588 /*
589 * structure for free buffer ring 1 minimum descriptor reg in rxdma address map
590 * located at address 0x2070
591 * Defined Earlier (RXDMA_FBR_MIN_DES_t)
592 */
593
594 /*
595 * Rx DMA Module of JAGCore Address Mapping
596 * Located at address 0x2000
597 */
598 typedef struct _RXDMA_t { /* Location: */
599 RXDMA_CSR_t csr; /* 0x2000 */
600 u32 dma_wb_base_lo; /* 0x2004 */
601 u32 dma_wb_base_hi; /* 0x2008 */
602 RXDMA_NUM_PKT_DONE_t num_pkt_done; /* 0x200C */
603 u32 max_pkt_time; /* 0x2010 */
604 u32 rxq_rd_addr; /* 0x2014 */
605 u32 rxq_rd_addr_ext; /* 0x2018 */
606 u32 rxq_wr_addr; /* 0x201C */
607 u32 psr_base_lo; /* 0x2020 */
608 u32 psr_base_hi; /* 0x2024 */
609 RXDMA_PSR_NUM_DES_t psr_num_des; /* 0x2028 */
610 RXDMA_PSR_AVAIL_OFFSET_t psr_avail_offset; /* 0x202C */
611 RXDMA_PSR_FULL_OFFSET_t psr_full_offset; /* 0x2030 */
612 RXDMA_PSR_ACCESS_INDEX_t psr_access_index; /* 0x2034 */
613 RXDMA_PSR_MIN_DES_t psr_min_des; /* 0x2038 */
614 u32 fbr0_base_lo; /* 0x203C */
615 u32 fbr0_base_hi; /* 0x2040 */
616 RXDMA_FBR_NUM_DES_t fbr0_num_des; /* 0x2044 */
617 u32 fbr0_avail_offset; /* 0x2048 */
618 u32 fbr0_full_offset; /* 0x204C */
619 RXDMA_FBC_RD_INDEX_t fbr0_rd_index; /* 0x2050 */
620 RXDMA_FBR_MIN_DES_t fbr0_min_des; /* 0x2054 */
621 u32 fbr1_base_lo; /* 0x2058 */
622 u32 fbr1_base_hi; /* 0x205C */
623 RXDMA_FBR_NUM_DES_t fbr1_num_des; /* 0x2060 */
624 u32 fbr1_avail_offset; /* 0x2064 */
625 u32 fbr1_full_offset; /* 0x2068 */
626 RXDMA_FBC_RD_INDEX_t fbr1_rd_index; /* 0x206C */
627 RXDMA_FBR_MIN_DES_t fbr1_min_des; /* 0x2070 */
628 } RXDMA_t, *PRXDMA_t;
629
630 /* END OF RXDMA REGISTER ADDRESS MAP */
631
632
633 /* START OF TXMAC REGISTER ADDRESS MAP */
634
635 /*
636 * structure for control reg in txmac address map
637 * located at address 0x3000
638 */
639 typedef union _TXMAC_CTL_t {
640 u32 value;
641 struct {
642 #ifdef _BIT_FIELDS_HTOL
643 u32 unused:24; /* bits 8-31 */
644 u32 cklseg_diable:1; /* bit 7 */
645 u32 ckbcnt_disable:1; /* bit 6 */
646 u32 cksegnum:1; /* bit 5 */
647 u32 async_disable:1; /* bit 4 */
648 u32 fc_disable:1; /* bit 3 */
649 u32 mcif_disable:1; /* bit 2 */
650 u32 mif_disable:1; /* bit 1 */
651 u32 txmac_en:1; /* bit 0 */
652 #else
653 u32 txmac_en:1; /* bit 0 */
654 u32 mif_disable:1; /* bit 1 mac interface */
655 u32 mcif_disable:1; /* bit 2 mem. contr. interface */
656 u32 fc_disable:1; /* bit 3 */
657 u32 async_disable:1; /* bit 4 */
658 u32 cksegnum:1; /* bit 5 */
659 u32 ckbcnt_disable:1; /* bit 6 */
660 u32 cklseg_diable:1; /* bit 7 */
661 u32 unused:24; /* bits 8-31 */
662 #endif
663 } bits;
664 } TXMAC_CTL_t, *PTXMAC_CTL_t;
665
666 /*
667 * structure for shadow pointer reg in txmac address map
668 * located at address 0x3004
669 * 31-27: reserved
670 * 26-16: txq rd ptr
671 * 15-11: reserved
672 * 10-0: txq wr ptr
673 */
674
675 /*
676 * structure for error count reg in txmac address map
677 * located at address 0x3008
678 */
679 typedef union _TXMAC_ERR_CNT_t {
680 u32 value;
681 struct {
682 #ifdef _BIT_FIELDS_HTOL
683 u32 unused:20; /* bits 12-31 */
684 u32 reserved:4; /* bits 8-11 */
685 u32 txq_underrun:4; /* bits 4-7 */
686 u32 fifo_underrun:4; /* bits 0-3 */
687 #else
688 u32 fifo_underrun:4; /* bits 0-3 */
689 u32 txq_underrun:4; /* bits 4-7 */
690 u32 reserved:4; /* bits 8-11 */
691 u32 unused:20; /* bits 12-31 */
692 #endif
693 } bits;
694 } TXMAC_ERR_CNT_t, *PTXMAC_ERR_CNT_t;
695
696 /*
697 * structure for max fill reg in txmac address map
698 * located at address 0x300C
699 * 31-12: unused
700 * 11-0: max fill
701 */
702
703 /*
704 * structure for cf parameter reg in txmac address map
705 * located at address 0x3010
706 * 31-16: cfep
707 * 15-0: cfpt
708 */
709
710 /*
711 * structure for tx test reg in txmac address map
712 * located at address 0x3014
713 * 31-17: unused
714 * 16: reserved1
715 * 15: txtest_en
716 * 14-11: unused
717 * 10-0: txq test pointer
718 */
719
720 /*
721 * structure for error reg in txmac address map
722 * located at address 0x3018
723 */
724 typedef union _TXMAC_ERR_t {
725 u32 value;
726 struct {
727 #ifdef _BIT_FIELDS_HTOL
728 u32 unused2:23; /* bits 9-31 */
729 u32 fifo_underrun:1; /* bit 8 */
730 u32 unused1:2; /* bits 6-7 */
731 u32 ctrl2_err:1; /* bit 5 */
732 u32 txq_underrun:1; /* bit 4 */
733 u32 bcnt_err:1; /* bit 3 */
734 u32 lseg_err:1; /* bit 2 */
735 u32 segnum_err:1; /* bit 1 */
736 u32 seg0_err:1; /* bit 0 */
737 #else
738 u32 seg0_err:1; /* bit 0 */
739 u32 segnum_err:1; /* bit 1 */
740 u32 lseg_err:1; /* bit 2 */
741 u32 bcnt_err:1; /* bit 3 */
742 u32 txq_underrun:1; /* bit 4 */
743 u32 ctrl2_err:1; /* bit 5 */
744 u32 unused1:2; /* bits 6-7 */
745 u32 fifo_underrun:1; /* bit 8 */
746 u32 unused2:23; /* bits 9-31 */
747 #endif
748 } bits;
749 } TXMAC_ERR_t, *PTXMAC_ERR_t;
750
751 /*
752 * structure for error interrupt reg in txmac address map
753 * located at address 0x301C
754 */
755 typedef union _TXMAC_ERR_INT_t {
756 u32 value;
757 struct {
758 #ifdef _BIT_FIELDS_HTOL
759 u32 unused2:23; /* bits 9-31 */
760 u32 fifo_underrun:1; /* bit 8 */
761 u32 unused1:2; /* bits 6-7 */
762 u32 ctrl2_err:1; /* bit 5 */
763 u32 txq_underrun:1; /* bit 4 */
764 u32 bcnt_err:1; /* bit 3 */
765 u32 lseg_err:1; /* bit 2 */
766 u32 segnum_err:1; /* bit 1 */
767 u32 seg0_err:1; /* bit 0 */
768 #else
769 u32 seg0_err:1; /* bit 0 */
770 u32 segnum_err:1; /* bit 1 */
771 u32 lseg_err:1; /* bit 2 */
772 u32 bcnt_err:1; /* bit 3 */
773 u32 txq_underrun:1; /* bit 4 */
774 u32 ctrl2_err:1; /* bit 5 */
775 u32 unused1:2; /* bits 6-7 */
776 u32 fifo_underrun:1; /* bit 8 */
777 u32 unused2:23; /* bits 9-31 */
778 #endif
779 } bits;
780 } TXMAC_ERR_INT_t, *PTXMAC_ERR_INT_t;
781
782 /*
783 * structure for error interrupt reg in txmac address map
784 * located at address 0x3020
785 *
786 * 31-2: unused
787 * 1: bp_req
788 * 0: bp_xonxoff
789 */
790
791 /*
792 * Tx MAC Module of JAGCore Address Mapping
793 */
794 typedef struct _TXMAC_t { /* Location: */
795 TXMAC_CTL_t ctl; /* 0x3000 */
796 u32 shadow_ptr; /* 0x3004 */
797 TXMAC_ERR_CNT_t err_cnt; /* 0x3008 */
798 u32 max_fill; /* 0x300C */
799 u32 cf_param; /* 0x3010 */
800 u32 tx_test; /* 0x3014 */
801 TXMAC_ERR_t err; /* 0x3018 */
802 TXMAC_ERR_INT_t err_int; /* 0x301C */
803 u32 bp_ctrl; /* 0x3020 */
804 } TXMAC_t, *PTXMAC_t;
805
806 /* END OF TXMAC REGISTER ADDRESS MAP */
807
808 /* START OF RXMAC REGISTER ADDRESS MAP */
809
810 /*
811 * structure for rxmac control reg in rxmac address map
812 * located at address 0x4000
813 */
814 typedef union _RXMAC_CTRL_t {
815 u32 value;
816 struct {
817 #ifdef _BIT_FIELDS_HTOL
818 u32 reserved:25; /* bits 7-31 */
819 u32 rxmac_int_disable:1; /* bit 6 */
820 u32 async_disable:1; /* bit 5 */
821 u32 mif_disable:1; /* bit 4 */
822 u32 wol_disable:1; /* bit 3 */
823 u32 pkt_filter_disable:1; /* bit 2 */
824 u32 mcif_disable:1; /* bit 1 */
825 u32 rxmac_en:1; /* bit 0 */
826 #else
827 u32 rxmac_en:1; /* bit 0 */
828 u32 mcif_disable:1; /* bit 1 */
829 u32 pkt_filter_disable:1; /* bit 2 */
830 u32 wol_disable:1; /* bit 3 */
831 u32 mif_disable:1; /* bit 4 */
832 u32 async_disable:1; /* bit 5 */
833 u32 rxmac_int_disable:1; /* bit 6 */
834 u32 reserved:25; /* bits 7-31 */
835 #endif
836 } bits;
837 } RXMAC_CTRL_t, *PRXMAC_CTRL_t;
838
839 /*
840 * structure for Wake On Lan Control and CRC 0 reg in rxmac address map
841 * located at address 0x4004
842 */
843 typedef union _RXMAC_WOL_CTL_CRC0_t {
844 u32 value;
845 struct {
846 #ifdef _BIT_FIELDS_HTOL
847 u32 crc0:16; /* bits 16-31 */
848 u32 reserve:4; /* bits 12-15 */
849 u32 ignore_pp:1; /* bit 11 */
850 u32 ignore_mp:1; /* bit 10 */
851 u32 clr_intr:1; /* bit 9 */
852 u32 ignore_link_chg:1; /* bit 8 */
853 u32 ignore_uni:1; /* bit 7 */
854 u32 ignore_multi:1; /* bit 6 */
855 u32 ignore_broad:1; /* bit 5 */
856 u32 valid_crc4:1; /* bit 4 */
857 u32 valid_crc3:1; /* bit 3 */
858 u32 valid_crc2:1; /* bit 2 */
859 u32 valid_crc1:1; /* bit 1 */
860 u32 valid_crc0:1; /* bit 0 */
861 #else
862 u32 valid_crc0:1; /* bit 0 */
863 u32 valid_crc1:1; /* bit 1 */
864 u32 valid_crc2:1; /* bit 2 */
865 u32 valid_crc3:1; /* bit 3 */
866 u32 valid_crc4:1; /* bit 4 */
867 u32 ignore_broad:1; /* bit 5 */
868 u32 ignore_multi:1; /* bit 6 */
869 u32 ignore_uni:1; /* bit 7 */
870 u32 ignore_link_chg:1; /* bit 8 */
871 u32 clr_intr:1; /* bit 9 */
872 u32 ignore_mp:1; /* bit 10 */
873 u32 ignore_pp:1; /* bit 11 */
874 u32 reserve:4; /* bits 12-15 */
875 u32 crc0:16; /* bits 16-31 */
876 #endif
877 } bits;
878 } RXMAC_WOL_CTL_CRC0_t, *PRXMAC_WOL_CTL_CRC0_t;
879
880 /*
881 * structure for CRC 1 and CRC 2 reg in rxmac address map
882 * located at address 0x4008
883 */
884 typedef union _RXMAC_WOL_CRC12_t {
885 u32 value;
886 struct {
887 #ifdef _BIT_FIELDS_HTOL
888 u32 crc2:16; /* bits 16-31 */
889 u32 crc1:16; /* bits 0-15 */
890 #else
891 u32 crc1:16; /* bits 0-15 */
892 u32 crc2:16; /* bits 16-31 */
893 #endif
894 } bits;
895 } RXMAC_WOL_CRC12_t, *PRXMAC_WOL_CRC12_t;
896
897 /*
898 * structure for CRC 3 and CRC 4 reg in rxmac address map
899 * located at address 0x400C
900 */
901 typedef union _RXMAC_WOL_CRC34_t {
902 u32 value;
903 struct {
904 #ifdef _BIT_FIELDS_HTOL
905 u32 crc4:16; /* bits 16-31 */
906 u32 crc3:16; /* bits 0-15 */
907 #else
908 u32 crc3:16; /* bits 0-15 */
909 u32 crc4:16; /* bits 16-31 */
910 #endif
911 } bits;
912 } RXMAC_WOL_CRC34_t, *PRXMAC_WOL_CRC34_t;
913
914 /*
915 * structure for Wake On Lan Source Address Lo reg in rxmac address map
916 * located at address 0x4010
917 */
918 typedef union _RXMAC_WOL_SA_LO_t {
919 u32 value;
920 struct {
921 #ifdef _BIT_FIELDS_HTOL
922 u32 sa3:8; /* bits 24-31 */
923 u32 sa4:8; /* bits 16-23 */
924 u32 sa5:8; /* bits 8-15 */
925 u32 sa6:8; /* bits 0-7 */
926 #else
927 u32 sa6:8; /* bits 0-7 */
928 u32 sa5:8; /* bits 8-15 */
929 u32 sa4:8; /* bits 16-23 */
930 u32 sa3:8; /* bits 24-31 */
931 #endif
932 } bits;
933 } RXMAC_WOL_SA_LO_t, *PRXMAC_WOL_SA_LO_t;
934
935 /*
936 * structure for Wake On Lan Source Address Hi reg in rxmac address map
937 * located at address 0x4014
938 */
939 typedef union _RXMAC_WOL_SA_HI_t {
940 u32 value;
941 struct {
942 #ifdef _BIT_FIELDS_HTOL
943 u32 reserved:16; /* bits 16-31 */
944 u32 sa1:8; /* bits 8-15 */
945 u32 sa2:8; /* bits 0-7 */
946 #else
947 u32 sa2:8; /* bits 0-7 */
948 u32 sa1:8; /* bits 8-15 */
949 u32 reserved:16; /* bits 16-31 */
950 #endif
951 } bits;
952 } RXMAC_WOL_SA_HI_t, *PRXMAC_WOL_SA_HI_t;
953
954 /*
955 * structure for Wake On Lan mask reg in rxmac address map
956 * located at address 0x4018 - 0x4064
957 * Defined earlier (u32)
958 */
959
960 /*
961 * structure for Unicast Paket Filter Address 1 reg in rxmac address map
962 * located at address 0x4068
963 */
964 typedef union _RXMAC_UNI_PF_ADDR1_t {
965 u32 value;
966 struct {
967 #ifdef _BIT_FIELDS_HTOL
968 u32 addr1_3:8; /* bits 24-31 */
969 u32 addr1_4:8; /* bits 16-23 */
970 u32 addr1_5:8; /* bits 8-15 */
971 u32 addr1_6:8; /* bits 0-7 */
972 #else
973 u32 addr1_6:8; /* bits 0-7 */
974 u32 addr1_5:8; /* bits 8-15 */
975 u32 addr1_4:8; /* bits 16-23 */
976 u32 addr1_3:8; /* bits 24-31 */
977 #endif
978 } bits;
979 } RXMAC_UNI_PF_ADDR1_t, *PRXMAC_UNI_PF_ADDR1_t;
980
981 /*
982 * structure for Unicast Paket Filter Address 2 reg in rxmac address map
983 * located at address 0x406C
984 */
985 typedef union _RXMAC_UNI_PF_ADDR2_t {
986 u32 value;
987 struct {
988 #ifdef _BIT_FIELDS_HTOL
989 u32 addr2_3:8; /* bits 24-31 */
990 u32 addr2_4:8; /* bits 16-23 */
991 u32 addr2_5:8; /* bits 8-15 */
992 u32 addr2_6:8; /* bits 0-7 */
993 #else
994 u32 addr2_6:8; /* bits 0-7 */
995 u32 addr2_5:8; /* bits 8-15 */
996 u32 addr2_4:8; /* bits 16-23 */
997 u32 addr2_3:8; /* bits 24-31 */
998 #endif
999 } bits;
1000 } RXMAC_UNI_PF_ADDR2_t, *PRXMAC_UNI_PF_ADDR2_t;
1001
1002 /*
1003 * structure for Unicast Paket Filter Address 1 & 2 reg in rxmac address map
1004 * located at address 0x4070
1005 */
1006 typedef union _RXMAC_UNI_PF_ADDR3_t {
1007 u32 value;
1008 struct {
1009 #ifdef _BIT_FIELDS_HTOL
1010 u32 addr2_1:8; /* bits 24-31 */
1011 u32 addr2_2:8; /* bits 16-23 */
1012 u32 addr1_1:8; /* bits 8-15 */
1013 u32 addr1_2:8; /* bits 0-7 */
1014 #else
1015 u32 addr1_2:8; /* bits 0-7 */
1016 u32 addr1_1:8; /* bits 8-15 */
1017 u32 addr2_2:8; /* bits 16-23 */
1018 u32 addr2_1:8; /* bits 24-31 */
1019 #endif
1020 } bits;
1021 } RXMAC_UNI_PF_ADDR3_t, *PRXMAC_UNI_PF_ADDR3_t;
1022
1023 /*
1024 * structure for Multicast Hash reg in rxmac address map
1025 * located at address 0x4074 - 0x4080
1026 * Defined earlier (u32)
1027 */
1028
1029 /*
1030 * structure for Packet Filter Control reg in rxmac address map
1031 * located at address 0x4084
1032 */
1033 typedef union _RXMAC_PF_CTRL_t {
1034 u32 value;
1035 struct {
1036 #ifdef _BIT_FIELDS_HTOL
1037 u32 unused2:9; /* bits 23-31 */
1038 u32 min_pkt_size:7; /* bits 16-22 */
1039 u32 unused1:12; /* bits 4-15 */
1040 u32 filter_frag_en:1; /* bit 3 */
1041 u32 filter_uni_en:1; /* bit 2 */
1042 u32 filter_multi_en:1; /* bit 1 */
1043 u32 filter_broad_en:1; /* bit 0 */
1044 #else
1045 u32 filter_broad_en:1; /* bit 0 */
1046 u32 filter_multi_en:1; /* bit 1 */
1047 u32 filter_uni_en:1; /* bit 2 */
1048 u32 filter_frag_en:1; /* bit 3 */
1049 u32 unused1:12; /* bits 4-15 */
1050 u32 min_pkt_size:7; /* bits 16-22 */
1051 u32 unused2:9; /* bits 23-31 */
1052 #endif
1053 } bits;
1054 } RXMAC_PF_CTRL_t, *PRXMAC_PF_CTRL_t;
1055
1056 /*
1057 * structure for Memory Controller Interface Control Max Segment reg in rxmac
1058 * address map. Located at address 0x4088
1059 */
1060 typedef union _RXMAC_MCIF_CTRL_MAX_SEG_t {
1061 u32 value;
1062 struct {
1063 #ifdef _BIT_FIELDS_HTOL
1064 u32 reserved:22; /* bits 10-31 */
1065 u32 max_size:8; /* bits 2-9 */
1066 u32 fc_en:1; /* bit 1 */
1067 u32 seg_en:1; /* bit 0 */
1068 #else
1069 u32 seg_en:1; /* bit 0 */
1070 u32 fc_en:1; /* bit 1 */
1071 u32 max_size:8; /* bits 2-9 */
1072 u32 reserved:22; /* bits 10-31 */
1073 #endif
1074 } bits;
1075 } RXMAC_MCIF_CTRL_MAX_SEG_t, *PRXMAC_MCIF_CTRL_MAX_SEG_t;
1076
1077 /*
1078 * structure for Memory Controller Interface Water Mark reg in rxmac address
1079 * map. Located at address 0x408C
1080 */
1081 typedef union _RXMAC_MCIF_WATER_MARK_t {
1082 u32 value;
1083 struct {
1084 #ifdef _BIT_FIELDS_HTOL
1085 u32 reserved2:6; /* bits 26-31 */
1086 u32 mark_hi:10; /* bits 16-25 */
1087 u32 reserved1:6; /* bits 10-15 */
1088 u32 mark_lo:10; /* bits 0-9 */
1089 #else
1090 u32 mark_lo:10; /* bits 0-9 */
1091 u32 reserved1:6; /* bits 10-15 */
1092 u32 mark_hi:10; /* bits 16-25 */
1093 u32 reserved2:6; /* bits 26-31 */
1094 #endif
1095 } bits;
1096 } RXMAC_MCIF_WATER_MARK_t, *PRXMAC_MCIF_WATER_MARK_t;
1097
1098 /*
1099 * structure for Rx Queue Dialog reg in rxmac address map.
1100 * located at address 0x4090
1101 */
1102 typedef union _RXMAC_RXQ_DIAG_t {
1103 u32 value;
1104 struct {
1105 #ifdef _BIT_FIELDS_HTOL
1106 u32 reserved2:6; /* bits 26-31 */
1107 u32 rd_ptr:10; /* bits 16-25 */
1108 u32 reserved1:6; /* bits 10-15 */
1109 u32 wr_ptr:10; /* bits 0-9 */
1110 #else
1111 u32 wr_ptr:10; /* bits 0-9 */
1112 u32 reserved1:6; /* bits 10-15 */
1113 u32 rd_ptr:10; /* bits 16-25 */
1114 u32 reserved2:6; /* bits 26-31 */
1115 #endif
1116 } bits;
1117 } RXMAC_RXQ_DIAG_t, *PRXMAC_RXQ_DIAG_t;
1118
1119 /*
1120 * structure for space availiable reg in rxmac address map.
1121 * located at address 0x4094
1122 */
1123 typedef union _RXMAC_SPACE_AVAIL_t {
1124 u32 value;
1125 struct {
1126 #ifdef _BIT_FIELDS_HTOL
1127 u32 reserved2:15; /* bits 17-31 */
1128 u32 space_avail_en:1; /* bit 16 */
1129 u32 reserved1:6; /* bits 10-15 */
1130 u32 space_avail:10; /* bits 0-9 */
1131 #else
1132 u32 space_avail:10; /* bits 0-9 */
1133 u32 reserved1:6; /* bits 10-15 */
1134 u32 space_avail_en:1; /* bit 16 */
1135 u32 reserved2:15; /* bits 17-31 */
1136 #endif
1137 } bits;
1138 } RXMAC_SPACE_AVAIL_t, *PRXMAC_SPACE_AVAIL_t;
1139
1140 /*
1141 * structure for management interface reg in rxmac address map.
1142 * located at address 0x4098
1143 */
1144 typedef union _RXMAC_MIF_CTL_t {
1145 u32 value;
1146 struct {
1147 #ifdef _BIT_FIELDS_HTOL
1148 u32 reserve:14; /* bits 18-31 */
1149 u32 drop_pkt_en:1; /* bit 17 */
1150 u32 drop_pkt_mask:17; /* bits 0-16 */
1151 #else
1152 u32 drop_pkt_mask:17; /* bits 0-16 */
1153 u32 drop_pkt_en:1; /* bit 17 */
1154 u32 reserve:14; /* bits 18-31 */
1155 #endif
1156 } bits;
1157 } RXMAC_MIF_CTL_t, *PRXMAC_MIF_CTL_t;
1158
1159 /*
1160 * structure for Error reg in rxmac address map.
1161 * located at address 0x409C
1162 */
1163 typedef union _RXMAC_ERROR_REG_t {
1164 u32 value;
1165 struct {
1166 #ifdef _BIT_FIELDS_HTOL
1167 u32 reserve:28; /* bits 4-31 */
1168 u32 mif:1; /* bit 3 */
1169 u32 async:1; /* bit 2 */
1170 u32 pkt_filter:1; /* bit 1 */
1171 u32 mcif:1; /* bit 0 */
1172 #else
1173 u32 mcif:1; /* bit 0 */
1174 u32 pkt_filter:1; /* bit 1 */
1175 u32 async:1; /* bit 2 */
1176 u32 mif:1; /* bit 3 */
1177 u32 reserve:28; /* bits 4-31 */
1178 #endif
1179 } bits;
1180 } RXMAC_ERROR_REG_t, *PRXMAC_ERROR_REG_t;
1181
1182 /*
1183 * Rx MAC Module of JAGCore Address Mapping
1184 */
1185 typedef struct _RXMAC_t { /* Location: */
1186 RXMAC_CTRL_t ctrl; /* 0x4000 */
1187 RXMAC_WOL_CTL_CRC0_t crc0; /* 0x4004 */
1188 RXMAC_WOL_CRC12_t crc12; /* 0x4008 */
1189 RXMAC_WOL_CRC34_t crc34; /* 0x400C */
1190 RXMAC_WOL_SA_LO_t sa_lo; /* 0x4010 */
1191 RXMAC_WOL_SA_HI_t sa_hi; /* 0x4014 */
1192 u32 mask0_word0; /* 0x4018 */
1193 u32 mask0_word1; /* 0x401C */
1194 u32 mask0_word2; /* 0x4020 */
1195 u32 mask0_word3; /* 0x4024 */
1196 u32 mask1_word0; /* 0x4028 */
1197 u32 mask1_word1; /* 0x402C */
1198 u32 mask1_word2; /* 0x4030 */
1199 u32 mask1_word3; /* 0x4034 */
1200 u32 mask2_word0; /* 0x4038 */
1201 u32 mask2_word1; /* 0x403C */
1202 u32 mask2_word2; /* 0x4040 */
1203 u32 mask2_word3; /* 0x4044 */
1204 u32 mask3_word0; /* 0x4048 */
1205 u32 mask3_word1; /* 0x404C */
1206 u32 mask3_word2; /* 0x4050 */
1207 u32 mask3_word3; /* 0x4054 */
1208 u32 mask4_word0; /* 0x4058 */
1209 u32 mask4_word1; /* 0x405C */
1210 u32 mask4_word2; /* 0x4060 */
1211 u32 mask4_word3; /* 0x4064 */
1212 RXMAC_UNI_PF_ADDR1_t uni_pf_addr1; /* 0x4068 */
1213 RXMAC_UNI_PF_ADDR2_t uni_pf_addr2; /* 0x406C */
1214 RXMAC_UNI_PF_ADDR3_t uni_pf_addr3; /* 0x4070 */
1215 u32 multi_hash1; /* 0x4074 */
1216 u32 multi_hash2; /* 0x4078 */
1217 u32 multi_hash3; /* 0x407C */
1218 u32 multi_hash4; /* 0x4080 */
1219 RXMAC_PF_CTRL_t pf_ctrl; /* 0x4084 */
1220 RXMAC_MCIF_CTRL_MAX_SEG_t mcif_ctrl_max_seg; /* 0x4088 */
1221 RXMAC_MCIF_WATER_MARK_t mcif_water_mark; /* 0x408C */
1222 RXMAC_RXQ_DIAG_t rxq_diag; /* 0x4090 */
1223 RXMAC_SPACE_AVAIL_t space_avail; /* 0x4094 */
1224
1225 RXMAC_MIF_CTL_t mif_ctrl; /* 0x4098 */
1226 RXMAC_ERROR_REG_t err_reg; /* 0x409C */
1227 } RXMAC_t, *PRXMAC_t;
1228
1229 /* END OF TXMAC REGISTER ADDRESS MAP */
1230
1231
1232 /* START OF MAC REGISTER ADDRESS MAP */
1233
1234 /*
1235 * structure for configuration #1 reg in mac address map.
1236 * located at address 0x5000
1237 *
1238 * 31: soft reset
1239 * 30: sim reset
1240 * 29-20: reserved
1241 * 19: reset rx mc
1242 * 18: reset tx mc
1243 * 17: reset rx func
1244 * 16: reset tx fnc
1245 * 15-9: reserved
1246 * 8: loopback
1247 * 7-6: reserved
1248 * 5: rx flow
1249 * 4: tx flow
1250 * 3: syncd rx en
1251 * 2: rx enable
1252 * 1: syncd tx en
1253 * 0: tx enable
1254 */
1255
1256 #define CFG1_LOOPBACK 0x00000100
1257 #define CFG1_RX_FLOW 0x00000020
1258 #define CFG1_TX_FLOW 0x00000010
1259 #define CFG1_RX_ENABLE 0x00000004
1260 #define CFG1_TX_ENABLE 0x00000001
1261 #define CFG1_WAIT 0x0000000A /* RX & TX syncd */
1262
1263 /*
1264 * structure for configuration #2 reg in mac address map.
1265 * located at address 0x5004
1266 * 31-16: reserved
1267 * 15-12: preamble
1268 * 11-10: reserved
1269 * 9-8: if mode
1270 * 7-6: reserved
1271 * 5: huge frame
1272 * 4: length check
1273 * 3: undefined
1274 * 2: pad crc
1275 * 1: crc enable
1276 * 0: full duplex
1277 */
1278
1279
1280 /*
1281 * structure for Interpacket gap reg in mac address map.
1282 * located at address 0x5008
1283 *
1284 * 31: reserved
1285 * 30-24: non B2B ipg 1
1286 * 23: undefined
1287 * 22-16: non B2B ipg 2
1288 * 15-8: Min ifg enforce
1289 * 7-0: B2B ipg
1290 *
1291 * structure for half duplex reg in mac address map.
1292 * located at address 0x500C
1293 * 31-24: reserved
1294 * 23-20: Alt BEB trunc
1295 * 19: Alt BEB enable
1296 * 18: BP no backoff
1297 * 17: no backoff
1298 * 16: excess defer
1299 * 15-12: re-xmit max
1300 * 11-10: reserved
1301 * 9-0: collision window
1302 */
1303
1304 /*
1305 * structure for Maximum Frame Length reg in mac address map.
1306 * located at address 0x5010: bits 0-15 hold the length.
1307 */
1308
1309 /*
1310 * structure for Reserve 1 reg in mac address map.
1311 * located at address 0x5014 - 0x5018
1312 * Defined earlier (u32)
1313 */
1314
1315 /*
1316 * structure for Test reg in mac address map.
1317 * located at address 0x501C
1318 * test: bits 0-2, rest unused
1319 */
1320
1321 /*
1322 * structure for MII Management Configuration reg in mac address map.
1323 * located at address 0x5020
1324 *
1325 * 31: reset MII mgmt
1326 * 30-6: unused
1327 * 5: scan auto increment
1328 * 4: preamble supress
1329 * 3: undefined
1330 * 2-0: mgmt clock reset
1331 */
1332
1333 /*
1334 * structure for MII Management Command reg in mac address map.
1335 * located at address 0x5024
1336 * bit 1: scan cycle
1337 * bit 0: read cycle
1338 */
1339
1340 /*
1341 * structure for MII Management Address reg in mac address map.
1342 * located at address 0x5028
1343 * 31-13: reserved
1344 * 12-8: phy addr
1345 * 7-5: reserved
1346 * 4-0: register
1347 */
1348
1349 #define MII_ADDR(phy,reg) ((phy) << 8 | (reg))
1350
1351 /*
1352 * structure for MII Management Control reg in mac address map.
1353 * located at address 0x502C
1354 * 31-16: reserved
1355 * 15-0: phy control
1356 */
1357
1358 /*
1359 * structure for MII Management Status reg in mac address map.
1360 * located at address 0x5030
1361 * 31-16: reserved
1362 * 15-0: phy control
1363 */
1364
1365 /*
1366 * structure for MII Management Indicators reg in mac address map.
1367 * located at address 0x5034
1368 * 31-3: reserved
1369 * 2: not valid
1370 * 1: scanning
1371 * 0: busy
1372 */
1373
1374 #define MGMT_BUSY 0x00000001 /* busy */
1375 #define MGMT_WAIT 0x00000005 /* busy | not valid */
1376
1377 /*
1378 * structure for Interface Control reg in mac address map.
1379 * located at address 0x5038
1380 *
1381 * 31: reset if module
1382 * 30-28: reserved
1383 * 27: tbi mode
1384 * 26: ghd mode
1385 * 25: lhd mode
1386 * 24: phy mode
1387 * 23: reset per mii
1388 * 22-17: reserved
1389 * 16: speed
1390 * 15: reset pe100x
1391 * 14-11: reserved
1392 * 10: force quiet
1393 * 9: no cipher
1394 * 8: disable link fail
1395 * 7: reset gpsi
1396 * 6-1: reserved
1397 * 0: enable jabber protection
1398 */
1399
1400 /*
1401 * structure for Interface Status reg in mac address map.
1402 * located at address 0x503C
1403 */
1404 typedef union _MAC_IF_STAT_t {
1405 u32 value;
1406 struct {
1407 #ifdef _BIT_FIELDS_HTOL
1408 u32 reserved:22; /* bits 10-31 */
1409 u32 excess_defer:1; /* bit 9 */
1410 u32 clash:1; /* bit 8 */
1411 u32 phy_jabber:1; /* bit 7 */
1412 u32 phy_link_ok:1; /* bit 6 */
1413 u32 phy_full_duplex:1; /* bit 5 */
1414 u32 phy_speed:1; /* bit 4 */
1415 u32 pe100x_link_fail:1; /* bit 3 */
1416 u32 pe10t_loss_carrie:1; /* bit 2 */
1417 u32 pe10t_sqe_error:1; /* bit 1 */
1418 u32 pe10t_jabber:1; /* bit 0 */
1419 #else
1420 u32 pe10t_jabber:1; /* bit 0 */
1421 u32 pe10t_sqe_error:1; /* bit 1 */
1422 u32 pe10t_loss_carrie:1; /* bit 2 */
1423 u32 pe100x_link_fail:1; /* bit 3 */
1424 u32 phy_speed:1; /* bit 4 */
1425 u32 phy_full_duplex:1; /* bit 5 */
1426 u32 phy_link_ok:1; /* bit 6 */
1427 u32 phy_jabber:1; /* bit 7 */
1428 u32 clash:1; /* bit 8 */
1429 u32 excess_defer:1; /* bit 9 */
1430 u32 reserved:22; /* bits 10-31 */
1431 #endif
1432 } bits;
1433 } MAC_IF_STAT_t, *PMAC_IF_STAT_t;
1434
1435 /*
1436 * structure for Mac Station Address, Part 1 reg in mac address map.
1437 * located at address 0x5040
1438 */
1439 typedef union _MAC_STATION_ADDR1_t {
1440 u32 value;
1441 struct {
1442 #ifdef _BIT_FIELDS_HTOL
1443 u32 Octet6:8; /* bits 24-31 */
1444 u32 Octet5:8; /* bits 16-23 */
1445 u32 Octet4:8; /* bits 8-15 */
1446 u32 Octet3:8; /* bits 0-7 */
1447 #else
1448 u32 Octet3:8; /* bits 0-7 */
1449 u32 Octet4:8; /* bits 8-15 */
1450 u32 Octet5:8; /* bits 16-23 */
1451 u32 Octet6:8; /* bits 24-31 */
1452 #endif
1453 } bits;
1454 } MAC_STATION_ADDR1_t, *PMAC_STATION_ADDR1_t;
1455
1456 /*
1457 * structure for Mac Station Address, Part 2 reg in mac address map.
1458 * located at address 0x5044
1459 */
1460 typedef union _MAC_STATION_ADDR2_t {
1461 u32 value;
1462 struct {
1463 #ifdef _BIT_FIELDS_HTOL
1464 u32 Octet2:8; /* bits 24-31 */
1465 u32 Octet1:8; /* bits 16-23 */
1466 u32 reserved:16; /* bits 0-15 */
1467 #else
1468 u32 reserved:16; /* bit 0-15 */
1469 u32 Octet1:8; /* bits 16-23 */
1470 u32 Octet2:8; /* bits 24-31 */
1471 #endif
1472 } bits;
1473 } MAC_STATION_ADDR2_t, *PMAC_STATION_ADDR2_t;
1474
1475 /*
1476 * MAC Module of JAGCore Address Mapping
1477 */
1478 typedef struct _MAC_t { /* Location: */
1479 u32 cfg1; /* 0x5000 */
1480 u32 cfg2; /* 0x5004 */
1481 u32 ipg; /* 0x5008 */
1482 u32 hfdp; /* 0x500C */
1483 u32 max_fm_len; /* 0x5010 */
1484 u32 rsv1; /* 0x5014 */
1485 u32 rsv2; /* 0x5018 */
1486 u32 mac_test; /* 0x501C */
1487 u32 mii_mgmt_cfg; /* 0x5020 */
1488 u32 mii_mgmt_cmd; /* 0x5024 */
1489 u32 mii_mgmt_addr; /* 0x5028 */
1490 u32 mii_mgmt_ctrl; /* 0x502C */
1491 u32 mii_mgmt_stat; /* 0x5030 */
1492 u32 mii_mgmt_indicator; /* 0x5034 */
1493 u32 if_ctrl; /* 0x5038 */
1494 MAC_IF_STAT_t if_stat; /* 0x503C */
1495 MAC_STATION_ADDR1_t station_addr_1; /* 0x5040 */
1496 MAC_STATION_ADDR2_t station_addr_2; /* 0x5044 */
1497 } MAC_t, *PMAC_t;
1498
1499 /* END OF MAC REGISTER ADDRESS MAP */
1500
1501 /* START OF MAC STAT REGISTER ADDRESS MAP */
1502
1503 /*
1504 * structure for Carry Register One and it's Mask Register reg located in mac
1505 * stat address map address 0x6130 and 0x6138.
1506 *
1507 * 31: tr64
1508 * 30: tr127
1509 * 29: tr255
1510 * 28: tr511
1511 * 27: tr1k
1512 * 26: trmax
1513 * 25: trmgv
1514 * 24-17: unused
1515 * 16: rbyt
1516 * 15: rpkt
1517 * 14: rfcs
1518 * 13: rmca
1519 * 12: rbca
1520 * 11: rxcf
1521 * 10: rxpf
1522 * 9: rxuo
1523 * 8: raln
1524 * 7: rflr
1525 * 6: rcde
1526 * 5: rcse
1527 * 4: rund
1528 * 3: rovr
1529 * 2: rfrg
1530 * 1: rjbr
1531 * 0: rdrp
1532 */
1533
1534 /*
1535 * structure for Carry Register Two Mask Register reg in mac stat address map.
1536 * located at address 0x613C
1537 *
1538 * 31-20: unused
1539 * 19: tjbr
1540 * 18: tfcs
1541 * 17: txcf
1542 * 16: tovr
1543 * 15: tund
1544 * 14: trfg
1545 * 13: tbyt
1546 * 12: tpkt
1547 * 11: tmca
1548 * 10: tbca
1549 * 9: txpf
1550 * 8: tdfr
1551 * 7: tedf
1552 * 6: tscl
1553 * 5: tmcl
1554 * 4: tlcl
1555 * 3: txcl
1556 * 2: tncl
1557 * 1: tpfh
1558 * 0: tdrp
1559 */
1560
1561 /*
1562 * MAC STATS Module of JAGCore Address Mapping
1563 */
1564 typedef struct _MAC_STAT_t { /* Location: */
1565 u32 pad[32]; /* 0x6000 - 607C */
1566
1567 /* Tx/Rx 0-64 Byte Frame Counter */
1568 u32 TR64; /* 0x6080 */
1569
1570 /* Tx/Rx 65-127 Byte Frame Counter */
1571 u32 TR127; /* 0x6084 */
1572
1573 /* Tx/Rx 128-255 Byte Frame Counter */
1574 u32 TR255; /* 0x6088 */
1575
1576 /* Tx/Rx 256-511 Byte Frame Counter */
1577 u32 TR511; /* 0x608C */
1578
1579 /* Tx/Rx 512-1023 Byte Frame Counter */
1580 u32 TR1K; /* 0x6090 */
1581
1582 /* Tx/Rx 1024-1518 Byte Frame Counter */
1583 u32 TRMax; /* 0x6094 */
1584
1585 /* Tx/Rx 1519-1522 Byte Good VLAN Frame Count */
1586 u32 TRMgv; /* 0x6098 */
1587
1588 /* Rx Byte Counter */
1589 u32 RByt; /* 0x609C */
1590
1591 /* Rx Packet Counter */
1592 u32 RPkt; /* 0x60A0 */
1593
1594 /* Rx FCS Error Counter */
1595 u32 RFcs; /* 0x60A4 */
1596
1597 /* Rx Multicast Packet Counter */
1598 u32 RMca; /* 0x60A8 */
1599
1600 /* Rx Broadcast Packet Counter */
1601 u32 RBca; /* 0x60AC */
1602
1603 /* Rx Control Frame Packet Counter */
1604 u32 RxCf; /* 0x60B0 */
1605
1606 /* Rx Pause Frame Packet Counter */
1607 u32 RxPf; /* 0x60B4 */
1608
1609 /* Rx Unknown OP Code Counter */
1610 u32 RxUo; /* 0x60B8 */
1611
1612 /* Rx Alignment Error Counter */
1613 u32 RAln; /* 0x60BC */
1614
1615 /* Rx Frame Length Error Counter */
1616 u32 RFlr; /* 0x60C0 */
1617
1618 /* Rx Code Error Counter */
1619 u32 RCde; /* 0x60C4 */
1620
1621 /* Rx Carrier Sense Error Counter */
1622 u32 RCse; /* 0x60C8 */
1623
1624 /* Rx Undersize Packet Counter */
1625 u32 RUnd; /* 0x60CC */
1626
1627 /* Rx Oversize Packet Counter */
1628 u32 ROvr; /* 0x60D0 */
1629
1630 /* Rx Fragment Counter */
1631 u32 RFrg; /* 0x60D4 */
1632
1633 /* Rx Jabber Counter */
1634 u32 RJbr; /* 0x60D8 */
1635
1636 /* Rx Drop */
1637 u32 RDrp; /* 0x60DC */
1638
1639 /* Tx Byte Counter */
1640 u32 TByt; /* 0x60E0 */
1641
1642 /* Tx Packet Counter */
1643 u32 TPkt; /* 0x60E4 */
1644
1645 /* Tx Multicast Packet Counter */
1646 u32 TMca; /* 0x60E8 */
1647
1648 /* Tx Broadcast Packet Counter */
1649 u32 TBca; /* 0x60EC */
1650
1651 /* Tx Pause Control Frame Counter */
1652 u32 TxPf; /* 0x60F0 */
1653
1654 /* Tx Deferral Packet Counter */
1655 u32 TDfr; /* 0x60F4 */
1656
1657 /* Tx Excessive Deferral Packet Counter */
1658 u32 TEdf; /* 0x60F8 */
1659
1660 /* Tx Single Collision Packet Counter */
1661 u32 TScl; /* 0x60FC */
1662
1663 /* Tx Multiple Collision Packet Counter */
1664 u32 TMcl; /* 0x6100 */
1665
1666 /* Tx Late Collision Packet Counter */
1667 u32 TLcl; /* 0x6104 */
1668
1669 /* Tx Excessive Collision Packet Counter */
1670 u32 TXcl; /* 0x6108 */
1671
1672 /* Tx Total Collision Packet Counter */
1673 u32 TNcl; /* 0x610C */
1674
1675 /* Tx Pause Frame Honored Counter */
1676 u32 TPfh; /* 0x6110 */
1677
1678 /* Tx Drop Frame Counter */
1679 u32 TDrp; /* 0x6114 */
1680
1681 /* Tx Jabber Frame Counter */
1682 u32 TJbr; /* 0x6118 */
1683
1684 /* Tx FCS Error Counter */
1685 u32 TFcs; /* 0x611C */
1686
1687 /* Tx Control Frame Counter */
1688 u32 TxCf; /* 0x6120 */
1689
1690 /* Tx Oversize Frame Counter */
1691 u32 TOvr; /* 0x6124 */
1692
1693 /* Tx Undersize Frame Counter */
1694 u32 TUnd; /* 0x6128 */
1695
1696 /* Tx Fragments Frame Counter */
1697 u32 TFrg; /* 0x612C */
1698
1699 /* Carry Register One Register */
1700 u32 Carry1; /* 0x6130 */
1701
1702 /* Carry Register Two Register */
1703 u32 Carry2; /* 0x6134 */
1704
1705 /* Carry Register One Mask Register */
1706 u32 Carry1M; /* 0x6138 */
1707
1708 /* Carry Register Two Mask Register */
1709 u32 Carry2M; /* 0x613C */
1710 } MAC_STAT_t, *PMAC_STAT_t;
1711
1712 /* END OF MAC STAT REGISTER ADDRESS MAP */
1713
1714
1715 /* START OF MMC REGISTER ADDRESS MAP */
1716
1717 /*
1718 * Main Memory Controller Control reg in mmc address map.
1719 * located at address 0x7000
1720 */
1721
1722 #define ET_MMC_ENABLE 1
1723 #define ET_MMC_ARB_DISABLE 2
1724 #define ET_MMC_RXMAC_DISABLE 4
1725 #define ET_MMC_TXMAC_DISABLE 8
1726 #define ET_MMC_TXDMA_DISABLE 16
1727 #define ET_MMC_RXDMA_DISABLE 32
1728 #define ET_MMC_FORCE_CE 64
1729
1730 /*
1731 * Main Memory Controller Host Memory Access Address reg in mmc
1732 * address map. Located at address 0x7004. Top 16 bits hold the address bits
1733 */
1734
1735 #define ET_SRAM_REQ_ACCESS 1
1736 #define ET_SRAM_WR_ACCESS 2
1737 #define ET_SRAM_IS_CTRL 4
1738
1739 /*
1740 * structure for Main Memory Controller Host Memory Access Data reg in mmc
1741 * address map. Located at address 0x7008 - 0x7014
1742 * Defined earlier (u32)
1743 */
1744
1745 /*
1746 * Memory Control Module of JAGCore Address Mapping
1747 */
1748 typedef struct _MMC_t { /* Location: */
1749 u32 mmc_ctrl; /* 0x7000 */
1750 u32 sram_access; /* 0x7004 */
1751 u32 sram_word1; /* 0x7008 */
1752 u32 sram_word2; /* 0x700C */
1753 u32 sram_word3; /* 0x7010 */
1754 u32 sram_word4; /* 0x7014 */
1755 } MMC_t, *PMMC_t;
1756
1757 /* END OF MMC REGISTER ADDRESS MAP */
1758
1759
1760 /* START OF EXP ROM REGISTER ADDRESS MAP */
1761
1762 /*
1763 * Expansion ROM Module of JAGCore Address Mapping
1764 */
1765
1766 /* Take this out until it is not empty */
1767 #if 0
1768 typedef struct _EXP_ROM_t {
1769
1770 } EXP_ROM_t, *PEXP_ROM_t;
1771 #endif
1772
1773 /* END OF EXP ROM REGISTER ADDRESS MAP */
1774
1775
1776 /*
1777 * JAGCore Address Mapping
1778 */
1779 typedef struct _ADDRESS_MAP_t {
1780 GLOBAL_t global;
1781 /* unused section of global address map */
1782 u8 unused_global[4096 - sizeof(GLOBAL_t)];
1783 TXDMA_t txdma;
1784 /* unused section of txdma address map */
1785 u8 unused_txdma[4096 - sizeof(TXDMA_t)];
1786 RXDMA_t rxdma;
1787 /* unused section of rxdma address map */
1788 u8 unused_rxdma[4096 - sizeof(RXDMA_t)];
1789 TXMAC_t txmac;
1790 /* unused section of txmac address map */
1791 u8 unused_txmac[4096 - sizeof(TXMAC_t)];
1792 RXMAC_t rxmac;
1793 /* unused section of rxmac address map */
1794 u8 unused_rxmac[4096 - sizeof(RXMAC_t)];
1795 MAC_t mac;
1796 /* unused section of mac address map */
1797 u8 unused_mac[4096 - sizeof(MAC_t)];
1798 MAC_STAT_t macStat;
1799 /* unused section of mac stat address map */
1800 u8 unused_mac_stat[4096 - sizeof(MAC_STAT_t)];
1801 MMC_t mmc;
1802 /* unused section of mmc address map */
1803 u8 unused_mmc[4096 - sizeof(MMC_t)];
1804 /* unused section of address map */
1805 u8 unused_[1015808];
1806
1807 /* Take this out until it is not empty */
1808 #if 0
1809 EXP_ROM_t exp_rom;
1810 #endif
1811
1812 u8 unused_exp_rom[4096]; /* MGS-size TBD */
1813 u8 unused__[524288]; /* unused section of address map */
1814 } ADDRESS_MAP_t, *PADDRESS_MAP_t;
1815
1816 #endif /* _ET1310_ADDRESS_MAP_H_ */
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