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ALSA: hda - Pull pages allocation to hda_controller
[linux-2.6/btrfs-unstable.git] / sound / pci / hda / hda_intel.c
blob4a0b228d70f7b4f46ae37b961549689fd6e0fa8f
1 /*
2 *
3 * hda_intel.c - Implementation of primary alsa driver code base
4 * for Intel HD Audio.
5 *
6 * Copyright(c) 2004 Intel Corporation. All rights reserved.
7 *
8 * Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
9 * PeiSen Hou <pshou@realtek.com.tw>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the Free
13 * Software Foundation; either version 2 of the License, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
19 * more details.
20 *
21 * You should have received a copy of the GNU General Public License along with
22 * this program; if not, write to the Free Software Foundation, Inc., 59
23 * Temple Place - Suite 330, Boston, MA 02111-1307, USA.
24 *
25 * CONTACTS:
26 *
27 * Matt Jared matt.jared@intel.com
28 * Andy Kopp andy.kopp@intel.com
29 * Dan Kogan dan.d.kogan@intel.com
30 *
31 * CHANGES:
32 *
33 * 2004.12.01 Major rewrite by tiwai, merged the work of pshou
34 *
35 */
36
37 #include <linux/delay.h>
38 #include <linux/interrupt.h>
39 #include <linux/kernel.h>
40 #include <linux/module.h>
41 #include <linux/dma-mapping.h>
42 #include <linux/moduleparam.h>
43 #include <linux/init.h>
44 #include <linux/slab.h>
45 #include <linux/pci.h>
46 #include <linux/mutex.h>
47 #include <linux/reboot.h>
48 #include <linux/io.h>
49 #include <linux/pm_runtime.h>
50 #include <linux/clocksource.h>
51 #include <linux/time.h>
52 #include <linux/completion.h>
53
54 #ifdef CONFIG_X86
55 /* for snoop control */
56 #include <asm/pgtable.h>
57 #include <asm/cacheflush.h>
58 #endif
59 #include <sound/core.h>
60 #include <sound/initval.h>
61 #include <linux/vgaarb.h>
62 #include <linux/vga_switcheroo.h>
63 #include <linux/firmware.h>
64 #include "hda_codec.h"
65 #include "hda_i915.h"
66 #include "hda_controller.h"
67 #include "hda_priv.h"
68
69
70 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
71 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
72 static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
73 static char *model[SNDRV_CARDS];
74 static int position_fix[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
75 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
76 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
77 static int probe_only[SNDRV_CARDS];
78 static int jackpoll_ms[SNDRV_CARDS];
79 static bool single_cmd;
80 static int enable_msi = -1;
81 #ifdef CONFIG_SND_HDA_PATCH_LOADER
82 static char *patch[SNDRV_CARDS];
83 #endif
84 #ifdef CONFIG_SND_HDA_INPUT_BEEP
85 static bool beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
86 CONFIG_SND_HDA_INPUT_BEEP_MODE};
87 #endif
88
89 module_param_array(index, int, NULL, 0444);
90 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
91 module_param_array(id, charp, NULL, 0444);
92 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
93 module_param_array(enable, bool, NULL, 0444);
94 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
95 module_param_array(model, charp, NULL, 0444);
96 MODULE_PARM_DESC(model, "Use the given board model.");
97 module_param_array(position_fix, int, NULL, 0444);
98 MODULE_PARM_DESC(position_fix, "DMA pointer read method."
99 "(-1 = system default, 0 = auto, 1 = LPIB, 2 = POSBUF, 3 = VIACOMBO, 4 = COMBO).");
100 module_param_array(bdl_pos_adj, int, NULL, 0644);
101 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
102 module_param_array(probe_mask, int, NULL, 0444);
103 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
104 module_param_array(probe_only, int, NULL, 0444);
105 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
106 module_param_array(jackpoll_ms, int, NULL, 0444);
107 MODULE_PARM_DESC(jackpoll_ms, "Ms between polling for jack events (default = 0, using unsol events only)");
108 module_param(single_cmd, bool, 0444);
109 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
110 "(for debugging only).");
111 module_param(enable_msi, bint, 0444);
112 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
113 #ifdef CONFIG_SND_HDA_PATCH_LOADER
114 module_param_array(patch, charp, NULL, 0444);
115 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
116 #endif
117 #ifdef CONFIG_SND_HDA_INPUT_BEEP
118 module_param_array(beep_mode, bool, NULL, 0444);
119 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
120 "(0=off, 1=on) (default=1).");
121 #endif
122
123 #ifdef CONFIG_PM
124 static int param_set_xint(const char *val, const struct kernel_param *kp);
125 static struct kernel_param_ops param_ops_xint = {
126 .set = param_set_xint,
127 .get = param_get_int,
128 };
129 #define param_check_xint param_check_int
130
131 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
132 static int *power_save_addr = &power_save;
133 module_param(power_save, xint, 0644);
134 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
135 "(in second, 0 = disable).");
136
137 /* reset the HD-audio controller in power save mode.
138 * this may give more power-saving, but will take longer time to
139 * wake up.
140 */
141 static bool power_save_controller = 1;
142 module_param(power_save_controller, bool, 0644);
143 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
144 #else
145 static int *power_save_addr;
146 #endif /* CONFIG_PM */
147
148 static int align_buffer_size = -1;
149 module_param(align_buffer_size, bint, 0644);
150 MODULE_PARM_DESC(align_buffer_size,
151 "Force buffer and period sizes to be multiple of 128 bytes.");
152
153 #ifdef CONFIG_X86
154 static bool hda_snoop = true;
155 module_param_named(snoop, hda_snoop, bool, 0444);
156 MODULE_PARM_DESC(snoop, "Enable/disable snooping");
157 #else
158 #define hda_snoop true
159 #endif
160
161
162 MODULE_LICENSE("GPL");
163 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
164 "{Intel, ICH6M},"
165 "{Intel, ICH7},"
166 "{Intel, ESB2},"
167 "{Intel, ICH8},"
168 "{Intel, ICH9},"
169 "{Intel, ICH10},"
170 "{Intel, PCH},"
171 "{Intel, CPT},"
172 "{Intel, PPT},"
173 "{Intel, LPT},"
174 "{Intel, LPT_LP},"
175 "{Intel, WPT_LP},"
176 "{Intel, HPT},"
177 "{Intel, PBG},"
178 "{Intel, SCH},"
179 "{ATI, SB450},"
180 "{ATI, SB600},"
181 "{ATI, RS600},"
182 "{ATI, RS690},"
183 "{ATI, RS780},"
184 "{ATI, R600},"
185 "{ATI, RV630},"
186 "{ATI, RV610},"
187 "{ATI, RV670},"
188 "{ATI, RV635},"
189 "{ATI, RV620},"
190 "{ATI, RV770},"
191 "{VIA, VT8251},"
192 "{VIA, VT8237A},"
193 "{SiS, SIS966},"
194 "{ULI, M5461}}");
195 MODULE_DESCRIPTION("Intel HDA driver");
196
197 #if defined(CONFIG_PM) && defined(CONFIG_VGA_SWITCHEROO)
198 #if IS_ENABLED(CONFIG_SND_HDA_CODEC_HDMI)
199 #define SUPPORT_VGA_SWITCHEROO
200 #endif
201 #endif
202
203
204 /*
205 */
206
207 /* driver types */
208 enum {
209 AZX_DRIVER_ICH,
210 AZX_DRIVER_PCH,
211 AZX_DRIVER_SCH,
212 AZX_DRIVER_HDMI,
213 AZX_DRIVER_ATI,
214 AZX_DRIVER_ATIHDMI,
215 AZX_DRIVER_ATIHDMI_NS,
216 AZX_DRIVER_VIA,
217 AZX_DRIVER_SIS,
218 AZX_DRIVER_ULI,
219 AZX_DRIVER_NVIDIA,
220 AZX_DRIVER_TERA,
221 AZX_DRIVER_CTX,
222 AZX_DRIVER_CTHDA,
223 AZX_DRIVER_GENERIC,
224 AZX_NUM_DRIVERS, /* keep this as last entry */
225 };
226
227 /* quirks for Intel PCH */
228 #define AZX_DCAPS_INTEL_PCH_NOPM \
229 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_BUFSIZE | \
230 AZX_DCAPS_COUNT_LPIB_DELAY)
231
232 #define AZX_DCAPS_INTEL_PCH \
233 (AZX_DCAPS_INTEL_PCH_NOPM | AZX_DCAPS_PM_RUNTIME)
234
235 #define AZX_DCAPS_INTEL_HASWELL \
236 (AZX_DCAPS_SCH_SNOOP | AZX_DCAPS_ALIGN_BUFSIZE | \
237 AZX_DCAPS_COUNT_LPIB_DELAY | AZX_DCAPS_PM_RUNTIME | \
238 AZX_DCAPS_I915_POWERWELL)
239
240 /* quirks for ATI SB / AMD Hudson */
241 #define AZX_DCAPS_PRESET_ATI_SB \
242 (AZX_DCAPS_ATI_SNOOP | AZX_DCAPS_NO_TCSEL | \
243 AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
244
245 /* quirks for ATI/AMD HDMI */
246 #define AZX_DCAPS_PRESET_ATI_HDMI \
247 (AZX_DCAPS_NO_TCSEL | AZX_DCAPS_SYNC_WRITE | AZX_DCAPS_POSFIX_LPIB)
248
249 /* quirks for Nvidia */
250 #define AZX_DCAPS_PRESET_NVIDIA \
251 (AZX_DCAPS_NVIDIA_SNOOP | AZX_DCAPS_RIRB_DELAY | AZX_DCAPS_NO_MSI |\
252 AZX_DCAPS_ALIGN_BUFSIZE | AZX_DCAPS_NO_64BIT)
253
254 #define AZX_DCAPS_PRESET_CTHDA \
255 (AZX_DCAPS_NO_MSI | AZX_DCAPS_POSFIX_LPIB | AZX_DCAPS_4K_BDLE_BOUNDARY)
256
257 /*
258 * VGA-switcher support
259 */
260 #ifdef SUPPORT_VGA_SWITCHEROO
261 #define use_vga_switcheroo(chip) ((chip)->use_vga_switcheroo)
262 #else
263 #define use_vga_switcheroo(chip) 0
264 #endif
265
266 static char *driver_short_names[] = {
267 [AZX_DRIVER_ICH] = "HDA Intel",
268 [AZX_DRIVER_PCH] = "HDA Intel PCH",
269 [AZX_DRIVER_SCH] = "HDA Intel MID",
270 [AZX_DRIVER_HDMI] = "HDA Intel HDMI",
271 [AZX_DRIVER_ATI] = "HDA ATI SB",
272 [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
273 [AZX_DRIVER_ATIHDMI_NS] = "HDA ATI HDMI",
274 [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
275 [AZX_DRIVER_SIS] = "HDA SIS966",
276 [AZX_DRIVER_ULI] = "HDA ULI M5461",
277 [AZX_DRIVER_NVIDIA] = "HDA NVidia",
278 [AZX_DRIVER_TERA] = "HDA Teradici",
279 [AZX_DRIVER_CTX] = "HDA Creative",
280 [AZX_DRIVER_CTHDA] = "HDA Creative",
281 [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
282 };
283
284 #ifdef CONFIG_X86
285 static void __mark_pages_wc(struct azx *chip, struct snd_dma_buffer *dmab, bool on)
286 {
287 int pages;
288
289 if (azx_snoop(chip))
290 return;
291 if (!dmab || !dmab->area || !dmab->bytes)
292 return;
293
294 #ifdef CONFIG_SND_DMA_SGBUF
295 if (dmab->dev.type == SNDRV_DMA_TYPE_DEV_SG) {
296 struct snd_sg_buf *sgbuf = dmab->private_data;
297 if (on)
298 set_pages_array_wc(sgbuf->page_table, sgbuf->pages);
299 else
300 set_pages_array_wb(sgbuf->page_table, sgbuf->pages);
301 return;
302 }
303 #endif
304
305 pages = (dmab->bytes + PAGE_SIZE - 1) >> PAGE_SHIFT;
306 if (on)
307 set_memory_wc((unsigned long)dmab->area, pages);
308 else
309 set_memory_wb((unsigned long)dmab->area, pages);
310 }
311
312 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
313 bool on)
314 {
315 __mark_pages_wc(chip, buf, on);
316 }
317 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
318 struct snd_pcm_substream *substream, bool on)
319 {
320 if (azx_dev->wc_marked != on) {
321 __mark_pages_wc(chip, snd_pcm_get_dma_buf(substream), on);
322 azx_dev->wc_marked = on;
323 }
324 }
325 #else
326 /* NOP for other archs */
327 static inline void mark_pages_wc(struct azx *chip, struct snd_dma_buffer *buf,
328 bool on)
329 {
330 }
331 static inline void mark_runtime_wc(struct azx *chip, struct azx_dev *azx_dev,
332 struct snd_pcm_substream *substream, bool on)
333 {
334 }
335 #endif
336
337 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
338 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
339 /*
340 * Interface for HD codec
341 */
342
343 /*
344 * CORB / RIRB interface
345 */
346 static int azx_alloc_cmd_io(struct azx *chip)
347 {
348 int err;
349
350 /* single page (at least 4096 bytes) must suffice for both ringbuffes */
351 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV,
352 PAGE_SIZE, &chip->rb);
353 if (err < 0)
354 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
355 return err;
356 }
357
358 static void azx_init_cmd_io(struct azx *chip)
359 {
360 int timeout;
361
362 spin_lock_irq(&chip->reg_lock);
363 /* CORB set up */
364 chip->corb.addr = chip->rb.addr;
365 chip->corb.buf = (u32 *)chip->rb.area;
366 azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
367 azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
368
369 /* set the corb size to 256 entries (ULI requires explicitly) */
370 azx_writeb(chip, CORBSIZE, 0x02);
371 /* set the corb write pointer to 0 */
372 azx_writew(chip, CORBWP, 0);
373
374 /* reset the corb hw read pointer */
375 azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
376 for (timeout = 1000; timeout > 0; timeout--) {
377 if ((azx_readw(chip, CORBRP) & ICH6_CORBRP_RST) == ICH6_CORBRP_RST)
378 break;
379 udelay(1);
380 }
381 if (timeout <= 0)
382 dev_err(chip->card->dev, "CORB reset timeout#1, CORBRP = %d\n",
383 azx_readw(chip, CORBRP));
384
385 azx_writew(chip, CORBRP, 0);
386 for (timeout = 1000; timeout > 0; timeout--) {
387 if (azx_readw(chip, CORBRP) == 0)
388 break;
389 udelay(1);
390 }
391 if (timeout <= 0)
392 dev_err(chip->card->dev, "CORB reset timeout#2, CORBRP = %d\n",
393 azx_readw(chip, CORBRP));
394
395 /* enable corb dma */
396 azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
397
398 /* RIRB set up */
399 chip->rirb.addr = chip->rb.addr + 2048;
400 chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
401 chip->rirb.wp = chip->rirb.rp = 0;
402 memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
403 azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
404 azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
405
406 /* set the rirb size to 256 entries (ULI requires explicitly) */
407 azx_writeb(chip, RIRBSIZE, 0x02);
408 /* reset the rirb hw write pointer */
409 azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
410 /* set N=1, get RIRB response interrupt for new entry */
411 if (chip->driver_caps & AZX_DCAPS_CTX_WORKAROUND)
412 azx_writew(chip, RINTCNT, 0xc0);
413 else
414 azx_writew(chip, RINTCNT, 1);
415 /* enable rirb dma and response irq */
416 azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
417 spin_unlock_irq(&chip->reg_lock);
418 }
419
420 static void azx_free_cmd_io(struct azx *chip)
421 {
422 spin_lock_irq(&chip->reg_lock);
423 /* disable ringbuffer DMAs */
424 azx_writeb(chip, RIRBCTL, 0);
425 azx_writeb(chip, CORBCTL, 0);
426 spin_unlock_irq(&chip->reg_lock);
427 }
428
429 static unsigned int azx_command_addr(u32 cmd)
430 {
431 unsigned int addr = cmd >> 28;
432
433 if (addr >= AZX_MAX_CODECS) {
434 snd_BUG();
435 addr = 0;
436 }
437
438 return addr;
439 }
440
441 /* send a command */
442 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
443 {
444 struct azx *chip = bus->private_data;
445 unsigned int addr = azx_command_addr(val);
446 unsigned int wp, rp;
447
448 spin_lock_irq(&chip->reg_lock);
449
450 /* add command to corb */
451 wp = azx_readw(chip, CORBWP);
452 if (wp == 0xffff) {
453 /* something wrong, controller likely turned to D3 */
454 spin_unlock_irq(&chip->reg_lock);
455 return -EIO;
456 }
457 wp++;
458 wp %= ICH6_MAX_CORB_ENTRIES;
459
460 rp = azx_readw(chip, CORBRP);
461 if (wp == rp) {
462 /* oops, it's full */
463 spin_unlock_irq(&chip->reg_lock);
464 return -EAGAIN;
465 }
466
467 chip->rirb.cmds[addr]++;
468 chip->corb.buf[wp] = cpu_to_le32(val);
469 azx_writew(chip, CORBWP, wp);
470
471 spin_unlock_irq(&chip->reg_lock);
472
473 return 0;
474 }
475
476 #define ICH6_RIRB_EX_UNSOL_EV (1<<4)
477
478 /* retrieve RIRB entry - called from interrupt handler */
479 static void azx_update_rirb(struct azx *chip)
480 {
481 unsigned int rp, wp;
482 unsigned int addr;
483 u32 res, res_ex;
484
485 wp = azx_readw(chip, RIRBWP);
486 if (wp == 0xffff) {
487 /* something wrong, controller likely turned to D3 */
488 return;
489 }
490
491 if (wp == chip->rirb.wp)
492 return;
493 chip->rirb.wp = wp;
494
495 while (chip->rirb.rp != wp) {
496 chip->rirb.rp++;
497 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
498
499 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
500 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
501 res = le32_to_cpu(chip->rirb.buf[rp]);
502 addr = res_ex & 0xf;
503 if ((addr >= AZX_MAX_CODECS) || !(chip->codec_mask & (1 << addr))) {
504 dev_err(chip->card->dev, "spurious response %#x:%#x, rp = %d, wp = %d",
505 res, res_ex,
506 chip->rirb.rp, wp);
507 snd_BUG();
508 }
509 else if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
510 snd_hda_queue_unsol_event(chip->bus, res, res_ex);
511 else if (chip->rirb.cmds[addr]) {
512 chip->rirb.res[addr] = res;
513 smp_wmb();
514 chip->rirb.cmds[addr]--;
515 } else if (printk_ratelimit()) {
516 dev_err(chip->card->dev, "spurious response %#x:%#x, last cmd=%#08x\n",
517 res, res_ex,
518 chip->last_cmd[addr]);
519 }
520 }
521 }
522
523 /* receive a response */
524 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
525 unsigned int addr)
526 {
527 struct azx *chip = bus->private_data;
528 unsigned long timeout;
529 unsigned long loopcounter;
530 int do_poll = 0;
531
532 again:
533 timeout = jiffies + msecs_to_jiffies(1000);
534
535 for (loopcounter = 0;; loopcounter++) {
536 if (chip->polling_mode || do_poll) {
537 spin_lock_irq(&chip->reg_lock);
538 azx_update_rirb(chip);
539 spin_unlock_irq(&chip->reg_lock);
540 }
541 if (!chip->rirb.cmds[addr]) {
542 smp_rmb();
543 bus->rirb_error = 0;
544
545 if (!do_poll)
546 chip->poll_count = 0;
547 return chip->rirb.res[addr]; /* the last value */
548 }
549 if (time_after(jiffies, timeout))
550 break;
551 if (bus->needs_damn_long_delay || loopcounter > 3000)
552 msleep(2); /* temporary workaround */
553 else {
554 udelay(10);
555 cond_resched();
556 }
557 }
558
559 if (!bus->no_response_fallback)
560 return -1;
561
562 if (!chip->polling_mode && chip->poll_count < 2) {
563 dev_dbg(chip->card->dev,
564 "azx_get_response timeout, polling the codec once: last cmd=0x%08x\n",
565 chip->last_cmd[addr]);
566 do_poll = 1;
567 chip->poll_count++;
568 goto again;
569 }
570
571
572 if (!chip->polling_mode) {
573 dev_warn(chip->card->dev,
574 "azx_get_response timeout, switching to polling mode: last cmd=0x%08x\n",
575 chip->last_cmd[addr]);
576 chip->polling_mode = 1;
577 goto again;
578 }
579
580 if (chip->msi) {
581 dev_warn(chip->card->dev,
582 "No response from codec, disabling MSI: last cmd=0x%08x\n",
583 chip->last_cmd[addr]);
584 if (chip->ops->disable_msi_reset_irq &&
585 chip->ops->disable_msi_reset_irq(chip) < 0) {
586 bus->rirb_error = 1;
587 return -1;
588 }
589 goto again;
590 }
591
592 if (chip->probing) {
593 /* If this critical timeout happens during the codec probing
594 * phase, this is likely an access to a non-existing codec
595 * slot. Better to return an error and reset the system.
596 */
597 return -1;
598 }
599
600 /* a fatal communication error; need either to reset or to fallback
601 * to the single_cmd mode
602 */
603 bus->rirb_error = 1;
604 if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
605 bus->response_reset = 1;
606 return -1; /* give a chance to retry */
607 }
608
609 dev_err(chip->card->dev,
610 "azx_get_response timeout, switching to single_cmd mode: last cmd=0x%08x\n",
611 chip->last_cmd[addr]);
612 chip->single_cmd = 1;
613 bus->response_reset = 0;
614 /* release CORB/RIRB */
615 azx_free_cmd_io(chip);
616 /* disable unsolicited responses */
617 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
618 return -1;
619 }
620
621 /*
622 * Use the single immediate command instead of CORB/RIRB for simplicity
623 *
624 * Note: according to Intel, this is not preferred use. The command was
625 * intended for the BIOS only, and may get confused with unsolicited
626 * responses. So, we shouldn't use it for normal operation from the
627 * driver.
628 * I left the codes, however, for debugging/testing purposes.
629 */
630
631 /* receive a response */
632 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
633 {
634 int timeout = 50;
635
636 while (timeout--) {
637 /* check IRV busy bit */
638 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
639 /* reuse rirb.res as the response return value */
640 chip->rirb.res[addr] = azx_readl(chip, IR);
641 return 0;
642 }
643 udelay(1);
644 }
645 if (printk_ratelimit())
646 dev_dbg(chip->card->dev, "get_response timeout: IRS=0x%x\n",
647 azx_readw(chip, IRS));
648 chip->rirb.res[addr] = -1;
649 return -EIO;
650 }
651
652 /* send a command */
653 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
654 {
655 struct azx *chip = bus->private_data;
656 unsigned int addr = azx_command_addr(val);
657 int timeout = 50;
658
659 bus->rirb_error = 0;
660 while (timeout--) {
661 /* check ICB busy bit */
662 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
663 /* Clear IRV valid bit */
664 azx_writew(chip, IRS, azx_readw(chip, IRS) |
665 ICH6_IRS_VALID);
666 azx_writel(chip, IC, val);
667 azx_writew(chip, IRS, azx_readw(chip, IRS) |
668 ICH6_IRS_BUSY);
669 return azx_single_wait_for_response(chip, addr);
670 }
671 udelay(1);
672 }
673 if (printk_ratelimit())
674 dev_dbg(chip->card->dev,
675 "send_cmd timeout: IRS=0x%x, val=0x%x\n",
676 azx_readw(chip, IRS), val);
677 return -EIO;
678 }
679
680 /* receive a response */
681 static unsigned int azx_single_get_response(struct hda_bus *bus,
682 unsigned int addr)
683 {
684 struct azx *chip = bus->private_data;
685 return chip->rirb.res[addr];
686 }
687
688 /*
689 * The below are the main callbacks from hda_codec.
690 *
691 * They are just the skeleton to call sub-callbacks according to the
692 * current setting of chip->single_cmd.
693 */
694
695 /* send a command */
696 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
697 {
698 struct azx *chip = bus->private_data;
699
700 if (chip->disabled)
701 return 0;
702 chip->last_cmd[azx_command_addr(val)] = val;
703 if (chip->single_cmd)
704 return azx_single_send_cmd(bus, val);
705 else
706 return azx_corb_send_cmd(bus, val);
707 }
708
709 /* get a response */
710 static unsigned int azx_get_response(struct hda_bus *bus,
711 unsigned int addr)
712 {
713 struct azx *chip = bus->private_data;
714 if (chip->disabled)
715 return 0;
716 if (chip->single_cmd)
717 return azx_single_get_response(bus, addr);
718 else
719 return azx_rirb_get_response(bus, addr);
720 }
721
722 #ifdef CONFIG_PM
723 static void azx_power_notify(struct hda_bus *bus, bool power_up);
724 #endif
725
726 #ifdef CONFIG_SND_HDA_DSP_LOADER
727 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
728 unsigned int byte_size,
729 struct snd_dma_buffer *bufp);
730 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start);
731 static void azx_load_dsp_cleanup(struct hda_bus *bus,
732 struct snd_dma_buffer *dmab);
733 #endif
734
735 /* enter link reset */
736 static void azx_enter_link_reset(struct azx *chip)
737 {
738 unsigned long timeout;
739
740 /* reset controller */
741 azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
742
743 timeout = jiffies + msecs_to_jiffies(100);
744 while ((azx_readb(chip, GCTL) & ICH6_GCTL_RESET) &&
745 time_before(jiffies, timeout))
746 usleep_range(500, 1000);
747 }
748
749 /* exit link reset */
750 static void azx_exit_link_reset(struct azx *chip)
751 {
752 unsigned long timeout;
753
754 azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
755
756 timeout = jiffies + msecs_to_jiffies(100);
757 while (!azx_readb(chip, GCTL) &&
758 time_before(jiffies, timeout))
759 usleep_range(500, 1000);
760 }
761
762 /* reset codec link */
763 static int azx_reset(struct azx *chip, int full_reset)
764 {
765 if (!full_reset)
766 goto __skip;
767
768 /* clear STATESTS */
769 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
770
771 /* reset controller */
772 azx_enter_link_reset(chip);
773
774 /* delay for >= 100us for codec PLL to settle per spec
775 * Rev 0.9 section 5.5.1
776 */
777 usleep_range(500, 1000);
778
779 /* Bring controller out of reset */
780 azx_exit_link_reset(chip);
781
782 /* Brent Chartrand said to wait >= 540us for codecs to initialize */
783 usleep_range(1000, 1200);
784
785 __skip:
786 /* check to see if controller is ready */
787 if (!azx_readb(chip, GCTL)) {
788 dev_dbg(chip->card->dev, "azx_reset: controller not ready!\n");
789 return -EBUSY;
790 }
791
792 /* Accept unsolicited responses */
793 if (!chip->single_cmd)
794 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
795 ICH6_GCTL_UNSOL);
796
797 /* detect codecs */
798 if (!chip->codec_mask) {
799 chip->codec_mask = azx_readw(chip, STATESTS);
800 dev_dbg(chip->card->dev, "codec_mask = 0x%x\n",
801 chip->codec_mask);
802 }
803
804 return 0;
805 }
806
807
808 /*
809 * Lowlevel interface
810 */
811
812 /* enable interrupts */
813 static void azx_int_enable(struct azx *chip)
814 {
815 /* enable controller CIE and GIE */
816 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
817 ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
818 }
819
820 /* disable interrupts */
821 static void azx_int_disable(struct azx *chip)
822 {
823 int i;
824
825 /* disable interrupts in stream descriptor */
826 for (i = 0; i < chip->num_streams; i++) {
827 struct azx_dev *azx_dev = &chip->azx_dev[i];
828 azx_sd_writeb(chip, azx_dev, SD_CTL,
829 azx_sd_readb(chip, azx_dev, SD_CTL) &
830 ~SD_INT_MASK);
831 }
832
833 /* disable SIE for all streams */
834 azx_writeb(chip, INTCTL, 0);
835
836 /* disable controller CIE and GIE */
837 azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
838 ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
839 }
840
841 /* clear interrupts */
842 static void azx_int_clear(struct azx *chip)
843 {
844 int i;
845
846 /* clear stream status */
847 for (i = 0; i < chip->num_streams; i++) {
848 struct azx_dev *azx_dev = &chip->azx_dev[i];
849 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
850 }
851
852 /* clear STATESTS */
853 azx_writew(chip, STATESTS, STATESTS_INT_MASK);
854
855 /* clear rirb status */
856 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
857
858 /* clear int status */
859 azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
860 }
861
862 /*
863 * reset and start the controller registers
864 */
865 static void azx_init_chip(struct azx *chip, int full_reset)
866 {
867 if (chip->initialized)
868 return;
869
870 /* reset controller */
871 azx_reset(chip, full_reset);
872
873 /* initialize interrupts */
874 azx_int_clear(chip);
875 azx_int_enable(chip);
876
877 /* initialize the codec command I/O */
878 if (!chip->single_cmd)
879 azx_init_cmd_io(chip);
880
881 /* program the position buffer */
882 azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
883 azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
884
885 chip->initialized = 1;
886 }
887
888 /*
889 * initialize the PCI registers
890 */
891 /* update bits in a PCI register byte */
892 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
893 unsigned char mask, unsigned char val)
894 {
895 unsigned char data;
896
897 pci_read_config_byte(pci, reg, &data);
898 data &= ~mask;
899 data |= (val & mask);
900 pci_write_config_byte(pci, reg, data);
901 }
902
903 static void azx_init_pci(struct azx *chip)
904 {
905 /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
906 * TCSEL == Traffic Class Select Register, which sets PCI express QOS
907 * Ensuring these bits are 0 clears playback static on some HD Audio
908 * codecs.
909 * The PCI register TCSEL is defined in the Intel manuals.
910 */
911 if (!(chip->driver_caps & AZX_DCAPS_NO_TCSEL)) {
912 dev_dbg(chip->card->dev, "Clearing TCSEL\n");
913 update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
914 }
915
916 /* For ATI SB450/600/700/800/900 and AMD Hudson azalia HD audio,
917 * we need to enable snoop.
918 */
919 if (chip->driver_caps & AZX_DCAPS_ATI_SNOOP) {
920 dev_dbg(chip->card->dev, "Setting ATI snoop: %d\n",
921 azx_snoop(chip));
922 update_pci_byte(chip->pci,
923 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR, 0x07,
924 azx_snoop(chip) ? ATI_SB450_HDAUDIO_ENABLE_SNOOP : 0);
925 }
926
927 /* For NVIDIA HDA, enable snoop */
928 if (chip->driver_caps & AZX_DCAPS_NVIDIA_SNOOP) {
929 dev_dbg(chip->card->dev, "Setting Nvidia snoop: %d\n",
930 azx_snoop(chip));
931 update_pci_byte(chip->pci,
932 NVIDIA_HDA_TRANSREG_ADDR,
933 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
934 update_pci_byte(chip->pci,
935 NVIDIA_HDA_ISTRM_COH,
936 0x01, NVIDIA_HDA_ENABLE_COHBIT);
937 update_pci_byte(chip->pci,
938 NVIDIA_HDA_OSTRM_COH,
939 0x01, NVIDIA_HDA_ENABLE_COHBIT);
940 }
941
942 /* Enable SCH/PCH snoop if needed */
943 if (chip->driver_caps & AZX_DCAPS_SCH_SNOOP) {
944 unsigned short snoop;
945 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
946 if ((!azx_snoop(chip) && !(snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)) ||
947 (azx_snoop(chip) && (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP))) {
948 snoop &= ~INTEL_SCH_HDA_DEVC_NOSNOOP;
949 if (!azx_snoop(chip))
950 snoop |= INTEL_SCH_HDA_DEVC_NOSNOOP;
951 pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC, snoop);
952 pci_read_config_word(chip->pci,
953 INTEL_SCH_HDA_DEVC, &snoop);
954 }
955 dev_dbg(chip->card->dev, "SCH snoop: %s\n",
956 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) ?
957 "Disabled" : "Enabled");
958 }
959 }
960
961
962 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
963
964 /*
965 * interrupt handler
966 */
967 static irqreturn_t azx_interrupt(int irq, void *dev_id)
968 {
969 struct azx *chip = dev_id;
970 struct azx_dev *azx_dev;
971 u32 status;
972 u8 sd_status;
973 int i, ok;
974
975 #ifdef CONFIG_PM_RUNTIME
976 if (chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
977 if (chip->card->dev->power.runtime_status != RPM_ACTIVE)
978 return IRQ_NONE;
979 #endif
980
981 spin_lock(&chip->reg_lock);
982
983 if (chip->disabled) {
984 spin_unlock(&chip->reg_lock);
985 return IRQ_NONE;
986 }
987
988 status = azx_readl(chip, INTSTS);
989 if (status == 0 || status == 0xffffffff) {
990 spin_unlock(&chip->reg_lock);
991 return IRQ_NONE;
992 }
993
994 for (i = 0; i < chip->num_streams; i++) {
995 azx_dev = &chip->azx_dev[i];
996 if (status & azx_dev->sd_int_sta_mask) {
997 sd_status = azx_sd_readb(chip, azx_dev, SD_STS);
998 azx_sd_writeb(chip, azx_dev, SD_STS, SD_INT_MASK);
999 if (!azx_dev->substream || !azx_dev->running ||
1000 !(sd_status & SD_INT_COMPLETE))
1001 continue;
1002 /* check whether this IRQ is really acceptable */
1003 ok = azx_position_ok(chip, azx_dev);
1004 if (ok == 1) {
1005 azx_dev->irq_pending = 0;
1006 spin_unlock(&chip->reg_lock);
1007 snd_pcm_period_elapsed(azx_dev->substream);
1008 spin_lock(&chip->reg_lock);
1009 } else if (ok == 0 && chip->bus && chip->bus->workq) {
1010 /* bogus IRQ, process it later */
1011 azx_dev->irq_pending = 1;
1012 queue_work(chip->bus->workq,
1013 &chip->irq_pending_work);
1014 }
1015 }
1016 }
1017
1018 /* clear rirb int */
1019 status = azx_readb(chip, RIRBSTS);
1020 if (status & RIRB_INT_MASK) {
1021 if (status & RIRB_INT_RESPONSE) {
1022 if (chip->driver_caps & AZX_DCAPS_RIRB_PRE_DELAY)
1023 udelay(80);
1024 azx_update_rirb(chip);
1025 }
1026 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1027 }
1028
1029 spin_unlock(&chip->reg_lock);
1030
1031 return IRQ_HANDLED;
1032 }
1033
1034 /*
1035 * Probe the given codec address
1036 */
1037 static int probe_codec(struct azx *chip, int addr)
1038 {
1039 unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1040 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1041 unsigned int res;
1042
1043 mutex_lock(&chip->bus->cmd_mutex);
1044 chip->probing = 1;
1045 azx_send_cmd(chip->bus, cmd);
1046 res = azx_get_response(chip->bus, addr);
1047 chip->probing = 0;
1048 mutex_unlock(&chip->bus->cmd_mutex);
1049 if (res == -1)
1050 return -EIO;
1051 dev_dbg(chip->card->dev, "codec #%d probed OK\n", addr);
1052 return 0;
1053 }
1054
1055 static void azx_stop_chip(struct azx *chip);
1056
1057 static void azx_bus_reset(struct hda_bus *bus)
1058 {
1059 struct azx *chip = bus->private_data;
1060
1061 bus->in_reset = 1;
1062 azx_stop_chip(chip);
1063 azx_init_chip(chip, 1);
1064 #ifdef CONFIG_PM
1065 if (chip->initialized) {
1066 struct azx_pcm *p;
1067 list_for_each_entry(p, &chip->pcm_list, list)
1068 snd_pcm_suspend_all(p->pcm);
1069 snd_hda_suspend(chip->bus);
1070 snd_hda_resume(chip->bus);
1071 }
1072 #endif
1073 bus->in_reset = 0;
1074 }
1075
1076 static int get_jackpoll_interval(struct azx *chip)
1077 {
1078 int i;
1079 unsigned int j;
1080
1081 if (!chip->jackpoll_ms)
1082 return 0;
1083
1084 i = chip->jackpoll_ms[chip->dev_index];
1085 if (i == 0)
1086 return 0;
1087 if (i < 50 || i > 60000)
1088 j = 0;
1089 else
1090 j = msecs_to_jiffies(i);
1091 if (j == 0)
1092 dev_warn(chip->card->dev,
1093 "jackpoll_ms value out of range: %d\n", i);
1094 return j;
1095 }
1096
1097 /*
1098 * Codec initialization
1099 */
1100
1101 static int azx_codec_create(struct azx *chip, const char *model,
1102 unsigned int max_slots,
1103 int *power_save_to)
1104 {
1105 struct hda_bus_template bus_temp;
1106 int c, codecs, err;
1107
1108 memset(&bus_temp, 0, sizeof(bus_temp));
1109 bus_temp.private_data = chip;
1110 bus_temp.modelname = model;
1111 bus_temp.pci = chip->pci;
1112 bus_temp.ops.command = azx_send_cmd;
1113 bus_temp.ops.get_response = azx_get_response;
1114 bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1115 bus_temp.ops.bus_reset = azx_bus_reset;
1116 #ifdef CONFIG_PM
1117 bus_temp.power_save = power_save_to;
1118 bus_temp.ops.pm_notify = azx_power_notify;
1119 #endif
1120 #ifdef CONFIG_SND_HDA_DSP_LOADER
1121 bus_temp.ops.load_dsp_prepare = azx_load_dsp_prepare;
1122 bus_temp.ops.load_dsp_trigger = azx_load_dsp_trigger;
1123 bus_temp.ops.load_dsp_cleanup = azx_load_dsp_cleanup;
1124 #endif
1125
1126 err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1127 if (err < 0)
1128 return err;
1129
1130 if (chip->driver_caps & AZX_DCAPS_RIRB_DELAY) {
1131 dev_dbg(chip->card->dev, "Enable delay in RIRB handling\n");
1132 chip->bus->needs_damn_long_delay = 1;
1133 }
1134
1135 codecs = 0;
1136 if (!max_slots)
1137 max_slots = AZX_DEFAULT_CODECS;
1138
1139 /* First try to probe all given codec slots */
1140 for (c = 0; c < max_slots; c++) {
1141 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1142 if (probe_codec(chip, c) < 0) {
1143 /* Some BIOSen give you wrong codec addresses
1144 * that don't exist
1145 */
1146 dev_warn(chip->card->dev,
1147 "Codec #%d probe error; disabling it...\n", c);
1148 chip->codec_mask &= ~(1 << c);
1149 /* More badly, accessing to a non-existing
1150 * codec often screws up the controller chip,
1151 * and disturbs the further communications.
1152 * Thus if an error occurs during probing,
1153 * better to reset the controller chip to
1154 * get back to the sanity state.
1155 */
1156 azx_stop_chip(chip);
1157 azx_init_chip(chip, 1);
1158 }
1159 }
1160 }
1161
1162 /* AMD chipsets often cause the communication stalls upon certain
1163 * sequence like the pin-detection. It seems that forcing the synced
1164 * access works around the stall. Grrr...
1165 */
1166 if (chip->driver_caps & AZX_DCAPS_SYNC_WRITE) {
1167 dev_dbg(chip->card->dev, "Enable sync_write for stable communication\n");
1168 chip->bus->sync_write = 1;
1169 chip->bus->allow_bus_reset = 1;
1170 }
1171
1172 /* Then create codec instances */
1173 for (c = 0; c < max_slots; c++) {
1174 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1175 struct hda_codec *codec;
1176 err = snd_hda_codec_new(chip->bus, c, &codec);
1177 if (err < 0)
1178 continue;
1179 codec->jackpoll_interval = get_jackpoll_interval(chip);
1180 codec->beep_mode = chip->beep_mode;
1181 codecs++;
1182 }
1183 }
1184 if (!codecs) {
1185 dev_err(chip->card->dev, "no codecs initialized\n");
1186 return -ENXIO;
1187 }
1188 return 0;
1189 }
1190
1191 /* configure each codec instance */
1192 static int azx_codec_configure(struct azx *chip)
1193 {
1194 struct hda_codec *codec;
1195 list_for_each_entry(codec, &chip->bus->codec_list, list) {
1196 snd_hda_codec_configure(codec);
1197 }
1198 return 0;
1199 }
1200
1201 /*
1202 * Check whether the current DMA position is acceptable for updating
1203 * periods. Returns non-zero if it's OK.
1204 *
1205 * Many HD-audio controllers appear pretty inaccurate about
1206 * the update-IRQ timing. The IRQ is issued before actually the
1207 * data is processed. So, we need to process it afterwords in a
1208 * workqueue.
1209 */
1210 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1211 {
1212 u32 wallclk;
1213 unsigned int pos;
1214
1215 wallclk = azx_readl(chip, WALLCLK) - azx_dev->start_wallclk;
1216 if (wallclk < (azx_dev->period_wallclk * 2) / 3)
1217 return -1; /* bogus (too early) interrupt */
1218
1219 pos = azx_get_position(chip, azx_dev, true);
1220
1221 if (WARN_ONCE(!azx_dev->period_bytes,
1222 "hda-intel: zero azx_dev->period_bytes"))
1223 return -1; /* this shouldn't happen! */
1224 if (wallclk < (azx_dev->period_wallclk * 5) / 4 &&
1225 pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1226 /* NG - it's below the first next period boundary */
1227 return chip->bdl_pos_adj[chip->dev_index] ? 0 : -1;
1228 azx_dev->start_wallclk += wallclk;
1229 return 1; /* OK, it's fine */
1230 }
1231
1232 /*
1233 * The work for pending PCM period updates.
1234 */
1235 static void azx_irq_pending_work(struct work_struct *work)
1236 {
1237 struct azx *chip = container_of(work, struct azx, irq_pending_work);
1238 int i, pending, ok;
1239
1240 if (!chip->irq_pending_warned) {
1241 dev_info(chip->card->dev,
1242 "IRQ timing workaround is activated for card #%d. Suggest a bigger bdl_pos_adj.\n",
1243 chip->card->number);
1244 chip->irq_pending_warned = 1;
1245 }
1246
1247 for (;;) {
1248 pending = 0;
1249 spin_lock_irq(&chip->reg_lock);
1250 for (i = 0; i < chip->num_streams; i++) {
1251 struct azx_dev *azx_dev = &chip->azx_dev[i];
1252 if (!azx_dev->irq_pending ||
1253 !azx_dev->substream ||
1254 !azx_dev->running)
1255 continue;
1256 ok = azx_position_ok(chip, azx_dev);
1257 if (ok > 0) {
1258 azx_dev->irq_pending = 0;
1259 spin_unlock(&chip->reg_lock);
1260 snd_pcm_period_elapsed(azx_dev->substream);
1261 spin_lock(&chip->reg_lock);
1262 } else if (ok < 0) {
1263 pending = 0; /* too early */
1264 } else
1265 pending++;
1266 }
1267 spin_unlock_irq(&chip->reg_lock);
1268 if (!pending)
1269 return;
1270 msleep(1);
1271 }
1272 }
1273
1274 /* clear irq_pending flags and assure no on-going workq */
1275 static void azx_clear_irq_pending(struct azx *chip)
1276 {
1277 int i;
1278
1279 spin_lock_irq(&chip->reg_lock);
1280 for (i = 0; i < chip->num_streams; i++)
1281 chip->azx_dev[i].irq_pending = 0;
1282 spin_unlock_irq(&chip->reg_lock);
1283 }
1284
1285 /*
1286 * mixer creation - all stuff is implemented in hda module
1287 */
1288 static int azx_mixer_create(struct azx *chip)
1289 {
1290 return snd_hda_build_controls(chip->bus);
1291 }
1292
1293
1294 /*
1295 * initialize SD streams
1296 */
1297 static int azx_init_stream(struct azx *chip)
1298 {
1299 int i;
1300
1301 /* initialize each stream (aka device)
1302 * assign the starting bdl address to each stream (device)
1303 * and initialize
1304 */
1305 for (i = 0; i < chip->num_streams; i++) {
1306 struct azx_dev *azx_dev = &chip->azx_dev[i];
1307 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1308 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1309 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1310 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1311 azx_dev->sd_int_sta_mask = 1 << i;
1312 /* stream tag: must be non-zero and unique */
1313 azx_dev->index = i;
1314 azx_dev->stream_tag = i + 1;
1315 }
1316
1317 return 0;
1318 }
1319
1320 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1321 {
1322 if (request_irq(chip->pci->irq, azx_interrupt,
1323 chip->msi ? 0 : IRQF_SHARED,
1324 KBUILD_MODNAME, chip)) {
1325 dev_err(chip->card->dev,
1326 "unable to grab IRQ %d, disabling device\n",
1327 chip->pci->irq);
1328 if (do_disconnect)
1329 snd_card_disconnect(chip->card);
1330 return -1;
1331 }
1332 chip->irq = chip->pci->irq;
1333 pci_intx(chip->pci, !chip->msi);
1334 return 0;
1335 }
1336
1337
1338 static void azx_stop_chip(struct azx *chip)
1339 {
1340 if (!chip->initialized)
1341 return;
1342
1343 /* disable interrupts */
1344 azx_int_disable(chip);
1345 azx_int_clear(chip);
1346
1347 /* disable CORB/RIRB */
1348 azx_free_cmd_io(chip);
1349
1350 /* disable position buffer */
1351 azx_writel(chip, DPLBASE, 0);
1352 azx_writel(chip, DPUBASE, 0);
1353
1354 chip->initialized = 0;
1355 }
1356
1357 #ifdef CONFIG_SND_HDA_DSP_LOADER
1358 /*
1359 * DSP loading code (e.g. for CA0132)
1360 */
1361
1362 /* use the first stream for loading DSP */
1363 static struct azx_dev *
1364 azx_get_dsp_loader_dev(struct azx *chip)
1365 {
1366 return &chip->azx_dev[chip->playback_index_offset];
1367 }
1368
1369 static int azx_load_dsp_prepare(struct hda_bus *bus, unsigned int format,
1370 unsigned int byte_size,
1371 struct snd_dma_buffer *bufp)
1372 {
1373 u32 *bdl;
1374 struct azx *chip = bus->private_data;
1375 struct azx_dev *azx_dev;
1376 int err;
1377
1378 azx_dev = azx_get_dsp_loader_dev(chip);
1379
1380 dsp_lock(azx_dev);
1381 spin_lock_irq(&chip->reg_lock);
1382 if (azx_dev->running || azx_dev->locked) {
1383 spin_unlock_irq(&chip->reg_lock);
1384 err = -EBUSY;
1385 goto unlock;
1386 }
1387 azx_dev->prepared = 0;
1388 chip->saved_azx_dev = *azx_dev;
1389 azx_dev->locked = 1;
1390 spin_unlock_irq(&chip->reg_lock);
1391
1392 err = chip->ops->dma_alloc_pages(chip, SNDRV_DMA_TYPE_DEV_SG,
1393 byte_size, bufp);
1394 if (err < 0)
1395 goto err_alloc;
1396
1397 azx_dev->bufsize = byte_size;
1398 azx_dev->period_bytes = byte_size;
1399 azx_dev->format_val = format;
1400
1401 azx_stream_reset(chip, azx_dev);
1402
1403 /* reset BDL address */
1404 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1405 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1406
1407 azx_dev->frags = 0;
1408 bdl = (u32 *)azx_dev->bdl.area;
1409 err = setup_bdle(chip, bufp, azx_dev, &bdl, 0, byte_size, 0);
1410 if (err < 0)
1411 goto error;
1412
1413 azx_setup_controller(chip, azx_dev);
1414 dsp_unlock(azx_dev);
1415 return azx_dev->stream_tag;
1416
1417 error:
1418 chip->ops->dma_free_pages(chip, bufp);
1419 err_alloc:
1420 spin_lock_irq(&chip->reg_lock);
1421 if (azx_dev->opened)
1422 *azx_dev = chip->saved_azx_dev;
1423 azx_dev->locked = 0;
1424 spin_unlock_irq(&chip->reg_lock);
1425 unlock:
1426 dsp_unlock(azx_dev);
1427 return err;
1428 }
1429
1430 static void azx_load_dsp_trigger(struct hda_bus *bus, bool start)
1431 {
1432 struct azx *chip = bus->private_data;
1433 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1434
1435 if (start)
1436 azx_stream_start(chip, azx_dev);
1437 else
1438 azx_stream_stop(chip, azx_dev);
1439 azx_dev->running = start;
1440 }
1441
1442 static void azx_load_dsp_cleanup(struct hda_bus *bus,
1443 struct snd_dma_buffer *dmab)
1444 {
1445 struct azx *chip = bus->private_data;
1446 struct azx_dev *azx_dev = azx_get_dsp_loader_dev(chip);
1447
1448 if (!dmab->area || !azx_dev->locked)
1449 return;
1450
1451 dsp_lock(azx_dev);
1452 /* reset BDL address */
1453 azx_sd_writel(chip, azx_dev, SD_BDLPL, 0);
1454 azx_sd_writel(chip, azx_dev, SD_BDLPU, 0);
1455 azx_sd_writel(chip, azx_dev, SD_CTL, 0);
1456 azx_dev->bufsize = 0;
1457 azx_dev->period_bytes = 0;
1458 azx_dev->format_val = 0;
1459
1460 chip->ops->dma_free_pages(chip, dmab);
1461 dmab->area = NULL;
1462
1463 spin_lock_irq(&chip->reg_lock);
1464 if (azx_dev->opened)
1465 *azx_dev = chip->saved_azx_dev;
1466 azx_dev->locked = 0;
1467 spin_unlock_irq(&chip->reg_lock);
1468 dsp_unlock(azx_dev);
1469 }
1470 #endif /* CONFIG_SND_HDA_DSP_LOADER */
1471
1472 #ifdef CONFIG_PM
1473 /* power-up/down the controller */
1474 static void azx_power_notify(struct hda_bus *bus, bool power_up)
1475 {
1476 struct azx *chip = bus->private_data;
1477
1478 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1479 return;
1480
1481 if (power_up)
1482 pm_runtime_get_sync(chip->card->dev);
1483 else
1484 pm_runtime_put_sync(chip->card->dev);
1485 }
1486
1487 static DEFINE_MUTEX(card_list_lock);
1488 static LIST_HEAD(card_list);
1489
1490 static void azx_add_card_list(struct azx *chip)
1491 {
1492 mutex_lock(&card_list_lock);
1493 list_add(&chip->list, &card_list);
1494 mutex_unlock(&card_list_lock);
1495 }
1496
1497 static void azx_del_card_list(struct azx *chip)
1498 {
1499 mutex_lock(&card_list_lock);
1500 list_del_init(&chip->list);
1501 mutex_unlock(&card_list_lock);
1502 }
1503
1504 /* trigger power-save check at writing parameter */
1505 static int param_set_xint(const char *val, const struct kernel_param *kp)
1506 {
1507 struct azx *chip;
1508 struct hda_codec *c;
1509 int prev = power_save;
1510 int ret = param_set_int(val, kp);
1511
1512 if (ret || prev == power_save)
1513 return ret;
1514
1515 mutex_lock(&card_list_lock);
1516 list_for_each_entry(chip, &card_list, list) {
1517 if (!chip->bus || chip->disabled)
1518 continue;
1519 list_for_each_entry(c, &chip->bus->codec_list, list)
1520 snd_hda_power_sync(c);
1521 }
1522 mutex_unlock(&card_list_lock);
1523 return 0;
1524 }
1525 #else
1526 #define azx_add_card_list(chip) /* NOP */
1527 #define azx_del_card_list(chip) /* NOP */
1528 #endif /* CONFIG_PM */
1529
1530 #if defined(CONFIG_PM_SLEEP) || defined(SUPPORT_VGA_SWITCHEROO)
1531 /*
1532 * power management
1533 */
1534 static int azx_suspend(struct device *dev)
1535 {
1536 struct pci_dev *pci = to_pci_dev(dev);
1537 struct snd_card *card = dev_get_drvdata(dev);
1538 struct azx *chip = card->private_data;
1539 struct azx_pcm *p;
1540
1541 if (chip->disabled)
1542 return 0;
1543
1544 snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1545 azx_clear_irq_pending(chip);
1546 list_for_each_entry(p, &chip->pcm_list, list)
1547 snd_pcm_suspend_all(p->pcm);
1548 if (chip->initialized)
1549 snd_hda_suspend(chip->bus);
1550 azx_stop_chip(chip);
1551 azx_enter_link_reset(chip);
1552 if (chip->irq >= 0) {
1553 free_irq(chip->irq, chip);
1554 chip->irq = -1;
1555 }
1556 if (chip->msi)
1557 pci_disable_msi(chip->pci);
1558 pci_disable_device(pci);
1559 pci_save_state(pci);
1560 pci_set_power_state(pci, PCI_D3hot);
1561 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1562 hda_display_power(false);
1563 return 0;
1564 }
1565
1566 static int azx_resume(struct device *dev)
1567 {
1568 struct pci_dev *pci = to_pci_dev(dev);
1569 struct snd_card *card = dev_get_drvdata(dev);
1570 struct azx *chip = card->private_data;
1571
1572 if (chip->disabled)
1573 return 0;
1574
1575 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1576 hda_display_power(true);
1577 pci_set_power_state(pci, PCI_D0);
1578 pci_restore_state(pci);
1579 if (pci_enable_device(pci) < 0) {
1580 dev_err(chip->card->dev,
1581 "pci_enable_device failed, disabling device\n");
1582 snd_card_disconnect(card);
1583 return -EIO;
1584 }
1585 pci_set_master(pci);
1586 if (chip->msi)
1587 if (pci_enable_msi(pci) < 0)
1588 chip->msi = 0;
1589 if (azx_acquire_irq(chip, 1) < 0)
1590 return -EIO;
1591 azx_init_pci(chip);
1592
1593 azx_init_chip(chip, 1);
1594
1595 snd_hda_resume(chip->bus);
1596 snd_power_change_state(card, SNDRV_CTL_POWER_D0);
1597 return 0;
1598 }
1599 #endif /* CONFIG_PM_SLEEP || SUPPORT_VGA_SWITCHEROO */
1600
1601 #ifdef CONFIG_PM_RUNTIME
1602 static int azx_runtime_suspend(struct device *dev)
1603 {
1604 struct snd_card *card = dev_get_drvdata(dev);
1605 struct azx *chip = card->private_data;
1606
1607 if (chip->disabled)
1608 return 0;
1609
1610 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1611 return 0;
1612
1613 /* enable controller wake up event */
1614 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) |
1615 STATESTS_INT_MASK);
1616
1617 azx_stop_chip(chip);
1618 azx_enter_link_reset(chip);
1619 azx_clear_irq_pending(chip);
1620 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1621 hda_display_power(false);
1622 return 0;
1623 }
1624
1625 static int azx_runtime_resume(struct device *dev)
1626 {
1627 struct snd_card *card = dev_get_drvdata(dev);
1628 struct azx *chip = card->private_data;
1629 struct hda_bus *bus;
1630 struct hda_codec *codec;
1631 int status;
1632
1633 if (chip->disabled)
1634 return 0;
1635
1636 if (!(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1637 return 0;
1638
1639 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
1640 hda_display_power(true);
1641
1642 /* Read STATESTS before controller reset */
1643 status = azx_readw(chip, STATESTS);
1644
1645 azx_init_pci(chip);
1646 azx_init_chip(chip, 1);
1647
1648 bus = chip->bus;
1649 if (status && bus) {
1650 list_for_each_entry(codec, &bus->codec_list, list)
1651 if (status & (1 << codec->addr))
1652 queue_delayed_work(codec->bus->workq,
1653 &codec->jackpoll_work, codec->jackpoll_interval);
1654 }
1655
1656 /* disable controller Wake Up event*/
1657 azx_writew(chip, WAKEEN, azx_readw(chip, WAKEEN) &
1658 ~STATESTS_INT_MASK);
1659
1660 return 0;
1661 }
1662
1663 static int azx_runtime_idle(struct device *dev)
1664 {
1665 struct snd_card *card = dev_get_drvdata(dev);
1666 struct azx *chip = card->private_data;
1667
1668 if (chip->disabled)
1669 return 0;
1670
1671 if (!power_save_controller ||
1672 !(chip->driver_caps & AZX_DCAPS_PM_RUNTIME))
1673 return -EBUSY;
1674
1675 return 0;
1676 }
1677
1678 #endif /* CONFIG_PM_RUNTIME */
1679
1680 #ifdef CONFIG_PM
1681 static const struct dev_pm_ops azx_pm = {
1682 SET_SYSTEM_SLEEP_PM_OPS(azx_suspend, azx_resume)
1683 SET_RUNTIME_PM_OPS(azx_runtime_suspend, azx_runtime_resume, azx_runtime_idle)
1684 };
1685
1686 #define AZX_PM_OPS &azx_pm
1687 #else
1688 #define AZX_PM_OPS NULL
1689 #endif /* CONFIG_PM */
1690
1691
1692 /*
1693 * reboot notifier for hang-up problem at power-down
1694 */
1695 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
1696 {
1697 struct azx *chip = container_of(nb, struct azx, reboot_notifier);
1698 snd_hda_bus_reboot_notify(chip->bus);
1699 azx_stop_chip(chip);
1700 return NOTIFY_OK;
1701 }
1702
1703 static void azx_notifier_register(struct azx *chip)
1704 {
1705 chip->reboot_notifier.notifier_call = azx_halt;
1706 register_reboot_notifier(&chip->reboot_notifier);
1707 }
1708
1709 static void azx_notifier_unregister(struct azx *chip)
1710 {
1711 if (chip->reboot_notifier.notifier_call)
1712 unregister_reboot_notifier(&chip->reboot_notifier);
1713 }
1714
1715 static int azx_probe_continue(struct azx *chip);
1716
1717 #ifdef SUPPORT_VGA_SWITCHEROO
1718 static struct pci_dev *get_bound_vga(struct pci_dev *pci);
1719
1720 static void azx_vs_set_state(struct pci_dev *pci,
1721 enum vga_switcheroo_state state)
1722 {
1723 struct snd_card *card = pci_get_drvdata(pci);
1724 struct azx *chip = card->private_data;
1725 bool disabled;
1726
1727 wait_for_completion(&chip->probe_wait);
1728 if (chip->init_failed)
1729 return;
1730
1731 disabled = (state == VGA_SWITCHEROO_OFF);
1732 if (chip->disabled == disabled)
1733 return;
1734
1735 if (!chip->bus) {
1736 chip->disabled = disabled;
1737 if (!disabled) {
1738 dev_info(chip->card->dev,
1739 "Start delayed initialization\n");
1740 if (azx_probe_continue(chip) < 0) {
1741 dev_err(chip->card->dev, "initialization error\n");
1742 chip->init_failed = true;
1743 }
1744 }
1745 } else {
1746 dev_info(chip->card->dev, "%s via VGA-switcheroo\n",
1747 disabled ? "Disabling" : "Enabling");
1748 if (disabled) {
1749 pm_runtime_put_sync_suspend(card->dev);
1750 azx_suspend(card->dev);
1751 /* when we get suspended by vga switcheroo we end up in D3cold,
1752 * however we have no ACPI handle, so pci/acpi can't put us there,
1753 * put ourselves there */
1754 pci->current_state = PCI_D3cold;
1755 chip->disabled = true;
1756 if (snd_hda_lock_devices(chip->bus))
1757 dev_warn(chip->card->dev,
1758 "Cannot lock devices!\n");
1759 } else {
1760 snd_hda_unlock_devices(chip->bus);
1761 pm_runtime_get_noresume(card->dev);
1762 chip->disabled = false;
1763 azx_resume(card->dev);
1764 }
1765 }
1766 }
1767
1768 static bool azx_vs_can_switch(struct pci_dev *pci)
1769 {
1770 struct snd_card *card = pci_get_drvdata(pci);
1771 struct azx *chip = card->private_data;
1772
1773 wait_for_completion(&chip->probe_wait);
1774 if (chip->init_failed)
1775 return false;
1776 if (chip->disabled || !chip->bus)
1777 return true;
1778 if (snd_hda_lock_devices(chip->bus))
1779 return false;
1780 snd_hda_unlock_devices(chip->bus);
1781 return true;
1782 }
1783
1784 static void init_vga_switcheroo(struct azx *chip)
1785 {
1786 struct pci_dev *p = get_bound_vga(chip->pci);
1787 if (p) {
1788 dev_info(chip->card->dev,
1789 "Handle VGA-switcheroo audio client\n");
1790 chip->use_vga_switcheroo = 1;
1791 pci_dev_put(p);
1792 }
1793 }
1794
1795 static const struct vga_switcheroo_client_ops azx_vs_ops = {
1796 .set_gpu_state = azx_vs_set_state,
1797 .can_switch = azx_vs_can_switch,
1798 };
1799
1800 static int register_vga_switcheroo(struct azx *chip)
1801 {
1802 int err;
1803
1804 if (!chip->use_vga_switcheroo)
1805 return 0;
1806 /* FIXME: currently only handling DIS controller
1807 * is there any machine with two switchable HDMI audio controllers?
1808 */
1809 err = vga_switcheroo_register_audio_client(chip->pci, &azx_vs_ops,
1810 VGA_SWITCHEROO_DIS,
1811 chip->bus != NULL);
1812 if (err < 0)
1813 return err;
1814 chip->vga_switcheroo_registered = 1;
1815
1816 /* register as an optimus hdmi audio power domain */
1817 vga_switcheroo_init_domain_pm_optimus_hdmi_audio(chip->card->dev,
1818 &chip->hdmi_pm_domain);
1819 return 0;
1820 }
1821 #else
1822 #define init_vga_switcheroo(chip) /* NOP */
1823 #define register_vga_switcheroo(chip) 0
1824 #define check_hdmi_disabled(pci) false
1825 #endif /* SUPPORT_VGA_SWITCHER */
1826
1827 /*
1828 * destructor
1829 */
1830 static int azx_free(struct azx *chip)
1831 {
1832 struct pci_dev *pci = chip->pci;
1833 int i;
1834
1835 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME)
1836 && chip->running)
1837 pm_runtime_get_noresume(&pci->dev);
1838
1839 azx_del_card_list(chip);
1840
1841 azx_notifier_unregister(chip);
1842
1843 chip->init_failed = 1; /* to be sure */
1844 complete_all(&chip->probe_wait);
1845
1846 if (use_vga_switcheroo(chip)) {
1847 if (chip->disabled && chip->bus)
1848 snd_hda_unlock_devices(chip->bus);
1849 if (chip->vga_switcheroo_registered)
1850 vga_switcheroo_unregister_client(chip->pci);
1851 }
1852
1853 if (chip->initialized) {
1854 azx_clear_irq_pending(chip);
1855 for (i = 0; i < chip->num_streams; i++)
1856 azx_stream_stop(chip, &chip->azx_dev[i]);
1857 azx_stop_chip(chip);
1858 }
1859
1860 if (chip->irq >= 0)
1861 free_irq(chip->irq, (void*)chip);
1862 if (chip->msi)
1863 pci_disable_msi(chip->pci);
1864 if (chip->remap_addr)
1865 iounmap(chip->remap_addr);
1866
1867 azx_free_stream_pages(chip);
1868 if (chip->region_requested)
1869 pci_release_regions(chip->pci);
1870 pci_disable_device(chip->pci);
1871 kfree(chip->azx_dev);
1872 #ifdef CONFIG_SND_HDA_PATCH_LOADER
1873 if (chip->fw)
1874 release_firmware(chip->fw);
1875 #endif
1876 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
1877 hda_display_power(false);
1878 hda_i915_exit();
1879 }
1880 kfree(chip);
1881
1882 return 0;
1883 }
1884
1885 static int azx_dev_free(struct snd_device *device)
1886 {
1887 return azx_free(device->device_data);
1888 }
1889
1890 #ifdef SUPPORT_VGA_SWITCHEROO
1891 /*
1892 * Check of disabled HDMI controller by vga-switcheroo
1893 */
1894 static struct pci_dev *get_bound_vga(struct pci_dev *pci)
1895 {
1896 struct pci_dev *p;
1897
1898 /* check only discrete GPU */
1899 switch (pci->vendor) {
1900 case PCI_VENDOR_ID_ATI:
1901 case PCI_VENDOR_ID_AMD:
1902 case PCI_VENDOR_ID_NVIDIA:
1903 if (pci->devfn == 1) {
1904 p = pci_get_domain_bus_and_slot(pci_domain_nr(pci->bus),
1905 pci->bus->number, 0);
1906 if (p) {
1907 if ((p->class >> 8) == PCI_CLASS_DISPLAY_VGA)
1908 return p;
1909 pci_dev_put(p);
1910 }
1911 }
1912 break;
1913 }
1914 return NULL;
1915 }
1916
1917 static bool check_hdmi_disabled(struct pci_dev *pci)
1918 {
1919 bool vga_inactive = false;
1920 struct pci_dev *p = get_bound_vga(pci);
1921
1922 if (p) {
1923 if (vga_switcheroo_get_client_state(p) == VGA_SWITCHEROO_OFF)
1924 vga_inactive = true;
1925 pci_dev_put(p);
1926 }
1927 return vga_inactive;
1928 }
1929 #endif /* SUPPORT_VGA_SWITCHEROO */
1930
1931 /*
1932 * white/black-listing for position_fix
1933 */
1934 static struct snd_pci_quirk position_fix_list[] = {
1935 SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
1936 SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
1937 SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
1938 SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
1939 SND_PCI_QUIRK(0x1043, 0x81b3, "ASUS", POS_FIX_LPIB),
1940 SND_PCI_QUIRK(0x1043, 0x81e7, "ASUS M2V", POS_FIX_LPIB),
1941 SND_PCI_QUIRK(0x104d, 0x9069, "Sony VPCS11V9E", POS_FIX_LPIB),
1942 SND_PCI_QUIRK(0x10de, 0xcb89, "Macbook Pro 7,1", POS_FIX_LPIB),
1943 SND_PCI_QUIRK(0x1297, 0x3166, "Shuttle", POS_FIX_LPIB),
1944 SND_PCI_QUIRK(0x1458, 0xa022, "ga-ma770-ud3", POS_FIX_LPIB),
1945 SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
1946 SND_PCI_QUIRK(0x1565, 0x8218, "Biostar Microtech", POS_FIX_LPIB),
1947 SND_PCI_QUIRK(0x1849, 0x0888, "775Dual-VSTA", POS_FIX_LPIB),
1948 SND_PCI_QUIRK(0x8086, 0x2503, "DG965OT AAD63733-203", POS_FIX_LPIB),
1949 {}
1950 };
1951
1952 static int check_position_fix(struct azx *chip, int fix)
1953 {
1954 const struct snd_pci_quirk *q;
1955
1956 switch (fix) {
1957 case POS_FIX_AUTO:
1958 case POS_FIX_LPIB:
1959 case POS_FIX_POSBUF:
1960 case POS_FIX_VIACOMBO:
1961 case POS_FIX_COMBO:
1962 return fix;
1963 }
1964
1965 q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
1966 if (q) {
1967 dev_info(chip->card->dev,
1968 "position_fix set to %d for device %04x:%04x\n",
1969 q->value, q->subvendor, q->subdevice);
1970 return q->value;
1971 }
1972
1973 /* Check VIA/ATI HD Audio Controller exist */
1974 if (chip->driver_caps & AZX_DCAPS_POSFIX_VIA) {
1975 dev_dbg(chip->card->dev, "Using VIACOMBO position fix\n");
1976 return POS_FIX_VIACOMBO;
1977 }
1978 if (chip->driver_caps & AZX_DCAPS_POSFIX_LPIB) {
1979 dev_dbg(chip->card->dev, "Using LPIB position fix\n");
1980 return POS_FIX_LPIB;
1981 }
1982 return POS_FIX_AUTO;
1983 }
1984
1985 /*
1986 * black-lists for probe_mask
1987 */
1988 static struct snd_pci_quirk probe_mask_list[] = {
1989 /* Thinkpad often breaks the controller communication when accessing
1990 * to the non-working (or non-existing) modem codec slot.
1991 */
1992 SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
1993 SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
1994 SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
1995 /* broken BIOS */
1996 SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
1997 /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
1998 SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
1999 /* forced codec slots */
2000 SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2001 SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2002 /* WinFast VP200 H (Teradici) user reported broken communication */
2003 SND_PCI_QUIRK(0x3a21, 0x040d, "WinFast VP200 H", 0x101),
2004 {}
2005 };
2006
2007 #define AZX_FORCE_CODEC_MASK 0x100
2008
2009 static void check_probe_mask(struct azx *chip, int dev)
2010 {
2011 const struct snd_pci_quirk *q;
2012
2013 chip->codec_probe_mask = probe_mask[dev];
2014 if (chip->codec_probe_mask == -1) {
2015 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2016 if (q) {
2017 dev_info(chip->card->dev,
2018 "probe_mask set to 0x%x for device %04x:%04x\n",
2019 q->value, q->subvendor, q->subdevice);
2020 chip->codec_probe_mask = q->value;
2021 }
2022 }
2023
2024 /* check forced option */
2025 if (chip->codec_probe_mask != -1 &&
2026 (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2027 chip->codec_mask = chip->codec_probe_mask & 0xff;
2028 dev_info(chip->card->dev, "codec_mask forced to 0x%x\n",
2029 chip->codec_mask);
2030 }
2031 }
2032
2033 /*
2034 * white/black-list for enable_msi
2035 */
2036 static struct snd_pci_quirk msi_black_list[] = {
2037 SND_PCI_QUIRK(0x103c, 0x2191, "HP", 0), /* AMD Hudson */
2038 SND_PCI_QUIRK(0x103c, 0x2192, "HP", 0), /* AMD Hudson */
2039 SND_PCI_QUIRK(0x103c, 0x21f7, "HP", 0), /* AMD Hudson */
2040 SND_PCI_QUIRK(0x103c, 0x21fa, "HP", 0), /* AMD Hudson */
2041 SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2042 SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2043 SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2044 SND_PCI_QUIRK(0x1179, 0xfb44, "Toshiba Satellite C870", 0), /* AMD Hudson */
2045 SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2046 SND_PCI_QUIRK(0xa0a0, 0x0575, "Aopen MZ915-M", 0), /* ICH6 */
2047 {}
2048 };
2049
2050 static void check_msi(struct azx *chip)
2051 {
2052 const struct snd_pci_quirk *q;
2053
2054 if (enable_msi >= 0) {
2055 chip->msi = !!enable_msi;
2056 return;
2057 }
2058 chip->msi = 1; /* enable MSI as default */
2059 q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2060 if (q) {
2061 dev_info(chip->card->dev,
2062 "msi for device %04x:%04x set to %d\n",
2063 q->subvendor, q->subdevice, q->value);
2064 chip->msi = q->value;
2065 return;
2066 }
2067
2068 /* NVidia chipsets seem to cause troubles with MSI */
2069 if (chip->driver_caps & AZX_DCAPS_NO_MSI) {
2070 dev_info(chip->card->dev, "Disabling MSI\n");
2071 chip->msi = 0;
2072 }
2073 }
2074
2075 /* check the snoop mode availability */
2076 static void azx_check_snoop_available(struct azx *chip)
2077 {
2078 bool snoop = chip->snoop;
2079
2080 switch (chip->driver_type) {
2081 case AZX_DRIVER_VIA:
2082 /* force to non-snoop mode for a new VIA controller
2083 * when BIOS is set
2084 */
2085 if (snoop) {
2086 u8 val;
2087 pci_read_config_byte(chip->pci, 0x42, &val);
2088 if (!(val & 0x80) && chip->pci->revision == 0x30)
2089 snoop = false;
2090 }
2091 break;
2092 case AZX_DRIVER_ATIHDMI_NS:
2093 /* new ATI HDMI requires non-snoop */
2094 snoop = false;
2095 break;
2096 case AZX_DRIVER_CTHDA:
2097 snoop = false;
2098 break;
2099 }
2100
2101 if (snoop != chip->snoop) {
2102 dev_info(chip->card->dev, "Force to %s mode\n",
2103 snoop ? "snoop" : "non-snoop");
2104 chip->snoop = snoop;
2105 }
2106 }
2107
2108 static void azx_probe_work(struct work_struct *work)
2109 {
2110 azx_probe_continue(container_of(work, struct azx, probe_work));
2111 }
2112
2113 /*
2114 * constructor
2115 */
2116 static int azx_create(struct snd_card *card, struct pci_dev *pci,
2117 int dev, unsigned int driver_caps,
2118 const struct hda_controller_ops *hda_ops,
2119 struct azx **rchip)
2120 {
2121 static struct snd_device_ops ops = {
2122 .dev_free = azx_dev_free,
2123 };
2124 struct azx *chip;
2125 int err;
2126
2127 *rchip = NULL;
2128
2129 err = pci_enable_device(pci);
2130 if (err < 0)
2131 return err;
2132
2133 chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2134 if (!chip) {
2135 dev_err(card->dev, "Cannot allocate chip\n");
2136 pci_disable_device(pci);
2137 return -ENOMEM;
2138 }
2139
2140 spin_lock_init(&chip->reg_lock);
2141 mutex_init(&chip->open_mutex);
2142 chip->card = card;
2143 chip->pci = pci;
2144 chip->ops = hda_ops;
2145 chip->irq = -1;
2146 chip->driver_caps = driver_caps;
2147 chip->driver_type = driver_caps & 0xff;
2148 check_msi(chip);
2149 chip->dev_index = dev;
2150 chip->jackpoll_ms = jackpoll_ms;
2151 INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2152 INIT_LIST_HEAD(&chip->pcm_list);
2153 INIT_LIST_HEAD(&chip->list);
2154 init_vga_switcheroo(chip);
2155 init_completion(&chip->probe_wait);
2156
2157 chip->position_fix[0] = chip->position_fix[1] =
2158 check_position_fix(chip, position_fix[dev]);
2159 /* combo mode uses LPIB for playback */
2160 if (chip->position_fix[0] == POS_FIX_COMBO) {
2161 chip->position_fix[0] = POS_FIX_LPIB;
2162 chip->position_fix[1] = POS_FIX_AUTO;
2163 }
2164
2165 check_probe_mask(chip, dev);
2166
2167 chip->single_cmd = single_cmd;
2168 chip->snoop = hda_snoop;
2169 azx_check_snoop_available(chip);
2170
2171 if (bdl_pos_adj[dev] < 0) {
2172 switch (chip->driver_type) {
2173 case AZX_DRIVER_ICH:
2174 case AZX_DRIVER_PCH:
2175 bdl_pos_adj[dev] = 1;
2176 break;
2177 default:
2178 bdl_pos_adj[dev] = 32;
2179 break;
2180 }
2181 }
2182 chip->bdl_pos_adj = bdl_pos_adj;
2183
2184 err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2185 if (err < 0) {
2186 dev_err(card->dev, "Error creating device [card]!\n");
2187 azx_free(chip);
2188 return err;
2189 }
2190
2191 /* continue probing in work context as may trigger request module */
2192 INIT_WORK(&chip->probe_work, azx_probe_work);
2193
2194 *rchip = chip;
2195
2196 return 0;
2197 }
2198
2199 static int azx_first_init(struct azx *chip)
2200 {
2201 int dev = chip->dev_index;
2202 struct pci_dev *pci = chip->pci;
2203 struct snd_card *card = chip->card;
2204 int err;
2205 unsigned short gcap;
2206
2207 #if BITS_PER_LONG != 64
2208 /* Fix up base address on ULI M5461 */
2209 if (chip->driver_type == AZX_DRIVER_ULI) {
2210 u16 tmp3;
2211 pci_read_config_word(pci, 0x40, &tmp3);
2212 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2213 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2214 }
2215 #endif
2216
2217 err = pci_request_regions(pci, "ICH HD audio");
2218 if (err < 0)
2219 return err;
2220 chip->region_requested = 1;
2221
2222 chip->addr = pci_resource_start(pci, 0);
2223 chip->remap_addr = pci_ioremap_bar(pci, 0);
2224 if (chip->remap_addr == NULL) {
2225 dev_err(card->dev, "ioremap error\n");
2226 return -ENXIO;
2227 }
2228
2229 if (chip->msi)
2230 if (pci_enable_msi(pci) < 0)
2231 chip->msi = 0;
2232
2233 if (azx_acquire_irq(chip, 0) < 0)
2234 return -EBUSY;
2235
2236 pci_set_master(pci);
2237 synchronize_irq(chip->irq);
2238
2239 gcap = azx_readw(chip, GCAP);
2240 dev_dbg(card->dev, "chipset global capabilities = 0x%x\n", gcap);
2241
2242 /* disable SB600 64bit support for safety */
2243 if (chip->pci->vendor == PCI_VENDOR_ID_ATI) {
2244 struct pci_dev *p_smbus;
2245 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2246 PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2247 NULL);
2248 if (p_smbus) {
2249 if (p_smbus->revision < 0x30)
2250 gcap &= ~ICH6_GCAP_64OK;
2251 pci_dev_put(p_smbus);
2252 }
2253 }
2254
2255 /* disable 64bit DMA address on some devices */
2256 if (chip->driver_caps & AZX_DCAPS_NO_64BIT) {
2257 dev_dbg(card->dev, "Disabling 64bit DMA\n");
2258 gcap &= ~ICH6_GCAP_64OK;
2259 }
2260
2261 /* disable buffer size rounding to 128-byte multiples if supported */
2262 if (align_buffer_size >= 0)
2263 chip->align_buffer_size = !!align_buffer_size;
2264 else {
2265 if (chip->driver_caps & AZX_DCAPS_BUFSIZE)
2266 chip->align_buffer_size = 0;
2267 else if (chip->driver_caps & AZX_DCAPS_ALIGN_BUFSIZE)
2268 chip->align_buffer_size = 1;
2269 else
2270 chip->align_buffer_size = 1;
2271 }
2272
2273 /* allow 64bit DMA address if supported by H/W */
2274 if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2275 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2276 else {
2277 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2278 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2279 }
2280
2281 /* read number of streams from GCAP register instead of using
2282 * hardcoded value
2283 */
2284 chip->capture_streams = (gcap >> 8) & 0x0f;
2285 chip->playback_streams = (gcap >> 12) & 0x0f;
2286 if (!chip->playback_streams && !chip->capture_streams) {
2287 /* gcap didn't give any info, switching to old method */
2288
2289 switch (chip->driver_type) {
2290 case AZX_DRIVER_ULI:
2291 chip->playback_streams = ULI_NUM_PLAYBACK;
2292 chip->capture_streams = ULI_NUM_CAPTURE;
2293 break;
2294 case AZX_DRIVER_ATIHDMI:
2295 case AZX_DRIVER_ATIHDMI_NS:
2296 chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2297 chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2298 break;
2299 case AZX_DRIVER_GENERIC:
2300 default:
2301 chip->playback_streams = ICH6_NUM_PLAYBACK;
2302 chip->capture_streams = ICH6_NUM_CAPTURE;
2303 break;
2304 }
2305 }
2306 chip->capture_index_offset = 0;
2307 chip->playback_index_offset = chip->capture_streams;
2308 chip->num_streams = chip->playback_streams + chip->capture_streams;
2309 chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2310 GFP_KERNEL);
2311 if (!chip->azx_dev) {
2312 dev_err(card->dev, "cannot malloc azx_dev\n");
2313 return -ENOMEM;
2314 }
2315
2316 err = azx_alloc_stream_pages(chip);
2317 if (err < 0)
2318 return err;
2319 /* allocate CORB/RIRB */
2320 err = azx_alloc_cmd_io(chip);
2321 if (err < 0)
2322 return err;
2323
2324 /* initialize streams */
2325 azx_init_stream(chip);
2326
2327 /* initialize chip */
2328 azx_init_pci(chip);
2329 azx_init_chip(chip, (probe_only[dev] & 2) == 0);
2330
2331 /* codec detection */
2332 if (!chip->codec_mask) {
2333 dev_err(card->dev, "no codecs found!\n");
2334 return -ENODEV;
2335 }
2336
2337 strcpy(card->driver, "HDA-Intel");
2338 strlcpy(card->shortname, driver_short_names[chip->driver_type],
2339 sizeof(card->shortname));
2340 snprintf(card->longname, sizeof(card->longname),
2341 "%s at 0x%lx irq %i",
2342 card->shortname, chip->addr, chip->irq);
2343
2344 return 0;
2345 }
2346
2347 static void power_down_all_codecs(struct azx *chip)
2348 {
2349 #ifdef CONFIG_PM
2350 /* The codecs were powered up in snd_hda_codec_new().
2351 * Now all initialization done, so turn them down if possible
2352 */
2353 struct hda_codec *codec;
2354 list_for_each_entry(codec, &chip->bus->codec_list, list) {
2355 snd_hda_power_down(codec);
2356 }
2357 #endif
2358 }
2359
2360 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2361 /* callback from request_firmware_nowait() */
2362 static void azx_firmware_cb(const struct firmware *fw, void *context)
2363 {
2364 struct snd_card *card = context;
2365 struct azx *chip = card->private_data;
2366 struct pci_dev *pci = chip->pci;
2367
2368 if (!fw) {
2369 dev_err(card->dev, "Cannot load firmware, aborting\n");
2370 goto error;
2371 }
2372
2373 chip->fw = fw;
2374 if (!chip->disabled) {
2375 /* continue probing */
2376 if (azx_probe_continue(chip))
2377 goto error;
2378 }
2379 return; /* OK */
2380
2381 error:
2382 snd_card_free(card);
2383 pci_set_drvdata(pci, NULL);
2384 }
2385 #endif
2386
2387 /*
2388 * HDA controller ops.
2389 */
2390
2391 /* PCI register access. */
2392 static void pci_azx_writel(u32 value, u32 *addr)
2393 {
2394 writel(value, addr);
2395 }
2396
2397 static u32 pci_azx_readl(u32 *addr)
2398 {
2399 return readl(addr);
2400 }
2401
2402 static void pci_azx_writew(u16 value, u16 *addr)
2403 {
2404 writew(value, addr);
2405 }
2406
2407 static u16 pci_azx_readw(u16 *addr)
2408 {
2409 return readw(addr);
2410 }
2411
2412 static void pci_azx_writeb(u8 value, u8 *addr)
2413 {
2414 writeb(value, addr);
2415 }
2416
2417 static u8 pci_azx_readb(u8 *addr)
2418 {
2419 return readb(addr);
2420 }
2421
2422 static int disable_msi_reset_irq(struct azx *chip)
2423 {
2424 int err;
2425
2426 free_irq(chip->irq, chip);
2427 chip->irq = -1;
2428 pci_disable_msi(chip->pci);
2429 chip->msi = 0;
2430 err = azx_acquire_irq(chip, 1);
2431 if (err < 0)
2432 return err;
2433
2434 return 0;
2435 }
2436
2437 /* DMA page allocation helpers. */
2438 static int dma_alloc_pages(struct azx *chip,
2439 int type,
2440 size_t size,
2441 struct snd_dma_buffer *buf)
2442 {
2443 int err;
2444
2445 err = snd_dma_alloc_pages(type,
2446 chip->card->dev,
2447 size, buf);
2448 if (err < 0)
2449 return err;
2450 mark_pages_wc(chip, buf, true);
2451 return 0;
2452 }
2453
2454 static void dma_free_pages(struct azx *chip, struct snd_dma_buffer *buf)
2455 {
2456 mark_pages_wc(chip, buf, false);
2457 snd_dma_free_pages(buf);
2458 }
2459
2460 static int substream_alloc_pages(struct azx *chip,
2461 struct snd_pcm_substream *substream,
2462 size_t size)
2463 {
2464 struct azx_dev *azx_dev = get_azx_dev(substream);
2465 int ret;
2466
2467 mark_runtime_wc(chip, azx_dev, substream, false);
2468 azx_dev->bufsize = 0;
2469 azx_dev->period_bytes = 0;
2470 azx_dev->format_val = 0;
2471 ret = snd_pcm_lib_malloc_pages(substream, size);
2472 if (ret < 0)
2473 return ret;
2474 mark_runtime_wc(chip, azx_dev, substream, true);
2475 return 0;
2476 }
2477
2478 static int substream_free_pages(struct azx *chip,
2479 struct snd_pcm_substream *substream)
2480 {
2481 struct azx_dev *azx_dev = get_azx_dev(substream);
2482 mark_runtime_wc(chip, azx_dev, substream, false);
2483 return snd_pcm_lib_free_pages(substream);
2484 }
2485
2486 static void pcm_mmap_prepare(struct snd_pcm_substream *substream,
2487 struct vm_area_struct *area)
2488 {
2489 #ifdef CONFIG_X86
2490 struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
2491 struct azx *chip = apcm->chip;
2492 if (!azx_snoop(chip))
2493 area->vm_page_prot = pgprot_writecombine(area->vm_page_prot);
2494 #endif
2495 }
2496
2497 static const struct hda_controller_ops pci_hda_ops = {
2498 .writel = pci_azx_writel,
2499 .readl = pci_azx_readl,
2500 .writew = pci_azx_writew,
2501 .readw = pci_azx_readw,
2502 .writeb = pci_azx_writeb,
2503 .readb = pci_azx_readb,
2504 .disable_msi_reset_irq = disable_msi_reset_irq,
2505 .dma_alloc_pages = dma_alloc_pages,
2506 .dma_free_pages = dma_free_pages,
2507 .substream_alloc_pages = substream_alloc_pages,
2508 .substream_free_pages = substream_free_pages,
2509 .pcm_mmap_prepare = pcm_mmap_prepare,
2510 };
2511
2512 static int azx_probe(struct pci_dev *pci,
2513 const struct pci_device_id *pci_id)
2514 {
2515 static int dev;
2516 struct snd_card *card;
2517 struct azx *chip;
2518 bool schedule_probe;
2519 int err;
2520
2521 if (dev >= SNDRV_CARDS)
2522 return -ENODEV;
2523 if (!enable[dev]) {
2524 dev++;
2525 return -ENOENT;
2526 }
2527
2528 err = snd_card_new(&pci->dev, index[dev], id[dev], THIS_MODULE,
2529 0, &card);
2530 if (err < 0) {
2531 dev_err(&pci->dev, "Error creating card!\n");
2532 return err;
2533 }
2534
2535 err = azx_create(card, pci, dev, pci_id->driver_data,
2536 &pci_hda_ops, &chip);
2537 if (err < 0)
2538 goto out_free;
2539 card->private_data = chip;
2540
2541 pci_set_drvdata(pci, card);
2542
2543 err = register_vga_switcheroo(chip);
2544 if (err < 0) {
2545 dev_err(card->dev, "Error registering VGA-switcheroo client\n");
2546 goto out_free;
2547 }
2548
2549 if (check_hdmi_disabled(pci)) {
2550 dev_info(card->dev, "VGA controller is disabled\n");
2551 dev_info(card->dev, "Delaying initialization\n");
2552 chip->disabled = true;
2553 }
2554
2555 schedule_probe = !chip->disabled;
2556
2557 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2558 if (patch[dev] && *patch[dev]) {
2559 dev_info(card->dev, "Applying patch firmware '%s'\n",
2560 patch[dev]);
2561 err = request_firmware_nowait(THIS_MODULE, true, patch[dev],
2562 &pci->dev, GFP_KERNEL, card,
2563 azx_firmware_cb);
2564 if (err < 0)
2565 goto out_free;
2566 schedule_probe = false; /* continued in azx_firmware_cb() */
2567 }
2568 #endif /* CONFIG_SND_HDA_PATCH_LOADER */
2569
2570 #ifndef CONFIG_SND_HDA_I915
2571 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL)
2572 dev_err(card->dev, "Haswell must build in CONFIG_SND_HDA_I915\n");
2573 #endif
2574
2575 if (schedule_probe)
2576 schedule_work(&chip->probe_work);
2577
2578 dev++;
2579 if (chip->disabled)
2580 complete_all(&chip->probe_wait);
2581 return 0;
2582
2583 out_free:
2584 snd_card_free(card);
2585 return err;
2586 }
2587
2588 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
2589 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] = {
2590 [AZX_DRIVER_NVIDIA] = 8,
2591 [AZX_DRIVER_TERA] = 1,
2592 };
2593
2594 static int azx_probe_continue(struct azx *chip)
2595 {
2596 struct pci_dev *pci = chip->pci;
2597 int dev = chip->dev_index;
2598 int err;
2599
2600 /* Request power well for Haswell HDA controller and codec */
2601 if (chip->driver_caps & AZX_DCAPS_I915_POWERWELL) {
2602 #ifdef CONFIG_SND_HDA_I915
2603 err = hda_i915_init();
2604 if (err < 0) {
2605 dev_err(chip->card->dev,
2606 "Error request power-well from i915\n");
2607 goto out_free;
2608 }
2609 #endif
2610 hda_display_power(true);
2611 }
2612
2613 err = azx_first_init(chip);
2614 if (err < 0)
2615 goto out_free;
2616
2617 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2618 chip->beep_mode = beep_mode[dev];
2619 #endif
2620
2621 /* create codec instances */
2622 err = azx_codec_create(chip, model[dev],
2623 azx_max_codecs[chip->driver_type],
2624 power_save_addr);
2625
2626 if (err < 0)
2627 goto out_free;
2628 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2629 if (chip->fw) {
2630 err = snd_hda_load_patch(chip->bus, chip->fw->size,
2631 chip->fw->data);
2632 if (err < 0)
2633 goto out_free;
2634 #ifndef CONFIG_PM
2635 release_firmware(chip->fw); /* no longer needed */
2636 chip->fw = NULL;
2637 #endif
2638 }
2639 #endif
2640 if ((probe_only[dev] & 1) == 0) {
2641 err = azx_codec_configure(chip);
2642 if (err < 0)
2643 goto out_free;
2644 }
2645
2646 /* create PCM streams */
2647 err = snd_hda_build_pcms(chip->bus);
2648 if (err < 0)
2649 goto out_free;
2650
2651 /* create mixer controls */
2652 err = azx_mixer_create(chip);
2653 if (err < 0)
2654 goto out_free;
2655
2656 err = snd_card_register(chip->card);
2657 if (err < 0)
2658 goto out_free;
2659
2660 chip->running = 1;
2661 power_down_all_codecs(chip);
2662 azx_notifier_register(chip);
2663 azx_add_card_list(chip);
2664 if ((chip->driver_caps & AZX_DCAPS_PM_RUNTIME) || chip->use_vga_switcheroo)
2665 pm_runtime_put_noidle(&pci->dev);
2666
2667 out_free:
2668 if (err < 0)
2669 chip->init_failed = 1;
2670 complete_all(&chip->probe_wait);
2671 return err;
2672 }
2673
2674 static void azx_remove(struct pci_dev *pci)
2675 {
2676 struct snd_card *card = pci_get_drvdata(pci);
2677
2678 if (card)
2679 snd_card_free(card);
2680 }
2681
2682 /* PCI IDs */
2683 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2684 /* CPT */
2685 { PCI_DEVICE(0x8086, 0x1c20),
2686 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2687 /* PBG */
2688 { PCI_DEVICE(0x8086, 0x1d20),
2689 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2690 /* Panther Point */
2691 { PCI_DEVICE(0x8086, 0x1e20),
2692 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2693 /* Lynx Point */
2694 { PCI_DEVICE(0x8086, 0x8c20),
2695 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2696 /* Wellsburg */
2697 { PCI_DEVICE(0x8086, 0x8d20),
2698 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2699 { PCI_DEVICE(0x8086, 0x8d21),
2700 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2701 /* Lynx Point-LP */
2702 { PCI_DEVICE(0x8086, 0x9c20),
2703 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2704 /* Lynx Point-LP */
2705 { PCI_DEVICE(0x8086, 0x9c21),
2706 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2707 /* Wildcat Point-LP */
2708 { PCI_DEVICE(0x8086, 0x9ca0),
2709 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
2710 /* Haswell */
2711 { PCI_DEVICE(0x8086, 0x0a0c),
2712 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2713 { PCI_DEVICE(0x8086, 0x0c0c),
2714 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2715 { PCI_DEVICE(0x8086, 0x0d0c),
2716 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2717 /* Broadwell */
2718 { PCI_DEVICE(0x8086, 0x160c),
2719 .driver_data = AZX_DRIVER_HDMI | AZX_DCAPS_INTEL_HASWELL },
2720 /* 5 Series/3400 */
2721 { PCI_DEVICE(0x8086, 0x3b56),
2722 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2723 /* Poulsbo */
2724 { PCI_DEVICE(0x8086, 0x811b),
2725 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2726 /* Oaktrail */
2727 { PCI_DEVICE(0x8086, 0x080a),
2728 .driver_data = AZX_DRIVER_SCH | AZX_DCAPS_INTEL_PCH_NOPM },
2729 /* BayTrail */
2730 { PCI_DEVICE(0x8086, 0x0f04),
2731 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
2732 /* ICH */
2733 { PCI_DEVICE(0x8086, 0x2668),
2734 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2735 AZX_DCAPS_BUFSIZE }, /* ICH6 */
2736 { PCI_DEVICE(0x8086, 0x27d8),
2737 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2738 AZX_DCAPS_BUFSIZE }, /* ICH7 */
2739 { PCI_DEVICE(0x8086, 0x269a),
2740 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2741 AZX_DCAPS_BUFSIZE }, /* ESB2 */
2742 { PCI_DEVICE(0x8086, 0x284b),
2743 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2744 AZX_DCAPS_BUFSIZE }, /* ICH8 */
2745 { PCI_DEVICE(0x8086, 0x293e),
2746 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2747 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2748 { PCI_DEVICE(0x8086, 0x293f),
2749 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2750 AZX_DCAPS_BUFSIZE }, /* ICH9 */
2751 { PCI_DEVICE(0x8086, 0x3a3e),
2752 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2753 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2754 { PCI_DEVICE(0x8086, 0x3a6e),
2755 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_OLD_SSYNC |
2756 AZX_DCAPS_BUFSIZE }, /* ICH10 */
2757 /* Generic Intel */
2758 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_ANY_ID),
2759 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2760 .class_mask = 0xffffff,
2761 .driver_data = AZX_DRIVER_ICH | AZX_DCAPS_BUFSIZE },
2762 /* ATI SB 450/600/700/800/900 */
2763 { PCI_DEVICE(0x1002, 0x437b),
2764 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2765 { PCI_DEVICE(0x1002, 0x4383),
2766 .driver_data = AZX_DRIVER_ATI | AZX_DCAPS_PRESET_ATI_SB },
2767 /* AMD Hudson */
2768 { PCI_DEVICE(0x1022, 0x780d),
2769 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_SB },
2770 /* ATI HDMI */
2771 { PCI_DEVICE(0x1002, 0x793b),
2772 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2773 { PCI_DEVICE(0x1002, 0x7919),
2774 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2775 { PCI_DEVICE(0x1002, 0x960f),
2776 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2777 { PCI_DEVICE(0x1002, 0x970f),
2778 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2779 { PCI_DEVICE(0x1002, 0xaa00),
2780 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2781 { PCI_DEVICE(0x1002, 0xaa08),
2782 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2783 { PCI_DEVICE(0x1002, 0xaa10),
2784 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2785 { PCI_DEVICE(0x1002, 0xaa18),
2786 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2787 { PCI_DEVICE(0x1002, 0xaa20),
2788 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2789 { PCI_DEVICE(0x1002, 0xaa28),
2790 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2791 { PCI_DEVICE(0x1002, 0xaa30),
2792 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2793 { PCI_DEVICE(0x1002, 0xaa38),
2794 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2795 { PCI_DEVICE(0x1002, 0xaa40),
2796 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2797 { PCI_DEVICE(0x1002, 0xaa48),
2798 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2799 { PCI_DEVICE(0x1002, 0xaa50),
2800 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2801 { PCI_DEVICE(0x1002, 0xaa58),
2802 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2803 { PCI_DEVICE(0x1002, 0xaa60),
2804 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2805 { PCI_DEVICE(0x1002, 0xaa68),
2806 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2807 { PCI_DEVICE(0x1002, 0xaa80),
2808 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2809 { PCI_DEVICE(0x1002, 0xaa88),
2810 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2811 { PCI_DEVICE(0x1002, 0xaa90),
2812 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2813 { PCI_DEVICE(0x1002, 0xaa98),
2814 .driver_data = AZX_DRIVER_ATIHDMI | AZX_DCAPS_PRESET_ATI_HDMI },
2815 { PCI_DEVICE(0x1002, 0x9902),
2816 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2817 { PCI_DEVICE(0x1002, 0xaaa0),
2818 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2819 { PCI_DEVICE(0x1002, 0xaaa8),
2820 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2821 { PCI_DEVICE(0x1002, 0xaab0),
2822 .driver_data = AZX_DRIVER_ATIHDMI_NS | AZX_DCAPS_PRESET_ATI_HDMI },
2823 /* VIA VT8251/VT8237A */
2824 { PCI_DEVICE(0x1106, 0x3288),
2825 .driver_data = AZX_DRIVER_VIA | AZX_DCAPS_POSFIX_VIA },
2826 /* VIA GFX VT7122/VX900 */
2827 { PCI_DEVICE(0x1106, 0x9170), .driver_data = AZX_DRIVER_GENERIC },
2828 /* VIA GFX VT6122/VX11 */
2829 { PCI_DEVICE(0x1106, 0x9140), .driver_data = AZX_DRIVER_GENERIC },
2830 /* SIS966 */
2831 { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2832 /* ULI M5461 */
2833 { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2834 /* NVIDIA MCP */
2835 { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2836 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2837 .class_mask = 0xffffff,
2838 .driver_data = AZX_DRIVER_NVIDIA | AZX_DCAPS_PRESET_NVIDIA },
2839 /* Teradici */
2840 { PCI_DEVICE(0x6549, 0x1200),
2841 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2842 { PCI_DEVICE(0x6549, 0x2200),
2843 .driver_data = AZX_DRIVER_TERA | AZX_DCAPS_NO_64BIT },
2844 /* Creative X-Fi (CA0110-IBG) */
2845 /* CTHDA chips */
2846 { PCI_DEVICE(0x1102, 0x0010),
2847 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2848 { PCI_DEVICE(0x1102, 0x0012),
2849 .driver_data = AZX_DRIVER_CTHDA | AZX_DCAPS_PRESET_CTHDA },
2850 #if !IS_ENABLED(CONFIG_SND_CTXFI)
2851 /* the following entry conflicts with snd-ctxfi driver,
2852 * as ctxfi driver mutates from HD-audio to native mode with
2853 * a special command sequence.
2854 */
2855 { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2856 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2857 .class_mask = 0xffffff,
2858 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2859 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2860 #else
2861 /* this entry seems still valid -- i.e. without emu20kx chip */
2862 { PCI_DEVICE(0x1102, 0x0009),
2863 .driver_data = AZX_DRIVER_CTX | AZX_DCAPS_CTX_WORKAROUND |
2864 AZX_DCAPS_RIRB_PRE_DELAY | AZX_DCAPS_POSFIX_LPIB },
2865 #endif
2866 /* Vortex86MX */
2867 { PCI_DEVICE(0x17f3, 0x3010), .driver_data = AZX_DRIVER_GENERIC },
2868 /* VMware HDAudio */
2869 { PCI_DEVICE(0x15ad, 0x1977), .driver_data = AZX_DRIVER_GENERIC },
2870 /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2871 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2872 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2873 .class_mask = 0xffffff,
2874 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2875 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2876 .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2877 .class_mask = 0xffffff,
2878 .driver_data = AZX_DRIVER_GENERIC | AZX_DCAPS_PRESET_ATI_HDMI },
2879 { 0, }
2880 };
2881 MODULE_DEVICE_TABLE(pci, azx_ids);
2882
2883 /* pci_driver definition */
2884 static struct pci_driver azx_driver = {
2885 .name = KBUILD_MODNAME,
2886 .id_table = azx_ids,
2887 .probe = azx_probe,
2888 .remove = azx_remove,
2889 .driver = {
2890 .pm = AZX_PM_OPS,
2891 },
2892 };
2893
2894 module_pci_driver(azx_driver);
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