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netxen: enable ip addr hashing
[linux-2.6/btrfs-unstable.git] / drivers / net / netxen / netxen_nic_hw.c
blob088611bb5bdbc16c13a55c00d6e577c26638bebe
1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
19 *
20 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
22 *
23 * Contact Information:
24 * info@netxen.com
25 * NetXen Inc,
26 * 18922 Forge Drive
27 * Cupertino, CA 95014-0701
28 *
29 */
30
31 #include "netxen_nic.h"
32 #include "netxen_nic_hw.h"
33 #include "netxen_nic_phan_reg.h"
34
35 #include <net/ip.h>
36
37 #define MASK(n) ((1ULL<<(n))-1)
38 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
39 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
40 #define MS_WIN(addr) (addr & 0x0ffc0000)
41
42 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
43
44 #define CRB_BLK(off) ((off >> 20) & 0x3f)
45 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
46 #define CRB_WINDOW_2M (0x130060)
47 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
48 #define CRB_INDIRECT_2M (0x1e0000UL)
49
50 #ifndef readq
51 static inline u64 readq(void __iomem *addr)
52 {
53 return readl(addr) | (((u64) readl(addr + 4)) << 32LL);
54 }
55 #endif
56
57 #ifndef writeq
58 static inline void writeq(u64 val, void __iomem *addr)
59 {
60 writel(((u32) (val)), (addr));
61 writel(((u32) (val >> 32)), (addr + 4));
62 }
63 #endif
64
65 #define ADDR_IN_RANGE(addr, low, high) \
66 (((addr) < (high)) && ((addr) >= (low)))
67
68 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
69 ((adapter)->ahw.pci_base0 + (off))
70 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
71 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
72 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
73 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
74
75 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
76 unsigned long off)
77 {
78 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
79 return PCI_OFFSET_FIRST_RANGE(adapter, off);
80
81 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
82 return PCI_OFFSET_SECOND_RANGE(adapter, off);
83
84 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
85 return PCI_OFFSET_THIRD_RANGE(adapter, off);
86
87 return NULL;
88 }
89
90 #define CRB_WIN_LOCK_TIMEOUT 100000000
91 static crb_128M_2M_block_map_t
92 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
93 {{{0, 0, 0, 0} } }, /* 0: PCI */
94 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
95 {1, 0x0110000, 0x0120000, 0x130000},
96 {1, 0x0120000, 0x0122000, 0x124000},
97 {1, 0x0130000, 0x0132000, 0x126000},
98 {1, 0x0140000, 0x0142000, 0x128000},
99 {1, 0x0150000, 0x0152000, 0x12a000},
100 {1, 0x0160000, 0x0170000, 0x110000},
101 {1, 0x0170000, 0x0172000, 0x12e000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {1, 0x01e0000, 0x01e0800, 0x122000},
109 {0, 0x0000000, 0x0000000, 0x000000} } },
110 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
111 {{{0, 0, 0, 0} } }, /* 3: */
112 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
113 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
114 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
115 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
116 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {0, 0x0000000, 0x0000000, 0x000000},
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {1, 0x08f0000, 0x08f2000, 0x172000} } },
132 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {1, 0x09f0000, 0x09f2000, 0x176000} } },
148 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
164 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
165 {0, 0x0000000, 0x0000000, 0x000000},
166 {0, 0x0000000, 0x0000000, 0x000000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
180 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
181 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
182 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
183 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
184 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
185 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
186 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
187 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
188 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
189 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
190 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
191 {{{0, 0, 0, 0} } }, /* 23: */
192 {{{0, 0, 0, 0} } }, /* 24: */
193 {{{0, 0, 0, 0} } }, /* 25: */
194 {{{0, 0, 0, 0} } }, /* 26: */
195 {{{0, 0, 0, 0} } }, /* 27: */
196 {{{0, 0, 0, 0} } }, /* 28: */
197 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
198 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
199 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
200 {{{0} } }, /* 32: PCI */
201 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
202 {1, 0x2110000, 0x2120000, 0x130000},
203 {1, 0x2120000, 0x2122000, 0x124000},
204 {1, 0x2130000, 0x2132000, 0x126000},
205 {1, 0x2140000, 0x2142000, 0x128000},
206 {1, 0x2150000, 0x2152000, 0x12a000},
207 {1, 0x2160000, 0x2170000, 0x110000},
208 {1, 0x2170000, 0x2172000, 0x12e000},
209 {0, 0x0000000, 0x0000000, 0x000000},
210 {0, 0x0000000, 0x0000000, 0x000000},
211 {0, 0x0000000, 0x0000000, 0x000000},
212 {0, 0x0000000, 0x0000000, 0x000000},
213 {0, 0x0000000, 0x0000000, 0x000000},
214 {0, 0x0000000, 0x0000000, 0x000000},
215 {0, 0x0000000, 0x0000000, 0x000000},
216 {0, 0x0000000, 0x0000000, 0x000000} } },
217 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
218 {{{0} } }, /* 35: */
219 {{{0} } }, /* 36: */
220 {{{0} } }, /* 37: */
221 {{{0} } }, /* 38: */
222 {{{0} } }, /* 39: */
223 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
224 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
225 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
226 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
227 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
228 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
229 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
230 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
231 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
232 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
233 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
234 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
235 {{{0} } }, /* 52: */
236 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
237 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
238 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
239 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
240 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
241 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
242 {{{0} } }, /* 59: I2C0 */
243 {{{0} } }, /* 60: I2C1 */
244 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
245 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
246 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
247 };
248
249 /*
250 * top 12 bits of crb internal address (hub, agent)
251 */
252 static unsigned crb_hub_agt[64] =
253 {
254 0,
255 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
256 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
257 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
260 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
261 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
262 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
264 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
265 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
266 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
267 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
270 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
271 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
272 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
273 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
274 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
275 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
276 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
277 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
278 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
280 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
281 0,
282 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
283 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
284 0,
285 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
286 0,
287 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
288 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
289 0,
290 0,
291 0,
292 0,
293 0,
294 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
295 0,
296 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
297 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
298 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
299 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
300 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
301 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
302 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
303 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
304 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
305 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
306 0,
307 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
308 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
309 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
310 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
311 0,
312 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
313 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
314 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
315 0,
316 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
317 0,
318 };
319
320 /* PCI Windowing for DDR regions. */
321
322 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
323
324 #define NETXEN_UNICAST_ADDR(port, index) \
325 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
326 #define NETXEN_MCAST_ADDR(port, index) \
327 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
328 #define MAC_HI(addr) \
329 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
330 #define MAC_LO(addr) \
331 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
332
333 static int
334 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
335 {
336 u32 val = 0;
337 u16 port = adapter->physical_port;
338 u8 *addr = adapter->netdev->dev_addr;
339
340 if (adapter->mc_enabled)
341 return 0;
342
343 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
344 val |= (1UL << (28+port));
345 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
346
347 /* add broadcast addr to filter */
348 val = 0xffffff;
349 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
350 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
351
352 /* add station addr to filter */
353 val = MAC_HI(addr);
354 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
355 val = MAC_LO(addr);
356 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
357
358 adapter->mc_enabled = 1;
359 return 0;
360 }
361
362 static int
363 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
364 {
365 u32 val = 0;
366 u16 port = adapter->physical_port;
367 u8 *addr = adapter->netdev->dev_addr;
368
369 if (!adapter->mc_enabled)
370 return 0;
371
372 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
373 val &= ~(1UL << (28+port));
374 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
375
376 val = MAC_HI(addr);
377 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
378 val = MAC_LO(addr);
379 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
380
381 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
382 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
383
384 adapter->mc_enabled = 0;
385 return 0;
386 }
387
388 static int
389 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
390 int index, u8 *addr)
391 {
392 u32 hi = 0, lo = 0;
393 u16 port = adapter->physical_port;
394
395 lo = MAC_LO(addr);
396 hi = MAC_HI(addr);
397
398 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
399 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
400
401 return 0;
402 }
403
404 void netxen_p2_nic_set_multi(struct net_device *netdev)
405 {
406 struct netxen_adapter *adapter = netdev_priv(netdev);
407 struct dev_mc_list *mc_ptr;
408 u8 null_addr[6];
409 int index = 0;
410
411 memset(null_addr, 0, 6);
412
413 if (netdev->flags & IFF_PROMISC) {
414
415 adapter->set_promisc(adapter,
416 NETXEN_NIU_PROMISC_MODE);
417
418 /* Full promiscuous mode */
419 netxen_nic_disable_mcast_filter(adapter);
420
421 return;
422 }
423
424 if (netdev->mc_count == 0) {
425 adapter->set_promisc(adapter,
426 NETXEN_NIU_NON_PROMISC_MODE);
427 netxen_nic_disable_mcast_filter(adapter);
428 return;
429 }
430
431 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
432 if (netdev->flags & IFF_ALLMULTI ||
433 netdev->mc_count > adapter->max_mc_count) {
434 netxen_nic_disable_mcast_filter(adapter);
435 return;
436 }
437
438 netxen_nic_enable_mcast_filter(adapter);
439
440 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
441 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
442
443 if (index != netdev->mc_count)
444 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
445 netxen_nic_driver_name, netdev->name);
446
447 /* Clear out remaining addresses */
448 for (; index < adapter->max_mc_count; index++)
449 netxen_nic_set_mcast_addr(adapter, index, null_addr);
450 }
451
452 static int
453 netxen_send_cmd_descs(struct netxen_adapter *adapter,
454 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
455 {
456 u32 i, producer, consumer;
457 struct netxen_cmd_buffer *pbuf;
458 struct cmd_desc_type0 *cmd_desc;
459 struct nx_host_tx_ring *tx_ring;
460
461 i = 0;
462
463 tx_ring = adapter->tx_ring;
464 __netif_tx_lock_bh(tx_ring->txq);
465
466 producer = tx_ring->producer;
467 consumer = tx_ring->sw_consumer;
468
469 if (nr_desc >= netxen_tx_avail(tx_ring)) {
470 netif_tx_stop_queue(tx_ring->txq);
471 __netif_tx_unlock_bh(tx_ring->txq);
472 return -EBUSY;
473 }
474
475 do {
476 cmd_desc = &cmd_desc_arr[i];
477
478 pbuf = &tx_ring->cmd_buf_arr[producer];
479 pbuf->skb = NULL;
480 pbuf->frag_count = 0;
481
482 memcpy(&tx_ring->desc_head[producer],
483 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
484
485 producer = get_next_index(producer, tx_ring->num_desc);
486 i++;
487
488 } while (i != nr_desc);
489
490 tx_ring->producer = producer;
491
492 netxen_nic_update_cmd_producer(adapter, tx_ring);
493
494 __netif_tx_unlock_bh(tx_ring->txq);
495
496 return 0;
497 }
498
499 static int
500 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
501 {
502 nx_nic_req_t req;
503 nx_mac_req_t *mac_req;
504 u64 word;
505
506 memset(&req, 0, sizeof(nx_nic_req_t));
507 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
508
509 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
510 req.req_hdr = cpu_to_le64(word);
511
512 mac_req = (nx_mac_req_t *)&req.words[0];
513 mac_req->op = op;
514 memcpy(mac_req->mac_addr, addr, 6);
515
516 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
517 }
518
519 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
520 u8 *addr, struct list_head *del_list)
521 {
522 struct list_head *head;
523 nx_mac_list_t *cur;
524
525 /* look up if already exists */
526 list_for_each(head, del_list) {
527 cur = list_entry(head, nx_mac_list_t, list);
528
529 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
530 list_move_tail(head, &adapter->mac_list);
531 return 0;
532 }
533 }
534
535 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
536 if (cur == NULL) {
537 printk(KERN_ERR "%s: failed to add mac address filter\n",
538 adapter->netdev->name);
539 return -ENOMEM;
540 }
541 memcpy(cur->mac_addr, addr, ETH_ALEN);
542 list_add_tail(&cur->list, &adapter->mac_list);
543 return nx_p3_sre_macaddr_change(adapter,
544 cur->mac_addr, NETXEN_MAC_ADD);
545 }
546
547 void netxen_p3_nic_set_multi(struct net_device *netdev)
548 {
549 struct netxen_adapter *adapter = netdev_priv(netdev);
550 struct dev_mc_list *mc_ptr;
551 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
552 u32 mode = VPORT_MISS_MODE_DROP;
553 LIST_HEAD(del_list);
554 struct list_head *head;
555 nx_mac_list_t *cur;
556
557 list_splice_tail_init(&adapter->mac_list, &del_list);
558
559 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &del_list);
560 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
561
562 if (netdev->flags & IFF_PROMISC) {
563 mode = VPORT_MISS_MODE_ACCEPT_ALL;
564 goto send_fw_cmd;
565 }
566
567 if ((netdev->flags & IFF_ALLMULTI) ||
568 (netdev->mc_count > adapter->max_mc_count)) {
569 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
570 goto send_fw_cmd;
571 }
572
573 if (netdev->mc_count > 0) {
574 for (mc_ptr = netdev->mc_list; mc_ptr;
575 mc_ptr = mc_ptr->next) {
576 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr, &del_list);
577 }
578 }
579
580 send_fw_cmd:
581 adapter->set_promisc(adapter, mode);
582 head = &del_list;
583 while (!list_empty(head)) {
584 cur = list_entry(head->next, nx_mac_list_t, list);
585
586 nx_p3_sre_macaddr_change(adapter,
587 cur->mac_addr, NETXEN_MAC_DEL);
588 list_del(&cur->list);
589 kfree(cur);
590 }
591 }
592
593 int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
594 {
595 nx_nic_req_t req;
596 u64 word;
597
598 memset(&req, 0, sizeof(nx_nic_req_t));
599
600 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
601
602 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
603 ((u64)adapter->portnum << 16);
604 req.req_hdr = cpu_to_le64(word);
605
606 req.words[0] = cpu_to_le64(mode);
607
608 return netxen_send_cmd_descs(adapter,
609 (struct cmd_desc_type0 *)&req, 1);
610 }
611
612 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
613 {
614 nx_mac_list_t *cur;
615 struct list_head *head = &adapter->mac_list;
616
617 while (!list_empty(head)) {
618 cur = list_entry(head->next, nx_mac_list_t, list);
619 nx_p3_sre_macaddr_change(adapter,
620 cur->mac_addr, NETXEN_MAC_DEL);
621 list_del(&cur->list);
622 kfree(cur);
623 }
624 }
625
626 int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
627 {
628 /* assuming caller has already copied new addr to netdev */
629 netxen_p3_nic_set_multi(adapter->netdev);
630 return 0;
631 }
632
633 #define NETXEN_CONFIG_INTR_COALESCE 3
634
635 /*
636 * Send the interrupt coalescing parameter set by ethtool to the card.
637 */
638 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
639 {
640 nx_nic_req_t req;
641 u64 word;
642 int rv;
643
644 memset(&req, 0, sizeof(nx_nic_req_t));
645
646 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
647
648 word = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
649 req.req_hdr = cpu_to_le64(word);
650
651 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
652
653 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
654 if (rv != 0) {
655 printk(KERN_ERR "ERROR. Could not send "
656 "interrupt coalescing parameters\n");
657 }
658
659 return rv;
660 }
661
662 #define RSS_HASHTYPE_IP_TCP 0x3
663
664 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
665 {
666 nx_nic_req_t req;
667 u64 word;
668 int i, rv;
669
670 u64 key[] = { 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
671 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
672 0x255b0ec26d5a56daULL };
673
674
675 memset(&req, 0, sizeof(nx_nic_req_t));
676 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
677
678 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
679 req.req_hdr = cpu_to_le64(word);
680
681 /*
682 * RSS request:
683 * bits 3-0: hash_method
684 * 5-4: hash_type_ipv4
685 * 7-6: hash_type_ipv6
686 * 8: enable
687 * 9: use indirection table
688 * 47-10: reserved
689 * 63-48: indirection table mask
690 */
691 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
692 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
693 ((u64)(enable & 0x1) << 8) |
694 ((0x7ULL) << 48);
695 req.words[0] = cpu_to_le64(word);
696 for (i = 0; i < 5; i++)
697 req.words[i+1] = cpu_to_le64(key[i]);
698
699
700 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
701 if (rv != 0) {
702 printk(KERN_ERR "%s: could not configure RSS\n",
703 adapter->netdev->name);
704 }
705
706 return rv;
707 }
708
709 int netxen_config_ipaddr(struct netxen_adapter *adapter, u32 ip, int cmd)
710 {
711 nx_nic_req_t req;
712 u64 word;
713 int rv;
714
715 memset(&req, 0, sizeof(nx_nic_req_t));
716 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
717
718 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
719 req.req_hdr = cpu_to_le64(word);
720
721 req.words[0] = cpu_to_le64(cmd);
722 req.words[1] = cpu_to_le64(ip);
723
724 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
725 if (rv != 0) {
726 printk(KERN_ERR "%s: could not notify %s IP 0x%x reuqest\n",
727 adapter->netdev->name,
728 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
729 }
730 return rv;
731 }
732
733 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
734 {
735 nx_nic_req_t req;
736 u64 word;
737 int rv;
738
739 memset(&req, 0, sizeof(nx_nic_req_t));
740 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
741
742 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
743 req.req_hdr = cpu_to_le64(word);
744 req.words[0] = cpu_to_le64(enable | (enable << 8));
745
746 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
747 if (rv != 0) {
748 printk(KERN_ERR "%s: could not configure link notification\n",
749 adapter->netdev->name);
750 }
751
752 return rv;
753 }
754
755 /*
756 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
757 * @returns 0 on success, negative on failure
758 */
759
760 #define MTU_FUDGE_FACTOR 100
761
762 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
763 {
764 struct netxen_adapter *adapter = netdev_priv(netdev);
765 int max_mtu;
766 int rc = 0;
767
768 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
769 max_mtu = P3_MAX_MTU;
770 else
771 max_mtu = P2_MAX_MTU;
772
773 if (mtu > max_mtu) {
774 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
775 netdev->name, max_mtu);
776 return -EINVAL;
777 }
778
779 if (adapter->set_mtu)
780 rc = adapter->set_mtu(adapter, mtu);
781
782 if (!rc)
783 netdev->mtu = mtu;
784
785 return rc;
786 }
787
788 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
789 int size, __le32 * buf)
790 {
791 int i, v, addr;
792 __le32 *ptr32;
793
794 addr = base;
795 ptr32 = buf;
796 for (i = 0; i < size / sizeof(u32); i++) {
797 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
798 return -1;
799 *ptr32 = cpu_to_le32(v);
800 ptr32++;
801 addr += sizeof(u32);
802 }
803 if ((char *)buf + size > (char *)ptr32) {
804 __le32 local;
805 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
806 return -1;
807 local = cpu_to_le32(v);
808 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
809 }
810
811 return 0;
812 }
813
814 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
815 {
816 __le32 *pmac = (__le32 *) mac;
817 u32 offset;
818
819 offset = NETXEN_USER_START +
820 offsetof(struct netxen_new_user_info, mac_addr) +
821 adapter->portnum * sizeof(u64);
822
823 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
824 return -1;
825
826 if (*mac == cpu_to_le64(~0ULL)) {
827
828 offset = NETXEN_USER_START_OLD +
829 offsetof(struct netxen_user_old_info, mac_addr) +
830 adapter->portnum * sizeof(u64);
831
832 if (netxen_get_flash_block(adapter,
833 offset, sizeof(u64), pmac) == -1)
834 return -1;
835
836 if (*mac == cpu_to_le64(~0ULL))
837 return -1;
838 }
839 return 0;
840 }
841
842 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, __le64 *mac)
843 {
844 uint32_t crbaddr, mac_hi, mac_lo;
845 int pci_func = adapter->ahw.pci_func;
846
847 crbaddr = CRB_MAC_BLOCK_START +
848 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
849
850 mac_lo = NXRD32(adapter, crbaddr);
851 mac_hi = NXRD32(adapter, crbaddr+4);
852
853 if (pci_func & 1)
854 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
855 else
856 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
857
858 return 0;
859 }
860
861 #define CRB_WIN_LOCK_TIMEOUT 100000000
862
863 static int crb_win_lock(struct netxen_adapter *adapter)
864 {
865 int done = 0, timeout = 0;
866
867 while (!done) {
868 /* acquire semaphore3 from PCI HW block */
869 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_LOCK));
870 if (done == 1)
871 break;
872 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
873 return -1;
874 timeout++;
875 udelay(1);
876 }
877 NXWR32(adapter, NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
878 return 0;
879 }
880
881 static void crb_win_unlock(struct netxen_adapter *adapter)
882 {
883 int val;
884
885 val = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK));
886 }
887
888 /*
889 * Changes the CRB window to the specified window.
890 */
891 void
892 netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
893 {
894 void __iomem *offset;
895 u32 tmp;
896 int count = 0;
897 uint8_t func = adapter->ahw.pci_func;
898
899 if (adapter->curr_window == wndw)
900 return;
901 /*
902 * Move the CRB window.
903 * We need to write to the "direct access" region of PCI
904 * to avoid a race condition where the window register has
905 * not been successfully written across CRB before the target
906 * register address is received by PCI. The direct region bypasses
907 * the CRB bus.
908 */
909 offset = PCI_OFFSET_SECOND_RANGE(adapter,
910 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
911
912 if (wndw & 0x1)
913 wndw = NETXEN_WINDOW_ONE;
914
915 writel(wndw, offset);
916
917 /* MUST make sure window is set before we forge on... */
918 while ((tmp = readl(offset)) != wndw) {
919 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
920 "registered properly: 0x%08x.\n",
921 netxen_nic_driver_name, __func__, tmp);
922 mdelay(1);
923 if (count >= 10)
924 break;
925 count++;
926 }
927
928 if (wndw == NETXEN_WINDOW_ONE)
929 adapter->curr_window = 1;
930 else
931 adapter->curr_window = 0;
932 }
933
934 /*
935 * Return -1 if off is not valid,
936 * 1 if window access is needed. 'off' is set to offset from
937 * CRB space in 128M pci map
938 * 0 if no window access is needed. 'off' is set to 2M addr
939 * In: 'off' is offset from base in 128M pci map
940 */
941 static int
942 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter, ulong *off)
943 {
944 crb_128M_2M_sub_block_map_t *m;
945
946
947 if (*off >= NETXEN_CRB_MAX)
948 return -1;
949
950 if (*off >= NETXEN_PCI_CAMQM && (*off < NETXEN_PCI_CAMQM_2M_END)) {
951 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
952 (ulong)adapter->ahw.pci_base0;
953 return 0;
954 }
955
956 if (*off < NETXEN_PCI_CRBSPACE)
957 return -1;
958
959 *off -= NETXEN_PCI_CRBSPACE;
960
961 /*
962 * Try direct map
963 */
964 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
965
966 if (m->valid && (m->start_128M <= *off) && (m->end_128M > *off)) {
967 *off = *off + m->start_2M - m->start_128M +
968 (ulong)adapter->ahw.pci_base0;
969 return 0;
970 }
971
972 /*
973 * Not in direct map, use crb window
974 */
975 return 1;
976 }
977
978 /*
979 * In: 'off' is offset from CRB space in 128M pci map
980 * Out: 'off' is 2M pci map addr
981 * side effect: lock crb window
982 */
983 static void
984 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
985 {
986 u32 win_read;
987
988 adapter->crb_win = CRB_HI(*off);
989 writel(adapter->crb_win, (adapter->ahw.pci_base0 + CRB_WINDOW_2M));
990 /*
991 * Read back value to make sure write has gone through before trying
992 * to use it.
993 */
994 win_read = readl(adapter->ahw.pci_base0 + CRB_WINDOW_2M);
995 if (win_read != adapter->crb_win) {
996 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
997 "Read crbwin (0x%x), off=0x%lx\n",
998 __func__, adapter->crb_win, win_read, *off);
999 }
1000 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
1001 (ulong)adapter->ahw.pci_base0;
1002 }
1003
1004 int
1005 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1006 {
1007 void __iomem *addr;
1008
1009 if (ADDR_IN_WINDOW1(off)) {
1010 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1011 } else { /* Window 0 */
1012 addr = pci_base_offset(adapter, off);
1013 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1014 }
1015
1016 if (!addr) {
1017 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1018 return 1;
1019 }
1020
1021 writel(data, addr);
1022
1023 if (!ADDR_IN_WINDOW1(off))
1024 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1025
1026 return 0;
1027 }
1028
1029 u32
1030 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1031 {
1032 void __iomem *addr;
1033 u32 data;
1034
1035 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1036 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1037 } else { /* Window 0 */
1038 addr = pci_base_offset(adapter, off);
1039 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1040 }
1041
1042 if (!addr) {
1043 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1044 return 1;
1045 }
1046
1047 data = readl(addr);
1048
1049 if (!ADDR_IN_WINDOW1(off))
1050 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1051
1052 return data;
1053 }
1054
1055 int
1056 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1057 {
1058 unsigned long flags = 0;
1059 int rv;
1060
1061 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1062
1063 if (rv == -1) {
1064 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1065 __func__, off);
1066 dump_stack();
1067 return -1;
1068 }
1069
1070 if (rv == 1) {
1071 write_lock_irqsave(&adapter->adapter_lock, flags);
1072 crb_win_lock(adapter);
1073 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1074 writel(data, (void __iomem *)off);
1075 crb_win_unlock(adapter);
1076 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1077 } else
1078 writel(data, (void __iomem *)off);
1079
1080
1081 return 0;
1082 }
1083
1084 u32
1085 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1086 {
1087 unsigned long flags = 0;
1088 int rv;
1089 u32 data;
1090
1091 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off);
1092
1093 if (rv == -1) {
1094 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1095 __func__, off);
1096 dump_stack();
1097 return -1;
1098 }
1099
1100 if (rv == 1) {
1101 write_lock_irqsave(&adapter->adapter_lock, flags);
1102 crb_win_lock(adapter);
1103 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1104 data = readl((void __iomem *)off);
1105 crb_win_unlock(adapter);
1106 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1107 } else
1108 data = readl((void __iomem *)off);
1109
1110 return data;
1111 }
1112
1113 /*
1114 * check memory access boundary.
1115 * used by test agent. support ddr access only for now
1116 */
1117 static unsigned long
1118 netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1119 unsigned long long addr, int size)
1120 {
1121 if (!ADDR_IN_RANGE(addr,
1122 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1123 !ADDR_IN_RANGE(addr+size-1,
1124 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1125 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1126 return 0;
1127 }
1128
1129 return 1;
1130 }
1131
1132 static int netxen_pci_set_window_warning_count;
1133
1134 unsigned long
1135 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1136 unsigned long long addr)
1137 {
1138 void __iomem *offset;
1139 int window;
1140 unsigned long long qdr_max;
1141 uint8_t func = adapter->ahw.pci_func;
1142
1143 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1144 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1145 } else {
1146 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1147 }
1148
1149 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1150 /* DDR network side */
1151 addr -= NETXEN_ADDR_DDR_NET;
1152 window = (addr >> 25) & 0x3ff;
1153 if (adapter->ahw.ddr_mn_window != window) {
1154 adapter->ahw.ddr_mn_window = window;
1155 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1156 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1157 writel(window, offset);
1158 /* MUST make sure window is set before we forge on... */
1159 readl(offset);
1160 }
1161 addr -= (window * NETXEN_WINDOW_ONE);
1162 addr += NETXEN_PCI_DDR_NET;
1163 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1164 addr -= NETXEN_ADDR_OCM0;
1165 addr += NETXEN_PCI_OCM0;
1166 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1167 addr -= NETXEN_ADDR_OCM1;
1168 addr += NETXEN_PCI_OCM1;
1169 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1170 /* QDR network side */
1171 addr -= NETXEN_ADDR_QDR_NET;
1172 window = (addr >> 22) & 0x3f;
1173 if (adapter->ahw.qdr_sn_window != window) {
1174 adapter->ahw.qdr_sn_window = window;
1175 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1176 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1177 writel((window << 22), offset);
1178 /* MUST make sure window is set before we forge on... */
1179 readl(offset);
1180 }
1181 addr -= (window * 0x400000);
1182 addr += NETXEN_PCI_QDR_NET;
1183 } else {
1184 /*
1185 * peg gdb frequently accesses memory that doesn't exist,
1186 * this limits the chit chat so debugging isn't slowed down.
1187 */
1188 if ((netxen_pci_set_window_warning_count++ < 8)
1189 || (netxen_pci_set_window_warning_count % 64 == 0))
1190 printk("%s: Warning:netxen_nic_pci_set_window()"
1191 " Unknown address range!\n",
1192 netxen_nic_driver_name);
1193 addr = -1UL;
1194 }
1195 return addr;
1196 }
1197
1198 /*
1199 * Note : only 32-bit writes!
1200 */
1201 int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1202 u64 off, u32 data)
1203 {
1204 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1205 return 0;
1206 }
1207
1208 u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1209 {
1210 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1211 }
1212
1213 unsigned long
1214 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1215 unsigned long long addr)
1216 {
1217 int window;
1218 u32 win_read;
1219
1220 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1221 /* DDR network side */
1222 window = MN_WIN(addr);
1223 adapter->ahw.ddr_mn_window = window;
1224 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1225 window);
1226 win_read = NXRD32(adapter,
1227 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1228 if ((win_read << 17) != window) {
1229 printk(KERN_INFO "Written MNwin (0x%x) != "
1230 "Read MNwin (0x%x)\n", window, win_read);
1231 }
1232 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1233 } else if (ADDR_IN_RANGE(addr,
1234 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1235 if ((addr & 0x00ff800) == 0xff800) {
1236 printk("%s: QM access not handled.\n", __func__);
1237 addr = -1UL;
1238 }
1239
1240 window = OCM_WIN(addr);
1241 adapter->ahw.ddr_mn_window = window;
1242 NXWR32(adapter, adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1243 window);
1244 win_read = NXRD32(adapter,
1245 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE);
1246 if ((win_read >> 7) != window) {
1247 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1248 "Read OCMwin (0x%x)\n",
1249 __func__, window, win_read);
1250 }
1251 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1252
1253 } else if (ADDR_IN_RANGE(addr,
1254 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1255 /* QDR network side */
1256 window = MS_WIN(addr);
1257 adapter->ahw.qdr_sn_window = window;
1258 NXWR32(adapter, adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1259 window);
1260 win_read = NXRD32(adapter,
1261 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE);
1262 if (win_read != window) {
1263 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1264 "Read MSwin (0x%x)\n",
1265 __func__, window, win_read);
1266 }
1267 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1268
1269 } else {
1270 /*
1271 * peg gdb frequently accesses memory that doesn't exist,
1272 * this limits the chit chat so debugging isn't slowed down.
1273 */
1274 if ((netxen_pci_set_window_warning_count++ < 8)
1275 || (netxen_pci_set_window_warning_count%64 == 0)) {
1276 printk("%s: Warning:%s Unknown address range!\n",
1277 __func__, netxen_nic_driver_name);
1278 }
1279 addr = -1UL;
1280 }
1281 return addr;
1282 }
1283
1284 static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1285 unsigned long long addr)
1286 {
1287 int window;
1288 unsigned long long qdr_max;
1289
1290 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1291 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1292 else
1293 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1294
1295 if (ADDR_IN_RANGE(addr,
1296 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1297 /* DDR network side */
1298 BUG(); /* MN access can not come here */
1299 } else if (ADDR_IN_RANGE(addr,
1300 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1301 return 1;
1302 } else if (ADDR_IN_RANGE(addr,
1303 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1304 return 1;
1305 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1306 /* QDR network side */
1307 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1308 if (adapter->ahw.qdr_sn_window == window)
1309 return 1;
1310 }
1311
1312 return 0;
1313 }
1314
1315 static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1316 u64 off, void *data, int size)
1317 {
1318 unsigned long flags;
1319 void __iomem *addr, *mem_ptr = NULL;
1320 int ret = 0;
1321 u64 start;
1322 unsigned long mem_base;
1323 unsigned long mem_page;
1324
1325 write_lock_irqsave(&adapter->adapter_lock, flags);
1326
1327 /*
1328 * If attempting to access unknown address or straddle hw windows,
1329 * do not access.
1330 */
1331 start = adapter->pci_set_window(adapter, off);
1332 if ((start == -1UL) ||
1333 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1334 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1335 printk(KERN_ERR "%s out of bound pci memory access. "
1336 "offset is 0x%llx\n", netxen_nic_driver_name,
1337 (unsigned long long)off);
1338 return -1;
1339 }
1340
1341 addr = pci_base_offset(adapter, start);
1342 if (!addr) {
1343 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1344 mem_base = pci_resource_start(adapter->pdev, 0);
1345 mem_page = start & PAGE_MASK;
1346 /* Map two pages whenever user tries to access addresses in two
1347 consecutive pages.
1348 */
1349 if (mem_page != ((start + size - 1) & PAGE_MASK))
1350 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1351 else
1352 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1353 if (mem_ptr == NULL) {
1354 *(uint8_t *)data = 0;
1355 return -1;
1356 }
1357 addr = mem_ptr;
1358 addr += start & (PAGE_SIZE - 1);
1359 write_lock_irqsave(&adapter->adapter_lock, flags);
1360 }
1361
1362 switch (size) {
1363 case 1:
1364 *(uint8_t *)data = readb(addr);
1365 break;
1366 case 2:
1367 *(uint16_t *)data = readw(addr);
1368 break;
1369 case 4:
1370 *(uint32_t *)data = readl(addr);
1371 break;
1372 case 8:
1373 *(uint64_t *)data = readq(addr);
1374 break;
1375 default:
1376 ret = -1;
1377 break;
1378 }
1379 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1380
1381 if (mem_ptr)
1382 iounmap(mem_ptr);
1383 return ret;
1384 }
1385
1386 static int
1387 netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1388 void *data, int size)
1389 {
1390 unsigned long flags;
1391 void __iomem *addr, *mem_ptr = NULL;
1392 int ret = 0;
1393 u64 start;
1394 unsigned long mem_base;
1395 unsigned long mem_page;
1396
1397 write_lock_irqsave(&adapter->adapter_lock, flags);
1398
1399 /*
1400 * If attempting to access unknown address or straddle hw windows,
1401 * do not access.
1402 */
1403 start = adapter->pci_set_window(adapter, off);
1404 if ((start == -1UL) ||
1405 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1406 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1407 printk(KERN_ERR "%s out of bound pci memory access. "
1408 "offset is 0x%llx\n", netxen_nic_driver_name,
1409 (unsigned long long)off);
1410 return -1;
1411 }
1412
1413 addr = pci_base_offset(adapter, start);
1414 if (!addr) {
1415 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1416 mem_base = pci_resource_start(adapter->pdev, 0);
1417 mem_page = start & PAGE_MASK;
1418 /* Map two pages whenever user tries to access addresses in two
1419 * consecutive pages.
1420 */
1421 if (mem_page != ((start + size - 1) & PAGE_MASK))
1422 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1423 else
1424 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1425 if (mem_ptr == NULL)
1426 return -1;
1427 addr = mem_ptr;
1428 addr += start & (PAGE_SIZE - 1);
1429 write_lock_irqsave(&adapter->adapter_lock, flags);
1430 }
1431
1432 switch (size) {
1433 case 1:
1434 writeb(*(uint8_t *)data, addr);
1435 break;
1436 case 2:
1437 writew(*(uint16_t *)data, addr);
1438 break;
1439 case 4:
1440 writel(*(uint32_t *)data, addr);
1441 break;
1442 case 8:
1443 writeq(*(uint64_t *)data, addr);
1444 break;
1445 default:
1446 ret = -1;
1447 break;
1448 }
1449 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1450 if (mem_ptr)
1451 iounmap(mem_ptr);
1452 return ret;
1453 }
1454
1455 #define MAX_CTL_CHECK 1000
1456
1457 int
1458 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1459 u64 off, void *data, int size)
1460 {
1461 unsigned long flags;
1462 int i, j, ret = 0, loop, sz[2], off0;
1463 uint32_t temp;
1464 uint64_t off8, tmpw, word[2] = {0, 0};
1465 void __iomem *mem_crb;
1466
1467 /*
1468 * If not MN, go check for MS or invalid.
1469 */
1470 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1471 return netxen_nic_pci_mem_write_direct(adapter,
1472 off, data, size);
1473
1474 off8 = off & 0xfffffff8;
1475 off0 = off & 0x7;
1476 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1477 sz[1] = size - sz[0];
1478 loop = ((off0 + size - 1) >> 3) + 1;
1479 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1480
1481 if ((size != 8) || (off0 != 0)) {
1482 for (i = 0; i < loop; i++) {
1483 if (adapter->pci_mem_read(adapter,
1484 off8 + (i << 3), &word[i], 8))
1485 return -1;
1486 }
1487 }
1488
1489 switch (size) {
1490 case 1:
1491 tmpw = *((uint8_t *)data);
1492 break;
1493 case 2:
1494 tmpw = *((uint16_t *)data);
1495 break;
1496 case 4:
1497 tmpw = *((uint32_t *)data);
1498 break;
1499 case 8:
1500 default:
1501 tmpw = *((uint64_t *)data);
1502 break;
1503 }
1504 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1505 word[0] |= tmpw << (off0 * 8);
1506
1507 if (loop == 2) {
1508 word[1] &= ~(~0ULL << (sz[1] * 8));
1509 word[1] |= tmpw >> (sz[0] * 8);
1510 }
1511
1512 write_lock_irqsave(&adapter->adapter_lock, flags);
1513 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1514
1515 for (i = 0; i < loop; i++) {
1516 writel((uint32_t)(off8 + (i << 3)),
1517 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1518 writel(0,
1519 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1520 writel(word[i] & 0xffffffff,
1521 (mem_crb+MIU_TEST_AGT_WRDATA_LO));
1522 writel((word[i] >> 32) & 0xffffffff,
1523 (mem_crb+MIU_TEST_AGT_WRDATA_HI));
1524 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1525 (mem_crb+MIU_TEST_AGT_CTRL));
1526 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1527 (mem_crb+MIU_TEST_AGT_CTRL));
1528
1529 for (j = 0; j < MAX_CTL_CHECK; j++) {
1530 temp = readl(
1531 (mem_crb+MIU_TEST_AGT_CTRL));
1532 if ((temp & MIU_TA_CTL_BUSY) == 0)
1533 break;
1534 }
1535
1536 if (j >= MAX_CTL_CHECK) {
1537 if (printk_ratelimit())
1538 dev_err(&adapter->pdev->dev,
1539 "failed to write through agent\n");
1540 ret = -1;
1541 break;
1542 }
1543 }
1544
1545 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1546 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1547 return ret;
1548 }
1549
1550 int
1551 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1552 u64 off, void *data, int size)
1553 {
1554 unsigned long flags;
1555 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1556 uint32_t temp;
1557 uint64_t off8, val, word[2] = {0, 0};
1558 void __iomem *mem_crb;
1559
1560
1561 /*
1562 * If not MN, go check for MS or invalid.
1563 */
1564 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1565 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1566
1567 off8 = off & 0xfffffff8;
1568 off0[0] = off & 0x7;
1569 off0[1] = 0;
1570 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1571 sz[1] = size - sz[0];
1572 loop = ((off0[0] + size - 1) >> 3) + 1;
1573 mem_crb = pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1574
1575 write_lock_irqsave(&adapter->adapter_lock, flags);
1576 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1577
1578 for (i = 0; i < loop; i++) {
1579 writel((uint32_t)(off8 + (i << 3)),
1580 (mem_crb+MIU_TEST_AGT_ADDR_LO));
1581 writel(0,
1582 (mem_crb+MIU_TEST_AGT_ADDR_HI));
1583 writel(MIU_TA_CTL_ENABLE,
1584 (mem_crb+MIU_TEST_AGT_CTRL));
1585 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1586 (mem_crb+MIU_TEST_AGT_CTRL));
1587
1588 for (j = 0; j < MAX_CTL_CHECK; j++) {
1589 temp = readl(
1590 (mem_crb+MIU_TEST_AGT_CTRL));
1591 if ((temp & MIU_TA_CTL_BUSY) == 0)
1592 break;
1593 }
1594
1595 if (j >= MAX_CTL_CHECK) {
1596 if (printk_ratelimit())
1597 dev_err(&adapter->pdev->dev,
1598 "failed to read through agent\n");
1599 break;
1600 }
1601
1602 start = off0[i] >> 2;
1603 end = (off0[i] + sz[i] - 1) >> 2;
1604 for (k = start; k <= end; k++) {
1605 word[i] |= ((uint64_t) readl(
1606 (mem_crb +
1607 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1608 }
1609 }
1610
1611 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1612 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1613
1614 if (j >= MAX_CTL_CHECK)
1615 return -1;
1616
1617 if (sz[0] == 8) {
1618 val = word[0];
1619 } else {
1620 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1621 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1622 }
1623
1624 switch (size) {
1625 case 1:
1626 *(uint8_t *)data = val;
1627 break;
1628 case 2:
1629 *(uint16_t *)data = val;
1630 break;
1631 case 4:
1632 *(uint32_t *)data = val;
1633 break;
1634 case 8:
1635 *(uint64_t *)data = val;
1636 break;
1637 }
1638 return 0;
1639 }
1640
1641 int
1642 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1643 u64 off, void *data, int size)
1644 {
1645 int i, j, ret = 0, loop, sz[2], off0;
1646 uint32_t temp;
1647 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1648
1649 /*
1650 * If not MN, go check for MS or invalid.
1651 */
1652 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1653 mem_crb = NETXEN_CRB_QDR_NET;
1654 else {
1655 mem_crb = NETXEN_CRB_DDR_NET;
1656 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1657 return netxen_nic_pci_mem_write_direct(adapter,
1658 off, data, size);
1659 }
1660
1661 off8 = off & 0xfffffff8;
1662 off0 = off & 0x7;
1663 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1664 sz[1] = size - sz[0];
1665 loop = ((off0 + size - 1) >> 3) + 1;
1666
1667 if ((size != 8) || (off0 != 0)) {
1668 for (i = 0; i < loop; i++) {
1669 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1670 &word[i], 8))
1671 return -1;
1672 }
1673 }
1674
1675 switch (size) {
1676 case 1:
1677 tmpw = *((uint8_t *)data);
1678 break;
1679 case 2:
1680 tmpw = *((uint16_t *)data);
1681 break;
1682 case 4:
1683 tmpw = *((uint32_t *)data);
1684 break;
1685 case 8:
1686 default:
1687 tmpw = *((uint64_t *)data);
1688 break;
1689 }
1690
1691 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1692 word[0] |= tmpw << (off0 * 8);
1693
1694 if (loop == 2) {
1695 word[1] &= ~(~0ULL << (sz[1] * 8));
1696 word[1] |= tmpw >> (sz[0] * 8);
1697 }
1698
1699 /*
1700 * don't lock here - write_wx gets the lock if each time
1701 * write_lock_irqsave(&adapter->adapter_lock, flags);
1702 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1703 */
1704
1705 for (i = 0; i < loop; i++) {
1706 temp = off8 + (i << 3);
1707 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1708 temp = 0;
1709 NXWR32(adapter, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1710 temp = word[i] & 0xffffffff;
1711 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1712 temp = (word[i] >> 32) & 0xffffffff;
1713 NXWR32(adapter, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1714 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1715 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1716 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1717 NXWR32(adapter, mem_crb+MIU_TEST_AGT_CTRL, temp);
1718
1719 for (j = 0; j < MAX_CTL_CHECK; j++) {
1720 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1721 if ((temp & MIU_TA_CTL_BUSY) == 0)
1722 break;
1723 }
1724
1725 if (j >= MAX_CTL_CHECK) {
1726 if (printk_ratelimit())
1727 dev_err(&adapter->pdev->dev,
1728 "failed to write through agent\n");
1729 ret = -1;
1730 break;
1731 }
1732 }
1733
1734 /*
1735 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1736 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1737 */
1738 return ret;
1739 }
1740
1741 int
1742 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1743 u64 off, void *data, int size)
1744 {
1745 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1746 uint32_t temp;
1747 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1748
1749 /*
1750 * If not MN, go check for MS or invalid.
1751 */
1752
1753 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1754 mem_crb = NETXEN_CRB_QDR_NET;
1755 else {
1756 mem_crb = NETXEN_CRB_DDR_NET;
1757 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1758 return netxen_nic_pci_mem_read_direct(adapter,
1759 off, data, size);
1760 }
1761
1762 off8 = off & 0xfffffff8;
1763 off0[0] = off & 0x7;
1764 off0[1] = 0;
1765 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1766 sz[1] = size - sz[0];
1767 loop = ((off0[0] + size - 1) >> 3) + 1;
1768
1769 /*
1770 * don't lock here - write_wx gets the lock if each time
1771 * write_lock_irqsave(&adapter->adapter_lock, flags);
1772 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1773 */
1774
1775 for (i = 0; i < loop; i++) {
1776 temp = off8 + (i << 3);
1777 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1778 temp = 0;
1779 NXWR32(adapter, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1780 temp = MIU_TA_CTL_ENABLE;
1781 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1782 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1783 NXWR32(adapter, mem_crb + MIU_TEST_AGT_CTRL, temp);
1784
1785 for (j = 0; j < MAX_CTL_CHECK; j++) {
1786 temp = NXRD32(adapter, mem_crb + MIU_TEST_AGT_CTRL);
1787 if ((temp & MIU_TA_CTL_BUSY) == 0)
1788 break;
1789 }
1790
1791 if (j >= MAX_CTL_CHECK) {
1792 if (printk_ratelimit())
1793 dev_err(&adapter->pdev->dev,
1794 "failed to read through agent\n");
1795 break;
1796 }
1797
1798 start = off0[i] >> 2;
1799 end = (off0[i] + sz[i] - 1) >> 2;
1800 for (k = start; k <= end; k++) {
1801 temp = NXRD32(adapter,
1802 mem_crb + MIU_TEST_AGT_RDDATA(k));
1803 word[i] |= ((uint64_t)temp << (32 * k));
1804 }
1805 }
1806
1807 /*
1808 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1809 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1810 */
1811
1812 if (j >= MAX_CTL_CHECK)
1813 return -1;
1814
1815 if (sz[0] == 8) {
1816 val = word[0];
1817 } else {
1818 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1819 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1820 }
1821
1822 switch (size) {
1823 case 1:
1824 *(uint8_t *)data = val;
1825 break;
1826 case 2:
1827 *(uint16_t *)data = val;
1828 break;
1829 case 4:
1830 *(uint32_t *)data = val;
1831 break;
1832 case 8:
1833 *(uint64_t *)data = val;
1834 break;
1835 }
1836 return 0;
1837 }
1838
1839 /*
1840 * Note : only 32-bit writes!
1841 */
1842 int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1843 u64 off, u32 data)
1844 {
1845 NXWR32(adapter, off, data);
1846
1847 return 0;
1848 }
1849
1850 u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1851 {
1852 return NXRD32(adapter, off);
1853 }
1854
1855 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1856 {
1857 int offset, board_type, magic, header_version;
1858 struct pci_dev *pdev = adapter->pdev;
1859
1860 offset = NETXEN_BRDCFG_START +
1861 offsetof(struct netxen_board_info, magic);
1862 if (netxen_rom_fast_read(adapter, offset, &magic))
1863 return -EIO;
1864
1865 offset = NETXEN_BRDCFG_START +
1866 offsetof(struct netxen_board_info, header_version);
1867 if (netxen_rom_fast_read(adapter, offset, &header_version))
1868 return -EIO;
1869
1870 if (magic != NETXEN_BDINFO_MAGIC ||
1871 header_version != NETXEN_BDINFO_VERSION) {
1872 dev_err(&pdev->dev,
1873 "invalid board config, magic=%08x, version=%08x\n",
1874 magic, header_version);
1875 return -EIO;
1876 }
1877
1878 offset = NETXEN_BRDCFG_START +
1879 offsetof(struct netxen_board_info, board_type);
1880 if (netxen_rom_fast_read(adapter, offset, &board_type))
1881 return -EIO;
1882
1883 adapter->ahw.board_type = board_type;
1884
1885 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1886 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1887 if ((gpio & 0x8000) == 0)
1888 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1889 }
1890
1891 switch (board_type) {
1892 case NETXEN_BRDTYPE_P2_SB35_4G:
1893 adapter->ahw.port_type = NETXEN_NIC_GBE;
1894 break;
1895 case NETXEN_BRDTYPE_P2_SB31_10G:
1896 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1897 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1898 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1899 case NETXEN_BRDTYPE_P3_HMEZ:
1900 case NETXEN_BRDTYPE_P3_XG_LOM:
1901 case NETXEN_BRDTYPE_P3_10G_CX4:
1902 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1903 case NETXEN_BRDTYPE_P3_IMEZ:
1904 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1905 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1906 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1907 case NETXEN_BRDTYPE_P3_10G_XFP:
1908 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1909 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1910 break;
1911 case NETXEN_BRDTYPE_P1_BD:
1912 case NETXEN_BRDTYPE_P1_SB:
1913 case NETXEN_BRDTYPE_P1_SMAX:
1914 case NETXEN_BRDTYPE_P1_SOCK:
1915 case NETXEN_BRDTYPE_P3_REF_QG:
1916 case NETXEN_BRDTYPE_P3_4_GB:
1917 case NETXEN_BRDTYPE_P3_4_GB_MM:
1918 adapter->ahw.port_type = NETXEN_NIC_GBE;
1919 break;
1920 case NETXEN_BRDTYPE_P3_10G_TP:
1921 adapter->ahw.port_type = (adapter->portnum < 2) ?
1922 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1923 break;
1924 default:
1925 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1926 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1927 break;
1928 }
1929
1930 return 0;
1931 }
1932
1933 /* NIU access sections */
1934
1935 int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
1936 {
1937 new_mtu += MTU_FUDGE_FACTOR;
1938 NXWR32(adapter, NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
1939 new_mtu);
1940 return 0;
1941 }
1942
1943 int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1944 {
1945 new_mtu += MTU_FUDGE_FACTOR;
1946 if (adapter->physical_port == 0)
1947 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1948 else
1949 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1950 return 0;
1951 }
1952
1953 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1954 {
1955 __u32 status;
1956 __u32 autoneg;
1957 __u32 port_mode;
1958
1959 if (!netif_carrier_ok(adapter->netdev)) {
1960 adapter->link_speed = 0;
1961 adapter->link_duplex = -1;
1962 adapter->link_autoneg = AUTONEG_ENABLE;
1963 return;
1964 }
1965
1966 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
1967 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
1968 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1969 adapter->link_speed = SPEED_1000;
1970 adapter->link_duplex = DUPLEX_FULL;
1971 adapter->link_autoneg = AUTONEG_DISABLE;
1972 return;
1973 }
1974
1975 if (adapter->phy_read
1976 && adapter->phy_read(adapter,
1977 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1978 &status) == 0) {
1979 if (netxen_get_phy_link(status)) {
1980 switch (netxen_get_phy_speed(status)) {
1981 case 0:
1982 adapter->link_speed = SPEED_10;
1983 break;
1984 case 1:
1985 adapter->link_speed = SPEED_100;
1986 break;
1987 case 2:
1988 adapter->link_speed = SPEED_1000;
1989 break;
1990 default:
1991 adapter->link_speed = 0;
1992 break;
1993 }
1994 switch (netxen_get_phy_duplex(status)) {
1995 case 0:
1996 adapter->link_duplex = DUPLEX_HALF;
1997 break;
1998 case 1:
1999 adapter->link_duplex = DUPLEX_FULL;
2000 break;
2001 default:
2002 adapter->link_duplex = -1;
2003 break;
2004 }
2005 if (adapter->phy_read
2006 && adapter->phy_read(adapter,
2007 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
2008 &autoneg) != 0)
2009 adapter->link_autoneg = autoneg;
2010 } else
2011 goto link_down;
2012 } else {
2013 link_down:
2014 adapter->link_speed = 0;
2015 adapter->link_duplex = -1;
2016 }
2017 }
2018 }
2019
2020 void netxen_nic_get_firmware_info(struct netxen_adapter *adapter)
2021 {
2022 u32 fw_major, fw_minor, fw_build;
2023 char brd_name[NETXEN_MAX_SHORT_NAME];
2024 char serial_num[32];
2025 int i, addr, val;
2026 int *ptr32;
2027 struct pci_dev *pdev = adapter->pdev;
2028
2029 adapter->driver_mismatch = 0;
2030
2031 ptr32 = (int *)&serial_num;
2032 addr = NETXEN_USER_START +
2033 offsetof(struct netxen_new_user_info, serial_num);
2034 for (i = 0; i < 8; i++) {
2035 if (netxen_rom_fast_read(adapter, addr, &val) == -1) {
2036 dev_err(&pdev->dev, "error reading board info\n");
2037 adapter->driver_mismatch = 1;
2038 return;
2039 }
2040 ptr32[i] = cpu_to_le32(val);
2041 addr += sizeof(u32);
2042 }
2043
2044 fw_major = NXRD32(adapter, NETXEN_FW_VERSION_MAJOR);
2045 fw_minor = NXRD32(adapter, NETXEN_FW_VERSION_MINOR);
2046 fw_build = NXRD32(adapter, NETXEN_FW_VERSION_SUB);
2047
2048 adapter->fw_major = fw_major;
2049 adapter->fw_version = NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build);
2050
2051 if (adapter->portnum == 0) {
2052 get_brd_name_by_type(adapter->ahw.board_type, brd_name);
2053
2054 printk(KERN_INFO "NetXen %s Board S/N %s Chip rev 0x%x\n",
2055 brd_name, serial_num, adapter->ahw.revision_id);
2056 }
2057
2058 if (adapter->fw_version < NETXEN_VERSION_CODE(3, 4, 216)) {
2059 adapter->driver_mismatch = 1;
2060 dev_warn(&pdev->dev, "firmware version %d.%d.%d unsupported\n",
2061 fw_major, fw_minor, fw_build);
2062 return;
2063 }
2064
2065 dev_info(&pdev->dev, "firmware version %d.%d.%d\n",
2066 fw_major, fw_minor, fw_build);
2067
2068 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
2069 i = NXRD32(adapter, NETXEN_SRE_MISC);
2070 adapter->ahw.cut_through = (i & 0x8000) ? 1 : 0;
2071 dev_info(&pdev->dev, "firmware running in %s mode\n",
2072 adapter->ahw.cut_through ? "cut-through" : "legacy");
2073 }
2074
2075 if (adapter->fw_version >= NETXEN_VERSION_CODE(4, 0, 222))
2076 adapter->capabilities = NXRD32(adapter, CRB_FW_CAPABILITIES_1);
2077 }
2078
2079 int
2080 netxen_nic_wol_supported(struct netxen_adapter *adapter)
2081 {
2082 u32 wol_cfg;
2083
2084 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
2085 return 0;
2086
2087 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
2088 if (wol_cfg & (1UL << adapter->portnum)) {
2089 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
2090 if (wol_cfg & (1 << adapter->portnum))
2091 return 1;
2092 }
2093
2094 return 0;
2095 }
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