2 * OMAP2 Power Management Routines
4 * Copyright (C) 2005 Texas Instruments, Inc.
5 * Copyright (C) 2006-2008 Nokia Corporation
8 * Richard Woodruff <r-woodruff2@ti.com>
11 * Amit Kucheria <amit.kucheria@nokia.com>
12 * Igor Stoppa <igor.stoppa@nokia.com>
14 * Based on pm.c for omap1
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License version 2 as
18 * published by the Free Software Foundation.
21 #include <linux/suspend.h>
22 #include <linux/sched.h>
23 #include <linux/proc_fs.h>
24 #include <linux/interrupt.h>
25 #include <linux/sysfs.h>
26 #include <linux/module.h>
27 #include <linux/delay.h>
28 #include <linux/clk.h>
29 #include <linux/irq.h>
30 #include <linux/time.h>
31 #include <linux/gpio.h>
32 #include <linux/platform_data/gpio-omap.h>
34 #include <asm/fncpy.h>
36 #include <asm/mach/time.h>
37 #include <asm/mach/irq.h>
38 #include <asm/mach-types.h>
39 #include <asm/system_misc.h>
41 #include <plat-omap/dma-omap.h>
47 #include "prm-regbits-24xx.h"
49 #include "cm-regbits-24xx.h"
54 #include "powerdomain.h"
55 #include "clockdomain.h"
57 static void (*omap2_sram_idle
)(void);
58 static void (*omap2_sram_suspend
)(u32 dllctrl
, void __iomem
*sdrc_dlla_ctrl
,
59 void __iomem
*sdrc_power
);
61 static struct powerdomain
*mpu_pwrdm
, *core_pwrdm
;
62 static struct clockdomain
*dsp_clkdm
, *mpu_clkdm
, *wkup_clkdm
, *gfx_clkdm
;
64 static struct clk
*osc_ck
, *emul_ck
;
66 static int omap2_fclks_active(void)
70 f1
= omap2_cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
71 f2
= omap2_cm_read_mod_reg(CORE_MOD
, OMAP24XX_CM_FCLKEN2
);
73 return (f1
| f2
) ? 1 : 0;
76 static int omap2_enter_full_retention(void)
80 /* There is 1 reference hold for all children of the oscillator
81 * clock, the following will remove it. If no one else uses the
82 * oscillator itself it will be disabled if/when we enter retention
87 /* Clear old wake-up events */
88 /* REVISIT: These write to reserved bits? */
89 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
90 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
91 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD
, PM_WKST
);
94 * Set MPU powerdomain's next power state to RETENTION;
95 * preserve logic state during retention
97 pwrdm_set_logic_retst(mpu_pwrdm
, PWRDM_POWER_RET
);
98 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
100 /* Workaround to kill USB */
101 l
= omap_ctrl_readl(OMAP2_CONTROL_DEVCONF0
) | OMAP24XX_USBSTANDBYCTRL
;
102 omap_ctrl_writel(l
, OMAP2_CONTROL_DEVCONF0
);
104 omap2_gpio_prepare_for_idle(0);
106 /* One last check for pending IRQs to avoid extra latency due
107 * to sleeping unnecessarily. */
108 if (omap_irq_pending())
111 /* Jump to SRAM suspend code */
112 omap2_sram_suspend(sdrc_read_reg(SDRC_DLLA_CTRL
),
113 OMAP_SDRC_REGADDR(SDRC_DLLA_CTRL
),
114 OMAP_SDRC_REGADDR(SDRC_POWER
));
117 omap2_gpio_resume_after_idle();
121 /* clear CORE wake-up events */
122 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
123 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
125 /* wakeup domain events - bit 1: GPT1, bit5 GPIO */
126 omap2_prm_clear_mod_reg_bits(0x4 | 0x1, WKUP_MOD
, PM_WKST
);
128 /* MPU domain wake events */
129 l
= omap2_prm_read_mod_reg(OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
131 omap2_prm_write_mod_reg(0x01, OCP_MOD
,
132 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
134 omap2_prm_write_mod_reg(0x20, OCP_MOD
,
135 OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
137 /* Mask future PRCM-to-MPU interrupts */
138 omap2_prm_write_mod_reg(0x0, OCP_MOD
, OMAP2_PRCM_IRQSTATUS_MPU_OFFSET
);
143 static int omap2_i2c_active(void)
147 l
= omap2_cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
148 return l
& (OMAP2420_EN_I2C2_MASK
| OMAP2420_EN_I2C1_MASK
);
151 static int sti_console_enabled
;
153 static int omap2_allow_mpu_retention(void)
157 /* Check for MMC, UART2, UART1, McSPI2, McSPI1 and DSS1. */
158 l
= omap2_cm_read_mod_reg(CORE_MOD
, CM_FCLKEN1
);
159 if (l
& (OMAP2420_EN_MMC_MASK
| OMAP24XX_EN_UART2_MASK
|
160 OMAP24XX_EN_UART1_MASK
| OMAP24XX_EN_MCSPI2_MASK
|
161 OMAP24XX_EN_MCSPI1_MASK
| OMAP24XX_EN_DSS1_MASK
))
163 /* Check for UART3. */
164 l
= omap2_cm_read_mod_reg(CORE_MOD
, OMAP24XX_CM_FCLKEN2
);
165 if (l
& OMAP24XX_EN_UART3_MASK
)
167 if (sti_console_enabled
)
173 static void omap2_enter_mpu_retention(void)
175 /* Putting MPU into the WFI state while a transfer is active
176 * seems to cause the I2C block to timeout. Why? Good question. */
177 if (omap2_i2c_active())
180 /* The peripherals seem not to be able to wake up the MPU when
181 * it is in retention mode. */
182 if (omap2_allow_mpu_retention()) {
183 /* REVISIT: These write to reserved bits? */
184 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, PM_WKST1
);
185 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD
, OMAP24XX_PM_WKST2
);
186 omap2_prm_write_mod_reg(0xffffffff, WKUP_MOD
, PM_WKST
);
188 /* Try to enter MPU retention */
189 omap2_prm_write_mod_reg((0x01 << OMAP_POWERSTATE_SHIFT
) |
190 OMAP_LOGICRETSTATE_MASK
,
191 MPU_MOD
, OMAP2_PM_PWSTCTRL
);
193 /* Block MPU retention */
195 omap2_prm_write_mod_reg(OMAP_LOGICRETSTATE_MASK
, MPU_MOD
,
202 static int omap2_can_sleep(void)
204 if (omap2_fclks_active())
206 if (osc_ck
->usecount
> 1)
208 if (omap_dma_running())
214 static void omap2_pm_idle(void)
218 if (!omap2_can_sleep()) {
219 if (omap_irq_pending())
221 omap2_enter_mpu_retention();
225 if (omap_irq_pending())
228 omap2_enter_full_retention();
234 static void __init
prcm_setup_regs(void)
236 int i
, num_mem_banks
;
237 struct powerdomain
*pwrdm
;
241 * XXX This should be handled by hwmod code or PRCM init code
243 omap2_prm_write_mod_reg(OMAP24XX_AUTOIDLE_MASK
, OCP_MOD
,
244 OMAP2_PRCM_SYSCONFIG_OFFSET
);
247 * Set CORE powerdomain memory banks to retain their contents
250 num_mem_banks
= pwrdm_get_mem_bank_count(core_pwrdm
);
251 for (i
= 0; i
< num_mem_banks
; i
++)
252 pwrdm_set_mem_retst(core_pwrdm
, i
, PWRDM_POWER_RET
);
254 /* Set CORE powerdomain's next power state to RETENTION */
255 pwrdm_set_next_pwrst(core_pwrdm
, PWRDM_POWER_RET
);
258 * Set MPU powerdomain's next power state to RETENTION;
259 * preserve logic state during retention
261 pwrdm_set_logic_retst(mpu_pwrdm
, PWRDM_POWER_RET
);
262 pwrdm_set_next_pwrst(mpu_pwrdm
, PWRDM_POWER_RET
);
264 /* Force-power down DSP, GFX powerdomains */
266 pwrdm
= clkdm_get_pwrdm(dsp_clkdm
);
267 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
268 clkdm_sleep(dsp_clkdm
);
270 pwrdm
= clkdm_get_pwrdm(gfx_clkdm
);
271 pwrdm_set_next_pwrst(pwrdm
, PWRDM_POWER_OFF
);
272 clkdm_sleep(gfx_clkdm
);
274 /* Enable hardware-supervised idle for all clkdms */
275 clkdm_for_each(omap_pm_clkdms_setup
, NULL
);
276 clkdm_add_wkdep(mpu_clkdm
, wkup_clkdm
);
278 #ifdef CONFIG_SUSPEND
279 omap_pm_suspend
= omap2_enter_full_retention
;
282 /* REVISIT: Configure number of 32 kHz clock cycles for sys_clk
284 omap2_prm_write_mod_reg(15 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
285 OMAP2_PRCM_CLKSSETUP_OFFSET
);
287 /* Configure automatic voltage transition */
288 omap2_prm_write_mod_reg(2 << OMAP_SETUP_TIME_SHIFT
, OMAP24XX_GR_MOD
,
289 OMAP2_PRCM_VOLTSETUP_OFFSET
);
290 omap2_prm_write_mod_reg(OMAP24XX_AUTO_EXTVOLT_MASK
|
291 (0x1 << OMAP24XX_SETOFF_LEVEL_SHIFT
) |
292 OMAP24XX_MEMRETCTRL_MASK
|
293 (0x1 << OMAP24XX_SETRET_LEVEL_SHIFT
) |
294 (0x0 << OMAP24XX_VOLT_LEVEL_SHIFT
),
295 OMAP24XX_GR_MOD
, OMAP2_PRCM_VOLTCTRL_OFFSET
);
297 /* Enable wake-up events */
298 omap2_prm_write_mod_reg(OMAP24XX_EN_GPIOS_MASK
| OMAP24XX_EN_GPT1_MASK
,
302 int __init
omap2_pm_init(void)
306 printk(KERN_INFO
"Power Management for OMAP2 initializing\n");
307 l
= omap2_prm_read_mod_reg(OCP_MOD
, OMAP2_PRCM_REVISION_OFFSET
);
308 printk(KERN_INFO
"PRCM revision %d.%d\n", (l
>> 4) & 0x0f, l
& 0x0f);
310 /* Look up important powerdomains */
312 mpu_pwrdm
= pwrdm_lookup("mpu_pwrdm");
314 pr_err("PM: mpu_pwrdm not found\n");
316 core_pwrdm
= pwrdm_lookup("core_pwrdm");
318 pr_err("PM: core_pwrdm not found\n");
320 /* Look up important clockdomains */
322 mpu_clkdm
= clkdm_lookup("mpu_clkdm");
324 pr_err("PM: mpu_clkdm not found\n");
326 wkup_clkdm
= clkdm_lookup("wkup_clkdm");
328 pr_err("PM: wkup_clkdm not found\n");
330 dsp_clkdm
= clkdm_lookup("dsp_clkdm");
332 pr_err("PM: dsp_clkdm not found\n");
334 gfx_clkdm
= clkdm_lookup("gfx_clkdm");
336 pr_err("PM: gfx_clkdm not found\n");
339 osc_ck
= clk_get(NULL
, "osc_ck");
340 if (IS_ERR(osc_ck
)) {
341 printk(KERN_ERR
"could not get osc_ck\n");
345 if (cpu_is_omap242x()) {
346 emul_ck
= clk_get(NULL
, "emul_ck");
347 if (IS_ERR(emul_ck
)) {
348 printk(KERN_ERR
"could not get emul_ck\n");
357 * We copy the assembler sleep/wakeup routines to SRAM.
358 * These routines need to be in SRAM as that's the only
359 * memory the MPU can see when it wakes up.
361 omap2_sram_idle
= omap_sram_push(omap24xx_idle_loop_suspend
,
362 omap24xx_idle_loop_suspend_sz
);
364 omap2_sram_suspend
= omap_sram_push(omap24xx_cpu_suspend
,
365 omap24xx_cpu_suspend_sz
);
367 arm_pm_idle
= omap2_pm_idle
;