?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
KVM: MMU: Refactor mmu_alloc_roots function
[linux-2.6/btrfs-unstable.git] / arch / x86 / kvm / mmu.c
blob9cd5a717ede56a5c2785596022bcdb93e4185d50
1 /*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
10 * Copyright 2010 Red Hat, Inc. and/or its affilates.
11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21 #include "mmu.h"
22 #include "x86.h"
23 #include "kvm_cache_regs.h"
24
25 #include <linux/kvm_host.h>
26 #include <linux/types.h>
27 #include <linux/string.h>
28 #include <linux/mm.h>
29 #include <linux/highmem.h>
30 #include <linux/module.h>
31 #include <linux/swap.h>
32 #include <linux/hugetlb.h>
33 #include <linux/compiler.h>
34 #include <linux/srcu.h>
35 #include <linux/slab.h>
36 #include <linux/uaccess.h>
37
38 #include <asm/page.h>
39 #include <asm/cmpxchg.h>
40 #include <asm/io.h>
41 #include <asm/vmx.h>
42
43 /*
44 * When setting this variable to true it enables Two-Dimensional-Paging
45 * where the hardware walks 2 page tables:
46 * 1. the guest-virtual to guest-physical
47 * 2. while doing 1. it walks guest-physical to host-physical
48 * If the hardware supports that we don't need to do shadow paging.
49 */
50 bool tdp_enabled = false;
51
52 enum {
53 AUDIT_PRE_PAGE_FAULT,
54 AUDIT_POST_PAGE_FAULT,
55 AUDIT_PRE_PTE_WRITE,
56 AUDIT_POST_PTE_WRITE
57 };
58
59 char *audit_point_name[] = {
60 "pre page fault",
61 "post page fault",
62 "pre pte write",
63 "post pte write"
64 };
65
66 #undef MMU_DEBUG
67
68 #ifdef MMU_DEBUG
69
70 #define pgprintk(x...) do { if (dbg) printk(x); } while (0)
71 #define rmap_printk(x...) do { if (dbg) printk(x); } while (0)
72
73 #else
74
75 #define pgprintk(x...) do { } while (0)
76 #define rmap_printk(x...) do { } while (0)
77
78 #endif
79
80 #ifdef MMU_DEBUG
81 static int dbg = 0;
82 module_param(dbg, bool, 0644);
83 #endif
84
85 static int oos_shadow = 1;
86 module_param(oos_shadow, bool, 0644);
87
88 #ifndef MMU_DEBUG
89 #define ASSERT(x) do { } while (0)
90 #else
91 #define ASSERT(x) \
92 if (!(x)) { \
93 printk(KERN_WARNING "assertion failed %s:%d: %s\n", \
94 __FILE__, __LINE__, #x); \
95 }
96 #endif
97
98 #define PTE_PREFETCH_NUM 8
99
100 #define PT_FIRST_AVAIL_BITS_SHIFT 9
101 #define PT64_SECOND_AVAIL_BITS_SHIFT 52
102
103 #define PT64_LEVEL_BITS 9
104
105 #define PT64_LEVEL_SHIFT(level) \
106 (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS)
107
108 #define PT64_LEVEL_MASK(level) \
109 (((1ULL << PT64_LEVEL_BITS) - 1) << PT64_LEVEL_SHIFT(level))
110
111 #define PT64_INDEX(address, level)\
112 (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1))
113
114
115 #define PT32_LEVEL_BITS 10
116
117 #define PT32_LEVEL_SHIFT(level) \
118 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
119
120 #define PT32_LEVEL_MASK(level) \
121 (((1ULL << PT32_LEVEL_BITS) - 1) << PT32_LEVEL_SHIFT(level))
122 #define PT32_LVL_OFFSET_MASK(level) \
123 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
124 * PT32_LEVEL_BITS))) - 1))
125
126 #define PT32_INDEX(address, level)\
127 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
128
129
130 #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1))
131 #define PT64_DIR_BASE_ADDR_MASK \
132 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + PT64_LEVEL_BITS)) - 1))
133 #define PT64_LVL_ADDR_MASK(level) \
134 (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
135 * PT64_LEVEL_BITS))) - 1))
136 #define PT64_LVL_OFFSET_MASK(level) \
137 (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
138 * PT64_LEVEL_BITS))) - 1))
139
140 #define PT32_BASE_ADDR_MASK PAGE_MASK
141 #define PT32_DIR_BASE_ADDR_MASK \
142 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
143 #define PT32_LVL_ADDR_MASK(level) \
144 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
145 * PT32_LEVEL_BITS))) - 1))
146
147 #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | PT_USER_MASK \
148 | PT64_NX_MASK)
149
150 #define RMAP_EXT 4
151
152 #define ACC_EXEC_MASK 1
153 #define ACC_WRITE_MASK PT_WRITABLE_MASK
154 #define ACC_USER_MASK PT_USER_MASK
155 #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK)
156
157 #include <trace/events/kvm.h>
158
159 #define CREATE_TRACE_POINTS
160 #include "mmutrace.h"
161
162 #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT)
163
164 #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level)
165
166 struct kvm_rmap_desc {
167 u64 *sptes[RMAP_EXT];
168 struct kvm_rmap_desc *more;
169 };
170
171 struct kvm_shadow_walk_iterator {
172 u64 addr;
173 hpa_t shadow_addr;
174 int level;
175 u64 *sptep;
176 unsigned index;
177 };
178
179 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
180 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
181 shadow_walk_okay(&(_walker)); \
182 shadow_walk_next(&(_walker)))
183
184 typedef void (*mmu_parent_walk_fn) (struct kvm_mmu_page *sp, u64 *spte);
185
186 static struct kmem_cache *pte_chain_cache;
187 static struct kmem_cache *rmap_desc_cache;
188 static struct kmem_cache *mmu_page_header_cache;
189 static struct percpu_counter kvm_total_used_mmu_pages;
190
191 static u64 __read_mostly shadow_trap_nonpresent_pte;
192 static u64 __read_mostly shadow_notrap_nonpresent_pte;
193 static u64 __read_mostly shadow_base_present_pte;
194 static u64 __read_mostly shadow_nx_mask;
195 static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */
196 static u64 __read_mostly shadow_user_mask;
197 static u64 __read_mostly shadow_accessed_mask;
198 static u64 __read_mostly shadow_dirty_mask;
199
200 static inline u64 rsvd_bits(int s, int e)
201 {
202 return ((1ULL << (e - s + 1)) - 1) << s;
203 }
204
205 void kvm_mmu_set_nonpresent_ptes(u64 trap_pte, u64 notrap_pte)
206 {
207 shadow_trap_nonpresent_pte = trap_pte;
208 shadow_notrap_nonpresent_pte = notrap_pte;
209 }
210 EXPORT_SYMBOL_GPL(kvm_mmu_set_nonpresent_ptes);
211
212 void kvm_mmu_set_base_ptes(u64 base_pte)
213 {
214 shadow_base_present_pte = base_pte;
215 }
216 EXPORT_SYMBOL_GPL(kvm_mmu_set_base_ptes);
217
218 void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask,
219 u64 dirty_mask, u64 nx_mask, u64 x_mask)
220 {
221 shadow_user_mask = user_mask;
222 shadow_accessed_mask = accessed_mask;
223 shadow_dirty_mask = dirty_mask;
224 shadow_nx_mask = nx_mask;
225 shadow_x_mask = x_mask;
226 }
227 EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes);
228
229 static bool is_write_protection(struct kvm_vcpu *vcpu)
230 {
231 return kvm_read_cr0_bits(vcpu, X86_CR0_WP);
232 }
233
234 static int is_cpuid_PSE36(void)
235 {
236 return 1;
237 }
238
239 static int is_nx(struct kvm_vcpu *vcpu)
240 {
241 return vcpu->arch.efer & EFER_NX;
242 }
243
244 static int is_shadow_present_pte(u64 pte)
245 {
246 return pte != shadow_trap_nonpresent_pte
247 && pte != shadow_notrap_nonpresent_pte;
248 }
249
250 static int is_large_pte(u64 pte)
251 {
252 return pte & PT_PAGE_SIZE_MASK;
253 }
254
255 static int is_writable_pte(unsigned long pte)
256 {
257 return pte & PT_WRITABLE_MASK;
258 }
259
260 static int is_dirty_gpte(unsigned long pte)
261 {
262 return pte & PT_DIRTY_MASK;
263 }
264
265 static int is_rmap_spte(u64 pte)
266 {
267 return is_shadow_present_pte(pte);
268 }
269
270 static int is_last_spte(u64 pte, int level)
271 {
272 if (level == PT_PAGE_TABLE_LEVEL)
273 return 1;
274 if (is_large_pte(pte))
275 return 1;
276 return 0;
277 }
278
279 static pfn_t spte_to_pfn(u64 pte)
280 {
281 return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
282 }
283
284 static gfn_t pse36_gfn_delta(u32 gpte)
285 {
286 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
287
288 return (gpte & PT32_DIR_PSE36_MASK) << shift;
289 }
290
291 static void __set_spte(u64 *sptep, u64 spte)
292 {
293 set_64bit(sptep, spte);
294 }
295
296 static u64 __xchg_spte(u64 *sptep, u64 new_spte)
297 {
298 #ifdef CONFIG_X86_64
299 return xchg(sptep, new_spte);
300 #else
301 u64 old_spte;
302
303 do {
304 old_spte = *sptep;
305 } while (cmpxchg64(sptep, old_spte, new_spte) != old_spte);
306
307 return old_spte;
308 #endif
309 }
310
311 static bool spte_has_volatile_bits(u64 spte)
312 {
313 if (!shadow_accessed_mask)
314 return false;
315
316 if (!is_shadow_present_pte(spte))
317 return false;
318
319 if ((spte & shadow_accessed_mask) &&
320 (!is_writable_pte(spte) || (spte & shadow_dirty_mask)))
321 return false;
322
323 return true;
324 }
325
326 static bool spte_is_bit_cleared(u64 old_spte, u64 new_spte, u64 bit_mask)
327 {
328 return (old_spte & bit_mask) && !(new_spte & bit_mask);
329 }
330
331 static void update_spte(u64 *sptep, u64 new_spte)
332 {
333 u64 mask, old_spte = *sptep;
334
335 WARN_ON(!is_rmap_spte(new_spte));
336
337 new_spte |= old_spte & shadow_dirty_mask;
338
339 mask = shadow_accessed_mask;
340 if (is_writable_pte(old_spte))
341 mask |= shadow_dirty_mask;
342
343 if (!spte_has_volatile_bits(old_spte) || (new_spte & mask) == mask)
344 __set_spte(sptep, new_spte);
345 else
346 old_spte = __xchg_spte(sptep, new_spte);
347
348 if (!shadow_accessed_mask)
349 return;
350
351 if (spte_is_bit_cleared(old_spte, new_spte, shadow_accessed_mask))
352 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
353 if (spte_is_bit_cleared(old_spte, new_spte, shadow_dirty_mask))
354 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
355 }
356
357 static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache,
358 struct kmem_cache *base_cache, int min)
359 {
360 void *obj;
361
362 if (cache->nobjs >= min)
363 return 0;
364 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
365 obj = kmem_cache_zalloc(base_cache, GFP_KERNEL);
366 if (!obj)
367 return -ENOMEM;
368 cache->objects[cache->nobjs++] = obj;
369 }
370 return 0;
371 }
372
373 static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc,
374 struct kmem_cache *cache)
375 {
376 while (mc->nobjs)
377 kmem_cache_free(cache, mc->objects[--mc->nobjs]);
378 }
379
380 static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache,
381 int min)
382 {
383 struct page *page;
384
385 if (cache->nobjs >= min)
386 return 0;
387 while (cache->nobjs < ARRAY_SIZE(cache->objects)) {
388 page = alloc_page(GFP_KERNEL);
389 if (!page)
390 return -ENOMEM;
391 cache->objects[cache->nobjs++] = page_address(page);
392 }
393 return 0;
394 }
395
396 static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc)
397 {
398 while (mc->nobjs)
399 free_page((unsigned long)mc->objects[--mc->nobjs]);
400 }
401
402 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu)
403 {
404 int r;
405
406 r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_chain_cache,
407 pte_chain_cache, 4);
408 if (r)
409 goto out;
410 r = mmu_topup_memory_cache(&vcpu->arch.mmu_rmap_desc_cache,
411 rmap_desc_cache, 4 + PTE_PREFETCH_NUM);
412 if (r)
413 goto out;
414 r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8);
415 if (r)
416 goto out;
417 r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
418 mmu_page_header_cache, 4);
419 out:
420 return r;
421 }
422
423 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
424 {
425 mmu_free_memory_cache(&vcpu->arch.mmu_pte_chain_cache, pte_chain_cache);
426 mmu_free_memory_cache(&vcpu->arch.mmu_rmap_desc_cache, rmap_desc_cache);
427 mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache);
428 mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache,
429 mmu_page_header_cache);
430 }
431
432 static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc,
433 size_t size)
434 {
435 void *p;
436
437 BUG_ON(!mc->nobjs);
438 p = mc->objects[--mc->nobjs];
439 return p;
440 }
441
442 static struct kvm_pte_chain *mmu_alloc_pte_chain(struct kvm_vcpu *vcpu)
443 {
444 return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_chain_cache,
445 sizeof(struct kvm_pte_chain));
446 }
447
448 static void mmu_free_pte_chain(struct kvm_pte_chain *pc)
449 {
450 kmem_cache_free(pte_chain_cache, pc);
451 }
452
453 static struct kvm_rmap_desc *mmu_alloc_rmap_desc(struct kvm_vcpu *vcpu)
454 {
455 return mmu_memory_cache_alloc(&vcpu->arch.mmu_rmap_desc_cache,
456 sizeof(struct kvm_rmap_desc));
457 }
458
459 static void mmu_free_rmap_desc(struct kvm_rmap_desc *rd)
460 {
461 kmem_cache_free(rmap_desc_cache, rd);
462 }
463
464 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
465 {
466 if (!sp->role.direct)
467 return sp->gfns[index];
468
469 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
470 }
471
472 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
473 {
474 if (sp->role.direct)
475 BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index));
476 else
477 sp->gfns[index] = gfn;
478 }
479
480 /*
481 * Return the pointer to the largepage write count for a given
482 * gfn, handling slots that are not large page aligned.
483 */
484 static int *slot_largepage_idx(gfn_t gfn,
485 struct kvm_memory_slot *slot,
486 int level)
487 {
488 unsigned long idx;
489
490 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
491 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
492 return &slot->lpage_info[level - 2][idx].write_count;
493 }
494
495 static void account_shadowed(struct kvm *kvm, gfn_t gfn)
496 {
497 struct kvm_memory_slot *slot;
498 int *write_count;
499 int i;
500
501 slot = gfn_to_memslot(kvm, gfn);
502 for (i = PT_DIRECTORY_LEVEL;
503 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
504 write_count = slot_largepage_idx(gfn, slot, i);
505 *write_count += 1;
506 }
507 }
508
509 static void unaccount_shadowed(struct kvm *kvm, gfn_t gfn)
510 {
511 struct kvm_memory_slot *slot;
512 int *write_count;
513 int i;
514
515 slot = gfn_to_memslot(kvm, gfn);
516 for (i = PT_DIRECTORY_LEVEL;
517 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
518 write_count = slot_largepage_idx(gfn, slot, i);
519 *write_count -= 1;
520 WARN_ON(*write_count < 0);
521 }
522 }
523
524 static int has_wrprotected_page(struct kvm *kvm,
525 gfn_t gfn,
526 int level)
527 {
528 struct kvm_memory_slot *slot;
529 int *largepage_idx;
530
531 slot = gfn_to_memslot(kvm, gfn);
532 if (slot) {
533 largepage_idx = slot_largepage_idx(gfn, slot, level);
534 return *largepage_idx;
535 }
536
537 return 1;
538 }
539
540 static int host_mapping_level(struct kvm *kvm, gfn_t gfn)
541 {
542 unsigned long page_size;
543 int i, ret = 0;
544
545 page_size = kvm_host_page_size(kvm, gfn);
546
547 for (i = PT_PAGE_TABLE_LEVEL;
548 i < (PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES); ++i) {
549 if (page_size >= KVM_HPAGE_SIZE(i))
550 ret = i;
551 else
552 break;
553 }
554
555 return ret;
556 }
557
558 static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn)
559 {
560 struct kvm_memory_slot *slot;
561 int host_level, level, max_level;
562
563 slot = gfn_to_memslot(vcpu->kvm, large_gfn);
564 if (slot && slot->dirty_bitmap)
565 return PT_PAGE_TABLE_LEVEL;
566
567 host_level = host_mapping_level(vcpu->kvm, large_gfn);
568
569 if (host_level == PT_PAGE_TABLE_LEVEL)
570 return host_level;
571
572 max_level = kvm_x86_ops->get_lpage_level() < host_level ?
573 kvm_x86_ops->get_lpage_level() : host_level;
574
575 for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level)
576 if (has_wrprotected_page(vcpu->kvm, large_gfn, level))
577 break;
578
579 return level - 1;
580 }
581
582 /*
583 * Take gfn and return the reverse mapping to it.
584 */
585
586 static unsigned long *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, int level)
587 {
588 struct kvm_memory_slot *slot;
589 unsigned long idx;
590
591 slot = gfn_to_memslot(kvm, gfn);
592 if (likely(level == PT_PAGE_TABLE_LEVEL))
593 return &slot->rmap[gfn - slot->base_gfn];
594
595 idx = (gfn >> KVM_HPAGE_GFN_SHIFT(level)) -
596 (slot->base_gfn >> KVM_HPAGE_GFN_SHIFT(level));
597
598 return &slot->lpage_info[level - 2][idx].rmap_pde;
599 }
600
601 /*
602 * Reverse mapping data structures:
603 *
604 * If rmapp bit zero is zero, then rmapp point to the shadw page table entry
605 * that points to page_address(page).
606 *
607 * If rmapp bit zero is one, (then rmap & ~1) points to a struct kvm_rmap_desc
608 * containing more mappings.
609 *
610 * Returns the number of rmap entries before the spte was added or zero if
611 * the spte was not added.
612 *
613 */
614 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
615 {
616 struct kvm_mmu_page *sp;
617 struct kvm_rmap_desc *desc;
618 unsigned long *rmapp;
619 int i, count = 0;
620
621 if (!is_rmap_spte(*spte))
622 return count;
623 sp = page_header(__pa(spte));
624 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
625 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
626 if (!*rmapp) {
627 rmap_printk("rmap_add: %p %llx 0->1\n", spte, *spte);
628 *rmapp = (unsigned long)spte;
629 } else if (!(*rmapp & 1)) {
630 rmap_printk("rmap_add: %p %llx 1->many\n", spte, *spte);
631 desc = mmu_alloc_rmap_desc(vcpu);
632 desc->sptes[0] = (u64 *)*rmapp;
633 desc->sptes[1] = spte;
634 *rmapp = (unsigned long)desc | 1;
635 } else {
636 rmap_printk("rmap_add: %p %llx many->many\n", spte, *spte);
637 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
638 while (desc->sptes[RMAP_EXT-1] && desc->more) {
639 desc = desc->more;
640 count += RMAP_EXT;
641 }
642 if (desc->sptes[RMAP_EXT-1]) {
643 desc->more = mmu_alloc_rmap_desc(vcpu);
644 desc = desc->more;
645 }
646 for (i = 0; desc->sptes[i]; ++i)
647 ;
648 desc->sptes[i] = spte;
649 }
650 return count;
651 }
652
653 static void rmap_desc_remove_entry(unsigned long *rmapp,
654 struct kvm_rmap_desc *desc,
655 int i,
656 struct kvm_rmap_desc *prev_desc)
657 {
658 int j;
659
660 for (j = RMAP_EXT - 1; !desc->sptes[j] && j > i; --j)
661 ;
662 desc->sptes[i] = desc->sptes[j];
663 desc->sptes[j] = NULL;
664 if (j != 0)
665 return;
666 if (!prev_desc && !desc->more)
667 *rmapp = (unsigned long)desc->sptes[0];
668 else
669 if (prev_desc)
670 prev_desc->more = desc->more;
671 else
672 *rmapp = (unsigned long)desc->more | 1;
673 mmu_free_rmap_desc(desc);
674 }
675
676 static void rmap_remove(struct kvm *kvm, u64 *spte)
677 {
678 struct kvm_rmap_desc *desc;
679 struct kvm_rmap_desc *prev_desc;
680 struct kvm_mmu_page *sp;
681 gfn_t gfn;
682 unsigned long *rmapp;
683 int i;
684
685 sp = page_header(__pa(spte));
686 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
687 rmapp = gfn_to_rmap(kvm, gfn, sp->role.level);
688 if (!*rmapp) {
689 printk(KERN_ERR "rmap_remove: %p 0->BUG\n", spte);
690 BUG();
691 } else if (!(*rmapp & 1)) {
692 rmap_printk("rmap_remove: %p 1->0\n", spte);
693 if ((u64 *)*rmapp != spte) {
694 printk(KERN_ERR "rmap_remove: %p 1->BUG\n", spte);
695 BUG();
696 }
697 *rmapp = 0;
698 } else {
699 rmap_printk("rmap_remove: %p many->many\n", spte);
700 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
701 prev_desc = NULL;
702 while (desc) {
703 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i)
704 if (desc->sptes[i] == spte) {
705 rmap_desc_remove_entry(rmapp,
706 desc, i,
707 prev_desc);
708 return;
709 }
710 prev_desc = desc;
711 desc = desc->more;
712 }
713 pr_err("rmap_remove: %p many->many\n", spte);
714 BUG();
715 }
716 }
717
718 static void set_spte_track_bits(u64 *sptep, u64 new_spte)
719 {
720 pfn_t pfn;
721 u64 old_spte = *sptep;
722
723 if (!spte_has_volatile_bits(old_spte))
724 __set_spte(sptep, new_spte);
725 else
726 old_spte = __xchg_spte(sptep, new_spte);
727
728 if (!is_rmap_spte(old_spte))
729 return;
730
731 pfn = spte_to_pfn(old_spte);
732 if (!shadow_accessed_mask || old_spte & shadow_accessed_mask)
733 kvm_set_pfn_accessed(pfn);
734 if (!shadow_dirty_mask || (old_spte & shadow_dirty_mask))
735 kvm_set_pfn_dirty(pfn);
736 }
737
738 static void drop_spte(struct kvm *kvm, u64 *sptep, u64 new_spte)
739 {
740 set_spte_track_bits(sptep, new_spte);
741 rmap_remove(kvm, sptep);
742 }
743
744 static u64 *rmap_next(struct kvm *kvm, unsigned long *rmapp, u64 *spte)
745 {
746 struct kvm_rmap_desc *desc;
747 u64 *prev_spte;
748 int i;
749
750 if (!*rmapp)
751 return NULL;
752 else if (!(*rmapp & 1)) {
753 if (!spte)
754 return (u64 *)*rmapp;
755 return NULL;
756 }
757 desc = (struct kvm_rmap_desc *)(*rmapp & ~1ul);
758 prev_spte = NULL;
759 while (desc) {
760 for (i = 0; i < RMAP_EXT && desc->sptes[i]; ++i) {
761 if (prev_spte == spte)
762 return desc->sptes[i];
763 prev_spte = desc->sptes[i];
764 }
765 desc = desc->more;
766 }
767 return NULL;
768 }
769
770 static int rmap_write_protect(struct kvm *kvm, u64 gfn)
771 {
772 unsigned long *rmapp;
773 u64 *spte;
774 int i, write_protected = 0;
775
776 rmapp = gfn_to_rmap(kvm, gfn, PT_PAGE_TABLE_LEVEL);
777
778 spte = rmap_next(kvm, rmapp, NULL);
779 while (spte) {
780 BUG_ON(!spte);
781 BUG_ON(!(*spte & PT_PRESENT_MASK));
782 rmap_printk("rmap_write_protect: spte %p %llx\n", spte, *spte);
783 if (is_writable_pte(*spte)) {
784 update_spte(spte, *spte & ~PT_WRITABLE_MASK);
785 write_protected = 1;
786 }
787 spte = rmap_next(kvm, rmapp, spte);
788 }
789
790 /* check for huge page mappings */
791 for (i = PT_DIRECTORY_LEVEL;
792 i < PT_PAGE_TABLE_LEVEL + KVM_NR_PAGE_SIZES; ++i) {
793 rmapp = gfn_to_rmap(kvm, gfn, i);
794 spte = rmap_next(kvm, rmapp, NULL);
795 while (spte) {
796 BUG_ON(!spte);
797 BUG_ON(!(*spte & PT_PRESENT_MASK));
798 BUG_ON((*spte & (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK)) != (PT_PAGE_SIZE_MASK|PT_PRESENT_MASK));
799 pgprintk("rmap_write_protect(large): spte %p %llx %lld\n", spte, *spte, gfn);
800 if (is_writable_pte(*spte)) {
801 drop_spte(kvm, spte,
802 shadow_trap_nonpresent_pte);
803 --kvm->stat.lpages;
804 spte = NULL;
805 write_protected = 1;
806 }
807 spte = rmap_next(kvm, rmapp, spte);
808 }
809 }
810
811 return write_protected;
812 }
813
814 static int kvm_unmap_rmapp(struct kvm *kvm, unsigned long *rmapp,
815 unsigned long data)
816 {
817 u64 *spte;
818 int need_tlb_flush = 0;
819
820 while ((spte = rmap_next(kvm, rmapp, NULL))) {
821 BUG_ON(!(*spte & PT_PRESENT_MASK));
822 rmap_printk("kvm_rmap_unmap_hva: spte %p %llx\n", spte, *spte);
823 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
824 need_tlb_flush = 1;
825 }
826 return need_tlb_flush;
827 }
828
829 static int kvm_set_pte_rmapp(struct kvm *kvm, unsigned long *rmapp,
830 unsigned long data)
831 {
832 int need_flush = 0;
833 u64 *spte, new_spte;
834 pte_t *ptep = (pte_t *)data;
835 pfn_t new_pfn;
836
837 WARN_ON(pte_huge(*ptep));
838 new_pfn = pte_pfn(*ptep);
839 spte = rmap_next(kvm, rmapp, NULL);
840 while (spte) {
841 BUG_ON(!is_shadow_present_pte(*spte));
842 rmap_printk("kvm_set_pte_rmapp: spte %p %llx\n", spte, *spte);
843 need_flush = 1;
844 if (pte_write(*ptep)) {
845 drop_spte(kvm, spte, shadow_trap_nonpresent_pte);
846 spte = rmap_next(kvm, rmapp, NULL);
847 } else {
848 new_spte = *spte &~ (PT64_BASE_ADDR_MASK);
849 new_spte |= (u64)new_pfn << PAGE_SHIFT;
850
851 new_spte &= ~PT_WRITABLE_MASK;
852 new_spte &= ~SPTE_HOST_WRITEABLE;
853 new_spte &= ~shadow_accessed_mask;
854 set_spte_track_bits(spte, new_spte);
855 spte = rmap_next(kvm, rmapp, spte);
856 }
857 }
858 if (need_flush)
859 kvm_flush_remote_tlbs(kvm);
860
861 return 0;
862 }
863
864 static int kvm_handle_hva(struct kvm *kvm, unsigned long hva,
865 unsigned long data,
866 int (*handler)(struct kvm *kvm, unsigned long *rmapp,
867 unsigned long data))
868 {
869 int i, j;
870 int ret;
871 int retval = 0;
872 struct kvm_memslots *slots;
873
874 slots = kvm_memslots(kvm);
875
876 for (i = 0; i < slots->nmemslots; i++) {
877 struct kvm_memory_slot *memslot = &slots->memslots[i];
878 unsigned long start = memslot->userspace_addr;
879 unsigned long end;
880
881 end = start + (memslot->npages << PAGE_SHIFT);
882 if (hva >= start && hva < end) {
883 gfn_t gfn_offset = (hva - start) >> PAGE_SHIFT;
884
885 ret = handler(kvm, &memslot->rmap[gfn_offset], data);
886
887 for (j = 0; j < KVM_NR_PAGE_SIZES - 1; ++j) {
888 unsigned long idx;
889 int sh;
890
891 sh = KVM_HPAGE_GFN_SHIFT(PT_DIRECTORY_LEVEL+j);
892 idx = ((memslot->base_gfn+gfn_offset) >> sh) -
893 (memslot->base_gfn >> sh);
894 ret |= handler(kvm,
895 &memslot->lpage_info[j][idx].rmap_pde,
896 data);
897 }
898 trace_kvm_age_page(hva, memslot, ret);
899 retval |= ret;
900 }
901 }
902
903 return retval;
904 }
905
906 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva)
907 {
908 return kvm_handle_hva(kvm, hva, 0, kvm_unmap_rmapp);
909 }
910
911 void kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte)
912 {
913 kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp);
914 }
915
916 static int kvm_age_rmapp(struct kvm *kvm, unsigned long *rmapp,
917 unsigned long data)
918 {
919 u64 *spte;
920 int young = 0;
921
922 /*
923 * Emulate the accessed bit for EPT, by checking if this page has
924 * an EPT mapping, and clearing it if it does. On the next access,
925 * a new EPT mapping will be established.
926 * This has some overhead, but not as much as the cost of swapping
927 * out actively used pages or breaking up actively used hugepages.
928 */
929 if (!shadow_accessed_mask)
930 return kvm_unmap_rmapp(kvm, rmapp, data);
931
932 spte = rmap_next(kvm, rmapp, NULL);
933 while (spte) {
934 int _young;
935 u64 _spte = *spte;
936 BUG_ON(!(_spte & PT_PRESENT_MASK));
937 _young = _spte & PT_ACCESSED_MASK;
938 if (_young) {
939 young = 1;
940 clear_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
941 }
942 spte = rmap_next(kvm, rmapp, spte);
943 }
944 return young;
945 }
946
947 #define RMAP_RECYCLE_THRESHOLD 1000
948
949 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
950 {
951 unsigned long *rmapp;
952 struct kvm_mmu_page *sp;
953
954 sp = page_header(__pa(spte));
955
956 rmapp = gfn_to_rmap(vcpu->kvm, gfn, sp->role.level);
957
958 kvm_unmap_rmapp(vcpu->kvm, rmapp, 0);
959 kvm_flush_remote_tlbs(vcpu->kvm);
960 }
961
962 int kvm_age_hva(struct kvm *kvm, unsigned long hva)
963 {
964 return kvm_handle_hva(kvm, hva, 0, kvm_age_rmapp);
965 }
966
967 #ifdef MMU_DEBUG
968 static int is_empty_shadow_page(u64 *spt)
969 {
970 u64 *pos;
971 u64 *end;
972
973 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
974 if (is_shadow_present_pte(*pos)) {
975 printk(KERN_ERR "%s: %p %llx\n", __func__,
976 pos, *pos);
977 return 0;
978 }
979 return 1;
980 }
981 #endif
982
983 /*
984 * This value is the sum of all of the kvm instances's
985 * kvm->arch.n_used_mmu_pages values. We need a global,
986 * aggregate version in order to make the slab shrinker
987 * faster
988 */
989 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr)
990 {
991 kvm->arch.n_used_mmu_pages += nr;
992 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
993 }
994
995 static void kvm_mmu_free_page(struct kvm *kvm, struct kvm_mmu_page *sp)
996 {
997 ASSERT(is_empty_shadow_page(sp->spt));
998 hlist_del(&sp->hash_link);
999 list_del(&sp->link);
1000 __free_page(virt_to_page(sp->spt));
1001 if (!sp->role.direct)
1002 __free_page(virt_to_page(sp->gfns));
1003 kmem_cache_free(mmu_page_header_cache, sp);
1004 kvm_mod_used_mmu_pages(kvm, -1);
1005 }
1006
1007 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1008 {
1009 return gfn & ((1 << KVM_MMU_HASH_SHIFT) - 1);
1010 }
1011
1012 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu,
1013 u64 *parent_pte, int direct)
1014 {
1015 struct kvm_mmu_page *sp;
1016
1017 sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache, sizeof *sp);
1018 sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache, PAGE_SIZE);
1019 if (!direct)
1020 sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache,
1021 PAGE_SIZE);
1022 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1023 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1024 bitmap_zero(sp->slot_bitmap, KVM_MEMORY_SLOTS + KVM_PRIVATE_MEM_SLOTS);
1025 sp->multimapped = 0;
1026 sp->parent_pte = parent_pte;
1027 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1028 return sp;
1029 }
1030
1031 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1032 struct kvm_mmu_page *sp, u64 *parent_pte)
1033 {
1034 struct kvm_pte_chain *pte_chain;
1035 struct hlist_node *node;
1036 int i;
1037
1038 if (!parent_pte)
1039 return;
1040 if (!sp->multimapped) {
1041 u64 *old = sp->parent_pte;
1042
1043 if (!old) {
1044 sp->parent_pte = parent_pte;
1045 return;
1046 }
1047 sp->multimapped = 1;
1048 pte_chain = mmu_alloc_pte_chain(vcpu);
1049 INIT_HLIST_HEAD(&sp->parent_ptes);
1050 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
1051 pte_chain->parent_ptes[0] = old;
1052 }
1053 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link) {
1054 if (pte_chain->parent_ptes[NR_PTE_CHAIN_ENTRIES-1])
1055 continue;
1056 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i)
1057 if (!pte_chain->parent_ptes[i]) {
1058 pte_chain->parent_ptes[i] = parent_pte;
1059 return;
1060 }
1061 }
1062 pte_chain = mmu_alloc_pte_chain(vcpu);
1063 BUG_ON(!pte_chain);
1064 hlist_add_head(&pte_chain->link, &sp->parent_ptes);
1065 pte_chain->parent_ptes[0] = parent_pte;
1066 }
1067
1068 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1069 u64 *parent_pte)
1070 {
1071 struct kvm_pte_chain *pte_chain;
1072 struct hlist_node *node;
1073 int i;
1074
1075 if (!sp->multimapped) {
1076 BUG_ON(sp->parent_pte != parent_pte);
1077 sp->parent_pte = NULL;
1078 return;
1079 }
1080 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1081 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1082 if (!pte_chain->parent_ptes[i])
1083 break;
1084 if (pte_chain->parent_ptes[i] != parent_pte)
1085 continue;
1086 while (i + 1 < NR_PTE_CHAIN_ENTRIES
1087 && pte_chain->parent_ptes[i + 1]) {
1088 pte_chain->parent_ptes[i]
1089 = pte_chain->parent_ptes[i + 1];
1090 ++i;
1091 }
1092 pte_chain->parent_ptes[i] = NULL;
1093 if (i == 0) {
1094 hlist_del(&pte_chain->link);
1095 mmu_free_pte_chain(pte_chain);
1096 if (hlist_empty(&sp->parent_ptes)) {
1097 sp->multimapped = 0;
1098 sp->parent_pte = NULL;
1099 }
1100 }
1101 return;
1102 }
1103 BUG();
1104 }
1105
1106 static void mmu_parent_walk(struct kvm_mmu_page *sp, mmu_parent_walk_fn fn)
1107 {
1108 struct kvm_pte_chain *pte_chain;
1109 struct hlist_node *node;
1110 struct kvm_mmu_page *parent_sp;
1111 int i;
1112
1113 if (!sp->multimapped && sp->parent_pte) {
1114 parent_sp = page_header(__pa(sp->parent_pte));
1115 fn(parent_sp, sp->parent_pte);
1116 return;
1117 }
1118
1119 hlist_for_each_entry(pte_chain, node, &sp->parent_ptes, link)
1120 for (i = 0; i < NR_PTE_CHAIN_ENTRIES; ++i) {
1121 u64 *spte = pte_chain->parent_ptes[i];
1122
1123 if (!spte)
1124 break;
1125 parent_sp = page_header(__pa(spte));
1126 fn(parent_sp, spte);
1127 }
1128 }
1129
1130 static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte);
1131 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1132 {
1133 mmu_parent_walk(sp, mark_unsync);
1134 }
1135
1136 static void mark_unsync(struct kvm_mmu_page *sp, u64 *spte)
1137 {
1138 unsigned int index;
1139
1140 index = spte - sp->spt;
1141 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1142 return;
1143 if (sp->unsync_children++)
1144 return;
1145 kvm_mmu_mark_parents_unsync(sp);
1146 }
1147
1148 static void nonpaging_prefetch_page(struct kvm_vcpu *vcpu,
1149 struct kvm_mmu_page *sp)
1150 {
1151 int i;
1152
1153 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
1154 sp->spt[i] = shadow_trap_nonpresent_pte;
1155 }
1156
1157 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1158 struct kvm_mmu_page *sp, bool clear_unsync)
1159 {
1160 return 1;
1161 }
1162
1163 static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
1164 {
1165 }
1166
1167 #define KVM_PAGE_ARRAY_NR 16
1168
1169 struct kvm_mmu_pages {
1170 struct mmu_page_and_offset {
1171 struct kvm_mmu_page *sp;
1172 unsigned int idx;
1173 } page[KVM_PAGE_ARRAY_NR];
1174 unsigned int nr;
1175 };
1176
1177 #define for_each_unsync_children(bitmap, idx) \
1178 for (idx = find_first_bit(bitmap, 512); \
1179 idx < 512; \
1180 idx = find_next_bit(bitmap, 512, idx+1))
1181
1182 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1183 int idx)
1184 {
1185 int i;
1186
1187 if (sp->unsync)
1188 for (i=0; i < pvec->nr; i++)
1189 if (pvec->page[i].sp == sp)
1190 return 0;
1191
1192 pvec->page[pvec->nr].sp = sp;
1193 pvec->page[pvec->nr].idx = idx;
1194 pvec->nr++;
1195 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1196 }
1197
1198 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1199 struct kvm_mmu_pages *pvec)
1200 {
1201 int i, ret, nr_unsync_leaf = 0;
1202
1203 for_each_unsync_children(sp->unsync_child_bitmap, i) {
1204 struct kvm_mmu_page *child;
1205 u64 ent = sp->spt[i];
1206
1207 if (!is_shadow_present_pte(ent) || is_large_pte(ent))
1208 goto clear_child_bitmap;
1209
1210 child = page_header(ent & PT64_BASE_ADDR_MASK);
1211
1212 if (child->unsync_children) {
1213 if (mmu_pages_add(pvec, child, i))
1214 return -ENOSPC;
1215
1216 ret = __mmu_unsync_walk(child, pvec);
1217 if (!ret)
1218 goto clear_child_bitmap;
1219 else if (ret > 0)
1220 nr_unsync_leaf += ret;
1221 else
1222 return ret;
1223 } else if (child->unsync) {
1224 nr_unsync_leaf++;
1225 if (mmu_pages_add(pvec, child, i))
1226 return -ENOSPC;
1227 } else
1228 goto clear_child_bitmap;
1229
1230 continue;
1231
1232 clear_child_bitmap:
1233 __clear_bit(i, sp->unsync_child_bitmap);
1234 sp->unsync_children--;
1235 WARN_ON((int)sp->unsync_children < 0);
1236 }
1237
1238
1239 return nr_unsync_leaf;
1240 }
1241
1242 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1243 struct kvm_mmu_pages *pvec)
1244 {
1245 if (!sp->unsync_children)
1246 return 0;
1247
1248 mmu_pages_add(pvec, sp, 0);
1249 return __mmu_unsync_walk(sp, pvec);
1250 }
1251
1252 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1253 {
1254 WARN_ON(!sp->unsync);
1255 trace_kvm_mmu_sync_page(sp);
1256 sp->unsync = 0;
1257 --kvm->stat.mmu_unsync;
1258 }
1259
1260 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1261 struct list_head *invalid_list);
1262 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1263 struct list_head *invalid_list);
1264
1265 #define for_each_gfn_sp(kvm, sp, gfn, pos) \
1266 hlist_for_each_entry(sp, pos, \
1267 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1268 if ((sp)->gfn != (gfn)) {} else
1269
1270 #define for_each_gfn_indirect_valid_sp(kvm, sp, gfn, pos) \
1271 hlist_for_each_entry(sp, pos, \
1272 &(kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)], hash_link) \
1273 if ((sp)->gfn != (gfn) || (sp)->role.direct || \
1274 (sp)->role.invalid) {} else
1275
1276 /* @sp->gfn should be write-protected at the call site */
1277 static int __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1278 struct list_head *invalid_list, bool clear_unsync)
1279 {
1280 if (sp->role.cr4_pae != !!is_pae(vcpu)) {
1281 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1282 return 1;
1283 }
1284
1285 if (clear_unsync)
1286 kvm_unlink_unsync_page(vcpu->kvm, sp);
1287
1288 if (vcpu->arch.mmu.sync_page(vcpu, sp, clear_unsync)) {
1289 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1290 return 1;
1291 }
1292
1293 kvm_mmu_flush_tlb(vcpu);
1294 return 0;
1295 }
1296
1297 static int kvm_sync_page_transient(struct kvm_vcpu *vcpu,
1298 struct kvm_mmu_page *sp)
1299 {
1300 LIST_HEAD(invalid_list);
1301 int ret;
1302
1303 ret = __kvm_sync_page(vcpu, sp, &invalid_list, false);
1304 if (ret)
1305 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1306
1307 return ret;
1308 }
1309
1310 static int kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1311 struct list_head *invalid_list)
1312 {
1313 return __kvm_sync_page(vcpu, sp, invalid_list, true);
1314 }
1315
1316 /* @gfn should be write-protected at the call site */
1317 static void kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1318 {
1319 struct kvm_mmu_page *s;
1320 struct hlist_node *node;
1321 LIST_HEAD(invalid_list);
1322 bool flush = false;
1323
1324 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1325 if (!s->unsync)
1326 continue;
1327
1328 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1329 if ((s->role.cr4_pae != !!is_pae(vcpu)) ||
1330 (vcpu->arch.mmu.sync_page(vcpu, s, true))) {
1331 kvm_mmu_prepare_zap_page(vcpu->kvm, s, &invalid_list);
1332 continue;
1333 }
1334 kvm_unlink_unsync_page(vcpu->kvm, s);
1335 flush = true;
1336 }
1337
1338 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1339 if (flush)
1340 kvm_mmu_flush_tlb(vcpu);
1341 }
1342
1343 struct mmu_page_path {
1344 struct kvm_mmu_page *parent[PT64_ROOT_LEVEL-1];
1345 unsigned int idx[PT64_ROOT_LEVEL-1];
1346 };
1347
1348 #define for_each_sp(pvec, sp, parents, i) \
1349 for (i = mmu_pages_next(&pvec, &parents, -1), \
1350 sp = pvec.page[i].sp; \
1351 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1352 i = mmu_pages_next(&pvec, &parents, i))
1353
1354 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1355 struct mmu_page_path *parents,
1356 int i)
1357 {
1358 int n;
1359
1360 for (n = i+1; n < pvec->nr; n++) {
1361 struct kvm_mmu_page *sp = pvec->page[n].sp;
1362
1363 if (sp->role.level == PT_PAGE_TABLE_LEVEL) {
1364 parents->idx[0] = pvec->page[n].idx;
1365 return n;
1366 }
1367
1368 parents->parent[sp->role.level-2] = sp;
1369 parents->idx[sp->role.level-1] = pvec->page[n].idx;
1370 }
1371
1372 return n;
1373 }
1374
1375 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1376 {
1377 struct kvm_mmu_page *sp;
1378 unsigned int level = 0;
1379
1380 do {
1381 unsigned int idx = parents->idx[level];
1382
1383 sp = parents->parent[level];
1384 if (!sp)
1385 return;
1386
1387 --sp->unsync_children;
1388 WARN_ON((int)sp->unsync_children < 0);
1389 __clear_bit(idx, sp->unsync_child_bitmap);
1390 level++;
1391 } while (level < PT64_ROOT_LEVEL-1 && !sp->unsync_children);
1392 }
1393
1394 static void kvm_mmu_pages_init(struct kvm_mmu_page *parent,
1395 struct mmu_page_path *parents,
1396 struct kvm_mmu_pages *pvec)
1397 {
1398 parents->parent[parent->role.level-1] = NULL;
1399 pvec->nr = 0;
1400 }
1401
1402 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1403 struct kvm_mmu_page *parent)
1404 {
1405 int i;
1406 struct kvm_mmu_page *sp;
1407 struct mmu_page_path parents;
1408 struct kvm_mmu_pages pages;
1409 LIST_HEAD(invalid_list);
1410
1411 kvm_mmu_pages_init(parent, &parents, &pages);
1412 while (mmu_unsync_walk(parent, &pages)) {
1413 int protected = 0;
1414
1415 for_each_sp(pages, sp, parents, i)
1416 protected |= rmap_write_protect(vcpu->kvm, sp->gfn);
1417
1418 if (protected)
1419 kvm_flush_remote_tlbs(vcpu->kvm);
1420
1421 for_each_sp(pages, sp, parents, i) {
1422 kvm_sync_page(vcpu, sp, &invalid_list);
1423 mmu_pages_clear_parents(&parents);
1424 }
1425 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
1426 cond_resched_lock(&vcpu->kvm->mmu_lock);
1427 kvm_mmu_pages_init(parent, &parents, &pages);
1428 }
1429 }
1430
1431 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1432 gfn_t gfn,
1433 gva_t gaddr,
1434 unsigned level,
1435 int direct,
1436 unsigned access,
1437 u64 *parent_pte)
1438 {
1439 union kvm_mmu_page_role role;
1440 unsigned quadrant;
1441 struct kvm_mmu_page *sp;
1442 struct hlist_node *node;
1443 bool need_sync = false;
1444
1445 role = vcpu->arch.mmu.base_role;
1446 role.level = level;
1447 role.direct = direct;
1448 if (role.direct)
1449 role.cr4_pae = 0;
1450 role.access = access;
1451 if (!vcpu->arch.mmu.direct_map
1452 && vcpu->arch.mmu.root_level <= PT32_ROOT_LEVEL) {
1453 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
1454 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
1455 role.quadrant = quadrant;
1456 }
1457 for_each_gfn_sp(vcpu->kvm, sp, gfn, node) {
1458 if (!need_sync && sp->unsync)
1459 need_sync = true;
1460
1461 if (sp->role.word != role.word)
1462 continue;
1463
1464 if (sp->unsync && kvm_sync_page_transient(vcpu, sp))
1465 break;
1466
1467 mmu_page_add_parent_pte(vcpu, sp, parent_pte);
1468 if (sp->unsync_children) {
1469 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
1470 kvm_mmu_mark_parents_unsync(sp);
1471 } else if (sp->unsync)
1472 kvm_mmu_mark_parents_unsync(sp);
1473
1474 trace_kvm_mmu_get_page(sp, false);
1475 return sp;
1476 }
1477 ++vcpu->kvm->stat.mmu_cache_miss;
1478 sp = kvm_mmu_alloc_page(vcpu, parent_pte, direct);
1479 if (!sp)
1480 return sp;
1481 sp->gfn = gfn;
1482 sp->role = role;
1483 hlist_add_head(&sp->hash_link,
1484 &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]);
1485 if (!direct) {
1486 if (rmap_write_protect(vcpu->kvm, gfn))
1487 kvm_flush_remote_tlbs(vcpu->kvm);
1488 if (level > PT_PAGE_TABLE_LEVEL && need_sync)
1489 kvm_sync_pages(vcpu, gfn);
1490
1491 account_shadowed(vcpu->kvm, gfn);
1492 }
1493 if (shadow_trap_nonpresent_pte != shadow_notrap_nonpresent_pte)
1494 vcpu->arch.mmu.prefetch_page(vcpu, sp);
1495 else
1496 nonpaging_prefetch_page(vcpu, sp);
1497 trace_kvm_mmu_get_page(sp, true);
1498 return sp;
1499 }
1500
1501 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
1502 struct kvm_vcpu *vcpu, u64 addr)
1503 {
1504 iterator->addr = addr;
1505 iterator->shadow_addr = vcpu->arch.mmu.root_hpa;
1506 iterator->level = vcpu->arch.mmu.shadow_root_level;
1507 if (iterator->level == PT32E_ROOT_LEVEL) {
1508 iterator->shadow_addr
1509 = vcpu->arch.mmu.pae_root[(addr >> 30) & 3];
1510 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
1511 --iterator->level;
1512 if (!iterator->shadow_addr)
1513 iterator->level = 0;
1514 }
1515 }
1516
1517 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
1518 {
1519 if (iterator->level < PT_PAGE_TABLE_LEVEL)
1520 return false;
1521
1522 if (iterator->level == PT_PAGE_TABLE_LEVEL)
1523 if (is_large_pte(*iterator->sptep))
1524 return false;
1525
1526 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
1527 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
1528 return true;
1529 }
1530
1531 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
1532 {
1533 iterator->shadow_addr = *iterator->sptep & PT64_BASE_ADDR_MASK;
1534 --iterator->level;
1535 }
1536
1537 static void link_shadow_page(u64 *sptep, struct kvm_mmu_page *sp)
1538 {
1539 u64 spte;
1540
1541 spte = __pa(sp->spt)
1542 | PT_PRESENT_MASK | PT_ACCESSED_MASK
1543 | PT_WRITABLE_MASK | PT_USER_MASK;
1544 __set_spte(sptep, spte);
1545 }
1546
1547 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1548 {
1549 if (is_large_pte(*sptep)) {
1550 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1551 kvm_flush_remote_tlbs(vcpu->kvm);
1552 }
1553 }
1554
1555 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1556 unsigned direct_access)
1557 {
1558 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
1559 struct kvm_mmu_page *child;
1560
1561 /*
1562 * For the direct sp, if the guest pte's dirty bit
1563 * changed form clean to dirty, it will corrupt the
1564 * sp's access: allow writable in the read-only sp,
1565 * so we should update the spte at this point to get
1566 * a new sp with the correct access.
1567 */
1568 child = page_header(*sptep & PT64_BASE_ADDR_MASK);
1569 if (child->role.access == direct_access)
1570 return;
1571
1572 mmu_page_remove_parent_pte(child, sptep);
1573 __set_spte(sptep, shadow_trap_nonpresent_pte);
1574 kvm_flush_remote_tlbs(vcpu->kvm);
1575 }
1576 }
1577
1578 static void kvm_mmu_page_unlink_children(struct kvm *kvm,
1579 struct kvm_mmu_page *sp)
1580 {
1581 unsigned i;
1582 u64 *pt;
1583 u64 ent;
1584
1585 pt = sp->spt;
1586
1587 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1588 ent = pt[i];
1589
1590 if (is_shadow_present_pte(ent)) {
1591 if (!is_last_spte(ent, sp->role.level)) {
1592 ent &= PT64_BASE_ADDR_MASK;
1593 mmu_page_remove_parent_pte(page_header(ent),
1594 &pt[i]);
1595 } else {
1596 if (is_large_pte(ent))
1597 --kvm->stat.lpages;
1598 drop_spte(kvm, &pt[i],
1599 shadow_trap_nonpresent_pte);
1600 }
1601 }
1602 pt[i] = shadow_trap_nonpresent_pte;
1603 }
1604 }
1605
1606 static void kvm_mmu_put_page(struct kvm_mmu_page *sp, u64 *parent_pte)
1607 {
1608 mmu_page_remove_parent_pte(sp, parent_pte);
1609 }
1610
1611 static void kvm_mmu_reset_last_pte_updated(struct kvm *kvm)
1612 {
1613 int i;
1614 struct kvm_vcpu *vcpu;
1615
1616 kvm_for_each_vcpu(i, vcpu, kvm)
1617 vcpu->arch.last_pte_updated = NULL;
1618 }
1619
1620 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
1621 {
1622 u64 *parent_pte;
1623
1624 while (sp->multimapped || sp->parent_pte) {
1625 if (!sp->multimapped)
1626 parent_pte = sp->parent_pte;
1627 else {
1628 struct kvm_pte_chain *chain;
1629
1630 chain = container_of(sp->parent_ptes.first,
1631 struct kvm_pte_chain, link);
1632 parent_pte = chain->parent_ptes[0];
1633 }
1634 BUG_ON(!parent_pte);
1635 kvm_mmu_put_page(sp, parent_pte);
1636 __set_spte(parent_pte, shadow_trap_nonpresent_pte);
1637 }
1638 }
1639
1640 static int mmu_zap_unsync_children(struct kvm *kvm,
1641 struct kvm_mmu_page *parent,
1642 struct list_head *invalid_list)
1643 {
1644 int i, zapped = 0;
1645 struct mmu_page_path parents;
1646 struct kvm_mmu_pages pages;
1647
1648 if (parent->role.level == PT_PAGE_TABLE_LEVEL)
1649 return 0;
1650
1651 kvm_mmu_pages_init(parent, &parents, &pages);
1652 while (mmu_unsync_walk(parent, &pages)) {
1653 struct kvm_mmu_page *sp;
1654
1655 for_each_sp(pages, sp, parents, i) {
1656 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
1657 mmu_pages_clear_parents(&parents);
1658 zapped++;
1659 }
1660 kvm_mmu_pages_init(parent, &parents, &pages);
1661 }
1662
1663 return zapped;
1664 }
1665
1666 static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1667 struct list_head *invalid_list)
1668 {
1669 int ret;
1670
1671 trace_kvm_mmu_prepare_zap_page(sp);
1672 ++kvm->stat.mmu_shadow_zapped;
1673 ret = mmu_zap_unsync_children(kvm, sp, invalid_list);
1674 kvm_mmu_page_unlink_children(kvm, sp);
1675 kvm_mmu_unlink_parents(kvm, sp);
1676 if (!sp->role.invalid && !sp->role.direct)
1677 unaccount_shadowed(kvm, sp->gfn);
1678 if (sp->unsync)
1679 kvm_unlink_unsync_page(kvm, sp);
1680 if (!sp->root_count) {
1681 /* Count self */
1682 ret++;
1683 list_move(&sp->link, invalid_list);
1684 } else {
1685 list_move(&sp->link, &kvm->arch.active_mmu_pages);
1686 kvm_reload_remote_mmus(kvm);
1687 }
1688
1689 sp->role.invalid = 1;
1690 kvm_mmu_reset_last_pte_updated(kvm);
1691 return ret;
1692 }
1693
1694 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1695 struct list_head *invalid_list)
1696 {
1697 struct kvm_mmu_page *sp;
1698
1699 if (list_empty(invalid_list))
1700 return;
1701
1702 kvm_flush_remote_tlbs(kvm);
1703
1704 do {
1705 sp = list_first_entry(invalid_list, struct kvm_mmu_page, link);
1706 WARN_ON(!sp->role.invalid || sp->root_count);
1707 kvm_mmu_free_page(kvm, sp);
1708 } while (!list_empty(invalid_list));
1709
1710 }
1711
1712 /*
1713 * Changing the number of mmu pages allocated to the vm
1714 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
1715 */
1716 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages)
1717 {
1718 LIST_HEAD(invalid_list);
1719 /*
1720 * If we set the number of mmu pages to be smaller be than the
1721 * number of actived pages , we must to free some mmu pages before we
1722 * change the value
1723 */
1724
1725 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
1726 while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages &&
1727 !list_empty(&kvm->arch.active_mmu_pages)) {
1728 struct kvm_mmu_page *page;
1729
1730 page = container_of(kvm->arch.active_mmu_pages.prev,
1731 struct kvm_mmu_page, link);
1732 kvm_mmu_prepare_zap_page(kvm, page, &invalid_list);
1733 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1734 }
1735 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
1736 }
1737
1738 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
1739 }
1740
1741 static int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
1742 {
1743 struct kvm_mmu_page *sp;
1744 struct hlist_node *node;
1745 LIST_HEAD(invalid_list);
1746 int r;
1747
1748 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
1749 r = 0;
1750
1751 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1752 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
1753 sp->role.word);
1754 r = 1;
1755 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1756 }
1757 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1758 return r;
1759 }
1760
1761 static void mmu_unshadow(struct kvm *kvm, gfn_t gfn)
1762 {
1763 struct kvm_mmu_page *sp;
1764 struct hlist_node *node;
1765 LIST_HEAD(invalid_list);
1766
1767 for_each_gfn_indirect_valid_sp(kvm, sp, gfn, node) {
1768 pgprintk("%s: zap %llx %x\n",
1769 __func__, gfn, sp->role.word);
1770 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
1771 }
1772 kvm_mmu_commit_zap_page(kvm, &invalid_list);
1773 }
1774
1775 static void page_header_update_slot(struct kvm *kvm, void *pte, gfn_t gfn)
1776 {
1777 int slot = memslot_id(kvm, gfn);
1778 struct kvm_mmu_page *sp = page_header(__pa(pte));
1779
1780 __set_bit(slot, sp->slot_bitmap);
1781 }
1782
1783 static void mmu_convert_notrap(struct kvm_mmu_page *sp)
1784 {
1785 int i;
1786 u64 *pt = sp->spt;
1787
1788 if (shadow_trap_nonpresent_pte == shadow_notrap_nonpresent_pte)
1789 return;
1790
1791 for (i = 0; i < PT64_ENT_PER_PAGE; ++i) {
1792 if (pt[i] == shadow_notrap_nonpresent_pte)
1793 __set_spte(&pt[i], shadow_trap_nonpresent_pte);
1794 }
1795 }
1796
1797 /*
1798 * The function is based on mtrr_type_lookup() in
1799 * arch/x86/kernel/cpu/mtrr/generic.c
1800 */
1801 static int get_mtrr_type(struct mtrr_state_type *mtrr_state,
1802 u64 start, u64 end)
1803 {
1804 int i;
1805 u64 base, mask;
1806 u8 prev_match, curr_match;
1807 int num_var_ranges = KVM_NR_VAR_MTRR;
1808
1809 if (!mtrr_state->enabled)
1810 return 0xFF;
1811
1812 /* Make end inclusive end, instead of exclusive */
1813 end--;
1814
1815 /* Look in fixed ranges. Just return the type as per start */
1816 if (mtrr_state->have_fixed && (start < 0x100000)) {
1817 int idx;
1818
1819 if (start < 0x80000) {
1820 idx = 0;
1821 idx += (start >> 16);
1822 return mtrr_state->fixed_ranges[idx];
1823 } else if (start < 0xC0000) {
1824 idx = 1 * 8;
1825 idx += ((start - 0x80000) >> 14);
1826 return mtrr_state->fixed_ranges[idx];
1827 } else if (start < 0x1000000) {
1828 idx = 3 * 8;
1829 idx += ((start - 0xC0000) >> 12);
1830 return mtrr_state->fixed_ranges[idx];
1831 }
1832 }
1833
1834 /*
1835 * Look in variable ranges
1836 * Look of multiple ranges matching this address and pick type
1837 * as per MTRR precedence
1838 */
1839 if (!(mtrr_state->enabled & 2))
1840 return mtrr_state->def_type;
1841
1842 prev_match = 0xFF;
1843 for (i = 0; i < num_var_ranges; ++i) {
1844 unsigned short start_state, end_state;
1845
1846 if (!(mtrr_state->var_ranges[i].mask_lo & (1 << 11)))
1847 continue;
1848
1849 base = (((u64)mtrr_state->var_ranges[i].base_hi) << 32) +
1850 (mtrr_state->var_ranges[i].base_lo & PAGE_MASK);
1851 mask = (((u64)mtrr_state->var_ranges[i].mask_hi) << 32) +
1852 (mtrr_state->var_ranges[i].mask_lo & PAGE_MASK);
1853
1854 start_state = ((start & mask) == (base & mask));
1855 end_state = ((end & mask) == (base & mask));
1856 if (start_state != end_state)
1857 return 0xFE;
1858
1859 if ((start & mask) != (base & mask))
1860 continue;
1861
1862 curr_match = mtrr_state->var_ranges[i].base_lo & 0xff;
1863 if (prev_match == 0xFF) {
1864 prev_match = curr_match;
1865 continue;
1866 }
1867
1868 if (prev_match == MTRR_TYPE_UNCACHABLE ||
1869 curr_match == MTRR_TYPE_UNCACHABLE)
1870 return MTRR_TYPE_UNCACHABLE;
1871
1872 if ((prev_match == MTRR_TYPE_WRBACK &&
1873 curr_match == MTRR_TYPE_WRTHROUGH) ||
1874 (prev_match == MTRR_TYPE_WRTHROUGH &&
1875 curr_match == MTRR_TYPE_WRBACK)) {
1876 prev_match = MTRR_TYPE_WRTHROUGH;
1877 curr_match = MTRR_TYPE_WRTHROUGH;
1878 }
1879
1880 if (prev_match != curr_match)
1881 return MTRR_TYPE_UNCACHABLE;
1882 }
1883
1884 if (prev_match != 0xFF)
1885 return prev_match;
1886
1887 return mtrr_state->def_type;
1888 }
1889
1890 u8 kvm_get_guest_memory_type(struct kvm_vcpu *vcpu, gfn_t gfn)
1891 {
1892 u8 mtrr;
1893
1894 mtrr = get_mtrr_type(&vcpu->arch.mtrr_state, gfn << PAGE_SHIFT,
1895 (gfn << PAGE_SHIFT) + PAGE_SIZE);
1896 if (mtrr == 0xfe || mtrr == 0xff)
1897 mtrr = MTRR_TYPE_WRBACK;
1898 return mtrr;
1899 }
1900 EXPORT_SYMBOL_GPL(kvm_get_guest_memory_type);
1901
1902 static void __kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
1903 {
1904 trace_kvm_mmu_unsync_page(sp);
1905 ++vcpu->kvm->stat.mmu_unsync;
1906 sp->unsync = 1;
1907
1908 kvm_mmu_mark_parents_unsync(sp);
1909 mmu_convert_notrap(sp);
1910 }
1911
1912 static void kvm_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn)
1913 {
1914 struct kvm_mmu_page *s;
1915 struct hlist_node *node;
1916
1917 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1918 if (s->unsync)
1919 continue;
1920 WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL);
1921 __kvm_unsync_page(vcpu, s);
1922 }
1923 }
1924
1925 static int mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn,
1926 bool can_unsync)
1927 {
1928 struct kvm_mmu_page *s;
1929 struct hlist_node *node;
1930 bool need_unsync = false;
1931
1932 for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn, node) {
1933 if (!can_unsync)
1934 return 1;
1935
1936 if (s->role.level != PT_PAGE_TABLE_LEVEL)
1937 return 1;
1938
1939 if (!need_unsync && !s->unsync) {
1940 if (!oos_shadow)
1941 return 1;
1942 need_unsync = true;
1943 }
1944 }
1945 if (need_unsync)
1946 kvm_unsync_pages(vcpu, gfn);
1947 return 0;
1948 }
1949
1950 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
1951 unsigned pte_access, int user_fault,
1952 int write_fault, int dirty, int level,
1953 gfn_t gfn, pfn_t pfn, bool speculative,
1954 bool can_unsync, bool reset_host_protection)
1955 {
1956 u64 spte;
1957 int ret = 0;
1958
1959 /*
1960 * We don't set the accessed bit, since we sometimes want to see
1961 * whether the guest actually used the pte (in order to detect
1962 * demand paging).
1963 */
1964 spte = shadow_base_present_pte;
1965 if (!speculative)
1966 spte |= shadow_accessed_mask;
1967 if (!dirty)
1968 pte_access &= ~ACC_WRITE_MASK;
1969 if (pte_access & ACC_EXEC_MASK)
1970 spte |= shadow_x_mask;
1971 else
1972 spte |= shadow_nx_mask;
1973 if (pte_access & ACC_USER_MASK)
1974 spte |= shadow_user_mask;
1975 if (level > PT_PAGE_TABLE_LEVEL)
1976 spte |= PT_PAGE_SIZE_MASK;
1977 if (vcpu->arch.mmu.direct_map)
1978 spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn,
1979 kvm_is_mmio_pfn(pfn));
1980
1981 if (reset_host_protection)
1982 spte |= SPTE_HOST_WRITEABLE;
1983
1984 spte |= (u64)pfn << PAGE_SHIFT;
1985
1986 if ((pte_access & ACC_WRITE_MASK)
1987 || (!vcpu->arch.mmu.direct_map && write_fault
1988 && !is_write_protection(vcpu) && !user_fault)) {
1989
1990 if (level > PT_PAGE_TABLE_LEVEL &&
1991 has_wrprotected_page(vcpu->kvm, gfn, level)) {
1992 ret = 1;
1993 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
1994 goto done;
1995 }
1996
1997 spte |= PT_WRITABLE_MASK;
1998
1999 if (!vcpu->arch.mmu.direct_map
2000 && !(pte_access & ACC_WRITE_MASK))
2001 spte &= ~PT_USER_MASK;
2002
2003 /*
2004 * Optimization: for pte sync, if spte was writable the hash
2005 * lookup is unnecessary (and expensive). Write protection
2006 * is responsibility of mmu_get_page / kvm_sync_page.
2007 * Same reasoning can be applied to dirty page accounting.
2008 */
2009 if (!can_unsync && is_writable_pte(*sptep))
2010 goto set_pte;
2011
2012 if (mmu_need_write_protect(vcpu, gfn, can_unsync)) {
2013 pgprintk("%s: found shadow page for %llx, marking ro\n",
2014 __func__, gfn);
2015 ret = 1;
2016 pte_access &= ~ACC_WRITE_MASK;
2017 if (is_writable_pte(spte))
2018 spte &= ~PT_WRITABLE_MASK;
2019 }
2020 }
2021
2022 if (pte_access & ACC_WRITE_MASK)
2023 mark_page_dirty(vcpu->kvm, gfn);
2024
2025 set_pte:
2026 update_spte(sptep, spte);
2027 done:
2028 return ret;
2029 }
2030
2031 static void mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2032 unsigned pt_access, unsigned pte_access,
2033 int user_fault, int write_fault, int dirty,
2034 int *ptwrite, int level, gfn_t gfn,
2035 pfn_t pfn, bool speculative,
2036 bool reset_host_protection)
2037 {
2038 int was_rmapped = 0;
2039 int rmap_count;
2040
2041 pgprintk("%s: spte %llx access %x write_fault %d"
2042 " user_fault %d gfn %llx\n",
2043 __func__, *sptep, pt_access,
2044 write_fault, user_fault, gfn);
2045
2046 if (is_rmap_spte(*sptep)) {
2047 /*
2048 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2049 * the parent of the now unreachable PTE.
2050 */
2051 if (level > PT_PAGE_TABLE_LEVEL &&
2052 !is_large_pte(*sptep)) {
2053 struct kvm_mmu_page *child;
2054 u64 pte = *sptep;
2055
2056 child = page_header(pte & PT64_BASE_ADDR_MASK);
2057 mmu_page_remove_parent_pte(child, sptep);
2058 __set_spte(sptep, shadow_trap_nonpresent_pte);
2059 kvm_flush_remote_tlbs(vcpu->kvm);
2060 } else if (pfn != spte_to_pfn(*sptep)) {
2061 pgprintk("hfn old %llx new %llx\n",
2062 spte_to_pfn(*sptep), pfn);
2063 drop_spte(vcpu->kvm, sptep, shadow_trap_nonpresent_pte);
2064 kvm_flush_remote_tlbs(vcpu->kvm);
2065 } else
2066 was_rmapped = 1;
2067 }
2068
2069 if (set_spte(vcpu, sptep, pte_access, user_fault, write_fault,
2070 dirty, level, gfn, pfn, speculative, true,
2071 reset_host_protection)) {
2072 if (write_fault)
2073 *ptwrite = 1;
2074 kvm_mmu_flush_tlb(vcpu);
2075 }
2076
2077 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2078 pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n",
2079 is_large_pte(*sptep)? "2MB" : "4kB",
2080 *sptep & PT_PRESENT_MASK ?"RW":"R", gfn,
2081 *sptep, sptep);
2082 if (!was_rmapped && is_large_pte(*sptep))
2083 ++vcpu->kvm->stat.lpages;
2084
2085 page_header_update_slot(vcpu->kvm, sptep, gfn);
2086 if (!was_rmapped) {
2087 rmap_count = rmap_add(vcpu, sptep, gfn);
2088 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2089 rmap_recycle(vcpu, sptep, gfn);
2090 }
2091 kvm_release_pfn_clean(pfn);
2092 if (speculative) {
2093 vcpu->arch.last_pte_updated = sptep;
2094 vcpu->arch.last_pte_gfn = gfn;
2095 }
2096 }
2097
2098 static void nonpaging_new_cr3(struct kvm_vcpu *vcpu)
2099 {
2100 }
2101
2102 static struct kvm_memory_slot *
2103 pte_prefetch_gfn_to_memslot(struct kvm_vcpu *vcpu, gfn_t gfn, bool no_dirty_log)
2104 {
2105 struct kvm_memory_slot *slot;
2106
2107 slot = gfn_to_memslot(vcpu->kvm, gfn);
2108 if (!slot || slot->flags & KVM_MEMSLOT_INVALID ||
2109 (no_dirty_log && slot->dirty_bitmap))
2110 slot = NULL;
2111
2112 return slot;
2113 }
2114
2115 static pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2116 bool no_dirty_log)
2117 {
2118 struct kvm_memory_slot *slot;
2119 unsigned long hva;
2120
2121 slot = pte_prefetch_gfn_to_memslot(vcpu, gfn, no_dirty_log);
2122 if (!slot) {
2123 get_page(bad_page);
2124 return page_to_pfn(bad_page);
2125 }
2126
2127 hva = gfn_to_hva_memslot(slot, gfn);
2128
2129 return hva_to_pfn_atomic(vcpu->kvm, hva);
2130 }
2131
2132 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2133 struct kvm_mmu_page *sp,
2134 u64 *start, u64 *end)
2135 {
2136 struct page *pages[PTE_PREFETCH_NUM];
2137 unsigned access = sp->role.access;
2138 int i, ret;
2139 gfn_t gfn;
2140
2141 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2142 if (!pte_prefetch_gfn_to_memslot(vcpu, gfn, access & ACC_WRITE_MASK))
2143 return -1;
2144
2145 ret = gfn_to_page_many_atomic(vcpu->kvm, gfn, pages, end - start);
2146 if (ret <= 0)
2147 return -1;
2148
2149 for (i = 0; i < ret; i++, gfn++, start++)
2150 mmu_set_spte(vcpu, start, ACC_ALL,
2151 access, 0, 0, 1, NULL,
2152 sp->role.level, gfn,
2153 page_to_pfn(pages[i]), true, true);
2154
2155 return 0;
2156 }
2157
2158 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2159 struct kvm_mmu_page *sp, u64 *sptep)
2160 {
2161 u64 *spte, *start = NULL;
2162 int i;
2163
2164 WARN_ON(!sp->role.direct);
2165
2166 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2167 spte = sp->spt + i;
2168
2169 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2170 if (*spte != shadow_trap_nonpresent_pte || spte == sptep) {
2171 if (!start)
2172 continue;
2173 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2174 break;
2175 start = NULL;
2176 } else if (!start)
2177 start = spte;
2178 }
2179 }
2180
2181 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2182 {
2183 struct kvm_mmu_page *sp;
2184
2185 /*
2186 * Since it's no accessed bit on EPT, it's no way to
2187 * distinguish between actually accessed translations
2188 * and prefetched, so disable pte prefetch if EPT is
2189 * enabled.
2190 */
2191 if (!shadow_accessed_mask)
2192 return;
2193
2194 sp = page_header(__pa(sptep));
2195 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
2196 return;
2197
2198 __direct_pte_prefetch(vcpu, sp, sptep);
2199 }
2200
2201 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t v, int write,
2202 int level, gfn_t gfn, pfn_t pfn)
2203 {
2204 struct kvm_shadow_walk_iterator iterator;
2205 struct kvm_mmu_page *sp;
2206 int pt_write = 0;
2207 gfn_t pseudo_gfn;
2208
2209 for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) {
2210 if (iterator.level == level) {
2211 mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, ACC_ALL,
2212 0, write, 1, &pt_write,
2213 level, gfn, pfn, false, true);
2214 direct_pte_prefetch(vcpu, iterator.sptep);
2215 ++vcpu->stat.pf_fixed;
2216 break;
2217 }
2218
2219 if (*iterator.sptep == shadow_trap_nonpresent_pte) {
2220 u64 base_addr = iterator.addr;
2221
2222 base_addr &= PT64_LVL_ADDR_MASK(iterator.level);
2223 pseudo_gfn = base_addr >> PAGE_SHIFT;
2224 sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr,
2225 iterator.level - 1,
2226 1, ACC_ALL, iterator.sptep);
2227 if (!sp) {
2228 pgprintk("nonpaging_map: ENOMEM\n");
2229 kvm_release_pfn_clean(pfn);
2230 return -ENOMEM;
2231 }
2232
2233 __set_spte(iterator.sptep,
2234 __pa(sp->spt)
2235 | PT_PRESENT_MASK | PT_WRITABLE_MASK
2236 | shadow_user_mask | shadow_x_mask);
2237 }
2238 }
2239 return pt_write;
2240 }
2241
2242 static void kvm_send_hwpoison_signal(struct kvm *kvm, gfn_t gfn)
2243 {
2244 char buf[1];
2245 void __user *hva;
2246 int r;
2247
2248 /* Touch the page, so send SIGBUS */
2249 hva = (void __user *)gfn_to_hva(kvm, gfn);
2250 r = copy_from_user(buf, hva, 1);
2251 }
2252
2253 static int kvm_handle_bad_page(struct kvm *kvm, gfn_t gfn, pfn_t pfn)
2254 {
2255 kvm_release_pfn_clean(pfn);
2256 if (is_hwpoison_pfn(pfn)) {
2257 kvm_send_hwpoison_signal(kvm, gfn);
2258 return 0;
2259 } else if (is_fault_pfn(pfn))
2260 return -EFAULT;
2261
2262 return 1;
2263 }
2264
2265 static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, int write, gfn_t gfn)
2266 {
2267 int r;
2268 int level;
2269 pfn_t pfn;
2270 unsigned long mmu_seq;
2271
2272 level = mapping_level(vcpu, gfn);
2273
2274 /*
2275 * This path builds a PAE pagetable - so we can map 2mb pages at
2276 * maximum. Therefore check if the level is larger than that.
2277 */
2278 if (level > PT_DIRECTORY_LEVEL)
2279 level = PT_DIRECTORY_LEVEL;
2280
2281 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2282
2283 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2284 smp_rmb();
2285 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2286
2287 /* mmio */
2288 if (is_error_pfn(pfn))
2289 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
2290
2291 spin_lock(&vcpu->kvm->mmu_lock);
2292 if (mmu_notifier_retry(vcpu, mmu_seq))
2293 goto out_unlock;
2294 kvm_mmu_free_some_pages(vcpu);
2295 r = __direct_map(vcpu, v, write, level, gfn, pfn);
2296 spin_unlock(&vcpu->kvm->mmu_lock);
2297
2298
2299 return r;
2300
2301 out_unlock:
2302 spin_unlock(&vcpu->kvm->mmu_lock);
2303 kvm_release_pfn_clean(pfn);
2304 return 0;
2305 }
2306
2307
2308 static void mmu_free_roots(struct kvm_vcpu *vcpu)
2309 {
2310 int i;
2311 struct kvm_mmu_page *sp;
2312 LIST_HEAD(invalid_list);
2313
2314 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2315 return;
2316 spin_lock(&vcpu->kvm->mmu_lock);
2317 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2318 hpa_t root = vcpu->arch.mmu.root_hpa;
2319
2320 sp = page_header(root);
2321 --sp->root_count;
2322 if (!sp->root_count && sp->role.invalid) {
2323 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
2324 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2325 }
2326 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2327 spin_unlock(&vcpu->kvm->mmu_lock);
2328 return;
2329 }
2330 for (i = 0; i < 4; ++i) {
2331 hpa_t root = vcpu->arch.mmu.pae_root[i];
2332
2333 if (root) {
2334 root &= PT64_BASE_ADDR_MASK;
2335 sp = page_header(root);
2336 --sp->root_count;
2337 if (!sp->root_count && sp->role.invalid)
2338 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2339 &invalid_list);
2340 }
2341 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
2342 }
2343 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2344 spin_unlock(&vcpu->kvm->mmu_lock);
2345 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
2346 }
2347
2348 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
2349 {
2350 int ret = 0;
2351
2352 if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) {
2353 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2354 ret = 1;
2355 }
2356
2357 return ret;
2358 }
2359
2360 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
2361 {
2362 struct kvm_mmu_page *sp;
2363 int i;
2364
2365 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2366 spin_lock(&vcpu->kvm->mmu_lock);
2367 kvm_mmu_free_some_pages(vcpu);
2368 sp = kvm_mmu_get_page(vcpu, 0, 0, PT64_ROOT_LEVEL,
2369 1, ACC_ALL, NULL);
2370 ++sp->root_count;
2371 spin_unlock(&vcpu->kvm->mmu_lock);
2372 vcpu->arch.mmu.root_hpa = __pa(sp->spt);
2373 } else if (vcpu->arch.mmu.shadow_root_level == PT32E_ROOT_LEVEL) {
2374 for (i = 0; i < 4; ++i) {
2375 hpa_t root = vcpu->arch.mmu.pae_root[i];
2376
2377 ASSERT(!VALID_PAGE(root));
2378 spin_lock(&vcpu->kvm->mmu_lock);
2379 kvm_mmu_free_some_pages(vcpu);
2380 sp = kvm_mmu_get_page(vcpu, i << 30, i << 30,
2381 PT32_ROOT_LEVEL, 1, ACC_ALL,
2382 NULL);
2383 root = __pa(sp->spt);
2384 ++sp->root_count;
2385 spin_unlock(&vcpu->kvm->mmu_lock);
2386 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2387 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2388 }
2389 } else
2390 BUG();
2391
2392 return 0;
2393 }
2394
2395 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
2396 {
2397 int i;
2398 gfn_t root_gfn;
2399 struct kvm_mmu_page *sp;
2400 u64 pdptr;
2401
2402 root_gfn = vcpu->arch.mmu.get_cr3(vcpu) >> PAGE_SHIFT;
2403
2404 if (mmu_check_root(vcpu, root_gfn))
2405 return 1;
2406
2407 /*
2408 * Do we shadow a long mode page table? If so we need to
2409 * write-protect the guests page table root.
2410 */
2411 if (vcpu->arch.mmu.root_level == PT64_ROOT_LEVEL) {
2412 hpa_t root = vcpu->arch.mmu.root_hpa;
2413
2414 ASSERT(!VALID_PAGE(root));
2415
2416 spin_lock(&vcpu->kvm->mmu_lock);
2417 kvm_mmu_free_some_pages(vcpu);
2418 sp = kvm_mmu_get_page(vcpu, root_gfn, 0, PT64_ROOT_LEVEL,
2419 0, ACC_ALL, NULL);
2420 root = __pa(sp->spt);
2421 ++sp->root_count;
2422 spin_unlock(&vcpu->kvm->mmu_lock);
2423 vcpu->arch.mmu.root_hpa = root;
2424 return 0;
2425 }
2426
2427 /*
2428 * We shadow a 32 bit page table. This may be a legacy 2-level
2429 * or a PAE 3-level page table.
2430 */
2431 for (i = 0; i < 4; ++i) {
2432 hpa_t root = vcpu->arch.mmu.pae_root[i];
2433
2434 ASSERT(!VALID_PAGE(root));
2435 if (vcpu->arch.mmu.root_level == PT32E_ROOT_LEVEL) {
2436 pdptr = kvm_pdptr_read_mmu(vcpu, &vcpu->arch.mmu, i);
2437 if (!is_present_gpte(pdptr)) {
2438 vcpu->arch.mmu.pae_root[i] = 0;
2439 continue;
2440 }
2441 root_gfn = pdptr >> PAGE_SHIFT;
2442 if (mmu_check_root(vcpu, root_gfn))
2443 return 1;
2444 }
2445 spin_lock(&vcpu->kvm->mmu_lock);
2446 kvm_mmu_free_some_pages(vcpu);
2447 sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30,
2448 PT32_ROOT_LEVEL, 0,
2449 ACC_ALL, NULL);
2450 root = __pa(sp->spt);
2451 ++sp->root_count;
2452 spin_unlock(&vcpu->kvm->mmu_lock);
2453
2454 vcpu->arch.mmu.pae_root[i] = root | PT_PRESENT_MASK;
2455 }
2456 vcpu->arch.mmu.root_hpa = __pa(vcpu->arch.mmu.pae_root);
2457 return 0;
2458 }
2459
2460 static int mmu_alloc_roots(struct kvm_vcpu *vcpu)
2461 {
2462 if (vcpu->arch.mmu.direct_map)
2463 return mmu_alloc_direct_roots(vcpu);
2464 else
2465 return mmu_alloc_shadow_roots(vcpu);
2466 }
2467
2468 static void mmu_sync_roots(struct kvm_vcpu *vcpu)
2469 {
2470 int i;
2471 struct kvm_mmu_page *sp;
2472
2473 if (!VALID_PAGE(vcpu->arch.mmu.root_hpa))
2474 return;
2475 if (vcpu->arch.mmu.shadow_root_level == PT64_ROOT_LEVEL) {
2476 hpa_t root = vcpu->arch.mmu.root_hpa;
2477 sp = page_header(root);
2478 mmu_sync_children(vcpu, sp);
2479 return;
2480 }
2481 for (i = 0; i < 4; ++i) {
2482 hpa_t root = vcpu->arch.mmu.pae_root[i];
2483
2484 if (root && VALID_PAGE(root)) {
2485 root &= PT64_BASE_ADDR_MASK;
2486 sp = page_header(root);
2487 mmu_sync_children(vcpu, sp);
2488 }
2489 }
2490 }
2491
2492 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
2493 {
2494 spin_lock(&vcpu->kvm->mmu_lock);
2495 mmu_sync_roots(vcpu);
2496 spin_unlock(&vcpu->kvm->mmu_lock);
2497 }
2498
2499 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr,
2500 u32 access, u32 *error)
2501 {
2502 if (error)
2503 *error = 0;
2504 return vaddr;
2505 }
2506
2507 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr,
2508 u32 access, u32 *error)
2509 {
2510 if (error)
2511 *error = 0;
2512 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access);
2513 }
2514
2515 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva,
2516 u32 error_code)
2517 {
2518 gfn_t gfn;
2519 int r;
2520
2521 pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code);
2522 r = mmu_topup_memory_caches(vcpu);
2523 if (r)
2524 return r;
2525
2526 ASSERT(vcpu);
2527 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2528
2529 gfn = gva >> PAGE_SHIFT;
2530
2531 return nonpaging_map(vcpu, gva & PAGE_MASK,
2532 error_code & PFERR_WRITE_MASK, gfn);
2533 }
2534
2535 static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa,
2536 u32 error_code)
2537 {
2538 pfn_t pfn;
2539 int r;
2540 int level;
2541 gfn_t gfn = gpa >> PAGE_SHIFT;
2542 unsigned long mmu_seq;
2543
2544 ASSERT(vcpu);
2545 ASSERT(VALID_PAGE(vcpu->arch.mmu.root_hpa));
2546
2547 r = mmu_topup_memory_caches(vcpu);
2548 if (r)
2549 return r;
2550
2551 level = mapping_level(vcpu, gfn);
2552
2553 gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1);
2554
2555 mmu_seq = vcpu->kvm->mmu_notifier_seq;
2556 smp_rmb();
2557 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2558 if (is_error_pfn(pfn))
2559 return kvm_handle_bad_page(vcpu->kvm, gfn, pfn);
2560 spin_lock(&vcpu->kvm->mmu_lock);
2561 if (mmu_notifier_retry(vcpu, mmu_seq))
2562 goto out_unlock;
2563 kvm_mmu_free_some_pages(vcpu);
2564 r = __direct_map(vcpu, gpa, error_code & PFERR_WRITE_MASK,
2565 level, gfn, pfn);
2566 spin_unlock(&vcpu->kvm->mmu_lock);
2567
2568 return r;
2569
2570 out_unlock:
2571 spin_unlock(&vcpu->kvm->mmu_lock);
2572 kvm_release_pfn_clean(pfn);
2573 return 0;
2574 }
2575
2576 static void nonpaging_free(struct kvm_vcpu *vcpu)
2577 {
2578 mmu_free_roots(vcpu);
2579 }
2580
2581 static int nonpaging_init_context(struct kvm_vcpu *vcpu,
2582 struct kvm_mmu *context)
2583 {
2584 context->new_cr3 = nonpaging_new_cr3;
2585 context->page_fault = nonpaging_page_fault;
2586 context->gva_to_gpa = nonpaging_gva_to_gpa;
2587 context->free = nonpaging_free;
2588 context->prefetch_page = nonpaging_prefetch_page;
2589 context->sync_page = nonpaging_sync_page;
2590 context->invlpg = nonpaging_invlpg;
2591 context->root_level = 0;
2592 context->shadow_root_level = PT32E_ROOT_LEVEL;
2593 context->root_hpa = INVALID_PAGE;
2594 context->direct_map = true;
2595 return 0;
2596 }
2597
2598 void kvm_mmu_flush_tlb(struct kvm_vcpu *vcpu)
2599 {
2600 ++vcpu->stat.tlb_flush;
2601 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
2602 }
2603
2604 static void paging_new_cr3(struct kvm_vcpu *vcpu)
2605 {
2606 pgprintk("%s: cr3 %lx\n", __func__, vcpu->arch.cr3);
2607 mmu_free_roots(vcpu);
2608 }
2609
2610 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
2611 {
2612 return vcpu->arch.cr3;
2613 }
2614
2615 static void inject_page_fault(struct kvm_vcpu *vcpu)
2616 {
2617 vcpu->arch.mmu.inject_page_fault(vcpu);
2618 }
2619
2620 static void paging_free(struct kvm_vcpu *vcpu)
2621 {
2622 nonpaging_free(vcpu);
2623 }
2624
2625 static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level)
2626 {
2627 int bit7;
2628
2629 bit7 = (gpte >> 7) & 1;
2630 return (gpte & mmu->rsvd_bits_mask[bit7][level-1]) != 0;
2631 }
2632
2633 #define PTTYPE 64
2634 #include "paging_tmpl.h"
2635 #undef PTTYPE
2636
2637 #define PTTYPE 32
2638 #include "paging_tmpl.h"
2639 #undef PTTYPE
2640
2641 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
2642 struct kvm_mmu *context,
2643 int level)
2644 {
2645 int maxphyaddr = cpuid_maxphyaddr(vcpu);
2646 u64 exb_bit_rsvd = 0;
2647
2648 if (!is_nx(vcpu))
2649 exb_bit_rsvd = rsvd_bits(63, 63);
2650 switch (level) {
2651 case PT32_ROOT_LEVEL:
2652 /* no rsvd bits for 2 level 4K page table entries */
2653 context->rsvd_bits_mask[0][1] = 0;
2654 context->rsvd_bits_mask[0][0] = 0;
2655 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2656
2657 if (!is_pse(vcpu)) {
2658 context->rsvd_bits_mask[1][1] = 0;
2659 break;
2660 }
2661
2662 if (is_cpuid_PSE36())
2663 /* 36bits PSE 4MB page */
2664 context->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
2665 else
2666 /* 32 bits PSE 4MB page */
2667 context->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
2668 break;
2669 case PT32E_ROOT_LEVEL:
2670 context->rsvd_bits_mask[0][2] =
2671 rsvd_bits(maxphyaddr, 63) |
2672 rsvd_bits(7, 8) | rsvd_bits(1, 2); /* PDPTE */
2673 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2674 rsvd_bits(maxphyaddr, 62); /* PDE */
2675 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2676 rsvd_bits(maxphyaddr, 62); /* PTE */
2677 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2678 rsvd_bits(maxphyaddr, 62) |
2679 rsvd_bits(13, 20); /* large page */
2680 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2681 break;
2682 case PT64_ROOT_LEVEL:
2683 context->rsvd_bits_mask[0][3] = exb_bit_rsvd |
2684 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2685 context->rsvd_bits_mask[0][2] = exb_bit_rsvd |
2686 rsvd_bits(maxphyaddr, 51) | rsvd_bits(7, 8);
2687 context->rsvd_bits_mask[0][1] = exb_bit_rsvd |
2688 rsvd_bits(maxphyaddr, 51);
2689 context->rsvd_bits_mask[0][0] = exb_bit_rsvd |
2690 rsvd_bits(maxphyaddr, 51);
2691 context->rsvd_bits_mask[1][3] = context->rsvd_bits_mask[0][3];
2692 context->rsvd_bits_mask[1][2] = exb_bit_rsvd |
2693 rsvd_bits(maxphyaddr, 51) |
2694 rsvd_bits(13, 29);
2695 context->rsvd_bits_mask[1][1] = exb_bit_rsvd |
2696 rsvd_bits(maxphyaddr, 51) |
2697 rsvd_bits(13, 20); /* large page */
2698 context->rsvd_bits_mask[1][0] = context->rsvd_bits_mask[0][0];
2699 break;
2700 }
2701 }
2702
2703 static int paging64_init_context_common(struct kvm_vcpu *vcpu,
2704 struct kvm_mmu *context,
2705 int level)
2706 {
2707 reset_rsvds_bits_mask(vcpu, context, level);
2708
2709 ASSERT(is_pae(vcpu));
2710 context->new_cr3 = paging_new_cr3;
2711 context->page_fault = paging64_page_fault;
2712 context->gva_to_gpa = paging64_gva_to_gpa;
2713 context->prefetch_page = paging64_prefetch_page;
2714 context->sync_page = paging64_sync_page;
2715 context->invlpg = paging64_invlpg;
2716 context->free = paging_free;
2717 context->root_level = level;
2718 context->shadow_root_level = level;
2719 context->root_hpa = INVALID_PAGE;
2720 context->direct_map = false;
2721 return 0;
2722 }
2723
2724 static int paging64_init_context(struct kvm_vcpu *vcpu,
2725 struct kvm_mmu *context)
2726 {
2727 return paging64_init_context_common(vcpu, context, PT64_ROOT_LEVEL);
2728 }
2729
2730 static int paging32_init_context(struct kvm_vcpu *vcpu,
2731 struct kvm_mmu *context)
2732 {
2733 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
2734
2735 context->new_cr3 = paging_new_cr3;
2736 context->page_fault = paging32_page_fault;
2737 context->gva_to_gpa = paging32_gva_to_gpa;
2738 context->free = paging_free;
2739 context->prefetch_page = paging32_prefetch_page;
2740 context->sync_page = paging32_sync_page;
2741 context->invlpg = paging32_invlpg;
2742 context->root_level = PT32_ROOT_LEVEL;
2743 context->shadow_root_level = PT32E_ROOT_LEVEL;
2744 context->root_hpa = INVALID_PAGE;
2745 context->direct_map = false;
2746 return 0;
2747 }
2748
2749 static int paging32E_init_context(struct kvm_vcpu *vcpu,
2750 struct kvm_mmu *context)
2751 {
2752 return paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
2753 }
2754
2755 static int init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
2756 {
2757 struct kvm_mmu *context = vcpu->arch.walk_mmu;
2758
2759 context->new_cr3 = nonpaging_new_cr3;
2760 context->page_fault = tdp_page_fault;
2761 context->free = nonpaging_free;
2762 context->prefetch_page = nonpaging_prefetch_page;
2763 context->sync_page = nonpaging_sync_page;
2764 context->invlpg = nonpaging_invlpg;
2765 context->shadow_root_level = kvm_x86_ops->get_tdp_level();
2766 context->root_hpa = INVALID_PAGE;
2767 context->direct_map = true;
2768 context->set_cr3 = kvm_x86_ops->set_tdp_cr3;
2769 context->get_cr3 = get_cr3;
2770 context->inject_page_fault = kvm_inject_page_fault;
2771
2772 if (!is_paging(vcpu)) {
2773 context->gva_to_gpa = nonpaging_gva_to_gpa;
2774 context->root_level = 0;
2775 } else if (is_long_mode(vcpu)) {
2776 reset_rsvds_bits_mask(vcpu, context, PT64_ROOT_LEVEL);
2777 context->gva_to_gpa = paging64_gva_to_gpa;
2778 context->root_level = PT64_ROOT_LEVEL;
2779 } else if (is_pae(vcpu)) {
2780 reset_rsvds_bits_mask(vcpu, context, PT32E_ROOT_LEVEL);
2781 context->gva_to_gpa = paging64_gva_to_gpa;
2782 context->root_level = PT32E_ROOT_LEVEL;
2783 } else {
2784 reset_rsvds_bits_mask(vcpu, context, PT32_ROOT_LEVEL);
2785 context->gva_to_gpa = paging32_gva_to_gpa;
2786 context->root_level = PT32_ROOT_LEVEL;
2787 }
2788
2789 return 0;
2790 }
2791
2792 int kvm_init_shadow_mmu(struct kvm_vcpu *vcpu, struct kvm_mmu *context)
2793 {
2794 int r;
2795 ASSERT(vcpu);
2796 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
2797
2798 if (!is_paging(vcpu))
2799 r = nonpaging_init_context(vcpu, context);
2800 else if (is_long_mode(vcpu))
2801 r = paging64_init_context(vcpu, context);
2802 else if (is_pae(vcpu))
2803 r = paging32E_init_context(vcpu, context);
2804 else
2805 r = paging32_init_context(vcpu, context);
2806
2807 vcpu->arch.mmu.base_role.cr4_pae = !!is_pae(vcpu);
2808 vcpu->arch.mmu.base_role.cr0_wp = is_write_protection(vcpu);
2809
2810 return r;
2811 }
2812 EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu);
2813
2814 static int init_kvm_softmmu(struct kvm_vcpu *vcpu)
2815 {
2816 int r = kvm_init_shadow_mmu(vcpu, vcpu->arch.walk_mmu);
2817
2818 vcpu->arch.walk_mmu->set_cr3 = kvm_x86_ops->set_cr3;
2819 vcpu->arch.walk_mmu->get_cr3 = get_cr3;
2820 vcpu->arch.walk_mmu->inject_page_fault = kvm_inject_page_fault;
2821
2822 return r;
2823 }
2824
2825 static int init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
2826 {
2827 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
2828
2829 g_context->get_cr3 = get_cr3;
2830 g_context->inject_page_fault = kvm_inject_page_fault;
2831
2832 /*
2833 * Note that arch.mmu.gva_to_gpa translates l2_gva to l1_gpa. The
2834 * translation of l2_gpa to l1_gpa addresses is done using the
2835 * arch.nested_mmu.gva_to_gpa function. Basically the gva_to_gpa
2836 * functions between mmu and nested_mmu are swapped.
2837 */
2838 if (!is_paging(vcpu)) {
2839 g_context->root_level = 0;
2840 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
2841 } else if (is_long_mode(vcpu)) {
2842 reset_rsvds_bits_mask(vcpu, g_context, PT64_ROOT_LEVEL);
2843 g_context->root_level = PT64_ROOT_LEVEL;
2844 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
2845 } else if (is_pae(vcpu)) {
2846 reset_rsvds_bits_mask(vcpu, g_context, PT32E_ROOT_LEVEL);
2847 g_context->root_level = PT32E_ROOT_LEVEL;
2848 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
2849 } else {
2850 reset_rsvds_bits_mask(vcpu, g_context, PT32_ROOT_LEVEL);
2851 g_context->root_level = PT32_ROOT_LEVEL;
2852 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
2853 }
2854
2855 return 0;
2856 }
2857
2858 static int init_kvm_mmu(struct kvm_vcpu *vcpu)
2859 {
2860 vcpu->arch.update_pte.pfn = bad_pfn;
2861
2862 if (mmu_is_nested(vcpu))
2863 return init_kvm_nested_mmu(vcpu);
2864 else if (tdp_enabled)
2865 return init_kvm_tdp_mmu(vcpu);
2866 else
2867 return init_kvm_softmmu(vcpu);
2868 }
2869
2870 static void destroy_kvm_mmu(struct kvm_vcpu *vcpu)
2871 {
2872 ASSERT(vcpu);
2873 if (VALID_PAGE(vcpu->arch.mmu.root_hpa))
2874 /* mmu.free() should set root_hpa = INVALID_PAGE */
2875 vcpu->arch.mmu.free(vcpu);
2876 }
2877
2878 int kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
2879 {
2880 destroy_kvm_mmu(vcpu);
2881 return init_kvm_mmu(vcpu);
2882 }
2883 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
2884
2885 int kvm_mmu_load(struct kvm_vcpu *vcpu)
2886 {
2887 int r;
2888
2889 r = mmu_topup_memory_caches(vcpu);
2890 if (r)
2891 goto out;
2892 r = mmu_alloc_roots(vcpu);
2893 spin_lock(&vcpu->kvm->mmu_lock);
2894 mmu_sync_roots(vcpu);
2895 spin_unlock(&vcpu->kvm->mmu_lock);
2896 if (r)
2897 goto out;
2898 /* set_cr3() should ensure TLB has been flushed */
2899 vcpu->arch.mmu.set_cr3(vcpu, vcpu->arch.mmu.root_hpa);
2900 out:
2901 return r;
2902 }
2903 EXPORT_SYMBOL_GPL(kvm_mmu_load);
2904
2905 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
2906 {
2907 mmu_free_roots(vcpu);
2908 }
2909
2910 static void mmu_pte_write_zap_pte(struct kvm_vcpu *vcpu,
2911 struct kvm_mmu_page *sp,
2912 u64 *spte)
2913 {
2914 u64 pte;
2915 struct kvm_mmu_page *child;
2916
2917 pte = *spte;
2918 if (is_shadow_present_pte(pte)) {
2919 if (is_last_spte(pte, sp->role.level))
2920 drop_spte(vcpu->kvm, spte, shadow_trap_nonpresent_pte);
2921 else {
2922 child = page_header(pte & PT64_BASE_ADDR_MASK);
2923 mmu_page_remove_parent_pte(child, spte);
2924 }
2925 }
2926 __set_spte(spte, shadow_trap_nonpresent_pte);
2927 if (is_large_pte(pte))
2928 --vcpu->kvm->stat.lpages;
2929 }
2930
2931 static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu,
2932 struct kvm_mmu_page *sp,
2933 u64 *spte,
2934 const void *new)
2935 {
2936 if (sp->role.level != PT_PAGE_TABLE_LEVEL) {
2937 ++vcpu->kvm->stat.mmu_pde_zapped;
2938 return;
2939 }
2940
2941 if (is_rsvd_bits_set(&vcpu->arch.mmu, *(u64 *)new, PT_PAGE_TABLE_LEVEL))
2942 return;
2943
2944 ++vcpu->kvm->stat.mmu_pte_updated;
2945 if (!sp->role.cr4_pae)
2946 paging32_update_pte(vcpu, sp, spte, new);
2947 else
2948 paging64_update_pte(vcpu, sp, spte, new);
2949 }
2950
2951 static bool need_remote_flush(u64 old, u64 new)
2952 {
2953 if (!is_shadow_present_pte(old))
2954 return false;
2955 if (!is_shadow_present_pte(new))
2956 return true;
2957 if ((old ^ new) & PT64_BASE_ADDR_MASK)
2958 return true;
2959 old ^= PT64_NX_MASK;
2960 new ^= PT64_NX_MASK;
2961 return (old & ~new & PT64_PERM_MASK) != 0;
2962 }
2963
2964 static void mmu_pte_write_flush_tlb(struct kvm_vcpu *vcpu, bool zap_page,
2965 bool remote_flush, bool local_flush)
2966 {
2967 if (zap_page)
2968 return;
2969
2970 if (remote_flush)
2971 kvm_flush_remote_tlbs(vcpu->kvm);
2972 else if (local_flush)
2973 kvm_mmu_flush_tlb(vcpu);
2974 }
2975
2976 static bool last_updated_pte_accessed(struct kvm_vcpu *vcpu)
2977 {
2978 u64 *spte = vcpu->arch.last_pte_updated;
2979
2980 return !!(spte && (*spte & shadow_accessed_mask));
2981 }
2982
2983 static void mmu_guess_page_from_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
2984 u64 gpte)
2985 {
2986 gfn_t gfn;
2987 pfn_t pfn;
2988
2989 if (!is_present_gpte(gpte))
2990 return;
2991 gfn = (gpte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT;
2992
2993 vcpu->arch.update_pte.mmu_seq = vcpu->kvm->mmu_notifier_seq;
2994 smp_rmb();
2995 pfn = gfn_to_pfn(vcpu->kvm, gfn);
2996
2997 if (is_error_pfn(pfn)) {
2998 kvm_release_pfn_clean(pfn);
2999 return;
3000 }
3001 vcpu->arch.update_pte.gfn = gfn;
3002 vcpu->arch.update_pte.pfn = pfn;
3003 }
3004
3005 static void kvm_mmu_access_page(struct kvm_vcpu *vcpu, gfn_t gfn)
3006 {
3007 u64 *spte = vcpu->arch.last_pte_updated;
3008
3009 if (spte
3010 && vcpu->arch.last_pte_gfn == gfn
3011 && shadow_accessed_mask
3012 && !(*spte & shadow_accessed_mask)
3013 && is_shadow_present_pte(*spte))
3014 set_bit(PT_ACCESSED_SHIFT, (unsigned long *)spte);
3015 }
3016
3017 void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
3018 const u8 *new, int bytes,
3019 bool guest_initiated)
3020 {
3021 gfn_t gfn = gpa >> PAGE_SHIFT;
3022 union kvm_mmu_page_role mask = { .word = 0 };
3023 struct kvm_mmu_page *sp;
3024 struct hlist_node *node;
3025 LIST_HEAD(invalid_list);
3026 u64 entry, gentry;
3027 u64 *spte;
3028 unsigned offset = offset_in_page(gpa);
3029 unsigned pte_size;
3030 unsigned page_offset;
3031 unsigned misaligned;
3032 unsigned quadrant;
3033 int level;
3034 int flooded = 0;
3035 int npte;
3036 int r;
3037 int invlpg_counter;
3038 bool remote_flush, local_flush, zap_page;
3039
3040 zap_page = remote_flush = local_flush = false;
3041
3042 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
3043
3044 invlpg_counter = atomic_read(&vcpu->kvm->arch.invlpg_counter);
3045
3046 /*
3047 * Assume that the pte write on a page table of the same type
3048 * as the current vcpu paging mode. This is nearly always true
3049 * (might be false while changing modes). Note it is verified later
3050 * by update_pte().
3051 */
3052 if ((is_pae(vcpu) && bytes == 4) || !new) {
3053 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
3054 if (is_pae(vcpu)) {
3055 gpa &= ~(gpa_t)7;
3056 bytes = 8;
3057 }
3058 r = kvm_read_guest(vcpu->kvm, gpa, &gentry, min(bytes, 8));
3059 if (r)
3060 gentry = 0;
3061 new = (const u8 *)&gentry;
3062 }
3063
3064 switch (bytes) {
3065 case 4:
3066 gentry = *(const u32 *)new;
3067 break;
3068 case 8:
3069 gentry = *(const u64 *)new;
3070 break;
3071 default:
3072 gentry = 0;
3073 break;
3074 }
3075
3076 mmu_guess_page_from_pte_write(vcpu, gpa, gentry);
3077 spin_lock(&vcpu->kvm->mmu_lock);
3078 if (atomic_read(&vcpu->kvm->arch.invlpg_counter) != invlpg_counter)
3079 gentry = 0;
3080 kvm_mmu_access_page(vcpu, gfn);
3081 kvm_mmu_free_some_pages(vcpu);
3082 ++vcpu->kvm->stat.mmu_pte_write;
3083 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
3084 if (guest_initiated) {
3085 if (gfn == vcpu->arch.last_pt_write_gfn
3086 && !last_updated_pte_accessed(vcpu)) {
3087 ++vcpu->arch.last_pt_write_count;
3088 if (vcpu->arch.last_pt_write_count >= 3)
3089 flooded = 1;
3090 } else {
3091 vcpu->arch.last_pt_write_gfn = gfn;
3092 vcpu->arch.last_pt_write_count = 1;
3093 vcpu->arch.last_pte_updated = NULL;
3094 }
3095 }
3096
3097 mask.cr0_wp = mask.cr4_pae = mask.nxe = 1;
3098 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn, node) {
3099 pte_size = sp->role.cr4_pae ? 8 : 4;
3100 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
3101 misaligned |= bytes < 4;
3102 if (misaligned || flooded) {
3103 /*
3104 * Misaligned accesses are too much trouble to fix
3105 * up; also, they usually indicate a page is not used
3106 * as a page table.
3107 *
3108 * If we're seeing too many writes to a page,
3109 * it may no longer be a page table, or we may be
3110 * forking, in which case it is better to unmap the
3111 * page.
3112 */
3113 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
3114 gpa, bytes, sp->role.word);
3115 zap_page |= !!kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
3116 &invalid_list);
3117 ++vcpu->kvm->stat.mmu_flooded;
3118 continue;
3119 }
3120 page_offset = offset;
3121 level = sp->role.level;
3122 npte = 1;
3123 if (!sp->role.cr4_pae) {
3124 page_offset <<= 1; /* 32->64 */
3125 /*
3126 * A 32-bit pde maps 4MB while the shadow pdes map
3127 * only 2MB. So we need to double the offset again
3128 * and zap two pdes instead of one.
3129 */
3130 if (level == PT32_ROOT_LEVEL) {
3131 page_offset &= ~7; /* kill rounding error */
3132 page_offset <<= 1;
3133 npte = 2;
3134 }
3135 quadrant = page_offset >> PAGE_SHIFT;
3136 page_offset &= ~PAGE_MASK;
3137 if (quadrant != sp->role.quadrant)
3138 continue;
3139 }
3140 local_flush = true;
3141 spte = &sp->spt[page_offset / sizeof(*spte)];
3142 while (npte--) {
3143 entry = *spte;
3144 mmu_pte_write_zap_pte(vcpu, sp, spte);
3145 if (gentry &&
3146 !((sp->role.word ^ vcpu->arch.mmu.base_role.word)
3147 & mask.word))
3148 mmu_pte_write_new_pte(vcpu, sp, spte, &gentry);
3149 if (!remote_flush && need_remote_flush(entry, *spte))
3150 remote_flush = true;
3151 ++spte;
3152 }
3153 }
3154 mmu_pte_write_flush_tlb(vcpu, zap_page, remote_flush, local_flush);
3155 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3156 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
3157 spin_unlock(&vcpu->kvm->mmu_lock);
3158 if (!is_error_pfn(vcpu->arch.update_pte.pfn)) {
3159 kvm_release_pfn_clean(vcpu->arch.update_pte.pfn);
3160 vcpu->arch.update_pte.pfn = bad_pfn;
3161 }
3162 }
3163
3164 int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
3165 {
3166 gpa_t gpa;
3167 int r;
3168
3169 if (vcpu->arch.mmu.direct_map)
3170 return 0;
3171
3172 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
3173
3174 spin_lock(&vcpu->kvm->mmu_lock);
3175 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
3176 spin_unlock(&vcpu->kvm->mmu_lock);
3177 return r;
3178 }
3179 EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt);
3180
3181 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu)
3182 {
3183 LIST_HEAD(invalid_list);
3184
3185 while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES &&
3186 !list_empty(&vcpu->kvm->arch.active_mmu_pages)) {
3187 struct kvm_mmu_page *sp;
3188
3189 sp = container_of(vcpu->kvm->arch.active_mmu_pages.prev,
3190 struct kvm_mmu_page, link);
3191 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
3192 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
3193 ++vcpu->kvm->stat.mmu_recycled;
3194 }
3195 }
3196
3197 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u32 error_code)
3198 {
3199 int r;
3200 enum emulation_result er;
3201
3202 r = vcpu->arch.mmu.page_fault(vcpu, cr2, error_code);
3203 if (r < 0)
3204 goto out;
3205
3206 if (!r) {
3207 r = 1;
3208 goto out;
3209 }
3210
3211 r = mmu_topup_memory_caches(vcpu);
3212 if (r)
3213 goto out;
3214
3215 er = emulate_instruction(vcpu, cr2, error_code, 0);
3216
3217 switch (er) {
3218 case EMULATE_DONE:
3219 return 1;
3220 case EMULATE_DO_MMIO:
3221 ++vcpu->stat.mmio_exits;
3222 /* fall through */
3223 case EMULATE_FAIL:
3224 return 0;
3225 default:
3226 BUG();
3227 }
3228 out:
3229 return r;
3230 }
3231 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
3232
3233 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
3234 {
3235 vcpu->arch.mmu.invlpg(vcpu, gva);
3236 kvm_mmu_flush_tlb(vcpu);
3237 ++vcpu->stat.invlpg;
3238 }
3239 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
3240
3241 void kvm_enable_tdp(void)
3242 {
3243 tdp_enabled = true;
3244 }
3245 EXPORT_SYMBOL_GPL(kvm_enable_tdp);
3246
3247 void kvm_disable_tdp(void)
3248 {
3249 tdp_enabled = false;
3250 }
3251 EXPORT_SYMBOL_GPL(kvm_disable_tdp);
3252
3253 static void free_mmu_pages(struct kvm_vcpu *vcpu)
3254 {
3255 free_page((unsigned long)vcpu->arch.mmu.pae_root);
3256 }
3257
3258 static int alloc_mmu_pages(struct kvm_vcpu *vcpu)
3259 {
3260 struct page *page;
3261 int i;
3262
3263 ASSERT(vcpu);
3264
3265 /*
3266 * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64.
3267 * Therefore we need to allocate shadow page tables in the first
3268 * 4GB of memory, which happens to fit the DMA32 zone.
3269 */
3270 page = alloc_page(GFP_KERNEL | __GFP_DMA32);
3271 if (!page)
3272 return -ENOMEM;
3273
3274 vcpu->arch.mmu.pae_root = page_address(page);
3275 for (i = 0; i < 4; ++i)
3276 vcpu->arch.mmu.pae_root[i] = INVALID_PAGE;
3277
3278 return 0;
3279 }
3280
3281 int kvm_mmu_create(struct kvm_vcpu *vcpu)
3282 {
3283 ASSERT(vcpu);
3284 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3285
3286 return alloc_mmu_pages(vcpu);
3287 }
3288
3289 int kvm_mmu_setup(struct kvm_vcpu *vcpu)
3290 {
3291 ASSERT(vcpu);
3292 ASSERT(!VALID_PAGE(vcpu->arch.mmu.root_hpa));
3293
3294 return init_kvm_mmu(vcpu);
3295 }
3296
3297 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
3298 {
3299 ASSERT(vcpu);
3300
3301 destroy_kvm_mmu(vcpu);
3302 free_mmu_pages(vcpu);
3303 mmu_free_memory_caches(vcpu);
3304 }
3305
3306 void kvm_mmu_slot_remove_write_access(struct kvm *kvm, int slot)
3307 {
3308 struct kvm_mmu_page *sp;
3309
3310 list_for_each_entry(sp, &kvm->arch.active_mmu_pages, link) {
3311 int i;
3312 u64 *pt;
3313
3314 if (!test_bit(slot, sp->slot_bitmap))
3315 continue;
3316
3317 pt = sp->spt;
3318 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
3319 /* avoid RMW */
3320 if (is_writable_pte(pt[i]))
3321 pt[i] &= ~PT_WRITABLE_MASK;
3322 }
3323 kvm_flush_remote_tlbs(kvm);
3324 }
3325
3326 void kvm_mmu_zap_all(struct kvm *kvm)
3327 {
3328 struct kvm_mmu_page *sp, *node;
3329 LIST_HEAD(invalid_list);
3330
3331 spin_lock(&kvm->mmu_lock);
3332 restart:
3333 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link)
3334 if (kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list))
3335 goto restart;
3336
3337 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3338 spin_unlock(&kvm->mmu_lock);
3339 }
3340
3341 static int kvm_mmu_remove_some_alloc_mmu_pages(struct kvm *kvm,
3342 struct list_head *invalid_list)
3343 {
3344 struct kvm_mmu_page *page;
3345
3346 page = container_of(kvm->arch.active_mmu_pages.prev,
3347 struct kvm_mmu_page, link);
3348 return kvm_mmu_prepare_zap_page(kvm, page, invalid_list);
3349 }
3350
3351 static int mmu_shrink(struct shrinker *shrink, int nr_to_scan, gfp_t gfp_mask)
3352 {
3353 struct kvm *kvm;
3354 struct kvm *kvm_freed = NULL;
3355
3356 if (nr_to_scan == 0)
3357 goto out;
3358
3359 spin_lock(&kvm_lock);
3360
3361 list_for_each_entry(kvm, &vm_list, vm_list) {
3362 int idx, freed_pages;
3363 LIST_HEAD(invalid_list);
3364
3365 idx = srcu_read_lock(&kvm->srcu);
3366 spin_lock(&kvm->mmu_lock);
3367 if (!kvm_freed && nr_to_scan > 0 &&
3368 kvm->arch.n_used_mmu_pages > 0) {
3369 freed_pages = kvm_mmu_remove_some_alloc_mmu_pages(kvm,
3370 &invalid_list);
3371 kvm_freed = kvm;
3372 }
3373 nr_to_scan--;
3374
3375 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3376 spin_unlock(&kvm->mmu_lock);
3377 srcu_read_unlock(&kvm->srcu, idx);
3378 }
3379 if (kvm_freed)
3380 list_move_tail(&kvm_freed->vm_list, &vm_list);
3381
3382 spin_unlock(&kvm_lock);
3383
3384 out:
3385 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
3386 }
3387
3388 static struct shrinker mmu_shrinker = {
3389 .shrink = mmu_shrink,
3390 .seeks = DEFAULT_SEEKS * 10,
3391 };
3392
3393 static void mmu_destroy_caches(void)
3394 {
3395 if (pte_chain_cache)
3396 kmem_cache_destroy(pte_chain_cache);
3397 if (rmap_desc_cache)
3398 kmem_cache_destroy(rmap_desc_cache);
3399 if (mmu_page_header_cache)
3400 kmem_cache_destroy(mmu_page_header_cache);
3401 }
3402
3403 void kvm_mmu_module_exit(void)
3404 {
3405 mmu_destroy_caches();
3406 percpu_counter_destroy(&kvm_total_used_mmu_pages);
3407 unregister_shrinker(&mmu_shrinker);
3408 }
3409
3410 int kvm_mmu_module_init(void)
3411 {
3412 pte_chain_cache = kmem_cache_create("kvm_pte_chain",
3413 sizeof(struct kvm_pte_chain),
3414 0, 0, NULL);
3415 if (!pte_chain_cache)
3416 goto nomem;
3417 rmap_desc_cache = kmem_cache_create("kvm_rmap_desc",
3418 sizeof(struct kvm_rmap_desc),
3419 0, 0, NULL);
3420 if (!rmap_desc_cache)
3421 goto nomem;
3422
3423 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
3424 sizeof(struct kvm_mmu_page),
3425 0, 0, NULL);
3426 if (!mmu_page_header_cache)
3427 goto nomem;
3428
3429 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0))
3430 goto nomem;
3431
3432 register_shrinker(&mmu_shrinker);
3433
3434 return 0;
3435
3436 nomem:
3437 mmu_destroy_caches();
3438 return -ENOMEM;
3439 }
3440
3441 /*
3442 * Caculate mmu pages needed for kvm.
3443 */
3444 unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm)
3445 {
3446 int i;
3447 unsigned int nr_mmu_pages;
3448 unsigned int nr_pages = 0;
3449 struct kvm_memslots *slots;
3450
3451 slots = kvm_memslots(kvm);
3452
3453 for (i = 0; i < slots->nmemslots; i++)
3454 nr_pages += slots->memslots[i].npages;
3455
3456 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
3457 nr_mmu_pages = max(nr_mmu_pages,
3458 (unsigned int) KVM_MIN_ALLOC_MMU_PAGES);
3459
3460 return nr_mmu_pages;
3461 }
3462
3463 static void *pv_mmu_peek_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3464 unsigned len)
3465 {
3466 if (len > buffer->len)
3467 return NULL;
3468 return buffer->ptr;
3469 }
3470
3471 static void *pv_mmu_read_buffer(struct kvm_pv_mmu_op_buffer *buffer,
3472 unsigned len)
3473 {
3474 void *ret;
3475
3476 ret = pv_mmu_peek_buffer(buffer, len);
3477 if (!ret)
3478 return ret;
3479 buffer->ptr += len;
3480 buffer->len -= len;
3481 buffer->processed += len;
3482 return ret;
3483 }
3484
3485 static int kvm_pv_mmu_write(struct kvm_vcpu *vcpu,
3486 gpa_t addr, gpa_t value)
3487 {
3488 int bytes = 8;
3489 int r;
3490
3491 if (!is_long_mode(vcpu) && !is_pae(vcpu))
3492 bytes = 4;
3493
3494 r = mmu_topup_memory_caches(vcpu);
3495 if (r)
3496 return r;
3497
3498 if (!emulator_write_phys(vcpu, addr, &value, bytes))
3499 return -EFAULT;
3500
3501 return 1;
3502 }
3503
3504 static int kvm_pv_mmu_flush_tlb(struct kvm_vcpu *vcpu)
3505 {
3506 (void)kvm_set_cr3(vcpu, vcpu->arch.cr3);
3507 return 1;
3508 }
3509
3510 static int kvm_pv_mmu_release_pt(struct kvm_vcpu *vcpu, gpa_t addr)
3511 {
3512 spin_lock(&vcpu->kvm->mmu_lock);
3513 mmu_unshadow(vcpu->kvm, addr >> PAGE_SHIFT);
3514 spin_unlock(&vcpu->kvm->mmu_lock);
3515 return 1;
3516 }
3517
3518 static int kvm_pv_mmu_op_one(struct kvm_vcpu *vcpu,
3519 struct kvm_pv_mmu_op_buffer *buffer)
3520 {
3521 struct kvm_mmu_op_header *header;
3522
3523 header = pv_mmu_peek_buffer(buffer, sizeof *header);
3524 if (!header)
3525 return 0;
3526 switch (header->op) {
3527 case KVM_MMU_OP_WRITE_PTE: {
3528 struct kvm_mmu_op_write_pte *wpte;
3529
3530 wpte = pv_mmu_read_buffer(buffer, sizeof *wpte);
3531 if (!wpte)
3532 return 0;
3533 return kvm_pv_mmu_write(vcpu, wpte->pte_phys,
3534 wpte->pte_val);
3535 }
3536 case KVM_MMU_OP_FLUSH_TLB: {
3537 struct kvm_mmu_op_flush_tlb *ftlb;
3538
3539 ftlb = pv_mmu_read_buffer(buffer, sizeof *ftlb);
3540 if (!ftlb)
3541 return 0;
3542 return kvm_pv_mmu_flush_tlb(vcpu);
3543 }
3544 case KVM_MMU_OP_RELEASE_PT: {
3545 struct kvm_mmu_op_release_pt *rpt;
3546
3547 rpt = pv_mmu_read_buffer(buffer, sizeof *rpt);
3548 if (!rpt)
3549 return 0;
3550 return kvm_pv_mmu_release_pt(vcpu, rpt->pt_phys);
3551 }
3552 default: return 0;
3553 }
3554 }
3555
3556 int kvm_pv_mmu_op(struct kvm_vcpu *vcpu, unsigned long bytes,
3557 gpa_t addr, unsigned long *ret)
3558 {
3559 int r;
3560 struct kvm_pv_mmu_op_buffer *buffer = &vcpu->arch.mmu_op_buffer;
3561
3562 buffer->ptr = buffer->buf;
3563 buffer->len = min_t(unsigned long, bytes, sizeof buffer->buf);
3564 buffer->processed = 0;
3565
3566 r = kvm_read_guest(vcpu->kvm, addr, buffer->buf, buffer->len);
3567 if (r)
3568 goto out;
3569
3570 while (buffer->len) {
3571 r = kvm_pv_mmu_op_one(vcpu, buffer);
3572 if (r < 0)
3573 goto out;
3574 if (r == 0)
3575 break;
3576 }
3577
3578 r = 1;
3579 out:
3580 *ret = buffer->processed;
3581 return r;
3582 }
3583
3584 int kvm_mmu_get_spte_hierarchy(struct kvm_vcpu *vcpu, u64 addr, u64 sptes[4])
3585 {
3586 struct kvm_shadow_walk_iterator iterator;
3587 int nr_sptes = 0;
3588
3589 spin_lock(&vcpu->kvm->mmu_lock);
3590 for_each_shadow_entry(vcpu, addr, iterator) {
3591 sptes[iterator.level-1] = *iterator.sptep;
3592 nr_sptes++;
3593 if (!is_shadow_present_pte(*iterator.sptep))
3594 break;
3595 }
3596 spin_unlock(&vcpu->kvm->mmu_lock);
3597
3598 return nr_sptes;
3599 }
3600 EXPORT_SYMBOL_GPL(kvm_mmu_get_spte_hierarchy);
3601
3602 #ifdef CONFIG_KVM_MMU_AUDIT
3603 #include "mmu_audit.c"
3604 #endif
(deprecated) Btrfs devel tree