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iwlwifi: pcie: give a meaningful name to interrupt request
[linux-2.6/btrfs-unstable.git] / drivers / pci / setup-bus.c
blobc74059e10a6de9d1afe89cea272c4146bc183e68
1 /*
2 * drivers/pci/setup-bus.c
3 *
4 * Extruded from code written by
5 * Dave Rusling (david.rusling@reo.mts.dec.com)
6 * David Mosberger (davidm@cs.arizona.edu)
7 * David Miller (davem@redhat.com)
8 *
9 * Support routines for initializing a PCI subsystem.
10 */
11
12 /*
13 * Nov 2000, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
14 * PCI-PCI bridges cleanup, sorted resource allocation.
15 * Feb 2002, Ivan Kokshaysky <ink@jurassic.park.msu.ru>
16 * Converted to allocation in 3 passes, which gives
17 * tighter packing. Prefetchable range support.
18 */
19
20 #include <linux/init.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/pci.h>
24 #include <linux/errno.h>
25 #include <linux/ioport.h>
26 #include <linux/cache.h>
27 #include <linux/slab.h>
28 #include "pci.h"
29
30 unsigned int pci_flags;
31
32 struct pci_dev_resource {
33 struct list_head list;
34 struct resource *res;
35 struct pci_dev *dev;
36 resource_size_t start;
37 resource_size_t end;
38 resource_size_t add_size;
39 resource_size_t min_align;
40 unsigned long flags;
41 };
42
43 static void free_list(struct list_head *head)
44 {
45 struct pci_dev_resource *dev_res, *tmp;
46
47 list_for_each_entry_safe(dev_res, tmp, head, list) {
48 list_del(&dev_res->list);
49 kfree(dev_res);
50 }
51 }
52
53 /**
54 * add_to_list() - add a new resource tracker to the list
55 * @head: Head of the list
56 * @dev: device corresponding to which the resource
57 * belongs
58 * @res: The resource to be tracked
59 * @add_size: additional size to be optionally added
60 * to the resource
61 */
62 static int add_to_list(struct list_head *head,
63 struct pci_dev *dev, struct resource *res,
64 resource_size_t add_size, resource_size_t min_align)
65 {
66 struct pci_dev_resource *tmp;
67
68 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
69 if (!tmp) {
70 pr_warn("add_to_list: kmalloc() failed!\n");
71 return -ENOMEM;
72 }
73
74 tmp->res = res;
75 tmp->dev = dev;
76 tmp->start = res->start;
77 tmp->end = res->end;
78 tmp->flags = res->flags;
79 tmp->add_size = add_size;
80 tmp->min_align = min_align;
81
82 list_add(&tmp->list, head);
83
84 return 0;
85 }
86
87 static void remove_from_list(struct list_head *head,
88 struct resource *res)
89 {
90 struct pci_dev_resource *dev_res, *tmp;
91
92 list_for_each_entry_safe(dev_res, tmp, head, list) {
93 if (dev_res->res == res) {
94 list_del(&dev_res->list);
95 kfree(dev_res);
96 break;
97 }
98 }
99 }
100
101 static struct pci_dev_resource *res_to_dev_res(struct list_head *head,
102 struct resource *res)
103 {
104 struct pci_dev_resource *dev_res;
105
106 list_for_each_entry(dev_res, head, list) {
107 if (dev_res->res == res) {
108 int idx = res - &dev_res->dev->resource[0];
109
110 dev_printk(KERN_DEBUG, &dev_res->dev->dev,
111 "res[%d]=%pR res_to_dev_res add_size %llx min_align %llx\n",
112 idx, dev_res->res,
113 (unsigned long long)dev_res->add_size,
114 (unsigned long long)dev_res->min_align);
115
116 return dev_res;
117 }
118 }
119
120 return NULL;
121 }
122
123 static resource_size_t get_res_add_size(struct list_head *head,
124 struct resource *res)
125 {
126 struct pci_dev_resource *dev_res;
127
128 dev_res = res_to_dev_res(head, res);
129 return dev_res ? dev_res->add_size : 0;
130 }
131
132 static resource_size_t get_res_add_align(struct list_head *head,
133 struct resource *res)
134 {
135 struct pci_dev_resource *dev_res;
136
137 dev_res = res_to_dev_res(head, res);
138 return dev_res ? dev_res->min_align : 0;
139 }
140
141
142 /* Sort resources by alignment */
143 static void pdev_sort_resources(struct pci_dev *dev, struct list_head *head)
144 {
145 int i;
146
147 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
148 struct resource *r;
149 struct pci_dev_resource *dev_res, *tmp;
150 resource_size_t r_align;
151 struct list_head *n;
152
153 r = &dev->resource[i];
154
155 if (r->flags & IORESOURCE_PCI_FIXED)
156 continue;
157
158 if (!(r->flags) || r->parent)
159 continue;
160
161 r_align = pci_resource_alignment(dev, r);
162 if (!r_align) {
163 dev_warn(&dev->dev, "BAR %d: %pR has bogus alignment\n",
164 i, r);
165 continue;
166 }
167
168 tmp = kzalloc(sizeof(*tmp), GFP_KERNEL);
169 if (!tmp)
170 panic("pdev_sort_resources(): kmalloc() failed!\n");
171 tmp->res = r;
172 tmp->dev = dev;
173
174 /* fallback is smallest one or list is empty*/
175 n = head;
176 list_for_each_entry(dev_res, head, list) {
177 resource_size_t align;
178
179 align = pci_resource_alignment(dev_res->dev,
180 dev_res->res);
181
182 if (r_align > align) {
183 n = &dev_res->list;
184 break;
185 }
186 }
187 /* Insert it just before n*/
188 list_add_tail(&tmp->list, n);
189 }
190 }
191
192 static void __dev_sort_resources(struct pci_dev *dev,
193 struct list_head *head)
194 {
195 u16 class = dev->class >> 8;
196
197 /* Don't touch classless devices or host bridges or ioapics. */
198 if (class == PCI_CLASS_NOT_DEFINED || class == PCI_CLASS_BRIDGE_HOST)
199 return;
200
201 /* Don't touch ioapic devices already enabled by firmware */
202 if (class == PCI_CLASS_SYSTEM_PIC) {
203 u16 command;
204 pci_read_config_word(dev, PCI_COMMAND, &command);
205 if (command & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY))
206 return;
207 }
208
209 pdev_sort_resources(dev, head);
210 }
211
212 static inline void reset_resource(struct resource *res)
213 {
214 res->start = 0;
215 res->end = 0;
216 res->flags = 0;
217 }
218
219 /**
220 * reassign_resources_sorted() - satisfy any additional resource requests
221 *
222 * @realloc_head : head of the list tracking requests requiring additional
223 * resources
224 * @head : head of the list tracking requests with allocated
225 * resources
226 *
227 * Walk through each element of the realloc_head and try to procure
228 * additional resources for the element, provided the element
229 * is in the head list.
230 */
231 static void reassign_resources_sorted(struct list_head *realloc_head,
232 struct list_head *head)
233 {
234 struct resource *res;
235 struct pci_dev_resource *add_res, *tmp;
236 struct pci_dev_resource *dev_res;
237 resource_size_t add_size, align;
238 int idx;
239
240 list_for_each_entry_safe(add_res, tmp, realloc_head, list) {
241 bool found_match = false;
242
243 res = add_res->res;
244 /* skip resource that has been reset */
245 if (!res->flags)
246 goto out;
247
248 /* skip this resource if not found in head list */
249 list_for_each_entry(dev_res, head, list) {
250 if (dev_res->res == res) {
251 found_match = true;
252 break;
253 }
254 }
255 if (!found_match)/* just skip */
256 continue;
257
258 idx = res - &add_res->dev->resource[0];
259 add_size = add_res->add_size;
260 align = add_res->min_align;
261 if (!resource_size(res)) {
262 res->start = align;
263 res->end = res->start + add_size - 1;
264 if (pci_assign_resource(add_res->dev, idx))
265 reset_resource(res);
266 } else {
267 res->flags |= add_res->flags &
268 (IORESOURCE_STARTALIGN|IORESOURCE_SIZEALIGN);
269 if (pci_reassign_resource(add_res->dev, idx,
270 add_size, align))
271 dev_printk(KERN_DEBUG, &add_res->dev->dev,
272 "failed to add %llx res[%d]=%pR\n",
273 (unsigned long long)add_size,
274 idx, res);
275 }
276 out:
277 list_del(&add_res->list);
278 kfree(add_res);
279 }
280 }
281
282 /**
283 * assign_requested_resources_sorted() - satisfy resource requests
284 *
285 * @head : head of the list tracking requests for resources
286 * @fail_head : head of the list tracking requests that could
287 * not be allocated
288 *
289 * Satisfy resource requests of each element in the list. Add
290 * requests that could not satisfied to the failed_list.
291 */
292 static void assign_requested_resources_sorted(struct list_head *head,
293 struct list_head *fail_head)
294 {
295 struct resource *res;
296 struct pci_dev_resource *dev_res;
297 int idx;
298
299 list_for_each_entry(dev_res, head, list) {
300 res = dev_res->res;
301 idx = res - &dev_res->dev->resource[0];
302 if (resource_size(res) &&
303 pci_assign_resource(dev_res->dev, idx)) {
304 if (fail_head) {
305 /*
306 * if the failed res is for ROM BAR, and it will
307 * be enabled later, don't add it to the list
308 */
309 if (!((idx == PCI_ROM_RESOURCE) &&
310 (!(res->flags & IORESOURCE_ROM_ENABLE))))
311 add_to_list(fail_head,
312 dev_res->dev, res,
313 0 /* don't care */,
314 0 /* don't care */);
315 }
316 reset_resource(res);
317 }
318 }
319 }
320
321 static unsigned long pci_fail_res_type_mask(struct list_head *fail_head)
322 {
323 struct pci_dev_resource *fail_res;
324 unsigned long mask = 0;
325
326 /* check failed type */
327 list_for_each_entry(fail_res, fail_head, list)
328 mask |= fail_res->flags;
329
330 /*
331 * one pref failed resource will set IORESOURCE_MEM,
332 * as we can allocate pref in non-pref range.
333 * Will release all assigned non-pref sibling resources
334 * according to that bit.
335 */
336 return mask & (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_PREFETCH);
337 }
338
339 static bool pci_need_to_release(unsigned long mask, struct resource *res)
340 {
341 if (res->flags & IORESOURCE_IO)
342 return !!(mask & IORESOURCE_IO);
343
344 /* check pref at first */
345 if (res->flags & IORESOURCE_PREFETCH) {
346 if (mask & IORESOURCE_PREFETCH)
347 return true;
348 /* count pref if its parent is non-pref */
349 else if ((mask & IORESOURCE_MEM) &&
350 !(res->parent->flags & IORESOURCE_PREFETCH))
351 return true;
352 else
353 return false;
354 }
355
356 if (res->flags & IORESOURCE_MEM)
357 return !!(mask & IORESOURCE_MEM);
358
359 return false; /* should not get here */
360 }
361
362 static void __assign_resources_sorted(struct list_head *head,
363 struct list_head *realloc_head,
364 struct list_head *fail_head)
365 {
366 /*
367 * Should not assign requested resources at first.
368 * they could be adjacent, so later reassign can not reallocate
369 * them one by one in parent resource window.
370 * Try to assign requested + add_size at beginning
371 * if could do that, could get out early.
372 * if could not do that, we still try to assign requested at first,
373 * then try to reassign add_size for some resources.
374 *
375 * Separate three resource type checking if we need to release
376 * assigned resource after requested + add_size try.
377 * 1. if there is io port assign fail, will release assigned
378 * io port.
379 * 2. if there is pref mmio assign fail, release assigned
380 * pref mmio.
381 * if assigned pref mmio's parent is non-pref mmio and there
382 * is non-pref mmio assign fail, will release that assigned
383 * pref mmio.
384 * 3. if there is non-pref mmio assign fail or pref mmio
385 * assigned fail, will release assigned non-pref mmio.
386 */
387 LIST_HEAD(save_head);
388 LIST_HEAD(local_fail_head);
389 struct pci_dev_resource *save_res;
390 struct pci_dev_resource *dev_res, *tmp_res, *dev_res2;
391 unsigned long fail_type;
392 resource_size_t add_align, align;
393
394 /* Check if optional add_size is there */
395 if (!realloc_head || list_empty(realloc_head))
396 goto requested_and_reassign;
397
398 /* Save original start, end, flags etc at first */
399 list_for_each_entry(dev_res, head, list) {
400 if (add_to_list(&save_head, dev_res->dev, dev_res->res, 0, 0)) {
401 free_list(&save_head);
402 goto requested_and_reassign;
403 }
404 }
405
406 /* Update res in head list with add_size in realloc_head list */
407 list_for_each_entry_safe(dev_res, tmp_res, head, list) {
408 dev_res->res->end += get_res_add_size(realloc_head,
409 dev_res->res);
410
411 /*
412 * There are two kinds of additional resources in the list:
413 * 1. bridge resource -- IORESOURCE_STARTALIGN
414 * 2. SR-IOV resource -- IORESOURCE_SIZEALIGN
415 * Here just fix the additional alignment for bridge
416 */
417 if (!(dev_res->res->flags & IORESOURCE_STARTALIGN))
418 continue;
419
420 add_align = get_res_add_align(realloc_head, dev_res->res);
421
422 /*
423 * The "head" list is sorted by the alignment to make sure
424 * resources with bigger alignment will be assigned first.
425 * After we change the alignment of a dev_res in "head" list,
426 * we need to reorder the list by alignment to make it
427 * consistent.
428 */
429 if (add_align > dev_res->res->start) {
430 resource_size_t r_size = resource_size(dev_res->res);
431
432 dev_res->res->start = add_align;
433 dev_res->res->end = add_align + r_size - 1;
434
435 list_for_each_entry(dev_res2, head, list) {
436 align = pci_resource_alignment(dev_res2->dev,
437 dev_res2->res);
438 if (add_align > align) {
439 list_move_tail(&dev_res->list,
440 &dev_res2->list);
441 break;
442 }
443 }
444 }
445
446 }
447
448 /* Try updated head list with add_size added */
449 assign_requested_resources_sorted(head, &local_fail_head);
450
451 /* all assigned with add_size ? */
452 if (list_empty(&local_fail_head)) {
453 /* Remove head list from realloc_head list */
454 list_for_each_entry(dev_res, head, list)
455 remove_from_list(realloc_head, dev_res->res);
456 free_list(&save_head);
457 free_list(head);
458 return;
459 }
460
461 /* check failed type */
462 fail_type = pci_fail_res_type_mask(&local_fail_head);
463 /* remove not need to be released assigned res from head list etc */
464 list_for_each_entry_safe(dev_res, tmp_res, head, list)
465 if (dev_res->res->parent &&
466 !pci_need_to_release(fail_type, dev_res->res)) {
467 /* remove it from realloc_head list */
468 remove_from_list(realloc_head, dev_res->res);
469 remove_from_list(&save_head, dev_res->res);
470 list_del(&dev_res->list);
471 kfree(dev_res);
472 }
473
474 free_list(&local_fail_head);
475 /* Release assigned resource */
476 list_for_each_entry(dev_res, head, list)
477 if (dev_res->res->parent)
478 release_resource(dev_res->res);
479 /* Restore start/end/flags from saved list */
480 list_for_each_entry(save_res, &save_head, list) {
481 struct resource *res = save_res->res;
482
483 res->start = save_res->start;
484 res->end = save_res->end;
485 res->flags = save_res->flags;
486 }
487 free_list(&save_head);
488
489 requested_and_reassign:
490 /* Satisfy the must-have resource requests */
491 assign_requested_resources_sorted(head, fail_head);
492
493 /* Try to satisfy any additional optional resource
494 requests */
495 if (realloc_head)
496 reassign_resources_sorted(realloc_head, head);
497 free_list(head);
498 }
499
500 static void pdev_assign_resources_sorted(struct pci_dev *dev,
501 struct list_head *add_head,
502 struct list_head *fail_head)
503 {
504 LIST_HEAD(head);
505
506 __dev_sort_resources(dev, &head);
507 __assign_resources_sorted(&head, add_head, fail_head);
508
509 }
510
511 static void pbus_assign_resources_sorted(const struct pci_bus *bus,
512 struct list_head *realloc_head,
513 struct list_head *fail_head)
514 {
515 struct pci_dev *dev;
516 LIST_HEAD(head);
517
518 list_for_each_entry(dev, &bus->devices, bus_list)
519 __dev_sort_resources(dev, &head);
520
521 __assign_resources_sorted(&head, realloc_head, fail_head);
522 }
523
524 void pci_setup_cardbus(struct pci_bus *bus)
525 {
526 struct pci_dev *bridge = bus->self;
527 struct resource *res;
528 struct pci_bus_region region;
529
530 dev_info(&bridge->dev, "CardBus bridge to %pR\n",
531 &bus->busn_res);
532
533 res = bus->resource[0];
534 pcibios_resource_to_bus(bridge->bus, &region, res);
535 if (res->flags & IORESOURCE_IO) {
536 /*
537 * The IO resource is allocated a range twice as large as it
538 * would normally need. This allows us to set both IO regs.
539 */
540 dev_info(&bridge->dev, " bridge window %pR\n", res);
541 pci_write_config_dword(bridge, PCI_CB_IO_BASE_0,
542 region.start);
543 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_0,
544 region.end);
545 }
546
547 res = bus->resource[1];
548 pcibios_resource_to_bus(bridge->bus, &region, res);
549 if (res->flags & IORESOURCE_IO) {
550 dev_info(&bridge->dev, " bridge window %pR\n", res);
551 pci_write_config_dword(bridge, PCI_CB_IO_BASE_1,
552 region.start);
553 pci_write_config_dword(bridge, PCI_CB_IO_LIMIT_1,
554 region.end);
555 }
556
557 res = bus->resource[2];
558 pcibios_resource_to_bus(bridge->bus, &region, res);
559 if (res->flags & IORESOURCE_MEM) {
560 dev_info(&bridge->dev, " bridge window %pR\n", res);
561 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_0,
562 region.start);
563 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_0,
564 region.end);
565 }
566
567 res = bus->resource[3];
568 pcibios_resource_to_bus(bridge->bus, &region, res);
569 if (res->flags & IORESOURCE_MEM) {
570 dev_info(&bridge->dev, " bridge window %pR\n", res);
571 pci_write_config_dword(bridge, PCI_CB_MEMORY_BASE_1,
572 region.start);
573 pci_write_config_dword(bridge, PCI_CB_MEMORY_LIMIT_1,
574 region.end);
575 }
576 }
577 EXPORT_SYMBOL(pci_setup_cardbus);
578
579 /* Initialize bridges with base/limit values we have collected.
580 PCI-to-PCI Bridge Architecture Specification rev. 1.1 (1998)
581 requires that if there is no I/O ports or memory behind the
582 bridge, corresponding range must be turned off by writing base
583 value greater than limit to the bridge's base/limit registers.
584
585 Note: care must be taken when updating I/O base/limit registers
586 of bridges which support 32-bit I/O. This update requires two
587 config space writes, so it's quite possible that an I/O window of
588 the bridge will have some undesirable address (e.g. 0) after the
589 first write. Ditto 64-bit prefetchable MMIO. */
590 static void pci_setup_bridge_io(struct pci_dev *bridge)
591 {
592 struct resource *res;
593 struct pci_bus_region region;
594 unsigned long io_mask;
595 u8 io_base_lo, io_limit_lo;
596 u16 l;
597 u32 io_upper16;
598
599 io_mask = PCI_IO_RANGE_MASK;
600 if (bridge->io_window_1k)
601 io_mask = PCI_IO_1K_RANGE_MASK;
602
603 /* Set up the top and bottom of the PCI I/O segment for this bus. */
604 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 0];
605 pcibios_resource_to_bus(bridge->bus, &region, res);
606 if (res->flags & IORESOURCE_IO) {
607 pci_read_config_word(bridge, PCI_IO_BASE, &l);
608 io_base_lo = (region.start >> 8) & io_mask;
609 io_limit_lo = (region.end >> 8) & io_mask;
610 l = ((u16) io_limit_lo << 8) | io_base_lo;
611 /* Set up upper 16 bits of I/O base/limit. */
612 io_upper16 = (region.end & 0xffff0000) | (region.start >> 16);
613 dev_info(&bridge->dev, " bridge window %pR\n", res);
614 } else {
615 /* Clear upper 16 bits of I/O base/limit. */
616 io_upper16 = 0;
617 l = 0x00f0;
618 }
619 /* Temporarily disable the I/O range before updating PCI_IO_BASE. */
620 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, 0x0000ffff);
621 /* Update lower 16 bits of I/O base/limit. */
622 pci_write_config_word(bridge, PCI_IO_BASE, l);
623 /* Update upper 16 bits of I/O base/limit. */
624 pci_write_config_dword(bridge, PCI_IO_BASE_UPPER16, io_upper16);
625 }
626
627 static void pci_setup_bridge_mmio(struct pci_dev *bridge)
628 {
629 struct resource *res;
630 struct pci_bus_region region;
631 u32 l;
632
633 /* Set up the top and bottom of the PCI Memory segment for this bus. */
634 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 1];
635 pcibios_resource_to_bus(bridge->bus, &region, res);
636 if (res->flags & IORESOURCE_MEM) {
637 l = (region.start >> 16) & 0xfff0;
638 l |= region.end & 0xfff00000;
639 dev_info(&bridge->dev, " bridge window %pR\n", res);
640 } else {
641 l = 0x0000fff0;
642 }
643 pci_write_config_dword(bridge, PCI_MEMORY_BASE, l);
644 }
645
646 static void pci_setup_bridge_mmio_pref(struct pci_dev *bridge)
647 {
648 struct resource *res;
649 struct pci_bus_region region;
650 u32 l, bu, lu;
651
652 /* Clear out the upper 32 bits of PREF limit.
653 If PCI_PREF_BASE_UPPER32 was non-zero, this temporarily
654 disables PREF range, which is ok. */
655 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, 0);
656
657 /* Set up PREF base/limit. */
658 bu = lu = 0;
659 res = &bridge->resource[PCI_BRIDGE_RESOURCES + 2];
660 pcibios_resource_to_bus(bridge->bus, &region, res);
661 if (res->flags & IORESOURCE_PREFETCH) {
662 l = (region.start >> 16) & 0xfff0;
663 l |= region.end & 0xfff00000;
664 if (res->flags & IORESOURCE_MEM_64) {
665 bu = upper_32_bits(region.start);
666 lu = upper_32_bits(region.end);
667 }
668 dev_info(&bridge->dev, " bridge window %pR\n", res);
669 } else {
670 l = 0x0000fff0;
671 }
672 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, l);
673
674 /* Set the upper 32 bits of PREF base & limit. */
675 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32, bu);
676 pci_write_config_dword(bridge, PCI_PREF_LIMIT_UPPER32, lu);
677 }
678
679 static void __pci_setup_bridge(struct pci_bus *bus, unsigned long type)
680 {
681 struct pci_dev *bridge = bus->self;
682
683 dev_info(&bridge->dev, "PCI bridge to %pR\n",
684 &bus->busn_res);
685
686 if (type & IORESOURCE_IO)
687 pci_setup_bridge_io(bridge);
688
689 if (type & IORESOURCE_MEM)
690 pci_setup_bridge_mmio(bridge);
691
692 if (type & IORESOURCE_PREFETCH)
693 pci_setup_bridge_mmio_pref(bridge);
694
695 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL, bus->bridge_ctl);
696 }
697
698 void __weak pcibios_setup_bridge(struct pci_bus *bus, unsigned long type)
699 {
700 }
701
702 void pci_setup_bridge(struct pci_bus *bus)
703 {
704 unsigned long type = IORESOURCE_IO | IORESOURCE_MEM |
705 IORESOURCE_PREFETCH;
706
707 pcibios_setup_bridge(bus, type);
708 __pci_setup_bridge(bus, type);
709 }
710
711
712 int pci_claim_bridge_resource(struct pci_dev *bridge, int i)
713 {
714 if (i < PCI_BRIDGE_RESOURCES || i > PCI_BRIDGE_RESOURCE_END)
715 return 0;
716
717 if (pci_claim_resource(bridge, i) == 0)
718 return 0; /* claimed the window */
719
720 if ((bridge->class >> 8) != PCI_CLASS_BRIDGE_PCI)
721 return 0;
722
723 if (!pci_bus_clip_resource(bridge, i))
724 return -EINVAL; /* clipping didn't change anything */
725
726 switch (i - PCI_BRIDGE_RESOURCES) {
727 case 0:
728 pci_setup_bridge_io(bridge);
729 break;
730 case 1:
731 pci_setup_bridge_mmio(bridge);
732 break;
733 case 2:
734 pci_setup_bridge_mmio_pref(bridge);
735 break;
736 default:
737 return -EINVAL;
738 }
739
740 if (pci_claim_resource(bridge, i) == 0)
741 return 0; /* claimed a smaller window */
742
743 return -EINVAL;
744 }
745
746 /* Check whether the bridge supports optional I/O and
747 prefetchable memory ranges. If not, the respective
748 base/limit registers must be read-only and read as 0. */
749 static void pci_bridge_check_ranges(struct pci_bus *bus)
750 {
751 u16 io;
752 u32 pmem;
753 struct pci_dev *bridge = bus->self;
754 struct resource *b_res;
755
756 b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
757 b_res[1].flags |= IORESOURCE_MEM;
758
759 pci_read_config_word(bridge, PCI_IO_BASE, &io);
760 if (!io) {
761 pci_write_config_word(bridge, PCI_IO_BASE, 0xe0f0);
762 pci_read_config_word(bridge, PCI_IO_BASE, &io);
763 pci_write_config_word(bridge, PCI_IO_BASE, 0x0);
764 }
765 if (io)
766 b_res[0].flags |= IORESOURCE_IO;
767
768 /* DECchip 21050 pass 2 errata: the bridge may miss an address
769 disconnect boundary by one PCI data phase.
770 Workaround: do not use prefetching on this device. */
771 if (bridge->vendor == PCI_VENDOR_ID_DEC && bridge->device == 0x0001)
772 return;
773
774 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
775 if (!pmem) {
776 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE,
777 0xffe0fff0);
778 pci_read_config_dword(bridge, PCI_PREF_MEMORY_BASE, &pmem);
779 pci_write_config_dword(bridge, PCI_PREF_MEMORY_BASE, 0x0);
780 }
781 if (pmem) {
782 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
783 if ((pmem & PCI_PREF_RANGE_TYPE_MASK) ==
784 PCI_PREF_RANGE_TYPE_64) {
785 b_res[2].flags |= IORESOURCE_MEM_64;
786 b_res[2].flags |= PCI_PREF_RANGE_TYPE_64;
787 }
788 }
789
790 /* double check if bridge does support 64 bit pref */
791 if (b_res[2].flags & IORESOURCE_MEM_64) {
792 u32 mem_base_hi, tmp;
793 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32,
794 &mem_base_hi);
795 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
796 0xffffffff);
797 pci_read_config_dword(bridge, PCI_PREF_BASE_UPPER32, &tmp);
798 if (!tmp)
799 b_res[2].flags &= ~IORESOURCE_MEM_64;
800 pci_write_config_dword(bridge, PCI_PREF_BASE_UPPER32,
801 mem_base_hi);
802 }
803 }
804
805 /* Helper function for sizing routines: find first available
806 bus resource of a given type. Note: we intentionally skip
807 the bus resources which have already been assigned (that is,
808 have non-NULL parent resource). */
809 static struct resource *find_free_bus_resource(struct pci_bus *bus,
810 unsigned long type_mask, unsigned long type)
811 {
812 int i;
813 struct resource *r;
814
815 pci_bus_for_each_resource(bus, r, i) {
816 if (r == &ioport_resource || r == &iomem_resource)
817 continue;
818 if (r && (r->flags & type_mask) == type && !r->parent)
819 return r;
820 }
821 return NULL;
822 }
823
824 static resource_size_t calculate_iosize(resource_size_t size,
825 resource_size_t min_size,
826 resource_size_t size1,
827 resource_size_t old_size,
828 resource_size_t align)
829 {
830 if (size < min_size)
831 size = min_size;
832 if (old_size == 1)
833 old_size = 0;
834 /* To be fixed in 2.5: we should have sort of HAVE_ISA
835 flag in the struct pci_bus. */
836 #if defined(CONFIG_ISA) || defined(CONFIG_EISA)
837 size = (size & 0xff) + ((size & ~0xffUL) << 2);
838 #endif
839 size = ALIGN(size + size1, align);
840 if (size < old_size)
841 size = old_size;
842 return size;
843 }
844
845 static resource_size_t calculate_memsize(resource_size_t size,
846 resource_size_t min_size,
847 resource_size_t size1,
848 resource_size_t old_size,
849 resource_size_t align)
850 {
851 if (size < min_size)
852 size = min_size;
853 if (old_size == 1)
854 old_size = 0;
855 if (size < old_size)
856 size = old_size;
857 size = ALIGN(size + size1, align);
858 return size;
859 }
860
861 resource_size_t __weak pcibios_window_alignment(struct pci_bus *bus,
862 unsigned long type)
863 {
864 return 1;
865 }
866
867 #define PCI_P2P_DEFAULT_MEM_ALIGN 0x100000 /* 1MiB */
868 #define PCI_P2P_DEFAULT_IO_ALIGN 0x1000 /* 4KiB */
869 #define PCI_P2P_DEFAULT_IO_ALIGN_1K 0x400 /* 1KiB */
870
871 static resource_size_t window_alignment(struct pci_bus *bus,
872 unsigned long type)
873 {
874 resource_size_t align = 1, arch_align;
875
876 if (type & IORESOURCE_MEM)
877 align = PCI_P2P_DEFAULT_MEM_ALIGN;
878 else if (type & IORESOURCE_IO) {
879 /*
880 * Per spec, I/O windows are 4K-aligned, but some
881 * bridges have an extension to support 1K alignment.
882 */
883 if (bus->self->io_window_1k)
884 align = PCI_P2P_DEFAULT_IO_ALIGN_1K;
885 else
886 align = PCI_P2P_DEFAULT_IO_ALIGN;
887 }
888
889 arch_align = pcibios_window_alignment(bus, type);
890 return max(align, arch_align);
891 }
892
893 /**
894 * pbus_size_io() - size the io window of a given bus
895 *
896 * @bus : the bus
897 * @min_size : the minimum io window that must to be allocated
898 * @add_size : additional optional io window
899 * @realloc_head : track the additional io window on this list
900 *
901 * Sizing the IO windows of the PCI-PCI bridge is trivial,
902 * since these windows have 1K or 4K granularity and the IO ranges
903 * of non-bridge PCI devices are limited to 256 bytes.
904 * We must be careful with the ISA aliasing though.
905 */
906 static void pbus_size_io(struct pci_bus *bus, resource_size_t min_size,
907 resource_size_t add_size, struct list_head *realloc_head)
908 {
909 struct pci_dev *dev;
910 struct resource *b_res = find_free_bus_resource(bus, IORESOURCE_IO,
911 IORESOURCE_IO);
912 resource_size_t size = 0, size0 = 0, size1 = 0;
913 resource_size_t children_add_size = 0;
914 resource_size_t min_align, align;
915
916 if (!b_res)
917 return;
918
919 min_align = window_alignment(bus, IORESOURCE_IO);
920 list_for_each_entry(dev, &bus->devices, bus_list) {
921 int i;
922
923 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
924 struct resource *r = &dev->resource[i];
925 unsigned long r_size;
926
927 if (r->parent || !(r->flags & IORESOURCE_IO))
928 continue;
929 r_size = resource_size(r);
930
931 if (r_size < 0x400)
932 /* Might be re-aligned for ISA */
933 size += r_size;
934 else
935 size1 += r_size;
936
937 align = pci_resource_alignment(dev, r);
938 if (align > min_align)
939 min_align = align;
940
941 if (realloc_head)
942 children_add_size += get_res_add_size(realloc_head, r);
943 }
944 }
945
946 size0 = calculate_iosize(size, min_size, size1,
947 resource_size(b_res), min_align);
948 if (children_add_size > add_size)
949 add_size = children_add_size;
950 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
951 calculate_iosize(size, min_size, add_size + size1,
952 resource_size(b_res), min_align);
953 if (!size0 && !size1) {
954 if (b_res->start || b_res->end)
955 dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
956 b_res, &bus->busn_res);
957 b_res->flags = 0;
958 return;
959 }
960
961 b_res->start = min_align;
962 b_res->end = b_res->start + size0 - 1;
963 b_res->flags |= IORESOURCE_STARTALIGN;
964 if (size1 > size0 && realloc_head) {
965 add_to_list(realloc_head, bus->self, b_res, size1-size0,
966 min_align);
967 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx\n",
968 b_res, &bus->busn_res,
969 (unsigned long long)size1-size0);
970 }
971 }
972
973 static inline resource_size_t calculate_mem_align(resource_size_t *aligns,
974 int max_order)
975 {
976 resource_size_t align = 0;
977 resource_size_t min_align = 0;
978 int order;
979
980 for (order = 0; order <= max_order; order++) {
981 resource_size_t align1 = 1;
982
983 align1 <<= (order + 20);
984
985 if (!align)
986 min_align = align1;
987 else if (ALIGN(align + min_align, min_align) < align1)
988 min_align = align1 >> 1;
989 align += aligns[order];
990 }
991
992 return min_align;
993 }
994
995 /**
996 * pbus_size_mem() - size the memory window of a given bus
997 *
998 * @bus : the bus
999 * @mask: mask the resource flag, then compare it with type
1000 * @type: the type of free resource from bridge
1001 * @type2: second match type
1002 * @type3: third match type
1003 * @min_size : the minimum memory window that must to be allocated
1004 * @add_size : additional optional memory window
1005 * @realloc_head : track the additional memory window on this list
1006 *
1007 * Calculate the size of the bus and minimal alignment which
1008 * guarantees that all child resources fit in this size.
1009 *
1010 * Returns -ENOSPC if there's no available bus resource of the desired type.
1011 * Otherwise, sets the bus resource start/end to indicate the required
1012 * size, adds things to realloc_head (if supplied), and returns 0.
1013 */
1014 static int pbus_size_mem(struct pci_bus *bus, unsigned long mask,
1015 unsigned long type, unsigned long type2,
1016 unsigned long type3,
1017 resource_size_t min_size, resource_size_t add_size,
1018 struct list_head *realloc_head)
1019 {
1020 struct pci_dev *dev;
1021 resource_size_t min_align, align, size, size0, size1;
1022 resource_size_t aligns[18]; /* Alignments from 1Mb to 128Gb */
1023 int order, max_order;
1024 struct resource *b_res = find_free_bus_resource(bus,
1025 mask | IORESOURCE_PREFETCH, type);
1026 resource_size_t children_add_size = 0;
1027 resource_size_t children_add_align = 0;
1028 resource_size_t add_align = 0;
1029
1030 if (!b_res)
1031 return -ENOSPC;
1032
1033 memset(aligns, 0, sizeof(aligns));
1034 max_order = 0;
1035 size = 0;
1036
1037 list_for_each_entry(dev, &bus->devices, bus_list) {
1038 int i;
1039
1040 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1041 struct resource *r = &dev->resource[i];
1042 resource_size_t r_size;
1043
1044 if (r->parent || (r->flags & IORESOURCE_PCI_FIXED) ||
1045 ((r->flags & mask) != type &&
1046 (r->flags & mask) != type2 &&
1047 (r->flags & mask) != type3))
1048 continue;
1049 r_size = resource_size(r);
1050 #ifdef CONFIG_PCI_IOV
1051 /* put SRIOV requested res to the optional list */
1052 if (realloc_head && i >= PCI_IOV_RESOURCES &&
1053 i <= PCI_IOV_RESOURCE_END) {
1054 add_align = max(pci_resource_alignment(dev, r), add_align);
1055 r->end = r->start - 1;
1056 add_to_list(realloc_head, dev, r, r_size, 0/* don't care */);
1057 children_add_size += r_size;
1058 continue;
1059 }
1060 #endif
1061 /*
1062 * aligns[0] is for 1MB (since bridge memory
1063 * windows are always at least 1MB aligned), so
1064 * keep "order" from being negative for smaller
1065 * resources.
1066 */
1067 align = pci_resource_alignment(dev, r);
1068 order = __ffs(align) - 20;
1069 if (order < 0)
1070 order = 0;
1071 if (order >= ARRAY_SIZE(aligns)) {
1072 dev_warn(&dev->dev, "disabling BAR %d: %pR (bad alignment %#llx)\n",
1073 i, r, (unsigned long long) align);
1074 r->flags = 0;
1075 continue;
1076 }
1077 size += r_size;
1078 /* Exclude ranges with size > align from
1079 calculation of the alignment. */
1080 if (r_size == align)
1081 aligns[order] += align;
1082 if (order > max_order)
1083 max_order = order;
1084
1085 if (realloc_head) {
1086 children_add_size += get_res_add_size(realloc_head, r);
1087 children_add_align = get_res_add_align(realloc_head, r);
1088 add_align = max(add_align, children_add_align);
1089 }
1090 }
1091 }
1092
1093 min_align = calculate_mem_align(aligns, max_order);
1094 min_align = max(min_align, window_alignment(bus, b_res->flags));
1095 size0 = calculate_memsize(size, min_size, 0, resource_size(b_res), min_align);
1096 add_align = max(min_align, add_align);
1097 if (children_add_size > add_size)
1098 add_size = children_add_size;
1099 size1 = (!realloc_head || (realloc_head && !add_size)) ? size0 :
1100 calculate_memsize(size, min_size, add_size,
1101 resource_size(b_res), add_align);
1102 if (!size0 && !size1) {
1103 if (b_res->start || b_res->end)
1104 dev_info(&bus->self->dev, "disabling bridge window %pR to %pR (unused)\n",
1105 b_res, &bus->busn_res);
1106 b_res->flags = 0;
1107 return 0;
1108 }
1109 b_res->start = min_align;
1110 b_res->end = size0 + min_align - 1;
1111 b_res->flags |= IORESOURCE_STARTALIGN;
1112 if (size1 > size0 && realloc_head) {
1113 add_to_list(realloc_head, bus->self, b_res, size1-size0, add_align);
1114 dev_printk(KERN_DEBUG, &bus->self->dev, "bridge window %pR to %pR add_size %llx add_align %llx\n",
1115 b_res, &bus->busn_res,
1116 (unsigned long long) (size1 - size0),
1117 (unsigned long long) add_align);
1118 }
1119 return 0;
1120 }
1121
1122 unsigned long pci_cardbus_resource_alignment(struct resource *res)
1123 {
1124 if (res->flags & IORESOURCE_IO)
1125 return pci_cardbus_io_size;
1126 if (res->flags & IORESOURCE_MEM)
1127 return pci_cardbus_mem_size;
1128 return 0;
1129 }
1130
1131 static void pci_bus_size_cardbus(struct pci_bus *bus,
1132 struct list_head *realloc_head)
1133 {
1134 struct pci_dev *bridge = bus->self;
1135 struct resource *b_res = &bridge->resource[PCI_BRIDGE_RESOURCES];
1136 resource_size_t b_res_3_size = pci_cardbus_mem_size * 2;
1137 u16 ctrl;
1138
1139 if (b_res[0].parent)
1140 goto handle_b_res_1;
1141 /*
1142 * Reserve some resources for CardBus. We reserve
1143 * a fixed amount of bus space for CardBus bridges.
1144 */
1145 b_res[0].start = pci_cardbus_io_size;
1146 b_res[0].end = b_res[0].start + pci_cardbus_io_size - 1;
1147 b_res[0].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1148 if (realloc_head) {
1149 b_res[0].end -= pci_cardbus_io_size;
1150 add_to_list(realloc_head, bridge, b_res, pci_cardbus_io_size,
1151 pci_cardbus_io_size);
1152 }
1153
1154 handle_b_res_1:
1155 if (b_res[1].parent)
1156 goto handle_b_res_2;
1157 b_res[1].start = pci_cardbus_io_size;
1158 b_res[1].end = b_res[1].start + pci_cardbus_io_size - 1;
1159 b_res[1].flags |= IORESOURCE_IO | IORESOURCE_STARTALIGN;
1160 if (realloc_head) {
1161 b_res[1].end -= pci_cardbus_io_size;
1162 add_to_list(realloc_head, bridge, b_res+1, pci_cardbus_io_size,
1163 pci_cardbus_io_size);
1164 }
1165
1166 handle_b_res_2:
1167 /* MEM1 must not be pref mmio */
1168 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1169 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM1) {
1170 ctrl &= ~PCI_CB_BRIDGE_CTL_PREFETCH_MEM1;
1171 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1172 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1173 }
1174
1175 /*
1176 * Check whether prefetchable memory is supported
1177 * by this bridge.
1178 */
1179 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1180 if (!(ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0)) {
1181 ctrl |= PCI_CB_BRIDGE_CTL_PREFETCH_MEM0;
1182 pci_write_config_word(bridge, PCI_CB_BRIDGE_CONTROL, ctrl);
1183 pci_read_config_word(bridge, PCI_CB_BRIDGE_CONTROL, &ctrl);
1184 }
1185
1186 if (b_res[2].parent)
1187 goto handle_b_res_3;
1188 /*
1189 * If we have prefetchable memory support, allocate
1190 * two regions. Otherwise, allocate one region of
1191 * twice the size.
1192 */
1193 if (ctrl & PCI_CB_BRIDGE_CTL_PREFETCH_MEM0) {
1194 b_res[2].start = pci_cardbus_mem_size;
1195 b_res[2].end = b_res[2].start + pci_cardbus_mem_size - 1;
1196 b_res[2].flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH |
1197 IORESOURCE_STARTALIGN;
1198 if (realloc_head) {
1199 b_res[2].end -= pci_cardbus_mem_size;
1200 add_to_list(realloc_head, bridge, b_res+2,
1201 pci_cardbus_mem_size, pci_cardbus_mem_size);
1202 }
1203
1204 /* reduce that to half */
1205 b_res_3_size = pci_cardbus_mem_size;
1206 }
1207
1208 handle_b_res_3:
1209 if (b_res[3].parent)
1210 goto handle_done;
1211 b_res[3].start = pci_cardbus_mem_size;
1212 b_res[3].end = b_res[3].start + b_res_3_size - 1;
1213 b_res[3].flags |= IORESOURCE_MEM | IORESOURCE_STARTALIGN;
1214 if (realloc_head) {
1215 b_res[3].end -= b_res_3_size;
1216 add_to_list(realloc_head, bridge, b_res+3, b_res_3_size,
1217 pci_cardbus_mem_size);
1218 }
1219
1220 handle_done:
1221 ;
1222 }
1223
1224 void __pci_bus_size_bridges(struct pci_bus *bus, struct list_head *realloc_head)
1225 {
1226 struct pci_dev *dev;
1227 unsigned long mask, prefmask, type2 = 0, type3 = 0;
1228 resource_size_t additional_mem_size = 0, additional_io_size = 0;
1229 struct resource *b_res;
1230 int ret;
1231
1232 list_for_each_entry(dev, &bus->devices, bus_list) {
1233 struct pci_bus *b = dev->subordinate;
1234 if (!b)
1235 continue;
1236
1237 switch (dev->class >> 8) {
1238 case PCI_CLASS_BRIDGE_CARDBUS:
1239 pci_bus_size_cardbus(b, realloc_head);
1240 break;
1241
1242 case PCI_CLASS_BRIDGE_PCI:
1243 default:
1244 __pci_bus_size_bridges(b, realloc_head);
1245 break;
1246 }
1247 }
1248
1249 /* The root bus? */
1250 if (pci_is_root_bus(bus))
1251 return;
1252
1253 switch (bus->self->class >> 8) {
1254 case PCI_CLASS_BRIDGE_CARDBUS:
1255 /* don't size cardbuses yet. */
1256 break;
1257
1258 case PCI_CLASS_BRIDGE_PCI:
1259 pci_bridge_check_ranges(bus);
1260 if (bus->self->is_hotplug_bridge) {
1261 additional_io_size = pci_hotplug_io_size;
1262 additional_mem_size = pci_hotplug_mem_size;
1263 }
1264 /* Fall through */
1265 default:
1266 pbus_size_io(bus, realloc_head ? 0 : additional_io_size,
1267 additional_io_size, realloc_head);
1268
1269 /*
1270 * If there's a 64-bit prefetchable MMIO window, compute
1271 * the size required to put all 64-bit prefetchable
1272 * resources in it.
1273 */
1274 b_res = &bus->self->resource[PCI_BRIDGE_RESOURCES];
1275 mask = IORESOURCE_MEM;
1276 prefmask = IORESOURCE_MEM | IORESOURCE_PREFETCH;
1277 if (b_res[2].flags & IORESOURCE_MEM_64) {
1278 prefmask |= IORESOURCE_MEM_64;
1279 ret = pbus_size_mem(bus, prefmask, prefmask,
1280 prefmask, prefmask,
1281 realloc_head ? 0 : additional_mem_size,
1282 additional_mem_size, realloc_head);
1283
1284 /*
1285 * If successful, all non-prefetchable resources
1286 * and any 32-bit prefetchable resources will go in
1287 * the non-prefetchable window.
1288 */
1289 if (ret == 0) {
1290 mask = prefmask;
1291 type2 = prefmask & ~IORESOURCE_MEM_64;
1292 type3 = prefmask & ~IORESOURCE_PREFETCH;
1293 }
1294 }
1295
1296 /*
1297 * If there is no 64-bit prefetchable window, compute the
1298 * size required to put all prefetchable resources in the
1299 * 32-bit prefetchable window (if there is one).
1300 */
1301 if (!type2) {
1302 prefmask &= ~IORESOURCE_MEM_64;
1303 ret = pbus_size_mem(bus, prefmask, prefmask,
1304 prefmask, prefmask,
1305 realloc_head ? 0 : additional_mem_size,
1306 additional_mem_size, realloc_head);
1307
1308 /*
1309 * If successful, only non-prefetchable resources
1310 * will go in the non-prefetchable window.
1311 */
1312 if (ret == 0)
1313 mask = prefmask;
1314 else
1315 additional_mem_size += additional_mem_size;
1316
1317 type2 = type3 = IORESOURCE_MEM;
1318 }
1319
1320 /*
1321 * Compute the size required to put everything else in the
1322 * non-prefetchable window. This includes:
1323 *
1324 * - all non-prefetchable resources
1325 * - 32-bit prefetchable resources if there's a 64-bit
1326 * prefetchable window or no prefetchable window at all
1327 * - 64-bit prefetchable resources if there's no
1328 * prefetchable window at all
1329 *
1330 * Note that the strategy in __pci_assign_resource() must
1331 * match that used here. Specifically, we cannot put a
1332 * 32-bit prefetchable resource in a 64-bit prefetchable
1333 * window.
1334 */
1335 pbus_size_mem(bus, mask, IORESOURCE_MEM, type2, type3,
1336 realloc_head ? 0 : additional_mem_size,
1337 additional_mem_size, realloc_head);
1338 break;
1339 }
1340 }
1341
1342 void pci_bus_size_bridges(struct pci_bus *bus)
1343 {
1344 __pci_bus_size_bridges(bus, NULL);
1345 }
1346 EXPORT_SYMBOL(pci_bus_size_bridges);
1347
1348 static void assign_fixed_resource_on_bus(struct pci_bus *b, struct resource *r)
1349 {
1350 int i;
1351 struct resource *parent_r;
1352 unsigned long mask = IORESOURCE_IO | IORESOURCE_MEM |
1353 IORESOURCE_PREFETCH;
1354
1355 pci_bus_for_each_resource(b, parent_r, i) {
1356 if (!parent_r)
1357 continue;
1358
1359 if ((r->flags & mask) == (parent_r->flags & mask) &&
1360 resource_contains(parent_r, r))
1361 request_resource(parent_r, r);
1362 }
1363 }
1364
1365 /*
1366 * Try to assign any resources marked as IORESOURCE_PCI_FIXED, as they
1367 * are skipped by pbus_assign_resources_sorted().
1368 */
1369 static void pdev_assign_fixed_resources(struct pci_dev *dev)
1370 {
1371 int i;
1372
1373 for (i = 0; i < PCI_NUM_RESOURCES; i++) {
1374 struct pci_bus *b;
1375 struct resource *r = &dev->resource[i];
1376
1377 if (r->parent || !(r->flags & IORESOURCE_PCI_FIXED) ||
1378 !(r->flags & (IORESOURCE_IO | IORESOURCE_MEM)))
1379 continue;
1380
1381 b = dev->bus;
1382 while (b && !r->parent) {
1383 assign_fixed_resource_on_bus(b, r);
1384 b = b->parent;
1385 }
1386 }
1387 }
1388
1389 void __pci_bus_assign_resources(const struct pci_bus *bus,
1390 struct list_head *realloc_head,
1391 struct list_head *fail_head)
1392 {
1393 struct pci_bus *b;
1394 struct pci_dev *dev;
1395
1396 pbus_assign_resources_sorted(bus, realloc_head, fail_head);
1397
1398 list_for_each_entry(dev, &bus->devices, bus_list) {
1399 pdev_assign_fixed_resources(dev);
1400
1401 b = dev->subordinate;
1402 if (!b)
1403 continue;
1404
1405 __pci_bus_assign_resources(b, realloc_head, fail_head);
1406
1407 switch (dev->class >> 8) {
1408 case PCI_CLASS_BRIDGE_PCI:
1409 if (!pci_is_enabled(dev))
1410 pci_setup_bridge(b);
1411 break;
1412
1413 case PCI_CLASS_BRIDGE_CARDBUS:
1414 pci_setup_cardbus(b);
1415 break;
1416
1417 default:
1418 dev_info(&dev->dev, "not setting up bridge for bus %04x:%02x\n",
1419 pci_domain_nr(b), b->number);
1420 break;
1421 }
1422 }
1423 }
1424
1425 void pci_bus_assign_resources(const struct pci_bus *bus)
1426 {
1427 __pci_bus_assign_resources(bus, NULL, NULL);
1428 }
1429 EXPORT_SYMBOL(pci_bus_assign_resources);
1430
1431 static void pci_claim_device_resources(struct pci_dev *dev)
1432 {
1433 int i;
1434
1435 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
1436 struct resource *r = &dev->resource[i];
1437
1438 if (!r->flags || r->parent)
1439 continue;
1440
1441 pci_claim_resource(dev, i);
1442 }
1443 }
1444
1445 static void pci_claim_bridge_resources(struct pci_dev *dev)
1446 {
1447 int i;
1448
1449 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
1450 struct resource *r = &dev->resource[i];
1451
1452 if (!r->flags || r->parent)
1453 continue;
1454
1455 pci_claim_bridge_resource(dev, i);
1456 }
1457 }
1458
1459 static void pci_bus_allocate_dev_resources(struct pci_bus *b)
1460 {
1461 struct pci_dev *dev;
1462 struct pci_bus *child;
1463
1464 list_for_each_entry(dev, &b->devices, bus_list) {
1465 pci_claim_device_resources(dev);
1466
1467 child = dev->subordinate;
1468 if (child)
1469 pci_bus_allocate_dev_resources(child);
1470 }
1471 }
1472
1473 static void pci_bus_allocate_resources(struct pci_bus *b)
1474 {
1475 struct pci_bus *child;
1476
1477 /*
1478 * Carry out a depth-first search on the PCI bus
1479 * tree to allocate bridge apertures. Read the
1480 * programmed bridge bases and recursively claim
1481 * the respective bridge resources.
1482 */
1483 if (b->self) {
1484 pci_read_bridge_bases(b);
1485 pci_claim_bridge_resources(b->self);
1486 }
1487
1488 list_for_each_entry(child, &b->children, node)
1489 pci_bus_allocate_resources(child);
1490 }
1491
1492 void pci_bus_claim_resources(struct pci_bus *b)
1493 {
1494 pci_bus_allocate_resources(b);
1495 pci_bus_allocate_dev_resources(b);
1496 }
1497 EXPORT_SYMBOL(pci_bus_claim_resources);
1498
1499 static void __pci_bridge_assign_resources(const struct pci_dev *bridge,
1500 struct list_head *add_head,
1501 struct list_head *fail_head)
1502 {
1503 struct pci_bus *b;
1504
1505 pdev_assign_resources_sorted((struct pci_dev *)bridge,
1506 add_head, fail_head);
1507
1508 b = bridge->subordinate;
1509 if (!b)
1510 return;
1511
1512 __pci_bus_assign_resources(b, add_head, fail_head);
1513
1514 switch (bridge->class >> 8) {
1515 case PCI_CLASS_BRIDGE_PCI:
1516 pci_setup_bridge(b);
1517 break;
1518
1519 case PCI_CLASS_BRIDGE_CARDBUS:
1520 pci_setup_cardbus(b);
1521 break;
1522
1523 default:
1524 dev_info(&bridge->dev, "not setting up bridge for bus %04x:%02x\n",
1525 pci_domain_nr(b), b->number);
1526 break;
1527 }
1528 }
1529 static void pci_bridge_release_resources(struct pci_bus *bus,
1530 unsigned long type)
1531 {
1532 struct pci_dev *dev = bus->self;
1533 struct resource *r;
1534 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1535 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1536 unsigned old_flags = 0;
1537 struct resource *b_res;
1538 int idx = 1;
1539
1540 b_res = &dev->resource[PCI_BRIDGE_RESOURCES];
1541
1542 /*
1543 * 1. if there is io port assign fail, will release bridge
1544 * io port.
1545 * 2. if there is non pref mmio assign fail, release bridge
1546 * nonpref mmio.
1547 * 3. if there is 64bit pref mmio assign fail, and bridge pref
1548 * is 64bit, release bridge pref mmio.
1549 * 4. if there is pref mmio assign fail, and bridge pref is
1550 * 32bit mmio, release bridge pref mmio
1551 * 5. if there is pref mmio assign fail, and bridge pref is not
1552 * assigned, release bridge nonpref mmio.
1553 */
1554 if (type & IORESOURCE_IO)
1555 idx = 0;
1556 else if (!(type & IORESOURCE_PREFETCH))
1557 idx = 1;
1558 else if ((type & IORESOURCE_MEM_64) &&
1559 (b_res[2].flags & IORESOURCE_MEM_64))
1560 idx = 2;
1561 else if (!(b_res[2].flags & IORESOURCE_MEM_64) &&
1562 (b_res[2].flags & IORESOURCE_PREFETCH))
1563 idx = 2;
1564 else
1565 idx = 1;
1566
1567 r = &b_res[idx];
1568
1569 if (!r->parent)
1570 return;
1571
1572 /*
1573 * if there are children under that, we should release them
1574 * all
1575 */
1576 release_child_resources(r);
1577 if (!release_resource(r)) {
1578 type = old_flags = r->flags & type_mask;
1579 dev_printk(KERN_DEBUG, &dev->dev, "resource %d %pR released\n",
1580 PCI_BRIDGE_RESOURCES + idx, r);
1581 /* keep the old size */
1582 r->end = resource_size(r) - 1;
1583 r->start = 0;
1584 r->flags = 0;
1585
1586 /* avoiding touch the one without PREF */
1587 if (type & IORESOURCE_PREFETCH)
1588 type = IORESOURCE_PREFETCH;
1589 __pci_setup_bridge(bus, type);
1590 /* for next child res under same bridge */
1591 r->flags = old_flags;
1592 }
1593 }
1594
1595 enum release_type {
1596 leaf_only,
1597 whole_subtree,
1598 };
1599 /*
1600 * try to release pci bridge resources that is from leaf bridge,
1601 * so we can allocate big new one later
1602 */
1603 static void pci_bus_release_bridge_resources(struct pci_bus *bus,
1604 unsigned long type,
1605 enum release_type rel_type)
1606 {
1607 struct pci_dev *dev;
1608 bool is_leaf_bridge = true;
1609
1610 list_for_each_entry(dev, &bus->devices, bus_list) {
1611 struct pci_bus *b = dev->subordinate;
1612 if (!b)
1613 continue;
1614
1615 is_leaf_bridge = false;
1616
1617 if ((dev->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1618 continue;
1619
1620 if (rel_type == whole_subtree)
1621 pci_bus_release_bridge_resources(b, type,
1622 whole_subtree);
1623 }
1624
1625 if (pci_is_root_bus(bus))
1626 return;
1627
1628 if ((bus->self->class >> 8) != PCI_CLASS_BRIDGE_PCI)
1629 return;
1630
1631 if ((rel_type == whole_subtree) || is_leaf_bridge)
1632 pci_bridge_release_resources(bus, type);
1633 }
1634
1635 static void pci_bus_dump_res(struct pci_bus *bus)
1636 {
1637 struct resource *res;
1638 int i;
1639
1640 pci_bus_for_each_resource(bus, res, i) {
1641 if (!res || !res->end || !res->flags)
1642 continue;
1643
1644 dev_printk(KERN_DEBUG, &bus->dev, "resource %d %pR\n", i, res);
1645 }
1646 }
1647
1648 static void pci_bus_dump_resources(struct pci_bus *bus)
1649 {
1650 struct pci_bus *b;
1651 struct pci_dev *dev;
1652
1653
1654 pci_bus_dump_res(bus);
1655
1656 list_for_each_entry(dev, &bus->devices, bus_list) {
1657 b = dev->subordinate;
1658 if (!b)
1659 continue;
1660
1661 pci_bus_dump_resources(b);
1662 }
1663 }
1664
1665 static int pci_bus_get_depth(struct pci_bus *bus)
1666 {
1667 int depth = 0;
1668 struct pci_bus *child_bus;
1669
1670 list_for_each_entry(child_bus, &bus->children, node) {
1671 int ret;
1672
1673 ret = pci_bus_get_depth(child_bus);
1674 if (ret + 1 > depth)
1675 depth = ret + 1;
1676 }
1677
1678 return depth;
1679 }
1680
1681 /*
1682 * -1: undefined, will auto detect later
1683 * 0: disabled by user
1684 * 1: disabled by auto detect
1685 * 2: enabled by user
1686 * 3: enabled by auto detect
1687 */
1688 enum enable_type {
1689 undefined = -1,
1690 user_disabled,
1691 auto_disabled,
1692 user_enabled,
1693 auto_enabled,
1694 };
1695
1696 static enum enable_type pci_realloc_enable = undefined;
1697 void __init pci_realloc_get_opt(char *str)
1698 {
1699 if (!strncmp(str, "off", 3))
1700 pci_realloc_enable = user_disabled;
1701 else if (!strncmp(str, "on", 2))
1702 pci_realloc_enable = user_enabled;
1703 }
1704 static bool pci_realloc_enabled(enum enable_type enable)
1705 {
1706 return enable >= user_enabled;
1707 }
1708
1709 #if defined(CONFIG_PCI_IOV) && defined(CONFIG_PCI_REALLOC_ENABLE_AUTO)
1710 static int iov_resources_unassigned(struct pci_dev *dev, void *data)
1711 {
1712 int i;
1713 bool *unassigned = data;
1714
1715 for (i = PCI_IOV_RESOURCES; i <= PCI_IOV_RESOURCE_END; i++) {
1716 struct resource *r = &dev->resource[i];
1717 struct pci_bus_region region;
1718
1719 /* Not assigned or rejected by kernel? */
1720 if (!r->flags)
1721 continue;
1722
1723 pcibios_resource_to_bus(dev->bus, &region, r);
1724 if (!region.start) {
1725 *unassigned = true;
1726 return 1; /* return early from pci_walk_bus() */
1727 }
1728 }
1729
1730 return 0;
1731 }
1732
1733 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1734 enum enable_type enable_local)
1735 {
1736 bool unassigned = false;
1737
1738 if (enable_local != undefined)
1739 return enable_local;
1740
1741 pci_walk_bus(bus, iov_resources_unassigned, &unassigned);
1742 if (unassigned)
1743 return auto_enabled;
1744
1745 return enable_local;
1746 }
1747 #else
1748 static enum enable_type pci_realloc_detect(struct pci_bus *bus,
1749 enum enable_type enable_local)
1750 {
1751 return enable_local;
1752 }
1753 #endif
1754
1755 /*
1756 * first try will not touch pci bridge res
1757 * second and later try will clear small leaf bridge res
1758 * will stop till to the max depth if can not find good one
1759 */
1760 void pci_assign_unassigned_root_bus_resources(struct pci_bus *bus)
1761 {
1762 LIST_HEAD(realloc_head); /* list of resources that
1763 want additional resources */
1764 struct list_head *add_list = NULL;
1765 int tried_times = 0;
1766 enum release_type rel_type = leaf_only;
1767 LIST_HEAD(fail_head);
1768 struct pci_dev_resource *fail_res;
1769 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1770 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1771 int pci_try_num = 1;
1772 enum enable_type enable_local;
1773
1774 /* don't realloc if asked to do so */
1775 enable_local = pci_realloc_detect(bus, pci_realloc_enable);
1776 if (pci_realloc_enabled(enable_local)) {
1777 int max_depth = pci_bus_get_depth(bus);
1778
1779 pci_try_num = max_depth + 1;
1780 dev_printk(KERN_DEBUG, &bus->dev,
1781 "max bus depth: %d pci_try_num: %d\n",
1782 max_depth, pci_try_num);
1783 }
1784
1785 again:
1786 /*
1787 * last try will use add_list, otherwise will try good to have as
1788 * must have, so can realloc parent bridge resource
1789 */
1790 if (tried_times + 1 == pci_try_num)
1791 add_list = &realloc_head;
1792 /* Depth first, calculate sizes and alignments of all
1793 subordinate buses. */
1794 __pci_bus_size_bridges(bus, add_list);
1795
1796 /* Depth last, allocate resources and update the hardware. */
1797 __pci_bus_assign_resources(bus, add_list, &fail_head);
1798 if (add_list)
1799 BUG_ON(!list_empty(add_list));
1800 tried_times++;
1801
1802 /* any device complain? */
1803 if (list_empty(&fail_head))
1804 goto dump;
1805
1806 if (tried_times >= pci_try_num) {
1807 if (enable_local == undefined)
1808 dev_info(&bus->dev, "Some PCI device resources are unassigned, try booting with pci=realloc\n");
1809 else if (enable_local == auto_enabled)
1810 dev_info(&bus->dev, "Automatically enabled pci realloc, if you have problem, try booting with pci=realloc=off\n");
1811
1812 free_list(&fail_head);
1813 goto dump;
1814 }
1815
1816 dev_printk(KERN_DEBUG, &bus->dev,
1817 "No. %d try to assign unassigned res\n", tried_times + 1);
1818
1819 /* third times and later will not check if it is leaf */
1820 if ((tried_times + 1) > 2)
1821 rel_type = whole_subtree;
1822
1823 /*
1824 * Try to release leaf bridge's resources that doesn't fit resource of
1825 * child device under that bridge
1826 */
1827 list_for_each_entry(fail_res, &fail_head, list)
1828 pci_bus_release_bridge_resources(fail_res->dev->bus,
1829 fail_res->flags & type_mask,
1830 rel_type);
1831
1832 /* restore size and flags */
1833 list_for_each_entry(fail_res, &fail_head, list) {
1834 struct resource *res = fail_res->res;
1835
1836 res->start = fail_res->start;
1837 res->end = fail_res->end;
1838 res->flags = fail_res->flags;
1839 if (fail_res->dev->subordinate)
1840 res->flags = 0;
1841 }
1842 free_list(&fail_head);
1843
1844 goto again;
1845
1846 dump:
1847 /* dump the resource on buses */
1848 pci_bus_dump_resources(bus);
1849 }
1850
1851 void __init pci_assign_unassigned_resources(void)
1852 {
1853 struct pci_bus *root_bus;
1854
1855 list_for_each_entry(root_bus, &pci_root_buses, node)
1856 pci_assign_unassigned_root_bus_resources(root_bus);
1857 }
1858
1859 void pci_assign_unassigned_bridge_resources(struct pci_dev *bridge)
1860 {
1861 struct pci_bus *parent = bridge->subordinate;
1862 LIST_HEAD(add_list); /* list of resources that
1863 want additional resources */
1864 int tried_times = 0;
1865 LIST_HEAD(fail_head);
1866 struct pci_dev_resource *fail_res;
1867 int retval;
1868 unsigned long type_mask = IORESOURCE_IO | IORESOURCE_MEM |
1869 IORESOURCE_PREFETCH | IORESOURCE_MEM_64;
1870
1871 again:
1872 __pci_bus_size_bridges(parent, &add_list);
1873 __pci_bridge_assign_resources(bridge, &add_list, &fail_head);
1874 BUG_ON(!list_empty(&add_list));
1875 tried_times++;
1876
1877 if (list_empty(&fail_head))
1878 goto enable_all;
1879
1880 if (tried_times >= 2) {
1881 /* still fail, don't need to try more */
1882 free_list(&fail_head);
1883 goto enable_all;
1884 }
1885
1886 printk(KERN_DEBUG "PCI: No. %d try to assign unassigned res\n",
1887 tried_times + 1);
1888
1889 /*
1890 * Try to release leaf bridge's resources that doesn't fit resource of
1891 * child device under that bridge
1892 */
1893 list_for_each_entry(fail_res, &fail_head, list)
1894 pci_bus_release_bridge_resources(fail_res->dev->bus,
1895 fail_res->flags & type_mask,
1896 whole_subtree);
1897
1898 /* restore size and flags */
1899 list_for_each_entry(fail_res, &fail_head, list) {
1900 struct resource *res = fail_res->res;
1901
1902 res->start = fail_res->start;
1903 res->end = fail_res->end;
1904 res->flags = fail_res->flags;
1905 if (fail_res->dev->subordinate)
1906 res->flags = 0;
1907 }
1908 free_list(&fail_head);
1909
1910 goto again;
1911
1912 enable_all:
1913 retval = pci_reenable_device(bridge);
1914 if (retval)
1915 dev_err(&bridge->dev, "Error reenabling bridge (%d)\n", retval);
1916 pci_set_master(bridge);
1917 }
1918 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bridge_resources);
1919
1920 void pci_assign_unassigned_bus_resources(struct pci_bus *bus)
1921 {
1922 struct pci_dev *dev;
1923 LIST_HEAD(add_list); /* list of resources that
1924 want additional resources */
1925
1926 down_read(&pci_bus_sem);
1927 list_for_each_entry(dev, &bus->devices, bus_list)
1928 if (pci_is_bridge(dev) && pci_has_subordinate(dev))
1929 __pci_bus_size_bridges(dev->subordinate,
1930 &add_list);
1931 up_read(&pci_bus_sem);
1932 __pci_bus_assign_resources(bus, &add_list, NULL);
1933 BUG_ON(!list_empty(&add_list));
1934 }
1935 EXPORT_SYMBOL_GPL(pci_assign_unassigned_bus_resources);
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