arch/blackfin/mach-bf533/include/mach/mem_init.h

   1 /*
   2  * File:         include/asm-blackfin/mach-bf533/mem_init.h
   3  * Based on:
   4  * Author:
   5  *
   6  * Created:
   7  * Description:
   8  *
   9  * Rev:
  10  *
  11  * Modified:
  12  *               Copyright 2004-2006 Analog Devices Inc.
  13  *
  14  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
  15  *
  16  * This program is free software; you can redistribute it and/or modify
  17  * it under the terms of the GNU General Public License as published by
  18  * the Free Software Foundation; either version 2, or (at your option)
  19  * any later version.
  20  *
  21  * This program is distributed in the hope that it will be useful,
  22  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  23  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24  * GNU General Public License for more details.
  25  *
  26  * You should have received a copy of the GNU General Public License
  27  * along with this program; see the file COPYING.
  28  * If not, write to the Free Software Foundation,
  29  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  30  */
  31
  32 #if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
  33      CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
  34 #if (CONFIG_SCLK_HZ > 119402985)
  35 #define SDRAM_tRP       TRP_2
  36 #define SDRAM_tRP_num   2
  37 #define SDRAM_tRAS      TRAS_7
  38 #define SDRAM_tRAS_num  7
  39 #define SDRAM_tRCD      TRCD_2
  40 #define SDRAM_tWR       TWR_2
  41 #endif
  42 #if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
  43 #define SDRAM_tRP       TRP_2
  44 #define SDRAM_tRP_num   2
  45 #define SDRAM_tRAS      TRAS_6
  46 #define SDRAM_tRAS_num  6
  47 #define SDRAM_tRCD      TRCD_2
  48 #define SDRAM_tWR       TWR_2
  49 #endif
  50 #if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
  51 #define SDRAM_tRP       TRP_2
  52 #define SDRAM_tRP_num   2
  53 #define SDRAM_tRAS      TRAS_5
  54 #define SDRAM_tRAS_num  5
  55 #define SDRAM_tRCD      TRCD_2
  56 #define SDRAM_tWR       TWR_2
  57 #endif
  58 #if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
  59 #define SDRAM_tRP       TRP_2
  60 #define SDRAM_tRP_num   2
  61 #define SDRAM_tRAS      TRAS_4
  62 #define SDRAM_tRAS_num  4
  63 #define SDRAM_tRCD      TRCD_2
  64 #define SDRAM_tWR       TWR_2
  65 #endif
  66 #if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
  67 #define SDRAM_tRP       TRP_2
  68 #define SDRAM_tRP_num   2
  69 #define SDRAM_tRAS      TRAS_3
  70 #define SDRAM_tRAS_num  3
  71 #define SDRAM_tRCD      TRCD_2
  72 #define SDRAM_tWR       TWR_2
  73 #endif
  74 #if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
  75 #define SDRAM_tRP       TRP_1
  76 #define SDRAM_tRP_num   1
  77 #define SDRAM_tRAS      TRAS_4
  78 #define SDRAM_tRAS_num  3
  79 #define SDRAM_tRCD      TRCD_1
  80 #define SDRAM_tWR       TWR_2
  81 #endif
  82 #if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
  83 #define SDRAM_tRP       TRP_1
  84 #define SDRAM_tRP_num   1
  85 #define SDRAM_tRAS      TRAS_3
  86 #define SDRAM_tRAS_num  3
  87 #define SDRAM_tRCD      TRCD_1
  88 #define SDRAM_tWR       TWR_2
  89 #endif
  90 #if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
  91 #define SDRAM_tRP       TRP_1
  92 #define SDRAM_tRP_num   1
  93 #define SDRAM_tRAS      TRAS_2
  94 #define SDRAM_tRAS_num  2
  95 #define SDRAM_tRCD      TRCD_1
  96 #define SDRAM_tWR       TWR_2
  97 #endif
  98 #if (CONFIG_SCLK_HZ <= 29850746)
  99 #define SDRAM_tRP       TRP_1
 100 #define SDRAM_tRP_num   1
 101 #define SDRAM_tRAS      TRAS_1
 102 #define SDRAM_tRAS_num  1
 103 #define SDRAM_tRCD      TRCD_1
 104 #define SDRAM_tWR       TWR_2
 105 #endif
 106 #endif
 107
 108 #if (CONFIG_MEM_MT48LC16M16A2TG_75)
 109   /*SDRAM INFORMATION: */
 110 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 111 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 112 #define SDRAM_CL    CL_3
 113 #endif
 114
 115 #if (CONFIG_MEM_MT48LC64M4A2FB_7E)
 116   /*SDRAM INFORMATION: */
 117 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 118 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 119 #define SDRAM_CL    CL_3
 120 #endif
 121
 122 #if (CONFIG_MEM_MT48LC32M16A2TG_75)
 123   /*SDRAM INFORMATION: */
 124 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 125 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 126 #define SDRAM_CL    CL_3
 127 #endif
 128
 129 #if (CONFIG_MEM_GENERIC_BOARD)
 130   /*SDRAM INFORMATION: Modify this for your board */
 131 #define SDRAM_Tref  64          /* Refresh period in milliseconds   */
 132 #define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
 133 #define SDRAM_CL    CL_3
 134 #endif
 135
 136 /* Equation from section 17 (p17-46) of BF533 HRM */
 137 #define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
 138
 139 /* Enable SCLK Out */
 140 #define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
 141
 142 #if defined CONFIG_CLKIN_HALF
 143 #define CLKIN_HALF       1
 144 #else
 145 #define CLKIN_HALF       0
 146 #endif
 147
 148 #if defined CONFIG_PLL_BYPASS
 149 #define PLL_BYPASS      1
 150 #else
 151 #define PLL_BYPASS       0
 152 #endif
 153
 154 /***************************************Currently Not Being Used *********************************/
 155 #define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 156 #define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 157 #define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
 158 #define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 159 #define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
 160
 161 #if (flash_EBIU_AMBCTL_TT > 3)
 162 #define flash_EBIU_AMBCTL0_TT   B0TT_4
 163 #endif
 164 #if (flash_EBIU_AMBCTL_TT == 3)
 165 #define flash_EBIU_AMBCTL0_TT   B0TT_3
 166 #endif
 167 #if (flash_EBIU_AMBCTL_TT == 2)
 168 #define flash_EBIU_AMBCTL0_TT   B0TT_2
 169 #endif
 170 #if (flash_EBIU_AMBCTL_TT < 2)
 171 #define flash_EBIU_AMBCTL0_TT   B0TT_1
 172 #endif
 173
 174 #if (flash_EBIU_AMBCTL_ST > 3)
 175 #define flash_EBIU_AMBCTL0_ST   B0ST_4
 176 #endif
 177 #if (flash_EBIU_AMBCTL_ST == 3)
 178 #define flash_EBIU_AMBCTL0_ST   B0ST_3
 179 #endif
 180 #if (flash_EBIU_AMBCTL_ST == 2)
 181 #define flash_EBIU_AMBCTL0_ST   B0ST_2
 182 #endif
 183 #if (flash_EBIU_AMBCTL_ST < 2)
 184 #define flash_EBIU_AMBCTL0_ST   B0ST_1
 185 #endif
 186
 187 #if (flash_EBIU_AMBCTL_HT > 2)
 188 #define flash_EBIU_AMBCTL0_HT   B0HT_3
 189 #endif
 190 #if (flash_EBIU_AMBCTL_HT == 2)
 191 #define flash_EBIU_AMBCTL0_HT   B0HT_2
 192 #endif
 193 #if (flash_EBIU_AMBCTL_HT == 1)
 194 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 195 #endif
 196 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
 197 #define flash_EBIU_AMBCTL0_HT   B0HT_0
 198 #endif
 199 #if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
 200 #define flash_EBIU_AMBCTL0_HT   B0HT_1
 201 #endif
 202
 203 #if (flash_EBIU_AMBCTL_WAT > 14)
 204 #define flash_EBIU_AMBCTL0_WAT  B0WAT_15
 205 #endif
 206 #if (flash_EBIU_AMBCTL_WAT == 14)
 207 #define flash_EBIU_AMBCTL0_WAT  B0WAT_14
 208 #endif
 209 #if (flash_EBIU_AMBCTL_WAT == 13)
 210 #define flash_EBIU_AMBCTL0_WAT  B0WAT_13
 211 #endif
 212 #if (flash_EBIU_AMBCTL_WAT == 12)
 213 #define flash_EBIU_AMBCTL0_WAT  B0WAT_12
 214 #endif
 215 #if (flash_EBIU_AMBCTL_WAT == 11)
 216 #define flash_EBIU_AMBCTL0_WAT  B0WAT_11
 217 #endif
 218 #if (flash_EBIU_AMBCTL_WAT == 10)
 219 #define flash_EBIU_AMBCTL0_WAT  B0WAT_10
 220 #endif
 221 #if (flash_EBIU_AMBCTL_WAT == 9)
 222 #define flash_EBIU_AMBCTL0_WAT  B0WAT_9
 223 #endif
 224 #if (flash_EBIU_AMBCTL_WAT == 8)
 225 #define flash_EBIU_AMBCTL0_WAT  B0WAT_8
 226 #endif
 227 #if (flash_EBIU_AMBCTL_WAT == 7)
 228 #define flash_EBIU_AMBCTL0_WAT  B0WAT_7
 229 #endif
 230 #if (flash_EBIU_AMBCTL_WAT == 6)
 231 #define flash_EBIU_AMBCTL0_WAT  B0WAT_6
 232 #endif
 233 #if (flash_EBIU_AMBCTL_WAT == 5)
 234 #define flash_EBIU_AMBCTL0_WAT  B0WAT_5
 235 #endif
 236 #if (flash_EBIU_AMBCTL_WAT == 4)
 237 #define flash_EBIU_AMBCTL0_WAT  B0WAT_4
 238 #endif
 239 #if (flash_EBIU_AMBCTL_WAT == 3)
 240 #define flash_EBIU_AMBCTL0_WAT  B0WAT_3
 241 #endif
 242 #if (flash_EBIU_AMBCTL_WAT == 2)
 243 #define flash_EBIU_AMBCTL0_WAT  B0WAT_2
 244 #endif
 245 #if (flash_EBIU_AMBCTL_WAT == 1)
 246 #define flash_EBIU_AMBCTL0_WAT  B0WAT_1
 247 #endif
 248
 249 #if (flash_EBIU_AMBCTL_RAT > 14)
 250 #define flash_EBIU_AMBCTL0_RAT  B0RAT_15
 251 #endif
 252 #if (flash_EBIU_AMBCTL_RAT == 14)
 253 #define flash_EBIU_AMBCTL0_RAT  B0RAT_14
 254 #endif
 255 #if (flash_EBIU_AMBCTL_RAT == 13)
 256 #define flash_EBIU_AMBCTL0_RAT  B0RAT_13
 257 #endif
 258 #if (flash_EBIU_AMBCTL_RAT == 12)
 259 #define flash_EBIU_AMBCTL0_RAT  B0RAT_12
 260 #endif
 261 #if (flash_EBIU_AMBCTL_RAT == 11)
 262 #define flash_EBIU_AMBCTL0_RAT  B0RAT_11
 263 #endif
 264 #if (flash_EBIU_AMBCTL_RAT == 10)
 265 #define flash_EBIU_AMBCTL0_RAT  B0RAT_10
 266 #endif
 267 #if (flash_EBIU_AMBCTL_RAT == 9)
 268 #define flash_EBIU_AMBCTL0_RAT  B0RAT_9
 269 #endif
 270 #if (flash_EBIU_AMBCTL_RAT == 8)
 271 #define flash_EBIU_AMBCTL0_RAT  B0RAT_8
 272 #endif
 273 #if (flash_EBIU_AMBCTL_RAT == 7)
 274 #define flash_EBIU_AMBCTL0_RAT  B0RAT_7
 275 #endif
 276 #if (flash_EBIU_AMBCTL_RAT == 6)
 277 #define flash_EBIU_AMBCTL0_RAT  B0RAT_6
 278 #endif
 279 #if (flash_EBIU_AMBCTL_RAT == 5)
 280 #define flash_EBIU_AMBCTL0_RAT  B0RAT_5
 281 #endif
 282 #if (flash_EBIU_AMBCTL_RAT == 4)
 283 #define flash_EBIU_AMBCTL0_RAT  B0RAT_4
 284 #endif
 285 #if (flash_EBIU_AMBCTL_RAT == 3)
 286 #define flash_EBIU_AMBCTL0_RAT  B0RAT_3
 287 #endif
 288 #if (flash_EBIU_AMBCTL_RAT == 2)
 289 #define flash_EBIU_AMBCTL0_RAT  B0RAT_2
 290 #endif
 291 #if (flash_EBIU_AMBCTL_RAT == 1)
 292 #define flash_EBIU_AMBCTL0_RAT  B0RAT_1
 293 #endif
 294
 295 #define flash_EBIU_AMBCTL0  \
 296         (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
 297          flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)