2 * sun4i-ss-core.c - hardware cryptographic accelerator for Allwinner A20 SoC
4 * Copyright (C) 2013-2015 Corentin LABBE <clabbe.montjoie@gmail.com>
6 * Core file which registers crypto algorithms supported by the SS.
8 * You could find a link for the datasheet in Documentation/arm/sunxi/README
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 #include <linux/clk.h>
16 #include <linux/crypto.h>
18 #include <linux/module.h>
20 #include <linux/platform_device.h>
21 #include <crypto/scatterwalk.h>
22 #include <linux/scatterlist.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
28 static struct sun4i_ss_alg_template ss_algs
[] = {
29 { .type
= CRYPTO_ALG_TYPE_AHASH
,
32 .init
= sun4i_hash_init
,
33 .update
= sun4i_hash_update
,
34 .final
= sun4i_hash_final
,
35 .finup
= sun4i_hash_finup
,
36 .digest
= sun4i_hash_digest
,
37 .export
= sun4i_hash_export_md5
,
38 .import
= sun4i_hash_import_md5
,
40 .digestsize
= MD5_DIGEST_SIZE
,
43 .cra_driver_name
= "md5-sun4i-ss",
46 .cra_flags
= CRYPTO_ALG_TYPE_AHASH
,
47 .cra_blocksize
= MD5_HMAC_BLOCK_SIZE
,
48 .cra_ctxsize
= sizeof(struct sun4i_req_ctx
),
49 .cra_module
= THIS_MODULE
,
50 .cra_type
= &crypto_ahash_type
,
51 .cra_init
= sun4i_hash_crainit
56 { .type
= CRYPTO_ALG_TYPE_AHASH
,
59 .init
= sun4i_hash_init
,
60 .update
= sun4i_hash_update
,
61 .final
= sun4i_hash_final
,
62 .finup
= sun4i_hash_finup
,
63 .digest
= sun4i_hash_digest
,
64 .export
= sun4i_hash_export_sha1
,
65 .import
= sun4i_hash_import_sha1
,
67 .digestsize
= SHA1_DIGEST_SIZE
,
70 .cra_driver_name
= "sha1-sun4i-ss",
73 .cra_flags
= CRYPTO_ALG_TYPE_AHASH
,
74 .cra_blocksize
= SHA1_BLOCK_SIZE
,
75 .cra_ctxsize
= sizeof(struct sun4i_req_ctx
),
76 .cra_module
= THIS_MODULE
,
77 .cra_type
= &crypto_ahash_type
,
78 .cra_init
= sun4i_hash_crainit
83 { .type
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
85 .cra_name
= "cbc(aes)",
86 .cra_driver_name
= "cbc-aes-sun4i-ss",
88 .cra_blocksize
= AES_BLOCK_SIZE
,
89 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
90 .cra_ctxsize
= sizeof(struct sun4i_tfm_ctx
),
91 .cra_module
= THIS_MODULE
,
93 .cra_type
= &crypto_ablkcipher_type
,
94 .cra_init
= sun4i_ss_cipher_init
,
96 .min_keysize
= AES_MIN_KEY_SIZE
,
97 .max_keysize
= AES_MAX_KEY_SIZE
,
98 .ivsize
= AES_BLOCK_SIZE
,
99 .setkey
= sun4i_ss_aes_setkey
,
100 .encrypt
= sun4i_ss_cbc_aes_encrypt
,
101 .decrypt
= sun4i_ss_cbc_aes_decrypt
,
105 { .type
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
107 .cra_name
= "ecb(aes)",
108 .cra_driver_name
= "ecb-aes-sun4i-ss",
110 .cra_blocksize
= AES_BLOCK_SIZE
,
111 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
112 .cra_ctxsize
= sizeof(struct sun4i_tfm_ctx
),
113 .cra_module
= THIS_MODULE
,
115 .cra_type
= &crypto_ablkcipher_type
,
116 .cra_init
= sun4i_ss_cipher_init
,
118 .min_keysize
= AES_MIN_KEY_SIZE
,
119 .max_keysize
= AES_MAX_KEY_SIZE
,
120 .ivsize
= AES_BLOCK_SIZE
,
121 .setkey
= sun4i_ss_aes_setkey
,
122 .encrypt
= sun4i_ss_ecb_aes_encrypt
,
123 .decrypt
= sun4i_ss_ecb_aes_decrypt
,
127 { .type
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
129 .cra_name
= "cbc(des)",
130 .cra_driver_name
= "cbc-des-sun4i-ss",
132 .cra_blocksize
= DES_BLOCK_SIZE
,
133 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
134 .cra_ctxsize
= sizeof(struct sun4i_req_ctx
),
135 .cra_module
= THIS_MODULE
,
137 .cra_type
= &crypto_ablkcipher_type
,
138 .cra_init
= sun4i_ss_cipher_init
,
139 .cra_u
.ablkcipher
= {
140 .min_keysize
= DES_KEY_SIZE
,
141 .max_keysize
= DES_KEY_SIZE
,
142 .ivsize
= DES_BLOCK_SIZE
,
143 .setkey
= sun4i_ss_des_setkey
,
144 .encrypt
= sun4i_ss_cbc_des_encrypt
,
145 .decrypt
= sun4i_ss_cbc_des_decrypt
,
149 { .type
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
151 .cra_name
= "ecb(des)",
152 .cra_driver_name
= "ecb-des-sun4i-ss",
154 .cra_blocksize
= DES_BLOCK_SIZE
,
155 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
156 .cra_ctxsize
= sizeof(struct sun4i_req_ctx
),
157 .cra_module
= THIS_MODULE
,
159 .cra_type
= &crypto_ablkcipher_type
,
160 .cra_init
= sun4i_ss_cipher_init
,
161 .cra_u
.ablkcipher
= {
162 .min_keysize
= DES_KEY_SIZE
,
163 .max_keysize
= DES_KEY_SIZE
,
164 .setkey
= sun4i_ss_des_setkey
,
165 .encrypt
= sun4i_ss_ecb_des_encrypt
,
166 .decrypt
= sun4i_ss_ecb_des_decrypt
,
170 { .type
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
172 .cra_name
= "cbc(des3_ede)",
173 .cra_driver_name
= "cbc-des3-sun4i-ss",
175 .cra_blocksize
= DES3_EDE_BLOCK_SIZE
,
176 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
177 .cra_ctxsize
= sizeof(struct sun4i_req_ctx
),
178 .cra_module
= THIS_MODULE
,
180 .cra_type
= &crypto_ablkcipher_type
,
181 .cra_init
= sun4i_ss_cipher_init
,
182 .cra_u
.ablkcipher
= {
183 .min_keysize
= DES3_EDE_KEY_SIZE
,
184 .max_keysize
= DES3_EDE_KEY_SIZE
,
185 .ivsize
= DES3_EDE_BLOCK_SIZE
,
186 .setkey
= sun4i_ss_des3_setkey
,
187 .encrypt
= sun4i_ss_cbc_des3_encrypt
,
188 .decrypt
= sun4i_ss_cbc_des3_decrypt
,
192 { .type
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
194 .cra_name
= "ecb(des3_ede)",
195 .cra_driver_name
= "ecb-des3-sun4i-ss",
197 .cra_blocksize
= DES3_EDE_BLOCK_SIZE
,
198 .cra_flags
= CRYPTO_ALG_TYPE_ABLKCIPHER
,
199 .cra_ctxsize
= sizeof(struct sun4i_req_ctx
),
200 .cra_module
= THIS_MODULE
,
202 .cra_type
= &crypto_ablkcipher_type
,
203 .cra_init
= sun4i_ss_cipher_init
,
204 .cra_u
.ablkcipher
= {
205 .min_keysize
= DES3_EDE_KEY_SIZE
,
206 .max_keysize
= DES3_EDE_KEY_SIZE
,
207 .ivsize
= DES3_EDE_BLOCK_SIZE
,
208 .setkey
= sun4i_ss_des3_setkey
,
209 .encrypt
= sun4i_ss_ecb_des3_encrypt
,
210 .decrypt
= sun4i_ss_ecb_des3_decrypt
,
216 static int sun4i_ss_probe(struct platform_device
*pdev
)
218 struct resource
*res
;
222 const unsigned long cr_ahb
= 24 * 1000 * 1000;
223 const unsigned long cr_mod
= 150 * 1000 * 1000;
224 struct sun4i_ss_ctx
*ss
;
226 if (!pdev
->dev
.of_node
)
229 ss
= devm_kzalloc(&pdev
->dev
, sizeof(*ss
), GFP_KERNEL
);
233 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
234 ss
->base
= devm_ioremap_resource(&pdev
->dev
, res
);
235 if (IS_ERR(ss
->base
)) {
236 dev_err(&pdev
->dev
, "Cannot request MMIO\n");
237 return PTR_ERR(ss
->base
);
240 ss
->ssclk
= devm_clk_get(&pdev
->dev
, "mod");
241 if (IS_ERR(ss
->ssclk
)) {
242 err
= PTR_ERR(ss
->ssclk
);
243 dev_err(&pdev
->dev
, "Cannot get SS clock err=%d\n", err
);
246 dev_dbg(&pdev
->dev
, "clock ss acquired\n");
248 ss
->busclk
= devm_clk_get(&pdev
->dev
, "ahb");
249 if (IS_ERR(ss
->busclk
)) {
250 err
= PTR_ERR(ss
->busclk
);
251 dev_err(&pdev
->dev
, "Cannot get AHB SS clock err=%d\n", err
);
254 dev_dbg(&pdev
->dev
, "clock ahb_ss acquired\n");
256 /* Enable both clocks */
257 err
= clk_prepare_enable(ss
->busclk
);
259 dev_err(&pdev
->dev
, "Cannot prepare_enable busclk\n");
262 err
= clk_prepare_enable(ss
->ssclk
);
264 dev_err(&pdev
->dev
, "Cannot prepare_enable ssclk\n");
269 * Check that clock have the correct rates given in the datasheet
270 * Try to set the clock to the maximum allowed
272 err
= clk_set_rate(ss
->ssclk
, cr_mod
);
274 dev_err(&pdev
->dev
, "Cannot set clock rate to ssclk\n");
279 * The only impact on clocks below requirement are bad performance,
280 * so do not print "errors"
281 * warn on Overclocked clocks
283 cr
= clk_get_rate(ss
->busclk
);
285 dev_dbg(&pdev
->dev
, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
286 cr
, cr
/ 1000000, cr_ahb
);
288 dev_warn(&pdev
->dev
, "Clock bus %lu (%lu MHz) (must be >= %lu)\n",
289 cr
, cr
/ 1000000, cr_ahb
);
291 cr
= clk_get_rate(ss
->ssclk
);
294 dev_warn(&pdev
->dev
, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
295 cr
, cr
/ 1000000, cr_mod
);
297 dev_dbg(&pdev
->dev
, "Clock ss %lu (%lu MHz) (must be <= %lu)\n",
298 cr
, cr
/ 1000000, cr_mod
);
300 dev_warn(&pdev
->dev
, "Clock ss is at %lu (%lu MHz) (must be <= %lu)\n",
301 cr
, cr
/ 1000000, cr_mod
);
304 * Datasheet named it "Die Bonding ID"
305 * I expect to be a sort of Security System Revision number.
306 * Since the A80 seems to have an other version of SS
307 * this info could be useful
309 writel(SS_ENABLED
, ss
->base
+ SS_CTL
);
310 v
= readl(ss
->base
+ SS_CTL
);
313 dev_info(&pdev
->dev
, "Die ID %d\n", v
);
314 writel(0, ss
->base
+ SS_CTL
);
316 ss
->dev
= &pdev
->dev
;
318 spin_lock_init(&ss
->slock
);
320 for (i
= 0; i
< ARRAY_SIZE(ss_algs
); i
++) {
322 switch (ss_algs
[i
].type
) {
323 case CRYPTO_ALG_TYPE_ABLKCIPHER
:
324 err
= crypto_register_alg(&ss_algs
[i
].alg
.crypto
);
326 dev_err(ss
->dev
, "Fail to register %s\n",
327 ss_algs
[i
].alg
.crypto
.cra_name
);
331 case CRYPTO_ALG_TYPE_AHASH
:
332 err
= crypto_register_ahash(&ss_algs
[i
].alg
.hash
);
334 dev_err(ss
->dev
, "Fail to register %s\n",
335 ss_algs
[i
].alg
.hash
.halg
.base
.cra_name
);
341 platform_set_drvdata(pdev
, ss
);
345 for (; i
>= 0; i
--) {
346 switch (ss_algs
[i
].type
) {
347 case CRYPTO_ALG_TYPE_ABLKCIPHER
:
348 crypto_unregister_alg(&ss_algs
[i
].alg
.crypto
);
350 case CRYPTO_ALG_TYPE_AHASH
:
351 crypto_unregister_ahash(&ss_algs
[i
].alg
.hash
);
356 clk_disable_unprepare(ss
->ssclk
);
358 clk_disable_unprepare(ss
->busclk
);
362 static int sun4i_ss_remove(struct platform_device
*pdev
)
365 struct sun4i_ss_ctx
*ss
= platform_get_drvdata(pdev
);
367 for (i
= 0; i
< ARRAY_SIZE(ss_algs
); i
++) {
368 switch (ss_algs
[i
].type
) {
369 case CRYPTO_ALG_TYPE_ABLKCIPHER
:
370 crypto_unregister_alg(&ss_algs
[i
].alg
.crypto
);
372 case CRYPTO_ALG_TYPE_AHASH
:
373 crypto_unregister_ahash(&ss_algs
[i
].alg
.hash
);
378 writel(0, ss
->base
+ SS_CTL
);
379 clk_disable_unprepare(ss
->busclk
);
380 clk_disable_unprepare(ss
->ssclk
);
384 static const struct of_device_id a20ss_crypto_of_match_table
[] = {
385 { .compatible
= "allwinner,sun4i-a10-crypto" },
388 MODULE_DEVICE_TABLE(of
, a20ss_crypto_of_match_table
);
390 static struct platform_driver sun4i_ss_driver
= {
391 .probe
= sun4i_ss_probe
,
392 .remove
= sun4i_ss_remove
,
395 .of_match_table
= a20ss_crypto_of_match_table
,
399 module_platform_driver(sun4i_ss_driver
);
401 MODULE_DESCRIPTION("Allwinner Security System cryptographic accelerator");
402 MODULE_LICENSE("GPL");
403 MODULE_AUTHOR("Corentin LABBE <clabbe.montjoie@gmail.com>");