drivers/clk/meson/meson8b-clkc.c

   1 /*
   2  * Copyright (c) 2015 Endless Mobile, Inc.
   3  * Author: Carlo Caione <carlo@endlessm.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms and conditions of the GNU General Public License,
   7  * version 2, as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/clk-provider.h>
  19 #include <linux/kernel.h>
  20 #include <linux/of.h>
  21 #include <linux/of_address.h>
  22 #include <linux/slab.h>
  23 #include <dt-bindings/clock/meson8b-clkc.h>
  24
  25 #include "clkc.h"
  26
  27 /*
  28  * Clock controller register offsets
  29  *
  30  * Register offsets from the HardKernel[0] data sheet are listed in comment
  31  * blocks below. Those offsets must be multiplied by 4 before adding them to
  32  * the base address to get the right value
  33  *
  34  * [0] http://dn.odroid.com/S805/Datasheet/S805_Datasheet%20V0.8%2020150126.pdf
  35  */
  36 #define MESON8B_REG_SYS_CPU_CNTL1       0x015c /* 0x57 offset in data sheet */
  37 #define MESON8B_REG_HHI_MPEG            0x0174 /* 0x5d offset in data sheet */
  38 #define MESON8B_REG_MALI                0x01b0 /* 0x6c offset in data sheet */
  39 #define MESON8B_REG_PLL_FIXED           0x0280
  40 #define MESON8B_REG_PLL_SYS             0x0300
  41 #define MESON8B_REG_PLL_VID             0x0320
  42
  43 static const struct pll_rate_table sys_pll_rate_table[] = {
  44         PLL_RATE(312000000, 52, 1, 2),
  45         PLL_RATE(336000000, 56, 1, 2),
  46         PLL_RATE(360000000, 60, 1, 2),
  47         PLL_RATE(384000000, 64, 1, 2),
  48         PLL_RATE(408000000, 68, 1, 2),
  49         PLL_RATE(432000000, 72, 1, 2),
  50         PLL_RATE(456000000, 76, 1, 2),
  51         PLL_RATE(480000000, 80, 1, 2),
  52         PLL_RATE(504000000, 84, 1, 2),
  53         PLL_RATE(528000000, 88, 1, 2),
  54         PLL_RATE(552000000, 92, 1, 2),
  55         PLL_RATE(576000000, 96, 1, 2),
  56         PLL_RATE(600000000, 50, 1, 1),
  57         PLL_RATE(624000000, 52, 1, 1),
  58         PLL_RATE(648000000, 54, 1, 1),
  59         PLL_RATE(672000000, 56, 1, 1),
  60         PLL_RATE(696000000, 58, 1, 1),
  61         PLL_RATE(720000000, 60, 1, 1),
  62         PLL_RATE(744000000, 62, 1, 1),
  63         PLL_RATE(768000000, 64, 1, 1),
  64         PLL_RATE(792000000, 66, 1, 1),
  65         PLL_RATE(816000000, 68, 1, 1),
  66         PLL_RATE(840000000, 70, 1, 1),
  67         PLL_RATE(864000000, 72, 1, 1),
  68         PLL_RATE(888000000, 74, 1, 1),
  69         PLL_RATE(912000000, 76, 1, 1),
  70         PLL_RATE(936000000, 78, 1, 1),
  71         PLL_RATE(960000000, 80, 1, 1),
  72         PLL_RATE(984000000, 82, 1, 1),
  73         PLL_RATE(1008000000, 84, 1, 1),
  74         PLL_RATE(1032000000, 86, 1, 1),
  75         PLL_RATE(1056000000, 88, 1, 1),
  76         PLL_RATE(1080000000, 90, 1, 1),
  77         PLL_RATE(1104000000, 92, 1, 1),
  78         PLL_RATE(1128000000, 94, 1, 1),
  79         PLL_RATE(1152000000, 96, 1, 1),
  80         PLL_RATE(1176000000, 98, 1, 1),
  81         PLL_RATE(1200000000, 50, 1, 0),
  82         PLL_RATE(1224000000, 51, 1, 0),
  83         PLL_RATE(1248000000, 52, 1, 0),
  84         PLL_RATE(1272000000, 53, 1, 0),
  85         PLL_RATE(1296000000, 54, 1, 0),
  86         PLL_RATE(1320000000, 55, 1, 0),
  87         PLL_RATE(1344000000, 56, 1, 0),
  88         PLL_RATE(1368000000, 57, 1, 0),
  89         PLL_RATE(1392000000, 58, 1, 0),
  90         PLL_RATE(1416000000, 59, 1, 0),
  91         PLL_RATE(1440000000, 60, 1, 0),
  92         PLL_RATE(1464000000, 61, 1, 0),
  93         PLL_RATE(1488000000, 62, 1, 0),
  94         PLL_RATE(1512000000, 63, 1, 0),
  95         PLL_RATE(1536000000, 64, 1, 0),
  96         { /* sentinel */ },
  97 };
  98
  99 static const struct clk_div_table cpu_div_table[] = {
 100         { .val = 1, .div = 1 },
 101         { .val = 2, .div = 2 },
 102         { .val = 3, .div = 3 },
 103         { .val = 2, .div = 4 },
 104         { .val = 3, .div = 6 },
 105         { .val = 4, .div = 8 },
 106         { .val = 5, .div = 10 },
 107         { .val = 6, .div = 12 },
 108         { .val = 7, .div = 14 },
 109         { .val = 8, .div = 16 },
 110         { /* sentinel */ },
 111 };
 112
 113 PNAME(p_cpu_clk)        = { "sys_pll" };
 114 PNAME(p_clk81)          = { "fclk_div3", "fclk_div4", "fclk_div5" };
 115 PNAME(p_mali)           = { "fclk_div3", "fclk_div4", "fclk_div5",
 116                             "fclk_div7", "zero" };
 117
 118 static u32 mux_table_clk81[]    = { 6, 5, 7 };
 119 static u32 mux_table_mali[]     = { 6, 5, 7, 4, 0 };
 120
 121 static const struct composite_conf clk81_conf __initconst = {
 122         .mux_table              = mux_table_clk81,
 123         .mux_flags              = CLK_MUX_READ_ONLY,
 124         .mux_parm               = PARM(0x00, 12, 3),
 125         .div_parm               = PARM(0x00, 0, 7),
 126         .gate_parm              = PARM(0x00, 7, 1),
 127 };
 128
 129 static const struct composite_conf mali_conf __initconst = {
 130         .mux_table              = mux_table_mali,
 131         .mux_parm               = PARM(0x00, 9, 3),
 132         .div_parm               = PARM(0x00, 0, 7),
 133         .gate_parm              = PARM(0x00, 8, 1),
 134 };
 135
 136 static struct clk_fixed_rate meson8b_xtal = {
 137         .fixed_rate = 24000000,
 138         .hw.init = &(struct clk_init_data){
 139                 .name = "xtal",
 140                 .num_parents = 0,
 141                 .ops = &clk_fixed_rate_ops,
 142         },
 143 };
 144
 145 static struct clk_fixed_rate meson8b_zero = {
 146         .fixed_rate = 0,
 147         .hw.init = &(struct clk_init_data){
 148                 .name = "zero",
 149                 .num_parents = 0,
 150                 .ops = &clk_fixed_rate_ops,
 151         },
 152 };
 153
 154 static struct meson_clk_pll meson8b_fixed_pll = {
 155         .m = {
 156                 .reg_off = MESON8B_REG_PLL_FIXED,
 157                 .shift   = 0,
 158                 .width   = 9,
 159         },
 160         .n = {
 161                 .reg_off = MESON8B_REG_PLL_FIXED,
 162                 .shift   = 9,
 163                 .width   = 5,
 164         },
 165         .od = {
 166                 .reg_off = MESON8B_REG_PLL_FIXED,
 167                 .shift   = 16,
 168                 .width   = 2,
 169         },
 170         .lock = &clk_lock,
 171         .hw.init = &(struct clk_init_data){
 172                 .name = "fixed_pll",
 173                 .ops = &meson_clk_pll_ro_ops,
 174                 .parent_names = (const char *[]){ "xtal" },
 175                 .num_parents = 1,
 176                 .flags = CLK_GET_RATE_NOCACHE,
 177         },
 178 };
 179
 180 static struct meson_clk_pll meson8b_vid_pll = {
 181         .m = {
 182                 .reg_off = MESON8B_REG_PLL_VID,
 183                 .shift   = 0,
 184                 .width   = 9,
 185         },
 186         .n = {
 187                 .reg_off = MESON8B_REG_PLL_VID,
 188                 .shift   = 9,
 189                 .width   = 5,
 190         },
 191         .od = {
 192                 .reg_off = MESON8B_REG_PLL_VID,
 193                 .shift   = 16,
 194                 .width   = 2,
 195         },
 196         .lock = &clk_lock,
 197         .hw.init = &(struct clk_init_data){
 198                 .name = "vid_pll",
 199                 .ops = &meson_clk_pll_ro_ops,
 200                 .parent_names = (const char *[]){ "xtal" },
 201                 .num_parents = 1,
 202                 .flags = CLK_GET_RATE_NOCACHE,
 203         },
 204 };
 205
 206 static struct meson_clk_pll meson8b_sys_pll = {
 207         .m = {
 208                 .reg_off = MESON8B_REG_PLL_SYS,
 209                 .shift   = 0,
 210                 .width   = 9,
 211         },
 212         .n = {
 213                 .reg_off = MESON8B_REG_PLL_SYS,
 214                 .shift   = 9,
 215                 .width   = 5,
 216         },
 217         .od = {
 218                 .reg_off = MESON8B_REG_PLL_SYS,
 219                 .shift   = 16,
 220                 .width   = 2,
 221         },
 222         .rate_table = sys_pll_rate_table,
 223         .rate_count = ARRAY_SIZE(sys_pll_rate_table),
 224         .lock = &clk_lock,
 225         .hw.init = &(struct clk_init_data){
 226                 .name = "sys_pll",
 227                 .ops = &meson_clk_pll_ops,
 228                 .parent_names = (const char *[]){ "xtal" },
 229                 .num_parents = 1,
 230                 .flags = CLK_GET_RATE_NOCACHE,
 231         },
 232 };
 233
 234 static struct clk_fixed_factor meson8b_fclk_div2 = {
 235         .mult = 1,
 236         .div = 2,
 237         .hw.init = &(struct clk_init_data){
 238                 .name = "fclk_div2",
 239                 .ops = &clk_fixed_factor_ops,
 240                 .parent_names = (const char *[]){ "fixed_pll" },
 241                 .num_parents = 1,
 242         },
 243 };
 244
 245 static struct clk_fixed_factor meson8b_fclk_div3 = {
 246         .mult = 1,
 247         .div = 3,
 248         .hw.init = &(struct clk_init_data){
 249                 .name = "fclk_div3",
 250                 .ops = &clk_fixed_factor_ops,
 251                 .parent_names = (const char *[]){ "fixed_pll" },
 252                 .num_parents = 1,
 253         },
 254 };
 255
 256 static struct clk_fixed_factor meson8b_fclk_div4 = {
 257         .mult = 1,
 258         .div = 4,
 259         .hw.init = &(struct clk_init_data){
 260                 .name = "fclk_div4",
 261                 .ops = &clk_fixed_factor_ops,
 262                 .parent_names = (const char *[]){ "fixed_pll" },
 263                 .num_parents = 1,
 264         },
 265 };
 266
 267 static struct clk_fixed_factor meson8b_fclk_div5 = {
 268         .mult = 1,
 269         .div = 5,
 270         .hw.init = &(struct clk_init_data){
 271                 .name = "fclk_div5",
 272                 .ops = &clk_fixed_factor_ops,
 273                 .parent_names = (const char *[]){ "fixed_pll" },
 274                 .num_parents = 1,
 275         },
 276 };
 277
 278 static struct clk_fixed_factor meson8b_fclk_div7 = {
 279         .mult = 1,
 280         .div = 7,
 281         .hw.init = &(struct clk_init_data){
 282                 .name = "fclk_div7",
 283                 .ops = &clk_fixed_factor_ops,
 284                 .parent_names = (const char *[]){ "fixed_pll" },
 285                 .num_parents = 1,
 286         },
 287 };
 288
 289 static const struct clk_conf meson8b_clk_confs[] __initconst = {
 290         CPU(MESON8B_REG_SYS_CPU_CNTL1, CLKID_CPUCLK, "a5_clk", p_cpu_clk,
 291             cpu_div_table),
 292         COMPOSITE(MESON8B_REG_HHI_MPEG, CLKID_CLK81, "clk81", p_clk81,
 293                   CLK_SET_RATE_NO_REPARENT | CLK_IGNORE_UNUSED, &clk81_conf),
 294         COMPOSITE(MESON8B_REG_MALI, CLKID_MALI, "mali", p_mali,
 295                   CLK_IGNORE_UNUSED, &mali_conf),
 296 };
 297
 298 /*
 299  * FIXME we cannot register two providers w/o breaking things. Luckily only
 300  * clk81 is actually used by any drivers. Convert clk81 to use
 301  * clk_hw_onecell_data last and flip the switch to call of_clk_add_hw_provider
 302  * instead of of_clk_add_provider in the clk81 conversion patch to keep from
 303  * breaking bisect. Then delete this comment ;-)
 304  */
 305 static struct clk_hw_onecell_data meson8b_hw_onecell_data = {
 306         .hws = {
 307                 [CLKID_XTAL] = &meson8b_xtal.hw,
 308                 [CLKID_ZERO] = &meson8b_zero.hw,
 309                 [CLKID_PLL_FIXED] = &meson8b_fixed_pll.hw,
 310                 [CLKID_PLL_VID] = &meson8b_vid_pll.hw,
 311                 [CLKID_PLL_SYS] = &meson8b_sys_pll.hw,
 312                 [CLKID_FCLK_DIV2] = &meson8b_fclk_div2.hw,
 313                 [CLKID_FCLK_DIV3] = &meson8b_fclk_div3.hw,
 314                 [CLKID_FCLK_DIV4] = &meson8b_fclk_div4.hw,
 315                 [CLKID_FCLK_DIV5] = &meson8b_fclk_div5.hw,
 316                 [CLKID_FCLK_DIV7] = &meson8b_fclk_div7.hw,
 317         },
 318         .num = CLK_NR_CLKS,
 319 };
 320
 321 static struct meson_clk_pll *const meson8b_clk_plls[] = {
 322         &meson8b_fixed_pll,
 323         &meson8b_vid_pll,
 324         &meson8b_sys_pll,
 325 };
 326
 327 static void __init meson8b_clkc_init(struct device_node *np)
 328 {
 329         void __iomem *clk_base;
 330         int ret, clkid, i;
 331
 332         if (!meson_clk_init(np, CLK_NR_CLKS))
 333                 return;
 334
 335         /*  Generic clocks and PLLs */
 336         clk_base = of_iomap(np, 1);
 337         if (!clk_base) {
 338                 pr_err("%s: Unable to map clk base\n", __func__);
 339                 return;
 340         }
 341
 342         /* Populate base address for PLLs */
 343         for (i = 0; i < ARRAY_SIZE(meson8b_clk_plls); i++)
 344                 meson8b_clk_plls[i]->base = clk_base;
 345
 346         /*
 347          * register all clks
 348          * CLKID_UNUSED = 0, so skip it and start with CLKID_XTAL = 1
 349          */
 350         for (clkid = CLKID_XTAL; clkid < CLK_NR_CLKS; clkid++) {
 351                 /* array might be sparse */
 352                 if (!meson8b_hw_onecell_data.hws[clkid])
 353                         continue;
 354
 355                 /* FIXME convert to devm_clk_register */
 356                 ret = clk_hw_register(NULL, meson8b_hw_onecell_data.hws[clkid]);
 357                 if (ret)
 358                         goto unregister;
 359         }
 360
 361         meson_clk_register_clks(meson8b_clk_confs,
 362                                 ARRAY_SIZE(meson8b_clk_confs),
 363                                 clk_base);
 364         return;
 365
 366 /* FIXME remove after converting to platform_driver/devm_clk_register */
 367 unregister:
 368         for (clkid = CLK_NR_CLKS - 1; clkid >= 0; clkid--)
 369                 clk_hw_unregister(meson8b_hw_onecell_data.hws[clkid]);
 370 }
 371 CLK_OF_DECLARE(meson8b_clock, "amlogic,meson8b-clkc", meson8b_clkc_init);