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net: benet: slight optimization of addr compare
[linux-2.6/btrfs-unstable.git] / drivers / ata / ahci.c
blob14f1e95063380a5e2a315428fc8a4d5e8bcc39d3
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Tejun Heo <tj@kernel.org>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/dma-mapping.h>
43 #include <linux/device.h>
44 #include <linux/dmi.h>
45 #include <linux/gfp.h>
46 #include <scsi/scsi_host.h>
47 #include <scsi/scsi_cmnd.h>
48 #include <linux/libata.h>
49 #include "ahci.h"
50
51 #define DRV_NAME "ahci"
52 #define DRV_VERSION "3.0"
53
54 enum {
55 AHCI_PCI_BAR_STA2X11 = 0,
56 AHCI_PCI_BAR_ENMOTUS = 2,
57 AHCI_PCI_BAR_STANDARD = 5,
58 };
59
60 enum board_ids {
61 /* board IDs by feature in alphabetical order */
62 board_ahci,
63 board_ahci_ign_iferr,
64 board_ahci_nosntf,
65 board_ahci_yes_fbs,
66
67 /* board IDs for specific chipsets in alphabetical order */
68 board_ahci_mcp65,
69 board_ahci_mcp77,
70 board_ahci_mcp89,
71 board_ahci_mv,
72 board_ahci_sb600,
73 board_ahci_sb700, /* for SB700 and SB800 */
74 board_ahci_vt8251,
75
76 /* aliases */
77 board_ahci_mcp_linux = board_ahci_mcp65,
78 board_ahci_mcp67 = board_ahci_mcp65,
79 board_ahci_mcp73 = board_ahci_mcp65,
80 board_ahci_mcp79 = board_ahci_mcp77,
81 };
82
83 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
84 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
85 unsigned long deadline);
86 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
87 unsigned long deadline);
88 #ifdef CONFIG_PM
89 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
90 static int ahci_pci_device_resume(struct pci_dev *pdev);
91 #endif
92
93 static struct scsi_host_template ahci_sht = {
94 AHCI_SHT("ahci"),
95 };
96
97 static struct ata_port_operations ahci_vt8251_ops = {
98 .inherits = &ahci_ops,
99 .hardreset = ahci_vt8251_hardreset,
100 };
101
102 static struct ata_port_operations ahci_p5wdh_ops = {
103 .inherits = &ahci_ops,
104 .hardreset = ahci_p5wdh_hardreset,
105 };
106
107 static const struct ata_port_info ahci_port_info[] = {
108 /* by features */
109 [board_ahci] = {
110 .flags = AHCI_FLAG_COMMON,
111 .pio_mask = ATA_PIO4,
112 .udma_mask = ATA_UDMA6,
113 .port_ops = &ahci_ops,
114 },
115 [board_ahci_ign_iferr] = {
116 AHCI_HFLAGS (AHCI_HFLAG_IGN_IRQ_IF_ERR),
117 .flags = AHCI_FLAG_COMMON,
118 .pio_mask = ATA_PIO4,
119 .udma_mask = ATA_UDMA6,
120 .port_ops = &ahci_ops,
121 },
122 [board_ahci_nosntf] = {
123 AHCI_HFLAGS (AHCI_HFLAG_NO_SNTF),
124 .flags = AHCI_FLAG_COMMON,
125 .pio_mask = ATA_PIO4,
126 .udma_mask = ATA_UDMA6,
127 .port_ops = &ahci_ops,
128 },
129 [board_ahci_yes_fbs] = {
130 AHCI_HFLAGS (AHCI_HFLAG_YES_FBS),
131 .flags = AHCI_FLAG_COMMON,
132 .pio_mask = ATA_PIO4,
133 .udma_mask = ATA_UDMA6,
134 .port_ops = &ahci_ops,
135 },
136 /* by chipsets */
137 [board_ahci_mcp65] = {
138 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
139 AHCI_HFLAG_YES_NCQ),
140 .flags = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
141 .pio_mask = ATA_PIO4,
142 .udma_mask = ATA_UDMA6,
143 .port_ops = &ahci_ops,
144 },
145 [board_ahci_mcp77] = {
146 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
147 .flags = AHCI_FLAG_COMMON,
148 .pio_mask = ATA_PIO4,
149 .udma_mask = ATA_UDMA6,
150 .port_ops = &ahci_ops,
151 },
152 [board_ahci_mcp89] = {
153 AHCI_HFLAGS (AHCI_HFLAG_NO_FPDMA_AA),
154 .flags = AHCI_FLAG_COMMON,
155 .pio_mask = ATA_PIO4,
156 .udma_mask = ATA_UDMA6,
157 .port_ops = &ahci_ops,
158 },
159 [board_ahci_mv] = {
160 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
161 AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
162 .flags = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
163 .pio_mask = ATA_PIO4,
164 .udma_mask = ATA_UDMA6,
165 .port_ops = &ahci_ops,
166 },
167 [board_ahci_sb600] = {
168 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL |
169 AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
170 AHCI_HFLAG_32BIT_ONLY),
171 .flags = AHCI_FLAG_COMMON,
172 .pio_mask = ATA_PIO4,
173 .udma_mask = ATA_UDMA6,
174 .port_ops = &ahci_pmp_retry_srst_ops,
175 },
176 [board_ahci_sb700] = { /* for SB700 and SB800 */
177 AHCI_HFLAGS (AHCI_HFLAG_IGN_SERR_INTERNAL),
178 .flags = AHCI_FLAG_COMMON,
179 .pio_mask = ATA_PIO4,
180 .udma_mask = ATA_UDMA6,
181 .port_ops = &ahci_pmp_retry_srst_ops,
182 },
183 [board_ahci_vt8251] = {
184 AHCI_HFLAGS (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
185 .flags = AHCI_FLAG_COMMON,
186 .pio_mask = ATA_PIO4,
187 .udma_mask = ATA_UDMA6,
188 .port_ops = &ahci_vt8251_ops,
189 },
190 };
191
192 static const struct pci_device_id ahci_pci_tbl[] = {
193 /* Intel */
194 { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
195 { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
196 { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
197 { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
198 { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
199 { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
200 { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
201 { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
202 { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
203 { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
204 { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
205 { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
206 { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
207 { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
208 { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
209 { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
210 { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
211 { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
212 { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
213 { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
214 { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
215 { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
216 { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
217 { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
218 { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
219 { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
220 { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
221 { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
222 { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
223 { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
224 { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
225 { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
226 { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
227 { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
228 { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
229 { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
230 { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
231 { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
232 { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
233 { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
234 { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
235 { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
236 { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
237 { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
238 { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
239 { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
240 { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
241 { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
242 { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
243 { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
244 { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
245 { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
246 { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
247 { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
248 { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
249 { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
250 { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
251 { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
252 { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
253 { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
254 { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
255 { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
256 { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
257 { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
258 { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
259 { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
260 { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
261 { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
262 { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
263 { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
264 { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
265 { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
266 { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
267 { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
268 { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
269 { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
270 { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
271 { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
272 { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
273 { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
274 { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
275 { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
276 { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
277 { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
278 { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
279 { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
280 { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
281 { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
282 { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
283 { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
284 { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
285 { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
286 { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
287 { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
288 { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
289 { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
290 { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
291 { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
292 { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
293 { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
294 { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
295 { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
296 { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
297 { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
298 { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
299
300 /* JMicron 360/1/3/5/6, match class to avoid IDE function */
301 { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
302 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
303 /* JMicron 362B and 362C have an AHCI function with IDE class code */
304 { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
305 { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
306
307 /* ATI */
308 { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
309 { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
310 { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
311 { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
312 { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
313 { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
314 { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
315
316 /* AMD */
317 { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
318 { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
319 /* AMD is using RAID class only for ahci controllers */
320 { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
321 PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
322
323 /* VIA */
324 { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
325 { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
326
327 /* NVIDIA */
328 { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 }, /* MCP65 */
329 { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 }, /* MCP65 */
330 { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 }, /* MCP65 */
331 { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 }, /* MCP65 */
332 { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 }, /* MCP65 */
333 { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 }, /* MCP65 */
334 { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 }, /* MCP65 */
335 { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 }, /* MCP65 */
336 { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 }, /* MCP67 */
337 { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 }, /* MCP67 */
338 { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 }, /* MCP67 */
339 { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 }, /* MCP67 */
340 { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 }, /* MCP67 */
341 { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 }, /* MCP67 */
342 { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 }, /* MCP67 */
343 { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 }, /* MCP67 */
344 { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 }, /* MCP67 */
345 { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 }, /* MCP67 */
346 { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 }, /* MCP67 */
347 { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 }, /* MCP67 */
348 { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux }, /* Linux ID */
349 { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux }, /* Linux ID */
350 { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux }, /* Linux ID */
351 { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux }, /* Linux ID */
352 { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux }, /* Linux ID */
353 { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux }, /* Linux ID */
354 { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux }, /* Linux ID */
355 { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux }, /* Linux ID */
356 { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux }, /* Linux ID */
357 { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux }, /* Linux ID */
358 { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux }, /* Linux ID */
359 { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux }, /* Linux ID */
360 { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux }, /* Linux ID */
361 { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux }, /* Linux ID */
362 { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux }, /* Linux ID */
363 { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux }, /* Linux ID */
364 { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 }, /* MCP73 */
365 { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 }, /* MCP73 */
366 { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 }, /* MCP73 */
367 { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 }, /* MCP73 */
368 { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 }, /* MCP73 */
369 { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 }, /* MCP73 */
370 { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 }, /* MCP73 */
371 { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 }, /* MCP73 */
372 { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 }, /* MCP73 */
373 { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 }, /* MCP73 */
374 { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 }, /* MCP73 */
375 { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 }, /* MCP73 */
376 { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 }, /* MCP77 */
377 { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 }, /* MCP77 */
378 { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 }, /* MCP77 */
379 { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 }, /* MCP77 */
380 { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 }, /* MCP77 */
381 { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 }, /* MCP77 */
382 { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 }, /* MCP77 */
383 { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 }, /* MCP77 */
384 { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 }, /* MCP77 */
385 { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 }, /* MCP77 */
386 { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 }, /* MCP77 */
387 { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 }, /* MCP77 */
388 { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 }, /* MCP79 */
389 { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 }, /* MCP79 */
390 { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 }, /* MCP79 */
391 { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 }, /* MCP79 */
392 { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 }, /* MCP79 */
393 { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 }, /* MCP79 */
394 { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 }, /* MCP79 */
395 { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 }, /* MCP79 */
396 { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 }, /* MCP79 */
397 { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 }, /* MCP79 */
398 { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 }, /* MCP79 */
399 { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 }, /* MCP79 */
400 { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 }, /* MCP89 */
401 { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 }, /* MCP89 */
402 { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 }, /* MCP89 */
403 { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 }, /* MCP89 */
404 { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 }, /* MCP89 */
405 { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 }, /* MCP89 */
406 { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 }, /* MCP89 */
407 { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 }, /* MCP89 */
408 { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 }, /* MCP89 */
409 { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 }, /* MCP89 */
410 { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 }, /* MCP89 */
411 { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 }, /* MCP89 */
412
413 /* SiS */
414 { PCI_VDEVICE(SI, 0x1184), board_ahci }, /* SiS 966 */
415 { PCI_VDEVICE(SI, 0x1185), board_ahci }, /* SiS 968 */
416 { PCI_VDEVICE(SI, 0x0186), board_ahci }, /* SiS 968 */
417
418 /* ST Microelectronics */
419 { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci }, /* ST ConneXt */
420
421 /* Marvell */
422 { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv }, /* 6145 */
423 { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv }, /* 6121 */
424 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
425 .class = PCI_CLASS_STORAGE_SATA_AHCI,
426 .class_mask = 0xffffff,
427 .driver_data = board_ahci_yes_fbs }, /* 88se9128 */
428 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
429 .driver_data = board_ahci_yes_fbs }, /* 88se9125 */
430 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
431 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
432 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
433 .driver_data = board_ahci_yes_fbs }, /* 88se9172 */
434 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
435 .driver_data = board_ahci_yes_fbs }, /* 88se9172 on some Gigabyte */
436 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
437 .driver_data = board_ahci_yes_fbs },
438 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
439 .driver_data = board_ahci_yes_fbs },
440
441 /* Promise */
442 { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci }, /* PDC42819 */
443
444 /* Asmedia */
445 { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci }, /* ASM1060 */
446 { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci }, /* ASM1060 */
447 { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci }, /* ASM1061 */
448 { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci }, /* ASM1062 */
449
450 /* Enmotus */
451 { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
452
453 /* Generic, PCI class code for AHCI */
454 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
455 PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
456
457 { } /* terminate list */
458 };
459
460
461 static struct pci_driver ahci_pci_driver = {
462 .name = DRV_NAME,
463 .id_table = ahci_pci_tbl,
464 .probe = ahci_init_one,
465 .remove = ata_pci_remove_one,
466 #ifdef CONFIG_PM
467 .suspend = ahci_pci_device_suspend,
468 .resume = ahci_pci_device_resume,
469 #endif
470 };
471
472 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
473 static int marvell_enable;
474 #else
475 static int marvell_enable = 1;
476 #endif
477 module_param(marvell_enable, int, 0644);
478 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
479
480
481 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
482 struct ahci_host_priv *hpriv)
483 {
484 unsigned int force_port_map = 0;
485 unsigned int mask_port_map = 0;
486
487 if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
488 dev_info(&pdev->dev, "JMB361 has only one port\n");
489 force_port_map = 1;
490 }
491
492 /*
493 * Temporary Marvell 6145 hack: PATA port presence
494 * is asserted through the standard AHCI port
495 * presence register, as bit 4 (counting from 0)
496 */
497 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
498 if (pdev->device == 0x6121)
499 mask_port_map = 0x3;
500 else
501 mask_port_map = 0xf;
502 dev_info(&pdev->dev,
503 "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
504 }
505
506 ahci_save_initial_config(&pdev->dev, hpriv, force_port_map,
507 mask_port_map);
508 }
509
510 static int ahci_pci_reset_controller(struct ata_host *host)
511 {
512 struct pci_dev *pdev = to_pci_dev(host->dev);
513
514 ahci_reset_controller(host);
515
516 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
517 struct ahci_host_priv *hpriv = host->private_data;
518 u16 tmp16;
519
520 /* configure PCS */
521 pci_read_config_word(pdev, 0x92, &tmp16);
522 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
523 tmp16 |= hpriv->port_map;
524 pci_write_config_word(pdev, 0x92, tmp16);
525 }
526 }
527
528 return 0;
529 }
530
531 static void ahci_pci_init_controller(struct ata_host *host)
532 {
533 struct ahci_host_priv *hpriv = host->private_data;
534 struct pci_dev *pdev = to_pci_dev(host->dev);
535 void __iomem *port_mmio;
536 u32 tmp;
537 int mv;
538
539 if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
540 if (pdev->device == 0x6121)
541 mv = 2;
542 else
543 mv = 4;
544 port_mmio = __ahci_port_base(host, mv);
545
546 writel(0, port_mmio + PORT_IRQ_MASK);
547
548 /* clear port IRQ */
549 tmp = readl(port_mmio + PORT_IRQ_STAT);
550 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
551 if (tmp)
552 writel(tmp, port_mmio + PORT_IRQ_STAT);
553 }
554
555 ahci_init_controller(host);
556 }
557
558 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
559 unsigned long deadline)
560 {
561 struct ata_port *ap = link->ap;
562 bool online;
563 int rc;
564
565 DPRINTK("ENTER\n");
566
567 ahci_stop_engine(ap);
568
569 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
570 deadline, &online, NULL);
571
572 ahci_start_engine(ap);
573
574 DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
575
576 /* vt8251 doesn't clear BSY on signature FIS reception,
577 * request follow-up softreset.
578 */
579 return online ? -EAGAIN : rc;
580 }
581
582 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
583 unsigned long deadline)
584 {
585 struct ata_port *ap = link->ap;
586 struct ahci_port_priv *pp = ap->private_data;
587 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
588 struct ata_taskfile tf;
589 bool online;
590 int rc;
591
592 ahci_stop_engine(ap);
593
594 /* clear D2H reception area to properly wait for D2H FIS */
595 ata_tf_init(link->device, &tf);
596 tf.command = ATA_BUSY;
597 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
598
599 rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
600 deadline, &online, NULL);
601
602 ahci_start_engine(ap);
603
604 /* The pseudo configuration device on SIMG4726 attached to
605 * ASUS P5W-DH Deluxe doesn't send signature FIS after
606 * hardreset if no device is attached to the first downstream
607 * port && the pseudo device locks up on SRST w/ PMP==0. To
608 * work around this, wait for !BSY only briefly. If BSY isn't
609 * cleared, perform CLO and proceed to IDENTIFY (achieved by
610 * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
611 *
612 * Wait for two seconds. Devices attached to downstream port
613 * which can't process the following IDENTIFY after this will
614 * have to be reset again. For most cases, this should
615 * suffice while making probing snappish enough.
616 */
617 if (online) {
618 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
619 ahci_check_ready);
620 if (rc)
621 ahci_kick_engine(ap);
622 }
623 return rc;
624 }
625
626 #ifdef CONFIG_PM
627 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
628 {
629 struct ata_host *host = pci_get_drvdata(pdev);
630 struct ahci_host_priv *hpriv = host->private_data;
631 void __iomem *mmio = hpriv->mmio;
632 u32 ctl;
633
634 if (mesg.event & PM_EVENT_SUSPEND &&
635 hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
636 dev_err(&pdev->dev,
637 "BIOS update required for suspend/resume\n");
638 return -EIO;
639 }
640
641 if (mesg.event & PM_EVENT_SLEEP) {
642 /* AHCI spec rev1.1 section 8.3.3:
643 * Software must disable interrupts prior to requesting a
644 * transition of the HBA to D3 state.
645 */
646 ctl = readl(mmio + HOST_CTL);
647 ctl &= ~HOST_IRQ_EN;
648 writel(ctl, mmio + HOST_CTL);
649 readl(mmio + HOST_CTL); /* flush */
650 }
651
652 return ata_pci_device_suspend(pdev, mesg);
653 }
654
655 static int ahci_pci_device_resume(struct pci_dev *pdev)
656 {
657 struct ata_host *host = pci_get_drvdata(pdev);
658 int rc;
659
660 rc = ata_pci_device_do_resume(pdev);
661 if (rc)
662 return rc;
663
664 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
665 rc = ahci_pci_reset_controller(host);
666 if (rc)
667 return rc;
668
669 ahci_pci_init_controller(host);
670 }
671
672 ata_host_resume(host);
673
674 return 0;
675 }
676 #endif
677
678 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
679 {
680 int rc;
681
682 /*
683 * If the device fixup already set the dma_mask to some non-standard
684 * value, don't extend it here. This happens on STA2X11, for example.
685 */
686 if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
687 return 0;
688
689 if (using_dac &&
690 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
691 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
692 if (rc) {
693 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
694 if (rc) {
695 dev_err(&pdev->dev,
696 "64-bit DMA enable failed\n");
697 return rc;
698 }
699 }
700 } else {
701 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
702 if (rc) {
703 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
704 return rc;
705 }
706 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
707 if (rc) {
708 dev_err(&pdev->dev,
709 "32-bit consistent DMA enable failed\n");
710 return rc;
711 }
712 }
713 return 0;
714 }
715
716 static void ahci_pci_print_info(struct ata_host *host)
717 {
718 struct pci_dev *pdev = to_pci_dev(host->dev);
719 u16 cc;
720 const char *scc_s;
721
722 pci_read_config_word(pdev, 0x0a, &cc);
723 if (cc == PCI_CLASS_STORAGE_IDE)
724 scc_s = "IDE";
725 else if (cc == PCI_CLASS_STORAGE_SATA)
726 scc_s = "SATA";
727 else if (cc == PCI_CLASS_STORAGE_RAID)
728 scc_s = "RAID";
729 else
730 scc_s = "unknown";
731
732 ahci_print_info(host, scc_s);
733 }
734
735 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
736 * hardwired to on-board SIMG 4726. The chipset is ICH8 and doesn't
737 * support PMP and the 4726 either directly exports the device
738 * attached to the first downstream port or acts as a hardware storage
739 * controller and emulate a single ATA device (can be RAID 0/1 or some
740 * other configuration).
741 *
742 * When there's no device attached to the first downstream port of the
743 * 4726, "Config Disk" appears, which is a pseudo ATA device to
744 * configure the 4726. However, ATA emulation of the device is very
745 * lame. It doesn't send signature D2H Reg FIS after the initial
746 * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
747 *
748 * The following function works around the problem by always using
749 * hardreset on the port and not depending on receiving signature FIS
750 * afterward. If signature FIS isn't received soon, ATA class is
751 * assumed without follow-up softreset.
752 */
753 static void ahci_p5wdh_workaround(struct ata_host *host)
754 {
755 static struct dmi_system_id sysids[] = {
756 {
757 .ident = "P5W DH Deluxe",
758 .matches = {
759 DMI_MATCH(DMI_SYS_VENDOR,
760 "ASUSTEK COMPUTER INC"),
761 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
762 },
763 },
764 { }
765 };
766 struct pci_dev *pdev = to_pci_dev(host->dev);
767
768 if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
769 dmi_check_system(sysids)) {
770 struct ata_port *ap = host->ports[1];
771
772 dev_info(&pdev->dev,
773 "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
774
775 ap->ops = &ahci_p5wdh_ops;
776 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
777 }
778 }
779
780 /* only some SB600 ahci controllers can do 64bit DMA */
781 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
782 {
783 static const struct dmi_system_id sysids[] = {
784 /*
785 * The oldest version known to be broken is 0901 and
786 * working is 1501 which was released on 2007-10-26.
787 * Enable 64bit DMA on 1501 and anything newer.
788 *
789 * Please read bko#9412 for more info.
790 */
791 {
792 .ident = "ASUS M2A-VM",
793 .matches = {
794 DMI_MATCH(DMI_BOARD_VENDOR,
795 "ASUSTeK Computer INC."),
796 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
797 },
798 .driver_data = "20071026", /* yyyymmdd */
799 },
800 /*
801 * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
802 * support 64bit DMA.
803 *
804 * BIOS versions earlier than 1.5 had the Manufacturer DMI
805 * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
806 * This spelling mistake was fixed in BIOS version 1.5, so
807 * 1.5 and later have the Manufacturer as
808 * "MICRO-STAR INTERNATIONAL CO.,LTD".
809 * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
810 *
811 * BIOS versions earlier than 1.9 had a Board Product Name
812 * DMI field of "MS-7376". This was changed to be
813 * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
814 * match on DMI_BOARD_NAME of "MS-7376".
815 */
816 {
817 .ident = "MSI K9A2 Platinum",
818 .matches = {
819 DMI_MATCH(DMI_BOARD_VENDOR,
820 "MICRO-STAR INTER"),
821 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
822 },
823 },
824 /*
825 * All BIOS versions for the MSI K9AGM2 (MS-7327) support
826 * 64bit DMA.
827 *
828 * This board also had the typo mentioned above in the
829 * Manufacturer DMI field (fixed in BIOS version 1.5), so
830 * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
831 */
832 {
833 .ident = "MSI K9AGM2",
834 .matches = {
835 DMI_MATCH(DMI_BOARD_VENDOR,
836 "MICRO-STAR INTER"),
837 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
838 },
839 },
840 /*
841 * All BIOS versions for the Asus M3A support 64bit DMA.
842 * (all release versions from 0301 to 1206 were tested)
843 */
844 {
845 .ident = "ASUS M3A",
846 .matches = {
847 DMI_MATCH(DMI_BOARD_VENDOR,
848 "ASUSTeK Computer INC."),
849 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
850 },
851 },
852 { }
853 };
854 const struct dmi_system_id *match;
855 int year, month, date;
856 char buf[9];
857
858 match = dmi_first_match(sysids);
859 if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
860 !match)
861 return false;
862
863 if (!match->driver_data)
864 goto enable_64bit;
865
866 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
867 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
868
869 if (strcmp(buf, match->driver_data) >= 0)
870 goto enable_64bit;
871 else {
872 dev_warn(&pdev->dev,
873 "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
874 match->ident);
875 return false;
876 }
877
878 enable_64bit:
879 dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
880 return true;
881 }
882
883 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
884 {
885 static const struct dmi_system_id broken_systems[] = {
886 {
887 .ident = "HP Compaq nx6310",
888 .matches = {
889 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
890 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
891 },
892 /* PCI slot number of the controller */
893 .driver_data = (void *)0x1FUL,
894 },
895 {
896 .ident = "HP Compaq 6720s",
897 .matches = {
898 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
899 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
900 },
901 /* PCI slot number of the controller */
902 .driver_data = (void *)0x1FUL,
903 },
904
905 { } /* terminate list */
906 };
907 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
908
909 if (dmi) {
910 unsigned long slot = (unsigned long)dmi->driver_data;
911 /* apply the quirk only to on-board controllers */
912 return slot == PCI_SLOT(pdev->devfn);
913 }
914
915 return false;
916 }
917
918 static bool ahci_broken_suspend(struct pci_dev *pdev)
919 {
920 static const struct dmi_system_id sysids[] = {
921 /*
922 * On HP dv[4-6] and HDX18 with earlier BIOSen, link
923 * to the harddisk doesn't become online after
924 * resuming from STR. Warn and fail suspend.
925 *
926 * http://bugzilla.kernel.org/show_bug.cgi?id=12276
927 *
928 * Use dates instead of versions to match as HP is
929 * apparently recycling both product and version
930 * strings.
931 *
932 * http://bugzilla.kernel.org/show_bug.cgi?id=15462
933 */
934 {
935 .ident = "dv4",
936 .matches = {
937 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
938 DMI_MATCH(DMI_PRODUCT_NAME,
939 "HP Pavilion dv4 Notebook PC"),
940 },
941 .driver_data = "20090105", /* F.30 */
942 },
943 {
944 .ident = "dv5",
945 .matches = {
946 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
947 DMI_MATCH(DMI_PRODUCT_NAME,
948 "HP Pavilion dv5 Notebook PC"),
949 },
950 .driver_data = "20090506", /* F.16 */
951 },
952 {
953 .ident = "dv6",
954 .matches = {
955 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
956 DMI_MATCH(DMI_PRODUCT_NAME,
957 "HP Pavilion dv6 Notebook PC"),
958 },
959 .driver_data = "20090423", /* F.21 */
960 },
961 {
962 .ident = "HDX18",
963 .matches = {
964 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
965 DMI_MATCH(DMI_PRODUCT_NAME,
966 "HP HDX18 Notebook PC"),
967 },
968 .driver_data = "20090430", /* F.23 */
969 },
970 /*
971 * Acer eMachines G725 has the same problem. BIOS
972 * V1.03 is known to be broken. V3.04 is known to
973 * work. Between, there are V1.06, V2.06 and V3.03
974 * that we don't have much idea about. For now,
975 * blacklist anything older than V3.04.
976 *
977 * http://bugzilla.kernel.org/show_bug.cgi?id=15104
978 */
979 {
980 .ident = "G725",
981 .matches = {
982 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
983 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
984 },
985 .driver_data = "20091216", /* V3.04 */
986 },
987 { } /* terminate list */
988 };
989 const struct dmi_system_id *dmi = dmi_first_match(sysids);
990 int year, month, date;
991 char buf[9];
992
993 if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
994 return false;
995
996 dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
997 snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
998
999 return strcmp(buf, dmi->driver_data) < 0;
1000 }
1001
1002 static bool ahci_broken_online(struct pci_dev *pdev)
1003 {
1004 #define ENCODE_BUSDEVFN(bus, slot, func) \
1005 (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1006 static const struct dmi_system_id sysids[] = {
1007 /*
1008 * There are several gigabyte boards which use
1009 * SIMG5723s configured as hardware RAID. Certain
1010 * 5723 firmware revisions shipped there keep the link
1011 * online but fail to answer properly to SRST or
1012 * IDENTIFY when no device is attached downstream
1013 * causing libata to retry quite a few times leading
1014 * to excessive detection delay.
1015 *
1016 * As these firmwares respond to the second reset try
1017 * with invalid device signature, considering unknown
1018 * sig as offline works around the problem acceptably.
1019 */
1020 {
1021 .ident = "EP45-DQ6",
1022 .matches = {
1023 DMI_MATCH(DMI_BOARD_VENDOR,
1024 "Gigabyte Technology Co., Ltd."),
1025 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1026 },
1027 .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1028 },
1029 {
1030 .ident = "EP45-DS5",
1031 .matches = {
1032 DMI_MATCH(DMI_BOARD_VENDOR,
1033 "Gigabyte Technology Co., Ltd."),
1034 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1035 },
1036 .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1037 },
1038 { } /* terminate list */
1039 };
1040 #undef ENCODE_BUSDEVFN
1041 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1042 unsigned int val;
1043
1044 if (!dmi)
1045 return false;
1046
1047 val = (unsigned long)dmi->driver_data;
1048
1049 return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1050 }
1051
1052 #ifdef CONFIG_ATA_ACPI
1053 static void ahci_gtf_filter_workaround(struct ata_host *host)
1054 {
1055 static const struct dmi_system_id sysids[] = {
1056 /*
1057 * Aspire 3810T issues a bunch of SATA enable commands
1058 * via _GTF including an invalid one and one which is
1059 * rejected by the device. Among the successful ones
1060 * is FPDMA non-zero offset enable which when enabled
1061 * only on the drive side leads to NCQ command
1062 * failures. Filter it out.
1063 */
1064 {
1065 .ident = "Aspire 3810T",
1066 .matches = {
1067 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1068 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1069 },
1070 .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1071 },
1072 { }
1073 };
1074 const struct dmi_system_id *dmi = dmi_first_match(sysids);
1075 unsigned int filter;
1076 int i;
1077
1078 if (!dmi)
1079 return;
1080
1081 filter = (unsigned long)dmi->driver_data;
1082 dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1083 filter, dmi->ident);
1084
1085 for (i = 0; i < host->n_ports; i++) {
1086 struct ata_port *ap = host->ports[i];
1087 struct ata_link *link;
1088 struct ata_device *dev;
1089
1090 ata_for_each_link(link, ap, EDGE)
1091 ata_for_each_dev(dev, link, ALL)
1092 dev->gtf_filter |= filter;
1093 }
1094 }
1095 #else
1096 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1097 {}
1098 #endif
1099
1100 int ahci_init_interrupts(struct pci_dev *pdev, struct ahci_host_priv *hpriv)
1101 {
1102 int rc;
1103 unsigned int maxvec;
1104
1105 if (!(hpriv->flags & AHCI_HFLAG_NO_MSI)) {
1106 rc = pci_enable_msi_block_auto(pdev, &maxvec);
1107 if (rc > 0) {
1108 if ((rc == maxvec) || (rc == 1))
1109 return rc;
1110 /*
1111 * Assume that advantage of multipe MSIs is negated,
1112 * so fallback to single MSI mode to save resources
1113 */
1114 pci_disable_msi(pdev);
1115 if (!pci_enable_msi(pdev))
1116 return 1;
1117 }
1118 }
1119
1120 pci_intx(pdev, 1);
1121 return 0;
1122 }
1123
1124 /**
1125 * ahci_host_activate - start AHCI host, request IRQs and register it
1126 * @host: target ATA host
1127 * @irq: base IRQ number to request
1128 * @n_msis: number of MSIs allocated for this host
1129 * @irq_handler: irq_handler used when requesting IRQs
1130 * @irq_flags: irq_flags used when requesting IRQs
1131 *
1132 * Similar to ata_host_activate, but requests IRQs according to AHCI-1.1
1133 * when multiple MSIs were allocated. That is one MSI per port, starting
1134 * from @irq.
1135 *
1136 * LOCKING:
1137 * Inherited from calling layer (may sleep).
1138 *
1139 * RETURNS:
1140 * 0 on success, -errno otherwise.
1141 */
1142 int ahci_host_activate(struct ata_host *host, int irq, unsigned int n_msis)
1143 {
1144 int i, rc;
1145
1146 /* Sharing Last Message among several ports is not supported */
1147 if (n_msis < host->n_ports)
1148 return -EINVAL;
1149
1150 rc = ata_host_start(host);
1151 if (rc)
1152 return rc;
1153
1154 for (i = 0; i < host->n_ports; i++) {
1155 const char* desc;
1156 struct ahci_port_priv *pp = host->ports[i]->private_data;
1157
1158 /* pp is NULL for dummy ports */
1159 if (pp)
1160 desc = pp->irq_desc;
1161 else
1162 desc = dev_driver_string(host->dev);
1163
1164 rc = devm_request_threaded_irq(host->dev,
1165 irq + i, ahci_hw_interrupt, ahci_thread_fn, IRQF_SHARED,
1166 desc, host->ports[i]);
1167 if (rc)
1168 goto out_free_irqs;
1169 }
1170
1171 for (i = 0; i < host->n_ports; i++)
1172 ata_port_desc(host->ports[i], "irq %d", irq + i);
1173
1174 rc = ata_host_register(host, &ahci_sht);
1175 if (rc)
1176 goto out_free_all_irqs;
1177
1178 return 0;
1179
1180 out_free_all_irqs:
1181 i = host->n_ports;
1182 out_free_irqs:
1183 for (i--; i >= 0; i--)
1184 devm_free_irq(host->dev, irq + i, host->ports[i]);
1185
1186 return rc;
1187 }
1188
1189 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1190 {
1191 unsigned int board_id = ent->driver_data;
1192 struct ata_port_info pi = ahci_port_info[board_id];
1193 const struct ata_port_info *ppi[] = { &pi, NULL };
1194 struct device *dev = &pdev->dev;
1195 struct ahci_host_priv *hpriv;
1196 struct ata_host *host;
1197 int n_ports, n_msis, i, rc;
1198 int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1199
1200 VPRINTK("ENTER\n");
1201
1202 WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1203
1204 ata_print_version_once(&pdev->dev, DRV_VERSION);
1205
1206 /* The AHCI driver can only drive the SATA ports, the PATA driver
1207 can drive them all so if both drivers are selected make sure
1208 AHCI stays out of the way */
1209 if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1210 return -ENODEV;
1211
1212 /*
1213 * For some reason, MCP89 on MacBook 7,1 doesn't work with
1214 * ahci, use ata_generic instead.
1215 */
1216 if (pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1217 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1218 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1219 pdev->subsystem_device == 0xcb89)
1220 return -ENODEV;
1221
1222 /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1223 * At the moment, we can only use the AHCI mode. Let the users know
1224 * that for SAS drives they're out of luck.
1225 */
1226 if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1227 dev_info(&pdev->dev,
1228 "PDC42819 can only drive SATA devices with this driver\n");
1229
1230 /* Both Connext and Enmotus devices use non-standard BARs */
1231 if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1232 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1233 else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1234 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1235
1236 /* acquire resources */
1237 rc = pcim_enable_device(pdev);
1238 if (rc)
1239 return rc;
1240
1241 /* AHCI controllers often implement SFF compatible interface.
1242 * Grab all PCI BARs just in case.
1243 */
1244 rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1245 if (rc == -EBUSY)
1246 pcim_pin_device(pdev);
1247 if (rc)
1248 return rc;
1249
1250 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1251 (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1252 u8 map;
1253
1254 /* ICH6s share the same PCI ID for both piix and ahci
1255 * modes. Enabling ahci mode while MAP indicates
1256 * combined mode is a bad idea. Yield to ata_piix.
1257 */
1258 pci_read_config_byte(pdev, ICH_MAP, &map);
1259 if (map & 0x3) {
1260 dev_info(&pdev->dev,
1261 "controller is in combined mode, can't enable AHCI mode\n");
1262 return -ENODEV;
1263 }
1264 }
1265
1266 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1267 if (!hpriv)
1268 return -ENOMEM;
1269 hpriv->flags |= (unsigned long)pi.private_data;
1270
1271 /* MCP65 revision A1 and A2 can't do MSI */
1272 if (board_id == board_ahci_mcp65 &&
1273 (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1274 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1275
1276 /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1277 if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1278 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1279
1280 /* only some SB600s can do 64bit DMA */
1281 if (ahci_sb600_enable_64bit(pdev))
1282 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1283
1284 hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1285
1286 n_msis = ahci_init_interrupts(pdev, hpriv);
1287 if (n_msis > 1)
1288 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1289
1290 /* save initial config */
1291 ahci_pci_save_initial_config(pdev, hpriv);
1292
1293 /* prepare host */
1294 if (hpriv->cap & HOST_CAP_NCQ) {
1295 pi.flags |= ATA_FLAG_NCQ;
1296 /*
1297 * Auto-activate optimization is supposed to be
1298 * supported on all AHCI controllers indicating NCQ
1299 * capability, but it seems to be broken on some
1300 * chipsets including NVIDIAs.
1301 */
1302 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1303 pi.flags |= ATA_FLAG_FPDMA_AA;
1304
1305 /*
1306 * All AHCI controllers should be forward-compatible
1307 * with the new auxiliary field. This code should be
1308 * conditionalized if any buggy AHCI controllers are
1309 * encountered.
1310 */
1311 pi.flags |= ATA_FLAG_FPDMA_AUX;
1312 }
1313
1314 if (hpriv->cap & HOST_CAP_PMP)
1315 pi.flags |= ATA_FLAG_PMP;
1316
1317 ahci_set_em_messages(hpriv, &pi);
1318
1319 if (ahci_broken_system_poweroff(pdev)) {
1320 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1321 dev_info(&pdev->dev,
1322 "quirky BIOS, skipping spindown on poweroff\n");
1323 }
1324
1325 if (ahci_broken_suspend(pdev)) {
1326 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1327 dev_warn(&pdev->dev,
1328 "BIOS update required for suspend/resume\n");
1329 }
1330
1331 if (ahci_broken_online(pdev)) {
1332 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1333 dev_info(&pdev->dev,
1334 "online status unreliable, applying workaround\n");
1335 }
1336
1337 /* CAP.NP sometimes indicate the index of the last enabled
1338 * port, at other times, that of the last possible port, so
1339 * determining the maximum port number requires looking at
1340 * both CAP.NP and port_map.
1341 */
1342 n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1343
1344 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1345 if (!host)
1346 return -ENOMEM;
1347 host->private_data = hpriv;
1348
1349 if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1350 host->flags |= ATA_HOST_PARALLEL_SCAN;
1351 else
1352 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1353
1354 if (pi.flags & ATA_FLAG_EM)
1355 ahci_reset_em(host);
1356
1357 for (i = 0; i < host->n_ports; i++) {
1358 struct ata_port *ap = host->ports[i];
1359
1360 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1361 ata_port_pbar_desc(ap, ahci_pci_bar,
1362 0x100 + ap->port_no * 0x80, "port");
1363
1364 /* set enclosure management message type */
1365 if (ap->flags & ATA_FLAG_EM)
1366 ap->em_message_type = hpriv->em_msg_type;
1367
1368
1369 /* disabled/not-implemented port */
1370 if (!(hpriv->port_map & (1 << i)))
1371 ap->ops = &ata_dummy_port_ops;
1372 }
1373
1374 /* apply workaround for ASUS P5W DH Deluxe mainboard */
1375 ahci_p5wdh_workaround(host);
1376
1377 /* apply gtf filter quirk */
1378 ahci_gtf_filter_workaround(host);
1379
1380 /* initialize adapter */
1381 rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1382 if (rc)
1383 return rc;
1384
1385 rc = ahci_pci_reset_controller(host);
1386 if (rc)
1387 return rc;
1388
1389 ahci_pci_init_controller(host);
1390 ahci_pci_print_info(host);
1391
1392 pci_set_master(pdev);
1393
1394 if (hpriv->flags & AHCI_HFLAG_MULTI_MSI)
1395 return ahci_host_activate(host, pdev->irq, n_msis);
1396
1397 return ata_host_activate(host, pdev->irq, ahci_interrupt, IRQF_SHARED,
1398 &ahci_sht);
1399 }
1400
1401 module_pci_driver(ahci_pci_driver);
1402
1403 MODULE_AUTHOR("Jeff Garzik");
1404 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1405 MODULE_LICENSE("GPL");
1406 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1407 MODULE_VERSION(DRV_VERSION);
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