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metag: Fix __cmpxchg_u32 asm constraint for CMP
[linux-2.6/btrfs-unstable.git] / drivers / ata / pata_amd.c
blob8d4d959a821cab1a356dfde38226caf69ab5129f
1 /*
2 * pata_amd.c - AMD PATA for new ATA layer
3 * (C) 2005-2006 Red Hat Inc
4 *
5 * Based on pata-sil680. Errata information is taken from data sheets
6 * and the amd74xx.c driver by Vojtech Pavlik. Nvidia SATA devices are
7 * claimed by sata-nv.c.
8 *
9 * TODO:
10 * Variable system clock when/if it makes sense
11 * Power management on ports
12 *
13 *
14 * Documentation publicly available.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/pci.h>
20 #include <linux/blkdev.h>
21 #include <linux/delay.h>
22 #include <scsi/scsi_host.h>
23 #include <linux/libata.h>
24
25 #define DRV_NAME "pata_amd"
26 #define DRV_VERSION "0.4.1"
27
28 /**
29 * timing_setup - shared timing computation and load
30 * @ap: ATA port being set up
31 * @adev: drive being configured
32 * @offset: port offset
33 * @speed: target speed
34 * @clock: clock multiplier (number of times 33MHz for this part)
35 *
36 * Perform the actual timing set up for Nvidia or AMD PATA devices.
37 * The actual devices vary so they all call into this helper function
38 * providing the clock multipler and offset (because AMD and Nvidia put
39 * the ports at different locations).
40 */
41
42 static void timing_setup(struct ata_port *ap, struct ata_device *adev, int offset, int speed, int clock)
43 {
44 static const unsigned char amd_cyc2udma[] = {
45 6, 6, 5, 4, 0, 1, 1, 2, 2, 3, 3, 3, 3, 3, 3, 7
46 };
47
48 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
49 struct ata_device *peer = ata_dev_pair(adev);
50 int dn = ap->port_no * 2 + adev->devno;
51 struct ata_timing at, apeer;
52 int T, UT;
53 const int amd_clock = 33333; /* KHz. */
54 u8 t;
55
56 T = 1000000000 / amd_clock;
57 UT = T;
58 if (clock >= 2)
59 UT = T / 2;
60
61 if (ata_timing_compute(adev, speed, &at, T, UT) < 0) {
62 dev_err(&pdev->dev, "unknown mode %d\n", speed);
63 return;
64 }
65
66 if (peer) {
67 /* This may be over conservative */
68 if (peer->dma_mode) {
69 ata_timing_compute(peer, peer->dma_mode, &apeer, T, UT);
70 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
71 }
72 ata_timing_compute(peer, peer->pio_mode, &apeer, T, UT);
73 ata_timing_merge(&apeer, &at, &at, ATA_TIMING_8BIT);
74 }
75
76 if (speed == XFER_UDMA_5 && amd_clock <= 33333) at.udma = 1;
77 if (speed == XFER_UDMA_6 && amd_clock <= 33333) at.udma = 15;
78
79 /*
80 * Now do the setup work
81 */
82
83 /* Configure the address set up timing */
84 pci_read_config_byte(pdev, offset + 0x0C, &t);
85 t = (t & ~(3 << ((3 - dn) << 1))) | ((clamp_val(at.setup, 1, 4) - 1) << ((3 - dn) << 1));
86 pci_write_config_byte(pdev, offset + 0x0C , t);
87
88 /* Configure the 8bit I/O timing */
89 pci_write_config_byte(pdev, offset + 0x0E + (1 - (dn >> 1)),
90 ((clamp_val(at.act8b, 1, 16) - 1) << 4) | (clamp_val(at.rec8b, 1, 16) - 1));
91
92 /* Drive timing */
93 pci_write_config_byte(pdev, offset + 0x08 + (3 - dn),
94 ((clamp_val(at.active, 1, 16) - 1) << 4) | (clamp_val(at.recover, 1, 16) - 1));
95
96 switch (clock) {
97 case 1:
98 t = at.udma ? (0xc0 | (clamp_val(at.udma, 2, 5) - 2)) : 0x03;
99 break;
100
101 case 2:
102 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 2, 10)]) : 0x03;
103 break;
104
105 case 3:
106 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 10)]) : 0x03;
107 break;
108
109 case 4:
110 t = at.udma ? (0xc0 | amd_cyc2udma[clamp_val(at.udma, 1, 15)]) : 0x03;
111 break;
112
113 default:
114 return;
115 }
116
117 /* UDMA timing */
118 if (at.udma)
119 pci_write_config_byte(pdev, offset + 0x10 + (3 - dn), t);
120 }
121
122 /**
123 * amd_pre_reset - perform reset handling
124 * @link: ATA link
125 * @deadline: deadline jiffies for the operation
126 *
127 * Reset sequence checking enable bits to see which ports are
128 * active.
129 */
130
131 static int amd_pre_reset(struct ata_link *link, unsigned long deadline)
132 {
133 static const struct pci_bits amd_enable_bits[] = {
134 { 0x40, 1, 0x02, 0x02 },
135 { 0x40, 1, 0x01, 0x01 }
136 };
137
138 struct ata_port *ap = link->ap;
139 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
140
141 if (!pci_test_config_bits(pdev, &amd_enable_bits[ap->port_no]))
142 return -ENOENT;
143
144 return ata_sff_prereset(link, deadline);
145 }
146
147 /**
148 * amd_cable_detect - report cable type
149 * @ap: port
150 *
151 * AMD controller/BIOS setups record the cable type in word 0x42
152 */
153
154 static int amd_cable_detect(struct ata_port *ap)
155 {
156 static const u32 bitmask[2] = {0x03, 0x0C};
157 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
158 u8 ata66;
159
160 pci_read_config_byte(pdev, 0x42, &ata66);
161 if (ata66 & bitmask[ap->port_no])
162 return ATA_CBL_PATA80;
163 return ATA_CBL_PATA40;
164 }
165
166 /**
167 * amd_fifo_setup - set the PIO FIFO for ATA/ATAPI
168 * @ap: ATA interface
169 * @adev: ATA device
170 *
171 * Set the PCI fifo for this device according to the devices present
172 * on the bus at this point in time. We need to turn the post write buffer
173 * off for ATAPI devices as we may need to issue a word sized write to the
174 * device as the final I/O
175 */
176
177 static void amd_fifo_setup(struct ata_port *ap)
178 {
179 struct ata_device *adev;
180 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
181 static const u8 fifobit[2] = { 0xC0, 0x30};
182 u8 fifo = fifobit[ap->port_no];
183 u8 r;
184
185
186 ata_for_each_dev(adev, &ap->link, ENABLED) {
187 if (adev->class == ATA_DEV_ATAPI)
188 fifo = 0;
189 }
190 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7411) /* FIFO is broken */
191 fifo = 0;
192
193 /* On the later chips the read prefetch bits become no-op bits */
194 pci_read_config_byte(pdev, 0x41, &r);
195 r &= ~fifobit[ap->port_no];
196 r |= fifo;
197 pci_write_config_byte(pdev, 0x41, r);
198 }
199
200 /**
201 * amd33_set_piomode - set initial PIO mode data
202 * @ap: ATA interface
203 * @adev: ATA device
204 *
205 * Program the AMD registers for PIO mode.
206 */
207
208 static void amd33_set_piomode(struct ata_port *ap, struct ata_device *adev)
209 {
210 amd_fifo_setup(ap);
211 timing_setup(ap, adev, 0x40, adev->pio_mode, 1);
212 }
213
214 static void amd66_set_piomode(struct ata_port *ap, struct ata_device *adev)
215 {
216 amd_fifo_setup(ap);
217 timing_setup(ap, adev, 0x40, adev->pio_mode, 2);
218 }
219
220 static void amd100_set_piomode(struct ata_port *ap, struct ata_device *adev)
221 {
222 amd_fifo_setup(ap);
223 timing_setup(ap, adev, 0x40, adev->pio_mode, 3);
224 }
225
226 static void amd133_set_piomode(struct ata_port *ap, struct ata_device *adev)
227 {
228 amd_fifo_setup(ap);
229 timing_setup(ap, adev, 0x40, adev->pio_mode, 4);
230 }
231
232 /**
233 * amd33_set_dmamode - set initial DMA mode data
234 * @ap: ATA interface
235 * @adev: ATA device
236 *
237 * Program the MWDMA/UDMA modes for the AMD and Nvidia
238 * chipset.
239 */
240
241 static void amd33_set_dmamode(struct ata_port *ap, struct ata_device *adev)
242 {
243 timing_setup(ap, adev, 0x40, adev->dma_mode, 1);
244 }
245
246 static void amd66_set_dmamode(struct ata_port *ap, struct ata_device *adev)
247 {
248 timing_setup(ap, adev, 0x40, adev->dma_mode, 2);
249 }
250
251 static void amd100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
252 {
253 timing_setup(ap, adev, 0x40, adev->dma_mode, 3);
254 }
255
256 static void amd133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
257 {
258 timing_setup(ap, adev, 0x40, adev->dma_mode, 4);
259 }
260
261 /* Both host-side and drive-side detection results are worthless on NV
262 * PATAs. Ignore them and just follow what BIOS configured. Both the
263 * current configuration in PCI config reg and ACPI GTM result are
264 * cached during driver attach and are consulted to select transfer
265 * mode.
266 */
267 static unsigned long nv_mode_filter(struct ata_device *dev,
268 unsigned long xfer_mask)
269 {
270 static const unsigned int udma_mask_map[] =
271 { ATA_UDMA2, ATA_UDMA1, ATA_UDMA0, 0,
272 ATA_UDMA3, ATA_UDMA4, ATA_UDMA5, ATA_UDMA6 };
273 struct ata_port *ap = dev->link->ap;
274 char acpi_str[32] = "";
275 u32 saved_udma, udma;
276 const struct ata_acpi_gtm *gtm;
277 unsigned long bios_limit = 0, acpi_limit = 0, limit;
278
279 /* find out what BIOS configured */
280 udma = saved_udma = (unsigned long)ap->host->private_data;
281
282 if (ap->port_no == 0)
283 udma >>= 16;
284 if (dev->devno == 0)
285 udma >>= 8;
286
287 if ((udma & 0xc0) == 0xc0)
288 bios_limit = ata_pack_xfermask(0, 0, udma_mask_map[udma & 0x7]);
289
290 /* consult ACPI GTM too */
291 gtm = ata_acpi_init_gtm(ap);
292 if (gtm) {
293 acpi_limit = ata_acpi_gtm_xfermask(dev, gtm);
294
295 snprintf(acpi_str, sizeof(acpi_str), " (%u:%u:0x%x)",
296 gtm->drive[0].dma, gtm->drive[1].dma, gtm->flags);
297 }
298
299 /* be optimistic, EH can take care of things if something goes wrong */
300 limit = bios_limit | acpi_limit;
301
302 /* If PIO or DMA isn't configured at all, don't limit. Let EH
303 * handle it.
304 */
305 if (!(limit & ATA_MASK_PIO))
306 limit |= ATA_MASK_PIO;
307 if (!(limit & (ATA_MASK_MWDMA | ATA_MASK_UDMA)))
308 limit |= ATA_MASK_MWDMA | ATA_MASK_UDMA;
309 /* PIO4, MWDMA2, UDMA2 should always be supported regardless of
310 cable detection result */
311 limit |= ata_pack_xfermask(ATA_PIO4, ATA_MWDMA2, ATA_UDMA2);
312
313 ata_port_dbg(ap, "nv_mode_filter: 0x%lx&0x%lx->0x%lx, "
314 "BIOS=0x%lx (0x%x) ACPI=0x%lx%s\n",
315 xfer_mask, limit, xfer_mask & limit, bios_limit,
316 saved_udma, acpi_limit, acpi_str);
317
318 return xfer_mask & limit;
319 }
320
321 /**
322 * nv_probe_init - cable detection
323 * @lin: ATA link
324 *
325 * Perform cable detection. The BIOS stores this in PCI config
326 * space for us.
327 */
328
329 static int nv_pre_reset(struct ata_link *link, unsigned long deadline)
330 {
331 static const struct pci_bits nv_enable_bits[] = {
332 { 0x50, 1, 0x02, 0x02 },
333 { 0x50, 1, 0x01, 0x01 }
334 };
335
336 struct ata_port *ap = link->ap;
337 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
338
339 if (!pci_test_config_bits(pdev, &nv_enable_bits[ap->port_no]))
340 return -ENOENT;
341
342 return ata_sff_prereset(link, deadline);
343 }
344
345 /**
346 * nv100_set_piomode - set initial PIO mode data
347 * @ap: ATA interface
348 * @adev: ATA device
349 *
350 * Program the AMD registers for PIO mode.
351 */
352
353 static void nv100_set_piomode(struct ata_port *ap, struct ata_device *adev)
354 {
355 timing_setup(ap, adev, 0x50, adev->pio_mode, 3);
356 }
357
358 static void nv133_set_piomode(struct ata_port *ap, struct ata_device *adev)
359 {
360 timing_setup(ap, adev, 0x50, adev->pio_mode, 4);
361 }
362
363 /**
364 * nv100_set_dmamode - set initial DMA mode data
365 * @ap: ATA interface
366 * @adev: ATA device
367 *
368 * Program the MWDMA/UDMA modes for the AMD and Nvidia
369 * chipset.
370 */
371
372 static void nv100_set_dmamode(struct ata_port *ap, struct ata_device *adev)
373 {
374 timing_setup(ap, adev, 0x50, adev->dma_mode, 3);
375 }
376
377 static void nv133_set_dmamode(struct ata_port *ap, struct ata_device *adev)
378 {
379 timing_setup(ap, adev, 0x50, adev->dma_mode, 4);
380 }
381
382 static void nv_host_stop(struct ata_host *host)
383 {
384 u32 udma = (unsigned long)host->private_data;
385
386 /* restore PCI config register 0x60 */
387 pci_write_config_dword(to_pci_dev(host->dev), 0x60, udma);
388 }
389
390 static struct scsi_host_template amd_sht = {
391 ATA_BMDMA_SHT(DRV_NAME),
392 };
393
394 static const struct ata_port_operations amd_base_port_ops = {
395 .inherits = &ata_bmdma32_port_ops,
396 .prereset = amd_pre_reset,
397 };
398
399 static struct ata_port_operations amd33_port_ops = {
400 .inherits = &amd_base_port_ops,
401 .cable_detect = ata_cable_40wire,
402 .set_piomode = amd33_set_piomode,
403 .set_dmamode = amd33_set_dmamode,
404 };
405
406 static struct ata_port_operations amd66_port_ops = {
407 .inherits = &amd_base_port_ops,
408 .cable_detect = ata_cable_unknown,
409 .set_piomode = amd66_set_piomode,
410 .set_dmamode = amd66_set_dmamode,
411 };
412
413 static struct ata_port_operations amd100_port_ops = {
414 .inherits = &amd_base_port_ops,
415 .cable_detect = ata_cable_unknown,
416 .set_piomode = amd100_set_piomode,
417 .set_dmamode = amd100_set_dmamode,
418 };
419
420 static struct ata_port_operations amd133_port_ops = {
421 .inherits = &amd_base_port_ops,
422 .cable_detect = amd_cable_detect,
423 .set_piomode = amd133_set_piomode,
424 .set_dmamode = amd133_set_dmamode,
425 };
426
427 static const struct ata_port_operations nv_base_port_ops = {
428 .inherits = &ata_bmdma_port_ops,
429 .cable_detect = ata_cable_ignore,
430 .mode_filter = nv_mode_filter,
431 .prereset = nv_pre_reset,
432 .host_stop = nv_host_stop,
433 };
434
435 static struct ata_port_operations nv100_port_ops = {
436 .inherits = &nv_base_port_ops,
437 .set_piomode = nv100_set_piomode,
438 .set_dmamode = nv100_set_dmamode,
439 };
440
441 static struct ata_port_operations nv133_port_ops = {
442 .inherits = &nv_base_port_ops,
443 .set_piomode = nv133_set_piomode,
444 .set_dmamode = nv133_set_dmamode,
445 };
446
447 static void amd_clear_fifo(struct pci_dev *pdev)
448 {
449 u8 fifo;
450 /* Disable the FIFO, the FIFO logic will re-enable it as
451 appropriate */
452 pci_read_config_byte(pdev, 0x41, &fifo);
453 fifo &= 0x0F;
454 pci_write_config_byte(pdev, 0x41, fifo);
455 }
456
457 static int amd_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
458 {
459 static const struct ata_port_info info[10] = {
460 { /* 0: AMD 7401 - no swdma */
461 .flags = ATA_FLAG_SLAVE_POSS,
462 .pio_mask = ATA_PIO4,
463 .mwdma_mask = ATA_MWDMA2,
464 .udma_mask = ATA_UDMA2,
465 .port_ops = &amd33_port_ops
466 },
467 { /* 1: Early AMD7409 - no swdma */
468 .flags = ATA_FLAG_SLAVE_POSS,
469 .pio_mask = ATA_PIO4,
470 .mwdma_mask = ATA_MWDMA2,
471 .udma_mask = ATA_UDMA4,
472 .port_ops = &amd66_port_ops
473 },
474 { /* 2: AMD 7409 */
475 .flags = ATA_FLAG_SLAVE_POSS,
476 .pio_mask = ATA_PIO4,
477 .mwdma_mask = ATA_MWDMA2,
478 .udma_mask = ATA_UDMA4,
479 .port_ops = &amd66_port_ops
480 },
481 { /* 3: AMD 7411 */
482 .flags = ATA_FLAG_SLAVE_POSS,
483 .pio_mask = ATA_PIO4,
484 .mwdma_mask = ATA_MWDMA2,
485 .udma_mask = ATA_UDMA5,
486 .port_ops = &amd100_port_ops
487 },
488 { /* 4: AMD 7441 */
489 .flags = ATA_FLAG_SLAVE_POSS,
490 .pio_mask = ATA_PIO4,
491 .mwdma_mask = ATA_MWDMA2,
492 .udma_mask = ATA_UDMA5,
493 .port_ops = &amd100_port_ops
494 },
495 { /* 5: AMD 8111 - no swdma */
496 .flags = ATA_FLAG_SLAVE_POSS,
497 .pio_mask = ATA_PIO4,
498 .mwdma_mask = ATA_MWDMA2,
499 .udma_mask = ATA_UDMA6,
500 .port_ops = &amd133_port_ops
501 },
502 { /* 6: AMD 8111 UDMA 100 (Serenade) - no swdma */
503 .flags = ATA_FLAG_SLAVE_POSS,
504 .pio_mask = ATA_PIO4,
505 .mwdma_mask = ATA_MWDMA2,
506 .udma_mask = ATA_UDMA5,
507 .port_ops = &amd133_port_ops
508 },
509 { /* 7: Nvidia Nforce */
510 .flags = ATA_FLAG_SLAVE_POSS,
511 .pio_mask = ATA_PIO4,
512 .mwdma_mask = ATA_MWDMA2,
513 .udma_mask = ATA_UDMA5,
514 .port_ops = &nv100_port_ops
515 },
516 { /* 8: Nvidia Nforce2 and later - no swdma */
517 .flags = ATA_FLAG_SLAVE_POSS,
518 .pio_mask = ATA_PIO4,
519 .mwdma_mask = ATA_MWDMA2,
520 .udma_mask = ATA_UDMA6,
521 .port_ops = &nv133_port_ops
522 },
523 { /* 9: AMD CS5536 (Geode companion) */
524 .flags = ATA_FLAG_SLAVE_POSS,
525 .pio_mask = ATA_PIO4,
526 .mwdma_mask = ATA_MWDMA2,
527 .udma_mask = ATA_UDMA5,
528 .port_ops = &amd100_port_ops
529 }
530 };
531 const struct ata_port_info *ppi[] = { NULL, NULL };
532 int type = id->driver_data;
533 void *hpriv = NULL;
534 u8 fifo;
535 int rc;
536
537 ata_print_version_once(&pdev->dev, DRV_VERSION);
538
539 rc = pcim_enable_device(pdev);
540 if (rc)
541 return rc;
542
543 pci_read_config_byte(pdev, 0x41, &fifo);
544
545 /* Check for AMD7409 without swdma errata and if found adjust type */
546 if (type == 1 && pdev->revision > 0x7)
547 type = 2;
548
549 /* Serenade ? */
550 if (type == 5 && pdev->subsystem_vendor == PCI_VENDOR_ID_AMD &&
551 pdev->subsystem_device == PCI_DEVICE_ID_AMD_SERENADE)
552 type = 6; /* UDMA 100 only */
553
554 /*
555 * Okay, type is determined now. Apply type-specific workarounds.
556 */
557 ppi[0] = &info[type];
558
559 if (type < 3)
560 ata_pci_bmdma_clear_simplex(pdev);
561 if (pdev->vendor == PCI_VENDOR_ID_AMD)
562 amd_clear_fifo(pdev);
563 /* Cable detection on Nvidia chips doesn't work too well,
564 * cache BIOS programmed UDMA mode.
565 */
566 if (type == 7 || type == 8) {
567 u32 udma;
568
569 pci_read_config_dword(pdev, 0x60, &udma);
570 hpriv = (void *)(unsigned long)udma;
571 }
572
573 /* And fire it up */
574 return ata_pci_bmdma_init_one(pdev, ppi, &amd_sht, hpriv, 0);
575 }
576
577 #ifdef CONFIG_PM_SLEEP
578 static int amd_reinit_one(struct pci_dev *pdev)
579 {
580 struct ata_host *host = pci_get_drvdata(pdev);
581 int rc;
582
583 rc = ata_pci_device_do_resume(pdev);
584 if (rc)
585 return rc;
586
587 if (pdev->vendor == PCI_VENDOR_ID_AMD) {
588 amd_clear_fifo(pdev);
589 if (pdev->device == PCI_DEVICE_ID_AMD_VIPER_7409 ||
590 pdev->device == PCI_DEVICE_ID_AMD_COBRA_7401)
591 ata_pci_bmdma_clear_simplex(pdev);
592 }
593 ata_host_resume(host);
594 return 0;
595 }
596 #endif
597
598 static const struct pci_device_id amd[] = {
599 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_COBRA_7401), 0 },
600 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7409), 1 },
601 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_VIPER_7411), 3 },
602 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_OPUS_7441), 4 },
603 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_8111_IDE), 5 },
604 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_IDE), 7 },
605 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE), 8 },
606 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE), 8 },
607 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE), 8 },
608 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE), 8 },
609 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE), 8 },
610 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE), 8 },
611 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE), 8 },
612 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_IDE), 8 },
613 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_IDE), 8 },
614 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_IDE), 8 },
615 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_IDE), 8 },
616 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_IDE), 8 },
617 { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP77_IDE), 8 },
618 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_CS5536_IDE), 9 },
619
620 { },
621 };
622
623 static struct pci_driver amd_pci_driver = {
624 .name = DRV_NAME,
625 .id_table = amd,
626 .probe = amd_init_one,
627 .remove = ata_pci_remove_one,
628 #ifdef CONFIG_PM_SLEEP
629 .suspend = ata_pci_device_suspend,
630 .resume = amd_reinit_one,
631 #endif
632 };
633
634 module_pci_driver(amd_pci_driver);
635
636 MODULE_AUTHOR("Alan Cox");
637 MODULE_DESCRIPTION("low-level driver for AMD and Nvidia PATA IDE");
638 MODULE_LICENSE("GPL");
639 MODULE_DEVICE_TABLE(pci, amd);
640 MODULE_VERSION(DRV_VERSION);
(deprecated) Btrfs devel tree