2 * Blackfin On-Chip SPI Driver
4 * Copyright 2004-2010 Analog Devices Inc.
6 * Enter bugs at http://blackfin.uclinux.org/
8 * Licensed under the GPL-2 or later.
11 #include <linux/init.h>
12 #include <linux/module.h>
13 #include <linux/delay.h>
14 #include <linux/device.h>
15 #include <linux/slab.h>
17 #include <linux/ioport.h>
18 #include <linux/irq.h>
19 #include <linux/errno.h>
20 #include <linux/interrupt.h>
21 #include <linux/platform_device.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/spi/spi.h>
24 #include <linux/workqueue.h>
27 #include <asm/portmux.h>
28 #include <asm/bfin5xx_spi.h>
29 #include <asm/cacheflush.h>
31 #define DRV_NAME "bfin-spi"
32 #define DRV_AUTHOR "Bryan Wu, Luke Yang"
33 #define DRV_DESC "Blackfin on-chip SPI Controller Driver"
34 #define DRV_VERSION "1.0"
36 MODULE_AUTHOR(DRV_AUTHOR
);
37 MODULE_DESCRIPTION(DRV_DESC
);
38 MODULE_LICENSE("GPL");
40 #define START_STATE ((void *)0)
41 #define RUNNING_STATE ((void *)1)
42 #define DONE_STATE ((void *)2)
43 #define ERROR_STATE ((void *)-1)
45 struct bfin_spi_master_data
;
47 struct bfin_spi_transfer_ops
{
48 void (*write
) (struct bfin_spi_master_data
*);
49 void (*read
) (struct bfin_spi_master_data
*);
50 void (*duplex
) (struct bfin_spi_master_data
*);
53 struct bfin_spi_master_data
{
54 /* Driver model hookup */
55 struct platform_device
*pdev
;
57 /* SPI framework hookup */
58 struct spi_master
*master
;
60 /* Regs base of SPI controller */
61 struct bfin_spi_regs __iomem
*regs
;
63 /* Pin request list */
67 struct bfin5xx_spi_master
*master_info
;
69 /* Driver message queue */
70 struct workqueue_struct
*workqueue
;
71 struct work_struct pump_messages
;
73 struct list_head queue
;
77 /* Message Transfer pump */
78 struct tasklet_struct pump_transfers
;
80 /* Current message transfer state info */
81 struct spi_message
*cur_msg
;
82 struct spi_transfer
*cur_transfer
;
83 struct bfin_spi_slave_data
*cur_chip
;
108 const struct bfin_spi_transfer_ops
*ops
;
111 struct bfin_spi_slave_data
{
118 u16 cs_chg_udelay
; /* Some devices require > 255usec delay */
121 u8 pio_interrupt
; /* use spi data irq */
122 const struct bfin_spi_transfer_ops
*ops
;
125 static void bfin_spi_enable(struct bfin_spi_master_data
*drv_data
)
127 bfin_write_or(&drv_data
->regs
->ctl
, BIT_CTL_ENABLE
);
130 static void bfin_spi_disable(struct bfin_spi_master_data
*drv_data
)
132 bfin_write_and(&drv_data
->regs
->ctl
, ~BIT_CTL_ENABLE
);
135 /* Caculate the SPI_BAUD register value based on input HZ */
136 static u16
hz_to_spi_baud(u32 speed_hz
)
138 u_long sclk
= get_sclk();
139 u16 spi_baud
= (sclk
/ (2 * speed_hz
));
141 if ((sclk
% (2 * speed_hz
)) > 0)
144 if (spi_baud
< MIN_SPI_BAUD_VAL
)
145 spi_baud
= MIN_SPI_BAUD_VAL
;
150 static int bfin_spi_flush(struct bfin_spi_master_data
*drv_data
)
152 unsigned long limit
= loops_per_jiffy
<< 1;
154 /* wait for stop and clear stat */
155 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_SPIF
) && --limit
)
158 bfin_write(&drv_data
->regs
->stat
, BIT_STAT_CLR
);
163 /* Chip select operation functions for cs_change flag */
164 static void bfin_spi_cs_active(struct bfin_spi_master_data
*drv_data
, struct bfin_spi_slave_data
*chip
)
166 if (likely(chip
->chip_select_num
< MAX_CTRL_CS
))
167 bfin_write_and(&drv_data
->regs
->flg
, ~chip
->flag
);
169 gpio_set_value(chip
->cs_gpio
, 0);
172 static void bfin_spi_cs_deactive(struct bfin_spi_master_data
*drv_data
,
173 struct bfin_spi_slave_data
*chip
)
175 if (likely(chip
->chip_select_num
< MAX_CTRL_CS
))
176 bfin_write_or(&drv_data
->regs
->flg
, chip
->flag
);
178 gpio_set_value(chip
->cs_gpio
, 1);
180 /* Move delay here for consistency */
181 if (chip
->cs_chg_udelay
)
182 udelay(chip
->cs_chg_udelay
);
185 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */
186 static inline void bfin_spi_cs_enable(struct bfin_spi_master_data
*drv_data
,
187 struct bfin_spi_slave_data
*chip
)
189 if (chip
->chip_select_num
< MAX_CTRL_CS
)
190 bfin_write_or(&drv_data
->regs
->flg
, chip
->flag
>> 8);
193 static inline void bfin_spi_cs_disable(struct bfin_spi_master_data
*drv_data
,
194 struct bfin_spi_slave_data
*chip
)
196 if (chip
->chip_select_num
< MAX_CTRL_CS
)
197 bfin_write_and(&drv_data
->regs
->flg
, ~(chip
->flag
>> 8));
200 /* stop controller and re-config current chip*/
201 static void bfin_spi_restore_state(struct bfin_spi_master_data
*drv_data
)
203 struct bfin_spi_slave_data
*chip
= drv_data
->cur_chip
;
205 /* Clear status and disable clock */
206 bfin_write(&drv_data
->regs
->stat
, BIT_STAT_CLR
);
207 bfin_spi_disable(drv_data
);
208 dev_dbg(&drv_data
->pdev
->dev
, "restoring spi ctl state\n");
212 /* Load the registers */
213 bfin_write(&drv_data
->regs
->ctl
, chip
->ctl_reg
);
214 bfin_write(&drv_data
->regs
->baud
, chip
->baud
);
216 bfin_spi_enable(drv_data
);
217 bfin_spi_cs_active(drv_data
, chip
);
220 /* used to kick off transfer in rx mode and read unwanted RX data */
221 static inline void bfin_spi_dummy_read(struct bfin_spi_master_data
*drv_data
)
223 (void) bfin_read(&drv_data
->regs
->rdbr
);
226 static void bfin_spi_u8_writer(struct bfin_spi_master_data
*drv_data
)
228 /* clear RXS (we check for RXS inside the loop) */
229 bfin_spi_dummy_read(drv_data
);
231 while (drv_data
->tx
< drv_data
->tx_end
) {
232 bfin_write(&drv_data
->regs
->tdbr
, (*(u8
*) (drv_data
->tx
++)));
233 /* wait until transfer finished.
234 checking SPIF or TXS may not guarantee transfer completion */
235 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_RXS
))
237 /* discard RX data and clear RXS */
238 bfin_spi_dummy_read(drv_data
);
242 static void bfin_spi_u8_reader(struct bfin_spi_master_data
*drv_data
)
244 u16 tx_val
= drv_data
->cur_chip
->idle_tx_val
;
246 /* discard old RX data and clear RXS */
247 bfin_spi_dummy_read(drv_data
);
249 while (drv_data
->rx
< drv_data
->rx_end
) {
250 bfin_write(&drv_data
->regs
->tdbr
, tx_val
);
251 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_RXS
))
253 *(u8
*) (drv_data
->rx
++) = bfin_read(&drv_data
->regs
->rdbr
);
257 static void bfin_spi_u8_duplex(struct bfin_spi_master_data
*drv_data
)
259 /* discard old RX data and clear RXS */
260 bfin_spi_dummy_read(drv_data
);
262 while (drv_data
->rx
< drv_data
->rx_end
) {
263 bfin_write(&drv_data
->regs
->tdbr
, (*(u8
*) (drv_data
->tx
++)));
264 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_RXS
))
266 *(u8
*) (drv_data
->rx
++) = bfin_read(&drv_data
->regs
->rdbr
);
270 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u8
= {
271 .write
= bfin_spi_u8_writer
,
272 .read
= bfin_spi_u8_reader
,
273 .duplex
= bfin_spi_u8_duplex
,
276 static void bfin_spi_u16_writer(struct bfin_spi_master_data
*drv_data
)
278 /* clear RXS (we check for RXS inside the loop) */
279 bfin_spi_dummy_read(drv_data
);
281 while (drv_data
->tx
< drv_data
->tx_end
) {
282 bfin_write(&drv_data
->regs
->tdbr
, (*(u16
*) (drv_data
->tx
)));
284 /* wait until transfer finished.
285 checking SPIF or TXS may not guarantee transfer completion */
286 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_RXS
))
288 /* discard RX data and clear RXS */
289 bfin_spi_dummy_read(drv_data
);
293 static void bfin_spi_u16_reader(struct bfin_spi_master_data
*drv_data
)
295 u16 tx_val
= drv_data
->cur_chip
->idle_tx_val
;
297 /* discard old RX data and clear RXS */
298 bfin_spi_dummy_read(drv_data
);
300 while (drv_data
->rx
< drv_data
->rx_end
) {
301 bfin_write(&drv_data
->regs
->tdbr
, tx_val
);
302 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_RXS
))
304 *(u16
*) (drv_data
->rx
) = bfin_read(&drv_data
->regs
->rdbr
);
309 static void bfin_spi_u16_duplex(struct bfin_spi_master_data
*drv_data
)
311 /* discard old RX data and clear RXS */
312 bfin_spi_dummy_read(drv_data
);
314 while (drv_data
->rx
< drv_data
->rx_end
) {
315 bfin_write(&drv_data
->regs
->tdbr
, (*(u16
*) (drv_data
->tx
)));
317 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_RXS
))
319 *(u16
*) (drv_data
->rx
) = bfin_read(&drv_data
->regs
->rdbr
);
324 static const struct bfin_spi_transfer_ops bfin_bfin_spi_transfer_ops_u16
= {
325 .write
= bfin_spi_u16_writer
,
326 .read
= bfin_spi_u16_reader
,
327 .duplex
= bfin_spi_u16_duplex
,
330 /* test if there is more transfer to be done */
331 static void *bfin_spi_next_transfer(struct bfin_spi_master_data
*drv_data
)
333 struct spi_message
*msg
= drv_data
->cur_msg
;
334 struct spi_transfer
*trans
= drv_data
->cur_transfer
;
336 /* Move to next transfer */
337 if (trans
->transfer_list
.next
!= &msg
->transfers
) {
338 drv_data
->cur_transfer
=
339 list_entry(trans
->transfer_list
.next
,
340 struct spi_transfer
, transfer_list
);
341 return RUNNING_STATE
;
347 * caller already set message->status;
348 * dma and pio irqs are blocked give finished message back
350 static void bfin_spi_giveback(struct bfin_spi_master_data
*drv_data
)
352 struct bfin_spi_slave_data
*chip
= drv_data
->cur_chip
;
353 struct spi_transfer
*last_transfer
;
355 struct spi_message
*msg
;
357 spin_lock_irqsave(&drv_data
->lock
, flags
);
358 msg
= drv_data
->cur_msg
;
359 drv_data
->cur_msg
= NULL
;
360 drv_data
->cur_transfer
= NULL
;
361 drv_data
->cur_chip
= NULL
;
362 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
363 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
365 last_transfer
= list_entry(msg
->transfers
.prev
,
366 struct spi_transfer
, transfer_list
);
370 if (!drv_data
->cs_change
)
371 bfin_spi_cs_deactive(drv_data
, chip
);
373 /* Not stop spi in autobuffer mode */
374 if (drv_data
->tx_dma
!= 0xFFFF)
375 bfin_spi_disable(drv_data
);
378 msg
->complete(msg
->context
);
381 /* spi data irq handler */
382 static irqreturn_t
bfin_spi_pio_irq_handler(int irq
, void *dev_id
)
384 struct bfin_spi_master_data
*drv_data
= dev_id
;
385 struct bfin_spi_slave_data
*chip
= drv_data
->cur_chip
;
386 struct spi_message
*msg
= drv_data
->cur_msg
;
387 int n_bytes
= drv_data
->n_bytes
;
390 /* wait until transfer finished. */
391 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_RXS
))
394 if ((drv_data
->tx
&& drv_data
->tx
>= drv_data
->tx_end
) ||
395 (drv_data
->rx
&& drv_data
->rx
>= (drv_data
->rx_end
- n_bytes
))) {
398 dev_dbg(&drv_data
->pdev
->dev
, "last read\n");
399 if (!(n_bytes
% 2)) {
400 u16
*buf
= (u16
*)drv_data
->rx
;
401 for (loop
= 0; loop
< n_bytes
/ 2; loop
++)
402 *buf
++ = bfin_read(&drv_data
->regs
->rdbr
);
404 u8
*buf
= (u8
*)drv_data
->rx
;
405 for (loop
= 0; loop
< n_bytes
; loop
++)
406 *buf
++ = bfin_read(&drv_data
->regs
->rdbr
);
408 drv_data
->rx
+= n_bytes
;
411 msg
->actual_length
+= drv_data
->len_in_bytes
;
412 if (drv_data
->cs_change
)
413 bfin_spi_cs_deactive(drv_data
, chip
);
414 /* Move to next transfer */
415 msg
->state
= bfin_spi_next_transfer(drv_data
);
417 disable_irq_nosync(drv_data
->spi_irq
);
419 /* Schedule transfer tasklet */
420 tasklet_schedule(&drv_data
->pump_transfers
);
424 if (drv_data
->rx
&& drv_data
->tx
) {
426 dev_dbg(&drv_data
->pdev
->dev
, "duplex: write_TDBR\n");
427 if (!(n_bytes
% 2)) {
428 u16
*buf
= (u16
*)drv_data
->rx
;
429 u16
*buf2
= (u16
*)drv_data
->tx
;
430 for (loop
= 0; loop
< n_bytes
/ 2; loop
++) {
431 *buf
++ = bfin_read(&drv_data
->regs
->rdbr
);
432 bfin_write(&drv_data
->regs
->tdbr
, *buf2
++);
435 u8
*buf
= (u8
*)drv_data
->rx
;
436 u8
*buf2
= (u8
*)drv_data
->tx
;
437 for (loop
= 0; loop
< n_bytes
; loop
++) {
438 *buf
++ = bfin_read(&drv_data
->regs
->rdbr
);
439 bfin_write(&drv_data
->regs
->tdbr
, *buf2
++);
442 } else if (drv_data
->rx
) {
444 dev_dbg(&drv_data
->pdev
->dev
, "read: write_TDBR\n");
445 if (!(n_bytes
% 2)) {
446 u16
*buf
= (u16
*)drv_data
->rx
;
447 for (loop
= 0; loop
< n_bytes
/ 2; loop
++) {
448 *buf
++ = bfin_read(&drv_data
->regs
->rdbr
);
449 bfin_write(&drv_data
->regs
->tdbr
, chip
->idle_tx_val
);
452 u8
*buf
= (u8
*)drv_data
->rx
;
453 for (loop
= 0; loop
< n_bytes
; loop
++) {
454 *buf
++ = bfin_read(&drv_data
->regs
->rdbr
);
455 bfin_write(&drv_data
->regs
->tdbr
, chip
->idle_tx_val
);
458 } else if (drv_data
->tx
) {
460 dev_dbg(&drv_data
->pdev
->dev
, "write: write_TDBR\n");
461 if (!(n_bytes
% 2)) {
462 u16
*buf
= (u16
*)drv_data
->tx
;
463 for (loop
= 0; loop
< n_bytes
/ 2; loop
++) {
464 bfin_read(&drv_data
->regs
->rdbr
);
465 bfin_write(&drv_data
->regs
->tdbr
, *buf
++);
468 u8
*buf
= (u8
*)drv_data
->tx
;
469 for (loop
= 0; loop
< n_bytes
; loop
++) {
470 bfin_read(&drv_data
->regs
->rdbr
);
471 bfin_write(&drv_data
->regs
->tdbr
, *buf
++);
477 drv_data
->tx
+= n_bytes
;
479 drv_data
->rx
+= n_bytes
;
484 static irqreturn_t
bfin_spi_dma_irq_handler(int irq
, void *dev_id
)
486 struct bfin_spi_master_data
*drv_data
= dev_id
;
487 struct bfin_spi_slave_data
*chip
= drv_data
->cur_chip
;
488 struct spi_message
*msg
= drv_data
->cur_msg
;
489 unsigned long timeout
;
490 unsigned short dmastat
= get_dma_curr_irqstat(drv_data
->dma_channel
);
491 u16 spistat
= bfin_read(&drv_data
->regs
->stat
);
493 dev_dbg(&drv_data
->pdev
->dev
,
494 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
497 if (drv_data
->rx
!= NULL
) {
498 u16 cr
= bfin_read(&drv_data
->regs
->ctl
);
499 /* discard old RX data and clear RXS */
500 bfin_spi_dummy_read(drv_data
);
501 bfin_write(&drv_data
->regs
->ctl
, cr
& ~BIT_CTL_ENABLE
); /* Disable SPI */
502 bfin_write(&drv_data
->regs
->ctl
, cr
& ~BIT_CTL_TIMOD
); /* Restore State */
503 bfin_write(&drv_data
->regs
->stat
, BIT_STAT_CLR
); /* Clear Status */
506 clear_dma_irqstat(drv_data
->dma_channel
);
509 * wait for the last transaction shifted out. HRM states:
510 * at this point there may still be data in the SPI DMA FIFO waiting
511 * to be transmitted ... software needs to poll TXS in the SPI_STAT
512 * register until it goes low for 2 successive reads
514 if (drv_data
->tx
!= NULL
) {
515 while ((bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_TXS
) ||
516 (bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_TXS
))
520 dev_dbg(&drv_data
->pdev
->dev
,
521 "in dma_irq_handler dmastat:0x%x spistat:0x%x\n",
522 dmastat
, bfin_read(&drv_data
->regs
->stat
));
524 timeout
= jiffies
+ HZ
;
525 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_SPIF
))
526 if (!time_before(jiffies
, timeout
)) {
527 dev_warn(&drv_data
->pdev
->dev
, "timeout waiting for SPIF");
532 if ((dmastat
& DMA_ERR
) && (spistat
& BIT_STAT_RBSY
)) {
533 msg
->state
= ERROR_STATE
;
534 dev_err(&drv_data
->pdev
->dev
, "dma receive: fifo/buffer overflow\n");
536 msg
->actual_length
+= drv_data
->len_in_bytes
;
538 if (drv_data
->cs_change
)
539 bfin_spi_cs_deactive(drv_data
, chip
);
541 /* Move to next transfer */
542 msg
->state
= bfin_spi_next_transfer(drv_data
);
545 /* Schedule transfer tasklet */
546 tasklet_schedule(&drv_data
->pump_transfers
);
548 /* free the irq handler before next transfer */
549 dev_dbg(&drv_data
->pdev
->dev
,
550 "disable dma channel irq%d\n",
551 drv_data
->dma_channel
);
552 dma_disable_irq_nosync(drv_data
->dma_channel
);
557 static void bfin_spi_pump_transfers(unsigned long data
)
559 struct bfin_spi_master_data
*drv_data
= (struct bfin_spi_master_data
*)data
;
560 struct spi_message
*message
= NULL
;
561 struct spi_transfer
*transfer
= NULL
;
562 struct spi_transfer
*previous
= NULL
;
563 struct bfin_spi_slave_data
*chip
= NULL
;
564 unsigned int bits_per_word
;
565 u16 cr
, cr_width
, dma_width
, dma_config
;
566 u32 tranf_success
= 1;
569 /* Get current state information */
570 message
= drv_data
->cur_msg
;
571 transfer
= drv_data
->cur_transfer
;
572 chip
= drv_data
->cur_chip
;
575 * if msg is error or done, report it back using complete() callback
578 /* Handle for abort */
579 if (message
->state
== ERROR_STATE
) {
580 dev_dbg(&drv_data
->pdev
->dev
, "transfer: we've hit an error\n");
581 message
->status
= -EIO
;
582 bfin_spi_giveback(drv_data
);
586 /* Handle end of message */
587 if (message
->state
== DONE_STATE
) {
588 dev_dbg(&drv_data
->pdev
->dev
, "transfer: all done!\n");
590 bfin_spi_flush(drv_data
);
591 bfin_spi_giveback(drv_data
);
595 /* Delay if requested at end of transfer */
596 if (message
->state
== RUNNING_STATE
) {
597 dev_dbg(&drv_data
->pdev
->dev
, "transfer: still running ...\n");
598 previous
= list_entry(transfer
->transfer_list
.prev
,
599 struct spi_transfer
, transfer_list
);
600 if (previous
->delay_usecs
)
601 udelay(previous
->delay_usecs
);
604 /* Flush any existing transfers that may be sitting in the hardware */
605 if (bfin_spi_flush(drv_data
) == 0) {
606 dev_err(&drv_data
->pdev
->dev
, "pump_transfers: flush failed\n");
607 message
->status
= -EIO
;
608 bfin_spi_giveback(drv_data
);
612 if (transfer
->len
== 0) {
613 /* Move to next transfer of this msg */
614 message
->state
= bfin_spi_next_transfer(drv_data
);
615 /* Schedule next transfer tasklet */
616 tasklet_schedule(&drv_data
->pump_transfers
);
620 if (transfer
->tx_buf
!= NULL
) {
621 drv_data
->tx
= (void *)transfer
->tx_buf
;
622 drv_data
->tx_end
= drv_data
->tx
+ transfer
->len
;
623 dev_dbg(&drv_data
->pdev
->dev
, "tx_buf is %p, tx_end is %p\n",
624 transfer
->tx_buf
, drv_data
->tx_end
);
629 if (transfer
->rx_buf
!= NULL
) {
630 full_duplex
= transfer
->tx_buf
!= NULL
;
631 drv_data
->rx
= transfer
->rx_buf
;
632 drv_data
->rx_end
= drv_data
->rx
+ transfer
->len
;
633 dev_dbg(&drv_data
->pdev
->dev
, "rx_buf is %p, rx_end is %p\n",
634 transfer
->rx_buf
, drv_data
->rx_end
);
639 drv_data
->rx_dma
= transfer
->rx_dma
;
640 drv_data
->tx_dma
= transfer
->tx_dma
;
641 drv_data
->len_in_bytes
= transfer
->len
;
642 drv_data
->cs_change
= transfer
->cs_change
;
644 /* Bits per word setup */
645 bits_per_word
= transfer
->bits_per_word
;
646 if (bits_per_word
% 16 == 0) {
647 drv_data
->n_bytes
= bits_per_word
/8;
648 drv_data
->len
= (transfer
->len
) >> 1;
649 cr_width
= BIT_CTL_WORDSIZE
;
650 drv_data
->ops
= &bfin_bfin_spi_transfer_ops_u16
;
651 } else if (bits_per_word
% 8 == 0) {
652 drv_data
->n_bytes
= bits_per_word
/8;
653 drv_data
->len
= transfer
->len
;
655 drv_data
->ops
= &bfin_bfin_spi_transfer_ops_u8
;
657 dev_err(&drv_data
->pdev
->dev
, "transfer: unsupported bits_per_word\n");
658 message
->status
= -EINVAL
;
659 bfin_spi_giveback(drv_data
);
662 cr
= bfin_read(&drv_data
->regs
->ctl
) & ~(BIT_CTL_TIMOD
| BIT_CTL_WORDSIZE
);
664 bfin_write(&drv_data
->regs
->ctl
, cr
);
666 dev_dbg(&drv_data
->pdev
->dev
,
667 "transfer: drv_data->ops is %p, chip->ops is %p, u8_ops is %p\n",
668 drv_data
->ops
, chip
->ops
, &bfin_bfin_spi_transfer_ops_u8
);
670 message
->state
= RUNNING_STATE
;
673 /* Speed setup (surely valid because already checked) */
674 if (transfer
->speed_hz
)
675 bfin_write(&drv_data
->regs
->baud
, hz_to_spi_baud(transfer
->speed_hz
));
677 bfin_write(&drv_data
->regs
->baud
, chip
->baud
);
679 bfin_write(&drv_data
->regs
->stat
, BIT_STAT_CLR
);
680 bfin_spi_cs_active(drv_data
, chip
);
682 dev_dbg(&drv_data
->pdev
->dev
,
683 "now pumping a transfer: width is %d, len is %d\n",
684 cr_width
, transfer
->len
);
687 * Try to map dma buffer and do a dma transfer. If successful use,
688 * different way to r/w according to the enable_dma settings and if
689 * we are not doing a full duplex transfer (since the hardware does
690 * not support full duplex DMA transfers).
692 if (!full_duplex
&& drv_data
->cur_chip
->enable_dma
693 && drv_data
->len
> 6) {
695 unsigned long dma_start_addr
, flags
;
697 disable_dma(drv_data
->dma_channel
);
698 clear_dma_irqstat(drv_data
->dma_channel
);
700 /* config dma channel */
701 dev_dbg(&drv_data
->pdev
->dev
, "doing dma transfer\n");
702 set_dma_x_count(drv_data
->dma_channel
, drv_data
->len
);
703 if (cr_width
== BIT_CTL_WORDSIZE
) {
704 set_dma_x_modify(drv_data
->dma_channel
, 2);
705 dma_width
= WDSIZE_16
;
707 set_dma_x_modify(drv_data
->dma_channel
, 1);
708 dma_width
= WDSIZE_8
;
711 /* poll for SPI completion before start */
712 while (!(bfin_read(&drv_data
->regs
->stat
) & BIT_STAT_SPIF
))
715 /* dirty hack for autobuffer DMA mode */
716 if (drv_data
->tx_dma
== 0xFFFF) {
717 dev_dbg(&drv_data
->pdev
->dev
,
718 "doing autobuffer DMA out.\n");
720 /* no irq in autobuffer mode */
722 (DMAFLOW_AUTO
| RESTART
| dma_width
| DI_EN
);
723 set_dma_config(drv_data
->dma_channel
, dma_config
);
724 set_dma_start_addr(drv_data
->dma_channel
,
725 (unsigned long)drv_data
->tx
);
726 enable_dma(drv_data
->dma_channel
);
728 /* start SPI transfer */
729 bfin_write(&drv_data
->regs
->ctl
, cr
| BIT_CTL_TIMOD_DMA_TX
);
731 /* just return here, there can only be one transfer
735 bfin_spi_giveback(drv_data
);
739 /* In dma mode, rx or tx must be NULL in one transfer */
740 dma_config
= (RESTART
| dma_width
| DI_EN
);
741 if (drv_data
->rx
!= NULL
) {
742 /* set transfer mode, and enable SPI */
743 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA in to %p (size %zx)\n",
744 drv_data
->rx
, drv_data
->len_in_bytes
);
746 /* invalidate caches, if needed */
747 if (bfin_addr_dcacheable((unsigned long) drv_data
->rx
))
748 invalidate_dcache_range((unsigned long) drv_data
->rx
,
749 (unsigned long) (drv_data
->rx
+
750 drv_data
->len_in_bytes
));
753 dma_start_addr
= (unsigned long)drv_data
->rx
;
754 cr
|= BIT_CTL_TIMOD_DMA_RX
| BIT_CTL_SENDOPT
;
756 } else if (drv_data
->tx
!= NULL
) {
757 dev_dbg(&drv_data
->pdev
->dev
, "doing DMA out.\n");
759 /* flush caches, if needed */
760 if (bfin_addr_dcacheable((unsigned long) drv_data
->tx
))
761 flush_dcache_range((unsigned long) drv_data
->tx
,
762 (unsigned long) (drv_data
->tx
+
763 drv_data
->len_in_bytes
));
765 dma_start_addr
= (unsigned long)drv_data
->tx
;
766 cr
|= BIT_CTL_TIMOD_DMA_TX
;
771 /* oh man, here there be monsters ... and i dont mean the
772 * fluffy cute ones from pixar, i mean the kind that'll eat
773 * your data, kick your dog, and love it all. do *not* try
774 * and change these lines unless you (1) heavily test DMA
775 * with SPI flashes on a loaded system (e.g. ping floods),
776 * (2) know just how broken the DMA engine interaction with
777 * the SPI peripheral is, and (3) have someone else to blame
778 * when you screw it all up anyways.
780 set_dma_start_addr(drv_data
->dma_channel
, dma_start_addr
);
781 set_dma_config(drv_data
->dma_channel
, dma_config
);
782 local_irq_save(flags
);
784 bfin_write(&drv_data
->regs
->ctl
, cr
);
785 enable_dma(drv_data
->dma_channel
);
786 dma_enable_irq(drv_data
->dma_channel
);
787 local_irq_restore(flags
);
793 * We always use SPI_WRITE mode (transfer starts with TDBR write).
794 * SPI_READ mode (transfer starts with RDBR read) seems to have
795 * problems with setting up the output value in TDBR prior to the
796 * start of the transfer.
798 bfin_write(&drv_data
->regs
->ctl
, cr
| BIT_CTL_TXMOD
);
800 if (chip
->pio_interrupt
) {
801 /* SPI irq should have been disabled by now */
803 /* discard old RX data and clear RXS */
804 bfin_spi_dummy_read(drv_data
);
807 if (drv_data
->tx
== NULL
)
808 bfin_write(&drv_data
->regs
->tdbr
, chip
->idle_tx_val
);
811 if (bits_per_word
% 16 == 0) {
812 u16
*buf
= (u16
*)drv_data
->tx
;
813 for (loop
= 0; loop
< bits_per_word
/ 16;
815 bfin_write(&drv_data
->regs
->tdbr
, *buf
++);
817 } else if (bits_per_word
% 8 == 0) {
818 u8
*buf
= (u8
*)drv_data
->tx
;
819 for (loop
= 0; loop
< bits_per_word
/ 8; loop
++)
820 bfin_write(&drv_data
->regs
->tdbr
, *buf
++);
823 drv_data
->tx
+= drv_data
->n_bytes
;
826 /* once TDBR is empty, interrupt is triggered */
827 enable_irq(drv_data
->spi_irq
);
832 dev_dbg(&drv_data
->pdev
->dev
, "doing IO transfer\n");
835 /* full duplex mode */
836 BUG_ON((drv_data
->tx_end
- drv_data
->tx
) !=
837 (drv_data
->rx_end
- drv_data
->rx
));
838 dev_dbg(&drv_data
->pdev
->dev
,
839 "IO duplex: cr is 0x%x\n", cr
);
841 drv_data
->ops
->duplex(drv_data
);
843 if (drv_data
->tx
!= drv_data
->tx_end
)
845 } else if (drv_data
->tx
!= NULL
) {
846 /* write only half duplex */
847 dev_dbg(&drv_data
->pdev
->dev
,
848 "IO write: cr is 0x%x\n", cr
);
850 drv_data
->ops
->write(drv_data
);
852 if (drv_data
->tx
!= drv_data
->tx_end
)
854 } else if (drv_data
->rx
!= NULL
) {
855 /* read only half duplex */
856 dev_dbg(&drv_data
->pdev
->dev
,
857 "IO read: cr is 0x%x\n", cr
);
859 drv_data
->ops
->read(drv_data
);
860 if (drv_data
->rx
!= drv_data
->rx_end
)
864 if (!tranf_success
) {
865 dev_dbg(&drv_data
->pdev
->dev
,
866 "IO write error!\n");
867 message
->state
= ERROR_STATE
;
869 /* Update total byte transferred */
870 message
->actual_length
+= drv_data
->len_in_bytes
;
871 /* Move to next transfer of this msg */
872 message
->state
= bfin_spi_next_transfer(drv_data
);
873 if (drv_data
->cs_change
&& message
->state
!= DONE_STATE
) {
874 bfin_spi_flush(drv_data
);
875 bfin_spi_cs_deactive(drv_data
, chip
);
879 /* Schedule next transfer tasklet */
880 tasklet_schedule(&drv_data
->pump_transfers
);
883 /* pop a msg from queue and kick off real transfer */
884 static void bfin_spi_pump_messages(struct work_struct
*work
)
886 struct bfin_spi_master_data
*drv_data
;
889 drv_data
= container_of(work
, struct bfin_spi_master_data
, pump_messages
);
891 /* Lock queue and check for queue work */
892 spin_lock_irqsave(&drv_data
->lock
, flags
);
893 if (list_empty(&drv_data
->queue
) || !drv_data
->running
) {
894 /* pumper kicked off but no work to do */
896 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
900 /* Make sure we are not already running a message */
901 if (drv_data
->cur_msg
) {
902 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
906 /* Extract head of queue */
907 drv_data
->cur_msg
= list_entry(drv_data
->queue
.next
,
908 struct spi_message
, queue
);
910 /* Setup the SSP using the per chip configuration */
911 drv_data
->cur_chip
= spi_get_ctldata(drv_data
->cur_msg
->spi
);
912 bfin_spi_restore_state(drv_data
);
914 list_del_init(&drv_data
->cur_msg
->queue
);
916 /* Initial message state */
917 drv_data
->cur_msg
->state
= START_STATE
;
918 drv_data
->cur_transfer
= list_entry(drv_data
->cur_msg
->transfers
.next
,
919 struct spi_transfer
, transfer_list
);
921 dev_dbg(&drv_data
->pdev
->dev
, "got a message to pump, "
922 "state is set to: baud %d, flag 0x%x, ctl 0x%x\n",
923 drv_data
->cur_chip
->baud
, drv_data
->cur_chip
->flag
,
924 drv_data
->cur_chip
->ctl_reg
);
926 dev_dbg(&drv_data
->pdev
->dev
,
927 "the first transfer len is %d\n",
928 drv_data
->cur_transfer
->len
);
930 /* Mark as busy and launch transfers */
931 tasklet_schedule(&drv_data
->pump_transfers
);
934 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
938 * got a msg to transfer, queue it in drv_data->queue.
939 * And kick off message pumper
941 static int bfin_spi_transfer(struct spi_device
*spi
, struct spi_message
*msg
)
943 struct bfin_spi_master_data
*drv_data
= spi_master_get_devdata(spi
->master
);
946 spin_lock_irqsave(&drv_data
->lock
, flags
);
948 if (!drv_data
->running
) {
949 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
953 msg
->actual_length
= 0;
954 msg
->status
= -EINPROGRESS
;
955 msg
->state
= START_STATE
;
957 dev_dbg(&spi
->dev
, "adding an msg in transfer() \n");
958 list_add_tail(&msg
->queue
, &drv_data
->queue
);
960 if (drv_data
->running
&& !drv_data
->busy
)
961 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
963 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
968 #define MAX_SPI_SSEL 7
970 static const u16 ssel
[][MAX_SPI_SSEL
] = {
971 {P_SPI0_SSEL1
, P_SPI0_SSEL2
, P_SPI0_SSEL3
,
972 P_SPI0_SSEL4
, P_SPI0_SSEL5
,
973 P_SPI0_SSEL6
, P_SPI0_SSEL7
},
975 {P_SPI1_SSEL1
, P_SPI1_SSEL2
, P_SPI1_SSEL3
,
976 P_SPI1_SSEL4
, P_SPI1_SSEL5
,
977 P_SPI1_SSEL6
, P_SPI1_SSEL7
},
979 {P_SPI2_SSEL1
, P_SPI2_SSEL2
, P_SPI2_SSEL3
,
980 P_SPI2_SSEL4
, P_SPI2_SSEL5
,
981 P_SPI2_SSEL6
, P_SPI2_SSEL7
},
984 /* setup for devices (may be called multiple times -- not just first setup) */
985 static int bfin_spi_setup(struct spi_device
*spi
)
987 struct bfin5xx_spi_chip
*chip_info
;
988 struct bfin_spi_slave_data
*chip
= NULL
;
989 struct bfin_spi_master_data
*drv_data
= spi_master_get_devdata(spi
->master
);
993 /* Only alloc (or use chip_info) on first setup */
995 chip
= spi_get_ctldata(spi
);
997 chip
= kzalloc(sizeof(*chip
), GFP_KERNEL
);
999 dev_err(&spi
->dev
, "cannot allocate chip data\n");
1004 chip
->enable_dma
= 0;
1005 chip_info
= spi
->controller_data
;
1008 /* Let people set non-standard bits directly */
1009 bfin_ctl_reg
= BIT_CTL_OPENDRAIN
| BIT_CTL_EMISO
|
1010 BIT_CTL_PSSE
| BIT_CTL_GM
| BIT_CTL_SZ
;
1012 /* chip_info isn't always needed */
1014 /* Make sure people stop trying to set fields via ctl_reg
1015 * when they should actually be using common SPI framework.
1016 * Currently we let through: WOM EMISO PSSE GM SZ.
1017 * Not sure if a user actually needs/uses any of these,
1018 * but let's assume (for now) they do.
1020 if (chip_info
->ctl_reg
& ~bfin_ctl_reg
) {
1021 dev_err(&spi
->dev
, "do not set bits in ctl_reg "
1022 "that the SPI framework manages\n");
1025 chip
->enable_dma
= chip_info
->enable_dma
!= 0
1026 && drv_data
->master_info
->enable_dma
;
1027 chip
->ctl_reg
= chip_info
->ctl_reg
;
1028 chip
->cs_chg_udelay
= chip_info
->cs_chg_udelay
;
1029 chip
->idle_tx_val
= chip_info
->idle_tx_val
;
1030 chip
->pio_interrupt
= chip_info
->pio_interrupt
;
1032 /* force a default base state */
1033 chip
->ctl_reg
&= bfin_ctl_reg
;
1036 if (spi
->bits_per_word
% 8) {
1037 dev_err(&spi
->dev
, "%d bits_per_word is not supported\n",
1038 spi
->bits_per_word
);
1042 /* translate common spi framework into our register */
1043 if (spi
->mode
& ~(SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
)) {
1044 dev_err(&spi
->dev
, "unsupported spi modes detected\n");
1047 if (spi
->mode
& SPI_CPOL
)
1048 chip
->ctl_reg
|= BIT_CTL_CPOL
;
1049 if (spi
->mode
& SPI_CPHA
)
1050 chip
->ctl_reg
|= BIT_CTL_CPHA
;
1051 if (spi
->mode
& SPI_LSB_FIRST
)
1052 chip
->ctl_reg
|= BIT_CTL_LSBF
;
1053 /* we dont support running in slave mode (yet?) */
1054 chip
->ctl_reg
|= BIT_CTL_MASTER
;
1057 * Notice: for blackfin, the speed_hz is the value of register
1058 * SPI_BAUD, not the real baudrate
1060 chip
->baud
= hz_to_spi_baud(spi
->max_speed_hz
);
1061 chip
->chip_select_num
= spi
->chip_select
;
1062 if (chip
->chip_select_num
< MAX_CTRL_CS
) {
1063 if (!(spi
->mode
& SPI_CPHA
))
1064 dev_warn(&spi
->dev
, "Warning: SPI CPHA not set:"
1065 " Slave Select not under software control!\n"
1066 " See Documentation/blackfin/bfin-spi-notes.txt");
1068 chip
->flag
= (1 << spi
->chip_select
) << 8;
1070 chip
->cs_gpio
= chip
->chip_select_num
- MAX_CTRL_CS
;
1072 if (chip
->enable_dma
&& chip
->pio_interrupt
) {
1073 dev_err(&spi
->dev
, "enable_dma is set, "
1074 "do not set pio_interrupt\n");
1078 * if any one SPI chip is registered and wants DMA, request the
1079 * DMA channel for it
1081 if (chip
->enable_dma
&& !drv_data
->dma_requested
) {
1082 /* register dma irq handler */
1083 ret
= request_dma(drv_data
->dma_channel
, "BFIN_SPI_DMA");
1086 "Unable to request BlackFin SPI DMA channel\n");
1089 drv_data
->dma_requested
= 1;
1091 ret
= set_dma_callback(drv_data
->dma_channel
,
1092 bfin_spi_dma_irq_handler
, drv_data
);
1094 dev_err(&spi
->dev
, "Unable to set dma callback\n");
1097 dma_disable_irq(drv_data
->dma_channel
);
1100 if (chip
->pio_interrupt
&& !drv_data
->irq_requested
) {
1101 ret
= request_irq(drv_data
->spi_irq
, bfin_spi_pio_irq_handler
,
1102 0, "BFIN_SPI", drv_data
);
1104 dev_err(&spi
->dev
, "Unable to register spi IRQ\n");
1107 drv_data
->irq_requested
= 1;
1108 /* we use write mode, spi irq has to be disabled here */
1109 disable_irq(drv_data
->spi_irq
);
1112 if (chip
->chip_select_num
>= MAX_CTRL_CS
) {
1113 /* Only request on first setup */
1114 if (spi_get_ctldata(spi
) == NULL
) {
1115 ret
= gpio_request(chip
->cs_gpio
, spi
->modalias
);
1117 dev_err(&spi
->dev
, "gpio_request() error\n");
1120 gpio_direction_output(chip
->cs_gpio
, 1);
1124 dev_dbg(&spi
->dev
, "setup spi chip %s, width is %d, dma is %d\n",
1125 spi
->modalias
, spi
->bits_per_word
, chip
->enable_dma
);
1126 dev_dbg(&spi
->dev
, "ctl_reg is 0x%x, flag_reg is 0x%x\n",
1127 chip
->ctl_reg
, chip
->flag
);
1129 spi_set_ctldata(spi
, chip
);
1131 dev_dbg(&spi
->dev
, "chip select number is %d\n", chip
->chip_select_num
);
1132 if (chip
->chip_select_num
< MAX_CTRL_CS
) {
1133 ret
= peripheral_request(ssel
[spi
->master
->bus_num
]
1134 [chip
->chip_select_num
-1], spi
->modalias
);
1136 dev_err(&spi
->dev
, "peripheral_request() error\n");
1141 bfin_spi_cs_enable(drv_data
, chip
);
1142 bfin_spi_cs_deactive(drv_data
, chip
);
1147 if (chip
->chip_select_num
>= MAX_CTRL_CS
)
1148 gpio_free(chip
->cs_gpio
);
1150 peripheral_free(ssel
[spi
->master
->bus_num
]
1151 [chip
->chip_select_num
- 1]);
1154 if (drv_data
->dma_requested
)
1155 free_dma(drv_data
->dma_channel
);
1156 drv_data
->dma_requested
= 0;
1159 /* prevent free 'chip' twice */
1160 spi_set_ctldata(spi
, NULL
);
1167 * callback for spi framework.
1168 * clean driver specific data
1170 static void bfin_spi_cleanup(struct spi_device
*spi
)
1172 struct bfin_spi_slave_data
*chip
= spi_get_ctldata(spi
);
1173 struct bfin_spi_master_data
*drv_data
= spi_master_get_devdata(spi
->master
);
1178 if (chip
->chip_select_num
< MAX_CTRL_CS
) {
1179 peripheral_free(ssel
[spi
->master
->bus_num
]
1180 [chip
->chip_select_num
-1]);
1181 bfin_spi_cs_disable(drv_data
, chip
);
1183 gpio_free(chip
->cs_gpio
);
1186 /* prevent free 'chip' twice */
1187 spi_set_ctldata(spi
, NULL
);
1190 static int bfin_spi_init_queue(struct bfin_spi_master_data
*drv_data
)
1192 INIT_LIST_HEAD(&drv_data
->queue
);
1193 spin_lock_init(&drv_data
->lock
);
1195 drv_data
->running
= false;
1198 /* init transfer tasklet */
1199 tasklet_init(&drv_data
->pump_transfers
,
1200 bfin_spi_pump_transfers
, (unsigned long)drv_data
);
1202 /* init messages workqueue */
1203 INIT_WORK(&drv_data
->pump_messages
, bfin_spi_pump_messages
);
1204 drv_data
->workqueue
= create_singlethread_workqueue(
1205 dev_name(drv_data
->master
->dev
.parent
));
1206 if (drv_data
->workqueue
== NULL
)
1212 static int bfin_spi_start_queue(struct bfin_spi_master_data
*drv_data
)
1214 unsigned long flags
;
1216 spin_lock_irqsave(&drv_data
->lock
, flags
);
1218 if (drv_data
->running
|| drv_data
->busy
) {
1219 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1223 drv_data
->running
= true;
1224 drv_data
->cur_msg
= NULL
;
1225 drv_data
->cur_transfer
= NULL
;
1226 drv_data
->cur_chip
= NULL
;
1227 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1229 queue_work(drv_data
->workqueue
, &drv_data
->pump_messages
);
1234 static int bfin_spi_stop_queue(struct bfin_spi_master_data
*drv_data
)
1236 unsigned long flags
;
1237 unsigned limit
= 500;
1240 spin_lock_irqsave(&drv_data
->lock
, flags
);
1243 * This is a bit lame, but is optimized for the common execution path.
1244 * A wait_queue on the drv_data->busy could be used, but then the common
1245 * execution path (pump_messages) would be required to call wake_up or
1246 * friends on every SPI message. Do this instead
1248 drv_data
->running
= false;
1249 while ((!list_empty(&drv_data
->queue
) || drv_data
->busy
) && limit
--) {
1250 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1252 spin_lock_irqsave(&drv_data
->lock
, flags
);
1255 if (!list_empty(&drv_data
->queue
) || drv_data
->busy
)
1258 spin_unlock_irqrestore(&drv_data
->lock
, flags
);
1263 static int bfin_spi_destroy_queue(struct bfin_spi_master_data
*drv_data
)
1267 status
= bfin_spi_stop_queue(drv_data
);
1271 destroy_workqueue(drv_data
->workqueue
);
1276 static int bfin_spi_probe(struct platform_device
*pdev
)
1278 struct device
*dev
= &pdev
->dev
;
1279 struct bfin5xx_spi_master
*platform_info
;
1280 struct spi_master
*master
;
1281 struct bfin_spi_master_data
*drv_data
;
1282 struct resource
*res
;
1285 platform_info
= dev
->platform_data
;
1287 /* Allocate master with space for drv_data */
1288 master
= spi_alloc_master(dev
, sizeof(*drv_data
));
1290 dev_err(&pdev
->dev
, "can not alloc spi_master\n");
1294 drv_data
= spi_master_get_devdata(master
);
1295 drv_data
->master
= master
;
1296 drv_data
->master_info
= platform_info
;
1297 drv_data
->pdev
= pdev
;
1298 drv_data
->pin_req
= platform_info
->pin_req
;
1300 /* the spi->mode bits supported by this driver: */
1301 master
->mode_bits
= SPI_CPOL
| SPI_CPHA
| SPI_LSB_FIRST
;
1303 master
->bus_num
= pdev
->id
;
1304 master
->num_chipselect
= platform_info
->num_chipselect
;
1305 master
->cleanup
= bfin_spi_cleanup
;
1306 master
->setup
= bfin_spi_setup
;
1307 master
->transfer
= bfin_spi_transfer
;
1309 /* Find and map our resources */
1310 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1312 dev_err(dev
, "Cannot get IORESOURCE_MEM\n");
1314 goto out_error_get_res
;
1317 drv_data
->regs
= ioremap(res
->start
, resource_size(res
));
1318 if (drv_data
->regs
== NULL
) {
1319 dev_err(dev
, "Cannot map IO\n");
1321 goto out_error_ioremap
;
1324 res
= platform_get_resource(pdev
, IORESOURCE_DMA
, 0);
1326 dev_err(dev
, "No DMA channel specified\n");
1328 goto out_error_free_io
;
1330 drv_data
->dma_channel
= res
->start
;
1332 drv_data
->spi_irq
= platform_get_irq(pdev
, 0);
1333 if (drv_data
->spi_irq
< 0) {
1334 dev_err(dev
, "No spi pio irq specified\n");
1336 goto out_error_free_io
;
1339 /* Initial and start queue */
1340 status
= bfin_spi_init_queue(drv_data
);
1342 dev_err(dev
, "problem initializing queue\n");
1343 goto out_error_queue_alloc
;
1346 status
= bfin_spi_start_queue(drv_data
);
1348 dev_err(dev
, "problem starting queue\n");
1349 goto out_error_queue_alloc
;
1352 status
= peripheral_request_list(drv_data
->pin_req
, DRV_NAME
);
1354 dev_err(&pdev
->dev
, ": Requesting Peripherals failed\n");
1355 goto out_error_queue_alloc
;
1358 /* Reset SPI registers. If these registers were used by the boot loader,
1359 * the sky may fall on your head if you enable the dma controller.
1361 bfin_write(&drv_data
->regs
->ctl
, BIT_CTL_CPHA
| BIT_CTL_MASTER
);
1362 bfin_write(&drv_data
->regs
->flg
, 0xFF00);
1364 /* Register with the SPI framework */
1365 platform_set_drvdata(pdev
, drv_data
);
1366 status
= spi_register_master(master
);
1368 dev_err(dev
, "problem registering spi master\n");
1369 goto out_error_queue_alloc
;
1372 dev_info(dev
, "%s, Version %s, regs@%p, dma channel@%d\n",
1373 DRV_DESC
, DRV_VERSION
, drv_data
->regs
,
1374 drv_data
->dma_channel
);
1377 out_error_queue_alloc
:
1378 bfin_spi_destroy_queue(drv_data
);
1380 iounmap(drv_data
->regs
);
1383 spi_master_put(master
);
1388 /* stop hardware and remove the driver */
1389 static int bfin_spi_remove(struct platform_device
*pdev
)
1391 struct bfin_spi_master_data
*drv_data
= platform_get_drvdata(pdev
);
1397 /* Remove the queue */
1398 status
= bfin_spi_destroy_queue(drv_data
);
1402 /* Disable the SSP at the peripheral and SOC level */
1403 bfin_spi_disable(drv_data
);
1406 if (drv_data
->master_info
->enable_dma
) {
1407 if (dma_channel_active(drv_data
->dma_channel
))
1408 free_dma(drv_data
->dma_channel
);
1411 if (drv_data
->irq_requested
) {
1412 free_irq(drv_data
->spi_irq
, drv_data
);
1413 drv_data
->irq_requested
= 0;
1416 /* Disconnect from the SPI framework */
1417 spi_unregister_master(drv_data
->master
);
1419 peripheral_free_list(drv_data
->pin_req
);
1421 /* Prevent double remove */
1422 platform_set_drvdata(pdev
, NULL
);
1428 static int bfin_spi_suspend(struct platform_device
*pdev
, pm_message_t state
)
1430 struct bfin_spi_master_data
*drv_data
= platform_get_drvdata(pdev
);
1433 status
= bfin_spi_stop_queue(drv_data
);
1437 drv_data
->ctrl_reg
= bfin_read(&drv_data
->regs
->ctl
);
1438 drv_data
->flag_reg
= bfin_read(&drv_data
->regs
->flg
);
1441 * reset SPI_CTL and SPI_FLG registers
1443 bfin_write(&drv_data
->regs
->ctl
, BIT_CTL_CPHA
| BIT_CTL_MASTER
);
1444 bfin_write(&drv_data
->regs
->flg
, 0xFF00);
1449 static int bfin_spi_resume(struct platform_device
*pdev
)
1451 struct bfin_spi_master_data
*drv_data
= platform_get_drvdata(pdev
);
1454 bfin_write(&drv_data
->regs
->ctl
, drv_data
->ctrl_reg
);
1455 bfin_write(&drv_data
->regs
->flg
, drv_data
->flag_reg
);
1457 /* Start the queue running */
1458 status
= bfin_spi_start_queue(drv_data
);
1460 dev_err(&pdev
->dev
, "problem starting queue (%d)\n", status
);
1467 #define bfin_spi_suspend NULL
1468 #define bfin_spi_resume NULL
1469 #endif /* CONFIG_PM */
1471 MODULE_ALIAS("platform:bfin-spi");
1472 static struct platform_driver bfin_spi_driver
= {
1475 .owner
= THIS_MODULE
,
1477 .suspend
= bfin_spi_suspend
,
1478 .resume
= bfin_spi_resume
,
1479 .remove
= bfin_spi_remove
,
1482 static int __init
bfin_spi_init(void)
1484 return platform_driver_probe(&bfin_spi_driver
, bfin_spi_probe
);
1486 subsys_initcall(bfin_spi_init
);
1488 static void __exit
bfin_spi_exit(void)
1490 platform_driver_unregister(&bfin_spi_driver
);
1492 module_exit(bfin_spi_exit
);