| blob | 3c0221620c9dc8abae3bf4edb06102475bd27df9 |
1 /* Intel(R) Gigabit Ethernet Linux driver
2 * Copyright(c) 2007-2014 Intel Corporation.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License along with
14 * this program; if not, see <http://www.gnu.org/licenses/>.
15 *
16 * The full GNU General Public License is included in this distribution in
17 * the file called "COPYING".
18 *
19 * Contact Information:
20 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
21 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
22 */
26 #include <linux/module.h>
27 #include <linux/types.h>
28 #include <linux/init.h>
29 #include <linux/bitops.h>
30 #include <linux/vmalloc.h>
31 #include <linux/pagemap.h>
32 #include <linux/netdevice.h>
33 #include <linux/ipv6.h>
34 #include <linux/slab.h>
35 #include <net/checksum.h>
36 #include <net/ip6_checksum.h>
37 #include <linux/net_tstamp.h>
38 #include <linux/mii.h>
39 #include <linux/ethtool.h>
40 #include <linux/if.h>
41 #include <linux/if_vlan.h>
42 #include <linux/pci.h>
43 #include <linux/pci-aspm.h>
44 #include <linux/delay.h>
45 #include <linux/interrupt.h>
46 #include <linux/ip.h>
47 #include <linux/tcp.h>
48 #include <linux/sctp.h>
49 #include <linux/if_ether.h>
50 #include <linux/aer.h>
51 #include <linux/prefetch.h>
52 #include <linux/pm_runtime.h>
53 #ifdef CONFIG_IGB_DCA
54 #include <linux/dca.h>
55 #endif
56 #include <linux/i2c.h>
59 #define MAJ 5
60 #define MIN 2
61 #define BUILD 15
73 };
111 /* required last entry */
113 };
148 #ifdef CONFIG_IGB_DCA
159 netdev_features_t features);
179 #ifdef CONFIG_PCI_IOV
182 #endif
184 #ifdef CONFIG_PM
185 #ifdef CONFIG_PM_SLEEP
187 #endif
189 #ifdef CONFIG_PM_RUNTIME
193 #endif
197 igb_runtime_idle)
198 };
199 #endif
202 #ifdef CONFIG_IGB_DCA
208 };
209 #endif
210 #ifdef CONFIG_NET_POLL_CONTROLLER
211 /* for netdump / net console */
213 #endif
214 #ifdef CONFIG_PCI_IOV
217 MODULE_PARM_DESC(max_vfs, "Maximum number of virtual functions to allocate per physical function");
221 pci_channel_state_t);
229 };
238 #ifdef CONFIG_PM
240 #endif
244 };
251 #define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV|NETIF_MSG_PROBE|NETIF_MSG_LINK)
257 u32 ofs;
259 };
263 /* General Registers */
268 /* Interrupt Registers */
271 /* RX Registers */
280 /* TX Registers */
293 /* List Terminator */
294 {}
295 };
297 /* igb_regdump - register printout routine */
299 {
356 }
361 }
363 /* igb_dump - Print registers, Tx-rings and Rx-rings */
365 {
374 u32 staterr;
380 /* Print netdevice Info */
386 }
388 /* Print Registers */
394 }
396 /* Print TX Ring Summary */
412 }
414 /* Print TX Rings */
420 /* Transmit Descriptor Formats
421 *
422 * Advanced Transmit Descriptor
423 * +--------------------------------------------------------------+
424 * 0 | Buffer Address [63:0] |
425 * +--------------------------------------------------------------+
426 * 8 | PAYLEN | PORTS |CC|IDX | STA | DCMD |DTYP|MAC|RSV| DTALEN |
427 * +--------------------------------------------------------------+
428 * 63 46 45 40 39 38 36 35 32 31 24 15 0
429 */
451 else
465 DUMP_PREFIX_ADDRESS,
469 }
470 }
472 /* Print RX Rings Summary */
473 rx_ring_summary:
480 }
482 /* Print RX Rings */
488 /* Advanced Receive Descriptor (Read) Format
489 * 63 1 0
490 * +-----------------------------------------------------+
491 * 0 | Packet Buffer Address [63:1] |A0/NSE|
492 * +----------------------------------------------+------+
493 * 8 | Header Buffer Address [63:1] | DD |
494 * +-----------------------------------------------------+
495 *
496 *
497 * Advanced Receive Descriptor (Write-Back) Format
498 *
499 * 63 48 47 32 31 30 21 20 17 16 4 3 0
500 * +------------------------------------------------------+
501 * 0 | Packet IP |SPH| HDR_LEN | RSV|Packet| RSS |
502 * | Checksum Ident | | | | Type | Type |
503 * +------------------------------------------------------+
504 * 8 | VLAN Tag | Length | Extended Error | Extended Status |
505 * +------------------------------------------------------+
506 * 63 48 47 32 31 20 19 0
507 */
515 pr_info("RWB[desc] [PcsmIpSHl PtRs] [vl er S cks ln] ---------------- [bi->skb] <-- Adv Rx Write-Back format\n");
529 else
533 /* Descriptor Done */
538 next_desc);
545 next_desc);
550 DUMP_PREFIX_ADDRESS,
555 }
556 }
557 }
558 }
560 exit:
562 }
564 /**
565 * igb_get_i2c_data - Reads the I2C SDA data bit
566 * @hw: pointer to hardware structure
567 * @i2cctl: Current value of I2CCTL register
568 *
569 * Returns the I2C data bit value
570 **/
572 {
578 }
580 /**
581 * igb_set_i2c_data - Sets the I2C data bit
582 * @data: pointer to hardware structure
583 * @state: I2C data value (0 or 1) to set
584 *
585 * Sets the I2C data bit
586 **/
588 {
595 else
603 }
605 /**
606 * igb_set_i2c_clk - Sets the I2C SCL clock
607 * @data: pointer to hardware structure
608 * @state: state to set clock
609 *
610 * Sets the I2C clock line to state
611 **/
613 {
624 }
627 }
629 /**
630 * igb_get_i2c_clk - Gets the I2C SCL clock state
631 * @data: pointer to hardware structure
632 *
633 * Gets the I2C clock state
634 **/
636 {
642 }
651 };
653 /**
654 * igb_get_hw_dev - return device
655 * @hw: pointer to hardware structure
656 *
657 * used by hardware layer to print debugging information
658 **/
660 {
663 }
665 /**
666 * igb_init_module - Driver Registration Routine
667 *
668 * igb_init_module is the first routine called when the driver is
669 * loaded. All it does is register with the PCI subsystem.
670 **/
672 {
679 #ifdef CONFIG_IGB_DCA
681 #endif
684 }
688 /**
689 * igb_exit_module - Driver Exit Cleanup Routine
690 *
691 * igb_exit_module is called just before the driver is removed
692 * from memory.
693 **/
695 {
696 #ifdef CONFIG_IGB_DCA
698 #endif
700 }
704 #define Q_IDX_82576(i) (((i & 0x1) << 3) + (i >> 1))
705 /**
706 * igb_cache_ring_register - Descriptor ring to register mapping
707 * @adapter: board private structure to initialize
708 *
709 * Once we know the feature-set enabled for the device, we'll cache
710 * the register offset the descriptor ring is assigned to.
711 **/
713 {
719 /* The queues are allocated for virtualization such that VF 0
720 * is allocated queues 0 and 8, VF 1 queues 1 and 9, etc.
721 * In order to avoid collision we start at the first free queue
722 * and continue consuming queues in the same sequence
723 */
728 }
729 /* Fall through */
736 /* Fall through */
743 }
744 }
747 {
757 /* reads should not return all F's */
763 }
766 }
768 /**
769 * igb_write_ivar - configure ivar for given MSI-X vector
770 * @hw: pointer to the HW structure
771 * @msix_vector: vector number we are allocating to a given ring
772 * @index: row index of IVAR register to write within IVAR table
773 * @offset: column offset of in IVAR, should be multiple of 8
774 *
775 * This function is intended to handle the writing of the IVAR register
776 * for adapters 82576 and newer. The IVAR table consists of 2 columns,
777 * each containing an cause allocation for an Rx and Tx ring, and a
778 * variable number of rows depending on the number of queues supported.
779 **/
782 {
785 /* clear any bits that are currently set */
788 /* write vector and valid bit */
792 }
794 #define IGB_N0_QUEUE -1
796 {
810 /* The 82575 assigns vectors using a bitmask, which matches the
811 * bitmask for the EICR/EIMS/EIMC registers. To assign one
812 * or more queues to a vector, we write the appropriate bits
813 * into the MSIXBM register for that vector.
814 */
825 /* 82576 uses a table that essentially consists of 2 columns
826 * with 8 rows. The ordering is column-major so we use the
827 * lower 3 bits as the row index, and the 4th bit as the
828 * column offset.
829 */
845 /* On 82580 and newer adapters the scheme is similar to 82576
846 * however instead of ordering column-major we have things
847 * ordered row-major. So we traverse the table by using
848 * bit 0 as the column offset, and the remaining bits as the
849 * row index.
850 */
864 }
866 /* add q_vector eims value to global eims_enable_mask */
869 /* configure q_vector to set itr on first interrupt */
871 }
873 /**
874 * igb_configure_msix - Configure MSI-X hardware
875 * @adapter: board private structure to initialize
876 *
877 * igb_configure_msix sets up the hardware to properly
878 * generate MSI-X interrupts.
879 **/
881 {
882 u32 tmp;
888 /* set vector for other causes, i.e. link changes */
892 /* enable MSI-X PBA support*/
895 /* Auto-Mask interrupts upon ICR read. */
901 /* enable msix_other interrupt */
913 /* Turn on MSI-X capability first, or our settings
914 * won't stick. And it will take days to debug.
915 */
918 E1000_GPIE_NSICR);
920 /* enable msix_other interrupt */
927 /* do nothing, since nothing else supports MSI-X */
937 }
939 /**
940 * igb_request_msix - Initialize MSI-X interrupts
941 * @adapter: board private structure to initialize
942 *
943 * igb_request_msix allocates MSI-X vectors and requests interrupts from the
944 * kernel.
945 **/
947 {
960 vector++;
973 else
978 q_vector);
981 }
986 err_free:
987 /* free already assigned IRQs */
990 vector--;
994 }
995 err_out:
997 }
999 /**
1000 * igb_free_q_vector - Free memory allocated for specific interrupt vector
1001 * @adapter: board private structure to initialize
1002 * @v_idx: Index of vector to be freed
1003 *
1004 * This function frees the memory allocated to the q_vector.
1005 **/
1007 {
1012 /* igb_get_stats64() might access the rings on this vector,
1013 * we must wait a grace period before freeing it.
1014 */
1017 }
1019 /**
1020 * igb_reset_q_vector - Reset config for interrupt vector
1021 * @adapter: board private structure to initialize
1022 * @v_idx: Index of vector to be reset
1023 *
1024 * If NAPI is enabled it will delete any references to the
1025 * NAPI struct. This is preparation for igb_free_q_vector.
1026 **/
1028 {
1031 /* Coming from igb_set_interrupt_capability, the vectors are not yet
1032 * allocated. So, q_vector is NULL so we should stop here.
1033 */
1045 }
1048 {
1058 }
1060 /**
1061 * igb_free_q_vectors - Free memory allocated for interrupt vectors
1062 * @adapter: board private structure to initialize
1063 *
1064 * This function frees the memory allocated to the q_vectors. In addition if
1065 * NAPI is enabled it will delete any references to the NAPI struct prior
1066 * to freeing the q_vector.
1067 **/
1069 {
1079 }
1080 }
1082 /**
1083 * igb_clear_interrupt_scheme - reset the device to a state of no interrupts
1084 * @adapter: board private structure to initialize
1085 *
1086 * This function resets the device so that it has 0 Rx queues, Tx queues, and
1087 * MSI-X interrupts allocated.
1088 */
1090 {
1093 }
1095 /**
1096 * igb_set_interrupt_capability - set MSI or MSI-X if supported
1097 * @adapter: board private structure to initialize
1098 * @msix: boolean value of MSIX capability
1099 *
1100 * Attempt to configure interrupts using the best available
1101 * capabilities of the hardware and kernel.
1102 **/
1104 {
1112 /* Number of supported queues. */
1116 else
1119 /* start with one vector for every Rx queue */
1122 /* if Tx handler is separate add 1 for every Tx queue */
1126 /* store the number of vectors reserved for queues */
1129 /* add 1 vector for link status interrupts */
1130 numvecs++;
1136 numvecs,
1137 numvecs);
1143 /* If we can't do MSI-X, try MSI */
1144 msi_only:
1146 #ifdef CONFIG_PCI_IOV
1147 /* disable SR-IOV for non MSI-X configurations */
1150 /* disable iov and allow time for transactions to clear */
1160 }
1161 #endif
1170 }
1174 {
1177 }
1179 /**
1180 * igb_alloc_q_vector - Allocate memory for a single interrupt vector
1181 * @adapter: board private structure to initialize
1182 * @v_count: q_vectors allocated on adapter, used for ring interleaving
1183 * @v_idx: index of vector in adapter struct
1184 * @txr_count: total number of Tx rings to allocate
1185 * @txr_idx: index of first Tx ring to allocate
1186 * @rxr_count: total number of Rx rings to allocate
1187 * @rxr_idx: index of first Rx ring to allocate
1188 *
1189 * We allocate one q_vector. If allocation fails we return -ENOMEM.
1190 **/
1195 {
1200 /* igb only supports 1 Tx and/or 1 Rx queue per vector */
1208 /* allocate q_vector and rings */
1215 /* initialize NAPI */
1219 /* tie q_vector and adapter together */
1223 /* initialize work limits */
1226 /* initialize ITR configuration */
1230 /* initialize pointer to rings */
1233 /* intialize ITR */
1235 /* rx or rx/tx vector */
1239 /* tx only vector */
1242 }
1245 /* assign generic ring traits */
1249 /* configure backlink on ring */
1252 /* update q_vector Tx values */
1255 /* For 82575, context index must be unique per ring. */
1259 /* apply Tx specific ring traits */
1266 /* assign ring to adapter */
1269 /* push pointer to next ring */
1270 ring++;
1271 }
1274 /* assign generic ring traits */
1278 /* configure backlink on ring */
1281 /* update q_vector Rx values */
1284 /* set flag indicating ring supports SCTP checksum offload */
1288 /* On i350, i354, i210, and i211, loopback VLAN packets
1289 * have the tag byte-swapped.
1290 */
1294 /* apply Rx specific ring traits */
1300 /* assign ring to adapter */
1302 }
1305 }
1308 /**
1309 * igb_alloc_q_vectors - Allocate memory for interrupt vectors
1310 * @adapter: board private structure to initialize
1311 *
1312 * We allocate one q_vector per queue interrupt. If allocation fails we
1313 * return -ENOMEM.
1314 **/
1316 {
1331 /* update counts and index */
1332 rxr_remaining--;
1333 rxr_idx++;
1334 }
1335 }
1347 /* update counts and index */
1350 rxr_idx++;
1351 txr_idx++;
1352 }
1356 err_out:
1365 }
1367 /**
1368 * igb_init_interrupt_scheme - initialize interrupts, allocate queues/vectors
1369 * @adapter: board private structure to initialize
1370 * @msix: boolean value of MSIX capability
1371 *
1372 * This function initializes the interrupts and allocates all of the queues.
1373 **/
1375 {
1385 }
1391 err_alloc_q_vectors:
1394 }
1396 /**
1397 * igb_request_irq - initialize interrupts
1398 * @adapter: board private structure to initialize
1399 *
1400 * Attempts to configure interrupts using the best available
1401 * capabilities of the hardware and kernel.
1402 **/
1404 {
1413 /* fall back to MSI */
1425 }
1435 /* fall back to legacy interrupts */
1438 }
1445 err);
1447 request_done:
1449 }
1452 {
1463 }
1464 }
1466 /**
1467 * igb_irq_disable - Mask off interrupt generation on the NIC
1468 * @adapter: board private structure
1469 **/
1471 {
1474 /* we need to be careful when disabling interrupts. The VFs are also
1475 * mapped into these registers and so clearing the bits can cause
1476 * issues on the VF drivers so we only need to clear what we set
1477 */
1485 }
1497 }
1498 }
1500 /**
1501 * igb_irq_enable - Enable default interrupt generation settings
1502 * @adapter: board private structure
1503 **/
1505 {
1519 }
1523 E1000_IMS_DRSTA);
1525 E1000_IMS_DRSTA);
1526 }
1527 }
1530 {
1536 /* add VID to filter table */
1541 }
1546 /* remove VID from filter table */
1548 }
1549 }
1551 /**
1552 * igb_release_hw_control - release control of the h/w to f/w
1553 * @adapter: address of board private structure
1554 *
1555 * igb_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
1556 * For ASF and Pass Through versions of f/w this means that the
1557 * driver is no longer loaded.
1558 **/
1560 {
1562 u32 ctrl_ext;
1564 /* Let firmware take over control of h/w */
1568 }
1570 /**
1571 * igb_get_hw_control - get control of the h/w from f/w
1572 * @adapter: address of board private structure
1573 *
1574 * igb_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
1575 * For ASF and Pass Through versions of f/w this means that
1576 * the driver is loaded.
1577 **/
1579 {
1581 u32 ctrl_ext;
1583 /* Let firmware know the driver has taken over */
1587 }
1589 /**
1590 * igb_configure - configure the hardware for RX and TX
1591 * @adapter: private board structure
1592 **/
1594 {
1612 /* call igb_desc_unused which always leaves
1613 * at least 1 descriptor unused to make sure
1614 * next_to_use != next_to_clean
1615 */
1619 }
1620 }
1622 /**
1623 * igb_power_up_link - Power up the phy/serdes link
1624 * @adapter: address of board private structure
1625 **/
1627 {
1632 else
1636 }
1638 /**
1639 * igb_power_down_link - Power down the phy/serdes link
1640 * @adapter: address of board private structure
1641 */
1643 {
1646 else
1648 }
1650 /**
1651 * Detect and switch function for Media Auto Sense
1652 * @adapter: address of the board private structure
1653 **/
1655 {
1663 /* need to live swap if current media is copper and we have fiber/serdes
1664 * to go to.
1665 */
1671 /* copper signal takes time to appear */
1684 }
1685 }
1686 }
1695 ctrl_ext |=
1696 E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1704 ctrl_ext &=
1709 /* shouldn't get here during regular operation */
1713 }
1715 }
1717 /**
1718 * igb_up - Open the interface and prepare it to handle traffic
1719 * @adapter: board private structure
1720 **/
1722 {
1726 /* hardware has been reset, we need to reload some things */
1736 else
1739 /* Clear any pending interrupts. */
1743 /* notify VFs that reset has been completed */
1749 }
1753 /* start the watchdog. */
1762 }
1765 {
1771 /* signal that we're down so the interrupt handler does not
1772 * reschedule our watchdog timer
1773 */
1776 /* disable receives in the hardware */
1779 /* flush and sleep below */
1783 /* disable transmits in the hardware */
1787 /* flush both disables and wait for them to finish */
1799 }
1800 }
1808 /* record the stats before reset*/
1820 #ifdef CONFIG_IGB_DCA
1822 /* since we reset the hardware DCA settings were cleared */
1824 #endif
1825 }
1828 {
1835 }
1837 /** igb_enable_mas - Media Autosense re-enable after swap
1838 *
1839 * @adapter: adapter struct
1840 **/
1842 {
1844 u32 connsw;
1851 /* configure for SerDes media detect */
1858 /* already SerDes, no need to enable anything */
1864 }
1866 }
1869 {
1876 /* Repartition Pba for greater than 9k mtu
1877 * To take effect CTRL.RST is required.
1878 */
1896 }
1900 /* adjust PBA for jumbo frames */
1903 /* To maintain wire speed transmits, the Tx FIFO should be
1904 * large enough to accommodate two full transmit packets,
1905 * rounded up to the next 1KB and expressed in KB. Likewise,
1906 * the Rx FIFO should be large enough to accommodate at least
1907 * one full receive packet and is similarly rounded up and
1908 * expressed in KB.
1909 */
1911 /* upper 16 bits has Tx packet buffer allocation size in KB */
1913 /* lower 16 bits has Rx packet buffer allocation size in KB */
1915 /* the Tx fifo also stores 16 bytes of information about the Tx
1916 * but don't include ethernet FCS because hardware appends it
1917 */
1923 /* software strips receive CRC, so leave room for it */
1928 /* If current Tx allocation is less than the min Tx FIFO size,
1929 * and the min Tx FIFO size is less than the current Rx FIFO
1930 * allocation, take space away from current Rx allocation
1931 */
1936 /* if short on Rx space, Rx wins and must trump Tx
1937 * adjustment
1938 */
1941 }
1943 }
1945 /* flow control settings */
1946 /* The high water mark must be low enough to fit one full frame
1947 * (or the size used for early receive) above it in the Rx FIFO.
1948 * Set it to the lower of:
1949 * - 90% of the Rx FIFO size, or
1950 * - the full Rx FIFO size minus one full frame
1951 */
1961 /* disable receive for all VFs and wait one second */
1968 /* ping all the active vfs to let them know we are going down */
1971 /* disable transmits and receives */
1974 }
1976 /* Allow time for pending master requests to run */
1981 /* need to resetup here after media swap */
1984 }
1989 }
1993 /* Flow control settings reset on hardware reset, so guarantee flow
1994 * control is off when forcing speed.
1995 */
2000 #ifdef CONFIG_IGB_HWMON
2001 /* Re-initialize the thermal sensor on i350 devices. */
2004 /* If present, re-initialize the external thermal sensor
2005 * interface.
2006 */
2009 }
2010 }
2011 #endif
2012 /* Re-establish EEE setting */
2025 }
2026 }
2032 /* Enable h/w to recognize an 802.1Q VLAN Ethernet packet */
2035 /* Re-enable PTP, where applicable. */
2039 }
2042 netdev_features_t features)
2043 {
2044 /* Since there is no support for separate Rx/Tx vlan accel
2045 * enable/disable make sure Tx flag is always in same state as Rx.
2046 */
2049 else
2053 }
2056 netdev_features_t features)
2057 {
2071 else
2075 }
2095 #ifdef CONFIG_NET_POLL_CONTROLLER
2097 #endif
2100 };
2102 /**
2103 * igb_set_fw_version - Configure version string for ethtool
2104 * @adapter: adapter struct
2105 **/
2107 {
2123 }
2124 /* fall through */
2126 /* if option is rom valid, display its version too */
2133 /* no option rom */
2144 }
2146 }
2147 }
2149 /**
2150 * igb_init_mas - init Media Autosense feature if enabled in the NVM
2151 *
2152 * @adapter: adapter struct
2153 **/
2155 {
2157 u16 eeprom_data;
2167 }
2175 }
2183 }
2191 }
2194 /* Shouldn't get here */
2198 }
2199 }
2201 /**
2202 * igb_init_i2c - Init I2C interface
2203 * @adapter: pointer to adapter structure
2204 **/
2206 {
2209 /* I2C interface supported on i350 devices */
2213 /* Initialize the i2c bus which is controlled by the registers.
2214 * This bus will use the i2c_algo_bit structue that implements
2215 * the protocol through toggling of the 4 bits in the register.
2216 */
2226 }
2228 /**
2229 * igb_probe - Device Initialization Routine
2230 * @pdev: PCI device information struct
2231 * @ent: entry in igb_pci_tbl
2232 *
2233 * Returns 0 on success, negative on failure
2234 *
2235 * igb_probe initializes an adapter identified by a pci_dev structure.
2236 * The OS initialization, configuring of the adapter private structure,
2237 * and a hardware reset occur.
2238 **/
2240 {
2245 s32 ret_val;
2251 /* Catch broken hardware that put the wrong VF device ID in
2252 * the PCIe SR-IOV capability.
2253 */
2258 }
2274 }
2275 }
2278 IORESOURCE_MEM),
2279 igb_driver_name);
2290 IGB_MAX_TX_QUEUES);
2318 /* PCI config space info */
2325 /* Copy the default MAC, PHY and NVM function pointers */
2329 /* Initialize skew-specific constants */
2334 /* setup the private structure */
2343 /* Copper options */
2348 }
2354 /* features is initialized to 0 in allocation, it might have bits
2355 * set by igb_sw_init so we should use an or instead of an
2356 * assignment.
2357 */
2359 NETIF_F_IP_CSUM |
2360 NETIF_F_IPV6_CSUM |
2361 NETIF_F_TSO |
2362 NETIF_F_TSO6 |
2363 NETIF_F_RXHASH |
2364 NETIF_F_RXCSUM |
2365 NETIF_F_HW_VLAN_CTAG_RX |
2366 NETIF_F_HW_VLAN_CTAG_TX;
2368 /* copy netdev features into list of user selectable features */
2372 /* set this bit last since it cannot be part of hw_features */
2376 NETIF_F_TSO6 |
2377 NETIF_F_IP_CSUM |
2378 NETIF_F_IPV6_CSUM |
2379 NETIF_F_SG;
2386 }
2391 }
2397 /* before reading the NVM, reset the controller to put the device in a
2398 * known good starting state
2399 */
2402 /* make sure the NVM is good , i211/i210 parts can have special NVM
2403 * that doesn't contain a checksum
2404 */
2414 }
2415 }
2422 }
2424 }
2426 /* copy the MAC address out of the NVM */
2436 }
2438 /* get firmware version for ethtool -i */
2441 /* configure RXPBSIZE and TXPBSIZE */
2445 }
2455 /* Initialize link properties that are user-changeable */
2465 /* By default, support wake on port A */
2469 /* Check the NVM for wake support on non-port A ports */
2480 /* now that we have the eeprom settings, apply the special cases where
2481 * the eeprom may be wrong or the board simply won't support wake on
2482 * lan on a particular port
2483 */
2491 /* Wake events only supported on port A for dual fiber
2492 * regardless of eeprom setting
2493 */
2499 /* if quad port adapter, disable WoL on all but port A */
2502 else
2504 /* Reset for multiple quad port adapters */
2509 /* If the device can't wake, don't set software support */
2512 }
2514 /* initialize the wol settings based on the eeprom settings */
2518 /* Some vendors want WoL disabled by default, but still supported */
2523 }
2528 /* reset the hardware with the new settings */
2531 /* Init the I2C interface */
2536 }
2538 /* let the f/w know that the h/w is now under the control of the
2539 * driver.
2540 */
2548 /* carrier off reporting is important to ethtool even BEFORE open */
2551 #ifdef CONFIG_IGB_DCA
2556 }
2558 #endif
2559 #ifdef CONFIG_IGB_HWMON
2560 /* Initialize the thermal sensor on i350 devices. */
2562 u16 ets_word;
2564 /* Read the NVM to determine if this i350 device supports an
2565 * external thermal sensor.
2566 */
2570 else
2577 }
2578 #endif
2579 /* Check if Media Autosense is enabled */
2584 /* do hw tstamp init after resetting */
2588 /* print bus type/speed/width info, not applicable to i354 */
2601 }
2606 E1000_PBANUM_LENGTH);
2609 }
2624 /* Enable EEE for internal copper PHY devices */
2631 }
2635 E1000_CTRL_EXT_LINK_MODE_SGMII)) {
2642 }
2643 }
2647 }
2648 }
2652 err_register:
2655 err_eeprom:
2661 err_sw_init:
2664 err_ioremap:
2666 err_alloc_etherdev:
2669 err_pci_reg:
2670 err_dma:
2673 }
2675 #ifdef CONFIG_PCI_IOV
2677 {
2682 /* reclaim resources allocated to VFs */
2684 /* disable iov and allow time for transactions to clear */
2687 "Cannot deallocate SR-IOV virtual functions while they are assigned - VFs will not be deallocated\n");
2692 }
2702 /* Re-enable DMA Coalescing flag since IOV is turned off */
2704 }
2707 }
2710 {
2720 }
2734 /* if allocation failed then we do not support SR-IOV */
2741 }
2743 /* only call pci_enable_sriov() if no VFs are allocated already */
2748 }
2754 /* DMA Coalescing is not supported in IOV mode. */
2758 err_out:
2762 out:
2764 }
2766 #endif
2767 /**
2768 * igb_remove_i2c - Cleanup I2C interface
2769 * @adapter: pointer to adapter structure
2770 **/
2772 {
2773 /* free the adapter bus structure */
2775 }
2777 /**
2778 * igb_remove - Device Removal Routine
2779 * @pdev: PCI device information struct
2780 *
2781 * igb_remove is called by the PCI subsystem to alert the driver
2782 * that it should release a PCI device. The could be caused by a
2783 * Hot-Plug event, or because the driver is going to be removed from
2784 * memory.
2785 **/
2787 {
2793 #ifdef CONFIG_IGB_HWMON
2795 #endif
2798 /* The watchdog timer may be rescheduled, so explicitly
2799 * disable watchdog from being rescheduled.
2800 */
2808 #ifdef CONFIG_IGB_DCA
2814 }
2815 #endif
2817 /* Release control of h/w to f/w. If f/w is AMT enabled, this
2818 * would have already happened in close and is redundant.
2819 */
2826 #ifdef CONFIG_PCI_IOV
2828 #endif
2842 }
2844 /**
2845 * igb_probe_vfs - Initialize vf data storage and add VFs to pci config space
2846 * @adapter: board private structure to initialize
2847 *
2848 * This function initializes the vf specific data storage and then attempts to
2849 * allocate the VFs. The reason for ordering it this way is because it is much
2850 * mor expensive time wise to disable SR-IOV than it is to allocate and free
2851 * the memory for the VFs.
2852 **/
2854 {
2855 #ifdef CONFIG_PCI_IOV
2859 /* Virtualization features not supported on i210 family. */
2867 }
2870 {
2872 u32 max_rss_queues;
2874 /* Determine the maximum number of RSS queues supported. */
2884 /* I350 cannot do RSS and SR-IOV at the same time */
2888 }
2889 /* fall through */
2894 }
2895 /* fall through */
2901 }
2905 /* Determine if we need to pair queues. */
2909 /* Device supports enough interrupts without queue pairing. */
2912 /* If VFs are going to be allocated with RSS queues then we
2913 * should pair the queues in order to conserve interrupts due
2914 * to limited supply.
2915 */
2919 /* fall through */
2925 /* If rss_queues > half of max_rss_queues, pair the queues in
2926 * order to conserve interrupts due to limited supply.
2927 */
2931 }
2932 }
2934 /**
2935 * igb_sw_init - Initialize general software structures (struct igb_adapter)
2936 * @adapter: board private structure to initialize
2937 *
2938 * igb_sw_init initializes the Adapter private data structure.
2939 * Fields are initialized based on PCI device information and
2940 * OS network device settings (MTU size).
2941 **/
2943 {
2950 /* set default ring sizes */
2954 /* set default ITR values */
2958 /* set default work limits */
2962 VLAN_HLEN;
2966 #ifdef CONFIG_PCI_IOV
2978 "Enabling SR-IOV VFs using the module parameter is deprecated - please use the pci sysfs interface.\n");
2982 }
2987 /* Setup and initialize a copy of the hw vlan table array */
2989 GFP_ATOMIC);
2991 /* This call may decrease the number of queues */
2995 }
2999 /* Explicitly disable IRQ since the NIC can be in any state. */
3007 }
3009 /**
3010 * igb_open - Called when a network interface is made active
3011 * @netdev: network interface device structure
3012 *
3013 * Returns 0 on success, negative value on failure
3014 *
3015 * The open entry point is called when a network interface is made
3016 * active by the system (IFF_UP). At this point all resources needed
3017 * for transmit and receive operations are allocated, the interrupt
3018 * handler is registered with the OS, the watchdog timer is started,
3019 * and the stack is notified that the interface is ready.
3020 **/
3022 {
3029 /* disallow open during test */
3033 }
3040 /* allocate transmit descriptors */
3045 /* allocate receive descriptors */
3052 /* before we allocate an interrupt, we must be ready to handle it.
3053 * Setting DEBUG_SHIRQ in the kernel makes it fire an interrupt
3054 * as soon as we call pci_request_irq, so we have to setup our
3055 * clean_rx handler before we do so.
3056 */
3063 /* Notify the stack of the actual queue counts. */
3074 /* From here on the code is the same as igb_up() */
3080 /* Clear any pending interrupts. */
3085 /* notify VFs that reset has been completed */
3091 }
3098 /* start the watchdog. */
3104 err_set_queues:
3106 err_req_irq:
3110 err_setup_rx:
3112 err_setup_tx:
3118 }
3121 {
3123 }
3125 /**
3126 * igb_close - Disables a network interface
3127 * @netdev: network interface device structure
3128 *
3129 * Returns 0, this is not allowed to fail
3130 *
3131 * The close entry point is called when an interface is de-activated
3132 * by the OS. The hardware is still under the driver's control, but
3133 * needs to be disabled. A global MAC reset is issued to stop the
3134 * hardware, and all transmit and receive resources are freed.
3135 **/
3137 {
3155 }
3158 {
3160 }
3162 /**
3163 * igb_setup_tx_resources - allocate Tx resources (Descriptors)
3164 * @tx_ring: tx descriptor ring (for a specific queue) to setup
3165 *
3166 * Return 0 on success, negative on failure
3167 **/
3169 {
3179 /* round up to nearest 4K */
3193 err:
3198 }
3200 /**
3201 * igb_setup_all_tx_resources - wrapper to allocate Tx resources
3202 * (Descriptors) for all queues
3203 * @adapter: board private structure
3204 *
3205 * Return 0 on success, negative on failure
3206 **/
3208 {
3220 }
3221 }
3224 }
3226 /**
3227 * igb_setup_tctl - configure the transmit control registers
3228 * @adapter: Board private structure
3229 **/
3231 {
3233 u32 tctl;
3235 /* disable queue 0 which is enabled by default on 82575 and 82576 */
3238 /* Program the Transmit Control Register */
3246 /* Enable transmits */
3250 }
3252 /**
3253 * igb_configure_tx_ring - Configure transmit ring after Reset
3254 * @adapter: board private structure
3255 * @ring: tx ring to configure
3256 *
3257 * Configure a transmit ring after a reset.
3258 **/
3261 {
3267 /* disable the queue */
3288 }
3290 /**
3291 * igb_configure_tx - Configure transmit Unit after Reset
3292 * @adapter: board private structure
3293 *
3294 * Configure the Tx unit of the MAC after a reset.
3295 **/
3297 {
3302 }
3304 /**
3305 * igb_setup_rx_resources - allocate Rx resources (Descriptors)
3306 * @rx_ring: Rx descriptor ring (for a specific queue) to setup
3307 *
3308 * Returns 0 on success, negative on failure
3309 **/
3311 {
3321 /* Round up to nearest 4K */
3336 err:
3341 }
3343 /**
3344 * igb_setup_all_rx_resources - wrapper to allocate Rx resources
3345 * (Descriptors) for all queues
3346 * @adapter: board private structure
3347 *
3348 * Return 0 on success, negative on failure
3349 **/
3351 {
3363 }
3364 }
3367 }
3369 /**
3370 * igb_setup_mrqc - configure the multiple receive queue control registers
3371 * @adapter: Board private structure
3372 **/
3374 {
3388 /* 82576 supports 2 RSS queues for SR-IOV */
3394 }
3401 }
3404 /* Disable raw packet checksumming so that RSS hash is placed in
3405 * descriptor on writeback. No need to enable TCP/UDP/IP checksum
3406 * offloads as they are enabled by default
3407 */
3412 /* Enable Receive Checksum Offload for SCTP */
3415 /* Don't need to set TUOFL or IPOFL, they default to 1 */
3418 /* Generate RSS hash based on packet types, TCP/UDP
3419 * port numbers and/or IPv4/v6 src and dst addresses
3420 */
3422 E1000_MRQC_RSS_FIELD_IPV4_TCP |
3423 E1000_MRQC_RSS_FIELD_IPV6 |
3424 E1000_MRQC_RSS_FIELD_IPV6_TCP |
3425 E1000_MRQC_RSS_FIELD_IPV6_TCP_EX;
3432 /* If VMDq is enabled then we set the appropriate mode for that, else
3433 * we default to RSS so that an RSS hash is calculated per packet even
3434 * if we are only using one queue
3435 */
3438 /* Set the default pool for the PF's first queue */
3442 E1000_VT_CTL_DISABLE_DEF_POOL);
3444 E1000_VT_CTL_DEFAULT_POOL_SHIFT;
3446 }
3449 else
3454 }
3458 }
3460 /**
3461 * igb_setup_rctl - configure the receive control registers
3462 * @adapter: Board private structure
3463 **/
3465 {
3467 u32 rctl;
3477 /* enable stripping of CRC. It's unlikely this will break BMC
3478 * redirection as it did with e1000. Newer features require
3479 * that the HW strips the CRC.
3480 */
3483 /* disable store bad packets and clear size bits. */
3486 /* enable LPE to prevent packets larger than max_frame_size */
3489 /* disable queue 0 to prevent tail write w/o re-config */
3492 /* Attention!!! For SR-IOV PF driver operations you must enable
3493 * queue drop for all VF and PF queues to prevent head of line blocking
3494 * if an un-trusted VF does not provide descriptors to hardware.
3495 */
3497 /* set all queue drop enable bits */
3499 }
3501 /* This is useful for sniffing bad packets. */
3503 /* UPE and MPE will be handled by normal PROMISC logic
3504 * in e1000e_set_rx_mode
3505 */
3513 /* Do not mess with E1000_CTRL_VME, it affects transmit as well,
3514 * and that breaks VLANs.
3515 */
3516 }
3519 }
3523 {
3525 u32 vmolr;
3527 /* if it isn't the PF check to see if VFs are enabled and
3528 * increase the size to support vlan tags
3529 */
3540 }
3542 /**
3543 * igb_rlpml_set - set maximum receive packet size
3544 * @adapter: board private structure
3545 *
3546 * Configure maximum receivable packet size.
3547 **/
3549 {
3556 /* If we're in VMDQ or SR-IOV mode, then set global RLPML
3557 * to our max jumbo frame size, in case we need to enable
3558 * jumbo frames on one of the rings later.
3559 * This will not pass over-length frames into the default
3560 * queue because it's gated by the VMOLR.RLPML.
3561 */
3563 }
3566 }
3570 {
3572 u32 vmolr;
3574 /* This register exists only on 82576 and newer so if we are older then
3575 * we should exit and do nothing
3576 */
3583 u32 dvmolr;
3588 }
3591 else
3594 /* clear all bits that might not be set */
3599 /* for VMDq only allow the VFs and pool 0 to accept broadcast and
3600 * multicast packets
3601 */
3606 }
3608 /**
3609 * igb_configure_rx_ring - Configure a receive ring after Reset
3610 * @adapter: board private structure
3611 * @ring: receive ring to be configured
3612 *
3613 * Configure the Rx unit of the MAC after a reset.
3614 **/
3617 {
3623 /* disable the queue */
3626 /* Set DMA base address registers */
3633 /* initialize head and tail */
3638 /* set descriptor configuration */
3644 /* Only set Drop Enable if we are supporting multiple queues */
3650 /* set filtering for VMDQ pools */
3657 /* enable receive descriptor fetching */
3660 }
3662 /**
3663 * igb_configure_rx - Configure receive Unit after Reset
3664 * @adapter: board private structure
3665 *
3666 * Configure the Rx unit of the MAC after a reset.
3667 **/
3669 {
3672 /* set UTA to appropriate mode */
3675 /* set the correct pool for the PF default MAC address in entry 0 */
3679 /* Setup the HW Rx Head and Tail Descriptor Pointers and
3680 * the Base and Length of the Rx Descriptor Ring
3681 */
3684 }
3686 /**
3687 * igb_free_tx_resources - Free Tx Resources per Queue
3688 * @tx_ring: Tx descriptor ring for a specific queue
3689 *
3690 * Free all transmit software resources
3691 **/
3693 {
3699 /* if not set, then don't free */
3707 }
3709 /**
3710 * igb_free_all_tx_resources - Free Tx Resources for All Queues
3711 * @adapter: board private structure
3712 *
3713 * Free all transmit software resources
3714 **/
3716 {
3722 }
3726 {
3733 DMA_TO_DEVICE);
3738 DMA_TO_DEVICE);
3739 }
3743 /* buffer_info must be completely set up in the transmit path */
3744 }
3746 /**
3747 * igb_clean_tx_ring - Free Tx Buffers
3748 * @tx_ring: ring to be cleaned
3749 **/
3751 {
3754 u16 i;
3758 /* Free all the Tx ring sk_buffs */
3763 }
3770 /* Zero out the descriptor ring */
3775 }
3777 /**
3778 * igb_clean_all_tx_rings - Free Tx Buffers for all queues
3779 * @adapter: board private structure
3780 **/
3782 {
3788 }
3790 /**
3791 * igb_free_rx_resources - Free Rx Resources
3792 * @rx_ring: ring to clean the resources from
3793 *
3794 * Free all receive software resources
3795 **/
3797 {
3803 /* if not set, then don't free */
3811 }
3813 /**
3814 * igb_free_all_rx_resources - Free Rx Resources for All Queues
3815 * @adapter: board private structure
3816 *
3817 * Free all receive software resources
3818 **/
3820 {
3826 }
3828 /**
3829 * igb_clean_rx_ring - Free Rx Buffers per Queue
3830 * @rx_ring: ring to free buffers from
3831 **/
3833 {
3835 u16 i;
3844 /* Free all the Rx ring sk_buffs */
3853 PAGE_SIZE,
3854 DMA_FROM_DEVICE);
3858 }
3863 /* Zero out the descriptor ring */
3869 }
3871 /**
3872 * igb_clean_all_rx_rings - Free Rx Buffers for all queues
3873 * @adapter: board private structure
3874 **/
3876 {
3882 }
3884 /**
3885 * igb_set_mac - Change the Ethernet Address of the NIC
3886 * @netdev: network interface device structure
3887 * @p: pointer to an address structure
3888 *
3889 * Returns 0 on success, negative on failure
3890 **/
3892 {
3903 /* set the correct pool for the new PF MAC address in entry 0 */
3908 }
3910 /**
3911 * igb_write_mc_addr_list - write multicast addresses to MTA
3912 * @netdev: network interface device structure
3913 *
3914 * Writes multicast address list to the MTA hash table.
3915 * Returns: -ENOMEM on failure
3916 * 0 on no addresses written
3917 * X on writing X addresses to MTA
3918 **/
3920 {
3928 /* nothing to program, so clear mc list */
3932 }
3938 /* The shared function expects a packed array of only addresses. */
3947 }
3949 /**
3950 * igb_write_uc_addr_list - write unicast addresses to RAR table
3951 * @netdev: network interface device structure
3952 *
3953 * Writes unicast address list to the RAR table.
3954 * Returns: -ENOMEM on failure/insufficient address space
3955 * 0 on no addresses written
3956 * X on writing X addresses to the RAR table
3957 **/
3959 {
3966 /* return ENOMEM indicating insufficient memory for addresses */
3977 rar_entries--,
3978 vfn);
3979 count++;
3980 }
3981 }
3982 /* write the addresses in reverse order to avoid write combining */
3986 }
3990 }
3992 /**
3993 * igb_set_rx_mode - Secondary Unicast, Multicast and Promiscuous mode set
3994 * @netdev: network interface device structure
3995 *
3996 * The set_rx_mode entry point is called whenever the unicast or multicast
3997 * address lists or the network interface flags are updated. This routine is
3998 * responsible for configuring the hardware for proper unicast, multicast,
3999 * promiscuous mode, and all-multi behavior.
4000 **/
4002 {
4009 /* Check for Promiscuous and All Multicast modes */
4012 /* clear the effected bits */
4016 /* retain VLAN HW filtering if in VT mode */
4026 /* Write addresses to the MTA, if the attempt fails
4027 * then we should just turn on promiscuous mode so
4028 * that we can at least receive multicast traffic
4029 */
4036 }
4037 }
4038 /* Write addresses to available RAR registers, if there is not
4039 * sufficient space to store all the addresses then enable
4040 * unicast promiscuous mode
4041 */
4046 }
4048 }
4051 /* In order to support SR-IOV and eventually VMDq it is necessary to set
4052 * the VMOLR to enable the appropriate modes. Without this workaround
4053 * we will have issues with VLAN tag stripping not being done for frames
4054 * that are only arriving because we are the default pool
4055 */
4063 }
4066 {
4079 }
4082 }
4084 #define IGB_STAGGERED_QUEUE_OFFSET 8
4087 {
4101 }
4102 }
4103 }
4105 /* Need to wait a few seconds after link up to get diagnostic information from
4106 * the phy
4107 */
4109 {
4112 }
4114 /**
4115 * igb_has_link - check shared code for link and determine up/down
4116 * @adapter: pointer to driver private info
4117 **/
4119 {
4123 /* get_link_status is set on LSC (link status) interrupt or
4124 * rx sequence error interrupt. get_link_status will stay
4125 * false until the e1000_check_for_link establishes link
4126 * for copper adapters ONLY
4127 */
4139 }
4149 }
4150 }
4153 }
4156 {
4160 /* check for thermal sensor event on i350 copper only */
4168 }
4171 }
4173 /**
4174 * igb_check_lvmmc - check for malformed packets received
4175 * and indicated in LVMMC register
4176 * @adapter: pointer to adapter
4177 **/
4179 {
4181 u32 lvmmc;
4188 lvmmc);
4189 }
4190 }
4191 }
4193 /**
4194 * igb_watchdog - Timer Call-back
4195 * @data: pointer to adapter cast into an unsigned long
4196 **/
4198 {
4200 /* Do the rest outside of interrupt context */
4202 }
4205 {
4208 watchdog_task);
4212 u32 link;
4214 u32 connsw;
4221 else
4223 }
4225 /* Force link down if we have fiber to swap to */
4231 }
4232 }
4234 /* Perform a reset if the media type changed. */
4239 }
4240 /* Cancel scheduled suspend requests. */
4244 u32 ctrl;
4251 /* Links status message must follow this format */
4263 /* disable EEE if enabled */
4270 }
4272 /* check if SmartSpeed worked */
4277 /* check for thermal sensor event */
4279 E1000_THSTAT_LINK_THROTTLE))
4282 /* adjust timeout factor according to speed/duplex */
4289 /* maybe add some timeout factor ? */
4291 }
4298 /* link state has changed, schedule phy info update */
4302 }
4308 /* check for thermal sensor event */
4310 E1000_THSTAT_PWR_DOWN)) {
4312 }
4314 /* Links status message must follow this format */
4321 /* link state has changed, schedule phy info update */
4326 /* link is down, time to check for alternate media */
4331 /* return immediately */
4333 }
4334 }
4338 /* also check for alternate media here */
4344 /* return immediately */
4346 }
4347 }
4348 }
4357 /* We've lost link, so the controller stops DMA,
4358 * but we've got queued Tx work that's never going
4359 * to get done, so reset controller to flush Tx.
4360 * (Do the reset outside of interrupt context).
4361 */
4365 /* return immediately since reset is imminent */
4367 }
4368 }
4370 /* Force detection of hung controller every watchdog period */
4372 }
4374 /* Cause software interrupt to ensure Rx ring is cleaned */
4383 }
4388 /* Check LVMMC register on i350/i354 only */
4393 /* Reset the timer */
4398 else
4401 }
4402 }
4409 };
4411 /**
4412 * igb_update_ring_itr - update the dynamic ITR value based on packet size
4413 * @q_vector: pointer to q_vector
4414 *
4415 * Stores a new ITR value based on strictly on packet size. This
4416 * algorithm is less sophisticated than that used in igb_update_itr,
4417 * due to the difficulty of synchronizing statistics across multiple
4418 * receive rings. The divisors and thresholds used by this function
4419 * were determined based on theoretical maximum wire speed and testing
4420 * data, in order to minimize response time while increasing bulk
4421 * throughput.
4422 * This functionality is controlled by ethtool's coalescing settings.
4423 * NOTE: This function is called only when operating in a multiqueue
4424 * receive environment.
4425 **/
4427 {
4433 /* For non-gigabit speeds, just fix the interrupt rate at 4000
4434 * ints/sec - ITR timer value of 120 ticks.
4435 */
4439 }
4450 /* if avg_wire_size isn't set no work was done */
4454 /* Add 24 bytes to size to account for CRC, preamble, and gap */
4457 /* Don't starve jumbo frames */
4460 /* Give a little boost to mid-size frames */
4463 else
4466 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4472 set_itr_val:
4476 }
4477 clear_counts:
4482 }
4484 /**
4485 * igb_update_itr - update the dynamic ITR value based on statistics
4486 * @q_vector: pointer to q_vector
4487 * @ring_container: ring info to update the itr for
4488 *
4489 * Stores a new ITR value based on packets and byte
4490 * counts during the last interrupt. The advantage of per interrupt
4491 * computation is faster updates and more accurate ITR for the current
4492 * traffic pattern. Constants in this function were computed
4493 * based on theoretical maximum wire speed and thresholds were set based
4494 * on testing data as well as attempting to minimize response time
4495 * while increasing bulk throughput.
4496 * This functionality is controlled by ethtool's coalescing settings.
4497 * NOTE: These calculations are only valid when operating in a single-
4498 * queue environment.
4499 **/
4502 {
4507 /* no packets, exit with status unchanged */
4513 /* handle TSO and jumbo frames */
4521 /* this if handles the TSO accounting */
4532 }
4540 }
4542 }
4544 /* clear work counters since we have the values we need */
4548 /* write updated itr to ring container */
4550 }
4553 {
4558 /* for non-gigabit speeds, just fix the interrupt rate at 4000 */
4563 }
4570 /* conservative mode (itr 3) eliminates the lowest_latency setting */
4577 /* counts and packets in update_itr are dependent on these numbers */
4589 }
4591 set_itr_now:
4593 /* this attempts to bias the interrupt rate towards Bulk
4594 * by adding intermediate steps when interrupt rate is
4595 * increasing
4596 */
4601 /* Don't write the value here; it resets the adapter's
4602 * internal timer, and causes us to delay far longer than
4603 * we should between interrupts. Instead, we write the ITR
4604 * value at the beginning of the next interrupt so the timing
4605 * ends up being correct.
4606 */
4609 }
4610 }
4614 {
4620 i++;
4623 /* set bits to identify this as an advanced context descriptor */
4626 /* For 82575, context index must be unique per ring. */
4634 }
4639 {
4655 /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
4664 IPPROTO_TCP,
4668 IGB_TX_FLAGS_CSUM |
4669 IGB_TX_FLAGS_IPV4;
4676 IGB_TX_FLAGS_CSUM;
4677 }
4679 /* compute header lengths */
4683 /* update gso size and bytecount with header size */
4687 /* MSS L4LEN IDX */
4691 /* VLAN MACLEN IPLEN */
4699 }
4702 {
4729 }
4731 }
4737 E1000_ADVTXD_L4LEN_SHIFT;
4742 E1000_ADVTXD_L4LEN_SHIFT;
4746 E1000_ADVTXD_L4LEN_SHIFT;
4752 l4_hdr);
4753 }
4755 }
4757 /* update TX checksum flag */
4759 }
4765 }
4767 #define IGB_SET_FLAG(_input, _flag, _result) \
4768 ((_flag <= _result) ? \
4769 ((u32)(_input & _flag) * (_result / _flag)) : \
4770 ((u32)(_input & _flag) / (_flag / _result)))
4773 {
4774 /* set type for advanced descriptor with frame checksum insertion */
4776 E1000_ADVTXD_DCMD_DEXT |
4777 E1000_ADVTXD_DCMD_IFCS;
4779 /* set HW vlan bit if vlan is present */
4783 /* set segmentation bits for TSO */
4787 /* set timestamp bit if present */
4791 /* insert frame checksum */
4795 }
4800 {
4803 /* 82575 requires a unique index per ring */
4807 /* insert L4 checksum */
4809 IGB_TX_FLAGS_CSUM,
4812 /* insert IPv4 checksum */
4814 IGB_TX_FLAGS_IPV4,
4818 }
4821 {
4826 /* Herbert's original patch had:
4827 * smp_mb__after_netif_stop_queue();
4828 * but since that doesn't exist yet, just open code it.
4829 */
4832 /* We need to check again in a case another CPU has just
4833 * made room available.
4834 */
4838 /* A reprieve! */
4846 }
4849 {
4853 }
4858 {
4863 dma_addr_t dma;
4884 /* record length, and DMA address */
4894 i++;
4895 tx_desc++;
4899 }
4906 }
4913 i++;
4914 tx_desc++;
4918 }
4928 }
4930 /* write last descriptor with RS and EOP bits */
4936 /* set the timestamp */
4939 /* Force memory writes to complete before letting h/w know there
4940 * are new descriptors to fetch. (Only applicable for weak-ordered
4941 * memory model archs, such as IA-64).
4942 *
4943 * We also need this memory barrier to make certain all of the
4944 * status bits have been updated before next_to_watch is written.
4945 */
4948 /* set next_to_watch value indicating a packet is present */
4951 i++;
4957 /* Make sure there is space in the ring for the next send. */
4963 /* we need this if more than one processor can write to our tail
4964 * at a time, it synchronizes IO on IA64/Altix systems
4965 */
4967 }
4970 dma_error:
4973 /* clear dma mappings for failed tx_buffer_info map */
4981 i--;
4982 }
4985 }
4989 {
4997 /* need: 1 descriptor per page * PAGE_SIZE/IGB_MAX_DATA_PER_TXD,
4998 * + 1 desc for skb_headlen/IGB_MAX_DATA_PER_TXD,
4999 * + 2 desc gap to keep tail from touching head,
5000 * + 1 desc for context descriptor,
5001 * otherwise try next time
5002 */
5010 }
5013 /* this is a hard error */
5015 }
5017 /* record the location of the first descriptor for this packet */
5035 }
5036 }
5043 }
5045 /* record initial flags and protocol */
5059 out_drop:
5063 }
5067 {
5074 }
5078 {
5084 }
5089 }
5091 /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
5092 * in order to meet this minimum size requirement.
5093 */
5099 }
5102 }
5104 /**
5105 * igb_tx_timeout - Respond to a Tx Hang
5106 * @netdev: network interface device structure
5107 **/
5109 {
5113 /* Do the reset outside of interrupt context */
5122 }
5125 {
5132 }
5134 /**
5135 * igb_get_stats64 - Get System Network Statistics
5136 * @netdev: network interface device structure
5137 * @stats: rtnl_link_stats64 pointer
5138 **/
5141 {
5150 }
5152 /**
5153 * igb_change_mtu - Change the Maximum Transfer Unit
5154 * @netdev: network interface device structure
5155 * @new_mtu: new value for maximum frame size
5156 *
5157 * Returns 0 on success, negative on failure
5158 **/
5160 {
5168 }
5170 #define MAX_STD_JUMBO_FRAME_SIZE 9238
5174 }
5176 /* adjust max frame to be at least the size of a standard frame */
5183 /* igb_down has a dependency on max_frame_size */
5195 else
5201 }
5203 /**
5204 * igb_update_stats - Update the board statistics counters
5205 * @adapter: board private structure
5206 **/
5209 {
5218 /* Prevent stats update while adapter is being reset, or if the pci
5219 * connection is down.
5220 */
5239 }
5248 }
5264 }
5269 /* read stats registers */
5326 /* read internal phy specific stats */
5331 /* this stat has invalid values on i210/i211 */
5335 }
5350 /* Fill out the OS statistics structure */
5354 /* Rx Errors */
5356 /* RLEC on some newer hardware can be incorrect so build
5357 * our own version based on RUC and ROC
5358 */
5369 /* Tx Errors */
5376 /* Tx Dropped needs to be maintained elsewhere */
5378 /* Management Stats */
5383 /* OS2BMC Stats */
5390 }
5391 }
5394 {
5398 /* reading ICR causes bit 31 of EICR to be cleared */
5404 /* HW is reporting DMA is out of sync */
5406 /* The DMA Out of Sync is also indication of a spoof event
5407 * in IOV mode. Check the Wrong VM Behavior register to
5408 * see if it is really a spoof event.
5409 */
5411 }
5413 /* Check for a mailbox event */
5419 /* guard against interrupt when we're going down */
5422 }
5428 /* acknowledge the interrupt */
5430 /* retrieve hardware timestamp */
5432 }
5433 }
5438 }
5441 {
5453 else
5458 }
5461 {
5464 /* Write the ITR value calculated from the previous interrupt. */
5470 }
5472 #ifdef CONFIG_IGB_DCA
5476 {
5483 /* We can enable relaxed ordering for reads, but not writes when
5484 * DCA is enabled. This is due to a known issue in some chipsets
5485 * which will cause the DCA tag to be cleared.
5486 */
5488 E1000_DCA_TXCTRL_DATA_RRO_EN |
5489 E1000_DCA_TXCTRL_DESC_DCA_EN;
5492 }
5497 {
5504 /* We can enable relaxed ordering for reads, but not writes when
5505 * DCA is enabled. This is due to a known issue in some chipsets
5506 * which will cause the DCA tag to be cleared.
5507 */
5509 E1000_DCA_RXCTRL_DESC_DCA_EN;
5512 }
5515 {
5529 out_no_update:
5531 }
5534 {
5541 /* Always use CB2 mode, difference is masked in the CB driver. */
5547 }
5548 }
5551 {
5560 /* if already enabled, don't do it again */
5568 }
5569 /* Fall Through since DCA is disabled. */
5572 /* without this a class_device is left
5573 * hanging around in the sysfs model
5574 */
5579 }
5581 }
5584 }
5588 {
5592 __igb_notify_dca);
5595 }
5598 #ifdef CONFIG_PCI_IOV
5600 {
5606 /* By default spoof check is enabled for all VFs */
5610 }
5612 #endif
5614 {
5616 u32 ping;
5624 }
5625 }
5628 {
5634 IGB_VF_FLAG_MULTI_PROMISC);
5642 /* if we have hashes and we are clearing a multicast promisc
5643 * flag we need to write the hashes to the MTA as this step
5644 * was previously skipped
5645 */
5654 }
5655 }
5659 /* there are flags left unprocessed, likely not supported */
5664 }
5668 {
5674 /* salt away the number of multicast addresses assigned
5675 * to this VF for later use to restore when the PF multi cast
5676 * list changes
5677 */
5680 /* only up to 30 hash values supported */
5684 /* store the hashes for later use */
5688 /* Flush and reset the mta with the new values */
5692 }
5695 {
5714 }
5716 }
5717 }
5720 {
5727 /* Find the vlan filter for this id */
5731 /* remove the vf from the pool */
5734 /* if pool is empty then remove entry from vfta */
5740 }
5743 }
5746 }
5749 {
5753 /* The vlvf table only exists on 82576 hardware and newer */
5757 /* we only need to do this if VMDq is enabled */
5761 /* Find the vlan filter for this id */
5767 }
5771 /* Did not find a matching VLAN ID entry that was
5772 * enabled. Search for a free filter entry, i.e.
5773 * one without the enable bit set
5774 */
5779 }
5780 }
5782 /* Found an enabled/available entry */
5785 /* if !enabled we need to set this up in vfta */
5787 /* add VID to filter table */
5790 }
5795 /* do not modify RLPML for PF devices */
5800 u32 size;
5808 }
5811 }
5814 /* remove vf from the pool */
5816 /* if pool is empty then remove entry from vfta */
5820 }
5823 /* do not modify RLPML for PF devices */
5829 u32 size;
5837 }
5838 }
5839 }
5841 }
5844 {
5849 else
5851 }
5855 {
5876 }
5884 }
5885 out:
5887 }
5890 {
5893 u32 reg;
5895 /* Find the vlan filter for this id */
5901 }
5907 }
5910 {
5916 /* If in promiscuous mode we need to make sure the PF also has
5917 * the VLAN filter set.
5918 */
5930 /* Go through all the checks to see if the VLAN filter should
5931 * be wiped completely.
5932 */
5939 /* See if any other pools are set for this VLAN filter
5940 * entry other than the PF.
5941 */
5945 /* If the filter was removed then ensure PF pool bit
5946 * is cleared if the PF only added itself to the pool
5947 * because the PF is in promiscuous mode.
5948 */
5954 }
5956 out:
5958 }
5961 {
5962 /* clear flags - except flag that indicates PF has set the MAC */
5966 /* reset offloads to defaults */
5969 /* reset vlans for device */
5975 else
5978 /* reset multicast table array for vf */
5981 /* Flush and reset the mta with the new values */
5983 }
5986 {
5989 /* clear mac address as we were hotplug removed/added */
5993 /* process remaining reset events */
5995 }
5998 {
6005 /* process all the same items cleared in a function level reset */
6008 /* set vf mac address */
6011 /* enable transmit and receive for vf */
6019 /* reply to reset with ack and vf mac address */
6023 }
6026 {
6027 /* The VF MAC Address is stored in a packed array of bytes
6028 * starting at the second 32 bit word of the msg array
6029 */
6037 }
6040 {
6045 /* if device isn't clear to send it shouldn't be reading either */
6050 }
6051 }
6054 {
6059 s32 retval;
6064 /* if receive failed revoke VF CTS stats and restart init */
6070 }
6072 /* this is a message we already processed, do nothing */
6076 /* until the vf completes a reset it should not be
6077 * allowed to start any configuration.
6078 */
6082 }
6089 }
6096 else
6098 "VF %d attempted to override administratively set MAC address\nReload the VF driver to resume operations\n",
6099 vf);
6114 "VF %d attempted to override administratively set VLAN tag\nReload the VF driver to resume operations\n",
6115 vf);
6116 else
6123 }
6126 out:
6127 /* notify the VF of the results of what it sent us */
6130 else
6134 }
6137 {
6139 u32 vf;
6142 /* process any reset requests */
6146 /* process any messages pending */
6150 /* process any acks */
6153 }
6154 }
6156 /**
6157 * igb_set_uta - Set unicast filter table address
6158 * @adapter: board private structure
6159 *
6160 * The unicast table address is a register array of 32-bit registers.
6161 * The table is meant to be used in a way similar to how the MTA is used
6162 * however due to certain limitations in the hardware it is necessary to
6163 * set all the hash bits to 1 and use the VMOLR ROPE bit as a promiscuous
6164 * enable bit to allow vlan tag stripping when promiscuous mode is enabled
6165 **/
6167 {
6171 /* The UTA table only exists on 82576 hardware and newer */
6175 /* we only need to do this if VMDq is enabled */
6181 }
6183 /**
6184 * igb_intr_msi - Interrupt Handler
6185 * @irq: interrupt number
6186 * @data: pointer to a network interface device structure
6187 **/
6189 {
6193 /* read ICR disables interrupts using IAM */
6202 /* HW is reporting DMA is out of sync */
6204 }
6210 }
6216 /* acknowledge the interrupt */
6218 /* retrieve hardware timestamp */
6220 }
6221 }
6226 }
6228 /**
6229 * igb_intr - Legacy Interrupt Handler
6230 * @irq: interrupt number
6231 * @data: pointer to a network interface device structure
6232 **/
6234 {
6238 /* Interrupt Auto-Mask...upon reading ICR, interrupts are masked. No
6239 * need for the IMC write
6240 */
6243 /* IMS will not auto-mask if INT_ASSERTED is not set, and if it is
6244 * not set, then the adapter didn't send an interrupt
6245 */
6255 /* HW is reporting DMA is out of sync */
6257 }
6261 /* guard against interrupt when we're going down */
6264 }
6270 /* acknowledge the interrupt */
6272 /* retrieve hardware timestamp */
6274 }
6275 }
6280 }
6283 {
6291 else
6293 }
6298 else
6300 }
6301 }
6303 /**
6304 * igb_poll - NAPI Rx polling callback
6305 * @napi: napi polling structure
6306 * @budget: count of how many packets we should handle
6307 **/
6309 {
6312 napi);
6315 #ifdef CONFIG_IGB_DCA
6318 #endif
6325 /* If all work not completed, return budget and keep polling */
6329 /* If not enough Rx work done, exit the polling mode */
6334 }
6336 /**
6337 * igb_clean_tx_irq - Reclaim resources after transmit completes
6338 * @q_vector: pointer to q_vector containing needed info
6339 *
6340 * returns true if ring is completely cleaned
6341 **/
6343 {
6362 /* if next_to_watch is not set then there is no work pending */
6366 /* prevent any other reads prior to eop_desc */
6369 /* if DD is not set pending work has not been completed */
6373 /* clear next_to_watch to prevent false hangs */
6376 /* update the statistics for this packet */
6380 /* free the skb */
6383 /* unmap skb header data */
6387 DMA_TO_DEVICE);
6389 /* clear tx_buffer data */
6393 /* clear last DMA location and unmap remaining buffers */
6395 tx_buffer++;
6396 tx_desc++;
6397 i++;
6402 }
6404 /* unmap any remaining paged data */
6409 DMA_TO_DEVICE);
6411 }
6412 }
6414 /* move us one more past the eop_desc for start of next pkt */
6415 tx_buffer++;
6416 tx_desc++;
6417 i++;
6422 }
6424 /* issue prefetch for next Tx descriptor */
6427 /* update budget accounting */
6428 budget--;
6445 /* Detect a transmit hang in hardware, this serializes the
6446 * check with the clearing of time_stamp and movement of i
6447 */
6454 /* detected Tx unit hang */
6474 jiffies,
6479 /* we are about to reset, no point in enabling stuff */
6481 }
6482 }
6484 #define TX_WAKE_THRESHOLD (DESC_NEEDED * 2)
6488 /* Make sure that anybody stopping the queue after this
6489 * sees the new next_to_clean.
6490 */
6501 }
6502 }
6505 }
6507 /**
6508 * igb_reuse_rx_page - page flip buffer and store it back on the ring
6509 * @rx_ring: rx descriptor ring to store buffers on
6510 * @old_buff: donor buffer to have page reused
6511 *
6512 * Synchronizes page for reuse by the adapter
6513 **/
6516 {
6522 /* update, and store next to alloc */
6523 nta++;
6526 /* transfer page from old buffer to new buffer */
6529 /* sync the buffer for use by the device */
6532 IGB_RX_BUFSZ,
6533 DMA_FROM_DEVICE);
6534 }
6539 {
6540 /* avoid re-using remote pages */
6547 #if (PAGE_SIZE < 8192)
6548 /* if we are only owner of page we can reuse it */
6552 /* flip page offset to other buffer */
6555 /* Even if we own the page, we are not allowed to use atomic_set()
6556 * This would break get_page_unless_zero() users.
6557 */
6559 #else
6560 /* move offset up to the next cache line */
6566 /* bump ref count on page before it is given to the stack */
6568 #endif
6571 }
6573 /**
6574 * igb_add_rx_frag - Add contents of Rx buffer to sk_buff
6575 * @rx_ring: rx descriptor ring to transact packets on
6576 * @rx_buffer: buffer containing page to add
6577 * @rx_desc: descriptor containing length of buffer written by hardware
6578 * @skb: sk_buff to place the data into
6579 *
6580 * This function will add the data contained in rx_buffer->page to the skb.
6581 * This is done either through a direct copy if the data in the buffer is
6582 * less than the skb header size, otherwise it will just attach the page as
6583 * a frag to the skb.
6584 *
6585 * The function will then update the page offset if necessary and return
6586 * true if the buffer can be reused by the adapter.
6587 **/
6592 {
6595 #if (PAGE_SIZE < 8192)
6597 #else
6599 #endif
6608 }
6612 /* we can reuse buffer as-is, just make sure it is local */
6617 /* this page cannot be reused so discard it */
6620 }
6626 }
6631 {
6644 /* prefetch first cache line of first page */
6646 #if L1_CACHE_BYTES < 128
6648 #endif
6650 /* allocate a skb to store the frags */
6652 IGB_RX_HDR_LEN);
6656 }
6658 /* we will be copying header into skb->data in
6659 * pskb_may_pull so it is in our interest to prefetch
6660 * it now to avoid a possible cache miss
6661 */
6663 }
6665 /* we are reusing so sync this buffer for CPU use */
6669 IGB_RX_BUFSZ,
6670 DMA_FROM_DEVICE);
6672 /* pull page into skb */
6674 /* hand second half of page back to the ring */
6677 /* we are not reusing the buffer so unmap it */
6680 }
6682 /* clear contents of rx_buffer */
6686 }
6691 {
6694 /* Ignore Checksum bit is set */
6698 /* Rx checksum disabled via ethtool */
6702 /* TCP/UDP checksum error bit is set */
6704 E1000_RXDEXT_STATERR_TCPE |
6705 E1000_RXDEXT_STATERR_IPE)) {
6706 /* work around errata with sctp packets where the TCPE aka
6707 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
6708 * packets, (aka let the stack check the crc32c)
6709 */
6715 }
6716 /* let the stack verify checksum errors */
6718 }
6719 /* It must be a TCP or UDP packet with a valid checksum */
6721 E1000_RXD_STAT_UDPCS))
6726 }
6731 {
6735 PKT_HASH_TYPE_L3);
6736 }
6738 /**
6739 * igb_is_non_eop - process handling of non-EOP buffers
6740 * @rx_ring: Rx ring being processed
6741 * @rx_desc: Rx descriptor for current buffer
6742 * @skb: current socket buffer containing buffer in progress
6743 *
6744 * This function updates next to clean. If the buffer is an EOP buffer
6745 * this function exits returning false, otherwise it will place the
6746 * sk_buff in the next buffer to be chained and return true indicating
6747 * that this is in fact a non-EOP buffer.
6748 **/
6751 {
6754 /* fetch, update, and store next to clean */
6764 }
6766 /**
6767 * igb_pull_tail - igb specific version of skb_pull_tail
6768 * @rx_ring: rx descriptor ring packet is being transacted on
6769 * @rx_desc: pointer to the EOP Rx descriptor
6770 * @skb: pointer to current skb being adjusted
6771 *
6772 * This function is an igb specific version of __pskb_pull_tail. The
6773 * main difference between this version and the original function is that
6774 * this function can make several assumptions about the state of things
6775 * that allow for significant optimizations versus the standard function.
6776 * As a result we can do things like drop a frag and maintain an accurate
6777 * truesize for the skb.
6778 */
6782 {
6787 /* it is valid to use page_address instead of kmap since we are
6788 * working with pages allocated out of the lomem pool per
6789 * alloc_page(GFP_ATOMIC)
6790 */
6794 /* retrieve timestamp from buffer */
6797 /* update pointers to remove timestamp header */
6803 /* move va to start of packet data */
6805 }
6807 /* we need the header to contain the greater of either ETH_HLEN or
6808 * 60 bytes if the skb->len is less than 60 for skb_pad.
6809 */
6812 /* align pull length to size of long to optimize memcpy performance */
6815 /* update all of the pointers */
6820 }
6822 /**
6823 * igb_cleanup_headers - Correct corrupted or empty headers
6824 * @rx_ring: rx descriptor ring packet is being transacted on
6825 * @rx_desc: pointer to the EOP Rx descriptor
6826 * @skb: pointer to current skb being fixed
6827 *
6828 * Address the case where we are pulling data in on pages only
6829 * and as such no data is present in the skb header.
6830 *
6831 * In addition if skb is not at least 60 bytes we need to pad it so that
6832 * it is large enough to qualify as a valid Ethernet frame.
6833 *
6834 * Returns true if an error was encountered and skb was freed.
6835 **/
6839 {
6841 E1000_RXDEXT_ERR_FRAME_ERR_MASK)))) {
6846 }
6847 }
6849 /* place header in linear portion of buffer */
6853 /* if skb_pad returns an error the skb was freed */
6860 }
6863 }
6865 /**
6866 * igb_process_skb_fields - Populate skb header fields from Rx descriptor
6867 * @rx_ring: rx descriptor ring packet is being transacted on
6868 * @rx_desc: pointer to the EOP Rx descriptor
6869 * @skb: pointer to current skb being populated
6870 *
6871 * This function checks the ring, descriptor, and packet information in
6872 * order to populate the hash, checksum, VLAN, timestamp, protocol, and
6873 * other fields within the skb.
6874 **/
6878 {
6891 u16 vid;
6896 else
6900 }
6905 }
6908 {
6917 /* return some buffers to hardware, one at a time is too slow */
6921 }
6928 /* This memory barrier is needed to keep us from reading
6929 * any other fields out of the rx_desc until we know the
6930 * RXD_STAT_DD bit is set
6931 */
6934 /* retrieve a buffer from the ring */
6937 /* exit if we failed to retrieve a buffer */
6941 cleaned_count++;
6943 /* fetch next buffer in frame if non-eop */
6947 /* verify the packet layout is correct */
6951 }
6953 /* probably a little skewed due to removing CRC */
6956 /* populate checksum, timestamp, VLAN, and protocol */
6961 /* reset skb pointer */
6964 /* update budget accounting */
6965 total_packets++;
6966 }
6968 /* place incomplete frames back on ring for completion */
6982 }
6986 {
6988 dma_addr_t dma;
6990 /* since we are recycling buffers we should seldom need to alloc */
6994 /* alloc new page for storage */
6999 }
7001 /* map page for use */
7004 /* if mapping failed free memory back to system since
7005 * there isn't much point in holding memory we can't use
7006 */
7012 }
7019 }
7021 /**
7022 * igb_alloc_rx_buffers - Replace used receive buffers; packet split
7023 * @adapter: address of board private structure
7024 **/
7026 {
7031 /* nothing to do */
7043 /* Refresh the desc even if buffer_addrs didn't change
7044 * because each write-back erases this info.
7045 */
7048 rx_desc++;
7049 bi++;
7050 i++;
7055 }
7057 /* clear the hdr_addr for the next_to_use descriptor */
7060 cleaned_count--;
7066 /* record the next descriptor to use */
7069 /* update next to alloc since we have filled the ring */
7072 /* Force memory writes to complete before letting h/w
7073 * know there are new descriptors to fetch. (Only
7074 * applicable for weak-ordered memory model archs,
7075 * such as IA-64).
7076 */
7079 }
7080 }
7082 /**
7083 * igb_mii_ioctl -
7084 * @netdev:
7085 * @ifreq:
7086 * @cmd:
7087 **/
7089 {
7108 }
7110 }
7112 /**
7113 * igb_ioctl -
7114 * @netdev:
7115 * @ifreq:
7116 * @cmd:
7117 **/
7119 {
7131 }
7132 }
7135 {
7139 }
7142 {
7146 }
7149 {
7156 }
7159 {
7166 }
7169 {
7176 /* enable VLAN tag insert/strip */
7181 /* Disable CFI check */
7186 /* disable VLAN tag insert/strip */
7190 }
7193 }
7197 {
7202 /* attempt to add filter to vlvf array */
7205 /* add the filter since PF can receive vlans w/o entry in vlvf */
7211 }
7215 {
7219 s32 err;
7221 /* remove vlan from VLVF table array */
7224 /* if vid was not present in VLVF just remove it from table */
7231 }
7234 {
7235 u16 vid;
7241 }
7244 {
7250 /* Make sure dplx is at most 1 bit and lsb of speed is not set
7251 * for the switch() below to work
7252 */
7256 /* Fiber NIC's only allow 1000 gbps Full duplex
7257 * and 100Mbps Full duplex for 100baseFx sfp
7258 */
7267 }
7268 }
7290 }
7292 /* clear MDI, MDI(-X) override is only allowed when autoneg enabled */
7297 err_inval:
7300 }
7304 {
7310 #ifdef CONFIG_PM
7312 #endif
7321 #ifdef CONFIG_PM
7325 #endif
7335 /* turn on all-multi mode if wake on multicast is enabled */
7340 }
7343 /* advertise wake from D3Cold */
7344 #define E1000_CTRL_ADVD3WUC 0x00100000
7345 /* phy power management enable */
7346 #define E1000_CTRL_EN_PHY_PWR_MGMT 0x00200000
7350 /* Allow time for pending master requests to run */
7358 }
7363 else
7366 /* Release control of h/w to f/w. If f/w is AMT enabled, this
7367 * would have already happened in close and is redundant.
7368 */
7374 }
7376 #ifdef CONFIG_PM
7377 #ifdef CONFIG_PM_SLEEP
7379 {
7393 }
7396 }
7400 {
7405 u32 err;
7418 }
7427 }
7431 /* let the f/w know that the h/w is now under the control of the
7432 * driver.
7433 */
7444 }
7448 }
7450 #ifdef CONFIG_PM_RUNTIME
7452 {
7461 }
7464 {
7478 }
7481 }
7484 {
7486 }
7488 #endif
7491 {
7499 }
7500 }
7502 #ifdef CONFIG_PCI_IOV
7504 {
7513 else
7523 }
7531 }
7534 {
7541 }
7544 {
7554 out:
7556 }
7558 #endif
7560 {
7561 #ifdef CONFIG_PCI_IOV
7564 else
7566 #endif
7568 }
7570 #ifdef CONFIG_NET_POLL_CONTROLLER
7571 /* Polling 'interrupt' - used by things like netconsole to send skbs
7572 * without having to re-enable interrupts. It's not called while
7573 * the interrupt routine is executing.
7574 */
7576 {
7586 else
7589 }
7590 }
7593 /**
7594 * igb_io_error_detected - called when PCI error is detected
7595 * @pdev: Pointer to PCI device
7596 * @state: The current pci connection state
7597 *
7598 * This function is called after a PCI bus error affecting
7599 * this device has been detected.
7600 **/
7602 pci_channel_state_t state)
7603 {
7616 /* Request a slot slot reset. */
7618 }
7620 /**
7621 * igb_io_slot_reset - called after the pci bus has been reset.
7622 * @pdev: Pointer to PCI device
7623 *
7624 * Restart the card from scratch, as if from a cold-boot. Implementation
7625 * resembles the first-half of the igb_resume routine.
7626 **/
7628 {
7632 pci_ers_result_t result;
7650 }
7656 err);
7657 /* non-fatal, continue */
7658 }
7661 }
7663 /**
7664 * igb_io_resume - called when traffic can start flowing again.
7665 * @pdev: Pointer to PCI device
7666 *
7667 * This callback is called when the error recovery driver tells us that
7668 * its OK to resume normal operation. Implementation resembles the
7669 * second-half of the igb_resume routine.
7670 */
7672 {
7680 }
7681 }
7685 /* let the f/w know that the h/w is now under the control of the
7686 * driver.
7687 */
7689 }
7692 u8 qsel)
7693 {
7697 /* HW expects these in little endian so we reverse the byte order
7698 * from network order (big endian) to little endian
7699 */
7704 /* Indicate to hardware the Address is Valid. */
7709 else
7716 }
7720 {
7722 /* VF MAC addresses start at end of receive addresses and moves
7723 * towards the first, as a result a collision should not be possible
7724 */
7732 }
7735 {
7748 }
7750 }
7753 {
7761 }
7762 }
7766 {
7768 u32 bcnrc_val;
7771 /* Calculate the rate factor values to set */
7775 tx_rate;
7779 E1000_RTTBCNRC_RF_INT_MASK);
7783 }
7786 /* Set global transmit compensation time to the MMW_SIZE in RTTBCNRM
7787 * register. MMW_SIZE=0x014 if 9728-byte jumbo is supported.
7788 */
7791 }
7794 {
7798 /* VF TX rate limit was not set or not supported */
7809 }
7817 actual_link_speed);
7818 }
7819 }
7823 {
7846 }
7850 {
7866 else
7873 }
7877 {
7889 }
7892 {
7894 u32 reg;
7902 /* replication is not supported for 82575 */
7905 /* notify HW that the MAC is adding vlan tags */
7909 /* Fall through */
7911 /* enable replication vlan tag stripping */
7915 /* Fall through */
7917 /* none of the above registers are supported by i350 */
7919 }
7929 }
7930 }
7933 {
7935 u32 dmac_thr;
7936 u16 hwm;
7940 u32 reg;
7942 /* force threshold to 0. */
7945 /* DMA Coalescing high water mark needs to be greater
7946 * than the Rx threshold. Set hwm to PBA - max frame
7947 * size in 16B units, capping it at PBA - 6KB.
7948 */
7958 /* Set the DMA Coalescing Rx threshold to PBA - 2 * max
7959 * frame size, capping it at PBA - 10KB.
7960 */
7969 /* transition to L0x or L1 if available..*/
7972 /* watchdog timer= +-1000 usec in 32usec intervals */
7975 /* Disable BMC-to-OS Watchdog Enable */
7981 /* no lower threshold to disable
7982 * coalescing(smart fifb)-UTRESH=0
7983 */
7990 /* free space in tx packet buffer to wake from
7991 * DMA coal
7992 */
7996 /* make low power state decision controlled
7997 * by DMA coal
7998 */
8008 }
8009 }
8011 /**
8012 * igb_read_i2c_byte - Reads 8 bit word over I2C
8013 * @hw: pointer to hardware structure
8014 * @byte_offset: byte offset to read
8015 * @dev_addr: device address
8016 * @data: value read
8017 *
8018 * Performs byte read operation over I2C interface at
8019 * a specified device address.
8020 **/
8023 {
8026 s32 status;
8045 }
8046 }
8048 /**
8049 * igb_write_i2c_byte - Writes 8 bit word over I2C
8050 * @hw: pointer to hardware structure
8051 * @byte_offset: byte offset to write
8052 * @dev_addr: device address
8053 * @data: value to write
8054 *
8055 * Performs byte write operation over I2C interface at
8056 * a specified device address.
8057 **/
8060 {
8063 s32 status;
8076 else
8079 }
8082 {
8095 }
8101 }
8102 /* igb_main.c */