| blob | 1bb49cb699ab02a5af7ef1de66ab6bbed0aa47ae |
1 /*
2 * Broadcom Starfighter 2 switch register defines
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11 #ifndef __BCM_SF2_REGS_H
12 #define __BCM_SF2_REGS_H
14 /* Register set relative to 'REG' */
15 #define REG_SWITCH_CNTRL 0x00
16 #define MDIO_MASTER_SEL (1 << 0)
18 #define REG_SWITCH_STATUS 0x04
19 #define REG_DIR_DATA_WRITE 0x08
20 #define REG_DIR_DATA_READ 0x0C
22 #define REG_SWITCH_REVISION 0x18
23 #define SF2_REV_MASK 0xffff
24 #define SWITCH_TOP_REV_SHIFT 16
25 #define SWITCH_TOP_REV_MASK 0xffff
27 #define REG_PHY_REVISION 0x1C
28 #define PHY_REVISION_MASK 0xffff
30 #define REG_SPHY_CNTRL 0x2C
31 #define IDDQ_BIAS (1 << 0)
32 #define EXT_PWR_DOWN (1 << 1)
33 #define FORCE_DLL_EN (1 << 2)
34 #define IDDQ_GLOBAL_PWR (1 << 3)
35 #define CK25_DIS (1 << 4)
36 #define PHY_RESET (1 << 5)
37 #define PHY_PHYAD_SHIFT 8
38 #define PHY_PHYAD_MASK 0x1F
40 #define REG_RGMII_0_BASE 0x34
41 #define REG_RGMII_CNTRL 0x00
42 #define REG_RGMII_IB_STATUS 0x04
43 #define REG_RGMII_RX_CLOCK_DELAY_CNTRL 0x08
44 #define REG_RGMII_CNTRL_SIZE 0x0C
45 #define REG_RGMII_CNTRL_P(x) (REG_RGMII_0_BASE + \
46 ((x) * REG_RGMII_CNTRL_SIZE))
47 /* Relative to REG_RGMII_CNTRL */
48 #define RGMII_MODE_EN (1 << 0)
49 #define ID_MODE_DIS (1 << 1)
50 #define PORT_MODE_SHIFT 2
51 #define INT_EPHY (0 << PORT_MODE_SHIFT)
52 #define INT_GPHY (1 << PORT_MODE_SHIFT)
53 #define EXT_EPHY (2 << PORT_MODE_SHIFT)
54 #define EXT_GPHY (3 << PORT_MODE_SHIFT)
55 #define EXT_REVMII (4 << PORT_MODE_SHIFT)
56 #define PORT_MODE_MASK 0x7
57 #define RVMII_REF_SEL (1 << 5)
58 #define RX_PAUSE_EN (1 << 6)
59 #define TX_PAUSE_EN (1 << 7)
60 #define TX_CLK_STOP_EN (1 << 8)
61 #define LPI_COUNT_SHIFT 9
62 #define LPI_COUNT_MASK 0x3F
64 /* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
65 #define INTRL2_CPU_STATUS 0x00
66 #define INTRL2_CPU_SET 0x04
67 #define INTRL2_CPU_CLEAR 0x08
68 #define INTRL2_CPU_MASK_STATUS 0x0c
69 #define INTRL2_CPU_MASK_SET 0x10
70 #define INTRL2_CPU_MASK_CLEAR 0x14
72 /* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
73 #define P_LINK_UP_IRQ(x) (1 << (0 + (x)))
74 #define P_LINK_DOWN_IRQ(x) (1 << (1 + (x)))
75 #define P_ENERGY_ON_IRQ(x) (1 << (2 + (x)))
76 #define P_ENERGY_OFF_IRQ(x) (1 << (3 + (x)))
77 #define P_GPHY_IRQ(x) (1 << (4 + (x)))
78 #define P_NUM_IRQ 5
79 #define P_IRQ_MASK(x) (P_LINK_UP_IRQ((x)) | \
80 P_LINK_DOWN_IRQ((x)) | \
81 P_ENERGY_ON_IRQ((x)) | \
82 P_ENERGY_OFF_IRQ((x)) | \
83 P_GPHY_IRQ((x)))
85 /* INTRL2_0 interrupt sources */
86 #define P0_IRQ_OFF 0
87 #define MEM_DOUBLE_IRQ (1 << 5)
88 #define EEE_LPI_IRQ (1 << 6)
89 #define P5_CPU_WAKE_IRQ (1 << 7)
90 #define P8_CPU_WAKE_IRQ (1 << 8)
91 #define P7_CPU_WAKE_IRQ (1 << 9)
92 #define IEEE1588_IRQ (1 << 10)
93 #define MDIO_ERR_IRQ (1 << 11)
94 #define MDIO_DONE_IRQ (1 << 12)
95 #define GISB_ERR_IRQ (1 << 13)
96 #define UBUS_ERR_IRQ (1 << 14)
97 #define FAILOVER_ON_IRQ (1 << 15)
98 #define FAILOVER_OFF_IRQ (1 << 16)
99 #define TCAM_SOFT_ERR_IRQ (1 << 17)
101 /* INTRL2_1 interrupt sources */
102 #define P7_IRQ_OFF 0
103 #define P_IRQ_OFF(x) ((6 - (x)) * P_NUM_IRQ)
105 /* Register set relative to 'CORE' */
106 #define CORE_G_PCTL_PORT0 0x00000
107 #define CORE_G_PCTL_PORT(x) (CORE_G_PCTL_PORT0 + (x * 0x4))
108 #define CORE_IMP_CTL 0x00020
109 #define RX_DIS (1 << 0)
110 #define TX_DIS (1 << 1)
111 #define RX_BCST_EN (1 << 2)
112 #define RX_MCST_EN (1 << 3)
113 #define RX_UCST_EN (1 << 4)
114 #define G_MISTP_STATE_SHIFT 5
115 #define G_MISTP_NO_STP (0 << G_MISTP_STATE_SHIFT)
116 #define G_MISTP_DIS_STATE (1 << G_MISTP_STATE_SHIFT)
117 #define G_MISTP_BLOCK_STATE (2 << G_MISTP_STATE_SHIFT)
118 #define G_MISTP_LISTEN_STATE (3 << G_MISTP_STATE_SHIFT)
119 #define G_MISTP_LEARN_STATE (4 << G_MISTP_STATE_SHIFT)
120 #define G_MISTP_FWD_STATE (5 << G_MISTP_STATE_SHIFT)
121 #define G_MISTP_STATE_MASK 0x7
123 #define CORE_SWMODE 0x0002c
124 #define SW_FWDG_MODE (1 << 0)
125 #define SW_FWDG_EN (1 << 1)
126 #define RTRY_LMT_DIS (1 << 2)
128 #define CORE_STS_OVERRIDE_IMP 0x00038
129 #define GMII_SPEED_UP_2G (1 << 6)
130 #define MII_SW_OR (1 << 7)
132 #define CORE_NEW_CTRL 0x00084
133 #define IP_MC (1 << 0)
134 #define OUTRANGEERR_DISCARD (1 << 1)
135 #define INRANGEERR_DISCARD (1 << 2)
136 #define CABLE_DIAG_LEN (1 << 3)
137 #define OVERRIDE_AUTO_PD_WAR (1 << 4)
138 #define EN_AUTO_PD_WAR (1 << 5)
139 #define UC_FWD_EN (1 << 6)
140 #define MC_FWD_EN (1 << 7)
142 #define CORE_SWITCH_CTRL 0x00088
143 #define MII_DUMB_FWDG_EN (1 << 6)
145 #define CORE_SFT_LRN_CTRL 0x000f8
146 #define SW_LEARN_CNTL(x) (1 << (x))
148 #define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
149 #define LINK_STS (1 << 0)
150 #define DUPLX_MODE (1 << 1)
151 #define SPEED_SHIFT 2
152 #define SPEED_MASK 0x3
153 #define RXFLOW_CNTL (1 << 4)
154 #define TXFLOW_CNTL (1 << 5)
155 #define SW_OVERRIDE (1 << 6)
157 #define CORE_WATCHDOG_CTRL 0x001e4
158 #define SOFTWARE_RESET (1 << 7)
159 #define EN_CHIP_RST (1 << 6)
160 #define EN_SW_RESET (1 << 4)
162 #define CORE_LNKSTS 0x00400
163 #define LNK_STS_MASK 0x1ff
165 #define CORE_SPDSTS 0x00410
166 #define SPDSTS_10 0
167 #define SPDSTS_100 1
168 #define SPDSTS_1000 2
169 #define SPDSTS_SHIFT 2
170 #define SPDSTS_MASK 0x3
172 #define CORE_DUPSTS 0x00420
173 #define CORE_DUPSTS_MASK 0x1ff
175 #define CORE_PAUSESTS 0x00428
176 #define PAUSESTS_TX_PAUSE_SHIFT 9
178 #define CORE_GMNCFGCFG 0x0800
179 #define RST_MIB_CNT (1 << 0)
180 #define RXBPDU_EN (1 << 1)
182 #define CORE_IMP0_PRT_ID 0x0804
184 #define CORE_BRCM_HDR_CTRL 0x0080c
185 #define BRCM_HDR_EN_P8 (1 << 0)
186 #define BRCM_HDR_EN_P5 (1 << 1)
187 #define BRCM_HDR_EN_P7 (1 << 2)
189 #define CORE_BRCM_HDR_CTRL2 0x0828
191 #define CORE_HL_PRTC_CTRL 0x0940
192 #define ARP_EN (1 << 0)
193 #define RARP_EN (1 << 1)
194 #define DHCP_EN (1 << 2)
195 #define ICMPV4_EN (1 << 3)
196 #define ICMPV6_EN (1 << 4)
197 #define ICMPV6_FWD_MODE (1 << 5)
198 #define IGMP_DIP_EN (1 << 8)
199 #define IGMP_RPTLVE_EN (1 << 9)
200 #define IGMP_RTPLVE_FWD_MODE (1 << 10)
201 #define IGMP_QRY_EN (1 << 11)
202 #define IGMP_QRY_FWD_MODE (1 << 12)
203 #define IGMP_UKN_EN (1 << 13)
204 #define IGMP_UKN_FWD_MODE (1 << 14)
205 #define MLD_RPTDONE_EN (1 << 15)
206 #define MLD_RPTDONE_FWD_MODE (1 << 16)
207 #define MLD_QRY_EN (1 << 17)
208 #define MLD_QRY_FWD_MODE (1 << 18)
210 #define CORE_RST_MIB_CNT_EN 0x0950
212 #define CORE_BRCM_HDR_RX_DIS 0x0980
213 #define CORE_BRCM_HDR_TX_DIS 0x0988
215 #define CORE_MEM_PSM_VDD_CTRL 0x2380
216 #define P_TXQ_PSM_VDD_SHIFT 2
217 #define P_TXQ_PSM_VDD_MASK 0x3
218 #define P_TXQ_PSM_VDD(x) (P_TXQ_PSM_VDD_MASK << \
219 ((x) * P_TXQ_PSM_VDD_SHIFT))
221 #define CORE_P0_MIB_OFFSET 0x8000
222 #define P_MIB_SIZE 0x400
223 #define CORE_P_MIB_OFFSET(x) (CORE_P0_MIB_OFFSET + (x) * P_MIB_SIZE)
225 #define CORE_PORT_VLAN_CTL_PORT(x) (0xc400 + ((x) * 0x8))
226 #define PORT_VLAN_CTRL_MASK 0x1ff
228 #define CORE_EEE_EN_CTRL 0x24800
229 #define CORE_EEE_LPI_INDICATE 0x24810